xref: /linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h (revision 2c1ed907520c50326b8f604907a8478b27881a2e)
1 // SPDX-License-Identifier: MIT
2 //
3 // Copyright 2024 Advanced Micro Devices, Inc.
4 
5 #ifndef __DML2_CORE_SHARED_TYPES_H__
6 #define __DML2_CORE_SHARED_TYPES_H__
7 
8 #include "dml2_external_lib_deps.h"
9 #include "dml_top_display_cfg_types.h"
10 #include "dml_top_types.h"
11 
12 #define __DML_VBA_DEBUG__
13 #define __DML2_CALCS_MAX_VRATIO_PRE_OTO__ 4.0 //<brief max vratio for one-to-one prefetch bw scheduling
14 #define __DML2_CALCS_MAX_VRATIO_PRE_EQU__ 6.0 //<brief max vratio for equalized prefetch bw scheduling
15 #define __DML2_CALCS_MAX_VRATIO_PRE__ 8.0 //<brief max prefetch vratio register limit
16 
17 #define __DML2_CALCS_DPP_INVALID__ 0
18 #define __DML2_CALCS_DCFCLK_FACTOR__ 1.15 //<brief fudge factor for min dcfclk calclation
19 #define __DML2_CALCS_PIPE_NO_PLANE__ 99
20 
21 struct dml2_core_ip_params {
22 	unsigned int vblank_nom_default_us;
23 	unsigned int remote_iommu_outstanding_translations;
24 	unsigned int rob_buffer_size_kbytes;
25 	unsigned int config_return_buffer_size_in_kbytes;
26 	unsigned int config_return_buffer_segment_size_in_kbytes;
27 	unsigned int compressed_buffer_segment_size_in_kbytes;
28 	unsigned int meta_fifo_size_in_kentries;
29 	unsigned int dpte_buffer_size_in_pte_reqs_luma;
30 	unsigned int dpte_buffer_size_in_pte_reqs_chroma;
31 	unsigned int pixel_chunk_size_kbytes;
32 	unsigned int alpha_pixel_chunk_size_kbytes;
33 	unsigned int min_pixel_chunk_size_bytes;
34 	unsigned int writeback_chunk_size_kbytes;
35 	unsigned int line_buffer_size_bits;
36 	unsigned int max_line_buffer_lines;
37 	unsigned int writeback_interface_buffer_size_kbytes;
38 	unsigned int max_num_dpp;
39 	unsigned int max_num_otg;
40 	unsigned int max_num_wb;
41 	unsigned int max_dchub_pscl_bw_pix_per_clk;
42 	unsigned int max_pscl_lb_bw_pix_per_clk;
43 	unsigned int max_lb_vscl_bw_pix_per_clk;
44 	unsigned int max_vscl_hscl_bw_pix_per_clk;
45 	double max_hscl_ratio;
46 	double max_vscl_ratio;
47 	unsigned int max_hscl_taps;
48 	unsigned int max_vscl_taps;
49 	unsigned int num_dsc;
50 	unsigned int maximum_dsc_bits_per_component;
51 	unsigned int maximum_pixels_per_line_per_dsc_unit;
52 	bool dsc422_native_support;
53 	bool cursor_64bpp_support;
54 	double dispclk_ramp_margin_percent;
55 	unsigned int dppclk_delay_subtotal;
56 	unsigned int dppclk_delay_scl;
57 	unsigned int dppclk_delay_scl_lb_only;
58 	unsigned int dppclk_delay_cnvc_formatter;
59 	unsigned int dppclk_delay_cnvc_cursor;
60 	unsigned int cursor_buffer_size;
61 	unsigned int cursor_chunk_size;
62 	unsigned int dispclk_delay_subtotal;
63 	bool dynamic_metadata_vm_enabled;
64 	unsigned int max_inter_dcn_tile_repeaters;
65 	unsigned int max_num_hdmi_frl_outputs;
66 	unsigned int max_num_dp2p0_outputs;
67 	unsigned int max_num_dp2p0_streams;
68 	bool dcc_supported;
69 	bool ptoi_supported;
70 	double writeback_max_hscl_ratio;
71 	double writeback_max_vscl_ratio;
72 	double writeback_min_hscl_ratio;
73 	double writeback_min_vscl_ratio;
74 	unsigned int writeback_max_hscl_taps;
75 	unsigned int writeback_max_vscl_taps;
76 	unsigned int writeback_line_buffer_buffer_size;
77 
78 	unsigned int words_per_channel;
79 	bool imall_supported;
80 	unsigned int max_flip_time_us;
81 	unsigned int max_flip_time_lines;
82 	unsigned int subvp_swath_height_margin_lines;
83 	unsigned int subvp_fw_processing_delay_us;
84 	unsigned int subvp_pstate_allow_width_us;
85 
86 	// MRQ
87 	bool dcn_mrq_present;
88 	unsigned int zero_size_buffer_entries;
89 	unsigned int compbuf_reserved_space_zs;
90 	unsigned int dcc_meta_buffer_size_bytes;
91 	unsigned int meta_chunk_size_kbytes;
92 	unsigned int min_meta_chunk_size_bytes;
93 
94 	unsigned int dchub_arb_to_ret_delay; // num of dcfclk
95 	unsigned int hostvm_mode;
96 };
97 
98 struct dml2_core_internal_DmlPipe {
99 	double Dppclk;
100 	double Dispclk;
101 	double PixelClock;
102 	double DCFClkDeepSleep;
103 	unsigned int DPPPerSurface;
104 	bool ScalerEnabled;
105 	enum dml2_rotation_angle RotationAngle;
106 	bool mirrored;
107 	unsigned int ViewportHeight;
108 	unsigned int ViewportHeightC;
109 	unsigned int BlockWidth256BytesY;
110 	unsigned int BlockHeight256BytesY;
111 	unsigned int BlockWidth256BytesC;
112 	unsigned int BlockHeight256BytesC;
113 	unsigned int BlockWidthY;
114 	unsigned int BlockHeightY;
115 	unsigned int BlockWidthC;
116 	unsigned int BlockHeightC;
117 	unsigned int InterlaceEnable;
118 	unsigned int NumberOfCursors;
119 	unsigned int VBlank;
120 	unsigned int HTotal;
121 	unsigned int HActive;
122 	bool DCCEnable;
123 	enum dml2_odm_mode ODMMode;
124 	enum dml2_source_format_class SourcePixelFormat;
125 	enum dml2_swizzle_mode SurfaceTiling;
126 	unsigned int BytePerPixelY;
127 	unsigned int BytePerPixelC;
128 	bool ProgressiveToInterlaceUnitInOPP;
129 	double VRatio;
130 	double VRatioChroma;
131 	unsigned int VTaps;
132 	unsigned int VTapsChroma;
133 	unsigned int PitchY;
134 	unsigned int PitchC;
135 	bool ViewportStationary;
136 	unsigned int ViewportXStart;
137 	unsigned int ViewportYStart;
138 	unsigned int ViewportXStartC;
139 	unsigned int ViewportYStartC;
140 	bool FORCE_ONE_ROW_FOR_FRAME;
141 	unsigned int SwathHeightY;
142 	unsigned int SwathHeightC;
143 
144 	unsigned int DCCMetaPitchY;
145 	unsigned int DCCMetaPitchC;
146 };
147 
148 enum dml2_core_internal_request_type {
149 	dml2_core_internal_request_type_256_bytes = 0,
150 	dml2_core_internal_request_type_128_bytes_non_contiguous = 1,
151 	dml2_core_internal_request_type_128_bytes_contiguous = 2,
152 	dml2_core_internal_request_type_na = 3
153 };
154 enum dml2_core_internal_bw_type {
155 	dml2_core_internal_bw_sdp = 0,
156 	dml2_core_internal_bw_dram = 1,
157 	dml2_core_internal_bw_max
158 };
159 
160 enum dml2_core_internal_soc_state_type {
161 	dml2_core_internal_soc_state_sys_active = 0,
162 	dml2_core_internal_soc_state_svp_prefetch = 1,
163 	dml2_core_internal_soc_state_sys_idle = 2,
164 	dml2_core_internal_soc_state_max
165 };
166 
167 enum dml2_core_internal_output_type {
168 	dml2_core_internal_output_type_unknown = 0,
169 	dml2_core_internal_output_type_dp = 1,
170 	dml2_core_internal_output_type_edp = 2,
171 	dml2_core_internal_output_type_dp2p0 = 3,
172 	dml2_core_internal_output_type_hdmi = 4,
173 	dml2_core_internal_output_type_hdmifrl = 5
174 };
175 
176 enum dml2_core_internal_output_type_rate {
177 	dml2_core_internal_output_rate_unknown = 0,
178 	dml2_core_internal_output_rate_dp_rate_hbr = 1,
179 	dml2_core_internal_output_rate_dp_rate_hbr2 = 2,
180 	dml2_core_internal_output_rate_dp_rate_hbr3 = 3,
181 	dml2_core_internal_output_rate_dp_rate_uhbr10 = 4,
182 	dml2_core_internal_output_rate_dp_rate_uhbr13p5 = 5,
183 	dml2_core_internal_output_rate_dp_rate_uhbr20 = 6,
184 	dml2_core_internal_output_rate_hdmi_rate_3x3 = 7,
185 	dml2_core_internal_output_rate_hdmi_rate_6x3 = 8,
186 	dml2_core_internal_output_rate_hdmi_rate_6x4 = 9,
187 	dml2_core_internal_output_rate_hdmi_rate_8x4 = 10,
188 	dml2_core_internal_output_rate_hdmi_rate_10x4 = 11,
189 	dml2_core_internal_output_rate_hdmi_rate_12x4 = 12
190 };
191 
192 struct dml2_core_internal_watermarks {
193 	double UrgentWatermark;
194 	double WritebackUrgentWatermark;
195 	double DRAMClockChangeWatermark;
196 	double FCLKChangeWatermark;
197 	double WritebackDRAMClockChangeWatermark;
198 	double WritebackFCLKChangeWatermark;
199 	double StutterExitWatermark;
200 	double StutterEnterPlusExitWatermark;
201 	double Z8StutterExitWatermark;
202 	double Z8StutterEnterPlusExitWatermark;
203 	double USRRetrainingWatermark;
204 	double temp_read_or_ppt_watermark_us;
205 };
206 
207 struct dml2_core_internal_mode_support_info {
208 	//-----------------
209 	// Mode Support Information
210 	//-----------------
211 	bool ImmediateFlipSupport; //<brief Means mode support immediate flip at the max combine setting; determine in mode support and used in mode programming
212 
213 	// Mode Support Reason/
214 	bool WritebackLatencySupport;
215 	bool ScaleRatioAndTapsSupport;
216 	bool SourceFormatPixelAndScanSupport;
217 	bool P2IWith420;
218 	bool DSCSlicesODMModeSupported;
219 	bool DSCOnlyIfNecessaryWithBPP;
220 	bool DSC422NativeNotSupported;
221 	bool LinkRateDoesNotMatchDPVersion;
222 	bool LinkRateForMultistreamNotIndicated;
223 	bool BPPForMultistreamNotIndicated;
224 	bool MultistreamWithHDMIOreDP;
225 	bool MSOOrODMSplitWithNonDPLink;
226 	bool NotEnoughLanesForMSO;
227 	bool NumberOfOTGSupport;
228 	bool NumberOfHDMIFRLSupport;
229 	bool NumberOfDP2p0Support;
230 	bool WritebackScaleRatioAndTapsSupport;
231 	bool CursorSupport;
232 	bool PitchSupport;
233 	bool ViewportExceedsSurface;
234 	//bool ImmediateFlipRequiredButTheRequirementForEachSurfaceIsNotSpecified;
235 	bool ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe;
236 	bool InvalidCombinationOfMALLUseForPStateAndStaticScreen;
237 	bool InvalidCombinationOfMALLUseForPState;
238 	bool ExceededMALLSize;
239 	bool EnoughWritebackUnits;
240 
241 	bool ExceededMultistreamSlots;
242 	bool NotEnoughDSCUnits;
243 	bool NotEnoughDSCSlices;
244 	bool PixelsPerLinePerDSCUnitSupport;
245 	bool DSCCLKRequiredMoreThanSupported;
246 	bool DTBCLKRequiredMoreThanSupported;
247 	bool LinkCapacitySupport;
248 
249 	bool ROBSupport;
250 	bool OutstandingRequestsSupport;
251 	bool OutstandingRequestsUrgencyAvoidance;
252 
253 	bool PTEBufferSizeNotExceeded;
254 	bool DCCMetaBufferSizeNotExceeded;
255 	enum dml2_pstate_change_support DRAMClockChangeSupport[DML2_MAX_PLANES];
256 	enum dml2_pstate_change_support FCLKChangeSupport[DML2_MAX_PLANES];
257 	bool global_dram_clock_change_supported;
258 	bool global_fclk_change_supported;
259 	bool USRRetrainingSupport;
260 	bool AvgBandwidthSupport;
261 	bool UrgVactiveBandwidthSupport;
262 	bool EnoughUrgentLatencyHidingSupport;
263 	bool PrefetchSupported;
264 	bool PrefetchBandwidthSupported;
265 	bool DynamicMetadataSupported;
266 	bool VRatioInPrefetchSupported;
267 	bool DISPCLK_DPPCLK_Support;
268 	bool TotalAvailablePipesSupport;
269 	bool ModeSupport;
270 	bool ViewportSizeSupport;
271 
272 	bool MPCCombineEnable[DML2_MAX_PLANES]; /// <brief Indicate if the MPC Combine enable in the given state and optimize mpc combine setting
273 	enum dml2_odm_mode ODMMode[DML2_MAX_PLANES]; /// <brief ODM mode that is chosen in the mode check stage and will be used in mode programming stage
274 	unsigned int DPPPerSurface[DML2_MAX_PLANES]; /// <brief How many DPPs are needed drive the surface to output. If MPCC or ODMC could be 2 or 4.
275 	bool DSCEnabled[DML2_MAX_PLANES]; /// <brief Indicate if the DSC is actually required; used in mode_programming
276 	bool FECEnabled[DML2_MAX_PLANES]; /// <brief Indicate if the FEC is actually required
277 	unsigned int NumberOfDSCSlices[DML2_MAX_PLANES]; /// <brief Indicate how many slices needed to support the given mode
278 
279 	double OutputBpp[DML2_MAX_PLANES];
280 	enum dml2_core_internal_output_type OutputType[DML2_MAX_PLANES];
281 	enum dml2_core_internal_output_type_rate OutputRate[DML2_MAX_PLANES];
282 
283 	unsigned int AlignedYPitch[DML2_MAX_PLANES];
284 	unsigned int AlignedCPitch[DML2_MAX_PLANES];
285 
286 	unsigned int AlignedDCCMetaPitchY[DML2_MAX_PLANES];
287 	unsigned int AlignedDCCMetaPitchC[DML2_MAX_PLANES];
288 
289 	unsigned int request_size_bytes_luma[DML2_MAX_PLANES];
290 	unsigned int request_size_bytes_chroma[DML2_MAX_PLANES];
291 	enum dml2_core_internal_request_type RequestLuma[DML2_MAX_PLANES];
292 	enum dml2_core_internal_request_type RequestChroma[DML2_MAX_PLANES];
293 
294 	unsigned int DCCYMaxUncompressedBlock[DML2_MAX_PLANES];
295 	unsigned int DCCYMaxCompressedBlock[DML2_MAX_PLANES];
296 	unsigned int DCCYIndependentBlock[DML2_MAX_PLANES];
297 	unsigned int DCCCMaxUncompressedBlock[DML2_MAX_PLANES];
298 	unsigned int DCCCMaxCompressedBlock[DML2_MAX_PLANES];
299 	unsigned int DCCCIndependentBlock[DML2_MAX_PLANES];
300 
301 	double avg_bandwidth_available_min[dml2_core_internal_soc_state_max];
302 	double avg_bandwidth_available[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max];
303 	double urg_bandwidth_available_min_latency[dml2_core_internal_soc_state_max]; // min between SDP and DRAM, for latency evaluation
304 	double urg_bandwidth_available_min[dml2_core_internal_soc_state_max]; // min between SDP and DRAM
305 	double urg_bandwidth_available[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max];
306 	double urg_bandwidth_available_vm_only[dml2_core_internal_soc_state_max]; // the min of sdp bw and dram_vm_only bw, sdp has no different derate for vm/non-vm etc.
307 	double urg_bandwidth_available_pixel_and_vm[dml2_core_internal_soc_state_max]; // the min of sdp bw and dram_pixel_and_vm bw, sdp has no different derate for vm/non-vm etc.
308 
309 	double avg_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max];
310 	double urg_vactive_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // active bandwidth, scaled by urg burst factor
311 	double urg_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // include vm, prefetch, active bandwidth, scaled by urg burst factor
312 	double urg_bandwidth_required_qual[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // include vm, prefetch, active bandwidth, scaled by urg burst factor, use qual_row_bw
313 	double urg_bandwidth_required_flip[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // include vm, prefetch, active bandwidth + flip
314 
315 	double non_urg_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // same as urg_bandwidth, except not scaled by urg burst factor
316 	double non_urg_bandwidth_required_flip[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max];
317 
318 	bool avg_bandwidth_support_ok[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max];
319 
320 	double max_urgent_latency_us;
321 	double max_non_urgent_latency_us;
322 	double avg_non_urgent_latency_us;
323 	double avg_urgent_latency_us;
324 	double df_response_time_us;
325 
326 	bool incorrect_imall_usage;
327 
328 	bool g6_temp_read_support;
329 	bool temp_read_or_ppt_support;
330 
331 	struct dml2_core_internal_watermarks watermarks;
332 };
333 
334 struct dml2_core_internal_mode_support {
335 	// Physical info; only using for programming
336 	unsigned int state_idx; // <brief min clk state table index for mode support call
337 	unsigned int qos_param_index; // to access the uclk dependent qos_parameters table
338 	unsigned int active_min_uclk_dpm_index; // to access the min_clk table
339 	unsigned int num_active_planes; // <brief As determined by either e2e_pipe_param or display_cfg
340 
341 	// Calculated Clocks
342 	double RequiredDISPCLK; /// <brief Required DISPCLK; depends on pixel rate; odm mode etc.
343 	double RequiredDPPCLK[DML2_MAX_PLANES];
344 	double RequiredDISPCLKPerSurface[DML2_MAX_PLANES];
345 	double RequiredDTBCLK[DML2_MAX_PLANES];
346 
347 	double required_dscclk_freq_mhz[DML2_MAX_PLANES];
348 
349 	double FabricClock; /// <brief Basically just the clock freq at the min (or given) state
350 	double SOCCLK; /// <brief Basically just the clock freq at the min (or given) state
351 	double DCFCLK; /// <brief Basically just the clock freq at the min (or given) state and max combine setting
352 	double GlobalDPPCLK; /// <brief the Max DPPCLK freq out of all pipes
353 	double uclk_freq_mhz;
354 	double dram_bw_mbps;
355 	double max_dram_bw_mbps;
356 
357 	double MaxFabricClock; /// <brief Basically just the clock freq at the min (or given) state
358 	double MaxDCFCLK; /// <brief Basically just the clock freq at the min (or given) state and max combine setting
359 	double max_dispclk_freq_mhz;
360 	double max_dppclk_freq_mhz;
361 	double max_dscclk_freq_mhz;
362 
363 	bool NoTimeForPrefetch[DML2_MAX_PLANES];
364 	bool NoTimeForDynamicMetadata[DML2_MAX_PLANES];
365 
366 	// ----------------------------------
367 	// Mode Support Info and fail reason
368 	// ----------------------------------
369 	struct dml2_core_internal_mode_support_info support;
370 
371 	// These are calculated before the ModeSupport and ModeProgram step
372 	// They represent the bound for the return buffer sizing
373 	unsigned int MaxTotalDETInKByte;
374 	unsigned int NomDETInKByte;
375 	unsigned int MinCompressedBufferSizeInKByte;
376 
377 	// Info obtained at the end of mode support calculations
378 	// The reported info is at the "optimal" state and combine setting
379 	unsigned int DETBufferSizeInKByte[DML2_MAX_PLANES]; // <brief Recommended DET size configuration for this plane. All pipes under this plane should program the DET buffer size to the calculated value.
380 	unsigned int DETBufferSizeY[DML2_MAX_PLANES];
381 	unsigned int DETBufferSizeC[DML2_MAX_PLANES];
382 	unsigned int SwathHeightY[DML2_MAX_PLANES];
383 	unsigned int SwathHeightC[DML2_MAX_PLANES];
384 	unsigned int SwathWidthY[DML2_MAX_PLANES]; // per-pipe
385 	unsigned int SwathWidthC[DML2_MAX_PLANES]; // per-pipe
386 
387 	// ----------------------------------
388 	// Intermediates/Informational
389 	// ----------------------------------
390 	unsigned int TotImmediateFlipBytes;
391 	bool DCCEnabledInAnySurface;
392 	double WritebackRequiredDISPCLK;
393 	double TimeCalc;
394 	double TWait[DML2_MAX_PLANES];
395 
396 	bool UnboundedRequestEnabled;
397 	unsigned int CompressedBufferSizeInkByte;
398 	double VRatioPreY[DML2_MAX_PLANES];
399 	double VRatioPreC[DML2_MAX_PLANES];
400 	unsigned int swath_width_luma_ub[DML2_MAX_PLANES];
401 	unsigned int swath_width_chroma_ub[DML2_MAX_PLANES];
402 	unsigned int RequiredSlots[DML2_MAX_PLANES];
403 	unsigned int vm_bytes[DML2_MAX_PLANES];
404 	unsigned int DPTEBytesPerRow[DML2_MAX_PLANES];
405 	unsigned int PrefetchLinesY[DML2_MAX_PLANES];
406 	unsigned int PrefetchLinesC[DML2_MAX_PLANES];
407 	unsigned int MaxNumSwathY[DML2_MAX_PLANES]; /// <brief Max number of swath for prefetch
408 	unsigned int MaxNumSwathC[DML2_MAX_PLANES]; /// <brief Max number of swath for prefetch
409 	unsigned int PrefillY[DML2_MAX_PLANES];
410 	unsigned int PrefillC[DML2_MAX_PLANES];
411 	unsigned int full_swath_bytes_l[DML2_MAX_PLANES];
412 	unsigned int full_swath_bytes_c[DML2_MAX_PLANES];
413 
414 	bool use_one_row_for_frame[DML2_MAX_PLANES];
415 	bool use_one_row_for_frame_flip[DML2_MAX_PLANES];
416 
417 	double dst_y_prefetch[DML2_MAX_PLANES];
418 	double LinesForVM[DML2_MAX_PLANES];
419 	double LinesForDPTERow[DML2_MAX_PLANES];
420 	double SwathWidthYSingleDPP[DML2_MAX_PLANES];
421 	double SwathWidthCSingleDPP[DML2_MAX_PLANES];
422 	unsigned int BytePerPixelY[DML2_MAX_PLANES];
423 	unsigned int BytePerPixelC[DML2_MAX_PLANES];
424 	double BytePerPixelInDETY[DML2_MAX_PLANES];
425 	double BytePerPixelInDETC[DML2_MAX_PLANES];
426 
427 	unsigned int Read256BlockHeightY[DML2_MAX_PLANES];
428 	unsigned int Read256BlockWidthY[DML2_MAX_PLANES];
429 	unsigned int Read256BlockHeightC[DML2_MAX_PLANES];
430 	unsigned int Read256BlockWidthC[DML2_MAX_PLANES];
431 	unsigned int MacroTileHeightY[DML2_MAX_PLANES];
432 	unsigned int MacroTileHeightC[DML2_MAX_PLANES];
433 	unsigned int MacroTileWidthY[DML2_MAX_PLANES];
434 	unsigned int MacroTileWidthC[DML2_MAX_PLANES];
435 
436 	bool surf_linear128_l[DML2_MAX_PLANES];
437 	bool surf_linear128_c[DML2_MAX_PLANES];
438 
439 	double PSCL_FACTOR[DML2_MAX_PLANES];
440 	double PSCL_FACTOR_CHROMA[DML2_MAX_PLANES];
441 	double MaximumSwathWidthLuma[DML2_MAX_PLANES];
442 	double MaximumSwathWidthChroma[DML2_MAX_PLANES];
443 	double Tno_bw[DML2_MAX_PLANES];
444 	double Tno_bw_flip[DML2_MAX_PLANES];
445 	double dst_y_per_vm_flip[DML2_MAX_PLANES];
446 	double dst_y_per_row_flip[DML2_MAX_PLANES];
447 	double WritebackDelayTime[DML2_MAX_PLANES];
448 	unsigned int dpte_group_bytes[DML2_MAX_PLANES];
449 	unsigned int dpte_row_height[DML2_MAX_PLANES];
450 	unsigned int dpte_row_height_chroma[DML2_MAX_PLANES];
451 	double UrgLatency;
452 	double TripToMemory;
453 	double UrgentBurstFactorCursor[DML2_MAX_PLANES];
454 	double UrgentBurstFactorCursorPre[DML2_MAX_PLANES];
455 	double UrgentBurstFactorLuma[DML2_MAX_PLANES];
456 	double UrgentBurstFactorLumaPre[DML2_MAX_PLANES];
457 	double UrgentBurstFactorChroma[DML2_MAX_PLANES];
458 	double UrgentBurstFactorChromaPre[DML2_MAX_PLANES];
459 	double MaximumSwathWidthInLineBufferLuma;
460 	double MaximumSwathWidthInLineBufferChroma;
461 	double ExtraLatency;
462 	double ExtraLatency_sr;
463 	double ExtraLatencyPrefetch;
464 
465 	double dcc_dram_bw_nom_overhead_factor_p0[DML2_MAX_PLANES]; // overhead to request meta
466 	double dcc_dram_bw_nom_overhead_factor_p1[DML2_MAX_PLANES];
467 	double dcc_dram_bw_pref_overhead_factor_p0[DML2_MAX_PLANES]; // overhead to request meta
468 	double dcc_dram_bw_pref_overhead_factor_p1[DML2_MAX_PLANES];
469 	double mall_prefetch_sdp_overhead_factor[DML2_MAX_PLANES]; // overhead to the imall or phantom pipe
470 	double mall_prefetch_dram_overhead_factor[DML2_MAX_PLANES];
471 
472 	// Backend
473 	bool RequiresDSC[DML2_MAX_PLANES];
474 	bool RequiresFEC[DML2_MAX_PLANES];
475 	double OutputBpp[DML2_MAX_PLANES];
476 	unsigned int DSCDelay[DML2_MAX_PLANES];
477 	enum dml2_core_internal_output_type OutputType[DML2_MAX_PLANES];
478 	enum dml2_core_internal_output_type_rate OutputRate[DML2_MAX_PLANES];
479 
480 	// Bandwidth Related Info
481 	double BandwidthAvailableForImmediateFlip;
482 	double vactive_sw_bw_l[DML2_MAX_PLANES]; // no dcc overhead, for the plane
483 	double vactive_sw_bw_c[DML2_MAX_PLANES];
484 	double WriteBandwidth[DML2_MAX_PLANES][DML2_MAX_WRITEBACK];
485 	double RequiredPrefetchPixelDataBWLuma[DML2_MAX_PLANES];
486 	double RequiredPrefetchPixelDataBWChroma[DML2_MAX_PLANES];
487 	double cursor_bw[DML2_MAX_PLANES];
488 	double prefetch_cursor_bw[DML2_MAX_PLANES];
489 	double prefetch_vmrow_bw[DML2_MAX_PLANES];
490 	double final_flip_bw[DML2_MAX_PLANES];
491 	double meta_row_bw[DML2_MAX_PLANES];
492 	unsigned int meta_row_bytes[DML2_MAX_PLANES];
493 	double dpte_row_bw[DML2_MAX_PLANES];
494 	double excess_vactive_fill_bw_l[DML2_MAX_PLANES];
495 	double excess_vactive_fill_bw_c[DML2_MAX_PLANES];
496 	double surface_avg_vactive_required_bw[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max][DML2_MAX_PLANES];
497 	double surface_peak_required_bw[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max][DML2_MAX_PLANES];
498 
499 	// Something that should be feedback to caller
500 	enum dml2_odm_mode ODMMode[DML2_MAX_PLANES];
501 	unsigned int SurfaceSizeInMALL[DML2_MAX_PLANES];
502 	unsigned int NoOfDPP[DML2_MAX_PLANES];
503 	bool MPCCombine[DML2_MAX_PLANES];
504 	double dcfclk_deepsleep;
505 	double MinDPPCLKUsingSingleDPP[DML2_MAX_PLANES];
506 	bool SingleDPPViewportSizeSupportPerSurface[DML2_MAX_PLANES];
507 	bool ImmediateFlipSupportedForPipe[DML2_MAX_PLANES];
508 	bool NotEnoughUrgentLatencyHiding[DML2_MAX_PLANES];
509 	bool NotEnoughUrgentLatencyHidingPre[DML2_MAX_PLANES];
510 	bool PTEBufferSizeNotExceeded[DML2_MAX_PLANES];
511 	bool DCCMetaBufferSizeNotExceeded[DML2_MAX_PLANES];
512 	unsigned int TotalNumberOfActiveDPP;
513 	unsigned int TotalNumberOfSingleDPPSurfaces;
514 	unsigned int TotalNumberOfDCCActiveDPP;
515 	unsigned int Total3dlutActive;
516 
517 	unsigned int SubViewportLinesNeededInMALL[DML2_MAX_PLANES];
518 	double VActiveLatencyHidingMargin[DML2_MAX_PLANES];
519 	double VActiveLatencyHidingUs[DML2_MAX_PLANES];
520 	unsigned int MaxVStartupLines[DML2_MAX_PLANES];
521 	double dram_change_vactive_det_fill_delay_us[DML2_MAX_PLANES];
522 
523 	unsigned int num_mcaches_l[DML2_MAX_PLANES];
524 	unsigned int mcache_row_bytes_l[DML2_MAX_PLANES];
525 	unsigned int mcache_offsets_l[DML2_MAX_PLANES][DML2_MAX_MCACHES + 1];
526 	unsigned int mcache_shift_granularity_l[DML2_MAX_PLANES];
527 
528 	unsigned int num_mcaches_c[DML2_MAX_PLANES];
529 	unsigned int mcache_row_bytes_c[DML2_MAX_PLANES];
530 	unsigned int mcache_offsets_c[DML2_MAX_PLANES][DML2_MAX_MCACHES + 1];
531 	unsigned int mcache_shift_granularity_c[DML2_MAX_PLANES];
532 
533 	bool mall_comb_mcache_l[DML2_MAX_PLANES];
534 	bool mall_comb_mcache_c[DML2_MAX_PLANES];
535 	bool lc_comb_mcache[DML2_MAX_PLANES];
536 
537 
538 };
539 
540 /// @brief A mega structure that houses various info for model programming step.
541 struct dml2_core_internal_mode_program {
542 	unsigned int qos_param_index; // to access the uclk dependent dpm table
543 	unsigned int active_min_uclk_dpm_index; // to access the min_clk table
544 	double FabricClock; /// <brief Basically just the clock freq at the min (or given) state
545 	//double DCFCLK; /// <brief Basically just the clock freq at the min (or given) state and max combine setting
546 	double dram_bw_mbps;
547 	double uclk_freq_mhz;
548 	unsigned int NoOfDPP[DML2_MAX_PLANES];
549 	enum dml2_odm_mode ODMMode[DML2_MAX_PLANES];
550 
551 	//-------------
552 	// Intermediate/Informational
553 	//-------------
554 	double UrgentLatency;
555 	double TripToMemory;
556 	double MetaTripToMemory;
557 	unsigned int VInitPreFillY[DML2_MAX_PLANES];
558 	unsigned int VInitPreFillC[DML2_MAX_PLANES];
559 	unsigned int MaxNumSwathY[DML2_MAX_PLANES];
560 	unsigned int MaxNumSwathC[DML2_MAX_PLANES];
561 	unsigned int full_swath_bytes_l[DML2_MAX_PLANES];
562 	unsigned int full_swath_bytes_c[DML2_MAX_PLANES];
563 
564 	double BytePerPixelInDETY[DML2_MAX_PLANES];
565 	double BytePerPixelInDETC[DML2_MAX_PLANES];
566 	unsigned int BytePerPixelY[DML2_MAX_PLANES];
567 	unsigned int BytePerPixelC[DML2_MAX_PLANES];
568 	unsigned int SwathWidthY[DML2_MAX_PLANES]; // per-pipe
569 	unsigned int SwathWidthC[DML2_MAX_PLANES]; // per-pipe
570 	unsigned int req_per_swath_ub_l[DML2_MAX_PLANES];
571 	unsigned int req_per_swath_ub_c[DML2_MAX_PLANES];
572 	unsigned int SwathWidthSingleDPPY[DML2_MAX_PLANES];
573 	unsigned int SwathWidthSingleDPPC[DML2_MAX_PLANES];
574 	double vactive_sw_bw_l[DML2_MAX_PLANES];
575 	double vactive_sw_bw_c[DML2_MAX_PLANES];
576 	double excess_vactive_fill_bw_l[DML2_MAX_PLANES];
577 	double excess_vactive_fill_bw_c[DML2_MAX_PLANES];
578 
579 	unsigned int PixelPTEBytesPerRow[DML2_MAX_PLANES];
580 	unsigned int vm_bytes[DML2_MAX_PLANES];
581 	unsigned int PrefetchSourceLinesY[DML2_MAX_PLANES];
582 	double RequiredPrefetchPixelDataBWLuma[DML2_MAX_PLANES];
583 	double RequiredPrefetchPixelDataBWChroma[DML2_MAX_PLANES];
584 	unsigned int PrefetchSourceLinesC[DML2_MAX_PLANES];
585 	double PSCL_THROUGHPUT[DML2_MAX_PLANES];
586 	double PSCL_THROUGHPUT_CHROMA[DML2_MAX_PLANES];
587 	unsigned int DSCDelay[DML2_MAX_PLANES];
588 	double DPPCLKUsingSingleDPP[DML2_MAX_PLANES];
589 
590 	unsigned int Read256BlockHeightY[DML2_MAX_PLANES];
591 	unsigned int Read256BlockWidthY[DML2_MAX_PLANES];
592 	unsigned int Read256BlockHeightC[DML2_MAX_PLANES];
593 	unsigned int Read256BlockWidthC[DML2_MAX_PLANES];
594 	unsigned int MacroTileHeightY[DML2_MAX_PLANES];
595 	unsigned int MacroTileHeightC[DML2_MAX_PLANES];
596 	unsigned int MacroTileWidthY[DML2_MAX_PLANES];
597 	unsigned int MacroTileWidthC[DML2_MAX_PLANES];
598 
599 	bool surf_linear128_l[DML2_MAX_PLANES];
600 	bool surf_linear128_c[DML2_MAX_PLANES];
601 
602 	unsigned int SurfaceSizeInTheMALL[DML2_MAX_PLANES];
603 	double VRatioPrefetchY[DML2_MAX_PLANES];
604 	double VRatioPrefetchC[DML2_MAX_PLANES];
605 	double Tno_bw[DML2_MAX_PLANES];
606 	double Tno_bw_flip[DML2_MAX_PLANES];
607 	double final_flip_bw[DML2_MAX_PLANES];
608 	double prefetch_vmrow_bw[DML2_MAX_PLANES];
609 	double cursor_bw[DML2_MAX_PLANES];
610 	double prefetch_cursor_bw[DML2_MAX_PLANES];
611 	double WritebackDelay[DML2_MAX_PLANES];
612 	unsigned int dpte_row_height[DML2_MAX_PLANES];
613 	unsigned int dpte_row_height_linear[DML2_MAX_PLANES];
614 	unsigned int dpte_row_width_luma_ub[DML2_MAX_PLANES];
615 	unsigned int dpte_row_width_chroma_ub[DML2_MAX_PLANES];
616 	unsigned int dpte_row_height_chroma[DML2_MAX_PLANES];
617 	unsigned int dpte_row_height_linear_chroma[DML2_MAX_PLANES];
618 	unsigned int vm_group_bytes[DML2_MAX_PLANES];
619 	unsigned int dpte_group_bytes[DML2_MAX_PLANES];
620 
621 	double dpte_row_bw[DML2_MAX_PLANES];
622 	double time_per_tdlut_group[DML2_MAX_PLANES];
623 	double UrgentBurstFactorCursor[DML2_MAX_PLANES];
624 	double UrgentBurstFactorCursorPre[DML2_MAX_PLANES];
625 	double UrgentBurstFactorLuma[DML2_MAX_PLANES];
626 	double UrgentBurstFactorLumaPre[DML2_MAX_PLANES];
627 	double UrgentBurstFactorChroma[DML2_MAX_PLANES];
628 	double UrgentBurstFactorChromaPre[DML2_MAX_PLANES];
629 
630 	double meta_row_bw[DML2_MAX_PLANES];
631 	unsigned int meta_row_bytes[DML2_MAX_PLANES];
632 	unsigned int meta_req_width[DML2_MAX_PLANES];
633 	unsigned int meta_req_height[DML2_MAX_PLANES];
634 	unsigned int meta_row_width[DML2_MAX_PLANES];
635 	unsigned int meta_row_height[DML2_MAX_PLANES];
636 	unsigned int meta_req_width_chroma[DML2_MAX_PLANES];
637 	unsigned int meta_row_height_chroma[DML2_MAX_PLANES];
638 	unsigned int meta_row_width_chroma[DML2_MAX_PLANES];
639 	unsigned int meta_req_height_chroma[DML2_MAX_PLANES];
640 
641 	unsigned int swath_width_luma_ub[DML2_MAX_PLANES];
642 	unsigned int swath_width_chroma_ub[DML2_MAX_PLANES];
643 	unsigned int PixelPTEReqWidthY[DML2_MAX_PLANES];
644 	unsigned int PixelPTEReqHeightY[DML2_MAX_PLANES];
645 	unsigned int PTERequestSizeY[DML2_MAX_PLANES];
646 	unsigned int PixelPTEReqWidthC[DML2_MAX_PLANES];
647 	unsigned int PixelPTEReqHeightC[DML2_MAX_PLANES];
648 	unsigned int PTERequestSizeC[DML2_MAX_PLANES];
649 
650 	double TWait[DML2_MAX_PLANES];
651 	double Tdmdl_vm[DML2_MAX_PLANES];
652 	double Tdmdl[DML2_MAX_PLANES];
653 	double TSetup[DML2_MAX_PLANES];
654 	unsigned int dpde0_bytes_per_frame_ub_l[DML2_MAX_PLANES];
655 	unsigned int dpde0_bytes_per_frame_ub_c[DML2_MAX_PLANES];
656 
657 	unsigned int meta_pte_bytes_per_frame_ub_l[DML2_MAX_PLANES];
658 	unsigned int meta_pte_bytes_per_frame_ub_c[DML2_MAX_PLANES];
659 
660 	bool UnboundedRequestEnabled;
661 	unsigned int CompressedBufferSizeInkByte;
662 	unsigned int compbuf_reserved_space_64b;
663 	bool hw_debug5;
664 	unsigned int dcfclk_deep_sleep_hysteresis;
665 	unsigned int min_return_latency_in_dcfclk;
666 
667 	bool NotEnoughUrgentLatencyHiding[DML2_MAX_PLANES];
668 	bool NotEnoughUrgentLatencyHidingPre[DML2_MAX_PLANES];
669 	double ExtraLatency;
670 	double ExtraLatency_sr;
671 	double ExtraLatencyPrefetch;
672 	bool PrefetchAndImmediateFlipSupported;
673 	double TotalDataReadBandwidth;
674 	double BandwidthAvailableForImmediateFlip;
675 	bool NotEnoughTimeForDynamicMetadata[DML2_MAX_PLANES];
676 
677 	bool use_one_row_for_frame[DML2_MAX_PLANES];
678 	bool use_one_row_for_frame_flip[DML2_MAX_PLANES];
679 
680 	double TCalc;
681 	unsigned int TotImmediateFlipBytes;
682 
683 	// -------------------
684 	// Output
685 	// -------------------
686 	unsigned int pipe_plane[DML2_MAX_PLANES]; // <brief used mainly by dv to map the pipe inst to plane index within DML core; the plane idx of a pipe
687 	unsigned int num_active_pipes;
688 
689 	bool NoTimeToPrefetch[DML2_MAX_PLANES]; // <brief Prefetch schedule calculation result
690 
691 	// Support
692 	bool UrgVactiveBandwidthSupport;
693 	bool PrefetchModeSupported; // <brief Is the prefetch mode (bandwidth and latency) supported
694 	bool ImmediateFlipSupported;
695 	bool ImmediateFlipSupportedForPipe[DML2_MAX_PLANES];
696 
697 	// Clock
698 	double Dcfclk;
699 	double Dispclk; // <brief dispclk being used in mode programming
700 	double Dppclk[DML2_MAX_PLANES]; // <brief dppclk being used in mode programming
701 	double GlobalDPPCLK;
702 
703 	double DSCCLK[DML2_MAX_PLANES]; //< brief Required DSCCLK freq. Backend; not used in any subsequent calculations for now
704 	double DCFCLKDeepSleep;
705 
706 	// ARB reg
707 	bool DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE;
708 	struct dml2_core_internal_watermarks Watermark;
709 
710 	// DCC compression control
711 	unsigned int request_size_bytes_luma[DML2_MAX_PLANES];
712 	unsigned int request_size_bytes_chroma[DML2_MAX_PLANES];
713 	enum dml2_core_internal_request_type RequestLuma[DML2_MAX_PLANES];
714 	enum dml2_core_internal_request_type RequestChroma[DML2_MAX_PLANES];
715 	unsigned int DCCYMaxUncompressedBlock[DML2_MAX_PLANES];
716 	unsigned int DCCYMaxCompressedBlock[DML2_MAX_PLANES];
717 	unsigned int DCCYIndependentBlock[DML2_MAX_PLANES];
718 	unsigned int DCCCMaxUncompressedBlock[DML2_MAX_PLANES];
719 	unsigned int DCCCMaxCompressedBlock[DML2_MAX_PLANES];
720 	unsigned int DCCCIndependentBlock[DML2_MAX_PLANES];
721 
722 	// Stutter Efficiency
723 	double StutterEfficiency;
724 	double StutterEfficiencyNotIncludingVBlank;
725 	unsigned int NumberOfStutterBurstsPerFrame;
726 	double Z8StutterEfficiency;
727 	unsigned int Z8NumberOfStutterBurstsPerFrame;
728 	double Z8StutterEfficiencyNotIncludingVBlank;
729 	double StutterPeriod;
730 	double Z8StutterEfficiencyBestCase;
731 	unsigned int Z8NumberOfStutterBurstsPerFrameBestCase;
732 	double Z8StutterEfficiencyNotIncludingVBlankBestCase;
733 	double StutterPeriodBestCase;
734 
735 	// DLG TTU reg
736 	double MIN_DST_Y_NEXT_START[DML2_MAX_PLANES];
737 	bool VREADY_AT_OR_AFTER_VSYNC[DML2_MAX_PLANES];
738 	unsigned int DSTYAfterScaler[DML2_MAX_PLANES];
739 	unsigned int DSTXAfterScaler[DML2_MAX_PLANES];
740 	double dst_y_prefetch[DML2_MAX_PLANES];
741 	double dst_y_per_vm_vblank[DML2_MAX_PLANES];
742 	double dst_y_per_row_vblank[DML2_MAX_PLANES];
743 	double dst_y_per_vm_flip[DML2_MAX_PLANES];
744 	double dst_y_per_row_flip[DML2_MAX_PLANES];
745 	double MinTTUVBlank[DML2_MAX_PLANES];
746 	double DisplayPipeLineDeliveryTimeLuma[DML2_MAX_PLANES];
747 	double DisplayPipeLineDeliveryTimeChroma[DML2_MAX_PLANES];
748 	double DisplayPipeLineDeliveryTimeLumaPrefetch[DML2_MAX_PLANES];
749 	double DisplayPipeLineDeliveryTimeChromaPrefetch[DML2_MAX_PLANES];
750 	double DisplayPipeRequestDeliveryTimeLuma[DML2_MAX_PLANES];
751 	double DisplayPipeRequestDeliveryTimeChroma[DML2_MAX_PLANES];
752 	double DisplayPipeRequestDeliveryTimeLumaPrefetch[DML2_MAX_PLANES];
753 	double DisplayPipeRequestDeliveryTimeChromaPrefetch[DML2_MAX_PLANES];
754 	unsigned int CursorDstXOffset[DML2_MAX_PLANES];
755 	unsigned int CursorDstYOffset[DML2_MAX_PLANES];
756 	unsigned int CursorChunkHDLAdjust[DML2_MAX_PLANES];
757 
758 	double DST_Y_PER_PTE_ROW_NOM_L[DML2_MAX_PLANES];
759 	double DST_Y_PER_PTE_ROW_NOM_C[DML2_MAX_PLANES];
760 	double time_per_pte_group_nom_luma[DML2_MAX_PLANES];
761 	double time_per_pte_group_nom_chroma[DML2_MAX_PLANES];
762 	double time_per_pte_group_vblank_luma[DML2_MAX_PLANES];
763 	double time_per_pte_group_vblank_chroma[DML2_MAX_PLANES];
764 	double time_per_pte_group_flip_luma[DML2_MAX_PLANES];
765 	double time_per_pte_group_flip_chroma[DML2_MAX_PLANES];
766 	double TimePerVMGroupVBlank[DML2_MAX_PLANES];
767 	double TimePerVMGroupFlip[DML2_MAX_PLANES];
768 	double TimePerVMRequestVBlank[DML2_MAX_PLANES];
769 	double TimePerVMRequestFlip[DML2_MAX_PLANES];
770 
771 	double DST_Y_PER_META_ROW_NOM_L[DML2_MAX_PLANES];
772 	double DST_Y_PER_META_ROW_NOM_C[DML2_MAX_PLANES];
773 	double TimePerMetaChunkNominal[DML2_MAX_PLANES];
774 	double TimePerChromaMetaChunkNominal[DML2_MAX_PLANES];
775 	double TimePerMetaChunkVBlank[DML2_MAX_PLANES];
776 	double TimePerChromaMetaChunkVBlank[DML2_MAX_PLANES];
777 	double TimePerMetaChunkFlip[DML2_MAX_PLANES];
778 	double TimePerChromaMetaChunkFlip[DML2_MAX_PLANES];
779 
780 	double FractionOfUrgentBandwidth;
781 	double FractionOfUrgentBandwidthImmediateFlip;
782 	double FractionOfUrgentBandwidthMALL;
783 
784 	// RQ registers
785 	bool PTE_BUFFER_MODE[DML2_MAX_PLANES];
786 	unsigned int BIGK_FRAGMENT_SIZE[DML2_MAX_PLANES];
787 
788 	unsigned int SubViewportLinesNeededInMALL[DML2_MAX_PLANES];
789 	bool is_using_mall_for_ss[DML2_MAX_PLANES];
790 
791 	// OTG
792 	unsigned int VStartupMin[DML2_MAX_PLANES]; /// <brief Minimum vstartup to meet the prefetch schedule (i.e. the prefetch solution can be found at this vstartup time); not the actual global sync vstartup pos.
793 	unsigned int VStartup[DML2_MAX_PLANES]; /// <brief The vstartup value for OTG programming (will set to max vstartup; but now bounded by min(vblank_nom. actual vblank))
794 	unsigned int VUpdateOffsetPix[DML2_MAX_PLANES];
795 	unsigned int VUpdateWidthPix[DML2_MAX_PLANES];
796 	unsigned int VReadyOffsetPix[DML2_MAX_PLANES];
797 	unsigned int pstate_keepout_dst_lines[DML2_MAX_PLANES];
798 
799 	// Latency and Support
800 	double MaxActiveFCLKChangeLatencySupported;
801 	bool USRRetrainingSupport;
802 	bool g6_temp_read_support;
803 	bool temp_read_or_ppt_support;
804 	enum dml2_pstate_change_support FCLKChangeSupport[DML2_MAX_PLANES];
805 	enum dml2_pstate_change_support DRAMClockChangeSupport[DML2_MAX_PLANES];
806 	bool global_dram_clock_change_supported;
807 	bool global_fclk_change_supported;
808 	double MaxActiveDRAMClockChangeLatencySupported[DML2_MAX_PLANES];
809 	double WritebackAllowFCLKChangeEndPosition[DML2_MAX_PLANES];
810 	double WritebackAllowDRAMClockChangeEndPosition[DML2_MAX_PLANES];
811 
812 	// buffer sizing
813 	unsigned int DETBufferSizeInKByte[DML2_MAX_PLANES]; // <brief Recommended DET size configuration for this plane. All pipes under this plane should program the DET buffer size to the calculated value.
814 	unsigned int DETBufferSizeY[DML2_MAX_PLANES];
815 	unsigned int DETBufferSizeC[DML2_MAX_PLANES];
816 	unsigned int SwathHeightY[DML2_MAX_PLANES];
817 	unsigned int SwathHeightC[DML2_MAX_PLANES];
818 
819 	double urg_vactive_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // active bandwidth, scaled by urg burst factor
820 	double urg_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // include vm, prefetch, active bandwidth, scaled by urg burst factor
821 	double urg_bandwidth_required_qual[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // include vm, prefetch, active bandwidth, scaled by urg burst factor, use qual_row_bw
822 	double urg_bandwidth_required_flip[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // include vm, prefetch, active bandwidth + flip
823 	double non_urg_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // same as urg_bandwidth, except not scaled by urg burst factor
824 	double non_urg_bandwidth_required_flip[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max];
825 
826 	double avg_bandwidth_available_min[dml2_core_internal_soc_state_max];
827 	double avg_bandwidth_available[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max];
828 	double urg_bandwidth_available_min[dml2_core_internal_soc_state_max]; // min between SDP and DRAM
829 	double urg_bandwidth_available[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max];
830 	double urg_bandwidth_available_vm_only[dml2_core_internal_soc_state_max]; // the min of sdp bw and dram_vm_only bw, sdp has no different derate for vm/non-vm traffic etc.
831 	double urg_bandwidth_available_pixel_and_vm[dml2_core_internal_soc_state_max]; // the min of sdp bw and dram_pixel_and_vm bw, sdp has no different derate for vm/non-vm etc.
832 
833 	double dcc_dram_bw_nom_overhead_factor_p0[DML2_MAX_PLANES];
834 	double dcc_dram_bw_nom_overhead_factor_p1[DML2_MAX_PLANES];
835 	double dcc_dram_bw_pref_overhead_factor_p0[DML2_MAX_PLANES];
836 	double dcc_dram_bw_pref_overhead_factor_p1[DML2_MAX_PLANES];
837 	double mall_prefetch_sdp_overhead_factor[DML2_MAX_PLANES];
838 	double mall_prefetch_dram_overhead_factor[DML2_MAX_PLANES];
839 
840 	unsigned int num_mcaches_l[DML2_MAX_PLANES];
841 	unsigned int mcache_row_bytes_l[DML2_MAX_PLANES];
842 	unsigned int mcache_offsets_l[DML2_MAX_PLANES][DML2_MAX_MCACHES + 1];
843 	unsigned int mcache_shift_granularity_l[DML2_MAX_PLANES];
844 
845 	unsigned int num_mcaches_c[DML2_MAX_PLANES];
846 	unsigned int mcache_row_bytes_c[DML2_MAX_PLANES];
847 	unsigned int mcache_offsets_c[DML2_MAX_PLANES][DML2_MAX_MCACHES + 1];
848 	unsigned int mcache_shift_granularity_c[DML2_MAX_PLANES];
849 
850 	bool mall_comb_mcache_l[DML2_MAX_PLANES];
851 	bool mall_comb_mcache_c[DML2_MAX_PLANES];
852 	bool lc_comb_mcache[DML2_MAX_PLANES];
853 
854 	double impacted_prefetch_margin_us[DML2_MAX_PLANES];
855 };
856 
857 struct dml2_core_internal_SOCParametersList {
858 	double UrgentLatency;
859 	double ExtraLatency_sr;
860 	double ExtraLatency;
861 	double WritebackLatency;
862 	double DRAMClockChangeLatency;
863 	double FCLKChangeLatency;
864 	double SRExitTime;
865 	double SREnterPlusExitTime;
866 	double SRExitZ8Time;
867 	double SREnterPlusExitZ8Time;
868 	double USRRetrainingLatency;
869 	double SMNLatency;
870 	double g6_temp_read_blackout_us;
871 	double temp_read_or_ppt_blackout_us;
872 	double max_urgent_latency_us;
873 	double df_response_time_us;
874 	enum dml2_qos_param_type qos_type;
875 };
876 
877 struct dml2_core_calcs_mode_support_locals {
878 	double PixelClockBackEnd[DML2_MAX_PLANES];
879 	double OutputBpp[DML2_MAX_PLANES];
880 
881 	unsigned int meta_row_height_luma[DML2_MAX_PLANES];
882 	unsigned int meta_row_height_chroma[DML2_MAX_PLANES];
883 	unsigned int meta_row_bytes_per_row_ub_l[DML2_MAX_PLANES];
884 	unsigned int meta_row_bytes_per_row_ub_c[DML2_MAX_PLANES];
885 	unsigned int dpte_row_bytes_per_row_l[DML2_MAX_PLANES];
886 	unsigned int dpte_row_bytes_per_row_c[DML2_MAX_PLANES];
887 
888 	bool dummy_boolean[3];
889 	unsigned int dummy_integer[3];
890 	unsigned int dummy_integer_array[36][DML2_MAX_PLANES];
891 	enum dml2_odm_mode dummy_odm_mode[DML2_MAX_PLANES];
892 	bool dummy_boolean_array[2][DML2_MAX_PLANES];
893 	double dummy_single[3];
894 	double dummy_single_array[DML2_MAX_PLANES];
895 	struct dml2_core_internal_watermarks dummy_watermark;
896 	double dummy_bw[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max];
897 	double surface_dummy_bw[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max][DML2_MAX_PLANES];
898 
899 	unsigned int MaximumVStartup[DML2_MAX_PLANES];
900 	unsigned int DSTYAfterScaler[DML2_MAX_PLANES];
901 	unsigned int DSTXAfterScaler[DML2_MAX_PLANES];
902 	struct dml2_core_internal_SOCParametersList mSOCParameters;
903 	struct dml2_core_internal_DmlPipe myPipe;
904 	struct dml2_core_internal_DmlPipe SurfParameters[DML2_MAX_PLANES];
905 	unsigned int TotalNumberOfActiveWriteback;
906 	unsigned int MaximumSwathWidthSupportLuma;
907 	unsigned int MaximumSwathWidthSupportChroma;
908 	bool MPCCombineMethodAsNeededForPStateChangeAndVoltage;
909 	bool MPCCombineMethodAsPossible;
910 	bool TotalAvailablePipesSupportNoDSC;
911 	unsigned int NumberOfDPPNoDSC;
912 	enum dml2_odm_mode ODMModeNoDSC;
913 	double RequiredDISPCLKPerSurfaceNoDSC;
914 	bool TotalAvailablePipesSupportDSC;
915 	unsigned int NumberOfDPPDSC;
916 	enum dml2_odm_mode ODMModeDSC;
917 	double RequiredDISPCLKPerSurfaceDSC;
918 	double BWOfNonCombinedSurfaceOfMaximumBandwidth;
919 	unsigned int NumberOfNonCombinedSurfaceOfMaximumBandwidth;
920 	unsigned int TotalNumberOfActiveOTG;
921 	unsigned int TotalNumberOfActiveHDMIFRL;
922 	unsigned int TotalNumberOfActiveDP2p0;
923 	unsigned int TotalNumberOfActiveDP2p0Outputs;
924 	unsigned int TotalSlots;
925 	unsigned int DSCFormatFactor;
926 	unsigned int TotalDSCUnitsRequired;
927 	unsigned int ReorderingBytes;
928 	bool ImmediateFlipRequired;
929 	bool FullFrameMALLPStateMethod;
930 	bool SubViewportMALLPStateMethod;
931 	bool PhantomPipeMALLPStateMethod;
932 	bool SubViewportMALLRefreshGreaterThan120Hz;
933 
934 	double HostVMInefficiencyFactor;
935 	double HostVMInefficiencyFactorPrefetch;
936 	unsigned int MaxVStartup;
937 	double PixelClockBackEndFactor;
938 	unsigned int NumDSCUnitRequired;
939 
940 	double Tvm_trips[DML2_MAX_PLANES];
941 	double Tr0_trips[DML2_MAX_PLANES];
942 	double Tvm_trips_flip[DML2_MAX_PLANES];
943 	double Tr0_trips_flip[DML2_MAX_PLANES];
944 	double Tvm_trips_flip_rounded[DML2_MAX_PLANES];
945 	double Tr0_trips_flip_rounded[DML2_MAX_PLANES];
946 	unsigned int per_pipe_flip_bytes[DML2_MAX_PLANES];
947 
948 	unsigned int vmpg_width_y[DML2_MAX_PLANES];
949 	unsigned int vmpg_height_y[DML2_MAX_PLANES];
950 	unsigned int vmpg_width_c[DML2_MAX_PLANES];
951 	unsigned int vmpg_height_c[DML2_MAX_PLANES];
952 	unsigned int full_swath_bytes_l[DML2_MAX_PLANES];
953 	unsigned int full_swath_bytes_c[DML2_MAX_PLANES];
954 
955 	unsigned int tdlut_pte_bytes_per_frame[DML2_MAX_PLANES];
956 	unsigned int tdlut_bytes_per_frame[DML2_MAX_PLANES];
957 	unsigned int tdlut_row_bytes[DML2_MAX_PLANES];
958 	unsigned int tdlut_groups_per_2row_ub[DML2_MAX_PLANES];
959 	double tdlut_opt_time[DML2_MAX_PLANES];
960 	double tdlut_drain_time[DML2_MAX_PLANES];
961 	unsigned int tdlut_bytes_to_deliver[DML2_MAX_PLANES];
962 	unsigned int tdlut_bytes_per_group[DML2_MAX_PLANES];
963 
964 	unsigned int cursor_bytes_per_chunk[DML2_MAX_PLANES];
965 	unsigned int cursor_bytes_per_line[DML2_MAX_PLANES];
966 	unsigned int cursor_lines_per_chunk[DML2_MAX_PLANES];
967 	unsigned int cursor_bytes[DML2_MAX_PLANES];
968 	bool stream_visited[DML2_MAX_PLANES];
969 
970 	unsigned int pstate_bytes_required_l[DML2_MAX_PLANES];
971 	unsigned int pstate_bytes_required_c[DML2_MAX_PLANES];
972 
973 	double prefetch_sw_bytes[DML2_MAX_PLANES];
974 	double Tpre_rounded[DML2_MAX_PLANES];
975 	double Tpre_oto[DML2_MAX_PLANES];
976 	bool recalc_prefetch_schedule;
977 	bool recalc_prefetch_done;
978 	double impacted_dst_y_pre[DML2_MAX_PLANES];
979 	double line_times[DML2_MAX_PLANES];
980 	enum dml2_source_format_class pixel_format[DML2_MAX_PLANES];
981 	unsigned int lb_source_lines_l[DML2_MAX_PLANES];
982 	unsigned int lb_source_lines_c[DML2_MAX_PLANES];
983 	double prefetch_swath_time_us[DML2_MAX_PLANES];
984 };
985 
986 struct dml2_core_calcs_mode_programming_locals {
987 	double PixelClockBackEnd[DML2_MAX_PLANES];
988 	double OutputBpp[DML2_MAX_PLANES];
989 	unsigned int num_active_planes; // <brief As determined by either e2e_pipe_param or display_cfg
990 	unsigned int MaxTotalDETInKByte;
991 	unsigned int NomDETInKByte;
992 	unsigned int MinCompressedBufferSizeInKByte;
993 	double SOCCLK; /// <brief Basically just the clock freq at the min (or given) state
994 
995 	double dummy_bw[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max];
996 	double surface_dummy_bw[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max][DML2_MAX_PLANES];
997 	double surface_dummy_bw0[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max][DML2_MAX_PLANES];
998 	unsigned int dummy_integer_array[2][DML2_MAX_PLANES];
999 	enum dml2_output_encoder_class dummy_output_encoder_array[DML2_MAX_PLANES];
1000 	double dummy_single_array[2][DML2_MAX_PLANES];
1001 	unsigned int dummy_long_array[4][DML2_MAX_PLANES];
1002 	bool dummy_boolean_array[2][DML2_MAX_PLANES];
1003 	bool dummy_boolean[2];
1004 	double dummy_single[2];
1005 	struct dml2_core_internal_watermarks dummy_watermark;
1006 
1007 	unsigned int DSCFormatFactor;
1008 	struct dml2_core_internal_DmlPipe SurfaceParameters[DML2_MAX_PLANES];
1009 	unsigned int ReorderingBytes;
1010 	double HostVMInefficiencyFactor;
1011 	double HostVMInefficiencyFactorPrefetch;
1012 	unsigned int TotalDCCActiveDPP;
1013 	unsigned int TotalActiveDPP;
1014 	unsigned int Total3dlutActive;
1015 	unsigned int MaxVStartupLines[DML2_MAX_PLANES]; /// <brief more like vblank for the plane's OTG
1016 	bool immediate_flip_required; // any pipes need immediate flip
1017 	bool DestinationLineTimesForPrefetchLessThan2;
1018 	bool VRatioPrefetchMoreThanMax;
1019 	double MaxTotalRDBandwidthNotIncludingMALLPrefetch;
1020 	struct dml2_core_internal_SOCParametersList mmSOCParameters;
1021 	double Tvstartup_margin;
1022 	double dlg_vblank_start;
1023 	double LSetup;
1024 	double blank_lines_remaining;
1025 	double TotalWRBandwidth;
1026 	double WRBandwidth;
1027 	struct dml2_core_internal_DmlPipe myPipe;
1028 	double PixelClockBackEndFactor;
1029 	unsigned int vmpg_width_y[DML2_MAX_PLANES];
1030 	unsigned int vmpg_height_y[DML2_MAX_PLANES];
1031 	unsigned int vmpg_width_c[DML2_MAX_PLANES];
1032 	unsigned int vmpg_height_c[DML2_MAX_PLANES];
1033 	unsigned int full_swath_bytes_l[DML2_MAX_PLANES];
1034 	unsigned int full_swath_bytes_c[DML2_MAX_PLANES];
1035 
1036 	unsigned int meta_row_bytes_per_row_ub_l[DML2_MAX_PLANES];
1037 	unsigned int meta_row_bytes_per_row_ub_c[DML2_MAX_PLANES];
1038 	unsigned int dpte_row_bytes_per_row_l[DML2_MAX_PLANES];
1039 	unsigned int dpte_row_bytes_per_row_c[DML2_MAX_PLANES];
1040 
1041 	unsigned int tdlut_pte_bytes_per_frame[DML2_MAX_PLANES];
1042 	unsigned int tdlut_bytes_per_frame[DML2_MAX_PLANES];
1043 	unsigned int tdlut_row_bytes[DML2_MAX_PLANES];
1044 	unsigned int tdlut_groups_per_2row_ub[DML2_MAX_PLANES];
1045 	double tdlut_opt_time[DML2_MAX_PLANES];
1046 	double tdlut_drain_time[DML2_MAX_PLANES];
1047 	unsigned int tdlut_bytes_to_deliver[DML2_MAX_PLANES];
1048 	unsigned int tdlut_bytes_per_group[DML2_MAX_PLANES];
1049 
1050 	unsigned int cursor_bytes_per_chunk[DML2_MAX_PLANES];
1051 	unsigned int cursor_bytes_per_line[DML2_MAX_PLANES];
1052 	unsigned int cursor_lines_per_chunk[DML2_MAX_PLANES];
1053 	unsigned int cursor_bytes[DML2_MAX_PLANES];
1054 
1055 	double Tvm_trips[DML2_MAX_PLANES];
1056 	double Tr0_trips[DML2_MAX_PLANES];
1057 	double Tvm_trips_flip[DML2_MAX_PLANES];
1058 	double Tr0_trips_flip[DML2_MAX_PLANES];
1059 	double Tvm_trips_flip_rounded[DML2_MAX_PLANES];
1060 	double Tr0_trips_flip_rounded[DML2_MAX_PLANES];
1061 	unsigned int per_pipe_flip_bytes[DML2_MAX_PLANES];
1062 
1063 	unsigned int pstate_bytes_required_l[DML2_MAX_PLANES];
1064 	unsigned int pstate_bytes_required_c[DML2_MAX_PLANES];
1065 
1066 	double prefetch_sw_bytes[DML2_MAX_PLANES];
1067 	double Tpre_rounded[DML2_MAX_PLANES];
1068 	double Tpre_oto[DML2_MAX_PLANES];
1069 	bool recalc_prefetch_schedule;
1070 	double impacted_dst_y_pre[DML2_MAX_PLANES];
1071 	double line_times[DML2_MAX_PLANES];
1072 	enum dml2_source_format_class pixel_format[DML2_MAX_PLANES];
1073 	unsigned int lb_source_lines_l[DML2_MAX_PLANES];
1074 	unsigned int lb_source_lines_c[DML2_MAX_PLANES];
1075 };
1076 
1077 struct dml2_core_calcs_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_locals {
1078 	double ActiveDRAMClockChangeLatencyMargin[DML2_MAX_PLANES];
1079 	double ActiveFCLKChangeLatencyMargin[DML2_MAX_PLANES];
1080 	double USRRetrainingLatencyMargin[DML2_MAX_PLANES];
1081 	double g6_temp_read_latency_margin[DML2_MAX_PLANES];
1082 	double temp_read_or_ppt_latency_margin[DML2_MAX_PLANES];
1083 
1084 	double EffectiveLBLatencyHidingY;
1085 	double EffectiveLBLatencyHidingC;
1086 	double LinesInDETY[DML2_MAX_PLANES];
1087 	double LinesInDETC[DML2_MAX_PLANES];
1088 	unsigned int LinesInDETYRoundedDownToSwath[DML2_MAX_PLANES];
1089 	unsigned int LinesInDETCRoundedDownToSwath[DML2_MAX_PLANES];
1090 	double FullDETBufferingTimeY;
1091 	double FullDETBufferingTimeC;
1092 	double WritebackDRAMClockChangeLatencyMargin;
1093 	double WritebackFCLKChangeLatencyMargin;
1094 	double WritebackLatencyHiding;
1095 
1096 	unsigned int TotalActiveWriteback;
1097 	unsigned int LBLatencyHidingSourceLinesY[DML2_MAX_PLANES];
1098 	unsigned int LBLatencyHidingSourceLinesC[DML2_MAX_PLANES];
1099 	double TotalPixelBW;
1100 	double EffectiveDETBufferSizeY;
1101 	double ActiveClockChangeLatencyHidingY;
1102 	double ActiveClockChangeLatencyHidingC;
1103 	double ActiveClockChangeLatencyHiding;
1104 	unsigned int dst_y_pstate;
1105 	unsigned int src_y_pstate_l;
1106 	unsigned int src_y_pstate_c;
1107 	unsigned int src_y_ahead_l;
1108 	unsigned int src_y_ahead_c;
1109 	unsigned int sub_vp_lines_l;
1110 	unsigned int sub_vp_lines_c;
1111 
1112 };
1113 
1114 struct dml2_core_calcs_CalculateVMRowAndSwath_locals {
1115 	unsigned int PTEBufferSizeInRequestsForLuma[DML2_MAX_PLANES];
1116 	unsigned int PTEBufferSizeInRequestsForChroma[DML2_MAX_PLANES];
1117 	unsigned int vm_bytes_l;
1118 	unsigned int vm_bytes_c;
1119 	unsigned int PixelPTEBytesPerRowY[DML2_MAX_PLANES];
1120 	unsigned int PixelPTEBytesPerRowC[DML2_MAX_PLANES];
1121 	unsigned int PixelPTEBytesPerRowStorageY[DML2_MAX_PLANES];
1122 	unsigned int PixelPTEBytesPerRowStorageC[DML2_MAX_PLANES];
1123 	unsigned int PixelPTEBytesPerRowY_one_row_per_frame[DML2_MAX_PLANES];
1124 	unsigned int PixelPTEBytesPerRowC_one_row_per_frame[DML2_MAX_PLANES];
1125 	unsigned int dpte_row_width_luma_ub_one_row_per_frame[DML2_MAX_PLANES];
1126 	unsigned int dpte_row_height_luma_one_row_per_frame[DML2_MAX_PLANES];
1127 	unsigned int dpte_row_width_chroma_ub_one_row_per_frame[DML2_MAX_PLANES];
1128 	unsigned int dpte_row_height_chroma_one_row_per_frame[DML2_MAX_PLANES];
1129 	bool one_row_per_frame_fits_in_buffer[DML2_MAX_PLANES];
1130 	unsigned int HostVMDynamicLevels;
1131 	unsigned int meta_row_bytes_per_row_ub_l[DML2_MAX_PLANES];
1132 	unsigned int meta_row_bytes_per_row_ub_c[DML2_MAX_PLANES];
1133 };
1134 
1135 struct dml2_core_calcs_CalculateVMRowAndSwath_params {
1136 	const struct dml2_display_cfg *display_cfg;
1137 	unsigned int NumberOfActiveSurfaces;
1138 	struct dml2_core_internal_DmlPipe *myPipe;
1139 	unsigned int *SurfaceSizeInMALL;
1140 	unsigned int PTEBufferSizeInRequestsLuma;
1141 	unsigned int PTEBufferSizeInRequestsChroma;
1142 	unsigned int MALLAllocatedForDCN;
1143 	unsigned int *SwathWidthY;
1144 	unsigned int *SwathWidthC;
1145 	unsigned int HostVMMinPageSize;
1146 	unsigned int DCCMetaBufferSizeBytes;
1147 	bool mrq_present;
1148 
1149 	// Output
1150 	bool *PTEBufferSizeNotExceeded;
1151 	bool *DCCMetaBufferSizeNotExceeded;
1152 
1153 	unsigned int *dpte_row_width_luma_ub;
1154 	unsigned int *dpte_row_width_chroma_ub;
1155 	unsigned int *dpte_row_height_luma;
1156 	unsigned int *dpte_row_height_chroma;
1157 	unsigned int *dpte_row_height_linear_luma; // VBA_DELTA
1158 	unsigned int *dpte_row_height_linear_chroma; // VBA_DELTA
1159 
1160 	unsigned int *vm_group_bytes;
1161 	unsigned int *dpte_group_bytes;
1162 	unsigned int *PixelPTEReqWidthY;
1163 	unsigned int *PixelPTEReqHeightY;
1164 	unsigned int *PTERequestSizeY;
1165 	unsigned int *vmpg_width_y;
1166 	unsigned int *vmpg_height_y;
1167 
1168 	unsigned int *PixelPTEReqWidthC;
1169 	unsigned int *PixelPTEReqHeightC;
1170 	unsigned int *PTERequestSizeC;
1171 	unsigned int *vmpg_width_c;
1172 	unsigned int *vmpg_height_c;
1173 
1174 	unsigned int *dpde0_bytes_per_frame_ub_l;
1175 	unsigned int *dpde0_bytes_per_frame_ub_c;
1176 
1177 	unsigned int *PrefetchSourceLinesY;
1178 	unsigned int *PrefetchSourceLinesC;
1179 	unsigned int *VInitPreFillY;
1180 	unsigned int *VInitPreFillC;
1181 	unsigned int *MaxNumSwathY;
1182 	unsigned int *MaxNumSwathC;
1183 	double *dpte_row_bw;
1184 	unsigned int *PixelPTEBytesPerRow;
1185 	unsigned int *dpte_row_bytes_per_row_l;
1186 	unsigned int *dpte_row_bytes_per_row_c;
1187 	unsigned int *vm_bytes;
1188 	bool *use_one_row_for_frame;
1189 	bool *use_one_row_for_frame_flip;
1190 	bool *is_using_mall_for_ss;
1191 	bool *PTE_BUFFER_MODE;
1192 	unsigned int *BIGK_FRAGMENT_SIZE;
1193 
1194 	// MRQ
1195 	unsigned int *meta_req_width_luma;
1196 	unsigned int *meta_req_height_luma;
1197 	unsigned int *meta_row_width_luma;
1198 	unsigned int *meta_row_height_luma;
1199 	unsigned int *meta_pte_bytes_per_frame_ub_l;
1200 
1201 	unsigned int *meta_req_width_chroma;
1202 	unsigned int *meta_req_height_chroma;
1203 	unsigned int *meta_row_width_chroma;
1204 	unsigned int *meta_row_height_chroma;
1205 	unsigned int *meta_pte_bytes_per_frame_ub_c;
1206 	double *meta_row_bw;
1207 	unsigned int *meta_row_bytes;
1208 	unsigned int *meta_row_bytes_per_row_ub_l;
1209 	unsigned int *meta_row_bytes_per_row_ub_c;
1210 };
1211 
1212 struct dml2_core_calcs_CalculatePrefetchSchedule_locals {
1213 	bool NoTimeToPrefetch;
1214 	unsigned int DPPCycles;
1215 	unsigned int DISPCLKCycles;
1216 	double DSTTotalPixelsAfterScaler;
1217 	double LineTime;
1218 	double dst_y_prefetch_equ;
1219 	double prefetch_bw_oto;
1220 	double per_pipe_vactive_sw_bw;
1221 	double Tvm_oto;
1222 	double Tr0_oto;
1223 	double Tvm_oto_lines;
1224 	double Tr0_oto_lines;
1225 	double dst_y_prefetch_oto;
1226 	double TimeForFetchingVM;
1227 	double TimeForFetchingRowInVBlank;
1228 	double LinesToRequestPrefetchPixelData;
1229 	unsigned int HostVMDynamicLevelsTrips;
1230 	double trip_to_mem;
1231 	double Tvm_trips_rounded;
1232 	double Tr0_trips_rounded;
1233 	double max_Tsw;
1234 	double Lsw_oto;
1235 	double prefetch_bw_equ;
1236 	double Tvm_equ;
1237 	double Tr0_equ;
1238 	double Tdmbf;
1239 	double Tdmec;
1240 	double Tdmsks;
1241 	double total_row_bytes;
1242 	double prefetch_bw_pr;
1243 	double bytes_pp;
1244 	double dep_bytes;
1245 	double min_Lsw_oto;
1246 	double min_Lsw_equ;
1247 	double Tsw_est1;
1248 	double Tsw_est2;
1249 	double Tsw_est3;
1250 	double prefetch_bw1;
1251 	double prefetch_bw2;
1252 	double prefetch_bw3;
1253 	double prefetch_bw4;
1254 	double dst_y_prefetch_equ_impacted;
1255 
1256 	double TWait_p;
1257 	unsigned int cursor_prefetch_bytes;
1258 };
1259 
1260 struct dml2_core_shared_calculate_det_buffer_size_params {
1261 	const struct dml2_display_cfg *display_cfg;
1262 	bool ForceSingleDPP;
1263 	unsigned int NumberOfActiveSurfaces;
1264 	bool UnboundedRequestEnabled;
1265 	unsigned int nomDETInKByte;
1266 	unsigned int MaxTotalDETInKByte;
1267 	unsigned int ConfigReturnBufferSizeInKByte;
1268 	unsigned int MinCompressedBufferSizeInKByte;
1269 	unsigned int ConfigReturnBufferSegmentSizeInkByte;
1270 	unsigned int CompressedBufferSegmentSizeInkByte;
1271 	double *ReadBandwidthLuma;
1272 	double *ReadBandwidthChroma;
1273 	unsigned int *full_swath_bytes_l;
1274 	unsigned int *full_swath_bytes_c;
1275 	unsigned int *swath_time_value_us;
1276 	unsigned int *DPPPerSurface;
1277 	bool TryToAllocateForWriteLatency;
1278 	unsigned int bestEffortMinActiveLatencyHidingUs;
1279 
1280 	// Output
1281 	unsigned int *DETBufferSizeInKByte;
1282 	unsigned int *CompressedBufferSizeInkByte;
1283 };
1284 
1285 struct dml2_core_shared_calculate_vm_and_row_bytes_params {
1286 	bool ViewportStationary;
1287 	bool DCCEnable;
1288 	unsigned int NumberOfDPPs;
1289 	unsigned int BlockHeight256Bytes;
1290 	unsigned int BlockWidth256Bytes;
1291 	enum dml2_source_format_class SourcePixelFormat;
1292 	unsigned int SurfaceTiling;
1293 	unsigned int BytePerPixel;
1294 	enum dml2_rotation_angle RotationAngle;
1295 	unsigned int SwathWidth; // per pipe
1296 	unsigned int ViewportHeight;
1297 	unsigned int ViewportXStart;
1298 	unsigned int ViewportYStart;
1299 	bool GPUVMEnable;
1300 	unsigned int GPUVMMaxPageTableLevels;
1301 	unsigned int GPUVMMinPageSizeKBytes;
1302 	unsigned int PTEBufferSizeInRequests;
1303 	unsigned int Pitch;
1304 	unsigned int MacroTileWidth;
1305 	unsigned int MacroTileHeight;
1306 	bool is_phantom;
1307 	unsigned int DCCMetaPitch;
1308 	bool mrq_present;
1309 
1310 	// Output
1311 	unsigned int *PixelPTEBytesPerRow; // for bandwidth calculation
1312 	unsigned int *PixelPTEBytesPerRowStorage; // for PTE buffer size check
1313 	unsigned int *dpte_row_width_ub;
1314 	unsigned int *dpte_row_height;
1315 	unsigned int *dpte_row_height_linear;
1316 	unsigned int *PixelPTEBytesPerRow_one_row_per_frame;
1317 	unsigned int *dpte_row_width_ub_one_row_per_frame;
1318 	unsigned int *dpte_row_height_one_row_per_frame;
1319 	unsigned int *vmpg_width;
1320 	unsigned int *vmpg_height;
1321 	unsigned int *PixelPTEReqWidth;
1322 	unsigned int *PixelPTEReqHeight;
1323 	unsigned int *PTERequestSize;
1324 	unsigned int *dpde0_bytes_per_frame_ub;
1325 
1326 	unsigned int *meta_row_bytes;
1327 	unsigned int *MetaRequestWidth;
1328 	unsigned int *MetaRequestHeight;
1329 	unsigned int *meta_row_width;
1330 	unsigned int *meta_row_height;
1331 	unsigned int *meta_pte_bytes_per_frame_ub;
1332 };
1333 
1334 struct dml2_core_shared_CalculateSwathAndDETConfiguration_locals {
1335 	unsigned int MaximumSwathHeightY[DML2_MAX_PLANES];
1336 	unsigned int MaximumSwathHeightC[DML2_MAX_PLANES];
1337 	unsigned int RoundedUpSwathSizeBytesY[DML2_MAX_PLANES];
1338 	unsigned int RoundedUpSwathSizeBytesC[DML2_MAX_PLANES];
1339 	unsigned int SwathWidthSingleDPP[DML2_MAX_PLANES];
1340 	unsigned int SwathWidthSingleDPPChroma[DML2_MAX_PLANES];
1341 	unsigned int SwathTimeValueUs[DML2_MAX_PLANES];
1342 
1343 	struct dml2_core_shared_calculate_det_buffer_size_params calculate_det_buffer_size_params;
1344 };
1345 
1346 struct dml2_core_shared_TruncToValidBPP_locals {
1347 };
1348 
1349 struct dml2_core_shared_CalculateDETBufferSize_locals {
1350 	unsigned int DETBufferSizePoolInKByte;
1351 	unsigned int NextDETBufferPieceInKByte;
1352 	unsigned int NextSurfaceToAssignDETPiece;
1353 	double TotalBandwidth;
1354 	double BandwidthOfSurfacesNotAssignedDETPiece;
1355 	unsigned int max_minDET;
1356 	unsigned int minDET;
1357 	unsigned int minDET_pipe;
1358 	unsigned int TotalBandwidthPerStream[DML2_MAX_PLANES];
1359 	unsigned int TotalPixelRate;
1360 	unsigned int DETBudgetPerStream[DML2_MAX_PLANES];
1361 	unsigned int RemainingDETBudgetPerStream[DML2_MAX_PLANES];
1362 	unsigned int IdealDETBudget, DeltaDETBudget;
1363 	unsigned int ResidualDETAfterRounding;
1364 };
1365 
1366 struct dml2_core_shared_get_urgent_bandwidth_required_locals {
1367 	double required_bandwidth_mbps;
1368 	double required_bandwidth_mbps_this_surface;
1369 	double adj_factor_p0;
1370 	double adj_factor_p1;
1371 	double adj_factor_cur;
1372 	double adj_factor_p0_pre;
1373 	double adj_factor_p1_pre;
1374 	double adj_factor_cur_pre;
1375 	double per_plane_flip_bw[DML2_MAX_PLANES];
1376 	double mall_svp_prefetch_factor;
1377 	double tmp_nom_adj_factor_p0;
1378 	double tmp_nom_adj_factor_p1;
1379 	double tmp_pref_adj_factor_p0;
1380 	double tmp_pref_adj_factor_p1;
1381 	double vm_row_bw;
1382 	double flip_and_active_bw;
1383 	double flip_and_prefetch_bw;
1384 	double active_and_excess_bw;
1385 };
1386 
1387 struct dml2_core_shared_calculate_peak_bandwidth_required_locals {
1388 	double unity_array[DML2_MAX_PLANES];
1389 	double zero_array[DML2_MAX_PLANES];
1390 	double surface_dummy_bw[DML2_MAX_PLANES];
1391 };
1392 
1393 struct dml2_core_shared_CalculateFlipSchedule_locals {
1394 	double min_row_time;
1395 	double Tvm_flip;
1396 	double Tr0_flip;
1397 	double ImmediateFlipBW;
1398 	double dpte_row_bytes;
1399 	double min_row_height;
1400 	double min_row_height_chroma;
1401 	double max_flip_time;
1402 	double lb_flip_bw;
1403 	double hvm_scaled_vm_bytes;
1404 	double num_rows;
1405 	double hvm_scaled_row_bytes;
1406 	double hvm_scaled_vm_row_bytes;
1407 	bool dual_plane;
1408 };
1409 
1410 struct dml2_core_shared_rq_dlg_get_dlg_reg_locals {
1411 	unsigned int plane_idx;
1412 	enum dml2_source_format_class source_format;
1413 	const struct dml2_timing_cfg *timing;
1414 	bool dual_plane;
1415 	enum dml2_odm_mode odm_mode;
1416 
1417 	unsigned int htotal;
1418 	unsigned int hactive;
1419 	unsigned int hblank_end;
1420 	unsigned int vblank_end;
1421 	bool interlaced;
1422 	double pclk_freq_in_mhz;
1423 	double refclk_freq_in_mhz;
1424 	double ref_freq_to_pix_freq;
1425 
1426 	unsigned int num_active_pipes;
1427 	unsigned int first_pipe_idx_in_plane;
1428 	unsigned int pipe_idx_in_combine;
1429 	unsigned int odm_combine_factor;
1430 
1431 	double min_ttu_vblank;
1432 	unsigned int min_dst_y_next_start;
1433 
1434 	unsigned int vready_after_vcount0;
1435 
1436 	unsigned int dst_x_after_scaler;
1437 	unsigned int dst_y_after_scaler;
1438 
1439 	double dst_y_prefetch;
1440 	double dst_y_per_vm_vblank;
1441 	double dst_y_per_row_vblank;
1442 	double dst_y_per_vm_flip;
1443 	double dst_y_per_row_flip;
1444 
1445 	double max_dst_y_per_vm_vblank;
1446 	double max_dst_y_per_row_vblank;
1447 
1448 	double vratio_pre_l;
1449 	double vratio_pre_c;
1450 
1451 	double refcyc_per_line_delivery_pre_l;
1452 	double refcyc_per_line_delivery_l;
1453 
1454 	double refcyc_per_line_delivery_pre_c;
1455 	double refcyc_per_line_delivery_c;
1456 
1457 	double refcyc_per_req_delivery_pre_l;
1458 	double refcyc_per_req_delivery_l;
1459 
1460 	double refcyc_per_req_delivery_pre_c;
1461 	double refcyc_per_req_delivery_c;
1462 
1463 	double dst_y_per_pte_row_nom_l;
1464 	double dst_y_per_pte_row_nom_c;
1465 	double refcyc_per_pte_group_nom_l;
1466 	double refcyc_per_pte_group_nom_c;
1467 	double refcyc_per_pte_group_vblank_l;
1468 	double refcyc_per_pte_group_vblank_c;
1469 	double refcyc_per_pte_group_flip_l;
1470 	double refcyc_per_pte_group_flip_c;
1471 	double refcyc_per_tdlut_group;
1472 
1473 	double dst_y_per_meta_row_nom_l;
1474 	double dst_y_per_meta_row_nom_c;
1475 	double refcyc_per_meta_chunk_nom_l;
1476 	double refcyc_per_meta_chunk_nom_c;
1477 	double refcyc_per_meta_chunk_vblank_l;
1478 	double refcyc_per_meta_chunk_vblank_c;
1479 	double refcyc_per_meta_chunk_flip_l;
1480 	double refcyc_per_meta_chunk_flip_c;
1481 };
1482 
1483 struct dml2_core_shared_CalculateMetaAndPTETimes_params {
1484 	struct dml2_core_internal_scratch *scratch;
1485 	const struct dml2_display_cfg *display_cfg;
1486 	unsigned int NumberOfActiveSurfaces;
1487 	bool *use_one_row_for_frame;
1488 	double *dst_y_per_row_vblank;
1489 	double *dst_y_per_row_flip;
1490 	unsigned int *BytePerPixelY;
1491 	unsigned int *BytePerPixelC;
1492 	unsigned int *dpte_row_height;
1493 	unsigned int *dpte_row_height_chroma;
1494 	unsigned int *dpte_group_bytes;
1495 	unsigned int *PTERequestSizeY;
1496 	unsigned int *PTERequestSizeC;
1497 	unsigned int *PixelPTEReqWidthY;
1498 	unsigned int *PixelPTEReqHeightY;
1499 	unsigned int *PixelPTEReqWidthC;
1500 	unsigned int *PixelPTEReqHeightC;
1501 	unsigned int *dpte_row_width_luma_ub;
1502 	unsigned int *dpte_row_width_chroma_ub;
1503 	unsigned int *tdlut_groups_per_2row_ub;
1504 	bool mrq_present;
1505 	unsigned int MetaChunkSize;
1506 	unsigned int MinMetaChunkSizeBytes;
1507 	unsigned int *meta_row_width;
1508 	unsigned int *meta_row_width_chroma;
1509 	unsigned int *meta_row_height;
1510 	unsigned int *meta_row_height_chroma;
1511 	unsigned int *meta_req_width;
1512 	unsigned int *meta_req_width_chroma;
1513 	unsigned int *meta_req_height;
1514 	unsigned int *meta_req_height_chroma;
1515 
1516 	// Output
1517 	double *time_per_tdlut_group;
1518 	double *DST_Y_PER_PTE_ROW_NOM_L;
1519 	double *DST_Y_PER_PTE_ROW_NOM_C;
1520 	double *time_per_pte_group_nom_luma;
1521 	double *time_per_pte_group_vblank_luma;
1522 	double *time_per_pte_group_flip_luma;
1523 	double *time_per_pte_group_nom_chroma;
1524 	double *time_per_pte_group_vblank_chroma;
1525 	double *time_per_pte_group_flip_chroma;
1526 
1527 	double *DST_Y_PER_META_ROW_NOM_L;
1528 	double *DST_Y_PER_META_ROW_NOM_C;
1529 
1530 	double *TimePerMetaChunkNominal;
1531 	double *TimePerChromaMetaChunkNominal;
1532 	double *TimePerMetaChunkVBlank;
1533 	double *TimePerChromaMetaChunkVBlank;
1534 	double *TimePerMetaChunkFlip;
1535 	double *TimePerChromaMetaChunkFlip;
1536 };
1537 
1538 struct dml2_core_calcs_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_params {
1539 	const struct dml2_display_cfg *display_cfg;
1540 	bool USRRetrainingRequired;
1541 	unsigned int NumberOfActiveSurfaces;
1542 	unsigned int MaxLineBufferLines;
1543 	unsigned int LineBufferSize;
1544 	unsigned int WritebackInterfaceBufferSize;
1545 	double DCFCLK;
1546 	double ReturnBW;
1547 	bool SynchronizeTimings;
1548 	bool SynchronizeDRRDisplaysForUCLKPStateChange;
1549 	unsigned int *dpte_group_bytes;
1550 	struct dml2_core_internal_SOCParametersList mmSOCParameters;
1551 	unsigned int WritebackChunkSize;
1552 	double SOCCLK;
1553 	double DCFClkDeepSleep;
1554 	unsigned int *DETBufferSizeY;
1555 	unsigned int *DETBufferSizeC;
1556 	unsigned int *SwathHeightY;
1557 	unsigned int *SwathHeightC;
1558 	unsigned int *SwathWidthY;
1559 	unsigned int *SwathWidthC;
1560 	unsigned int *DPPPerSurface;
1561 	double *BytePerPixelDETY;
1562 	double *BytePerPixelDETC;
1563 	unsigned int *DSTXAfterScaler;
1564 	unsigned int *DSTYAfterScaler;
1565 	bool UnboundedRequestEnabled;
1566 	unsigned int CompressedBufferSizeInkByte;
1567 	bool max_oustanding_when_urgent_expected;
1568 	unsigned int max_outstanding_requests;
1569 	unsigned int max_request_size_bytes;
1570 	unsigned int *meta_row_height_l;
1571 	unsigned int *meta_row_height_c;
1572 
1573 	// Output
1574 	struct dml2_core_internal_watermarks *Watermark;
1575 	enum dml2_pstate_change_support *DRAMClockChangeSupport;
1576 	bool *global_dram_clock_change_supported;
1577 	double *MaxActiveDRAMClockChangeLatencySupported;
1578 	unsigned int *SubViewportLinesNeededInMALL;
1579 	enum dml2_pstate_change_support *FCLKChangeSupport;
1580 	bool *global_fclk_change_supported;
1581 	double *MaxActiveFCLKChangeLatencySupported;
1582 	bool *USRRetrainingSupport;
1583 	double *VActiveLatencyHidingMargin;
1584 	double *VActiveLatencyHidingUs;
1585 	bool *g6_temp_read_support;
1586 	bool *temp_read_or_ppt_support;
1587 };
1588 
1589 
1590 struct dml2_core_calcs_CalculateSwathAndDETConfiguration_params {
1591 	const struct dml2_display_cfg *display_cfg;
1592 	unsigned int ConfigReturnBufferSizeInKByte;
1593 	unsigned int MaxTotalDETInKByte;
1594 	unsigned int MinCompressedBufferSizeInKByte;
1595 	unsigned int rob_buffer_size_kbytes;
1596 	unsigned int pixel_chunk_size_kbytes;
1597 	bool ForceSingleDPP;
1598 	unsigned int NumberOfActiveSurfaces;
1599 	unsigned int nomDETInKByte;
1600 	unsigned int ConfigReturnBufferSegmentSizeInkByte;
1601 	unsigned int CompressedBufferSegmentSizeInkByte;
1602 	double *ReadBandwidthLuma;
1603 	double *ReadBandwidthChroma;
1604 	double *MaximumSwathWidthLuma;
1605 	double *MaximumSwathWidthChroma;
1606 	unsigned int *Read256BytesBlockHeightY;
1607 	unsigned int *Read256BytesBlockHeightC;
1608 	unsigned int *Read256BytesBlockWidthY;
1609 	unsigned int *Read256BytesBlockWidthC;
1610 	bool *surf_linear128_l;
1611 	bool *surf_linear128_c;
1612 	enum dml2_odm_mode *ODMMode;
1613 	unsigned int *BytePerPixY;
1614 	unsigned int *BytePerPixC;
1615 	double *BytePerPixDETY;
1616 	double *BytePerPixDETC;
1617 	unsigned int *DPPPerSurface;
1618 	bool mrq_present;
1619 
1620 	// output
1621 	unsigned int *req_per_swath_ub_l;
1622 	unsigned int *req_per_swath_ub_c;
1623 	unsigned int *swath_width_luma_ub;
1624 	unsigned int *swath_width_chroma_ub;
1625 	unsigned int *SwathWidth;
1626 	unsigned int *SwathWidthChroma;
1627 	unsigned int *SwathHeightY;
1628 	unsigned int *SwathHeightC;
1629 	unsigned int *request_size_bytes_luma;
1630 	unsigned int *request_size_bytes_chroma;
1631 	unsigned int *DETBufferSizeInKByte;
1632 	unsigned int *DETBufferSizeY;
1633 	unsigned int *DETBufferSizeC;
1634 	unsigned int *full_swath_bytes_l;
1635 	unsigned int *full_swath_bytes_c;
1636 	bool *UnboundedRequestEnabled;
1637 	unsigned int *compbuf_reserved_space_64b;
1638 	unsigned int *CompressedBufferSizeInkByte;
1639 	bool *ViewportSizeSupportPerSurface;
1640 	bool *ViewportSizeSupport;
1641 	bool *hw_debug5;
1642 
1643 	struct dml2_core_shared_calculation_funcs *funcs;
1644 };
1645 
1646 struct dml2_core_calcs_CalculateStutterEfficiency_locals {
1647 	double DETBufferingTimeY;
1648 	double SwathWidthYCriticalSurface;
1649 	double SwathHeightYCriticalSurface;
1650 	double VActiveTimeCriticalSurface;
1651 	double FrameTimeCriticalSurface;
1652 	unsigned int BytePerPixelYCriticalSurface;
1653 	unsigned int DETBufferSizeYCriticalSurface;
1654 	double MinTTUVBlankCriticalSurface;
1655 	unsigned int BlockWidth256BytesYCriticalSurface;
1656 	bool SinglePlaneCriticalSurface;
1657 	bool SinglePipeCriticalSurface;
1658 	double TotalCompressedReadBandwidth;
1659 	double TotalRowReadBandwidth;
1660 	double AverageDCCCompressionRate;
1661 	double EffectiveCompressedBufferSize;
1662 	double PartOfUncompressedPixelBurstThatFitsInROBAndCompressedBuffer;
1663 	double StutterBurstTime;
1664 	unsigned int TotalActiveWriteback;
1665 	double LinesInDETY;
1666 	double LinesInDETYRoundedDownToSwath;
1667 	double MaximumEffectiveCompressionLuma;
1668 	double MaximumEffectiveCompressionChroma;
1669 	double TotalZeroSizeRequestReadBandwidth;
1670 	double TotalZeroSizeCompressedReadBandwidth;
1671 	double AverageDCCZeroSizeFraction;
1672 	double AverageZeroSizeCompressionRate;
1673 	bool stream_visited[DML2_MAX_PLANES];
1674 };
1675 
1676 struct dml2_core_calcs_CalculateStutterEfficiency_params {
1677 	const struct dml2_display_cfg *display_cfg;
1678 	unsigned int CompressedBufferSizeInkByte;
1679 	bool UnboundedRequestEnabled;
1680 	unsigned int MetaFIFOSizeInKEntries;
1681 	unsigned int ZeroSizeBufferEntries;
1682 	unsigned int PixelChunkSizeInKByte;
1683 	unsigned int NumberOfActiveSurfaces;
1684 	unsigned int ROBBufferSizeInKByte;
1685 	double TotalDataReadBandwidth;
1686 	double DCFCLK;
1687 	double ReturnBW;
1688 	unsigned int CompbufReservedSpace64B;
1689 	unsigned int CompbufReservedSpaceZs;
1690 	bool hw_debug5;
1691 	double SRExitTime;
1692 	double SRExitZ8Time;
1693 	bool SynchronizeTimings;
1694 	double StutterEnterPlusExitWatermark;
1695 	double Z8StutterEnterPlusExitWatermark;
1696 	bool ProgressiveToInterlaceUnitInOPP;
1697 	double *MinTTUVBlank;
1698 	unsigned int *DPPPerSurface;
1699 	unsigned int *DETBufferSizeY;
1700 	unsigned int *BytePerPixelY;
1701 	double *BytePerPixelDETY;
1702 	unsigned int *SwathWidthY;
1703 	unsigned int *SwathHeightY;
1704 	unsigned int *SwathHeightC;
1705 	unsigned int *BlockHeight256BytesY;
1706 	unsigned int *BlockWidth256BytesY;
1707 	unsigned int *BlockHeight256BytesC;
1708 	unsigned int *BlockWidth256BytesC;
1709 	unsigned int *DCCYMaxUncompressedBlock;
1710 	unsigned int *DCCCMaxUncompressedBlock;
1711 	double *ReadBandwidthSurfaceLuma;
1712 	double *ReadBandwidthSurfaceChroma;
1713 	double *meta_row_bw;
1714 	double *dpte_row_bw;
1715 	bool rob_alloc_compressed;
1716 
1717 	// output
1718 	double *StutterEfficiencyNotIncludingVBlank;
1719 	double *StutterEfficiency;
1720 	unsigned int *NumberOfStutterBurstsPerFrame;
1721 	double *Z8StutterEfficiencyNotIncludingVBlank;
1722 	double *Z8StutterEfficiency;
1723 	unsigned int *Z8NumberOfStutterBurstsPerFrame;
1724 	double *StutterPeriod;
1725 	bool *DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE;
1726 };
1727 
1728 struct dml2_core_calcs_CalculatePrefetchSchedule_params {
1729 	const struct dml2_display_cfg *display_cfg;
1730 	double HostVMInefficiencyFactor;
1731 	struct dml2_core_internal_DmlPipe *myPipe;
1732 	unsigned int DSCDelay;
1733 	double DPPCLKDelaySubtotalPlusCNVCFormater;
1734 	double DPPCLKDelaySCL;
1735 	double DPPCLKDelaySCLLBOnly;
1736 	double DPPCLKDelayCNVCCursor;
1737 	double DISPCLKDelaySubtotal;
1738 	unsigned int DPP_RECOUT_WIDTH;
1739 	enum dml2_output_format_class OutputFormat;
1740 	unsigned int MaxInterDCNTileRepeaters;
1741 	unsigned int VStartup;
1742 	unsigned int HostVMMinPageSize;
1743 	bool DynamicMetadataEnable;
1744 	bool DynamicMetadataVMEnabled;
1745 	unsigned int DynamicMetadataLinesBeforeActiveRequired;
1746 	unsigned int DynamicMetadataTransmittedBytes;
1747 	double UrgentLatency;
1748 	double ExtraLatencyPrefetch;
1749 	double TCalc;
1750 	unsigned int vm_bytes;
1751 	unsigned int PixelPTEBytesPerRow;
1752 	double PrefetchSourceLinesY;
1753 	unsigned int VInitPreFillY;
1754 	unsigned int MaxNumSwathY;
1755 	double PrefetchSourceLinesC;
1756 	unsigned int VInitPreFillC;
1757 	unsigned int MaxNumSwathC;
1758 	unsigned int swath_width_luma_ub;  // per-pipe
1759 	unsigned int swath_width_chroma_ub; // per-pipe
1760 	unsigned int SwathHeightY;
1761 	unsigned int SwathHeightC;
1762 	double TWait;
1763 	double Ttrip;
1764 	double Turg;
1765 	bool setup_for_tdlut;
1766 	unsigned int tdlut_pte_bytes_per_frame;
1767 	unsigned int tdlut_bytes_per_frame;
1768 	double tdlut_opt_time;
1769 	double tdlut_drain_time;
1770 
1771 	unsigned int num_cursors;
1772 	unsigned int cursor_bytes_per_chunk;
1773 	unsigned int cursor_bytes_per_line;
1774 
1775 	// MRQ
1776 	bool dcc_enable;
1777 	bool mrq_present;
1778 	unsigned int meta_row_bytes;
1779 	double mall_prefetch_sdp_overhead_factor;
1780 
1781 	double impacted_dst_y_pre;
1782 	double vactive_sw_bw_l; // per surface bw
1783 	double vactive_sw_bw_c; // per surface bw
1784 
1785 	// output
1786 	unsigned int *DSTXAfterScaler;
1787 	unsigned int *DSTYAfterScaler;
1788 	double *dst_y_prefetch;
1789 	double *dst_y_per_vm_vblank;
1790 	double *dst_y_per_row_vblank;
1791 	double *VRatioPrefetchY;
1792 	double *VRatioPrefetchC;
1793 	double *RequiredPrefetchPixelDataBWLuma;
1794 	double *RequiredPrefetchPixelDataBWChroma;
1795 	bool *NotEnoughTimeForDynamicMetadata;
1796 	double *Tno_bw;
1797 	double *Tno_bw_flip;
1798 	double *prefetch_vmrow_bw;
1799 	double *Tdmdl_vm;
1800 	double *Tdmdl;
1801 	double *TSetup;
1802 	double *Tpre_rounded;
1803 	double *Tpre_oto;
1804 	double *Tvm_trips;
1805 	double *Tr0_trips;
1806 	double *Tvm_trips_flip;
1807 	double *Tr0_trips_flip;
1808 	double *Tvm_trips_flip_rounded;
1809 	double *Tr0_trips_flip_rounded;
1810 	unsigned int *VUpdateOffsetPix;
1811 	unsigned int *VUpdateWidthPix;
1812 	unsigned int *VReadyOffsetPix;
1813 	double *prefetch_cursor_bw;
1814 	double *prefetch_sw_bytes;
1815 	double *prefetch_swath_time_us;
1816 };
1817 
1818 struct dml2_core_calcs_CheckGlobalPrefetchAdmissibility_params {
1819 	unsigned int num_active_planes;
1820 	enum dml2_source_format_class *pixel_format;
1821 	unsigned int rob_buffer_size_kbytes;
1822 	unsigned int compressed_buffer_size_kbytes;
1823 	unsigned int chunk_bytes_l; // same for all planes
1824 	unsigned int chunk_bytes_c;
1825 	unsigned int *detile_buffer_size_bytes_l;
1826 	unsigned int *detile_buffer_size_bytes_c;
1827 	unsigned int *full_swath_bytes_l;
1828 	unsigned int *full_swath_bytes_c;
1829 	unsigned int *lb_source_lines_l;
1830 	unsigned int *lb_source_lines_c;
1831 	unsigned int *swath_height_l;
1832 	unsigned int *swath_height_c;
1833 	double *prefetch_sw_bytes;
1834 	double *Tpre_rounded;
1835 	double *Tpre_oto;
1836 	double estimated_dcfclk_mhz;
1837 	double estimated_urg_bandwidth_required_mbps;
1838 	double *line_time;
1839 	double *dst_y_prefetch;
1840 
1841 	// output
1842 	bool *recalc_prefetch_schedule;
1843 	double *impacted_dst_y_pre;
1844 };
1845 
1846 struct dml2_core_calcs_CheckGlobalPrefetchAdmissibility_locals {
1847 	unsigned int max_Trpd_dcfclk_cycles;
1848 	unsigned int burst_bytes_to_fill_det;
1849 	double time_to_fill_det_us;
1850 	unsigned int accumulated_return_path_dcfclk_cycles[DML2_MAX_PLANES];
1851 	bool prefetch_global_check_passed;
1852 	unsigned int src_swath_bytes_l[DML2_MAX_PLANES];
1853 	unsigned int src_swath_bytes_c[DML2_MAX_PLANES];
1854 	unsigned int src_detile_buf_size_bytes_l[DML2_MAX_PLANES];
1855 	unsigned int src_detile_buf_size_bytes_c[DML2_MAX_PLANES];
1856 };
1857 
1858 struct dml2_core_calcs_calculate_mcache_row_bytes_params {
1859 	unsigned int num_chans;
1860 	unsigned int mem_word_bytes;
1861 	unsigned int mcache_size_bytes;
1862 	unsigned int mcache_line_size_bytes;
1863 	unsigned int gpuvm_enable;
1864 	unsigned int gpuvm_page_size_kbytes;
1865 
1866 	//enum dml_rotation_angle rotation_angle;
1867 	bool surf_vert;
1868 	unsigned int vp_stationary;
1869 	unsigned int tiling_mode;
1870 	bool imall_enable;
1871 
1872 	unsigned int vp_start_x;
1873 	unsigned int vp_start_y;
1874 	unsigned int full_vp_width;
1875 	unsigned int full_vp_height;
1876 	unsigned int blk_width;
1877 	unsigned int blk_height;
1878 	unsigned int vmpg_width;
1879 	unsigned int vmpg_height;
1880 	unsigned int full_swath_bytes;
1881 	unsigned int bytes_per_pixel;
1882 
1883 	// output
1884 	unsigned int *num_mcaches;
1885 	unsigned int *mcache_row_bytes;
1886 	unsigned int *meta_row_width_ub;
1887 	double *dcc_dram_bw_nom_overhead_factor;
1888 	double *dcc_dram_bw_pref_overhead_factor;
1889 	unsigned int *mvmpg_width;
1890 	unsigned int *mvmpg_height;
1891 	unsigned int *full_vp_access_width_mvmpg_aligned;
1892 	unsigned int *mvmpg_per_mcache_lb;
1893 };
1894 
1895 struct dml2_core_shared_calculate_mcache_setting_locals {
1896 	struct dml2_core_calcs_calculate_mcache_row_bytes_params l_p;
1897 	struct dml2_core_calcs_calculate_mcache_row_bytes_params c_p;
1898 
1899 	bool is_dual_plane;
1900 	unsigned int mvmpg_width_l;
1901 	unsigned int mvmpg_height_l;
1902 	unsigned int full_vp_access_width_mvmpg_aligned_l;
1903 	unsigned int mvmpg_per_mcache_lb_l;
1904 	unsigned int meta_row_width_l;
1905 
1906 	unsigned int mvmpg_width_c;
1907 	unsigned int mvmpg_height_c;
1908 	unsigned int full_vp_access_width_mvmpg_aligned_c;
1909 	unsigned int mvmpg_per_mcache_lb_c;
1910 	unsigned int meta_row_width_c;
1911 
1912 	unsigned int lc_comb_last_mcache_size;
1913 	double luma_time_factor;
1914 	double mcache_remainder_l;
1915 	double mcache_remainder_c;
1916 	unsigned int mvmpg_access_width_l;
1917 	unsigned int mvmpg_access_width_c;
1918 	unsigned int avg_mcache_element_size_l;
1919 	unsigned int avg_mcache_element_size_c;
1920 
1921 	unsigned int full_vp_access_width_l;
1922 	unsigned int full_vp_access_width_c;
1923 };
1924 
1925 struct dml2_core_calcs_calculate_mcache_setting_params {
1926 	bool dcc_enable;
1927 	unsigned int num_chans;
1928 	unsigned int mem_word_bytes;
1929 	unsigned int mcache_size_bytes;
1930 	unsigned int mcache_line_size_bytes;
1931 	unsigned int gpuvm_enable;
1932 	unsigned int gpuvm_page_size_kbytes;
1933 
1934 	enum dml2_source_format_class source_format;
1935 	bool surf_vert;
1936 	unsigned int vp_stationary;
1937 	unsigned int tiling_mode;
1938 	bool imall_enable;
1939 
1940 	unsigned int vp_start_x_l;
1941 	unsigned int vp_start_y_l;
1942 	unsigned int full_vp_width_l;
1943 	unsigned int full_vp_height_l;
1944 	unsigned int blk_width_l;
1945 	unsigned int blk_height_l;
1946 	unsigned int vmpg_width_l;
1947 	unsigned int vmpg_height_l;
1948 	unsigned int full_swath_bytes_l;
1949 	unsigned int bytes_per_pixel_l;
1950 
1951 	unsigned int vp_start_x_c;
1952 	unsigned int vp_start_y_c;
1953 	unsigned int full_vp_width_c;
1954 	unsigned int full_vp_height_c;
1955 	unsigned int blk_width_c;
1956 	unsigned int blk_height_c;
1957 	unsigned int vmpg_width_c;
1958 	unsigned int vmpg_height_c;
1959 	unsigned int full_swath_bytes_c;
1960 	unsigned int bytes_per_pixel_c;
1961 
1962 	// output
1963 	unsigned int *num_mcaches_l;
1964 	unsigned int *mcache_row_bytes_l;
1965 	unsigned int *mcache_offsets_l;
1966 	unsigned int *mcache_shift_granularity_l;
1967 	double *dcc_dram_bw_nom_overhead_factor_l;
1968 	double *dcc_dram_bw_pref_overhead_factor_l;
1969 
1970 	unsigned int *num_mcaches_c;
1971 	unsigned int *mcache_row_bytes_c;
1972 	unsigned int *mcache_offsets_c;
1973 	unsigned int *mcache_shift_granularity_c;
1974 	double *dcc_dram_bw_nom_overhead_factor_c;
1975 	double *dcc_dram_bw_pref_overhead_factor_c;
1976 
1977 	bool *mall_comb_mcache_l;
1978 	bool *mall_comb_mcache_c;
1979 	bool *lc_comb_mcache;
1980 };
1981 
1982 struct dml2_core_calcs_calculate_tdlut_setting_params {
1983 	// input params
1984 	double dispclk_mhz;
1985 	bool setup_for_tdlut;
1986 	enum dml2_tdlut_width_mode tdlut_width_mode;
1987 	enum dml2_tdlut_addressing_mode tdlut_addressing_mode;
1988 	unsigned int cursor_buffer_size;
1989 	bool gpuvm_enable;
1990 	unsigned int gpuvm_page_size_kbytes;
1991 	bool is_gfx11;
1992 	bool tdlut_mpc_width_flag;
1993 
1994 	// output param
1995 	unsigned int *tdlut_pte_bytes_per_frame;
1996 	unsigned int *tdlut_bytes_per_frame;
1997 	unsigned int *tdlut_groups_per_2row_ub;
1998 	double *tdlut_opt_time;
1999 	double *tdlut_drain_time;
2000 	unsigned int *tdlut_bytes_to_deliver;
2001 	unsigned int *tdlut_bytes_per_group;
2002 };
2003 
2004 struct dml2_core_calcs_calculate_peak_bandwidth_required_params {
2005 	// output
2006 	double (*urg_vactive_bandwidth_required)[dml2_core_internal_bw_max];
2007 	double (*urg_bandwidth_required)[dml2_core_internal_bw_max];
2008 	double (*urg_bandwidth_required_qual)[dml2_core_internal_bw_max];
2009 	double (*non_urg_bandwidth_required)[dml2_core_internal_bw_max];
2010 	double (*surface_avg_vactive_required_bw)[dml2_core_internal_bw_max][DML2_MAX_PLANES];
2011 	double (*surface_peak_required_bw)[dml2_core_internal_bw_max][DML2_MAX_PLANES];
2012 
2013 	// input
2014 	const struct dml2_display_cfg *display_cfg;
2015 	bool inc_flip_bw;
2016 	unsigned int num_active_planes;
2017 	unsigned int *num_of_dpp;
2018 	double *dcc_dram_bw_nom_overhead_factor_p0;
2019 	double *dcc_dram_bw_nom_overhead_factor_p1;
2020 	double *dcc_dram_bw_pref_overhead_factor_p0;
2021 	double *dcc_dram_bw_pref_overhead_factor_p1;
2022 	double *mall_prefetch_sdp_overhead_factor;
2023 	double *mall_prefetch_dram_overhead_factor;
2024 	double *surface_read_bandwidth_l;
2025 	double *surface_read_bandwidth_c;
2026 	double *prefetch_bandwidth_l;
2027 	double *prefetch_bandwidth_c;
2028 	double *excess_vactive_fill_bw_l;
2029 	double *excess_vactive_fill_bw_c;
2030 	double *cursor_bw;
2031 	double *dpte_row_bw;
2032 	double *meta_row_bw;
2033 	double *prefetch_cursor_bw;
2034 	double *prefetch_vmrow_bw;
2035 	double *flip_bw;
2036 	double *urgent_burst_factor_l;
2037 	double *urgent_burst_factor_c;
2038 	double *urgent_burst_factor_cursor;
2039 	double *urgent_burst_factor_prefetch_l;
2040 	double *urgent_burst_factor_prefetch_c;
2041 	double *urgent_burst_factor_prefetch_cursor;
2042 };
2043 
2044 struct dml2_core_calcs_calculate_bytes_to_fetch_required_to_hide_latency_params {
2045 	/* inputs */
2046 	const struct dml2_display_cfg *display_cfg;
2047 	bool mrq_present;
2048 	unsigned int num_active_planes;
2049 	unsigned int *num_of_dpp;
2050 	unsigned int *meta_row_height_l;
2051 	unsigned int *meta_row_height_c;
2052 	unsigned int *meta_row_bytes_per_row_ub_l;
2053 	unsigned int *meta_row_bytes_per_row_ub_c;
2054 	unsigned int *dpte_row_height_l;
2055 	unsigned int *dpte_row_height_c;
2056 	unsigned int *dpte_bytes_per_row_l;
2057 	unsigned int *dpte_bytes_per_row_c;
2058 	unsigned int *byte_per_pix_l;
2059 	unsigned int *byte_per_pix_c;
2060 	unsigned int *swath_width_l;
2061 	unsigned int *swath_width_c;
2062 	unsigned int *swath_height_l;
2063 	unsigned int *swath_height_c;
2064 	double latency_to_hide_us;
2065 
2066 	/* outputs */
2067 	unsigned int *bytes_required_l;
2068 	unsigned int *bytes_required_c;
2069 };
2070 
2071 // A list of overridable function pointers in the core
2072 // shared calculation library.
2073 struct dml2_core_shared_calculation_funcs {
2074 	void (*calculate_det_buffer_size)(struct dml2_core_shared_calculate_det_buffer_size_params *p);
2075 };
2076 
2077 struct dml2_core_internal_scratch {
2078 	// Scratch space for function locals
2079 	struct dml2_core_calcs_mode_support_locals dml_core_mode_support_locals;
2080 	struct dml2_core_calcs_mode_programming_locals dml_core_mode_programming_locals;
2081 	struct dml2_core_calcs_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_locals CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_locals;
2082 	struct dml2_core_calcs_CalculateVMRowAndSwath_locals CalculateVMRowAndSwath_locals;
2083 	struct dml2_core_calcs_CalculatePrefetchSchedule_locals CalculatePrefetchSchedule_locals;
2084 	struct dml2_core_calcs_CheckGlobalPrefetchAdmissibility_locals CheckGlobalPrefetchAdmissibility_locals;
2085 	struct dml2_core_shared_CalculateSwathAndDETConfiguration_locals CalculateSwathAndDETConfiguration_locals;
2086 	struct dml2_core_shared_TruncToValidBPP_locals TruncToValidBPP_locals;
2087 	struct dml2_core_shared_CalculateDETBufferSize_locals CalculateDETBufferSize_locals;
2088 	struct dml2_core_shared_get_urgent_bandwidth_required_locals get_urgent_bandwidth_required_locals;
2089 	struct dml2_core_shared_calculate_peak_bandwidth_required_locals calculate_peak_bandwidth_required_locals;
2090 	struct dml2_core_shared_CalculateFlipSchedule_locals CalculateFlipSchedule_locals;
2091 	struct dml2_core_shared_rq_dlg_get_dlg_reg_locals rq_dlg_get_dlg_reg_locals;
2092 	struct dml2_core_calcs_CalculateStutterEfficiency_locals CalculateStutterEfficiency_locals;
2093 
2094 	// Scratch space for function params
2095 	struct dml2_core_calcs_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_params CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_params;
2096 	struct dml2_core_calcs_CalculateVMRowAndSwath_params CalculateVMRowAndSwath_params;
2097 	struct dml2_core_calcs_CalculateSwathAndDETConfiguration_params CalculateSwathAndDETConfiguration_params;
2098 	struct dml2_core_calcs_CalculateStutterEfficiency_params CalculateStutterEfficiency_params;
2099 	struct dml2_core_calcs_CalculatePrefetchSchedule_params CalculatePrefetchSchedule_params;
2100 	struct dml2_core_calcs_CheckGlobalPrefetchAdmissibility_params CheckGlobalPrefetchAdmissibility_params;
2101 	struct dml2_core_calcs_calculate_mcache_setting_params calculate_mcache_setting_params;
2102 	struct dml2_core_calcs_calculate_tdlut_setting_params calculate_tdlut_setting_params;
2103 	struct dml2_core_shared_calculate_vm_and_row_bytes_params calculate_vm_and_row_bytes_params;
2104 	struct dml2_core_shared_calculate_mcache_setting_locals calculate_mcache_setting_locals;
2105 	struct dml2_core_shared_CalculateMetaAndPTETimes_params CalculateMetaAndPTETimes_params;
2106 	struct dml2_core_calcs_calculate_peak_bandwidth_required_params calculate_peak_bandwidth_params;
2107 	struct dml2_core_calcs_calculate_bytes_to_fetch_required_to_hide_latency_params calculate_bytes_to_fetch_required_to_hide_latency_params;
2108 };
2109 
2110 //struct dml2_svp_mode_override;
2111 struct dml2_core_internal_display_mode_lib {
2112 	struct dml2_core_ip_params ip;
2113 	struct dml2_soc_bb soc;
2114 	struct dml2_ip_capabilities ip_caps;
2115 
2116 	//@brief Mode Support and Mode programming struct
2117 	// Used to hold input; intermediate and output of the calculations
2118 	struct dml2_core_internal_mode_support ms; // struct for mode support
2119 	struct dml2_core_internal_mode_program mp; // struct for mode programming
2120 	// Available overridable calculators for core_shared.
2121 	// if null, core_shared will use default calculators.
2122 	struct dml2_core_shared_calculation_funcs funcs;
2123 
2124 	struct dml2_core_internal_scratch scratch;
2125 };
2126 
2127 struct dml2_core_calcs_mode_support_ex {
2128 	struct dml2_core_internal_display_mode_lib *mode_lib;
2129 	const struct dml2_display_cfg *in_display_cfg;
2130 	const struct dml2_mcg_min_clock_table *min_clk_table;
2131 	int min_clk_index;
2132 	//unsigned int in_state_index;
2133 	struct dml2_core_internal_mode_support_info *out_evaluation_info;
2134 };
2135 
2136 struct core_display_cfg_support_info;
2137 
2138 struct dml2_core_calcs_mode_programming_ex {
2139 	struct dml2_core_internal_display_mode_lib *mode_lib;
2140 	const struct dml2_display_cfg *in_display_cfg;
2141 	const struct dml2_mcg_min_clock_table *min_clk_table;
2142 	const struct core_display_cfg_support_info *cfg_support_info;
2143 	int min_clk_index;
2144 	struct dml2_display_cfg_programming *programming;
2145 };
2146 
2147 #endif
2148