1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2006 Benno Rice.
5 * Copyright (C) 2007-2011 MARVELL INTERNATIONAL LTD.
6 * Copyright (c) 2012 Semihalf.
7 * All rights reserved.
8 *
9 * Developed by Semihalf.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 *
31 * from: FreeBSD: //depot/projects/arm/src/sys/arm/xscale/pxa2x0/pxa2x0_icu.c, rev 1
32 * from: FreeBSD: src/sys/arm/mv/ic.c,v 1.5 2011/02/08 01:49:30
33 */
34
35 #include <sys/cdefs.h>
36 #include "opt_platform.h"
37
38 #include <sys/param.h>
39 #include <sys/systm.h>
40 #include <sys/bus.h>
41 #include <sys/kernel.h>
42 #include <sys/cpuset.h>
43 #include <sys/ktr.h>
44 #include <sys/kdb.h>
45 #include <sys/module.h>
46 #include <sys/lock.h>
47 #include <sys/mutex.h>
48 #include <sys/rman.h>
49 #include <sys/proc.h>
50 #include <sys/smp.h>
51
52 #include <machine/bus.h>
53 #include <machine/intr.h>
54 #include <machine/smp.h>
55
56 #include <arm/mv/mvvar.h>
57 #include <arm/mv/mvreg.h>
58
59 #include <dev/ofw/ofw_bus.h>
60 #include <dev/ofw/ofw_bus_subr.h>
61 #include <dev/fdt/fdt_common.h>
62
63 #include "pic_if.h"
64
65 #ifdef DEBUG
66 #define debugf(fmt, args...) do { printf("%s(): ", __func__); \
67 printf(fmt,##args); } while (0)
68 #else
69 #define debugf(fmt, args...)
70 #endif
71
72 #define MPIC_INT_LOCAL 3
73 #define MPIC_INT_ERR 4
74 #define MPIC_INT_MSI 96
75
76 #define MPIC_IRQ_MASK 0x3ff
77
78 #define MPIC_CTRL 0x0
79 #define MPIC_SOFT_INT 0x4
80 #define MPIC_SOFT_INT_DRBL1 (1 << 5)
81 #define MPIC_ERR_CAUSE 0x20
82 #define MPIC_ISE 0x30
83 #define MPIC_ICE 0x34
84 #define MPIC_INT_CTL(irq) (0x100 + (irq)*4)
85
86 #define MPIC_INT_IRQ_FIQ_MASK(cpuid) (0x101 << (cpuid))
87 #define MPIC_CTRL_NIRQS(ctrl) (((ctrl) >> 2) & 0x3ff)
88
89 #define MPIC_IN_DRBL 0x08
90 #define MPIC_IN_DRBL_MASK 0x0c
91 #define MPIC_PPI_CAUSE 0x10
92 #define MPIC_CTP 0x40
93 #define MPIC_IIACK 0x44
94 #define MPIC_ISM 0x48
95 #define MPIC_ICM 0x4c
96 #define MPIC_ERR_MASK 0x50
97 #define MPIC_LOCAL_MASK 0x54
98 #define MPIC_CPU(n) (n) * 0x100
99
100 #define MPIC_PPI 32
101
102 struct mv_mpic_irqsrc {
103 struct intr_irqsrc mmi_isrc;
104 u_int mmi_irq;
105 };
106
107 struct mv_mpic_softc {
108 device_t sc_dev;
109 struct resource * mpic_res[4];
110 bus_space_tag_t mpic_bst;
111 bus_space_handle_t mpic_bsh;
112 bus_space_tag_t cpu_bst;
113 bus_space_handle_t cpu_bsh;
114 bus_space_tag_t drbl_bst;
115 bus_space_handle_t drbl_bsh;
116 struct mtx mtx;
117 struct mv_mpic_irqsrc * mpic_isrcs;
118 int nirqs;
119 void * intr_hand;
120 };
121
122 static struct resource_spec mv_mpic_spec[] = {
123 { SYS_RES_MEMORY, 0, RF_ACTIVE },
124 { SYS_RES_MEMORY, 1, RF_ACTIVE },
125 { SYS_RES_MEMORY, 2, RF_ACTIVE | RF_OPTIONAL },
126 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_OPTIONAL },
127 { -1, 0 }
128 };
129
130 static struct ofw_compat_data compat_data[] = {
131 {"mrvl,mpic", true},
132 {"marvell,mpic", true},
133 {NULL, false}
134 };
135
136 static struct mv_mpic_softc *mv_mpic_sc = NULL;
137
138 void mpic_send_ipi(int cpus, u_int ipi);
139
140 static int mv_mpic_probe(device_t);
141 static int mv_mpic_attach(device_t);
142 uint32_t mv_mpic_get_cause(void);
143 uint32_t mv_mpic_get_cause_err(void);
144 uint32_t mv_mpic_get_msi(void);
145 static void mpic_unmask_irq(uintptr_t nb);
146 static void mpic_mask_irq(uintptr_t nb);
147 static void mpic_mask_irq_err(uintptr_t nb);
148 static void mpic_unmask_irq_err(uintptr_t nb);
149 static boolean_t mpic_irq_is_percpu(uintptr_t);
150 static int mpic_intr(void *arg);
151 static void mpic_unmask_msi(void);
152 void mpic_ipi_send(device_t, struct intr_irqsrc*, cpuset_t, u_int);
153 int mpic_ipi_read(int);
154 void mpic_ipi_clear(int);
155
156 #define MPIC_WRITE(softc, reg, val) \
157 bus_space_write_4((softc)->mpic_bst, (softc)->mpic_bsh, (reg), (val))
158 #define MPIC_READ(softc, reg) \
159 bus_space_read_4((softc)->mpic_bst, (softc)->mpic_bsh, (reg))
160
161 #define MPIC_CPU_WRITE(softc, reg, val) \
162 bus_space_write_4((softc)->cpu_bst, (softc)->cpu_bsh, (reg), (val))
163 #define MPIC_CPU_READ(softc, reg) \
164 bus_space_read_4((softc)->cpu_bst, (softc)->cpu_bsh, (reg))
165
166 #define MPIC_DRBL_WRITE(softc, reg, val) \
167 bus_space_write_4((softc)->drbl_bst, (softc)->drbl_bsh, (reg), (val))
168 #define MPIC_DRBL_READ(softc, reg) \
169 bus_space_read_4((softc)->drbl_bst, (softc)->drbl_bsh, (reg))
170
171 static int
mv_mpic_probe(device_t dev)172 mv_mpic_probe(device_t dev)
173 {
174
175 if (!ofw_bus_status_okay(dev))
176 return (ENXIO);
177
178 if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data)
179 return (ENXIO);
180
181 device_set_desc(dev, "Marvell Integrated Interrupt Controller");
182 return (0);
183 }
184
185 static int
mv_mpic_register_isrcs(struct mv_mpic_softc * sc)186 mv_mpic_register_isrcs(struct mv_mpic_softc *sc)
187 {
188 int error;
189 uint32_t irq;
190 struct intr_irqsrc *isrc;
191 const char *name;
192
193 sc->mpic_isrcs = malloc(sc->nirqs * sizeof (*sc->mpic_isrcs), M_DEVBUF,
194 M_WAITOK | M_ZERO);
195
196 name = device_get_nameunit(sc->sc_dev);
197 for (irq = 0; irq < sc->nirqs; irq++) {
198 sc->mpic_isrcs[irq].mmi_irq = irq;
199
200 isrc = &sc->mpic_isrcs[irq].mmi_isrc;
201 if (irq < MPIC_PPI) {
202 error = intr_isrc_register(isrc, sc->sc_dev,
203 INTR_ISRCF_PPI, "%s", name);
204 } else {
205 error = intr_isrc_register(isrc, sc->sc_dev, 0, "%s",
206 name);
207 }
208 if (error != 0) {
209 /* XXX call intr_isrc_deregister() */
210 device_printf(sc->sc_dev, "%s failed", __func__);
211 return (error);
212 }
213 }
214 return (0);
215 }
216
217 static int
mv_mpic_attach(device_t dev)218 mv_mpic_attach(device_t dev)
219 {
220 struct mv_mpic_softc *sc;
221 int error;
222 uint32_t val;
223 int cpu;
224
225 sc = (struct mv_mpic_softc *)device_get_softc(dev);
226
227 if (mv_mpic_sc != NULL)
228 return (ENXIO);
229 mv_mpic_sc = sc;
230
231 sc->sc_dev = dev;
232
233 mtx_init(&sc->mtx, "MPIC lock", NULL, MTX_SPIN);
234
235 error = bus_alloc_resources(dev, mv_mpic_spec, sc->mpic_res);
236 if (error) {
237 device_printf(dev, "could not allocate resources\n");
238 return (ENXIO);
239 }
240 if (sc->mpic_res[3] == NULL)
241 device_printf(dev, "No interrupt to use.\n");
242 else
243 bus_setup_intr(dev, sc->mpic_res[3], INTR_TYPE_CLK,
244 mpic_intr, NULL, sc, &sc->intr_hand);
245
246 sc->mpic_bst = rman_get_bustag(sc->mpic_res[0]);
247 sc->mpic_bsh = rman_get_bushandle(sc->mpic_res[0]);
248
249 sc->cpu_bst = rman_get_bustag(sc->mpic_res[1]);
250 sc->cpu_bsh = rman_get_bushandle(sc->mpic_res[1]);
251
252 if (sc->mpic_res[2] != NULL) {
253 /* This is required only if MSIs are used. */
254 sc->drbl_bst = rman_get_bustag(sc->mpic_res[2]);
255 sc->drbl_bsh = rman_get_bushandle(sc->mpic_res[2]);
256 }
257
258 MPIC_WRITE(mv_mpic_sc, MPIC_CTRL, 1);
259 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_CTP, 0);
260
261 val = MPIC_READ(mv_mpic_sc, MPIC_CTRL);
262 sc->nirqs = MPIC_CTRL_NIRQS(val);
263
264 if (mv_mpic_register_isrcs(sc) != 0) {
265 device_printf(dev, "could not register PIC ISRCs\n");
266 bus_release_resources(dev, mv_mpic_spec, sc->mpic_res);
267 return (ENXIO);
268 }
269
270 OF_device_register_xref(OF_xref_from_node(ofw_bus_get_node(dev)), dev);
271
272 if (intr_pic_register(dev, OF_xref_from_device(dev)) == NULL) {
273 device_printf(dev, "could not register PIC\n");
274 bus_release_resources(dev, mv_mpic_spec, sc->mpic_res);
275 return (ENXIO);
276 }
277
278 mpic_unmask_msi();
279
280 /* Unmask CPU performance counters overflow irq */
281 for (cpu = 0; cpu < mp_ncpus; cpu++)
282 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_CPU(cpu) + MPIC_LOCAL_MASK,
283 (1 << cpu) | MPIC_CPU_READ(mv_mpic_sc,
284 MPIC_CPU(cpu) + MPIC_LOCAL_MASK));
285
286 return (0);
287 }
288
289 static int
mpic_intr(void * arg)290 mpic_intr(void *arg)
291 {
292 struct mv_mpic_softc *sc;
293 uint32_t cause, irqsrc;
294 unsigned int irq;
295 u_int cpuid;
296
297 sc = arg;
298 cpuid = PCPU_GET(cpuid);
299 irq = 0;
300
301 for (cause = MPIC_CPU_READ(sc, MPIC_PPI_CAUSE); cause > 0;
302 cause >>= 1, irq++) {
303 if (cause & 1) {
304 irqsrc = MPIC_READ(sc, MPIC_INT_CTL(irq));
305 if ((irqsrc & MPIC_INT_IRQ_FIQ_MASK(cpuid)) == 0)
306 continue;
307 if (intr_isrc_dispatch(&sc->mpic_isrcs[irq].mmi_isrc,
308 curthread->td_intr_frame) != 0) {
309 mpic_mask_irq(irq);
310 device_printf(sc->sc_dev, "Stray irq %u "
311 "disabled\n", irq);
312 }
313 }
314 }
315
316 return (FILTER_HANDLED);
317 }
318
319 static void
mpic_disable_intr(device_t dev,struct intr_irqsrc * isrc)320 mpic_disable_intr(device_t dev, struct intr_irqsrc *isrc)
321 {
322 u_int irq;
323
324 irq = ((struct mv_mpic_irqsrc *)isrc)->mmi_irq;
325 mpic_mask_irq(irq);
326 }
327
328 static void
mpic_enable_intr(device_t dev,struct intr_irqsrc * isrc)329 mpic_enable_intr(device_t dev, struct intr_irqsrc *isrc)
330 {
331 u_int irq;
332
333 irq = ((struct mv_mpic_irqsrc *)isrc)->mmi_irq;
334 mpic_unmask_irq(irq);
335 }
336
337 static int
mpic_map_intr(device_t dev,struct intr_map_data * data,struct intr_irqsrc ** isrcp)338 mpic_map_intr(device_t dev, struct intr_map_data *data,
339 struct intr_irqsrc **isrcp)
340 {
341 struct intr_map_data_fdt *daf;
342 struct mv_mpic_softc *sc;
343
344 if (data->type != INTR_MAP_DATA_FDT)
345 return (ENOTSUP);
346
347 sc = device_get_softc(dev);
348 daf = (struct intr_map_data_fdt *)data;
349
350 if (daf->ncells !=1 || daf->cells[0] >= sc->nirqs)
351 return (EINVAL);
352
353 *isrcp = &sc->mpic_isrcs[daf->cells[0]].mmi_isrc;
354 return (0);
355 }
356
357 static void
mpic_pre_ithread(device_t dev,struct intr_irqsrc * isrc)358 mpic_pre_ithread(device_t dev, struct intr_irqsrc *isrc)
359 {
360
361 mpic_disable_intr(dev, isrc);
362 }
363
364 static void
mpic_post_ithread(device_t dev,struct intr_irqsrc * isrc)365 mpic_post_ithread(device_t dev, struct intr_irqsrc *isrc)
366 {
367
368 mpic_enable_intr(dev, isrc);
369 }
370
371 static void
mpic_post_filter(device_t dev,struct intr_irqsrc * isrc)372 mpic_post_filter(device_t dev, struct intr_irqsrc *isrc)
373 {
374 }
375
376 static device_method_t mv_mpic_methods[] = {
377 DEVMETHOD(device_probe, mv_mpic_probe),
378 DEVMETHOD(device_attach, mv_mpic_attach),
379
380 DEVMETHOD(pic_disable_intr, mpic_disable_intr),
381 DEVMETHOD(pic_enable_intr, mpic_enable_intr),
382 DEVMETHOD(pic_map_intr, mpic_map_intr),
383 DEVMETHOD(pic_post_filter, mpic_post_filter),
384 DEVMETHOD(pic_post_ithread, mpic_post_ithread),
385 DEVMETHOD(pic_pre_ithread, mpic_pre_ithread),
386 DEVMETHOD(pic_ipi_send, mpic_ipi_send),
387 { 0, 0 }
388 };
389
390 static driver_t mv_mpic_driver = {
391 "mpic",
392 mv_mpic_methods,
393 sizeof(struct mv_mpic_softc),
394 };
395
396 EARLY_DRIVER_MODULE(mpic, simplebus, mv_mpic_driver, 0, 0,
397 BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE);
398
399 static void
mpic_unmask_msi(void)400 mpic_unmask_msi(void)
401 {
402
403 mpic_unmask_irq(MPIC_INT_MSI);
404 }
405
406 static void
mpic_unmask_irq_err(uintptr_t nb)407 mpic_unmask_irq_err(uintptr_t nb)
408 {
409 uint32_t mask;
410 uint8_t bit_off;
411
412 MPIC_WRITE(mv_mpic_sc, MPIC_ISE, MPIC_INT_ERR);
413 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ICM, MPIC_INT_ERR);
414
415 bit_off = nb - ERR_IRQ;
416 mask = MPIC_CPU_READ(mv_mpic_sc, MPIC_ERR_MASK);
417 mask |= (1 << bit_off);
418 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ERR_MASK, mask);
419 }
420
421 static void
mpic_mask_irq_err(uintptr_t nb)422 mpic_mask_irq_err(uintptr_t nb)
423 {
424 uint32_t mask;
425 uint8_t bit_off;
426
427 bit_off = nb - ERR_IRQ;
428 mask = MPIC_CPU_READ(mv_mpic_sc, MPIC_ERR_MASK);
429 mask &= ~(1 << bit_off);
430 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ERR_MASK, mask);
431 }
432
433 static boolean_t
mpic_irq_is_percpu(uintptr_t nb)434 mpic_irq_is_percpu(uintptr_t nb)
435 {
436 if (nb < MPIC_PPI)
437 return TRUE;
438
439 return FALSE;
440 }
441
442 static void
mpic_unmask_irq(uintptr_t nb)443 mpic_unmask_irq(uintptr_t nb)
444 {
445
446 #ifdef SMP
447 int cpu;
448
449 if (nb == MPIC_INT_LOCAL) {
450 for (cpu = 0; cpu < mp_ncpus; cpu++)
451 MPIC_CPU_WRITE(mv_mpic_sc,
452 MPIC_CPU(cpu) + MPIC_ICM, nb);
453 return;
454 }
455 #endif
456 if (mpic_irq_is_percpu(nb))
457 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ICM, nb);
458 else if (nb < ERR_IRQ)
459 MPIC_WRITE(mv_mpic_sc, MPIC_ISE, nb);
460 else if (nb < MSI_IRQ)
461 mpic_unmask_irq_err(nb);
462
463 if (nb == 0)
464 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_IN_DRBL_MASK, 0xffffffff);
465 }
466
467 static void
mpic_mask_irq(uintptr_t nb)468 mpic_mask_irq(uintptr_t nb)
469 {
470
471 #ifdef SMP
472 int cpu;
473
474 if (nb == MPIC_INT_LOCAL) {
475 for (cpu = 0; cpu < mp_ncpus; cpu++)
476 MPIC_CPU_WRITE(mv_mpic_sc,
477 MPIC_CPU(cpu) + MPIC_ISM, nb);
478 return;
479 }
480 #endif
481 if (mpic_irq_is_percpu(nb))
482 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ISM, nb);
483 else if (nb < ERR_IRQ)
484 MPIC_WRITE(mv_mpic_sc, MPIC_ICE, nb);
485 else if (nb < MSI_IRQ)
486 mpic_mask_irq_err(nb);
487 }
488
489 uint32_t
mv_mpic_get_cause(void)490 mv_mpic_get_cause(void)
491 {
492
493 return (MPIC_CPU_READ(mv_mpic_sc, MPIC_IIACK));
494 }
495
496 uint32_t
mv_mpic_get_cause_err(void)497 mv_mpic_get_cause_err(void)
498 {
499 uint32_t err_cause;
500 uint8_t bit_off;
501
502 err_cause = MPIC_READ(mv_mpic_sc, MPIC_ERR_CAUSE);
503
504 if (err_cause)
505 bit_off = ffs(err_cause) - 1;
506 else
507 return (-1);
508
509 debugf("%s: irq:%x cause:%x\n", __func__, bit_off, err_cause);
510 return (ERR_IRQ + bit_off);
511 }
512
513 uint32_t
mv_mpic_get_msi(void)514 mv_mpic_get_msi(void)
515 {
516 uint32_t cause;
517 uint8_t bit_off;
518
519 KASSERT(mv_mpic_sc->drbl_bst != NULL, ("No doorbell in mv_mpic_get_msi"));
520 cause = MPIC_DRBL_READ(mv_mpic_sc, 0);
521
522 if (cause)
523 bit_off = ffs(cause) - 1;
524 else
525 return (-1);
526
527 debugf("%s: irq:%x cause:%x\n", __func__, bit_off, cause);
528
529 cause &= ~(1 << bit_off);
530 MPIC_DRBL_WRITE(mv_mpic_sc, 0, cause);
531
532 return (MSI_IRQ + bit_off);
533 }
534
535 int
mv_msi_data(int irq,uint64_t * addr,uint32_t * data)536 mv_msi_data(int irq, uint64_t *addr, uint32_t *data)
537 {
538 u_long phys, base, size;
539 phandle_t node;
540 int error;
541
542 node = ofw_bus_get_node(mv_mpic_sc->sc_dev);
543
544 /* Get physical address of register space */
545 error = fdt_get_range(OF_parent(node), 0, &phys, &size);
546 if (error) {
547 printf("%s: Cannot get register physical address, err:%d",
548 __func__, error);
549 return (error);
550 }
551
552 /* Get offset of MPIC register space */
553 error = fdt_regsize(node, &base, &size);
554 if (error) {
555 printf("%s: Cannot get MPIC register offset, err:%d",
556 __func__, error);
557 return (error);
558 }
559
560 *addr = phys + base + MPIC_SOFT_INT;
561 *data = MPIC_SOFT_INT_DRBL1 | irq;
562
563 return (0);
564 }
565
566 void
mpic_ipi_send(device_t dev,struct intr_irqsrc * isrc,cpuset_t cpus,u_int ipi)567 mpic_ipi_send(device_t dev, struct intr_irqsrc *isrc, cpuset_t cpus, u_int ipi)
568 {
569 uint32_t val, i;
570
571 val = 0x00000000;
572 for (i = 0; i < MAXCPU; i++)
573 if (CPU_ISSET(i, &cpus))
574 val |= (1 << (8 + i));
575 val |= ipi;
576 MPIC_WRITE(mv_mpic_sc, MPIC_SOFT_INT, val);
577 }
578
579 int
mpic_ipi_read(int i __unused)580 mpic_ipi_read(int i __unused)
581 {
582 uint32_t val;
583 int ipi;
584
585 val = MPIC_CPU_READ(mv_mpic_sc, MPIC_IN_DRBL);
586 if (val) {
587 ipi = ffs(val) - 1;
588 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_IN_DRBL, ~(1 << ipi));
589 return (ipi);
590 }
591
592 return (0x3ff);
593 }
594
595 void
mpic_ipi_clear(int ipi)596 mpic_ipi_clear(int ipi)
597 {
598 }
599