1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2006 Benno Rice.
5 * Copyright (C) 2007-2008 MARVELL INTERNATIONAL LTD.
6 * All rights reserved.
7 *
8 * Adapted to Marvell SoC by Semihalf.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 *
30 * from: FreeBSD: //depot/projects/arm/src/sys/arm/xscale/pxa2x0/pxa2x0_timer.c, rev 1
31 */
32
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/bus.h>
36 #include <sys/eventhandler.h>
37 #include <sys/kernel.h>
38 #include <sys/module.h>
39 #include <sys/malloc.h>
40 #include <sys/rman.h>
41 #include <sys/timeet.h>
42 #include <sys/timetc.h>
43 #include <sys/watchdog.h>
44 #include <machine/bus.h>
45 #include <machine/cpu.h>
46 #include <machine/intr.h>
47 #include <machine/machdep.h>
48
49 #include <arm/mv/mvreg.h>
50 #include <arm/mv/mvvar.h>
51
52 #include <dev/ofw/ofw_bus.h>
53 #include <dev/ofw/ofw_bus_subr.h>
54
55 #define INITIAL_TIMECOUNTER (0xffffffff)
56 #define MAX_WATCHDOG_TICKS (0xffffffff)
57
58 #define MV_TMR 0x1
59 #define MV_WDT 0x2
60 #define MV_NONE 0x0
61
62 #define MV_CLOCK_SRC_ARMV7 25000000 /* Timers' 25MHz mode */
63
64 #define WATCHDOG_TIMER_ARMV5 2
65
66 typedef void (*mv_watchdog_enable_t)(void);
67 typedef void (*mv_watchdog_disable_t)(void);
68
69 struct mv_timer_config {
70 enum soc_family soc_family;
71 mv_watchdog_enable_t watchdog_enable;
72 mv_watchdog_disable_t watchdog_disable;
73 unsigned int clock_src;
74 uint32_t bridge_irq_cause;
75 uint32_t irq_timer0_clr;
76 uint32_t irq_timer_wd_clr;
77 };
78
79 struct mv_timer_softc {
80 struct resource * timer_res[2];
81 bus_space_tag_t timer_bst;
82 bus_space_handle_t timer_bsh;
83 struct mtx timer_mtx;
84 struct eventtimer et;
85 boolean_t has_wdt;
86 struct mv_timer_config* config;
87 };
88
89 static struct resource_spec mv_timer_spec[] = {
90 { SYS_RES_MEMORY, 0, RF_ACTIVE },
91 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_OPTIONAL },
92 { -1, 0 }
93 };
94
95 /* Interrupt is not required by MV_WDT devices */
96 static struct ofw_compat_data mv_timer_compat[] = {
97 {"marvell,armada-380-timer", MV_NONE },
98 {"marvell,armada-xp-timer", MV_TMR | MV_WDT },
99 {"mrvl,timer", MV_TMR | MV_WDT },
100 {NULL, MV_NONE }
101 };
102
103 static struct mv_timer_softc *timer_softc = NULL;
104 static int timers_initialized = 0;
105
106 static int mv_timer_probe(device_t);
107 static int mv_timer_attach(device_t);
108
109 static int mv_hardclock(void *);
110 static unsigned mv_timer_get_timecount(struct timecounter *);
111
112 static uint32_t mv_get_timer_control(void);
113 static void mv_set_timer_control(uint32_t);
114 static uint32_t mv_get_timer(uint32_t);
115 static void mv_set_timer(uint32_t, uint32_t);
116 static void mv_set_timer_rel(uint32_t, uint32_t);
117 static void mv_watchdog_event(void *, unsigned int, int *);
118 static int mv_timer_start(struct eventtimer *et,
119 sbintime_t first, sbintime_t period);
120 static int mv_timer_stop(struct eventtimer *et);
121 static void mv_setup_timers(void);
122
123 static void mv_watchdog_enable_armv5(void);
124 static void mv_watchdog_enable_armadaxp(void);
125 static void mv_watchdog_disable_armv5(void);
126 static void mv_watchdog_disable_armadaxp(void);
127
128 static void mv_delay(int usec, void* arg);
129
130 static struct mv_timer_config timer_armadaxp_config =
131 {
132 MV_SOC_ARMADA_XP,
133 &mv_watchdog_enable_armadaxp,
134 &mv_watchdog_disable_armadaxp,
135 MV_CLOCK_SRC_ARMV7,
136 BRIDGE_IRQ_CAUSE_ARMADAXP,
137 IRQ_TIMER0_CLR_ARMADAXP,
138 IRQ_TIMER_WD_CLR_ARMADAXP,
139 };
140 static struct mv_timer_config timer_armv5_config =
141 {
142 MV_SOC_ARMV5,
143 &mv_watchdog_enable_armv5,
144 &mv_watchdog_disable_armv5,
145 0,
146 BRIDGE_IRQ_CAUSE,
147 IRQ_TIMER0_CLR,
148 IRQ_TIMER_WD_CLR,
149 };
150
151 static struct ofw_compat_data mv_timer_soc_config[] = {
152 {"marvell,armada-xp-timer", (uintptr_t)&timer_armadaxp_config },
153 {"mrvl,timer", (uintptr_t)&timer_armv5_config },
154 {NULL, (uintptr_t)NULL },
155 };
156
157 static struct timecounter mv_timer_timecounter = {
158 .tc_get_timecount = mv_timer_get_timecount,
159 .tc_name = "CPUTimer1",
160 .tc_frequency = 0, /* This is assigned on the fly in the init sequence */
161 .tc_counter_mask = ~0u,
162 .tc_quality = 1000,
163 };
164
165 static int
mv_timer_probe(device_t dev)166 mv_timer_probe(device_t dev)
167 {
168
169 if (!ofw_bus_status_okay(dev))
170 return (ENXIO);
171
172 if (ofw_bus_search_compatible(dev, mv_timer_compat)->ocd_data == MV_NONE)
173 return (ENXIO);
174
175 device_set_desc(dev, "Marvell CPU Timer");
176 return (0);
177 }
178
179 static int
mv_timer_attach(device_t dev)180 mv_timer_attach(device_t dev)
181 {
182 int error;
183 void *ihl;
184 struct mv_timer_softc *sc;
185 uint32_t irq_cause, irq_mask;
186
187 if (timer_softc != NULL)
188 return (ENXIO);
189
190 sc = (struct mv_timer_softc *)device_get_softc(dev);
191 timer_softc = sc;
192
193 sc->config = (struct mv_timer_config*)
194 ofw_bus_search_compatible(dev, mv_timer_soc_config)->ocd_data;
195
196 if (sc->config->clock_src == 0)
197 sc->config->clock_src = get_tclk();
198
199 error = bus_alloc_resources(dev, mv_timer_spec, sc->timer_res);
200 if (error) {
201 device_printf(dev, "could not allocate resources\n");
202 return (ENXIO);
203 }
204
205 sc->timer_bst = rman_get_bustag(sc->timer_res[0]);
206 sc->timer_bsh = rman_get_bushandle(sc->timer_res[0]);
207
208 sc->has_wdt = ofw_bus_has_prop(dev, "mrvl,has-wdt");
209
210 mtx_init(&timer_softc->timer_mtx, "watchdog", NULL, MTX_DEF);
211
212 if (sc->has_wdt) {
213 if (sc->config->watchdog_disable)
214 sc->config->watchdog_disable();
215 EVENTHANDLER_REGISTER(watchdog_list, mv_watchdog_event, sc, 0);
216 }
217
218 if (ofw_bus_search_compatible(dev, mv_timer_compat)->ocd_data
219 == MV_WDT) {
220 /* Don't set timers for wdt-only entry. */
221 device_printf(dev, "only watchdog attached\n");
222 return (0);
223 } else if (sc->timer_res[1] == NULL) {
224 device_printf(dev, "no interrupt resource\n");
225 bus_release_resources(dev, mv_timer_spec, sc->timer_res);
226 return (ENXIO);
227 }
228
229 if (bus_setup_intr(dev, sc->timer_res[1], INTR_TYPE_CLK,
230 mv_hardclock, NULL, sc, &ihl) != 0) {
231 bus_release_resources(dev, mv_timer_spec, sc->timer_res);
232 device_printf(dev, "Could not setup interrupt.\n");
233 return (ENXIO);
234 }
235
236 mv_setup_timers();
237 if (sc->config->soc_family != MV_SOC_ARMADA_XP ) {
238 irq_cause = read_cpu_ctrl(sc->config->bridge_irq_cause);
239 irq_cause &= sc->config->irq_timer0_clr;
240
241 write_cpu_ctrl(sc->config->bridge_irq_cause, irq_cause);
242 irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK);
243 irq_mask |= IRQ_TIMER0_MASK;
244 irq_mask &= ~IRQ_TIMER1_MASK;
245 write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask);
246 }
247 sc->et.et_name = "CPUTimer0";
248 sc->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT;
249 sc->et.et_quality = 1000;
250
251 sc->et.et_frequency = sc->config->clock_src;
252 sc->et.et_min_period = (0x00000002LLU << 32) / sc->et.et_frequency;
253 sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency;
254 sc->et.et_start = mv_timer_start;
255 sc->et.et_stop = mv_timer_stop;
256 sc->et.et_priv = sc;
257 et_register(&sc->et);
258 mv_timer_timecounter.tc_frequency = sc->config->clock_src;
259 tc_init(&mv_timer_timecounter);
260
261 #ifdef PLATFORM
262 arm_set_delay(mv_delay, NULL);
263 #endif
264 return (0);
265 }
266
267 static int
mv_hardclock(void * arg)268 mv_hardclock(void *arg)
269 {
270 struct mv_timer_softc *sc;
271 uint32_t irq_cause;
272
273 irq_cause = read_cpu_ctrl(timer_softc->config->bridge_irq_cause);
274 irq_cause &= timer_softc->config->irq_timer0_clr;
275 write_cpu_ctrl(timer_softc->config->bridge_irq_cause, irq_cause);
276
277 sc = (struct mv_timer_softc *)arg;
278 if (sc->et.et_active)
279 sc->et.et_event_cb(&sc->et, sc->et.et_arg);
280
281 return (FILTER_HANDLED);
282 }
283
284 static device_method_t mv_timer_methods[] = {
285 DEVMETHOD(device_probe, mv_timer_probe),
286 DEVMETHOD(device_attach, mv_timer_attach),
287 { 0, 0 }
288 };
289
290 static driver_t mv_timer_driver = {
291 "timer",
292 mv_timer_methods,
293 sizeof(struct mv_timer_softc),
294 };
295
296 DRIVER_MODULE(timer_mv, simplebus, mv_timer_driver, 0, 0);
297
298 static unsigned
mv_timer_get_timecount(struct timecounter * tc)299 mv_timer_get_timecount(struct timecounter *tc)
300 {
301
302 return (INITIAL_TIMECOUNTER - mv_get_timer(1));
303 }
304
305 static void
mv_delay(int usec,void * arg)306 mv_delay(int usec, void* arg)
307 {
308 uint32_t val, val_temp;
309 int32_t nticks;
310
311 val = mv_get_timer(1);
312 nticks = ((timer_softc->config->clock_src / 1000000 + 1) * usec);
313
314 while (nticks > 0) {
315 val_temp = mv_get_timer(1);
316 if (val > val_temp)
317 nticks -= (val - val_temp);
318 else
319 nticks -= (val + (INITIAL_TIMECOUNTER - val_temp));
320
321 val = val_temp;
322 }
323 }
324
325 #ifndef PLATFORM
326 void
DELAY(int usec)327 DELAY(int usec)
328 {
329 uint32_t val;
330
331 if (!timers_initialized) {
332 for (; usec > 0; usec--)
333 for (val = 100; val > 0; val--)
334 __asm __volatile("nop" ::: "memory");
335 } else {
336 TSENTER();
337 mv_delay(usec, NULL);
338 TSEXIT();
339 }
340 }
341 #endif
342
343 static uint32_t
mv_get_timer_control(void)344 mv_get_timer_control(void)
345 {
346
347 return (bus_space_read_4(timer_softc->timer_bst,
348 timer_softc->timer_bsh, CPU_TIMER_CONTROL));
349 }
350
351 static void
mv_set_timer_control(uint32_t val)352 mv_set_timer_control(uint32_t val)
353 {
354
355 bus_space_write_4(timer_softc->timer_bst,
356 timer_softc->timer_bsh, CPU_TIMER_CONTROL, val);
357 }
358
359 static uint32_t
mv_get_timer(uint32_t timer)360 mv_get_timer(uint32_t timer)
361 {
362
363 return (bus_space_read_4(timer_softc->timer_bst,
364 timer_softc->timer_bsh, CPU_TIMER0 + timer * 0x8));
365 }
366
367 static void
mv_set_timer(uint32_t timer,uint32_t val)368 mv_set_timer(uint32_t timer, uint32_t val)
369 {
370
371 bus_space_write_4(timer_softc->timer_bst,
372 timer_softc->timer_bsh, CPU_TIMER0 + timer * 0x8, val);
373 }
374
375 static void
mv_set_timer_rel(uint32_t timer,uint32_t val)376 mv_set_timer_rel(uint32_t timer, uint32_t val)
377 {
378
379 bus_space_write_4(timer_softc->timer_bst,
380 timer_softc->timer_bsh, CPU_TIMER0_REL + timer * 0x8, val);
381 }
382
383 static void
mv_watchdog_enable_armv5(void)384 mv_watchdog_enable_armv5(void)
385 {
386 uint32_t val, irq_cause, irq_mask;
387
388 irq_cause = read_cpu_ctrl(timer_softc->config->bridge_irq_cause);
389 irq_cause &= timer_softc->config->irq_timer_wd_clr;
390 write_cpu_ctrl(timer_softc->config->bridge_irq_cause, irq_cause);
391
392 irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK);
393 irq_mask |= IRQ_TIMER_WD_MASK;
394 write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask);
395
396 val = read_cpu_ctrl(RSTOUTn_MASK);
397 val |= WD_RST_OUT_EN;
398 write_cpu_ctrl(RSTOUTn_MASK, val);
399
400 val = mv_get_timer_control();
401 val |= CPU_TIMER2_EN | CPU_TIMER2_AUTO;
402 mv_set_timer_control(val);
403 }
404
405 static void
mv_watchdog_enable_armadaxp(void)406 mv_watchdog_enable_armadaxp(void)
407 {
408 uint32_t irq_cause, val;
409
410 irq_cause = read_cpu_ctrl(timer_softc->config->bridge_irq_cause);
411 irq_cause &= timer_softc->config->irq_timer_wd_clr;
412 write_cpu_ctrl(timer_softc->config->bridge_irq_cause, irq_cause);
413
414 val = read_cpu_mp_clocks(WD_RSTOUTn_MASK);
415 val |= (WD_GLOBAL_MASK | WD_CPU0_MASK);
416 write_cpu_mp_clocks(WD_RSTOUTn_MASK, val);
417
418 val = read_cpu_misc(RSTOUTn_MASK_ARMV7);
419 val &= ~RSTOUTn_MASK_WD;
420 write_cpu_misc(RSTOUTn_MASK_ARMV7, val);
421
422 val = mv_get_timer_control();
423 val |= CPU_TIMER2_EN | CPU_TIMER2_AUTO | CPU_TIMER_WD_25MHZ_EN;
424 mv_set_timer_control(val);
425 }
426
427 static void
mv_watchdog_disable_armv5(void)428 mv_watchdog_disable_armv5(void)
429 {
430 uint32_t val, irq_cause,irq_mask;
431
432 val = mv_get_timer_control();
433 val &= ~(CPU_TIMER2_EN | CPU_TIMER2_AUTO);
434 mv_set_timer_control(val);
435
436 val = read_cpu_ctrl(RSTOUTn_MASK);
437 val &= ~WD_RST_OUT_EN;
438 write_cpu_ctrl(RSTOUTn_MASK, val);
439
440 irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK);
441 irq_mask &= ~(IRQ_TIMER_WD_MASK);
442 write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask);
443
444 irq_cause = read_cpu_ctrl(timer_softc->config->bridge_irq_cause);
445 irq_cause &= timer_softc->config->irq_timer_wd_clr;
446 write_cpu_ctrl(timer_softc->config->bridge_irq_cause, irq_cause);
447 }
448
449 static void
mv_watchdog_disable_armadaxp(void)450 mv_watchdog_disable_armadaxp(void)
451 {
452 uint32_t val, irq_cause;
453
454 val = read_cpu_mp_clocks(WD_RSTOUTn_MASK);
455 val &= ~(WD_GLOBAL_MASK | WD_CPU0_MASK);
456 write_cpu_mp_clocks(WD_RSTOUTn_MASK, val);
457
458 val = read_cpu_misc(RSTOUTn_MASK_ARMV7);
459 val |= RSTOUTn_MASK_WD;
460 write_cpu_misc(RSTOUTn_MASK_ARMV7, RSTOUTn_MASK_WD);
461
462 irq_cause = read_cpu_ctrl(timer_softc->config->bridge_irq_cause);
463 irq_cause &= timer_softc->config->irq_timer_wd_clr;
464 write_cpu_ctrl(timer_softc->config->bridge_irq_cause, irq_cause);
465
466 val = mv_get_timer_control();
467 val &= ~(CPU_TIMER2_EN | CPU_TIMER2_AUTO);
468 mv_set_timer_control(val);
469 }
470
471 /*
472 * Watchdog event handler.
473 */
474 static void
mv_watchdog_event(void * arg,unsigned int cmd,int * error)475 mv_watchdog_event(void *arg, unsigned int cmd, int *error)
476 {
477 uint64_t ns;
478 uint64_t ticks;
479
480 mtx_lock(&timer_softc->timer_mtx);
481 if (cmd == 0) {
482 if (timer_softc->config->watchdog_disable != NULL)
483 timer_softc->config->watchdog_disable();
484 } else {
485 /*
486 * Watchdog timeout is in nanosecs, calculation according to
487 * watchdog(9)
488 */
489 ns = (uint64_t)1 << (cmd & WD_INTERVAL);
490 ticks = (uint64_t)(ns * timer_softc->config->clock_src) / 1000000000;
491 if (ticks > MAX_WATCHDOG_TICKS) {
492 if (timer_softc->config->watchdog_disable != NULL)
493 timer_softc->config->watchdog_disable();
494 } else {
495 mv_set_timer(WATCHDOG_TIMER_ARMV5, ticks);
496 if (timer_softc->config->watchdog_enable != NULL)
497 timer_softc->config->watchdog_enable();
498 *error = 0;
499 }
500 }
501 mtx_unlock(&timer_softc->timer_mtx);
502 }
503
504 static int
mv_timer_start(struct eventtimer * et,sbintime_t first,sbintime_t period)505 mv_timer_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
506 {
507 struct mv_timer_softc *sc;
508 uint32_t val, val1;
509
510 /* Calculate dividers. */
511 sc = (struct mv_timer_softc *)et->et_priv;
512 if (period != 0)
513 val = ((uint32_t)sc->et.et_frequency * period) >> 32;
514 else
515 val = 0;
516 if (first != 0)
517 val1 = ((uint32_t)sc->et.et_frequency * first) >> 32;
518 else
519 val1 = val;
520
521 /* Apply configuration. */
522 mv_set_timer_rel(0, val);
523 mv_set_timer(0, val1);
524 val = mv_get_timer_control();
525 val |= CPU_TIMER0_EN;
526 if (period != 0)
527 val |= CPU_TIMER0_AUTO;
528 else
529 val &= ~CPU_TIMER0_AUTO;
530 mv_set_timer_control(val);
531 return (0);
532 }
533
534 static int
mv_timer_stop(struct eventtimer * et)535 mv_timer_stop(struct eventtimer *et)
536 {
537 uint32_t val;
538
539 val = mv_get_timer_control();
540 val &= ~(CPU_TIMER0_EN | CPU_TIMER0_AUTO);
541 mv_set_timer_control(val);
542 return (0);
543 }
544
545 static void
mv_setup_timers(void)546 mv_setup_timers(void)
547 {
548 uint32_t val;
549
550 mv_set_timer_rel(1, INITIAL_TIMECOUNTER);
551 mv_set_timer(1, INITIAL_TIMECOUNTER);
552 val = mv_get_timer_control();
553 val &= ~(CPU_TIMER0_EN | CPU_TIMER0_AUTO);
554 val |= CPU_TIMER1_EN | CPU_TIMER1_AUTO;
555
556 if (timer_softc->config->soc_family == MV_SOC_ARMADA_XP) {
557 /* Enable 25MHz mode */
558 val |= CPU_TIMER0_25MHZ_EN | CPU_TIMER1_25MHZ_EN;
559 }
560
561 mv_set_timer_control(val);
562 timers_initialized = 1;
563 }
564