1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * This file contains platform specific structure definitions
4 * and init function used by Meteor Lake PCH.
5 *
6 * Copyright (c) 2022, Intel Corporation.
7 * All Rights Reserved.
8 *
9 */
10
11 #include <linux/pci.h>
12 #include "core.h"
13
14 /* PMC SSRAM PMT Telemetry GUIDS */
15 #define SOCP_LPM_REQ_GUID 0x2625030
16 #define IOEM_LPM_REQ_GUID 0x4357464
17 #define IOEP_LPM_REQ_GUID 0x5077612
18
19 static const u8 MTL_LPM_REG_INDEX[] = {0, 4, 5, 6, 8, 9, 10, 11, 12, 13, 14, 15, 16, 20};
20
21 /*
22 * Die Mapping to Product.
23 * Product SOCDie IOEDie PCHDie
24 * MTL-M SOC-M IOE-M None
25 * MTL-P SOC-M IOE-P None
26 * MTL-S SOC-S IOE-P PCH-S
27 */
28
29 const struct pmc_bit_map mtl_socm_pfear_map[] = {
30 {"PMC", BIT(0)},
31 {"OPI", BIT(1)},
32 {"SPI", BIT(2)},
33 {"XHCI", BIT(3)},
34 {"SPA", BIT(4)},
35 {"SPB", BIT(5)},
36 {"SPC", BIT(6)},
37 {"GBE", BIT(7)},
38
39 {"SATA", BIT(0)},
40 {"DSP0", BIT(1)},
41 {"DSP1", BIT(2)},
42 {"DSP2", BIT(3)},
43 {"DSP3", BIT(4)},
44 {"SPD", BIT(5)},
45 {"LPSS", BIT(6)},
46 {"LPC", BIT(7)},
47
48 {"SMB", BIT(0)},
49 {"ISH", BIT(1)},
50 {"P2SB", BIT(2)},
51 {"NPK_VNN", BIT(3)},
52 {"SDX", BIT(4)},
53 {"SPE", BIT(5)},
54 {"FUSE", BIT(6)},
55 {"SBR8", BIT(7)},
56
57 {"RSVD24", BIT(0)},
58 {"OTG", BIT(1)},
59 {"EXI", BIT(2)},
60 {"CSE", BIT(3)},
61 {"CSME_KVM", BIT(4)},
62 {"CSME_PMT", BIT(5)},
63 {"CSME_CLINK", BIT(6)},
64 {"CSME_PTIO", BIT(7)},
65
66 {"CSME_USBR", BIT(0)},
67 {"CSME_SUSRAM", BIT(1)},
68 {"CSME_SMT1", BIT(2)},
69 {"RSVD35", BIT(3)},
70 {"CSME_SMS2", BIT(4)},
71 {"CSME_SMS", BIT(5)},
72 {"CSME_RTC", BIT(6)},
73 {"CSME_PSF", BIT(7)},
74
75 {"SBR0", BIT(0)},
76 {"SBR1", BIT(1)},
77 {"SBR2", BIT(2)},
78 {"SBR3", BIT(3)},
79 {"SBR4", BIT(4)},
80 {"SBR5", BIT(5)},
81 {"RSVD46", BIT(6)},
82 {"PSF1", BIT(7)},
83
84 {"PSF2", BIT(0)},
85 {"PSF3", BIT(1)},
86 {"PSF4", BIT(2)},
87 {"CNVI", BIT(3)},
88 {"UFSX2", BIT(4)},
89 {"EMMC", BIT(5)},
90 {"SPF", BIT(6)},
91 {"SBR6", BIT(7)},
92
93 {"SBR7", BIT(0)},
94 {"NPK_AON", BIT(1)},
95 {"HDA4", BIT(2)},
96 {"HDA5", BIT(3)},
97 {"HDA6", BIT(4)},
98 {"PSF6", BIT(5)},
99 {"RSVD62", BIT(6)},
100 {"RSVD63", BIT(7)},
101 {}
102 };
103
104 static const struct pmc_bit_map *ext_mtl_socm_pfear_map[] = {
105 mtl_socm_pfear_map,
106 NULL
107 };
108
109 static const struct pmc_bit_map mtl_socm_ltr_show_map[] = {
110 {"SOUTHPORT_A", CNP_PMC_LTR_SPA},
111 {"SOUTHPORT_B", CNP_PMC_LTR_SPB},
112 {"SATA", CNP_PMC_LTR_SATA},
113 {"GIGABIT_ETHERNET", CNP_PMC_LTR_GBE},
114 {"XHCI", CNP_PMC_LTR_XHCI},
115 {"SOUTHPORT_F", ADL_PMC_LTR_SPF},
116 {"ME", CNP_PMC_LTR_ME},
117 {"SATA1", CNP_PMC_LTR_EVA},
118 {"SOUTHPORT_C", CNP_PMC_LTR_SPC},
119 {"HD_AUDIO", CNP_PMC_LTR_AZ},
120 {"CNV", CNP_PMC_LTR_CNV},
121 {"LPSS", CNP_PMC_LTR_LPSS},
122 {"SOUTHPORT_D", CNP_PMC_LTR_SPD},
123 {"SOUTHPORT_E", CNP_PMC_LTR_SPE},
124 {"SATA2", CNP_PMC_LTR_CAM},
125 {"ESPI", CNP_PMC_LTR_ESPI},
126 {"SCC", CNP_PMC_LTR_SCC},
127 {"ISH", CNP_PMC_LTR_ISH},
128 {"UFSX2", CNP_PMC_LTR_UFSX2},
129 {"EMMC", CNP_PMC_LTR_EMMC},
130 {"WIGIG", ICL_PMC_LTR_WIGIG},
131 {"THC0", TGL_PMC_LTR_THC0},
132 {"THC1", TGL_PMC_LTR_THC1},
133 {"SOUTHPORT_G", MTL_PMC_LTR_SPG},
134 {"ESE", MTL_PMC_LTR_ESE},
135 {"IOE_PMC", MTL_PMC_LTR_IOE_PMC},
136
137 /* Below two cannot be used for LTR_IGNORE */
138 {"CURRENT_PLATFORM", CNP_PMC_LTR_CUR_PLT},
139 {"AGGREGATED_SYSTEM", CNP_PMC_LTR_CUR_ASLT},
140 {}
141 };
142
143 static const struct pmc_bit_map mtl_socm_clocksource_status_map[] = {
144 {"AON2_OFF_STS", BIT(0)},
145 {"AON3_OFF_STS", BIT(1)},
146 {"AON4_OFF_STS", BIT(2)},
147 {"AON5_OFF_STS", BIT(3)},
148 {"AON1_OFF_STS", BIT(4)},
149 {"XTAL_LVM_OFF_STS", BIT(5)},
150 {"MPFPW1_0_PLL_OFF_STS", BIT(6)},
151 {"MPFPW1_1_PLL_OFF_STS", BIT(7)},
152 {"USB3_PLL_OFF_STS", BIT(8)},
153 {"AON3_SPL_OFF_STS", BIT(9)},
154 {"MPFPW2_0_PLL_OFF_STS", BIT(12)},
155 {"MPFPW3_0_PLL_OFF_STS", BIT(13)},
156 {"XTAL_AGGR_OFF_STS", BIT(17)},
157 {"USB2_PLL_OFF_STS", BIT(18)},
158 {"FILTER_PLL_OFF_STS", BIT(22)},
159 {"ACE_PLL_OFF_STS", BIT(24)},
160 {"FABRIC_PLL_OFF_STS", BIT(25)},
161 {"SOC_PLL_OFF_STS", BIT(26)},
162 {"PCIFAB_PLL_OFF_STS", BIT(27)},
163 {"REF_PLL_OFF_STS", BIT(28)},
164 {"IMG_PLL_OFF_STS", BIT(29)},
165 {"RTC_PLL_OFF_STS", BIT(31)},
166 {}
167 };
168
169 static const struct pmc_bit_map mtl_socm_power_gating_status_0_map[] = {
170 {"PMC_PGD0_PG_STS", BIT(0)},
171 {"DMI_PGD0_PG_STS", BIT(1)},
172 {"ESPISPI_PGD0_PG_STS", BIT(2)},
173 {"XHCI_PGD0_PG_STS", BIT(3)},
174 {"SPA_PGD0_PG_STS", BIT(4)},
175 {"SPB_PGD0_PG_STS", BIT(5)},
176 {"SPC_PGD0_PG_STS", BIT(6)},
177 {"GBE_PGD0_PG_STS", BIT(7)},
178 {"SATA_PGD0_PG_STS", BIT(8)},
179 {"PSF13_PGD0_PG_STS", BIT(9)},
180 {"SOC_D2D_PGD3_PG_STS", BIT(10)},
181 {"MPFPW3_PGD0_PG_STS", BIT(11)},
182 {"ESE_PGD0_PG_STS", BIT(12)},
183 {"SPD_PGD0_PG_STS", BIT(13)},
184 {"LPSS_PGD0_PG_STS", BIT(14)},
185 {"LPC_PGD0_PG_STS", BIT(15)},
186 {"SMB_PGD0_PG_STS", BIT(16)},
187 {"ISH_PGD0_PG_STS", BIT(17)},
188 {"P2S_PGD0_PG_STS", BIT(18)},
189 {"NPK_PGD0_PG_STS", BIT(19)},
190 {"DBG_SBR_PGD0_PG_STS", BIT(20)},
191 {"SBRG_PGD0_PG_STS", BIT(21)},
192 {"FUSE_PGD0_PG_STS", BIT(22)},
193 {"SBR8_PGD0_PG_STS", BIT(23)},
194 {"SOC_D2D_PGD2_PG_STS", BIT(24)},
195 {"XDCI_PGD0_PG_STS", BIT(25)},
196 {"EXI_PGD0_PG_STS", BIT(26)},
197 {"CSE_PGD0_PG_STS", BIT(27)},
198 {"KVMCC_PGD0_PG_STS", BIT(28)},
199 {"PMT_PGD0_PG_STS", BIT(29)},
200 {"CLINK_PGD0_PG_STS", BIT(30)},
201 {"PTIO_PGD0_PG_STS", BIT(31)},
202 {}
203 };
204
205 static const struct pmc_bit_map mtl_socm_power_gating_status_1_map[] = {
206 {"USBR0_PGD0_PG_STS", BIT(0)},
207 {"SUSRAM_PGD0_PG_STS", BIT(1)},
208 {"SMT1_PGD0_PG_STS", BIT(2)},
209 {"FIACPCB_U_PGD0_PG_STS", BIT(3)},
210 {"SMS2_PGD0_PG_STS", BIT(4)},
211 {"SMS1_PGD0_PG_STS", BIT(5)},
212 {"CSMERTC_PGD0_PG_STS", BIT(6)},
213 {"CSMEPSF_PGD0_PG_STS", BIT(7)},
214 {"SBR0_PGD0_PG_STS", BIT(8)},
215 {"SBR1_PGD0_PG_STS", BIT(9)},
216 {"SBR2_PGD0_PG_STS", BIT(10)},
217 {"SBR3_PGD0_PG_STS", BIT(11)},
218 {"U3FPW1_PGD0_PG_STS", BIT(12)},
219 {"SBR5_PGD0_PG_STS", BIT(13)},
220 {"MPFPW1_PGD0_PG_STS", BIT(14)},
221 {"UFSPW1_PGD0_PG_STS", BIT(15)},
222 {"FIA_X_PGD0_PG_STS", BIT(16)},
223 {"SOC_D2D_PGD0_PG_STS", BIT(17)},
224 {"MPFPW2_PGD0_PG_STS", BIT(18)},
225 {"CNVI_PGD0_PG_STS", BIT(19)},
226 {"UFSX2_PGD0_PG_STS", BIT(20)},
227 {"ENDBG_PGD0_PG_STS", BIT(21)},
228 {"DBG_PSF_PGD0_PG_STS", BIT(22)},
229 {"SBR6_PGD0_PG_STS", BIT(23)},
230 {"SBR7_PGD0_PG_STS", BIT(24)},
231 {"NPK_PGD1_PG_STS", BIT(25)},
232 {"FIACPCB_X_PGD0_PG_STS", BIT(26)},
233 {"DBC_PGD0_PG_STS", BIT(27)},
234 {"FUSEGPSB_PGD0_PG_STS", BIT(28)},
235 {"PSF6_PGD0_PG_STS", BIT(29)},
236 {"PSF7_PGD0_PG_STS", BIT(30)},
237 {"GBETSN1_PGD0_PG_STS", BIT(31)},
238 {}
239 };
240
241 static const struct pmc_bit_map mtl_socm_power_gating_status_2_map[] = {
242 {"PSF8_PGD0_PG_STS", BIT(0)},
243 {"FIA_PGD0_PG_STS", BIT(1)},
244 {"SOC_D2D_PGD1_PG_STS", BIT(2)},
245 {"FIA_U_PGD0_PG_STS", BIT(3)},
246 {"TAM_PGD0_PG_STS", BIT(4)},
247 {"GBETSN_PGD0_PG_STS", BIT(5)},
248 {"TBTLSX_PGD0_PG_STS", BIT(6)},
249 {"THC0_PGD0_PG_STS", BIT(7)},
250 {"THC1_PGD0_PG_STS", BIT(8)},
251 {"PMC_PGD1_PG_STS", BIT(9)},
252 {"GNA_PGD0_PG_STS", BIT(10)},
253 {"ACE_PGD0_PG_STS", BIT(11)},
254 {"ACE_PGD1_PG_STS", BIT(12)},
255 {"ACE_PGD2_PG_STS", BIT(13)},
256 {"ACE_PGD3_PG_STS", BIT(14)},
257 {"ACE_PGD4_PG_STS", BIT(15)},
258 {"ACE_PGD5_PG_STS", BIT(16)},
259 {"ACE_PGD6_PG_STS", BIT(17)},
260 {"ACE_PGD7_PG_STS", BIT(18)},
261 {"ACE_PGD8_PG_STS", BIT(19)},
262 {"FIA_PGS_PGD0_PG_STS", BIT(20)},
263 {"FIACPCB_PGS_PGD0_PG_STS", BIT(21)},
264 {"FUSEPMSB_PGD0_PG_STS", BIT(22)},
265 {}
266 };
267
268 const struct pmc_bit_map mtl_socm_d3_status_0_map[] = {
269 {"LPSS_D3_STS", BIT(3)},
270 {"XDCI_D3_STS", BIT(4)},
271 {"XHCI_D3_STS", BIT(5)},
272 {"SPA_D3_STS", BIT(12)},
273 {"SPB_D3_STS", BIT(13)},
274 {"SPC_D3_STS", BIT(14)},
275 {"SPD_D3_STS", BIT(15)},
276 {"ESPISPI_D3_STS", BIT(18)},
277 {"SATA_D3_STS", BIT(20)},
278 {"PSTH_D3_STS", BIT(21)},
279 {"DMI_D3_STS", BIT(22)},
280 {}
281 };
282
283 const struct pmc_bit_map mtl_socm_d3_status_1_map[] = {
284 {"GBETSN1_D3_STS", BIT(14)},
285 {"GBE_D3_STS", BIT(19)},
286 {"ITSS_D3_STS", BIT(23)},
287 {"P2S_D3_STS", BIT(24)},
288 {"CNVI_D3_STS", BIT(27)},
289 {"UFSX2_D3_STS", BIT(28)},
290 {}
291 };
292
293 static const struct pmc_bit_map mtl_socm_d3_status_2_map[] = {
294 {"GNA_D3_STS", BIT(0)},
295 {"CSMERTC_D3_STS", BIT(1)},
296 {"SUSRAM_D3_STS", BIT(2)},
297 {"CSE_D3_STS", BIT(4)},
298 {"KVMCC_D3_STS", BIT(5)},
299 {"USBR0_D3_STS", BIT(6)},
300 {"ISH_D3_STS", BIT(7)},
301 {"SMT1_D3_STS", BIT(8)},
302 {"SMT2_D3_STS", BIT(9)},
303 {"SMT3_D3_STS", BIT(10)},
304 {"CLINK_D3_STS", BIT(14)},
305 {"PTIO_D3_STS", BIT(16)},
306 {"PMT_D3_STS", BIT(17)},
307 {"SMS1_D3_STS", BIT(18)},
308 {"SMS2_D3_STS", BIT(19)},
309 {}
310 };
311
312 static const struct pmc_bit_map mtl_socm_d3_status_3_map[] = {
313 {"ESE_D3_STS", BIT(2)},
314 {"GBETSN_D3_STS", BIT(13)},
315 {"THC0_D3_STS", BIT(14)},
316 {"THC1_D3_STS", BIT(15)},
317 {"ACE_D3_STS", BIT(23)},
318 {}
319 };
320
321 const struct pmc_bit_map mtl_socm_vnn_req_status_0_map[] = {
322 {"LPSS_VNN_REQ_STS", BIT(3)},
323 {"FIA_VNN_REQ_STS", BIT(17)},
324 {"ESPISPI_VNN_REQ_STS", BIT(18)},
325 {}
326 };
327
328 const struct pmc_bit_map mtl_socm_vnn_req_status_1_map[] = {
329 {"NPK_VNN_REQ_STS", BIT(4)},
330 {"DFXAGG_VNN_REQ_STS", BIT(8)},
331 {"EXI_VNN_REQ_STS", BIT(9)},
332 {"P2D_VNN_REQ_STS", BIT(18)},
333 {"GBE_VNN_REQ_STS", BIT(19)},
334 {"SMB_VNN_REQ_STS", BIT(25)},
335 {"LPC_VNN_REQ_STS", BIT(26)},
336 {}
337 };
338
339 const struct pmc_bit_map mtl_socm_vnn_req_status_2_map[] = {
340 {"CSMERTC_VNN_REQ_STS", BIT(1)},
341 {"CSE_VNN_REQ_STS", BIT(4)},
342 {"ISH_VNN_REQ_STS", BIT(7)},
343 {"SMT1_VNN_REQ_STS", BIT(8)},
344 {"CLINK_VNN_REQ_STS", BIT(14)},
345 {"SMS1_VNN_REQ_STS", BIT(18)},
346 {"SMS2_VNN_REQ_STS", BIT(19)},
347 {"GPIOCOM4_VNN_REQ_STS", BIT(20)},
348 {"GPIOCOM3_VNN_REQ_STS", BIT(21)},
349 {"GPIOCOM2_VNN_REQ_STS", BIT(22)},
350 {"GPIOCOM1_VNN_REQ_STS", BIT(23)},
351 {"GPIOCOM0_VNN_REQ_STS", BIT(24)},
352 {}
353 };
354
355 static const struct pmc_bit_map mtl_socm_vnn_req_status_3_map[] = {
356 {"ESE_VNN_REQ_STS", BIT(2)},
357 {"DTS0_VNN_REQ_STS", BIT(7)},
358 {"GPIOCOM5_VNN_REQ_STS", BIT(11)},
359 {}
360 };
361
362 const struct pmc_bit_map mtl_socm_vnn_misc_status_map[] = {
363 {"CPU_C10_REQ_STS", BIT(0)},
364 {"TS_OFF_REQ_STS", BIT(1)},
365 {"PNDE_MET_REQ_STS", BIT(2)},
366 {"PCIE_DEEP_PM_REQ_STS", BIT(3)},
367 {"PMC_CLK_THROTTLE_EN_REQ_STS", BIT(4)},
368 {"NPK_VNNAON_REQ_STS", BIT(5)},
369 {"VNN_SOC_REQ_STS", BIT(6)},
370 {"ISH_VNNAON_REQ_STS", BIT(7)},
371 {"IOE_COND_MET_S02I2_0_REQ_STS", BIT(8)},
372 {"IOE_COND_MET_S02I2_1_REQ_STS", BIT(9)},
373 {"IOE_COND_MET_S02I2_2_REQ_STS", BIT(10)},
374 {"PLT_GREATER_REQ_STS", BIT(11)},
375 {"PCIE_CLKREQ_REQ_STS", BIT(12)},
376 {"PMC_IDLE_FB_OCP_REQ_STS", BIT(13)},
377 {"PM_SYNC_STATES_REQ_STS", BIT(14)},
378 {"EA_REQ_STS", BIT(15)},
379 {"MPHY_CORE_OFF_REQ_STS", BIT(16)},
380 {"BRK_EV_EN_REQ_STS", BIT(17)},
381 {"AUTO_DEMO_EN_REQ_STS", BIT(18)},
382 {"ITSS_CLK_SRC_REQ_STS", BIT(19)},
383 {"LPC_CLK_SRC_REQ_STS", BIT(20)},
384 {"ARC_IDLE_REQ_STS", BIT(21)},
385 {"MPHY_SUS_REQ_STS", BIT(22)},
386 {"FIA_DEEP_PM_REQ_STS", BIT(23)},
387 {"UXD_CONNECTED_REQ_STS", BIT(24)},
388 {"ARC_INTERRUPT_WAKE_REQ_STS", BIT(25)},
389 {"USB2_VNNAON_ACT_REQ_STS", BIT(26)},
390 {"PRE_WAKE0_REQ_STS", BIT(27)},
391 {"PRE_WAKE1_REQ_STS", BIT(28)},
392 {"PRE_WAKE2_EN_REQ_STS", BIT(29)},
393 {"WOV_REQ_STS", BIT(30)},
394 {"CNVI_V1P05_REQ_STS", BIT(31)},
395 {}
396 };
397
398 const struct pmc_bit_map mtl_socm_signal_status_map[] = {
399 {"LSX_Wake0_En_STS", BIT(0)},
400 {"LSX_Wake0_Pol_STS", BIT(1)},
401 {"LSX_Wake1_En_STS", BIT(2)},
402 {"LSX_Wake1_Pol_STS", BIT(3)},
403 {"LSX_Wake2_En_STS", BIT(4)},
404 {"LSX_Wake2_Pol_STS", BIT(5)},
405 {"LSX_Wake3_En_STS", BIT(6)},
406 {"LSX_Wake3_Pol_STS", BIT(7)},
407 {"LSX_Wake4_En_STS", BIT(8)},
408 {"LSX_Wake4_Pol_STS", BIT(9)},
409 {"LSX_Wake5_En_STS", BIT(10)},
410 {"LSX_Wake5_Pol_STS", BIT(11)},
411 {"LSX_Wake6_En_STS", BIT(12)},
412 {"LSX_Wake6_Pol_STS", BIT(13)},
413 {"LSX_Wake7_En_STS", BIT(14)},
414 {"LSX_Wake7_Pol_STS", BIT(15)},
415 {"LPSS_Wake0_En_STS", BIT(16)},
416 {"LPSS_Wake0_Pol_STS", BIT(17)},
417 {"LPSS_Wake1_En_STS", BIT(18)},
418 {"LPSS_Wake1_Pol_STS", BIT(19)},
419 {"Int_Timer_SS_Wake0_En_STS", BIT(20)},
420 {"Int_Timer_SS_Wake0_Pol_STS", BIT(21)},
421 {"Int_Timer_SS_Wake1_En_STS", BIT(22)},
422 {"Int_Timer_SS_Wake1_Pol_STS", BIT(23)},
423 {"Int_Timer_SS_Wake2_En_STS", BIT(24)},
424 {"Int_Timer_SS_Wake2_Pol_STS", BIT(25)},
425 {"Int_Timer_SS_Wake3_En_STS", BIT(26)},
426 {"Int_Timer_SS_Wake3_Pol_STS", BIT(27)},
427 {"Int_Timer_SS_Wake4_En_STS", BIT(28)},
428 {"Int_Timer_SS_Wake4_Pol_STS", BIT(29)},
429 {"Int_Timer_SS_Wake5_En_STS", BIT(30)},
430 {"Int_Timer_SS_Wake5_Pol_STS", BIT(31)},
431 {}
432 };
433
434 static const struct pmc_bit_map *mtl_socm_lpm_maps[] = {
435 mtl_socm_clocksource_status_map,
436 mtl_socm_power_gating_status_0_map,
437 mtl_socm_power_gating_status_1_map,
438 mtl_socm_power_gating_status_2_map,
439 mtl_socm_d3_status_0_map,
440 mtl_socm_d3_status_1_map,
441 mtl_socm_d3_status_2_map,
442 mtl_socm_d3_status_3_map,
443 mtl_socm_vnn_req_status_0_map,
444 mtl_socm_vnn_req_status_1_map,
445 mtl_socm_vnn_req_status_2_map,
446 mtl_socm_vnn_req_status_3_map,
447 mtl_socm_vnn_misc_status_map,
448 mtl_socm_signal_status_map,
449 NULL
450 };
451
452 const struct pmc_reg_map mtl_socm_reg_map = {
453 .pfear_sts = ext_mtl_socm_pfear_map,
454 .slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,
455 .slp_s0_res_counter_step = TGL_PMC_SLP_S0_RES_COUNTER_STEP,
456 .ltr_show_sts = mtl_socm_ltr_show_map,
457 .msr_sts = msr_map,
458 .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
459 .regmap_length = MTL_SOC_PMC_MMIO_REG_LEN,
460 .ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,
461 .ppfear_buckets = MTL_SOCM_PPFEAR_NUM_ENTRIES,
462 .pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,
463 .pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
464 .lpm_num_maps = ADL_LPM_NUM_MAPS,
465 .ltr_ignore_max = MTL_SOCM_NUM_IP_IGN_ALLOWED,
466 .lpm_res_counter_step_x2 = TGL_PMC_LPM_RES_COUNTER_STEP_X2,
467 .etr3_offset = ETR3_OFFSET,
468 .lpm_sts_latch_en_offset = MTL_LPM_STATUS_LATCH_EN_OFFSET,
469 .lpm_priority_offset = MTL_LPM_PRI_OFFSET,
470 .lpm_en_offset = MTL_LPM_EN_OFFSET,
471 .lpm_residency_offset = MTL_LPM_RESIDENCY_OFFSET,
472 .lpm_sts = mtl_socm_lpm_maps,
473 .lpm_status_offset = MTL_LPM_STATUS_OFFSET,
474 .lpm_live_status_offset = MTL_LPM_LIVE_STATUS_OFFSET,
475 .lpm_reg_index = MTL_LPM_REG_INDEX,
476 };
477
478 static const struct pmc_bit_map mtl_ioep_pfear_map[] = {
479 {"PMC_0", BIT(0)},
480 {"OPI", BIT(1)},
481 {"TCSS", BIT(2)},
482 {"RSVD3", BIT(3)},
483 {"SPA", BIT(4)},
484 {"SPB", BIT(5)},
485 {"SPC", BIT(6)},
486 {"IOE_D2D_3", BIT(7)},
487
488 {"RSVD8", BIT(0)},
489 {"RSVD9", BIT(1)},
490 {"SPE", BIT(2)},
491 {"RSVD11", BIT(3)},
492 {"RSVD12", BIT(4)},
493 {"SPD", BIT(5)},
494 {"ACE_7", BIT(6)},
495 {"RSVD15", BIT(7)},
496
497 {"ACE_0", BIT(0)},
498 {"FIACPCB_P", BIT(1)},
499 {"P2S", BIT(2)},
500 {"RSVD19", BIT(3)},
501 {"ACE_8", BIT(4)},
502 {"IOE_D2D_0", BIT(5)},
503 {"FUSE", BIT(6)},
504 {"RSVD23", BIT(7)},
505
506 {"FIACPCB_P5", BIT(0)},
507 {"ACE_3", BIT(1)},
508 {"RSF5", BIT(2)},
509 {"ACE_2", BIT(3)},
510 {"ACE_4", BIT(4)},
511 {"RSVD29", BIT(5)},
512 {"RSF10", BIT(6)},
513 {"MPFPW5", BIT(7)},
514
515 {"PSF9", BIT(0)},
516 {"MPFPW4", BIT(1)},
517 {"RSVD34", BIT(2)},
518 {"RSVD35", BIT(3)},
519 {"RSVD36", BIT(4)},
520 {"RSVD37", BIT(5)},
521 {"RSVD38", BIT(6)},
522 {"RSVD39", BIT(7)},
523
524 {"SBR0", BIT(0)},
525 {"SBR1", BIT(1)},
526 {"SBR2", BIT(2)},
527 {"SBR3", BIT(3)},
528 {"SBR4", BIT(4)},
529 {"SBR5", BIT(5)},
530 {"RSVD46", BIT(6)},
531 {"RSVD47", BIT(7)},
532
533 {"RSVD48", BIT(0)},
534 {"FIA_P5", BIT(1)},
535 {"RSVD50", BIT(2)},
536 {"RSVD51", BIT(3)},
537 {"RSVD52", BIT(4)},
538 {"RSVD53", BIT(5)},
539 {"RSVD54", BIT(6)},
540 {"ACE_1", BIT(7)},
541
542 {"RSVD56", BIT(0)},
543 {"ACE_5", BIT(1)},
544 {"RSVD58", BIT(2)},
545 {"G5FPW1", BIT(3)},
546 {"RSVD60", BIT(4)},
547 {"ACE_6", BIT(5)},
548 {"RSVD62", BIT(6)},
549 {"GBETSN1", BIT(7)},
550
551 {"RSVD64", BIT(0)},
552 {"FIA", BIT(1)},
553 {"RSVD66", BIT(2)},
554 {"FIA_P", BIT(3)},
555 {"TAM", BIT(4)},
556 {"GBETSN", BIT(5)},
557 {"IOE_D2D_2", BIT(6)},
558 {"IOE_D2D_1", BIT(7)},
559
560 {"SPF", BIT(0)},
561 {"PMC_1", BIT(1)},
562 {}
563 };
564
565 static const struct pmc_bit_map *ext_mtl_ioep_pfear_map[] = {
566 mtl_ioep_pfear_map,
567 NULL
568 };
569
570 static const struct pmc_bit_map mtl_ioep_ltr_show_map[] = {
571 {"SOUTHPORT_A", CNP_PMC_LTR_SPA},
572 {"SOUTHPORT_B", CNP_PMC_LTR_SPB},
573 {"SATA", CNP_PMC_LTR_SATA},
574 {"GIGABIT_ETHERNET", CNP_PMC_LTR_GBE},
575 {"XHCI", CNP_PMC_LTR_XHCI},
576 {"SOUTHPORT_F", ADL_PMC_LTR_SPF},
577 {"ME", CNP_PMC_LTR_ME},
578 {"SATA1", CNP_PMC_LTR_EVA},
579 {"SOUTHPORT_C", CNP_PMC_LTR_SPC},
580 {"HD_AUDIO", CNP_PMC_LTR_AZ},
581 {"CNV", CNP_PMC_LTR_CNV},
582 {"LPSS", CNP_PMC_LTR_LPSS},
583 {"SOUTHPORT_D", CNP_PMC_LTR_SPD},
584 {"SOUTHPORT_E", CNP_PMC_LTR_SPE},
585 {"SATA2", CNP_PMC_LTR_CAM},
586 {"ESPI", CNP_PMC_LTR_ESPI},
587 {"SCC", CNP_PMC_LTR_SCC},
588 {"Reserved", MTL_PMC_LTR_RESERVED},
589 {"UFSX2", CNP_PMC_LTR_UFSX2},
590 {"EMMC", CNP_PMC_LTR_EMMC},
591 {"WIGIG", ICL_PMC_LTR_WIGIG},
592 {"THC0", TGL_PMC_LTR_THC0},
593 {"THC1", TGL_PMC_LTR_THC1},
594 {"SOUTHPORT_G", MTL_PMC_LTR_SPG},
595
596 /* Below two cannot be used for LTR_IGNORE */
597 {"CURRENT_PLATFORM", CNP_PMC_LTR_CUR_PLT},
598 {"AGGREGATED_SYSTEM", CNP_PMC_LTR_CUR_ASLT},
599 {}
600 };
601
602 static const struct pmc_bit_map mtl_ioep_clocksource_status_map[] = {
603 {"AON2_OFF_STS", BIT(0)},
604 {"AON3_OFF_STS", BIT(1)},
605 {"AON4_OFF_STS", BIT(2)},
606 {"AON5_OFF_STS", BIT(3)},
607 {"AON1_OFF_STS", BIT(4)},
608 {"TBT_PLL_OFF_STS", BIT(5)},
609 {"TMU_PLL_OFF_STS", BIT(6)},
610 {"BCLK_PLL_OFF_STS", BIT(7)},
611 {"D2D_PLL_OFF_STS", BIT(8)},
612 {"AON3_SPL_OFF_STS", BIT(9)},
613 {"MPFPW4_0_PLL_OFF_STS", BIT(12)},
614 {"MPFPW5_0_PLL_OFF_STS", BIT(13)},
615 {"G5FPW_0_PLL_OFF_STS", BIT(14)},
616 {"G5FPW_1_PLL_OFF_STS", BIT(15)},
617 {"XTAL_AGGR_OFF_STS", BIT(17)},
618 {"FABRIC_PLL_OFF_STS", BIT(25)},
619 {"SOC_PLL_OFF_STS", BIT(26)},
620 {"REF_PLL_OFF_STS", BIT(28)},
621 {"RTC_PLL_OFF_STS", BIT(31)},
622 {}
623 };
624
625 static const struct pmc_bit_map mtl_ioep_power_gating_status_0_map[] = {
626 {"PMC_PGD0_PG_STS", BIT(0)},
627 {"DMI_PGD0_PG_STS", BIT(1)},
628 {"TCSS_PGD0_PG_STS", BIT(2)},
629 {"SPA_PGD0_PG_STS", BIT(4)},
630 {"SPB_PGD0_PG_STS", BIT(5)},
631 {"SPC_PGD0_PG_STS", BIT(6)},
632 {"IOE_D2D_PGD3_PG_STS", BIT(7)},
633 {"SPE_PGD0_PG_STS", BIT(10)},
634 {"SPD_PGD0_PG_STS", BIT(13)},
635 {"ACE_PGD7_PG_STS", BIT(14)},
636 {"ACE_PGD0_PG_STS", BIT(16)},
637 {"FIACPCB_P_PGD0_PG_STS", BIT(17)},
638 {"P2S_PGD0_PG_STS", BIT(18)},
639 {"ACE_PGD8_PG_STS", BIT(20)},
640 {"IOE_D2D_PGD0_PG_STS", BIT(21)},
641 {"FUSE_PGD0_PG_STS", BIT(22)},
642 {"FIACPCB_P5_PGD0_PG_STS", BIT(24)},
643 {"ACE_PGD3_PG_STS", BIT(25)},
644 {"PSF5_PGD0_PG_STS", BIT(26)},
645 {"ACE_PGD2_PG_STS", BIT(27)},
646 {"ACE_PGD4_PG_STS", BIT(28)},
647 {"PSF10_PGD0_PG_STS", BIT(30)},
648 {"MPFPW5_PGD0_PG_STS", BIT(31)},
649 {}
650 };
651
652 static const struct pmc_bit_map mtl_ioep_power_gating_status_1_map[] = {
653 {"PSF9_PGD0_PG_STS", BIT(0)},
654 {"MPFPW4_PGD0_PG_STS", BIT(1)},
655 {"SBR0_PGD0_PG_STS", BIT(8)},
656 {"SBR1_PGD0_PG_STS", BIT(9)},
657 {"SBR2_PGD0_PG_STS", BIT(10)},
658 {"SBR3_PGD0_PG_STS", BIT(11)},
659 {"SBR4_PGD0_PG_STS", BIT(12)},
660 {"SBR5_PGD0_PG_STS", BIT(13)},
661 {"FIA_P5_PGD0_PG_STS", BIT(17)},
662 {"ACE_PGD1_PGD0_PG_STS", BIT(23)},
663 {"ACE_PGD5_PGD1_PG_STS", BIT(25)},
664 {"G5FPW1_PGD0_PG_STS", BIT(27)},
665 {"ACE_PGD6_PG_STS", BIT(29)},
666 {"GBETSN1_PGD0_PG_STS", BIT(31)},
667 {}
668 };
669
670 static const struct pmc_bit_map mtl_ioep_power_gating_status_2_map[] = {
671 {"FIA_PGD0_PG_STS", BIT(1)},
672 {"FIA_P_PGD0_PG_STS", BIT(3)},
673 {"TAM_PGD0_PG_STS", BIT(4)},
674 {"GBETSN_PGD0_PG_STS", BIT(5)},
675 {"IOE_D2D_PGD2_PG_STS", BIT(6)},
676 {"IOE_D2D_PGD1_PG_STS", BIT(7)},
677 {"SPF_PGD0_PG_STS", BIT(8)},
678 {"PMC_PGD1_PG_STS", BIT(9)},
679 {}
680 };
681
682 static const struct pmc_bit_map mtl_ioep_d3_status_0_map[] = {
683 {"SPF_D3_STS", BIT(0)},
684 {"SPA_D3_STS", BIT(12)},
685 {"SPB_D3_STS", BIT(13)},
686 {"SPC_D3_STS", BIT(14)},
687 {"SPD_D3_STS", BIT(15)},
688 {"SPE_D3_STS", BIT(16)},
689 {"DMI_D3_STS", BIT(22)},
690 {}
691 };
692
693 static const struct pmc_bit_map mtl_ioep_d3_status_1_map[] = {
694 {"GBETSN1_D3_STS", BIT(14)},
695 {"P2S_D3_STS", BIT(24)},
696 {}
697 };
698
699 static const struct pmc_bit_map mtl_ioep_d3_status_2_map[] = {
700 {}
701 };
702
703 static const struct pmc_bit_map mtl_ioep_d3_status_3_map[] = {
704 {"GBETSN_D3_STS", BIT(13)},
705 {"ACE_D3_STS", BIT(23)},
706 {}
707 };
708
709 static const struct pmc_bit_map mtl_ioep_vnn_req_status_0_map[] = {
710 {"FIA_VNN_REQ_STS", BIT(17)},
711 {}
712 };
713
714 static const struct pmc_bit_map mtl_ioep_vnn_req_status_1_map[] = {
715 {"DFXAGG_VNN_REQ_STS", BIT(8)},
716 {}
717 };
718
719 static const struct pmc_bit_map mtl_ioep_vnn_req_status_2_map[] = {
720 {}
721 };
722
723 static const struct pmc_bit_map mtl_ioep_vnn_req_status_3_map[] = {
724 {"DTS0_VNN_REQ_STS", BIT(7)},
725 {"DISP_VNN_REQ_STS", BIT(19)},
726 {}
727 };
728
729 static const struct pmc_bit_map mtl_ioep_vnn_misc_status_map[] = {
730 {"CPU_C10_REQ_STS", BIT(0)},
731 {"TS_OFF_REQ_STS", BIT(1)},
732 {"PNDE_MET_REQ_STS", BIT(2)},
733 {"PCIE_DEEP_PM_REQ_STS", BIT(3)},
734 {"PMC_CLK_THROTTLE_EN_REQ_STS", BIT(4)},
735 {"NPK_VNNAON_REQ_STS", BIT(5)},
736 {"VNN_SOC_REQ_STS", BIT(6)},
737 {"USB_DEVICE_ATTACHED_REQ_STS", BIT(8)},
738 {"FIA_EXIT_REQ_STS", BIT(9)},
739 {"USB2_SUS_PG_REQ_STS", BIT(10)},
740 {"PLT_GREATER_REQ_STS", BIT(11)},
741 {"PCIE_CLKREQ_REQ_STS", BIT(12)},
742 {"PMC_IDLE_FB_OCP_REQ_STS", BIT(13)},
743 {"PM_SYNC_STATES_REQ_STS", BIT(14)},
744 {"EA_REQ_STS", BIT(15)},
745 {"MPHY_CORE_OFF_REQ_STS", BIT(16)},
746 {"BRK_EV_EN_REQ_STS", BIT(17)},
747 {"AUTO_DEMO_EN_REQ_STS", BIT(18)},
748 {"ITSS_CLK_SRC_REQ_STS", BIT(19)},
749 {"LPC_CLK_SRC_REQ_STS", BIT(20)},
750 {"ARC_IDLE_REQ_STS", BIT(21)},
751 {"MPHY_SUS_REQ_STS", BIT(22)},
752 {"FIA_DEEP_PM_REQ_STS", BIT(23)},
753 {"UXD_CONNECTED_REQ_STS", BIT(24)},
754 {"ARC_INTERRUPT_WAKE_REQ_STS", BIT(25)},
755 {"USB2_VNNAON_ACT_REQ_STS", BIT(26)},
756 {"PRE_WAKE0_REQ_STS", BIT(27)},
757 {"PRE_WAKE1_REQ_STS", BIT(28)},
758 {"PRE_WAKE2_EN_REQ_STS", BIT(29)},
759 {"WOV_REQ_STS", BIT(30)},
760 {"CNVI_V1P05_REQ_STS", BIT(31)},
761 {}
762 };
763
764 static const struct pmc_bit_map *mtl_ioep_lpm_maps[] = {
765 mtl_ioep_clocksource_status_map,
766 mtl_ioep_power_gating_status_0_map,
767 mtl_ioep_power_gating_status_1_map,
768 mtl_ioep_power_gating_status_2_map,
769 mtl_ioep_d3_status_0_map,
770 mtl_ioep_d3_status_1_map,
771 mtl_ioep_d3_status_2_map,
772 mtl_ioep_d3_status_3_map,
773 mtl_ioep_vnn_req_status_0_map,
774 mtl_ioep_vnn_req_status_1_map,
775 mtl_ioep_vnn_req_status_2_map,
776 mtl_ioep_vnn_req_status_3_map,
777 mtl_ioep_vnn_misc_status_map,
778 mtl_socm_signal_status_map,
779 NULL
780 };
781
782 const struct pmc_reg_map mtl_ioep_reg_map = {
783 .regmap_length = MTL_IOE_PMC_MMIO_REG_LEN,
784 .pfear_sts = ext_mtl_ioep_pfear_map,
785 .ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,
786 .ppfear_buckets = MTL_IOE_PPFEAR_NUM_ENTRIES,
787 .lpm_status_offset = MTL_LPM_STATUS_OFFSET,
788 .lpm_live_status_offset = MTL_LPM_LIVE_STATUS_OFFSET,
789 .lpm_sts = mtl_ioep_lpm_maps,
790 .ltr_show_sts = mtl_ioep_ltr_show_map,
791 .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
792 .ltr_ignore_max = ADL_NUM_IP_IGN_ALLOWED,
793 .lpm_num_maps = ADL_LPM_NUM_MAPS,
794 .lpm_res_counter_step_x2 = TGL_PMC_LPM_RES_COUNTER_STEP_X2,
795 .lpm_residency_offset = MTL_LPM_RESIDENCY_OFFSET,
796 .lpm_priority_offset = MTL_LPM_PRI_OFFSET,
797 .lpm_en_offset = MTL_LPM_EN_OFFSET,
798 .lpm_sts_latch_en_offset = MTL_LPM_STATUS_LATCH_EN_OFFSET,
799 .lpm_reg_index = MTL_LPM_REG_INDEX,
800 };
801
802 static const struct pmc_bit_map mtl_ioem_pfear_map[] = {
803 {"PMC_0", BIT(0)},
804 {"OPI", BIT(1)},
805 {"TCSS", BIT(2)},
806 {"RSVD3", BIT(3)},
807 {"SPA", BIT(4)},
808 {"SPB", BIT(5)},
809 {"SPC", BIT(6)},
810 {"IOE_D2D_3", BIT(7)},
811
812 {"RSVD8", BIT(0)},
813 {"RSVD9", BIT(1)},
814 {"SPE", BIT(2)},
815 {"RSVD11", BIT(3)},
816 {"RSVD12", BIT(4)},
817 {"SPD", BIT(5)},
818 {"ACE_7", BIT(6)},
819 {"RSVD15", BIT(7)},
820
821 {"ACE_0", BIT(0)},
822 {"FIACPCB_P", BIT(1)},
823 {"P2S", BIT(2)},
824 {"RSVD19", BIT(3)},
825 {"ACE_8", BIT(4)},
826 {"IOE_D2D_0", BIT(5)},
827 {"FUSE", BIT(6)},
828 {"RSVD23", BIT(7)},
829
830 {"FIACPCB_P5", BIT(0)},
831 {"ACE_3", BIT(1)},
832 {"RSF5", BIT(2)},
833 {"ACE_2", BIT(3)},
834 {"ACE_4", BIT(4)},
835 {"RSVD29", BIT(5)},
836 {"RSF10", BIT(6)},
837 {"MPFPW5", BIT(7)},
838
839 {"PSF9", BIT(0)},
840 {"MPFPW4", BIT(1)},
841 {"RSVD34", BIT(2)},
842 {"RSVD35", BIT(3)},
843 {"RSVD36", BIT(4)},
844 {"RSVD37", BIT(5)},
845 {"RSVD38", BIT(6)},
846 {"RSVD39", BIT(7)},
847
848 {"SBR0", BIT(0)},
849 {"SBR1", BIT(1)},
850 {"SBR2", BIT(2)},
851 {"SBR3", BIT(3)},
852 {"SBR4", BIT(4)},
853 {"RSVD45", BIT(5)},
854 {"RSVD46", BIT(6)},
855 {"RSVD47", BIT(7)},
856
857 {"RSVD48", BIT(0)},
858 {"FIA_P5", BIT(1)},
859 {"RSVD50", BIT(2)},
860 {"RSVD51", BIT(3)},
861 {"RSVD52", BIT(4)},
862 {"RSVD53", BIT(5)},
863 {"RSVD54", BIT(6)},
864 {"ACE_1", BIT(7)},
865
866 {"RSVD56", BIT(0)},
867 {"ACE_5", BIT(1)},
868 {"RSVD58", BIT(2)},
869 {"G5FPW1", BIT(3)},
870 {"RSVD60", BIT(4)},
871 {"ACE_6", BIT(5)},
872 {"RSVD62", BIT(6)},
873 {"GBETSN1", BIT(7)},
874
875 {"RSVD64", BIT(0)},
876 {"FIA", BIT(1)},
877 {"RSVD66", BIT(2)},
878 {"FIA_P", BIT(3)},
879 {"TAM", BIT(4)},
880 {"GBETSN", BIT(5)},
881 {"IOE_D2D_2", BIT(6)},
882 {"IOE_D2D_1", BIT(7)},
883
884 {"SPF", BIT(0)},
885 {"PMC_1", BIT(1)},
886 {}
887 };
888
889 static const struct pmc_bit_map *ext_mtl_ioem_pfear_map[] = {
890 mtl_ioem_pfear_map,
891 NULL
892 };
893
894 static const struct pmc_bit_map mtl_ioem_power_gating_status_1_map[] = {
895 {"PSF9_PGD0_PG_STS", BIT(0)},
896 {"MPFPW4_PGD0_PG_STS", BIT(1)},
897 {"SBR0_PGD0_PG_STS", BIT(8)},
898 {"SBR1_PGD0_PG_STS", BIT(9)},
899 {"SBR2_PGD0_PG_STS", BIT(10)},
900 {"SBR3_PGD0_PG_STS", BIT(11)},
901 {"SBR4_PGD0_PG_STS", BIT(12)},
902 {"FIA_P5_PGD0_PG_STS", BIT(17)},
903 {"ACE_PGD1_PGD0_PG_STS", BIT(23)},
904 {"ACE_PGD5_PGD1_PG_STS", BIT(25)},
905 {"G5FPW1_PGD0_PG_STS", BIT(27)},
906 {"ACE_PGD6_PG_STS", BIT(29)},
907 {"GBETSN1_PGD0_PG_STS", BIT(31)},
908 {}
909 };
910
911 static const struct pmc_bit_map *mtl_ioem_lpm_maps[] = {
912 mtl_ioep_clocksource_status_map,
913 mtl_ioep_power_gating_status_0_map,
914 mtl_ioem_power_gating_status_1_map,
915 mtl_ioep_power_gating_status_2_map,
916 mtl_ioep_d3_status_0_map,
917 mtl_ioep_d3_status_1_map,
918 mtl_ioep_d3_status_2_map,
919 mtl_ioep_d3_status_3_map,
920 mtl_ioep_vnn_req_status_0_map,
921 mtl_ioep_vnn_req_status_1_map,
922 mtl_ioep_vnn_req_status_2_map,
923 mtl_ioep_vnn_req_status_3_map,
924 mtl_ioep_vnn_misc_status_map,
925 mtl_socm_signal_status_map,
926 NULL
927 };
928
929 static const struct pmc_reg_map mtl_ioem_reg_map = {
930 .regmap_length = MTL_IOE_PMC_MMIO_REG_LEN,
931 .pfear_sts = ext_mtl_ioem_pfear_map,
932 .ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,
933 .ppfear_buckets = MTL_IOE_PPFEAR_NUM_ENTRIES,
934 .lpm_status_offset = MTL_LPM_STATUS_OFFSET,
935 .lpm_live_status_offset = MTL_LPM_LIVE_STATUS_OFFSET,
936 .lpm_sts = mtl_ioem_lpm_maps,
937 .ltr_show_sts = mtl_ioep_ltr_show_map,
938 .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
939 .ltr_ignore_max = ADL_NUM_IP_IGN_ALLOWED,
940 .lpm_sts_latch_en_offset = MTL_LPM_STATUS_LATCH_EN_OFFSET,
941 .lpm_num_maps = ADL_LPM_NUM_MAPS,
942 .lpm_priority_offset = MTL_LPM_PRI_OFFSET,
943 .lpm_en_offset = MTL_LPM_EN_OFFSET,
944 .lpm_res_counter_step_x2 = TGL_PMC_LPM_RES_COUNTER_STEP_X2,
945 .lpm_residency_offset = MTL_LPM_RESIDENCY_OFFSET,
946 .lpm_reg_index = MTL_LPM_REG_INDEX,
947 };
948
949 static struct pmc_info mtl_pmc_info_list[] = {
950 {
951 .guid = SOCP_LPM_REQ_GUID,
952 .devid = PMC_DEVID_MTL_SOCM,
953 .map = &mtl_socm_reg_map,
954 },
955 {
956 .guid = IOEP_LPM_REQ_GUID,
957 .devid = PMC_DEVID_MTL_IOEP,
958 .map = &mtl_ioep_reg_map,
959 },
960 {
961 .guid = IOEM_LPM_REQ_GUID,
962 .devid = PMC_DEVID_MTL_IOEM,
963 .map = &mtl_ioem_reg_map
964 },
965 {}
966 };
967
968 #define MTL_GNA_PCI_DEV 0x7e4c
969 #define MTL_IPU_PCI_DEV 0x7d19
970 #define MTL_VPU_PCI_DEV 0x7d1d
971 /*
972 * Set power state of select devices that do not have drivers to D3
973 * so that they do not block Package C entry.
974 */
mtl_d3_fixup(void)975 static void mtl_d3_fixup(void)
976 {
977 pmc_core_set_device_d3(MTL_GNA_PCI_DEV);
978 pmc_core_set_device_d3(MTL_IPU_PCI_DEV);
979 pmc_core_set_device_d3(MTL_VPU_PCI_DEV);
980 }
981
mtl_resume(struct pmc_dev * pmcdev)982 static int mtl_resume(struct pmc_dev *pmcdev)
983 {
984 mtl_d3_fixup();
985
986 return cnl_resume(pmcdev);
987 }
988
mtl_core_init(struct pmc_dev * pmcdev,struct pmc_dev_info * pmc_dev_info)989 static int mtl_core_init(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_info)
990 {
991 mtl_d3_fixup();
992 return generic_core_init(pmcdev, pmc_dev_info);
993 }
994
995 struct pmc_dev_info mtl_pmc_dev = {
996 .pci_func = 2,
997 .dmu_guid = MTL_PMT_DMU_GUID,
998 .regmap_list = mtl_pmc_info_list,
999 .map = &mtl_socm_reg_map,
1000 .suspend = cnl_suspend,
1001 .resume = mtl_resume,
1002 .init = mtl_core_init,
1003 };
1004