1 // SPDX-License-Identifier: GPL-2.0
2
3 #include <media/videobuf2-v4l2.h>
4 #include <media/videobuf2-dma-contig.h>
5 #include <media/v4l2-event.h>
6 #include <media/v4l2-mem2mem.h>
7 #include <linux/module.h>
8
9 #include "mtk_vcodec_dec.h"
10 #include "mtk_vcodec_dec_pm.h"
11 #include "vdec_drv_if.h"
12
13 /**
14 * struct mtk_stateless_control - CID control type
15 * @cfg: control configuration
16 * @codec_type: codec type (V4L2 pixel format) for CID control type
17 */
18 struct mtk_stateless_control {
19 struct v4l2_ctrl_config cfg;
20 int codec_type;
21 };
22
23 static const struct mtk_stateless_control mtk_stateless_controls[] = {
24 {
25 .cfg = {
26 .id = V4L2_CID_STATELESS_H264_SPS,
27 },
28 .codec_type = V4L2_PIX_FMT_H264_SLICE,
29 },
30 {
31 .cfg = {
32 .id = V4L2_CID_STATELESS_H264_PPS,
33 },
34 .codec_type = V4L2_PIX_FMT_H264_SLICE,
35 },
36 {
37 .cfg = {
38 .id = V4L2_CID_STATELESS_H264_SCALING_MATRIX,
39 },
40 .codec_type = V4L2_PIX_FMT_H264_SLICE,
41 },
42 {
43 .cfg = {
44 .id = V4L2_CID_STATELESS_H264_DECODE_PARAMS,
45 },
46 .codec_type = V4L2_PIX_FMT_H264_SLICE,
47 },
48 {
49 .cfg = {
50 .id = V4L2_CID_MPEG_VIDEO_H264_PROFILE,
51 .def = V4L2_MPEG_VIDEO_H264_PROFILE_MAIN,
52 .max = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH,
53 .menu_skip_mask =
54 BIT(V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE) |
55 BIT(V4L2_MPEG_VIDEO_H264_PROFILE_EXTENDED),
56 },
57 .codec_type = V4L2_PIX_FMT_H264_SLICE,
58 },
59 {
60 .cfg = {
61 .id = V4L2_CID_MPEG_VIDEO_H264_LEVEL,
62 .min = V4L2_MPEG_VIDEO_H264_LEVEL_1_0,
63 .def = V4L2_MPEG_VIDEO_H264_LEVEL_4_1,
64 .max = V4L2_MPEG_VIDEO_H264_LEVEL_4_2,
65 },
66 .codec_type = V4L2_PIX_FMT_H264_SLICE,
67 },
68 {
69 .cfg = {
70 .id = V4L2_CID_STATELESS_H264_DECODE_MODE,
71 .min = V4L2_STATELESS_H264_DECODE_MODE_FRAME_BASED,
72 .def = V4L2_STATELESS_H264_DECODE_MODE_FRAME_BASED,
73 .max = V4L2_STATELESS_H264_DECODE_MODE_FRAME_BASED,
74 },
75 .codec_type = V4L2_PIX_FMT_H264_SLICE,
76 },
77 {
78 .cfg = {
79 .id = V4L2_CID_STATELESS_H264_START_CODE,
80 .min = V4L2_STATELESS_H264_START_CODE_ANNEX_B,
81 .def = V4L2_STATELESS_H264_START_CODE_ANNEX_B,
82 .max = V4L2_STATELESS_H264_START_CODE_ANNEX_B,
83 },
84 .codec_type = V4L2_PIX_FMT_H264_SLICE,
85 },
86 {
87 .cfg = {
88 .id = V4L2_CID_STATELESS_VP8_FRAME,
89 },
90 .codec_type = V4L2_PIX_FMT_VP8_FRAME,
91 },
92 {
93 .cfg = {
94 .id = V4L2_CID_MPEG_VIDEO_VP8_PROFILE,
95 .min = V4L2_MPEG_VIDEO_VP8_PROFILE_0,
96 .def = V4L2_MPEG_VIDEO_VP8_PROFILE_0,
97 .max = V4L2_MPEG_VIDEO_VP8_PROFILE_3,
98 },
99 .codec_type = V4L2_PIX_FMT_VP8_FRAME,
100 },
101 {
102 .cfg = {
103 .id = V4L2_CID_STATELESS_VP9_FRAME,
104 },
105 .codec_type = V4L2_PIX_FMT_VP9_FRAME,
106 },
107 {
108 .cfg = {
109 .id = V4L2_CID_MPEG_VIDEO_VP9_PROFILE,
110 .min = V4L2_MPEG_VIDEO_VP9_PROFILE_0,
111 .def = V4L2_MPEG_VIDEO_VP9_PROFILE_0,
112 .max = V4L2_MPEG_VIDEO_VP9_PROFILE_2,
113 .menu_skip_mask = BIT(V4L2_MPEG_VIDEO_VP9_PROFILE_1),
114 },
115 .codec_type = V4L2_PIX_FMT_VP9_FRAME,
116 },
117 {
118 .cfg = {
119 .id = V4L2_CID_MPEG_VIDEO_VP9_LEVEL,
120 .min = V4L2_MPEG_VIDEO_VP9_LEVEL_1_0,
121 .def = V4L2_MPEG_VIDEO_VP9_LEVEL_4_0,
122 .max = V4L2_MPEG_VIDEO_VP9_LEVEL_4_1,
123 },
124 .codec_type = V4L2_PIX_FMT_VP9_FRAME,
125 },
126 {
127 .cfg = {
128 .id = V4L2_CID_STATELESS_HEVC_SPS,
129 },
130 .codec_type = V4L2_PIX_FMT_HEVC_SLICE,
131 },
132 {
133 .cfg = {
134 .id = V4L2_CID_STATELESS_HEVC_PPS,
135 },
136 .codec_type = V4L2_PIX_FMT_HEVC_SLICE,
137 },
138 {
139 .cfg = {
140 .id = V4L2_CID_STATELESS_HEVC_SCALING_MATRIX,
141 },
142 .codec_type = V4L2_PIX_FMT_HEVC_SLICE,
143 },
144 {
145 .cfg = {
146 .id = V4L2_CID_STATELESS_HEVC_DECODE_PARAMS,
147 },
148 .codec_type = V4L2_PIX_FMT_HEVC_SLICE,
149 },
150 {
151 .cfg = {
152 .id = V4L2_CID_MPEG_VIDEO_HEVC_PROFILE,
153 .def = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
154 .max = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10,
155 .menu_skip_mask =
156 BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE),
157 },
158 .codec_type = V4L2_PIX_FMT_HEVC_SLICE,
159 },
160 {
161 .cfg = {
162 .id = V4L2_CID_MPEG_VIDEO_HEVC_LEVEL,
163 .min = V4L2_MPEG_VIDEO_HEVC_LEVEL_1,
164 .def = V4L2_MPEG_VIDEO_HEVC_LEVEL_4,
165 .max = V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1,
166 },
167 .codec_type = V4L2_PIX_FMT_HEVC_SLICE,
168 },
169
170 {
171 .cfg = {
172 .id = V4L2_CID_STATELESS_HEVC_DECODE_MODE,
173 .min = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED,
174 .def = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED,
175 .max = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED,
176 },
177 .codec_type = V4L2_PIX_FMT_HEVC_SLICE,
178 },
179 {
180 .cfg = {
181 .id = V4L2_CID_STATELESS_HEVC_START_CODE,
182 .min = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B,
183 .def = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B,
184 .max = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B,
185 },
186 .codec_type = V4L2_PIX_FMT_HEVC_SLICE,
187 },
188 {
189 .cfg = {
190 .id = V4L2_CID_STATELESS_AV1_SEQUENCE,
191
192 },
193 .codec_type = V4L2_PIX_FMT_AV1_FRAME,
194 },
195 {
196 .cfg = {
197 .id = V4L2_CID_STATELESS_AV1_FRAME,
198
199 },
200 .codec_type = V4L2_PIX_FMT_AV1_FRAME,
201 },
202 {
203 .cfg = {
204 .id = V4L2_CID_STATELESS_AV1_TILE_GROUP_ENTRY,
205 .dims = { V4L2_AV1_MAX_TILE_COUNT },
206
207 },
208 .codec_type = V4L2_PIX_FMT_AV1_FRAME,
209 },
210 {
211 .cfg = {
212 .id = V4L2_CID_MPEG_VIDEO_AV1_PROFILE,
213 .min = V4L2_MPEG_VIDEO_AV1_PROFILE_MAIN,
214 .def = V4L2_MPEG_VIDEO_AV1_PROFILE_MAIN,
215 .max = V4L2_MPEG_VIDEO_AV1_PROFILE_MAIN,
216 },
217 .codec_type = V4L2_PIX_FMT_AV1_FRAME,
218 },
219 {
220 .cfg = {
221 .id = V4L2_CID_MPEG_VIDEO_AV1_LEVEL,
222 .min = V4L2_MPEG_VIDEO_AV1_LEVEL_2_0,
223 .def = V4L2_MPEG_VIDEO_AV1_LEVEL_4_0,
224 .max = V4L2_MPEG_VIDEO_AV1_LEVEL_5_1,
225 },
226 .codec_type = V4L2_PIX_FMT_AV1_FRAME,
227 },
228 };
229
230 #define NUM_CTRLS ARRAY_SIZE(mtk_stateless_controls)
231
232 static struct mtk_video_fmt mtk_video_formats[9];
233
234 static struct mtk_video_fmt default_out_format;
235 static struct mtk_video_fmt default_cap_format;
236 static unsigned int num_formats;
237
238 static const struct v4l2_frmsize_stepwise stepwise_fhd = {
239 .min_width = MTK_VDEC_MIN_W,
240 .max_width = MTK_VDEC_MAX_W,
241 .step_width = 16,
242 .min_height = MTK_VDEC_MIN_H,
243 .max_height = MTK_VDEC_MAX_H,
244 .step_height = 16
245 };
246
mtk_vdec_stateless_cap_to_disp(struct mtk_vcodec_dec_ctx * ctx,int error,struct media_request * src_buf_req)247 static void mtk_vdec_stateless_cap_to_disp(struct mtk_vcodec_dec_ctx *ctx, int error,
248 struct media_request *src_buf_req)
249 {
250 struct vb2_v4l2_buffer *vb2_dst;
251 enum vb2_buffer_state state;
252
253 if (error)
254 state = VB2_BUF_STATE_ERROR;
255 else
256 state = VB2_BUF_STATE_DONE;
257
258 vb2_dst = v4l2_m2m_dst_buf_remove(ctx->m2m_ctx);
259 if (vb2_dst) {
260 v4l2_m2m_buf_done(vb2_dst, state);
261 mtk_v4l2_vdec_dbg(2, ctx, "free frame buffer id:%d to done list",
262 vb2_dst->vb2_buf.index);
263 } else {
264 mtk_v4l2_vdec_err(ctx, "dst buffer is NULL");
265 }
266
267 if (src_buf_req)
268 v4l2_ctrl_request_complete(src_buf_req, &ctx->ctrl_hdl);
269 }
270
vdec_get_cap_buffer(struct mtk_vcodec_dec_ctx * ctx)271 static struct vdec_fb *vdec_get_cap_buffer(struct mtk_vcodec_dec_ctx *ctx)
272 {
273 struct mtk_video_dec_buf *framebuf;
274 struct vb2_v4l2_buffer *vb2_v4l2;
275 struct vb2_buffer *dst_buf;
276 struct vdec_fb *pfb;
277
278 vb2_v4l2 = v4l2_m2m_next_dst_buf(ctx->m2m_ctx);
279 if (!vb2_v4l2) {
280 mtk_v4l2_vdec_dbg(1, ctx, "[%d] dst_buf empty!!", ctx->id);
281 return NULL;
282 }
283
284 dst_buf = &vb2_v4l2->vb2_buf;
285 framebuf = container_of(vb2_v4l2, struct mtk_video_dec_buf, m2m_buf.vb);
286
287 pfb = &framebuf->frame_buffer;
288 pfb->base_y.va = vb2_plane_vaddr(dst_buf, 0);
289 pfb->base_y.dma_addr = vb2_dma_contig_plane_dma_addr(dst_buf, 0);
290 pfb->base_y.size = ctx->q_data[MTK_Q_DATA_DST].sizeimage[0];
291
292 if (ctx->q_data[MTK_Q_DATA_DST].fmt->num_planes == 2) {
293 pfb->base_c.va = vb2_plane_vaddr(dst_buf, 1);
294 pfb->base_c.dma_addr =
295 vb2_dma_contig_plane_dma_addr(dst_buf, 1);
296 pfb->base_c.size = ctx->q_data[MTK_Q_DATA_DST].sizeimage[1];
297 }
298 mtk_v4l2_vdec_dbg(1, ctx,
299 "id=%d Framebuf pfb=%p VA=%p Y/C_DMA=%pad_%pad Sz=%zx frame_count = %d",
300 dst_buf->index, pfb, pfb->base_y.va, &pfb->base_y.dma_addr,
301 &pfb->base_c.dma_addr, pfb->base_y.size, ctx->decoded_frame_cnt);
302
303 return pfb;
304 }
305
vb2ops_vdec_buf_request_complete(struct vb2_buffer * vb)306 static void vb2ops_vdec_buf_request_complete(struct vb2_buffer *vb)
307 {
308 struct mtk_vcodec_dec_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
309
310 v4l2_ctrl_request_complete(vb->req_obj.req, &ctx->ctrl_hdl);
311 }
312
mtk_vdec_worker(struct work_struct * work)313 static void mtk_vdec_worker(struct work_struct *work)
314 {
315 struct mtk_vcodec_dec_ctx *ctx =
316 container_of(work, struct mtk_vcodec_dec_ctx, decode_work);
317 struct mtk_vcodec_dec_dev *dev = ctx->dev;
318 struct vb2_v4l2_buffer *vb2_v4l2_src;
319 struct vb2_buffer *vb2_src;
320 struct mtk_vcodec_mem *bs_src;
321 struct mtk_video_dec_buf *dec_buf_src;
322 struct media_request *src_buf_req;
323 enum vb2_buffer_state state;
324 bool res_chg = false;
325 int ret;
326
327 vb2_v4l2_src = v4l2_m2m_next_src_buf(ctx->m2m_ctx);
328 if (!vb2_v4l2_src) {
329 v4l2_m2m_job_finish(dev->m2m_dev_dec, ctx->m2m_ctx);
330 mtk_v4l2_vdec_dbg(1, ctx, "[%d] no available source buffer", ctx->id);
331 return;
332 }
333
334 vb2_src = &vb2_v4l2_src->vb2_buf;
335 dec_buf_src = container_of(vb2_v4l2_src, struct mtk_video_dec_buf,
336 m2m_buf.vb);
337 bs_src = &dec_buf_src->bs_buffer;
338
339 mtk_v4l2_vdec_dbg(3, ctx, "[%d] (%d) id=%d, vb=%p", ctx->id,
340 vb2_src->vb2_queue->type, vb2_src->index, vb2_src);
341
342 bs_src->va = vb2_plane_vaddr(vb2_src, 0);
343 bs_src->dma_addr = vb2_dma_contig_plane_dma_addr(vb2_src, 0);
344 bs_src->size = (size_t)vb2_src->planes[0].bytesused;
345 if (!bs_src->va) {
346 v4l2_m2m_job_finish(dev->m2m_dev_dec, ctx->m2m_ctx);
347 mtk_v4l2_vdec_err(ctx, "[%d] id=%d source buffer is NULL", ctx->id,
348 vb2_src->index);
349 return;
350 }
351
352 mtk_v4l2_vdec_dbg(3, ctx, "[%d] Bitstream VA=%p DMA=%pad Size=%zx vb=%p",
353 ctx->id, bs_src->va, &bs_src->dma_addr, bs_src->size, vb2_src);
354 /* Apply request controls. */
355 src_buf_req = vb2_src->req_obj.req;
356 if (src_buf_req)
357 v4l2_ctrl_request_setup(src_buf_req, &ctx->ctrl_hdl);
358 else
359 mtk_v4l2_vdec_err(ctx, "vb2 buffer media request is NULL");
360
361 ret = vdec_if_decode(ctx, bs_src, NULL, &res_chg);
362 if (ret && ret != -EAGAIN) {
363 mtk_v4l2_vdec_err(ctx,
364 "[%d] decode src_buf[%d] sz=0x%zx pts=%llu ret=%d res_chg=%d",
365 ctx->id, vb2_src->index, bs_src->size,
366 vb2_src->timestamp, ret, res_chg);
367 if (ret == -EIO) {
368 mutex_lock(&ctx->lock);
369 dec_buf_src->error = true;
370 mutex_unlock(&ctx->lock);
371 }
372 }
373
374 state = ret ? VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE;
375 if (!IS_VDEC_LAT_ARCH(dev->vdec_pdata->hw_arch) ||
376 ctx->current_codec == V4L2_PIX_FMT_VP8_FRAME) {
377 v4l2_m2m_buf_done_and_job_finish(dev->m2m_dev_dec, ctx->m2m_ctx, state);
378 if (src_buf_req)
379 v4l2_ctrl_request_complete(src_buf_req, &ctx->ctrl_hdl);
380 } else {
381 if (ret != -EAGAIN) {
382 v4l2_m2m_src_buf_remove(ctx->m2m_ctx);
383 v4l2_m2m_buf_done(vb2_v4l2_src, state);
384 }
385 v4l2_m2m_job_finish(dev->m2m_dev_dec, ctx->m2m_ctx);
386 }
387 }
388
vb2ops_vdec_stateless_buf_queue(struct vb2_buffer * vb)389 static void vb2ops_vdec_stateless_buf_queue(struct vb2_buffer *vb)
390 {
391 struct mtk_vcodec_dec_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
392 struct vb2_v4l2_buffer *vb2_v4l2 = to_vb2_v4l2_buffer(vb);
393
394 mtk_v4l2_vdec_dbg(3, ctx, "[%d] (%d) id=%d, vb=%p", ctx->id, vb->vb2_queue->type,
395 vb->index, vb);
396
397 mutex_lock(&ctx->lock);
398 v4l2_m2m_buf_queue(ctx->m2m_ctx, vb2_v4l2);
399 mutex_unlock(&ctx->lock);
400 if (vb->vb2_queue->type != V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)
401 return;
402
403 /* If an OUTPUT buffer, we may need to update the state */
404 if (ctx->state == MTK_STATE_INIT) {
405 ctx->state = MTK_STATE_HEADER;
406 mtk_v4l2_vdec_dbg(1, ctx, "Init driver from init to header.");
407 } else {
408 mtk_v4l2_vdec_dbg(3, ctx, "[%d] already init driver %d", ctx->id, ctx->state);
409 }
410 }
411
mtk_vdec_flush_decoder(struct mtk_vcodec_dec_ctx * ctx)412 static int mtk_vdec_flush_decoder(struct mtk_vcodec_dec_ctx *ctx)
413 {
414 bool res_chg;
415
416 return vdec_if_decode(ctx, NULL, NULL, &res_chg);
417 }
418
mtk_vcodec_get_pic_info(struct mtk_vcodec_dec_ctx * ctx)419 static int mtk_vcodec_get_pic_info(struct mtk_vcodec_dec_ctx *ctx)
420 {
421 struct mtk_q_data *q_data;
422 int ret = 0;
423
424 q_data = &ctx->q_data[MTK_Q_DATA_DST];
425 if (q_data->fmt->num_planes == 1) {
426 mtk_v4l2_vdec_err(ctx, "[%d]Error!! 10bit mode not support one plane", ctx->id);
427 return -EINVAL;
428 }
429
430 ctx->capture_fourcc = q_data->fmt->fourcc;
431 ret = vdec_if_get_param(ctx, GET_PARAM_PIC_INFO, &ctx->picinfo);
432 if (ret) {
433 mtk_v4l2_vdec_err(ctx, "[%d]Error!! Get GET_PARAM_PICTURE_INFO Fail", ctx->id);
434 return ret;
435 }
436
437 ctx->last_decoded_picinfo = ctx->picinfo;
438
439 q_data->sizeimage[0] = ctx->picinfo.fb_sz[0];
440 q_data->bytesperline[0] = ctx->picinfo.buf_w * 5 / 4;
441
442 q_data->sizeimage[1] = ctx->picinfo.fb_sz[1];
443 q_data->bytesperline[1] = ctx->picinfo.buf_w * 5 / 4;
444
445 q_data->coded_width = ctx->picinfo.buf_w;
446 q_data->coded_height = ctx->picinfo.buf_h;
447 mtk_v4l2_vdec_dbg(1, ctx, "[%d] wxh=%dx%d pic wxh=%dx%d sz[0]=0x%x sz[1]=0x%x",
448 ctx->id, ctx->picinfo.buf_w, ctx->picinfo.buf_h,
449 ctx->picinfo.pic_w, ctx->picinfo.pic_h,
450 q_data->sizeimage[0], q_data->sizeimage[1]);
451
452 return ret;
453 }
454
mtk_vdec_s_ctrl(struct v4l2_ctrl * ctrl)455 static int mtk_vdec_s_ctrl(struct v4l2_ctrl *ctrl)
456 {
457 struct mtk_vcodec_dec_ctx *ctx = ctrl_to_dec_ctx(ctrl);
458 struct v4l2_ctrl_h264_sps *h264;
459 struct v4l2_ctrl_hevc_sps *h265;
460 struct v4l2_ctrl_vp9_frame *frame;
461 struct v4l2_ctrl_av1_sequence *seq;
462 struct v4l2_ctrl *hdr_ctrl;
463 const struct mtk_vcodec_dec_pdata *dec_pdata = ctx->dev->vdec_pdata;
464 const struct mtk_video_fmt *fmt;
465 int i = 0, ret = 0;
466
467 hdr_ctrl = ctrl;
468 if (!hdr_ctrl || !hdr_ctrl->p_new.p)
469 return -EINVAL;
470
471 switch (hdr_ctrl->id) {
472 case V4L2_CID_STATELESS_H264_SPS:
473 h264 = (struct v4l2_ctrl_h264_sps *)hdr_ctrl->p_new.p;
474
475 if (h264->bit_depth_chroma_minus8 == 2 && h264->bit_depth_luma_minus8 == 2) {
476 ctx->is_10bit_bitstream = true;
477 } else if (h264->bit_depth_chroma_minus8 != 0 &&
478 h264->bit_depth_luma_minus8 != 0) {
479 mtk_v4l2_vdec_err(ctx, "H264: chroma_minus8:%d, luma_minus8:%d",
480 h264->bit_depth_chroma_minus8,
481 h264->bit_depth_luma_minus8);
482 return -EINVAL;
483 }
484 break;
485 case V4L2_CID_STATELESS_HEVC_SPS:
486 h265 = (struct v4l2_ctrl_hevc_sps *)hdr_ctrl->p_new.p;
487
488 if (h265->bit_depth_chroma_minus8 == 2 && h265->bit_depth_luma_minus8 == 2) {
489 ctx->is_10bit_bitstream = true;
490 } else if (h265->bit_depth_chroma_minus8 != 0 &&
491 h265->bit_depth_luma_minus8 != 0) {
492 mtk_v4l2_vdec_err(ctx, "HEVC: chroma_minus8:%d, luma_minus8:%d",
493 h265->bit_depth_chroma_minus8,
494 h265->bit_depth_luma_minus8);
495 return -EINVAL;
496 }
497 break;
498 case V4L2_CID_STATELESS_VP9_FRAME:
499 frame = (struct v4l2_ctrl_vp9_frame *)hdr_ctrl->p_new.p;
500
501 if (frame->bit_depth == 10) {
502 ctx->is_10bit_bitstream = true;
503 } else if (frame->bit_depth != 8) {
504 mtk_v4l2_vdec_err(ctx, "VP9: bit_depth:%d", frame->bit_depth);
505 return -EINVAL;
506 }
507 break;
508 case V4L2_CID_STATELESS_AV1_SEQUENCE:
509 seq = (struct v4l2_ctrl_av1_sequence *)hdr_ctrl->p_new.p;
510
511 if (seq->bit_depth == 10) {
512 ctx->is_10bit_bitstream = true;
513 } else if (seq->bit_depth != 8) {
514 mtk_v4l2_vdec_err(ctx, "AV1: bit_depth:%d", seq->bit_depth);
515 return -EINVAL;
516 }
517 break;
518 default:
519 mtk_v4l2_vdec_dbg(3, ctx, "Not supported to set ctrl id: 0x%x\n", hdr_ctrl->id);
520 return ret;
521 }
522
523 if (!ctx->is_10bit_bitstream)
524 return ret;
525
526 for (i = 0; i < *dec_pdata->num_formats; i++) {
527 fmt = &dec_pdata->vdec_formats[i];
528 if (fmt->fourcc == V4L2_PIX_FMT_MT2110R &&
529 hdr_ctrl->id == V4L2_CID_STATELESS_H264_SPS) {
530 ctx->q_data[MTK_Q_DATA_DST].fmt = fmt;
531 break;
532 }
533
534 if (fmt->fourcc == V4L2_PIX_FMT_MT2110T &&
535 (hdr_ctrl->id == V4L2_CID_STATELESS_HEVC_SPS ||
536 hdr_ctrl->id == V4L2_CID_STATELESS_VP9_FRAME ||
537 hdr_ctrl->id == V4L2_CID_STATELESS_AV1_SEQUENCE)) {
538 ctx->q_data[MTK_Q_DATA_DST].fmt = fmt;
539 break;
540 }
541 }
542 ret = mtk_vcodec_get_pic_info(ctx);
543
544 return ret;
545 }
546
547 static const struct v4l2_ctrl_ops mtk_vcodec_dec_ctrl_ops = {
548 .s_ctrl = mtk_vdec_s_ctrl,
549 };
550
mtk_vcodec_dec_fill_h264_level(struct v4l2_ctrl_config * cfg,struct mtk_vcodec_dec_ctx * ctx)551 static void mtk_vcodec_dec_fill_h264_level(struct v4l2_ctrl_config *cfg,
552 struct mtk_vcodec_dec_ctx *ctx)
553 {
554 switch (ctx->dev->chip_name) {
555 case MTK_VDEC_MT8192:
556 case MTK_VDEC_MT8188:
557 cfg->max = V4L2_MPEG_VIDEO_H264_LEVEL_5_2;
558 break;
559 case MTK_VDEC_MT8195:
560 cfg->max = V4L2_MPEG_VIDEO_H264_LEVEL_6_0;
561 break;
562 case MTK_VDEC_MT8183:
563 case MTK_VDEC_MT8186:
564 cfg->max = V4L2_MPEG_VIDEO_H264_LEVEL_4_2;
565 break;
566 default:
567 cfg->max = V4L2_MPEG_VIDEO_H264_LEVEL_4_1;
568 break;
569 }
570 }
571
mtk_vcodec_dec_fill_h264_profile(struct v4l2_ctrl_config * cfg,struct mtk_vcodec_dec_ctx * ctx)572 static void mtk_vcodec_dec_fill_h264_profile(struct v4l2_ctrl_config *cfg,
573 struct mtk_vcodec_dec_ctx *ctx)
574 {
575 switch (ctx->dev->chip_name) {
576 case MTK_VDEC_MT8188:
577 case MTK_VDEC_MT8195:
578 cfg->max = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_10;
579 break;
580 default:
581 cfg->max = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH;
582 break;
583 }
584 }
585
mtk_vcodec_dec_fill_h265_level(struct v4l2_ctrl_config * cfg,struct mtk_vcodec_dec_ctx * ctx)586 static void mtk_vcodec_dec_fill_h265_level(struct v4l2_ctrl_config *cfg,
587 struct mtk_vcodec_dec_ctx *ctx)
588 {
589 switch (ctx->dev->chip_name) {
590 case MTK_VDEC_MT8188:
591 cfg->max = V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1;
592 break;
593 case MTK_VDEC_MT8195:
594 cfg->max = V4L2_MPEG_VIDEO_HEVC_LEVEL_5_2;
595 break;
596 default:
597 cfg->max = V4L2_MPEG_VIDEO_HEVC_LEVEL_4;
598 break;
599 }
600 }
601
mtk_vcodec_dec_fill_h265_profile(struct v4l2_ctrl_config * cfg,struct mtk_vcodec_dec_ctx * ctx)602 static void mtk_vcodec_dec_fill_h265_profile(struct v4l2_ctrl_config *cfg,
603 struct mtk_vcodec_dec_ctx *ctx)
604 {
605 switch (ctx->dev->chip_name) {
606 case MTK_VDEC_MT8188:
607 case MTK_VDEC_MT8195:
608 cfg->max = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10;
609 break;
610 default:
611 cfg->max = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE;
612 break;
613 }
614 }
615
mtk_vcodec_dec_fill_vp9_level(struct v4l2_ctrl_config * cfg,struct mtk_vcodec_dec_ctx * ctx)616 static void mtk_vcodec_dec_fill_vp9_level(struct v4l2_ctrl_config *cfg,
617 struct mtk_vcodec_dec_ctx *ctx)
618 {
619 switch (ctx->dev->chip_name) {
620 case MTK_VDEC_MT8192:
621 case MTK_VDEC_MT8188:
622 cfg->max = V4L2_MPEG_VIDEO_VP9_LEVEL_5_1;
623 break;
624 case MTK_VDEC_MT8195:
625 cfg->max = V4L2_MPEG_VIDEO_VP9_LEVEL_5_2;
626 break;
627 case MTK_VDEC_MT8186:
628 cfg->max = V4L2_MPEG_VIDEO_VP9_LEVEL_4_1;
629 break;
630 default:
631 cfg->max = V4L2_MPEG_VIDEO_VP9_LEVEL_4_0;
632 break;
633 }
634 }
635
mtk_vcodec_dec_fill_vp9_profile(struct v4l2_ctrl_config * cfg,struct mtk_vcodec_dec_ctx * ctx)636 static void mtk_vcodec_dec_fill_vp9_profile(struct v4l2_ctrl_config *cfg,
637 struct mtk_vcodec_dec_ctx *ctx)
638 {
639 switch (ctx->dev->chip_name) {
640 case MTK_VDEC_MT8188:
641 case MTK_VDEC_MT8195:
642 cfg->max = V4L2_MPEG_VIDEO_VP9_PROFILE_2;
643 break;
644 default:
645 cfg->max = V4L2_MPEG_VIDEO_VP9_PROFILE_1;
646 break;
647 }
648 }
649
mtk_vcodec_dec_reset_controls(struct v4l2_ctrl_config * cfg,struct mtk_vcodec_dec_ctx * ctx)650 static void mtk_vcodec_dec_reset_controls(struct v4l2_ctrl_config *cfg,
651 struct mtk_vcodec_dec_ctx *ctx)
652 {
653 switch (cfg->id) {
654 case V4L2_CID_MPEG_VIDEO_H264_LEVEL:
655 mtk_vcodec_dec_fill_h264_level(cfg, ctx);
656 mtk_v4l2_vdec_dbg(3, ctx, "h264 supported level: %lld %lld", cfg->max, cfg->def);
657 break;
658 case V4L2_CID_MPEG_VIDEO_HEVC_LEVEL:
659 mtk_vcodec_dec_fill_h265_level(cfg, ctx);
660 mtk_v4l2_vdec_dbg(3, ctx, "h265 supported level: %lld %lld", cfg->max, cfg->def);
661 break;
662 case V4L2_CID_MPEG_VIDEO_VP9_LEVEL:
663 mtk_vcodec_dec_fill_vp9_level(cfg, ctx);
664 mtk_v4l2_vdec_dbg(3, ctx, "vp9 supported level: %lld %lld", cfg->max, cfg->def);
665 break;
666 case V4L2_CID_MPEG_VIDEO_H264_PROFILE:
667 mtk_vcodec_dec_fill_h264_profile(cfg, ctx);
668 mtk_v4l2_vdec_dbg(3, ctx, "h264 supported profile: %lld %lld", cfg->max,
669 cfg->menu_skip_mask);
670 break;
671 case V4L2_CID_MPEG_VIDEO_HEVC_PROFILE:
672 mtk_vcodec_dec_fill_h265_profile(cfg, ctx);
673 mtk_v4l2_vdec_dbg(3, ctx, "h265 supported profile: %lld %lld", cfg->max,
674 cfg->menu_skip_mask);
675 break;
676 case V4L2_CID_MPEG_VIDEO_VP9_PROFILE:
677 mtk_vcodec_dec_fill_vp9_profile(cfg, ctx);
678 mtk_v4l2_vdec_dbg(3, ctx, "vp9 supported profile: %lld %lld", cfg->max,
679 cfg->menu_skip_mask);
680 break;
681 default:
682 break;
683 }
684 }
685
mtk_vcodec_dec_ctrls_setup(struct mtk_vcodec_dec_ctx * ctx)686 static int mtk_vcodec_dec_ctrls_setup(struct mtk_vcodec_dec_ctx *ctx)
687 {
688 unsigned int i;
689
690 v4l2_ctrl_handler_init(&ctx->ctrl_hdl, NUM_CTRLS);
691 if (ctx->ctrl_hdl.error) {
692 mtk_v4l2_vdec_err(ctx, "v4l2_ctrl_handler_init failed\n");
693 return ctx->ctrl_hdl.error;
694 }
695
696 for (i = 0; i < NUM_CTRLS; i++) {
697 struct v4l2_ctrl_config cfg = mtk_stateless_controls[i].cfg;
698 cfg.ops = &mtk_vcodec_dec_ctrl_ops;
699
700 mtk_vcodec_dec_reset_controls(&cfg, ctx);
701 v4l2_ctrl_new_custom(&ctx->ctrl_hdl, &cfg, NULL);
702 if (ctx->ctrl_hdl.error) {
703 mtk_v4l2_vdec_err(ctx, "Adding control %d failed %d", i,
704 ctx->ctrl_hdl.error);
705 return ctx->ctrl_hdl.error;
706 }
707 }
708
709 v4l2_ctrl_handler_setup(&ctx->ctrl_hdl);
710
711 return 0;
712 }
713
fops_media_request_validate(struct media_request * mreq)714 static int fops_media_request_validate(struct media_request *mreq)
715 {
716 const unsigned int buffer_cnt = vb2_request_buffer_cnt(mreq);
717
718 switch (buffer_cnt) {
719 case 1:
720 /* We expect exactly one buffer with the request */
721 break;
722 case 0:
723 pr_debug(MTK_DBG_VCODEC_STR "No buffer provided with the request.");
724 return -ENOENT;
725 default:
726 pr_debug(MTK_DBG_VCODEC_STR "Too many buffers (%d) provided with the request.",
727 buffer_cnt);
728 return -EINVAL;
729 }
730
731 return vb2_request_validate(mreq);
732 }
733
734 const struct media_device_ops mtk_vcodec_media_ops = {
735 .req_validate = fops_media_request_validate,
736 .req_queue = v4l2_m2m_request_queue,
737 };
738
mtk_vcodec_add_formats(unsigned int fourcc,struct mtk_vcodec_dec_ctx * ctx)739 static void mtk_vcodec_add_formats(unsigned int fourcc,
740 struct mtk_vcodec_dec_ctx *ctx)
741 {
742 struct mtk_vcodec_dec_dev *dev = ctx->dev;
743 const struct mtk_vcodec_dec_pdata *pdata = dev->vdec_pdata;
744 int count_formats = *pdata->num_formats;
745
746 switch (fourcc) {
747 case V4L2_PIX_FMT_H264_SLICE:
748 case V4L2_PIX_FMT_VP8_FRAME:
749 case V4L2_PIX_FMT_VP9_FRAME:
750 case V4L2_PIX_FMT_HEVC_SLICE:
751 case V4L2_PIX_FMT_AV1_FRAME:
752 mtk_video_formats[count_formats].fourcc = fourcc;
753 mtk_video_formats[count_formats].type = MTK_FMT_DEC;
754 mtk_video_formats[count_formats].num_planes = 1;
755 mtk_video_formats[count_formats].frmsize = stepwise_fhd;
756
757 if (!(ctx->dev->dec_capability & VCODEC_CAPABILITY_4K_DISABLED) &&
758 fourcc != V4L2_PIX_FMT_VP8_FRAME) {
759 mtk_video_formats[count_formats].frmsize.max_width =
760 VCODEC_DEC_4K_CODED_WIDTH;
761 mtk_video_formats[count_formats].frmsize.max_height =
762 VCODEC_DEC_4K_CODED_HEIGHT;
763 }
764 break;
765 case V4L2_PIX_FMT_MM21:
766 case V4L2_PIX_FMT_MT21C:
767 case V4L2_PIX_FMT_MT2110T:
768 case V4L2_PIX_FMT_MT2110R:
769 mtk_video_formats[count_formats].fourcc = fourcc;
770 mtk_video_formats[count_formats].type = MTK_FMT_FRAME;
771 mtk_video_formats[count_formats].num_planes = 2;
772 break;
773 default:
774 mtk_v4l2_vdec_err(ctx, "Can not add unsupported format type");
775 return;
776 }
777
778 num_formats++;
779 mtk_v4l2_vdec_dbg(3, ctx, "num_formats: %d dec_capability: 0x%x",
780 count_formats, ctx->dev->dec_capability);
781 }
782
mtk_vcodec_get_supported_formats(struct mtk_vcodec_dec_ctx * ctx)783 static void mtk_vcodec_get_supported_formats(struct mtk_vcodec_dec_ctx *ctx)
784 {
785 int cap_format_count = 0, out_format_count = 0;
786
787 if (num_formats)
788 return;
789
790 if (ctx->dev->dec_capability & MTK_VDEC_FORMAT_MT21C) {
791 mtk_vcodec_add_formats(V4L2_PIX_FMT_MT21C, ctx);
792 cap_format_count++;
793 }
794 if (ctx->dev->dec_capability & MTK_VDEC_IS_SUPPORT_10BIT) {
795 mtk_vcodec_add_formats(V4L2_PIX_FMT_MT2110T, ctx);
796 cap_format_count++;
797 mtk_vcodec_add_formats(V4L2_PIX_FMT_MT2110R, ctx);
798 cap_format_count++;
799 }
800 if (ctx->dev->dec_capability & MTK_VDEC_FORMAT_MM21) {
801 mtk_vcodec_add_formats(V4L2_PIX_FMT_MM21, ctx);
802 cap_format_count++;
803 }
804 if (ctx->dev->dec_capability & MTK_VDEC_FORMAT_H264_SLICE) {
805 mtk_vcodec_add_formats(V4L2_PIX_FMT_H264_SLICE, ctx);
806 out_format_count++;
807 }
808 if (ctx->dev->dec_capability & MTK_VDEC_FORMAT_VP8_FRAME) {
809 mtk_vcodec_add_formats(V4L2_PIX_FMT_VP8_FRAME, ctx);
810 out_format_count++;
811 }
812 if (ctx->dev->dec_capability & MTK_VDEC_FORMAT_VP9_FRAME) {
813 mtk_vcodec_add_formats(V4L2_PIX_FMT_VP9_FRAME, ctx);
814 out_format_count++;
815 }
816 if (ctx->dev->dec_capability & MTK_VDEC_FORMAT_HEVC_FRAME) {
817 mtk_vcodec_add_formats(V4L2_PIX_FMT_HEVC_SLICE, ctx);
818 out_format_count++;
819 }
820 if (ctx->dev->dec_capability & MTK_VDEC_FORMAT_AV1_FRAME) {
821 mtk_vcodec_add_formats(V4L2_PIX_FMT_AV1_FRAME, ctx);
822 out_format_count++;
823 }
824
825 if (cap_format_count)
826 default_cap_format = mtk_video_formats[cap_format_count - 1];
827 if (out_format_count)
828 default_out_format =
829 mtk_video_formats[cap_format_count + out_format_count - 1];
830 }
831
mtk_init_vdec_params(struct mtk_vcodec_dec_ctx * ctx)832 static void mtk_init_vdec_params(struct mtk_vcodec_dec_ctx *ctx)
833 {
834 struct vb2_queue *src_vq;
835
836 src_vq = v4l2_m2m_get_vq(ctx->m2m_ctx,
837 V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
838
839 if (!ctx->dev->vdec_pdata->is_subdev_supported)
840 ctx->dev->dec_capability |=
841 MTK_VDEC_FORMAT_H264_SLICE | MTK_VDEC_FORMAT_MM21;
842 mtk_vcodec_get_supported_formats(ctx);
843
844 /* Support request api for output plane */
845 src_vq->supports_requests = true;
846 src_vq->requires_requests = true;
847 }
848
vb2ops_vdec_out_buf_validate(struct vb2_buffer * vb)849 static int vb2ops_vdec_out_buf_validate(struct vb2_buffer *vb)
850 {
851 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
852
853 vbuf->field = V4L2_FIELD_NONE;
854 return 0;
855 }
856
857 static const struct vb2_ops mtk_vdec_request_vb2_ops = {
858 .queue_setup = vb2ops_vdec_queue_setup,
859 .start_streaming = vb2ops_vdec_start_streaming,
860 .stop_streaming = vb2ops_vdec_stop_streaming,
861
862 .buf_queue = vb2ops_vdec_stateless_buf_queue,
863 .buf_out_validate = vb2ops_vdec_out_buf_validate,
864 .buf_init = vb2ops_vdec_buf_init,
865 .buf_prepare = vb2ops_vdec_buf_prepare,
866 .buf_finish = vb2ops_vdec_buf_finish,
867 .buf_request_complete = vb2ops_vdec_buf_request_complete,
868 };
869
870 const struct mtk_vcodec_dec_pdata mtk_vdec_8183_pdata = {
871 .init_vdec_params = mtk_init_vdec_params,
872 .ctrls_setup = mtk_vcodec_dec_ctrls_setup,
873 .vdec_vb2_ops = &mtk_vdec_request_vb2_ops,
874 .vdec_formats = mtk_video_formats,
875 .num_formats = &num_formats,
876 .default_out_fmt = &default_out_format,
877 .default_cap_fmt = &default_cap_format,
878 .uses_stateless_api = true,
879 .worker = mtk_vdec_worker,
880 .flush_decoder = mtk_vdec_flush_decoder,
881 .cap_to_disp = mtk_vdec_stateless_cap_to_disp,
882 .get_cap_buffer = vdec_get_cap_buffer,
883 .is_subdev_supported = false,
884 .hw_arch = MTK_VDEC_PURE_SINGLE_CORE,
885 };
886
887 /* This platform data is used for one lat and one core architecture. */
888 const struct mtk_vcodec_dec_pdata mtk_lat_sig_core_pdata = {
889 .init_vdec_params = mtk_init_vdec_params,
890 .ctrls_setup = mtk_vcodec_dec_ctrls_setup,
891 .vdec_vb2_ops = &mtk_vdec_request_vb2_ops,
892 .vdec_formats = mtk_video_formats,
893 .num_formats = &num_formats,
894 .default_out_fmt = &default_out_format,
895 .default_cap_fmt = &default_cap_format,
896 .uses_stateless_api = true,
897 .worker = mtk_vdec_worker,
898 .flush_decoder = mtk_vdec_flush_decoder,
899 .cap_to_disp = mtk_vdec_stateless_cap_to_disp,
900 .get_cap_buffer = vdec_get_cap_buffer,
901 .is_subdev_supported = true,
902 .hw_arch = MTK_VDEC_LAT_SINGLE_CORE,
903 };
904
905 const struct mtk_vcodec_dec_pdata mtk_vdec_single_core_pdata = {
906 .init_vdec_params = mtk_init_vdec_params,
907 .ctrls_setup = mtk_vcodec_dec_ctrls_setup,
908 .vdec_vb2_ops = &mtk_vdec_request_vb2_ops,
909 .vdec_formats = mtk_video_formats,
910 .num_formats = &num_formats,
911 .default_out_fmt = &default_out_format,
912 .default_cap_fmt = &default_cap_format,
913 .uses_stateless_api = true,
914 .worker = mtk_vdec_worker,
915 .flush_decoder = mtk_vdec_flush_decoder,
916 .cap_to_disp = mtk_vdec_stateless_cap_to_disp,
917 .get_cap_buffer = vdec_get_cap_buffer,
918 .is_subdev_supported = true,
919 .hw_arch = MTK_VDEC_PURE_SINGLE_CORE,
920 };
921