1 /*
2 * Copyright (c) 2004 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Cisco Systems. All rights reserved.
4 * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
5 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
6 *
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
12 *
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
15 * conditions are met:
16 *
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer.
20 *
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
25 *
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 * SOFTWARE.
34 */
35
36 #include <linux/string.h>
37 #include <linux/slab.h>
38 #include <linux/sched.h>
39
40 #include <asm/io.h>
41
42 #include <rdma/ib_verbs.h>
43 #include <rdma/ib_cache.h>
44 #include <rdma/ib_pack.h>
45 #include <rdma/uverbs_ioctl.h>
46
47 #include "mthca_dev.h"
48 #include "mthca_cmd.h"
49 #include "mthca_memfree.h"
50 #include "mthca_wqe.h"
51
52 enum {
53 MTHCA_MAX_DIRECT_QP_SIZE = 4 * PAGE_SIZE,
54 MTHCA_ACK_REQ_FREQ = 10,
55 MTHCA_FLIGHT_LIMIT = 9,
56 MTHCA_UD_HEADER_SIZE = 72, /* largest UD header possible */
57 MTHCA_INLINE_HEADER_SIZE = 4, /* data segment overhead for inline */
58 MTHCA_INLINE_CHUNK_SIZE = 16 /* inline data segment chunk */
59 };
60
61 enum {
62 MTHCA_QP_STATE_RST = 0,
63 MTHCA_QP_STATE_INIT = 1,
64 MTHCA_QP_STATE_RTR = 2,
65 MTHCA_QP_STATE_RTS = 3,
66 MTHCA_QP_STATE_SQE = 4,
67 MTHCA_QP_STATE_SQD = 5,
68 MTHCA_QP_STATE_ERR = 6,
69 MTHCA_QP_STATE_DRAINING = 7
70 };
71
72 enum {
73 MTHCA_QP_ST_RC = 0x0,
74 MTHCA_QP_ST_UC = 0x1,
75 MTHCA_QP_ST_RD = 0x2,
76 MTHCA_QP_ST_UD = 0x3,
77 MTHCA_QP_ST_MLX = 0x7
78 };
79
80 enum {
81 MTHCA_QP_PM_MIGRATED = 0x3,
82 MTHCA_QP_PM_ARMED = 0x0,
83 MTHCA_QP_PM_REARM = 0x1
84 };
85
86 enum {
87 /* qp_context flags */
88 MTHCA_QP_BIT_DE = 1 << 8,
89 /* params1 */
90 MTHCA_QP_BIT_SRE = 1 << 15,
91 MTHCA_QP_BIT_SWE = 1 << 14,
92 MTHCA_QP_BIT_SAE = 1 << 13,
93 MTHCA_QP_BIT_SIC = 1 << 4,
94 MTHCA_QP_BIT_SSC = 1 << 3,
95 /* params2 */
96 MTHCA_QP_BIT_RRE = 1 << 15,
97 MTHCA_QP_BIT_RWE = 1 << 14,
98 MTHCA_QP_BIT_RAE = 1 << 13,
99 MTHCA_QP_BIT_RIC = 1 << 4,
100 MTHCA_QP_BIT_RSC = 1 << 3
101 };
102
103 enum {
104 MTHCA_SEND_DOORBELL_FENCE = 1 << 5
105 };
106
107 struct mthca_qp_path {
108 __be32 port_pkey;
109 u8 rnr_retry;
110 u8 g_mylmc;
111 __be16 rlid;
112 u8 ackto;
113 u8 mgid_index;
114 u8 static_rate;
115 u8 hop_limit;
116 __be32 sl_tclass_flowlabel;
117 u8 rgid[16];
118 } __attribute__((packed));
119
120 struct mthca_qp_context {
121 __be32 flags;
122 __be32 tavor_sched_queue; /* Reserved on Arbel */
123 u8 mtu_msgmax;
124 u8 rq_size_stride; /* Reserved on Tavor */
125 u8 sq_size_stride; /* Reserved on Tavor */
126 u8 rlkey_arbel_sched_queue; /* Reserved on Tavor */
127 __be32 usr_page;
128 __be32 local_qpn;
129 __be32 remote_qpn;
130 u32 reserved1[2];
131 struct mthca_qp_path pri_path;
132 struct mthca_qp_path alt_path;
133 __be32 rdd;
134 __be32 pd;
135 __be32 wqe_base;
136 __be32 wqe_lkey;
137 __be32 params1;
138 __be32 reserved2;
139 __be32 next_send_psn;
140 __be32 cqn_snd;
141 __be32 snd_wqe_base_l; /* Next send WQE on Tavor */
142 __be32 snd_db_index; /* (debugging only entries) */
143 __be32 last_acked_psn;
144 __be32 ssn;
145 __be32 params2;
146 __be32 rnr_nextrecvpsn;
147 __be32 ra_buff_indx;
148 __be32 cqn_rcv;
149 __be32 rcv_wqe_base_l; /* Next recv WQE on Tavor */
150 __be32 rcv_db_index; /* (debugging only entries) */
151 __be32 qkey;
152 __be32 srqn;
153 __be32 rmsn;
154 __be16 rq_wqe_counter; /* reserved on Tavor */
155 __be16 sq_wqe_counter; /* reserved on Tavor */
156 u32 reserved3[18];
157 } __attribute__((packed));
158
159 struct mthca_qp_param {
160 __be32 opt_param_mask;
161 u32 reserved1;
162 struct mthca_qp_context context;
163 u32 reserved2[62];
164 } __attribute__((packed));
165
166 enum {
167 MTHCA_QP_OPTPAR_ALT_ADDR_PATH = 1 << 0,
168 MTHCA_QP_OPTPAR_RRE = 1 << 1,
169 MTHCA_QP_OPTPAR_RAE = 1 << 2,
170 MTHCA_QP_OPTPAR_RWE = 1 << 3,
171 MTHCA_QP_OPTPAR_PKEY_INDEX = 1 << 4,
172 MTHCA_QP_OPTPAR_Q_KEY = 1 << 5,
173 MTHCA_QP_OPTPAR_RNR_TIMEOUT = 1 << 6,
174 MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7,
175 MTHCA_QP_OPTPAR_SRA_MAX = 1 << 8,
176 MTHCA_QP_OPTPAR_RRA_MAX = 1 << 9,
177 MTHCA_QP_OPTPAR_PM_STATE = 1 << 10,
178 MTHCA_QP_OPTPAR_PORT_NUM = 1 << 11,
179 MTHCA_QP_OPTPAR_RETRY_COUNT = 1 << 12,
180 MTHCA_QP_OPTPAR_ALT_RNR_RETRY = 1 << 13,
181 MTHCA_QP_OPTPAR_ACK_TIMEOUT = 1 << 14,
182 MTHCA_QP_OPTPAR_RNR_RETRY = 1 << 15,
183 MTHCA_QP_OPTPAR_SCHED_QUEUE = 1 << 16
184 };
185
186 static const u8 mthca_opcode[] = {
187 [IB_WR_SEND] = MTHCA_OPCODE_SEND,
188 [IB_WR_SEND_WITH_IMM] = MTHCA_OPCODE_SEND_IMM,
189 [IB_WR_RDMA_WRITE] = MTHCA_OPCODE_RDMA_WRITE,
190 [IB_WR_RDMA_WRITE_WITH_IMM] = MTHCA_OPCODE_RDMA_WRITE_IMM,
191 [IB_WR_RDMA_READ] = MTHCA_OPCODE_RDMA_READ,
192 [IB_WR_ATOMIC_CMP_AND_SWP] = MTHCA_OPCODE_ATOMIC_CS,
193 [IB_WR_ATOMIC_FETCH_AND_ADD] = MTHCA_OPCODE_ATOMIC_FA,
194 };
195
is_sqp(struct mthca_dev * dev,struct mthca_qp * qp)196 static int is_sqp(struct mthca_dev *dev, struct mthca_qp *qp)
197 {
198 return qp->qpn >= dev->qp_table.sqp_start &&
199 qp->qpn <= dev->qp_table.sqp_start + 3;
200 }
201
is_qp0(struct mthca_dev * dev,struct mthca_qp * qp)202 static int is_qp0(struct mthca_dev *dev, struct mthca_qp *qp)
203 {
204 return qp->qpn >= dev->qp_table.sqp_start &&
205 qp->qpn <= dev->qp_table.sqp_start + 1;
206 }
207
get_recv_wqe(struct mthca_qp * qp,int n)208 static void *get_recv_wqe(struct mthca_qp *qp, int n)
209 {
210 if (qp->is_direct)
211 return qp->queue.direct.buf + (n << qp->rq.wqe_shift);
212 else
213 return qp->queue.page_list[(n << qp->rq.wqe_shift) >> PAGE_SHIFT].buf +
214 ((n << qp->rq.wqe_shift) & (PAGE_SIZE - 1));
215 }
216
get_send_wqe(struct mthca_qp * qp,int n)217 static void *get_send_wqe(struct mthca_qp *qp, int n)
218 {
219 if (qp->is_direct)
220 return qp->queue.direct.buf + qp->send_wqe_offset +
221 (n << qp->sq.wqe_shift);
222 else
223 return qp->queue.page_list[(qp->send_wqe_offset +
224 (n << qp->sq.wqe_shift)) >>
225 PAGE_SHIFT].buf +
226 ((qp->send_wqe_offset + (n << qp->sq.wqe_shift)) &
227 (PAGE_SIZE - 1));
228 }
229
mthca_wq_reset(struct mthca_wq * wq)230 static void mthca_wq_reset(struct mthca_wq *wq)
231 {
232 wq->next_ind = 0;
233 wq->last_comp = wq->max - 1;
234 wq->head = 0;
235 wq->tail = 0;
236 }
237
mthca_qp_event(struct mthca_dev * dev,u32 qpn,enum ib_event_type event_type)238 void mthca_qp_event(struct mthca_dev *dev, u32 qpn,
239 enum ib_event_type event_type)
240 {
241 struct mthca_qp *qp;
242 struct ib_event event;
243
244 spin_lock(&dev->qp_table.lock);
245 qp = mthca_array_get(&dev->qp_table.qp, qpn & (dev->limits.num_qps - 1));
246 if (qp)
247 ++qp->refcount;
248 spin_unlock(&dev->qp_table.lock);
249
250 if (!qp) {
251 mthca_warn(dev, "Async event %d for bogus QP %08x\n",
252 event_type, qpn);
253 return;
254 }
255
256 if (event_type == IB_EVENT_PATH_MIG)
257 qp->port = qp->alt_port;
258
259 event.device = &dev->ib_dev;
260 event.event = event_type;
261 event.element.qp = &qp->ibqp;
262 if (qp->ibqp.event_handler)
263 qp->ibqp.event_handler(&event, qp->ibqp.qp_context);
264
265 spin_lock(&dev->qp_table.lock);
266 if (!--qp->refcount)
267 wake_up(&qp->wait);
268 spin_unlock(&dev->qp_table.lock);
269 }
270
to_mthca_state(enum ib_qp_state ib_state)271 static int to_mthca_state(enum ib_qp_state ib_state)
272 {
273 switch (ib_state) {
274 case IB_QPS_RESET: return MTHCA_QP_STATE_RST;
275 case IB_QPS_INIT: return MTHCA_QP_STATE_INIT;
276 case IB_QPS_RTR: return MTHCA_QP_STATE_RTR;
277 case IB_QPS_RTS: return MTHCA_QP_STATE_RTS;
278 case IB_QPS_SQD: return MTHCA_QP_STATE_SQD;
279 case IB_QPS_SQE: return MTHCA_QP_STATE_SQE;
280 case IB_QPS_ERR: return MTHCA_QP_STATE_ERR;
281 default: return -1;
282 }
283 }
284
285 enum { RC, UC, UD, RD, RDEE, MLX, NUM_TRANS };
286
to_mthca_st(int transport)287 static int to_mthca_st(int transport)
288 {
289 switch (transport) {
290 case RC: return MTHCA_QP_ST_RC;
291 case UC: return MTHCA_QP_ST_UC;
292 case UD: return MTHCA_QP_ST_UD;
293 case RD: return MTHCA_QP_ST_RD;
294 case MLX: return MTHCA_QP_ST_MLX;
295 default: return -1;
296 }
297 }
298
store_attrs(struct mthca_sqp * sqp,const struct ib_qp_attr * attr,int attr_mask)299 static void store_attrs(struct mthca_sqp *sqp, const struct ib_qp_attr *attr,
300 int attr_mask)
301 {
302 if (attr_mask & IB_QP_PKEY_INDEX)
303 sqp->pkey_index = attr->pkey_index;
304 if (attr_mask & IB_QP_QKEY)
305 sqp->qkey = attr->qkey;
306 if (attr_mask & IB_QP_SQ_PSN)
307 sqp->send_psn = attr->sq_psn;
308 }
309
init_port(struct mthca_dev * dev,int port)310 static void init_port(struct mthca_dev *dev, int port)
311 {
312 int err;
313 struct mthca_init_ib_param param;
314
315 memset(¶m, 0, sizeof param);
316
317 param.port_width = dev->limits.port_width_cap;
318 param.vl_cap = dev->limits.vl_cap;
319 param.mtu_cap = dev->limits.mtu_cap;
320 param.gid_cap = dev->limits.gid_table_len;
321 param.pkey_cap = dev->limits.pkey_table_len;
322
323 err = mthca_INIT_IB(dev, ¶m, port);
324 if (err)
325 mthca_warn(dev, "INIT_IB failed, return code %d.\n", err);
326 }
327
get_hw_access_flags(struct mthca_qp * qp,const struct ib_qp_attr * attr,int attr_mask)328 static __be32 get_hw_access_flags(struct mthca_qp *qp, const struct ib_qp_attr *attr,
329 int attr_mask)
330 {
331 u8 dest_rd_atomic;
332 u32 access_flags;
333 u32 hw_access_flags = 0;
334
335 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
336 dest_rd_atomic = attr->max_dest_rd_atomic;
337 else
338 dest_rd_atomic = qp->resp_depth;
339
340 if (attr_mask & IB_QP_ACCESS_FLAGS)
341 access_flags = attr->qp_access_flags;
342 else
343 access_flags = qp->atomic_rd_en;
344
345 if (!dest_rd_atomic)
346 access_flags &= IB_ACCESS_REMOTE_WRITE;
347
348 if (access_flags & IB_ACCESS_REMOTE_READ)
349 hw_access_flags |= MTHCA_QP_BIT_RRE;
350 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
351 hw_access_flags |= MTHCA_QP_BIT_RAE;
352 if (access_flags & IB_ACCESS_REMOTE_WRITE)
353 hw_access_flags |= MTHCA_QP_BIT_RWE;
354
355 return cpu_to_be32(hw_access_flags);
356 }
357
to_ib_qp_state(int mthca_state)358 static inline enum ib_qp_state to_ib_qp_state(int mthca_state)
359 {
360 switch (mthca_state) {
361 case MTHCA_QP_STATE_RST: return IB_QPS_RESET;
362 case MTHCA_QP_STATE_INIT: return IB_QPS_INIT;
363 case MTHCA_QP_STATE_RTR: return IB_QPS_RTR;
364 case MTHCA_QP_STATE_RTS: return IB_QPS_RTS;
365 case MTHCA_QP_STATE_DRAINING:
366 case MTHCA_QP_STATE_SQD: return IB_QPS_SQD;
367 case MTHCA_QP_STATE_SQE: return IB_QPS_SQE;
368 case MTHCA_QP_STATE_ERR: return IB_QPS_ERR;
369 default: return -1;
370 }
371 }
372
to_ib_mig_state(int mthca_mig_state)373 static inline enum ib_mig_state to_ib_mig_state(int mthca_mig_state)
374 {
375 switch (mthca_mig_state) {
376 case 0: return IB_MIG_ARMED;
377 case 1: return IB_MIG_REARM;
378 case 3: return IB_MIG_MIGRATED;
379 default: return -1;
380 }
381 }
382
to_ib_qp_access_flags(int mthca_flags)383 static int to_ib_qp_access_flags(int mthca_flags)
384 {
385 int ib_flags = 0;
386
387 if (mthca_flags & MTHCA_QP_BIT_RRE)
388 ib_flags |= IB_ACCESS_REMOTE_READ;
389 if (mthca_flags & MTHCA_QP_BIT_RWE)
390 ib_flags |= IB_ACCESS_REMOTE_WRITE;
391 if (mthca_flags & MTHCA_QP_BIT_RAE)
392 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
393
394 return ib_flags;
395 }
396
to_rdma_ah_attr(struct mthca_dev * dev,struct rdma_ah_attr * ah_attr,struct mthca_qp_path * path)397 static void to_rdma_ah_attr(struct mthca_dev *dev,
398 struct rdma_ah_attr *ah_attr,
399 struct mthca_qp_path *path)
400 {
401 u8 port_num = (be32_to_cpu(path->port_pkey) >> 24) & 0x3;
402
403 memset(ah_attr, 0, sizeof *ah_attr);
404
405 if (port_num == 0 || port_num > dev->limits.num_ports)
406 return;
407 ah_attr->type = rdma_ah_find_type(&dev->ib_dev, port_num);
408 rdma_ah_set_port_num(ah_attr, port_num);
409
410 rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid));
411 rdma_ah_set_sl(ah_attr, be32_to_cpu(path->sl_tclass_flowlabel) >> 28);
412 rdma_ah_set_path_bits(ah_attr, path->g_mylmc & 0x7f);
413 rdma_ah_set_static_rate(ah_attr,
414 mthca_rate_to_ib(dev, path->static_rate & 0xf, port_num));
415 if (path->g_mylmc & (1 << 7)) {
416 u32 tc_fl = be32_to_cpu(path->sl_tclass_flowlabel);
417
418 rdma_ah_set_grh(ah_attr, NULL,
419 tc_fl & 0xfffff,
420 path->mgid_index &
421 (dev->limits.gid_table_len - 1),
422 path->hop_limit,
423 (tc_fl >> 20) & 0xff);
424 rdma_ah_set_dgid_raw(ah_attr, path->rgid);
425 }
426 }
427
mthca_query_qp(struct ib_qp * ibqp,struct ib_qp_attr * qp_attr,int qp_attr_mask,struct ib_qp_init_attr * qp_init_attr)428 int mthca_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
429 struct ib_qp_init_attr *qp_init_attr)
430 {
431 struct mthca_dev *dev = to_mdev(ibqp->device);
432 struct mthca_qp *qp = to_mqp(ibqp);
433 int err = 0;
434 struct mthca_mailbox *mailbox = NULL;
435 struct mthca_qp_param *qp_param;
436 struct mthca_qp_context *context;
437 int mthca_state;
438
439 mutex_lock(&qp->mutex);
440
441 if (qp->state == IB_QPS_RESET) {
442 qp_attr->qp_state = IB_QPS_RESET;
443 goto done;
444 }
445
446 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
447 if (IS_ERR(mailbox)) {
448 err = PTR_ERR(mailbox);
449 goto out;
450 }
451
452 err = mthca_QUERY_QP(dev, qp->qpn, 0, mailbox);
453 if (err) {
454 mthca_warn(dev, "QUERY_QP failed (%d)\n", err);
455 goto out_mailbox;
456 }
457
458 qp_param = mailbox->buf;
459 context = &qp_param->context;
460 mthca_state = be32_to_cpu(context->flags) >> 28;
461
462 qp->state = to_ib_qp_state(mthca_state);
463 qp_attr->qp_state = qp->state;
464 qp_attr->path_mtu = context->mtu_msgmax >> 5;
465 qp_attr->path_mig_state =
466 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
467 qp_attr->qkey = be32_to_cpu(context->qkey);
468 qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
469 qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff;
470 qp_attr->dest_qp_num = be32_to_cpu(context->remote_qpn) & 0xffffff;
471 qp_attr->qp_access_flags =
472 to_ib_qp_access_flags(be32_to_cpu(context->params2));
473
474 if (qp->transport == RC || qp->transport == UC) {
475 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
476 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
477 qp_attr->alt_pkey_index =
478 be32_to_cpu(context->alt_path.port_pkey) & 0x7f;
479 qp_attr->alt_port_num =
480 rdma_ah_get_port_num(&qp_attr->alt_ah_attr);
481 }
482
483 qp_attr->pkey_index = be32_to_cpu(context->pri_path.port_pkey) & 0x7f;
484 qp_attr->port_num =
485 (be32_to_cpu(context->pri_path.port_pkey) >> 24) & 0x3;
486
487 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
488 qp_attr->sq_draining = mthca_state == MTHCA_QP_STATE_DRAINING;
489
490 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
491
492 qp_attr->max_dest_rd_atomic =
493 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
494 qp_attr->min_rnr_timer =
495 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
496 qp_attr->timeout = context->pri_path.ackto >> 3;
497 qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7;
498 qp_attr->rnr_retry = context->pri_path.rnr_retry >> 5;
499 qp_attr->alt_timeout = context->alt_path.ackto >> 3;
500
501 done:
502 qp_attr->cur_qp_state = qp_attr->qp_state;
503 qp_attr->cap.max_send_wr = qp->sq.max;
504 qp_attr->cap.max_recv_wr = qp->rq.max;
505 qp_attr->cap.max_send_sge = qp->sq.max_gs;
506 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
507 qp_attr->cap.max_inline_data = qp->max_inline_data;
508
509 qp_init_attr->cap = qp_attr->cap;
510 qp_init_attr->sq_sig_type = qp->sq_policy;
511
512 out_mailbox:
513 mthca_free_mailbox(dev, mailbox);
514
515 out:
516 mutex_unlock(&qp->mutex);
517 return err;
518 }
519
mthca_path_set(struct mthca_dev * dev,const struct rdma_ah_attr * ah,struct mthca_qp_path * path,u8 port)520 static int mthca_path_set(struct mthca_dev *dev, const struct rdma_ah_attr *ah,
521 struct mthca_qp_path *path, u8 port)
522 {
523 path->g_mylmc = rdma_ah_get_path_bits(ah) & 0x7f;
524 path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah));
525 path->static_rate = mthca_get_rate(dev, rdma_ah_get_static_rate(ah),
526 port);
527
528 if (rdma_ah_get_ah_flags(ah) & IB_AH_GRH) {
529 const struct ib_global_route *grh = rdma_ah_read_grh(ah);
530
531 if (grh->sgid_index >= dev->limits.gid_table_len) {
532 mthca_dbg(dev, "sgid_index (%u) too large. max is %d\n",
533 grh->sgid_index, dev->limits.gid_table_len-1);
534 return -1;
535 }
536
537 path->g_mylmc |= 1 << 7;
538 path->mgid_index = grh->sgid_index;
539 path->hop_limit = grh->hop_limit;
540 path->sl_tclass_flowlabel =
541 cpu_to_be32((rdma_ah_get_sl(ah) << 28) |
542 (grh->traffic_class << 20) |
543 (grh->flow_label));
544 memcpy(path->rgid, grh->dgid.raw, 16);
545 } else
546 path->sl_tclass_flowlabel = cpu_to_be32(rdma_ah_get_sl(ah) <<
547 28);
548
549 return 0;
550 }
551
__mthca_modify_qp(struct ib_qp * ibqp,const struct ib_qp_attr * attr,int attr_mask,enum ib_qp_state cur_state,enum ib_qp_state new_state,struct ib_udata * udata)552 static int __mthca_modify_qp(struct ib_qp *ibqp,
553 const struct ib_qp_attr *attr, int attr_mask,
554 enum ib_qp_state cur_state,
555 enum ib_qp_state new_state,
556 struct ib_udata *udata)
557 {
558 struct mthca_dev *dev = to_mdev(ibqp->device);
559 struct mthca_qp *qp = to_mqp(ibqp);
560 struct mthca_ucontext *context = rdma_udata_to_drv_context(
561 udata, struct mthca_ucontext, ibucontext);
562 struct mthca_mailbox *mailbox;
563 struct mthca_qp_param *qp_param;
564 struct mthca_qp_context *qp_context;
565 u32 sqd_event = 0;
566 int err = -EINVAL;
567
568 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
569 if (IS_ERR(mailbox)) {
570 err = PTR_ERR(mailbox);
571 goto out;
572 }
573 qp_param = mailbox->buf;
574 qp_context = &qp_param->context;
575 memset(qp_param, 0, sizeof *qp_param);
576
577 qp_context->flags = cpu_to_be32((to_mthca_state(new_state) << 28) |
578 (to_mthca_st(qp->transport) << 16));
579 qp_context->flags |= cpu_to_be32(MTHCA_QP_BIT_DE);
580 if (!(attr_mask & IB_QP_PATH_MIG_STATE))
581 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11);
582 else {
583 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PM_STATE);
584 switch (attr->path_mig_state) {
585 case IB_MIG_MIGRATED:
586 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11);
587 break;
588 case IB_MIG_REARM:
589 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_REARM << 11);
590 break;
591 case IB_MIG_ARMED:
592 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_ARMED << 11);
593 break;
594 }
595 }
596
597 /* leave tavor_sched_queue as 0 */
598
599 if (qp->transport == MLX || qp->transport == UD)
600 qp_context->mtu_msgmax = (IB_MTU_2048 << 5) | 11;
601 else if (attr_mask & IB_QP_PATH_MTU) {
602 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_2048) {
603 mthca_dbg(dev, "path MTU (%u) is invalid\n",
604 attr->path_mtu);
605 goto out_mailbox;
606 }
607 qp_context->mtu_msgmax = (attr->path_mtu << 5) | 31;
608 }
609
610 if (mthca_is_memfree(dev)) {
611 if (qp->rq.max)
612 qp_context->rq_size_stride = ilog2(qp->rq.max) << 3;
613 qp_context->rq_size_stride |= qp->rq.wqe_shift - 4;
614
615 if (qp->sq.max)
616 qp_context->sq_size_stride = ilog2(qp->sq.max) << 3;
617 qp_context->sq_size_stride |= qp->sq.wqe_shift - 4;
618 }
619
620 /* leave arbel_sched_queue as 0 */
621
622 if (qp->ibqp.uobject)
623 qp_context->usr_page = cpu_to_be32(context->uar.index);
624 else
625 qp_context->usr_page = cpu_to_be32(dev->driver_uar.index);
626 qp_context->local_qpn = cpu_to_be32(qp->qpn);
627 if (attr_mask & IB_QP_DEST_QPN) {
628 qp_context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
629 }
630
631 if (qp->transport == MLX)
632 qp_context->pri_path.port_pkey |=
633 cpu_to_be32(qp->port << 24);
634 else {
635 if (attr_mask & IB_QP_PORT) {
636 qp_context->pri_path.port_pkey |=
637 cpu_to_be32(attr->port_num << 24);
638 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PORT_NUM);
639 }
640 }
641
642 if (attr_mask & IB_QP_PKEY_INDEX) {
643 qp_context->pri_path.port_pkey |=
644 cpu_to_be32(attr->pkey_index);
645 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PKEY_INDEX);
646 }
647
648 if (attr_mask & IB_QP_RNR_RETRY) {
649 qp_context->alt_path.rnr_retry = qp_context->pri_path.rnr_retry =
650 attr->rnr_retry << 5;
651 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_RETRY |
652 MTHCA_QP_OPTPAR_ALT_RNR_RETRY);
653 }
654
655 if (attr_mask & IB_QP_AV) {
656 if (mthca_path_set(dev, &attr->ah_attr, &qp_context->pri_path,
657 attr_mask & IB_QP_PORT ? attr->port_num : qp->port))
658 goto out_mailbox;
659
660 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH);
661 }
662
663 if (ibqp->qp_type == IB_QPT_RC &&
664 cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
665 u8 sched_queue = ibqp->uobject ? 0x2 : 0x1;
666
667 if (mthca_is_memfree(dev))
668 qp_context->rlkey_arbel_sched_queue |= sched_queue;
669 else
670 qp_context->tavor_sched_queue |= cpu_to_be32(sched_queue);
671
672 qp_param->opt_param_mask |=
673 cpu_to_be32(MTHCA_QP_OPTPAR_SCHED_QUEUE);
674 }
675
676 if (attr_mask & IB_QP_TIMEOUT) {
677 qp_context->pri_path.ackto = attr->timeout << 3;
678 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_ACK_TIMEOUT);
679 }
680
681 if (attr_mask & IB_QP_ALT_PATH) {
682 if (attr->alt_pkey_index >= dev->limits.pkey_table_len) {
683 mthca_dbg(dev, "Alternate P_Key index (%u) too large. max is %d\n",
684 attr->alt_pkey_index, dev->limits.pkey_table_len-1);
685 goto out_mailbox;
686 }
687
688 if (attr->alt_port_num == 0 || attr->alt_port_num > dev->limits.num_ports) {
689 mthca_dbg(dev, "Alternate port number (%u) is invalid\n",
690 attr->alt_port_num);
691 goto out_mailbox;
692 }
693
694 if (mthca_path_set(dev, &attr->alt_ah_attr, &qp_context->alt_path,
695 rdma_ah_get_port_num(&attr->alt_ah_attr)))
696 goto out_mailbox;
697
698 qp_context->alt_path.port_pkey |= cpu_to_be32(attr->alt_pkey_index |
699 attr->alt_port_num << 24);
700 qp_context->alt_path.ackto = attr->alt_timeout << 3;
701 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_ALT_ADDR_PATH);
702 }
703
704 /* leave rdd as 0 */
705 qp_context->pd = cpu_to_be32(to_mpd(ibqp->pd)->pd_num);
706 /* leave wqe_base as 0 (we always create an MR based at 0 for WQs) */
707 qp_context->wqe_lkey = cpu_to_be32(qp->mr.ibmr.lkey);
708 qp_context->params1 = cpu_to_be32((MTHCA_ACK_REQ_FREQ << 28) |
709 (MTHCA_FLIGHT_LIMIT << 24) |
710 MTHCA_QP_BIT_SWE);
711 if (qp->sq_policy == IB_SIGNAL_ALL_WR)
712 qp_context->params1 |= cpu_to_be32(MTHCA_QP_BIT_SSC);
713 if (attr_mask & IB_QP_RETRY_CNT) {
714 qp_context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
715 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RETRY_COUNT);
716 }
717
718 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
719 if (attr->max_rd_atomic) {
720 qp_context->params1 |=
721 cpu_to_be32(MTHCA_QP_BIT_SRE |
722 MTHCA_QP_BIT_SAE);
723 qp_context->params1 |=
724 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
725 }
726 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_SRA_MAX);
727 }
728
729 if (attr_mask & IB_QP_SQ_PSN)
730 qp_context->next_send_psn = cpu_to_be32(attr->sq_psn);
731 qp_context->cqn_snd = cpu_to_be32(to_mcq(ibqp->send_cq)->cqn);
732
733 if (mthca_is_memfree(dev)) {
734 qp_context->snd_wqe_base_l = cpu_to_be32(qp->send_wqe_offset);
735 qp_context->snd_db_index = cpu_to_be32(qp->sq.db_index);
736 }
737
738 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
739 if (attr->max_dest_rd_atomic)
740 qp_context->params2 |=
741 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
742
743 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RRA_MAX);
744 }
745
746 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
747 qp_context->params2 |= get_hw_access_flags(qp, attr, attr_mask);
748 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RWE |
749 MTHCA_QP_OPTPAR_RRE |
750 MTHCA_QP_OPTPAR_RAE);
751 }
752
753 qp_context->params2 |= cpu_to_be32(MTHCA_QP_BIT_RSC);
754
755 if (ibqp->srq)
756 qp_context->params2 |= cpu_to_be32(MTHCA_QP_BIT_RIC);
757
758 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
759 qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
760 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_TIMEOUT);
761 }
762 if (attr_mask & IB_QP_RQ_PSN)
763 qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
764
765 qp_context->ra_buff_indx =
766 cpu_to_be32(dev->qp_table.rdb_base +
767 ((qp->qpn & (dev->limits.num_qps - 1)) * MTHCA_RDB_ENTRY_SIZE <<
768 dev->qp_table.rdb_shift));
769
770 qp_context->cqn_rcv = cpu_to_be32(to_mcq(ibqp->recv_cq)->cqn);
771
772 if (mthca_is_memfree(dev))
773 qp_context->rcv_db_index = cpu_to_be32(qp->rq.db_index);
774
775 if (attr_mask & IB_QP_QKEY) {
776 qp_context->qkey = cpu_to_be32(attr->qkey);
777 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_Q_KEY);
778 }
779
780 if (ibqp->srq)
781 qp_context->srqn = cpu_to_be32(1 << 24 |
782 to_msrq(ibqp->srq)->srqn);
783
784 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD &&
785 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY &&
786 attr->en_sqd_async_notify)
787 sqd_event = 1 << 31;
788
789 err = mthca_MODIFY_QP(dev, cur_state, new_state, qp->qpn, 0,
790 mailbox, sqd_event);
791 if (err) {
792 mthca_warn(dev, "modify QP %d->%d returned %d.\n",
793 cur_state, new_state, err);
794 goto out_mailbox;
795 }
796
797 qp->state = new_state;
798 if (attr_mask & IB_QP_ACCESS_FLAGS)
799 qp->atomic_rd_en = attr->qp_access_flags;
800 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
801 qp->resp_depth = attr->max_dest_rd_atomic;
802 if (attr_mask & IB_QP_PORT)
803 qp->port = attr->port_num;
804 if (attr_mask & IB_QP_ALT_PATH)
805 qp->alt_port = attr->alt_port_num;
806
807 if (is_sqp(dev, qp))
808 store_attrs(to_msqp(qp), attr, attr_mask);
809
810 /*
811 * If we moved QP0 to RTR, bring the IB link up; if we moved
812 * QP0 to RESET or ERROR, bring the link back down.
813 */
814 if (is_qp0(dev, qp)) {
815 if (cur_state != IB_QPS_RTR &&
816 new_state == IB_QPS_RTR)
817 init_port(dev, qp->port);
818
819 if (cur_state != IB_QPS_RESET &&
820 cur_state != IB_QPS_ERR &&
821 (new_state == IB_QPS_RESET ||
822 new_state == IB_QPS_ERR))
823 mthca_CLOSE_IB(dev, qp->port);
824 }
825
826 /*
827 * If we moved a kernel QP to RESET, clean up all old CQ
828 * entries and reinitialize the QP.
829 */
830 if (new_state == IB_QPS_RESET && !qp->ibqp.uobject) {
831 mthca_cq_clean(dev, to_mcq(qp->ibqp.recv_cq), qp->qpn,
832 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
833 if (qp->ibqp.send_cq != qp->ibqp.recv_cq)
834 mthca_cq_clean(dev, to_mcq(qp->ibqp.send_cq), qp->qpn, NULL);
835
836 mthca_wq_reset(&qp->sq);
837 qp->sq.last = get_send_wqe(qp, qp->sq.max - 1);
838
839 mthca_wq_reset(&qp->rq);
840 qp->rq.last = get_recv_wqe(qp, qp->rq.max - 1);
841
842 if (mthca_is_memfree(dev)) {
843 *qp->sq.db = 0;
844 *qp->rq.db = 0;
845 }
846 }
847
848 out_mailbox:
849 mthca_free_mailbox(dev, mailbox);
850 out:
851 return err;
852 }
853
mthca_modify_qp(struct ib_qp * ibqp,struct ib_qp_attr * attr,int attr_mask,struct ib_udata * udata)854 int mthca_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask,
855 struct ib_udata *udata)
856 {
857 struct mthca_dev *dev = to_mdev(ibqp->device);
858 struct mthca_qp *qp = to_mqp(ibqp);
859 enum ib_qp_state cur_state, new_state;
860 int err = -EINVAL;
861
862 mutex_lock(&qp->mutex);
863 if (attr_mask & IB_QP_CUR_STATE) {
864 cur_state = attr->cur_qp_state;
865 } else {
866 spin_lock_irq(&qp->sq.lock);
867 spin_lock(&qp->rq.lock);
868 cur_state = qp->state;
869 spin_unlock(&qp->rq.lock);
870 spin_unlock_irq(&qp->sq.lock);
871 }
872
873 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
874
875 if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, attr_mask)) {
876 mthca_dbg(dev, "Bad QP transition (transport %d) "
877 "%d->%d with attr 0x%08x\n",
878 qp->transport, cur_state, new_state,
879 attr_mask);
880 goto out;
881 }
882
883 if ((attr_mask & IB_QP_PKEY_INDEX) &&
884 attr->pkey_index >= dev->limits.pkey_table_len) {
885 mthca_dbg(dev, "P_Key index (%u) too large. max is %d\n",
886 attr->pkey_index, dev->limits.pkey_table_len-1);
887 goto out;
888 }
889
890 if ((attr_mask & IB_QP_PORT) &&
891 (attr->port_num == 0 || attr->port_num > dev->limits.num_ports)) {
892 mthca_dbg(dev, "Port number (%u) is invalid\n", attr->port_num);
893 goto out;
894 }
895
896 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
897 attr->max_rd_atomic > dev->limits.max_qp_init_rdma) {
898 mthca_dbg(dev, "Max rdma_atomic as initiator %u too large (max is %d)\n",
899 attr->max_rd_atomic, dev->limits.max_qp_init_rdma);
900 goto out;
901 }
902
903 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
904 attr->max_dest_rd_atomic > 1 << dev->qp_table.rdb_shift) {
905 mthca_dbg(dev, "Max rdma_atomic as responder %u too large (max %d)\n",
906 attr->max_dest_rd_atomic, 1 << dev->qp_table.rdb_shift);
907 goto out;
908 }
909
910 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
911 err = 0;
912 goto out;
913 }
914
915 err = __mthca_modify_qp(ibqp, attr, attr_mask, cur_state, new_state,
916 udata);
917
918 out:
919 mutex_unlock(&qp->mutex);
920 return err;
921 }
922
mthca_max_data_size(struct mthca_dev * dev,struct mthca_qp * qp,int desc_sz)923 static int mthca_max_data_size(struct mthca_dev *dev, struct mthca_qp *qp, int desc_sz)
924 {
925 /*
926 * Calculate the maximum size of WQE s/g segments, excluding
927 * the next segment and other non-data segments.
928 */
929 int max_data_size = desc_sz - sizeof (struct mthca_next_seg);
930
931 switch (qp->transport) {
932 case MLX:
933 max_data_size -= 2 * sizeof (struct mthca_data_seg);
934 break;
935
936 case UD:
937 if (mthca_is_memfree(dev))
938 max_data_size -= sizeof (struct mthca_arbel_ud_seg);
939 else
940 max_data_size -= sizeof (struct mthca_tavor_ud_seg);
941 break;
942
943 default:
944 max_data_size -= sizeof (struct mthca_raddr_seg);
945 break;
946 }
947
948 return max_data_size;
949 }
950
mthca_max_inline_data(struct mthca_pd * pd,int max_data_size)951 static inline int mthca_max_inline_data(struct mthca_pd *pd, int max_data_size)
952 {
953 /* We don't support inline data for kernel QPs (yet). */
954 return pd->ibpd.uobject ? max_data_size - MTHCA_INLINE_HEADER_SIZE : 0;
955 }
956
mthca_adjust_qp_caps(struct mthca_dev * dev,struct mthca_pd * pd,struct mthca_qp * qp)957 static void mthca_adjust_qp_caps(struct mthca_dev *dev,
958 struct mthca_pd *pd,
959 struct mthca_qp *qp)
960 {
961 int max_data_size = mthca_max_data_size(dev, qp,
962 min(dev->limits.max_desc_sz,
963 1 << qp->sq.wqe_shift));
964
965 qp->max_inline_data = mthca_max_inline_data(pd, max_data_size);
966
967 qp->sq.max_gs = min_t(int, dev->limits.max_sg,
968 max_data_size / sizeof (struct mthca_data_seg));
969 qp->rq.max_gs = min_t(int, dev->limits.max_sg,
970 (min(dev->limits.max_desc_sz, 1 << qp->rq.wqe_shift) -
971 sizeof (struct mthca_next_seg)) /
972 sizeof (struct mthca_data_seg));
973 }
974
975 /*
976 * Allocate and register buffer for WQEs. qp->rq.max, sq.max,
977 * rq.max_gs and sq.max_gs must all be assigned.
978 * mthca_alloc_wqe_buf will calculate rq.wqe_shift and
979 * sq.wqe_shift (as well as send_wqe_offset, is_direct, and
980 * queue)
981 */
mthca_alloc_wqe_buf(struct mthca_dev * dev,struct mthca_pd * pd,struct mthca_qp * qp,struct ib_udata * udata)982 static int mthca_alloc_wqe_buf(struct mthca_dev *dev,
983 struct mthca_pd *pd,
984 struct mthca_qp *qp,
985 struct ib_udata *udata)
986 {
987 int size;
988 int err = -ENOMEM;
989
990 size = sizeof (struct mthca_next_seg) +
991 qp->rq.max_gs * sizeof (struct mthca_data_seg);
992
993 if (size > dev->limits.max_desc_sz)
994 return -EINVAL;
995
996 for (qp->rq.wqe_shift = 6; 1 << qp->rq.wqe_shift < size;
997 qp->rq.wqe_shift++)
998 ; /* nothing */
999
1000 size = qp->sq.max_gs * sizeof (struct mthca_data_seg);
1001 switch (qp->transport) {
1002 case MLX:
1003 size += 2 * sizeof (struct mthca_data_seg);
1004 break;
1005
1006 case UD:
1007 size += mthca_is_memfree(dev) ?
1008 sizeof (struct mthca_arbel_ud_seg) :
1009 sizeof (struct mthca_tavor_ud_seg);
1010 break;
1011
1012 case UC:
1013 size += sizeof (struct mthca_raddr_seg);
1014 break;
1015
1016 case RC:
1017 size += sizeof (struct mthca_raddr_seg);
1018 /*
1019 * An atomic op will require an atomic segment, a
1020 * remote address segment and one scatter entry.
1021 */
1022 size = max_t(int, size,
1023 sizeof (struct mthca_atomic_seg) +
1024 sizeof (struct mthca_raddr_seg) +
1025 sizeof (struct mthca_data_seg));
1026 break;
1027
1028 default:
1029 break;
1030 }
1031
1032 /* Make sure that we have enough space for a bind request */
1033 size = max_t(int, size, sizeof (struct mthca_bind_seg));
1034
1035 size += sizeof (struct mthca_next_seg);
1036
1037 if (size > dev->limits.max_desc_sz)
1038 return -EINVAL;
1039
1040 for (qp->sq.wqe_shift = 6; 1 << qp->sq.wqe_shift < size;
1041 qp->sq.wqe_shift++)
1042 ; /* nothing */
1043
1044 qp->send_wqe_offset = ALIGN(qp->rq.max << qp->rq.wqe_shift,
1045 1 << qp->sq.wqe_shift);
1046
1047 /*
1048 * If this is a userspace QP, we don't actually have to
1049 * allocate anything. All we need is to calculate the WQE
1050 * sizes and the send_wqe_offset, so we're done now.
1051 */
1052 if (udata)
1053 return 0;
1054
1055 size = PAGE_ALIGN(qp->send_wqe_offset +
1056 (qp->sq.max << qp->sq.wqe_shift));
1057
1058 qp->wrid = kmalloc_array(qp->rq.max + qp->sq.max, sizeof(u64),
1059 GFP_KERNEL);
1060 if (!qp->wrid)
1061 goto err_out;
1062
1063 err = mthca_buf_alloc(dev, size, MTHCA_MAX_DIRECT_QP_SIZE,
1064 &qp->queue, &qp->is_direct, pd, 0, &qp->mr);
1065 if (err)
1066 goto err_out;
1067
1068 return 0;
1069
1070 err_out:
1071 kfree(qp->wrid);
1072 return err;
1073 }
1074
mthca_free_wqe_buf(struct mthca_dev * dev,struct mthca_qp * qp)1075 static void mthca_free_wqe_buf(struct mthca_dev *dev,
1076 struct mthca_qp *qp)
1077 {
1078 mthca_buf_free(dev, PAGE_ALIGN(qp->send_wqe_offset +
1079 (qp->sq.max << qp->sq.wqe_shift)),
1080 &qp->queue, qp->is_direct, &qp->mr);
1081 kfree(qp->wrid);
1082 }
1083
mthca_map_memfree(struct mthca_dev * dev,struct mthca_qp * qp)1084 static int mthca_map_memfree(struct mthca_dev *dev,
1085 struct mthca_qp *qp)
1086 {
1087 int ret;
1088
1089 if (mthca_is_memfree(dev)) {
1090 ret = mthca_table_get(dev, dev->qp_table.qp_table, qp->qpn);
1091 if (ret)
1092 return ret;
1093
1094 ret = mthca_table_get(dev, dev->qp_table.eqp_table, qp->qpn);
1095 if (ret)
1096 goto err_qpc;
1097
1098 ret = mthca_table_get(dev, dev->qp_table.rdb_table,
1099 qp->qpn << dev->qp_table.rdb_shift);
1100 if (ret)
1101 goto err_eqpc;
1102 }
1103
1104 return 0;
1105
1106 err_eqpc:
1107 mthca_table_put(dev, dev->qp_table.eqp_table, qp->qpn);
1108
1109 err_qpc:
1110 mthca_table_put(dev, dev->qp_table.qp_table, qp->qpn);
1111
1112 return ret;
1113 }
1114
mthca_unmap_memfree(struct mthca_dev * dev,struct mthca_qp * qp)1115 static void mthca_unmap_memfree(struct mthca_dev *dev,
1116 struct mthca_qp *qp)
1117 {
1118 mthca_table_put(dev, dev->qp_table.rdb_table,
1119 qp->qpn << dev->qp_table.rdb_shift);
1120 mthca_table_put(dev, dev->qp_table.eqp_table, qp->qpn);
1121 mthca_table_put(dev, dev->qp_table.qp_table, qp->qpn);
1122 }
1123
mthca_alloc_memfree(struct mthca_dev * dev,struct mthca_qp * qp)1124 static int mthca_alloc_memfree(struct mthca_dev *dev,
1125 struct mthca_qp *qp)
1126 {
1127 if (mthca_is_memfree(dev)) {
1128 qp->rq.db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_RQ,
1129 qp->qpn, &qp->rq.db);
1130 if (qp->rq.db_index < 0)
1131 return -ENOMEM;
1132
1133 qp->sq.db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_SQ,
1134 qp->qpn, &qp->sq.db);
1135 if (qp->sq.db_index < 0) {
1136 mthca_free_db(dev, MTHCA_DB_TYPE_RQ, qp->rq.db_index);
1137 return -ENOMEM;
1138 }
1139 }
1140
1141 return 0;
1142 }
1143
mthca_free_memfree(struct mthca_dev * dev,struct mthca_qp * qp)1144 static void mthca_free_memfree(struct mthca_dev *dev,
1145 struct mthca_qp *qp)
1146 {
1147 if (mthca_is_memfree(dev)) {
1148 mthca_free_db(dev, MTHCA_DB_TYPE_SQ, qp->sq.db_index);
1149 mthca_free_db(dev, MTHCA_DB_TYPE_RQ, qp->rq.db_index);
1150 }
1151 }
1152
mthca_alloc_qp_common(struct mthca_dev * dev,struct mthca_pd * pd,struct mthca_cq * send_cq,struct mthca_cq * recv_cq,enum ib_sig_type send_policy,struct mthca_qp * qp,struct ib_udata * udata)1153 static int mthca_alloc_qp_common(struct mthca_dev *dev,
1154 struct mthca_pd *pd,
1155 struct mthca_cq *send_cq,
1156 struct mthca_cq *recv_cq,
1157 enum ib_sig_type send_policy,
1158 struct mthca_qp *qp,
1159 struct ib_udata *udata)
1160 {
1161 int ret;
1162 int i;
1163 struct mthca_next_seg *next;
1164
1165 qp->refcount = 1;
1166 init_waitqueue_head(&qp->wait);
1167 mutex_init(&qp->mutex);
1168 qp->state = IB_QPS_RESET;
1169 qp->atomic_rd_en = 0;
1170 qp->resp_depth = 0;
1171 qp->sq_policy = send_policy;
1172 mthca_wq_reset(&qp->sq);
1173 mthca_wq_reset(&qp->rq);
1174
1175 spin_lock_init(&qp->sq.lock);
1176 spin_lock_init(&qp->rq.lock);
1177
1178 ret = mthca_map_memfree(dev, qp);
1179 if (ret)
1180 return ret;
1181
1182 ret = mthca_alloc_wqe_buf(dev, pd, qp, udata);
1183 if (ret) {
1184 mthca_unmap_memfree(dev, qp);
1185 return ret;
1186 }
1187
1188 mthca_adjust_qp_caps(dev, pd, qp);
1189
1190 /*
1191 * If this is a userspace QP, we're done now. The doorbells
1192 * will be allocated and buffers will be initialized in
1193 * userspace.
1194 */
1195 if (udata)
1196 return 0;
1197
1198 ret = mthca_alloc_memfree(dev, qp);
1199 if (ret) {
1200 mthca_free_wqe_buf(dev, qp);
1201 mthca_unmap_memfree(dev, qp);
1202 return ret;
1203 }
1204
1205 if (mthca_is_memfree(dev)) {
1206 struct mthca_data_seg *scatter;
1207 int size = (sizeof (struct mthca_next_seg) +
1208 qp->rq.max_gs * sizeof (struct mthca_data_seg)) / 16;
1209
1210 for (i = 0; i < qp->rq.max; ++i) {
1211 next = get_recv_wqe(qp, i);
1212 next->nda_op = cpu_to_be32(((i + 1) & (qp->rq.max - 1)) <<
1213 qp->rq.wqe_shift);
1214 next->ee_nds = cpu_to_be32(size);
1215
1216 for (scatter = (void *) (next + 1);
1217 (void *) scatter < (void *) next + (1 << qp->rq.wqe_shift);
1218 ++scatter)
1219 scatter->lkey = cpu_to_be32(MTHCA_INVAL_LKEY);
1220 }
1221
1222 for (i = 0; i < qp->sq.max; ++i) {
1223 next = get_send_wqe(qp, i);
1224 next->nda_op = cpu_to_be32((((i + 1) & (qp->sq.max - 1)) <<
1225 qp->sq.wqe_shift) +
1226 qp->send_wqe_offset);
1227 }
1228 } else {
1229 for (i = 0; i < qp->rq.max; ++i) {
1230 next = get_recv_wqe(qp, i);
1231 next->nda_op = htonl((((i + 1) % qp->rq.max) <<
1232 qp->rq.wqe_shift) | 1);
1233 }
1234 }
1235
1236 qp->sq.last = get_send_wqe(qp, qp->sq.max - 1);
1237 qp->rq.last = get_recv_wqe(qp, qp->rq.max - 1);
1238
1239 return 0;
1240 }
1241
mthca_set_qp_size(struct mthca_dev * dev,struct ib_qp_cap * cap,struct mthca_pd * pd,struct mthca_qp * qp)1242 static int mthca_set_qp_size(struct mthca_dev *dev, struct ib_qp_cap *cap,
1243 struct mthca_pd *pd, struct mthca_qp *qp)
1244 {
1245 int max_data_size = mthca_max_data_size(dev, qp, dev->limits.max_desc_sz);
1246
1247 /* Sanity check QP size before proceeding */
1248 if (cap->max_send_wr > dev->limits.max_wqes ||
1249 cap->max_recv_wr > dev->limits.max_wqes ||
1250 cap->max_send_sge > dev->limits.max_sg ||
1251 cap->max_recv_sge > dev->limits.max_sg ||
1252 cap->max_inline_data > mthca_max_inline_data(pd, max_data_size))
1253 return -EINVAL;
1254
1255 /*
1256 * For MLX transport we need 2 extra send gather entries:
1257 * one for the header and one for the checksum at the end
1258 */
1259 if (qp->transport == MLX && cap->max_send_sge + 2 > dev->limits.max_sg)
1260 return -EINVAL;
1261
1262 if (mthca_is_memfree(dev)) {
1263 qp->rq.max = cap->max_recv_wr ?
1264 roundup_pow_of_two(cap->max_recv_wr) : 0;
1265 qp->sq.max = cap->max_send_wr ?
1266 roundup_pow_of_two(cap->max_send_wr) : 0;
1267 } else {
1268 qp->rq.max = cap->max_recv_wr;
1269 qp->sq.max = cap->max_send_wr;
1270 }
1271
1272 qp->rq.max_gs = cap->max_recv_sge;
1273 qp->sq.max_gs = max_t(int, cap->max_send_sge,
1274 ALIGN(cap->max_inline_data + MTHCA_INLINE_HEADER_SIZE,
1275 MTHCA_INLINE_CHUNK_SIZE) /
1276 sizeof (struct mthca_data_seg));
1277
1278 return 0;
1279 }
1280
mthca_alloc_qp(struct mthca_dev * dev,struct mthca_pd * pd,struct mthca_cq * send_cq,struct mthca_cq * recv_cq,enum ib_qp_type type,enum ib_sig_type send_policy,struct ib_qp_cap * cap,struct mthca_qp * qp,struct ib_udata * udata)1281 int mthca_alloc_qp(struct mthca_dev *dev,
1282 struct mthca_pd *pd,
1283 struct mthca_cq *send_cq,
1284 struct mthca_cq *recv_cq,
1285 enum ib_qp_type type,
1286 enum ib_sig_type send_policy,
1287 struct ib_qp_cap *cap,
1288 struct mthca_qp *qp,
1289 struct ib_udata *udata)
1290 {
1291 int err;
1292
1293 switch (type) {
1294 case IB_QPT_RC: qp->transport = RC; break;
1295 case IB_QPT_UC: qp->transport = UC; break;
1296 case IB_QPT_UD: qp->transport = UD; break;
1297 default: return -EINVAL;
1298 }
1299
1300 err = mthca_set_qp_size(dev, cap, pd, qp);
1301 if (err)
1302 return err;
1303
1304 qp->qpn = mthca_alloc(&dev->qp_table.alloc);
1305 if (qp->qpn == -1)
1306 return -ENOMEM;
1307
1308 /* initialize port to zero for error-catching. */
1309 qp->port = 0;
1310
1311 err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq,
1312 send_policy, qp, udata);
1313 if (err) {
1314 mthca_free(&dev->qp_table.alloc, qp->qpn);
1315 return err;
1316 }
1317
1318 spin_lock_irq(&dev->qp_table.lock);
1319 mthca_array_set(&dev->qp_table.qp,
1320 qp->qpn & (dev->limits.num_qps - 1), qp);
1321 spin_unlock_irq(&dev->qp_table.lock);
1322
1323 return 0;
1324 }
1325
mthca_lock_cqs(struct mthca_cq * send_cq,struct mthca_cq * recv_cq)1326 static void mthca_lock_cqs(struct mthca_cq *send_cq, struct mthca_cq *recv_cq)
1327 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
1328 {
1329 if (send_cq == recv_cq) {
1330 spin_lock_irq(&send_cq->lock);
1331 __acquire(&recv_cq->lock);
1332 } else if (send_cq->cqn < recv_cq->cqn) {
1333 spin_lock_irq(&send_cq->lock);
1334 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
1335 } else {
1336 spin_lock_irq(&recv_cq->lock);
1337 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
1338 }
1339 }
1340
mthca_unlock_cqs(struct mthca_cq * send_cq,struct mthca_cq * recv_cq)1341 static void mthca_unlock_cqs(struct mthca_cq *send_cq, struct mthca_cq *recv_cq)
1342 __releases(&send_cq->lock) __releases(&recv_cq->lock)
1343 {
1344 if (send_cq == recv_cq) {
1345 __release(&recv_cq->lock);
1346 spin_unlock_irq(&send_cq->lock);
1347 } else if (send_cq->cqn < recv_cq->cqn) {
1348 spin_unlock(&recv_cq->lock);
1349 spin_unlock_irq(&send_cq->lock);
1350 } else {
1351 spin_unlock(&send_cq->lock);
1352 spin_unlock_irq(&recv_cq->lock);
1353 }
1354 }
1355
mthca_alloc_sqp(struct mthca_dev * dev,struct mthca_pd * pd,struct mthca_cq * send_cq,struct mthca_cq * recv_cq,enum ib_sig_type send_policy,struct ib_qp_cap * cap,int qpn,int port,struct mthca_sqp * sqp,struct ib_udata * udata)1356 int mthca_alloc_sqp(struct mthca_dev *dev,
1357 struct mthca_pd *pd,
1358 struct mthca_cq *send_cq,
1359 struct mthca_cq *recv_cq,
1360 enum ib_sig_type send_policy,
1361 struct ib_qp_cap *cap,
1362 int qpn,
1363 int port,
1364 struct mthca_sqp *sqp,
1365 struct ib_udata *udata)
1366 {
1367 u32 mqpn = qpn * 2 + dev->qp_table.sqp_start + port - 1;
1368 int err;
1369
1370 sqp->qp.transport = MLX;
1371 err = mthca_set_qp_size(dev, cap, pd, &sqp->qp);
1372 if (err)
1373 return err;
1374
1375 sqp->header_buf_size = sqp->qp.sq.max * MTHCA_UD_HEADER_SIZE;
1376 sqp->header_buf = dma_alloc_coherent(&dev->pdev->dev, sqp->header_buf_size,
1377 &sqp->header_dma, GFP_KERNEL);
1378 if (!sqp->header_buf)
1379 return -ENOMEM;
1380
1381 spin_lock_irq(&dev->qp_table.lock);
1382 if (mthca_array_get(&dev->qp_table.qp, mqpn))
1383 err = -EBUSY;
1384 else
1385 mthca_array_set(&dev->qp_table.qp, mqpn, sqp);
1386 spin_unlock_irq(&dev->qp_table.lock);
1387
1388 if (err)
1389 goto err_out;
1390
1391 sqp->qp.port = port;
1392 sqp->qp.qpn = mqpn;
1393 sqp->qp.transport = MLX;
1394
1395 err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq,
1396 send_policy, &sqp->qp, udata);
1397 if (err)
1398 goto err_out_free;
1399
1400 atomic_inc(&pd->sqp_count);
1401
1402 return 0;
1403
1404 err_out_free:
1405 /*
1406 * Lock CQs here, so that CQ polling code can do QP lookup
1407 * without taking a lock.
1408 */
1409 mthca_lock_cqs(send_cq, recv_cq);
1410
1411 spin_lock(&dev->qp_table.lock);
1412 mthca_array_clear(&dev->qp_table.qp, mqpn);
1413 spin_unlock(&dev->qp_table.lock);
1414
1415 mthca_unlock_cqs(send_cq, recv_cq);
1416
1417 err_out:
1418 dma_free_coherent(&dev->pdev->dev, sqp->header_buf_size,
1419 sqp->header_buf, sqp->header_dma);
1420
1421 return err;
1422 }
1423
get_qp_refcount(struct mthca_dev * dev,struct mthca_qp * qp)1424 static inline int get_qp_refcount(struct mthca_dev *dev, struct mthca_qp *qp)
1425 {
1426 int c;
1427
1428 spin_lock_irq(&dev->qp_table.lock);
1429 c = qp->refcount;
1430 spin_unlock_irq(&dev->qp_table.lock);
1431
1432 return c;
1433 }
1434
mthca_free_qp(struct mthca_dev * dev,struct mthca_qp * qp)1435 void mthca_free_qp(struct mthca_dev *dev,
1436 struct mthca_qp *qp)
1437 {
1438 struct mthca_cq *send_cq;
1439 struct mthca_cq *recv_cq;
1440
1441 send_cq = to_mcq(qp->ibqp.send_cq);
1442 recv_cq = to_mcq(qp->ibqp.recv_cq);
1443
1444 /*
1445 * Lock CQs here, so that CQ polling code can do QP lookup
1446 * without taking a lock.
1447 */
1448 mthca_lock_cqs(send_cq, recv_cq);
1449
1450 spin_lock(&dev->qp_table.lock);
1451 mthca_array_clear(&dev->qp_table.qp,
1452 qp->qpn & (dev->limits.num_qps - 1));
1453 --qp->refcount;
1454 spin_unlock(&dev->qp_table.lock);
1455
1456 mthca_unlock_cqs(send_cq, recv_cq);
1457
1458 wait_event(qp->wait, !get_qp_refcount(dev, qp));
1459
1460 if (qp->state != IB_QPS_RESET)
1461 mthca_MODIFY_QP(dev, qp->state, IB_QPS_RESET, qp->qpn, 0,
1462 NULL, 0);
1463
1464 /*
1465 * If this is a userspace QP, the buffers, MR, CQs and so on
1466 * will be cleaned up in userspace, so all we have to do is
1467 * unref the mem-free tables and free the QPN in our table.
1468 */
1469 if (!qp->ibqp.uobject) {
1470 mthca_cq_clean(dev, recv_cq, qp->qpn,
1471 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1472 if (send_cq != recv_cq)
1473 mthca_cq_clean(dev, send_cq, qp->qpn, NULL);
1474
1475 mthca_free_memfree(dev, qp);
1476 mthca_free_wqe_buf(dev, qp);
1477 }
1478
1479 mthca_unmap_memfree(dev, qp);
1480
1481 if (is_sqp(dev, qp)) {
1482 atomic_dec(&(to_mpd(qp->ibqp.pd)->sqp_count));
1483 dma_free_coherent(&dev->pdev->dev,
1484 to_msqp(qp)->header_buf_size,
1485 to_msqp(qp)->header_buf,
1486 to_msqp(qp)->header_dma);
1487 } else
1488 mthca_free(&dev->qp_table.alloc, qp->qpn);
1489 }
1490
1491 /* Create UD header for an MLX send and build a data segment for it */
build_mlx_header(struct mthca_dev * dev,struct mthca_sqp * sqp,int ind,const struct ib_ud_wr * wr,struct mthca_mlx_seg * mlx,struct mthca_data_seg * data)1492 static int build_mlx_header(struct mthca_dev *dev, struct mthca_sqp *sqp,
1493 int ind, const struct ib_ud_wr *wr,
1494 struct mthca_mlx_seg *mlx,
1495 struct mthca_data_seg *data)
1496 {
1497 int header_size;
1498 int err;
1499 u16 pkey;
1500
1501 ib_ud_header_init(256, /* assume a MAD */ 1, 0, 0,
1502 mthca_ah_grh_present(to_mah(wr->ah)), 0, 0, 0,
1503 &sqp->ud_header);
1504
1505 err = mthca_read_ah(dev, to_mah(wr->ah), &sqp->ud_header);
1506 if (err)
1507 return err;
1508 mlx->flags &= ~cpu_to_be32(MTHCA_NEXT_SOLICIT | 1);
1509 mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MTHCA_MLX_VL15 : 0) |
1510 (sqp->ud_header.lrh.destination_lid ==
1511 IB_LID_PERMISSIVE ? MTHCA_MLX_SLR : 0) |
1512 (sqp->ud_header.lrh.service_level << 8));
1513 mlx->rlid = sqp->ud_header.lrh.destination_lid;
1514 mlx->vcrc = 0;
1515
1516 switch (wr->wr.opcode) {
1517 case IB_WR_SEND:
1518 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
1519 sqp->ud_header.immediate_present = 0;
1520 break;
1521 case IB_WR_SEND_WITH_IMM:
1522 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
1523 sqp->ud_header.immediate_present = 1;
1524 sqp->ud_header.immediate_data = wr->wr.ex.imm_data;
1525 break;
1526 default:
1527 return -EINVAL;
1528 }
1529
1530 sqp->ud_header.lrh.virtual_lane = !sqp->qp.ibqp.qp_num ? 15 : 0;
1531 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
1532 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
1533 sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED);
1534 if (!sqp->qp.ibqp.qp_num)
1535 ib_get_cached_pkey(&dev->ib_dev, sqp->qp.port,
1536 sqp->pkey_index, &pkey);
1537 else
1538 ib_get_cached_pkey(&dev->ib_dev, sqp->qp.port,
1539 wr->pkey_index, &pkey);
1540 sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
1541 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn);
1542 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
1543 sqp->ud_header.deth.qkey = cpu_to_be32(wr->remote_qkey & 0x80000000 ?
1544 sqp->qkey : wr->remote_qkey);
1545 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
1546
1547 header_size = ib_ud_header_pack(&sqp->ud_header,
1548 sqp->header_buf +
1549 ind * MTHCA_UD_HEADER_SIZE);
1550
1551 data->byte_count = cpu_to_be32(header_size);
1552 data->lkey = cpu_to_be32(to_mpd(sqp->qp.ibqp.pd)->ntmr.ibmr.lkey);
1553 data->addr = cpu_to_be64(sqp->header_dma +
1554 ind * MTHCA_UD_HEADER_SIZE);
1555
1556 return 0;
1557 }
1558
mthca_wq_overflow(struct mthca_wq * wq,int nreq,struct ib_cq * ib_cq)1559 static inline int mthca_wq_overflow(struct mthca_wq *wq, int nreq,
1560 struct ib_cq *ib_cq)
1561 {
1562 unsigned cur;
1563 struct mthca_cq *cq;
1564
1565 cur = wq->head - wq->tail;
1566 if (likely(cur + nreq < wq->max))
1567 return 0;
1568
1569 cq = to_mcq(ib_cq);
1570 spin_lock(&cq->lock);
1571 cur = wq->head - wq->tail;
1572 spin_unlock(&cq->lock);
1573
1574 return cur + nreq >= wq->max;
1575 }
1576
set_raddr_seg(struct mthca_raddr_seg * rseg,u64 remote_addr,u32 rkey)1577 static __always_inline void set_raddr_seg(struct mthca_raddr_seg *rseg,
1578 u64 remote_addr, u32 rkey)
1579 {
1580 rseg->raddr = cpu_to_be64(remote_addr);
1581 rseg->rkey = cpu_to_be32(rkey);
1582 rseg->reserved = 0;
1583 }
1584
set_atomic_seg(struct mthca_atomic_seg * aseg,const struct ib_atomic_wr * wr)1585 static __always_inline void set_atomic_seg(struct mthca_atomic_seg *aseg,
1586 const struct ib_atomic_wr *wr)
1587 {
1588 if (wr->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1589 aseg->swap_add = cpu_to_be64(wr->swap);
1590 aseg->compare = cpu_to_be64(wr->compare_add);
1591 } else {
1592 aseg->swap_add = cpu_to_be64(wr->compare_add);
1593 aseg->compare = 0;
1594 }
1595
1596 }
1597
set_tavor_ud_seg(struct mthca_tavor_ud_seg * useg,const struct ib_ud_wr * wr)1598 static void set_tavor_ud_seg(struct mthca_tavor_ud_seg *useg,
1599 const struct ib_ud_wr *wr)
1600 {
1601 useg->lkey = cpu_to_be32(to_mah(wr->ah)->key);
1602 useg->av_addr = cpu_to_be64(to_mah(wr->ah)->avdma);
1603 useg->dqpn = cpu_to_be32(wr->remote_qpn);
1604 useg->qkey = cpu_to_be32(wr->remote_qkey);
1605
1606 }
1607
set_arbel_ud_seg(struct mthca_arbel_ud_seg * useg,const struct ib_ud_wr * wr)1608 static void set_arbel_ud_seg(struct mthca_arbel_ud_seg *useg,
1609 const struct ib_ud_wr *wr)
1610 {
1611 memcpy(useg->av, to_mah(wr->ah)->av, MTHCA_AV_SIZE);
1612 useg->dqpn = cpu_to_be32(wr->remote_qpn);
1613 useg->qkey = cpu_to_be32(wr->remote_qkey);
1614 }
1615
mthca_tavor_post_send(struct ib_qp * ibqp,const struct ib_send_wr * wr,const struct ib_send_wr ** bad_wr)1616 int mthca_tavor_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
1617 const struct ib_send_wr **bad_wr)
1618 {
1619 struct mthca_dev *dev = to_mdev(ibqp->device);
1620 struct mthca_qp *qp = to_mqp(ibqp);
1621 void *wqe;
1622 void *prev_wqe;
1623 unsigned long flags;
1624 int err = 0;
1625 int nreq;
1626 int i;
1627 int size;
1628 /*
1629 * f0 and size0 are only used if nreq != 0, and they will
1630 * always be initialized the first time through the main loop
1631 * before nreq is incremented. So nreq cannot become non-zero
1632 * without initializing f0 and size0, and they are in fact
1633 * never used uninitialized.
1634 */
1635 int uninitialized_var(size0);
1636 u32 uninitialized_var(f0);
1637 int ind;
1638 u8 op0 = 0;
1639
1640 spin_lock_irqsave(&qp->sq.lock, flags);
1641
1642 /* XXX check that state is OK to post send */
1643
1644 ind = qp->sq.next_ind;
1645
1646 for (nreq = 0; wr; ++nreq, wr = wr->next) {
1647 if (mthca_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1648 mthca_err(dev, "SQ %06x full (%u head, %u tail,"
1649 " %d max, %d nreq)\n", qp->qpn,
1650 qp->sq.head, qp->sq.tail,
1651 qp->sq.max, nreq);
1652 err = -ENOMEM;
1653 *bad_wr = wr;
1654 goto out;
1655 }
1656
1657 wqe = get_send_wqe(qp, ind);
1658 prev_wqe = qp->sq.last;
1659 qp->sq.last = wqe;
1660
1661 ((struct mthca_next_seg *) wqe)->nda_op = 0;
1662 ((struct mthca_next_seg *) wqe)->ee_nds = 0;
1663 ((struct mthca_next_seg *) wqe)->flags =
1664 ((wr->send_flags & IB_SEND_SIGNALED) ?
1665 cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0) |
1666 ((wr->send_flags & IB_SEND_SOLICITED) ?
1667 cpu_to_be32(MTHCA_NEXT_SOLICIT) : 0) |
1668 cpu_to_be32(1);
1669 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
1670 wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
1671 ((struct mthca_next_seg *) wqe)->imm = wr->ex.imm_data;
1672
1673 wqe += sizeof (struct mthca_next_seg);
1674 size = sizeof (struct mthca_next_seg) / 16;
1675
1676 switch (qp->transport) {
1677 case RC:
1678 switch (wr->opcode) {
1679 case IB_WR_ATOMIC_CMP_AND_SWP:
1680 case IB_WR_ATOMIC_FETCH_AND_ADD:
1681 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
1682 atomic_wr(wr)->rkey);
1683 wqe += sizeof (struct mthca_raddr_seg);
1684
1685 set_atomic_seg(wqe, atomic_wr(wr));
1686 wqe += sizeof (struct mthca_atomic_seg);
1687 size += (sizeof (struct mthca_raddr_seg) +
1688 sizeof (struct mthca_atomic_seg)) / 16;
1689 break;
1690
1691 case IB_WR_RDMA_WRITE:
1692 case IB_WR_RDMA_WRITE_WITH_IMM:
1693 case IB_WR_RDMA_READ:
1694 set_raddr_seg(wqe, rdma_wr(wr)->remote_addr,
1695 rdma_wr(wr)->rkey);
1696 wqe += sizeof (struct mthca_raddr_seg);
1697 size += sizeof (struct mthca_raddr_seg) / 16;
1698 break;
1699
1700 default:
1701 /* No extra segments required for sends */
1702 break;
1703 }
1704
1705 break;
1706
1707 case UC:
1708 switch (wr->opcode) {
1709 case IB_WR_RDMA_WRITE:
1710 case IB_WR_RDMA_WRITE_WITH_IMM:
1711 set_raddr_seg(wqe, rdma_wr(wr)->remote_addr,
1712 rdma_wr(wr)->rkey);
1713 wqe += sizeof (struct mthca_raddr_seg);
1714 size += sizeof (struct mthca_raddr_seg) / 16;
1715 break;
1716
1717 default:
1718 /* No extra segments required for sends */
1719 break;
1720 }
1721
1722 break;
1723
1724 case UD:
1725 set_tavor_ud_seg(wqe, ud_wr(wr));
1726 wqe += sizeof (struct mthca_tavor_ud_seg);
1727 size += sizeof (struct mthca_tavor_ud_seg) / 16;
1728 break;
1729
1730 case MLX:
1731 err = build_mlx_header(dev, to_msqp(qp), ind, ud_wr(wr),
1732 wqe - sizeof (struct mthca_next_seg),
1733 wqe);
1734 if (err) {
1735 *bad_wr = wr;
1736 goto out;
1737 }
1738 wqe += sizeof (struct mthca_data_seg);
1739 size += sizeof (struct mthca_data_seg) / 16;
1740 break;
1741 }
1742
1743 if (wr->num_sge > qp->sq.max_gs) {
1744 mthca_err(dev, "too many gathers\n");
1745 err = -EINVAL;
1746 *bad_wr = wr;
1747 goto out;
1748 }
1749
1750 for (i = 0; i < wr->num_sge; ++i) {
1751 mthca_set_data_seg(wqe, wr->sg_list + i);
1752 wqe += sizeof (struct mthca_data_seg);
1753 size += sizeof (struct mthca_data_seg) / 16;
1754 }
1755
1756 /* Add one more inline data segment for ICRC */
1757 if (qp->transport == MLX) {
1758 ((struct mthca_data_seg *) wqe)->byte_count =
1759 cpu_to_be32((1 << 31) | 4);
1760 ((u32 *) wqe)[1] = 0;
1761 wqe += sizeof (struct mthca_data_seg);
1762 size += sizeof (struct mthca_data_seg) / 16;
1763 }
1764
1765 qp->wrid[ind + qp->rq.max] = wr->wr_id;
1766
1767 if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) {
1768 mthca_err(dev, "opcode invalid\n");
1769 err = -EINVAL;
1770 *bad_wr = wr;
1771 goto out;
1772 }
1773
1774 ((struct mthca_next_seg *) prev_wqe)->nda_op =
1775 cpu_to_be32(((ind << qp->sq.wqe_shift) +
1776 qp->send_wqe_offset) |
1777 mthca_opcode[wr->opcode]);
1778 wmb();
1779 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1780 cpu_to_be32((nreq ? 0 : MTHCA_NEXT_DBD) | size |
1781 ((wr->send_flags & IB_SEND_FENCE) ?
1782 MTHCA_NEXT_FENCE : 0));
1783
1784 if (!nreq) {
1785 size0 = size;
1786 op0 = mthca_opcode[wr->opcode];
1787 f0 = wr->send_flags & IB_SEND_FENCE ?
1788 MTHCA_SEND_DOORBELL_FENCE : 0;
1789 }
1790
1791 ++ind;
1792 if (unlikely(ind >= qp->sq.max))
1793 ind -= qp->sq.max;
1794 }
1795
1796 out:
1797 if (likely(nreq)) {
1798 wmb();
1799
1800 mthca_write64(((qp->sq.next_ind << qp->sq.wqe_shift) +
1801 qp->send_wqe_offset) | f0 | op0,
1802 (qp->qpn << 8) | size0,
1803 dev->kar + MTHCA_SEND_DOORBELL,
1804 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1805 /*
1806 * Make sure doorbells don't leak out of SQ spinlock
1807 * and reach the HCA out of order:
1808 */
1809 mmiowb();
1810 }
1811
1812 qp->sq.next_ind = ind;
1813 qp->sq.head += nreq;
1814
1815 spin_unlock_irqrestore(&qp->sq.lock, flags);
1816 return err;
1817 }
1818
mthca_tavor_post_receive(struct ib_qp * ibqp,const struct ib_recv_wr * wr,const struct ib_recv_wr ** bad_wr)1819 int mthca_tavor_post_receive(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
1820 const struct ib_recv_wr **bad_wr)
1821 {
1822 struct mthca_dev *dev = to_mdev(ibqp->device);
1823 struct mthca_qp *qp = to_mqp(ibqp);
1824 unsigned long flags;
1825 int err = 0;
1826 int nreq;
1827 int i;
1828 int size;
1829 /*
1830 * size0 is only used if nreq != 0, and it will always be
1831 * initialized the first time through the main loop before
1832 * nreq is incremented. So nreq cannot become non-zero
1833 * without initializing size0, and it is in fact never used
1834 * uninitialized.
1835 */
1836 int uninitialized_var(size0);
1837 int ind;
1838 void *wqe;
1839 void *prev_wqe;
1840
1841 spin_lock_irqsave(&qp->rq.lock, flags);
1842
1843 /* XXX check that state is OK to post receive */
1844
1845 ind = qp->rq.next_ind;
1846
1847 for (nreq = 0; wr; wr = wr->next) {
1848 if (mthca_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
1849 mthca_err(dev, "RQ %06x full (%u head, %u tail,"
1850 " %d max, %d nreq)\n", qp->qpn,
1851 qp->rq.head, qp->rq.tail,
1852 qp->rq.max, nreq);
1853 err = -ENOMEM;
1854 *bad_wr = wr;
1855 goto out;
1856 }
1857
1858 wqe = get_recv_wqe(qp, ind);
1859 prev_wqe = qp->rq.last;
1860 qp->rq.last = wqe;
1861
1862 ((struct mthca_next_seg *) wqe)->ee_nds =
1863 cpu_to_be32(MTHCA_NEXT_DBD);
1864 ((struct mthca_next_seg *) wqe)->flags = 0;
1865
1866 wqe += sizeof (struct mthca_next_seg);
1867 size = sizeof (struct mthca_next_seg) / 16;
1868
1869 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
1870 err = -EINVAL;
1871 *bad_wr = wr;
1872 goto out;
1873 }
1874
1875 for (i = 0; i < wr->num_sge; ++i) {
1876 mthca_set_data_seg(wqe, wr->sg_list + i);
1877 wqe += sizeof (struct mthca_data_seg);
1878 size += sizeof (struct mthca_data_seg) / 16;
1879 }
1880
1881 qp->wrid[ind] = wr->wr_id;
1882
1883 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1884 cpu_to_be32(MTHCA_NEXT_DBD | size);
1885
1886 if (!nreq)
1887 size0 = size;
1888
1889 ++ind;
1890 if (unlikely(ind >= qp->rq.max))
1891 ind -= qp->rq.max;
1892
1893 ++nreq;
1894 if (unlikely(nreq == MTHCA_TAVOR_MAX_WQES_PER_RECV_DB)) {
1895 nreq = 0;
1896
1897 wmb();
1898
1899 mthca_write64((qp->rq.next_ind << qp->rq.wqe_shift) | size0,
1900 qp->qpn << 8, dev->kar + MTHCA_RECEIVE_DOORBELL,
1901 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1902
1903 qp->rq.next_ind = ind;
1904 qp->rq.head += MTHCA_TAVOR_MAX_WQES_PER_RECV_DB;
1905 }
1906 }
1907
1908 out:
1909 if (likely(nreq)) {
1910 wmb();
1911
1912 mthca_write64((qp->rq.next_ind << qp->rq.wqe_shift) | size0,
1913 qp->qpn << 8 | nreq, dev->kar + MTHCA_RECEIVE_DOORBELL,
1914 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1915 }
1916
1917 qp->rq.next_ind = ind;
1918 qp->rq.head += nreq;
1919
1920 /*
1921 * Make sure doorbells don't leak out of RQ spinlock and reach
1922 * the HCA out of order:
1923 */
1924 mmiowb();
1925
1926 spin_unlock_irqrestore(&qp->rq.lock, flags);
1927 return err;
1928 }
1929
mthca_arbel_post_send(struct ib_qp * ibqp,const struct ib_send_wr * wr,const struct ib_send_wr ** bad_wr)1930 int mthca_arbel_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
1931 const struct ib_send_wr **bad_wr)
1932 {
1933 struct mthca_dev *dev = to_mdev(ibqp->device);
1934 struct mthca_qp *qp = to_mqp(ibqp);
1935 u32 dbhi;
1936 void *wqe;
1937 void *prev_wqe;
1938 unsigned long flags;
1939 int err = 0;
1940 int nreq;
1941 int i;
1942 int size;
1943 /*
1944 * f0 and size0 are only used if nreq != 0, and they will
1945 * always be initialized the first time through the main loop
1946 * before nreq is incremented. So nreq cannot become non-zero
1947 * without initializing f0 and size0, and they are in fact
1948 * never used uninitialized.
1949 */
1950 int uninitialized_var(size0);
1951 u32 uninitialized_var(f0);
1952 int ind;
1953 u8 op0 = 0;
1954
1955 spin_lock_irqsave(&qp->sq.lock, flags);
1956
1957 /* XXX check that state is OK to post send */
1958
1959 ind = qp->sq.head & (qp->sq.max - 1);
1960
1961 for (nreq = 0; wr; ++nreq, wr = wr->next) {
1962 if (unlikely(nreq == MTHCA_ARBEL_MAX_WQES_PER_SEND_DB)) {
1963 nreq = 0;
1964
1965 dbhi = (MTHCA_ARBEL_MAX_WQES_PER_SEND_DB << 24) |
1966 ((qp->sq.head & 0xffff) << 8) | f0 | op0;
1967
1968 qp->sq.head += MTHCA_ARBEL_MAX_WQES_PER_SEND_DB;
1969
1970 /*
1971 * Make sure that descriptors are written before
1972 * doorbell record.
1973 */
1974 wmb();
1975 *qp->sq.db = cpu_to_be32(qp->sq.head & 0xffff);
1976
1977 /*
1978 * Make sure doorbell record is written before we
1979 * write MMIO send doorbell.
1980 */
1981 wmb();
1982
1983 mthca_write64(dbhi, (qp->qpn << 8) | size0,
1984 dev->kar + MTHCA_SEND_DOORBELL,
1985 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1986 }
1987
1988 if (mthca_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1989 mthca_err(dev, "SQ %06x full (%u head, %u tail,"
1990 " %d max, %d nreq)\n", qp->qpn,
1991 qp->sq.head, qp->sq.tail,
1992 qp->sq.max, nreq);
1993 err = -ENOMEM;
1994 *bad_wr = wr;
1995 goto out;
1996 }
1997
1998 wqe = get_send_wqe(qp, ind);
1999 prev_wqe = qp->sq.last;
2000 qp->sq.last = wqe;
2001
2002 ((struct mthca_next_seg *) wqe)->flags =
2003 ((wr->send_flags & IB_SEND_SIGNALED) ?
2004 cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0) |
2005 ((wr->send_flags & IB_SEND_SOLICITED) ?
2006 cpu_to_be32(MTHCA_NEXT_SOLICIT) : 0) |
2007 ((wr->send_flags & IB_SEND_IP_CSUM) ?
2008 cpu_to_be32(MTHCA_NEXT_IP_CSUM | MTHCA_NEXT_TCP_UDP_CSUM) : 0) |
2009 cpu_to_be32(1);
2010 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
2011 wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
2012 ((struct mthca_next_seg *) wqe)->imm = wr->ex.imm_data;
2013
2014 wqe += sizeof (struct mthca_next_seg);
2015 size = sizeof (struct mthca_next_seg) / 16;
2016
2017 switch (qp->transport) {
2018 case RC:
2019 switch (wr->opcode) {
2020 case IB_WR_ATOMIC_CMP_AND_SWP:
2021 case IB_WR_ATOMIC_FETCH_AND_ADD:
2022 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
2023 atomic_wr(wr)->rkey);
2024 wqe += sizeof (struct mthca_raddr_seg);
2025
2026 set_atomic_seg(wqe, atomic_wr(wr));
2027 wqe += sizeof (struct mthca_atomic_seg);
2028 size += (sizeof (struct mthca_raddr_seg) +
2029 sizeof (struct mthca_atomic_seg)) / 16;
2030 break;
2031
2032 case IB_WR_RDMA_READ:
2033 case IB_WR_RDMA_WRITE:
2034 case IB_WR_RDMA_WRITE_WITH_IMM:
2035 set_raddr_seg(wqe, rdma_wr(wr)->remote_addr,
2036 rdma_wr(wr)->rkey);
2037 wqe += sizeof (struct mthca_raddr_seg);
2038 size += sizeof (struct mthca_raddr_seg) / 16;
2039 break;
2040
2041 default:
2042 /* No extra segments required for sends */
2043 break;
2044 }
2045
2046 break;
2047
2048 case UC:
2049 switch (wr->opcode) {
2050 case IB_WR_RDMA_WRITE:
2051 case IB_WR_RDMA_WRITE_WITH_IMM:
2052 set_raddr_seg(wqe, rdma_wr(wr)->remote_addr,
2053 rdma_wr(wr)->rkey);
2054 wqe += sizeof (struct mthca_raddr_seg);
2055 size += sizeof (struct mthca_raddr_seg) / 16;
2056 break;
2057
2058 default:
2059 /* No extra segments required for sends */
2060 break;
2061 }
2062
2063 break;
2064
2065 case UD:
2066 set_arbel_ud_seg(wqe, ud_wr(wr));
2067 wqe += sizeof (struct mthca_arbel_ud_seg);
2068 size += sizeof (struct mthca_arbel_ud_seg) / 16;
2069 break;
2070
2071 case MLX:
2072 err = build_mlx_header(dev, to_msqp(qp), ind, ud_wr(wr),
2073 wqe - sizeof (struct mthca_next_seg),
2074 wqe);
2075 if (err) {
2076 *bad_wr = wr;
2077 goto out;
2078 }
2079 wqe += sizeof (struct mthca_data_seg);
2080 size += sizeof (struct mthca_data_seg) / 16;
2081 break;
2082 }
2083
2084 if (wr->num_sge > qp->sq.max_gs) {
2085 mthca_err(dev, "too many gathers\n");
2086 err = -EINVAL;
2087 *bad_wr = wr;
2088 goto out;
2089 }
2090
2091 for (i = 0; i < wr->num_sge; ++i) {
2092 mthca_set_data_seg(wqe, wr->sg_list + i);
2093 wqe += sizeof (struct mthca_data_seg);
2094 size += sizeof (struct mthca_data_seg) / 16;
2095 }
2096
2097 /* Add one more inline data segment for ICRC */
2098 if (qp->transport == MLX) {
2099 ((struct mthca_data_seg *) wqe)->byte_count =
2100 cpu_to_be32((1 << 31) | 4);
2101 ((u32 *) wqe)[1] = 0;
2102 wqe += sizeof (struct mthca_data_seg);
2103 size += sizeof (struct mthca_data_seg) / 16;
2104 }
2105
2106 qp->wrid[ind + qp->rq.max] = wr->wr_id;
2107
2108 if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) {
2109 mthca_err(dev, "opcode invalid\n");
2110 err = -EINVAL;
2111 *bad_wr = wr;
2112 goto out;
2113 }
2114
2115 ((struct mthca_next_seg *) prev_wqe)->nda_op =
2116 cpu_to_be32(((ind << qp->sq.wqe_shift) +
2117 qp->send_wqe_offset) |
2118 mthca_opcode[wr->opcode]);
2119 wmb();
2120 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
2121 cpu_to_be32(MTHCA_NEXT_DBD | size |
2122 ((wr->send_flags & IB_SEND_FENCE) ?
2123 MTHCA_NEXT_FENCE : 0));
2124
2125 if (!nreq) {
2126 size0 = size;
2127 op0 = mthca_opcode[wr->opcode];
2128 f0 = wr->send_flags & IB_SEND_FENCE ?
2129 MTHCA_SEND_DOORBELL_FENCE : 0;
2130 }
2131
2132 ++ind;
2133 if (unlikely(ind >= qp->sq.max))
2134 ind -= qp->sq.max;
2135 }
2136
2137 out:
2138 if (likely(nreq)) {
2139 dbhi = (nreq << 24) | ((qp->sq.head & 0xffff) << 8) | f0 | op0;
2140
2141 qp->sq.head += nreq;
2142
2143 /*
2144 * Make sure that descriptors are written before
2145 * doorbell record.
2146 */
2147 wmb();
2148 *qp->sq.db = cpu_to_be32(qp->sq.head & 0xffff);
2149
2150 /*
2151 * Make sure doorbell record is written before we
2152 * write MMIO send doorbell.
2153 */
2154 wmb();
2155
2156 mthca_write64(dbhi, (qp->qpn << 8) | size0, dev->kar + MTHCA_SEND_DOORBELL,
2157 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
2158 }
2159
2160 /*
2161 * Make sure doorbells don't leak out of SQ spinlock and reach
2162 * the HCA out of order:
2163 */
2164 mmiowb();
2165
2166 spin_unlock_irqrestore(&qp->sq.lock, flags);
2167 return err;
2168 }
2169
mthca_arbel_post_receive(struct ib_qp * ibqp,const struct ib_recv_wr * wr,const struct ib_recv_wr ** bad_wr)2170 int mthca_arbel_post_receive(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
2171 const struct ib_recv_wr **bad_wr)
2172 {
2173 struct mthca_dev *dev = to_mdev(ibqp->device);
2174 struct mthca_qp *qp = to_mqp(ibqp);
2175 unsigned long flags;
2176 int err = 0;
2177 int nreq;
2178 int ind;
2179 int i;
2180 void *wqe;
2181
2182 spin_lock_irqsave(&qp->rq.lock, flags);
2183
2184 /* XXX check that state is OK to post receive */
2185
2186 ind = qp->rq.head & (qp->rq.max - 1);
2187
2188 for (nreq = 0; wr; ++nreq, wr = wr->next) {
2189 if (mthca_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
2190 mthca_err(dev, "RQ %06x full (%u head, %u tail,"
2191 " %d max, %d nreq)\n", qp->qpn,
2192 qp->rq.head, qp->rq.tail,
2193 qp->rq.max, nreq);
2194 err = -ENOMEM;
2195 *bad_wr = wr;
2196 goto out;
2197 }
2198
2199 wqe = get_recv_wqe(qp, ind);
2200
2201 ((struct mthca_next_seg *) wqe)->flags = 0;
2202
2203 wqe += sizeof (struct mthca_next_seg);
2204
2205 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
2206 err = -EINVAL;
2207 *bad_wr = wr;
2208 goto out;
2209 }
2210
2211 for (i = 0; i < wr->num_sge; ++i) {
2212 mthca_set_data_seg(wqe, wr->sg_list + i);
2213 wqe += sizeof (struct mthca_data_seg);
2214 }
2215
2216 if (i < qp->rq.max_gs)
2217 mthca_set_data_seg_inval(wqe);
2218
2219 qp->wrid[ind] = wr->wr_id;
2220
2221 ++ind;
2222 if (unlikely(ind >= qp->rq.max))
2223 ind -= qp->rq.max;
2224 }
2225 out:
2226 if (likely(nreq)) {
2227 qp->rq.head += nreq;
2228
2229 /*
2230 * Make sure that descriptors are written before
2231 * doorbell record.
2232 */
2233 wmb();
2234 *qp->rq.db = cpu_to_be32(qp->rq.head & 0xffff);
2235 }
2236
2237 spin_unlock_irqrestore(&qp->rq.lock, flags);
2238 return err;
2239 }
2240
mthca_free_err_wqe(struct mthca_dev * dev,struct mthca_qp * qp,int is_send,int index,int * dbd,__be32 * new_wqe)2241 void mthca_free_err_wqe(struct mthca_dev *dev, struct mthca_qp *qp, int is_send,
2242 int index, int *dbd, __be32 *new_wqe)
2243 {
2244 struct mthca_next_seg *next;
2245
2246 /*
2247 * For SRQs, all receive WQEs generate a CQE, so we're always
2248 * at the end of the doorbell chain.
2249 */
2250 if (qp->ibqp.srq && !is_send) {
2251 *new_wqe = 0;
2252 return;
2253 }
2254
2255 if (is_send)
2256 next = get_send_wqe(qp, index);
2257 else
2258 next = get_recv_wqe(qp, index);
2259
2260 *dbd = !!(next->ee_nds & cpu_to_be32(MTHCA_NEXT_DBD));
2261 if (next->ee_nds & cpu_to_be32(0x3f))
2262 *new_wqe = (next->nda_op & cpu_to_be32(~0x3f)) |
2263 (next->ee_nds & cpu_to_be32(0x3f));
2264 else
2265 *new_wqe = 0;
2266 }
2267
mthca_init_qp_table(struct mthca_dev * dev)2268 int mthca_init_qp_table(struct mthca_dev *dev)
2269 {
2270 int err;
2271 int i;
2272
2273 spin_lock_init(&dev->qp_table.lock);
2274
2275 /*
2276 * We reserve 2 extra QPs per port for the special QPs. The
2277 * special QP for port 1 has to be even, so round up.
2278 */
2279 dev->qp_table.sqp_start = (dev->limits.reserved_qps + 1) & ~1UL;
2280 err = mthca_alloc_init(&dev->qp_table.alloc,
2281 dev->limits.num_qps,
2282 (1 << 24) - 1,
2283 dev->qp_table.sqp_start +
2284 MTHCA_MAX_PORTS * 2);
2285 if (err)
2286 return err;
2287
2288 err = mthca_array_init(&dev->qp_table.qp,
2289 dev->limits.num_qps);
2290 if (err) {
2291 mthca_alloc_cleanup(&dev->qp_table.alloc);
2292 return err;
2293 }
2294
2295 for (i = 0; i < 2; ++i) {
2296 err = mthca_CONF_SPECIAL_QP(dev, i ? IB_QPT_GSI : IB_QPT_SMI,
2297 dev->qp_table.sqp_start + i * 2);
2298 if (err) {
2299 mthca_warn(dev, "CONF_SPECIAL_QP returned "
2300 "%d, aborting.\n", err);
2301 goto err_out;
2302 }
2303 }
2304 return 0;
2305
2306 err_out:
2307 for (i = 0; i < 2; ++i)
2308 mthca_CONF_SPECIAL_QP(dev, i, 0);
2309
2310 mthca_array_cleanup(&dev->qp_table.qp, dev->limits.num_qps);
2311 mthca_alloc_cleanup(&dev->qp_table.alloc);
2312
2313 return err;
2314 }
2315
mthca_cleanup_qp_table(struct mthca_dev * dev)2316 void mthca_cleanup_qp_table(struct mthca_dev *dev)
2317 {
2318 int i;
2319
2320 for (i = 0; i < 2; ++i)
2321 mthca_CONF_SPECIAL_QP(dev, i, 0);
2322
2323 mthca_array_cleanup(&dev->qp_table.qp, dev->limits.num_qps);
2324 mthca_alloc_cleanup(&dev->qp_table.alloc);
2325 }
2326