xref: /linux/drivers/platform/x86/amd/pmf/pmf.h (revision 3fd6c59042dbba50391e30862beac979491145fe)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * AMD Platform Management Framework Driver
4  *
5  * Copyright (c) 2022, Advanced Micro Devices, Inc.
6  * All Rights Reserved.
7  *
8  * Author: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
9  */
10 
11 #ifndef PMF_H
12 #define PMF_H
13 
14 #include <linux/acpi.h>
15 #include <linux/input.h>
16 #include <linux/platform_device.h>
17 #include <linux/platform_profile.h>
18 
19 #define POLICY_BUF_MAX_SZ		0x4b000
20 #define POLICY_SIGN_COOKIE		0x31535024
21 #define POLICY_COOKIE_OFFSET		0x10
22 
23 /* List of supported CPU ids */
24 #define AMD_CPU_ID_RMB                  0x14b5
25 #define AMD_CPU_ID_PS                   0x14e8
26 #define PCI_DEVICE_ID_AMD_1AH_M20H_ROOT 0x1507
27 #define PCI_DEVICE_ID_AMD_1AH_M60H_ROOT 0x1122
28 
29 struct cookie_header {
30 	u32 sign;
31 	u32 length;
32 } __packed;
33 
34 /* APMF Functions */
35 #define APMF_FUNC_VERIFY_INTERFACE			0
36 #define APMF_FUNC_GET_SYS_PARAMS			1
37 #define APMF_FUNC_SBIOS_REQUESTS			2
38 #define APMF_FUNC_SBIOS_HEARTBEAT			4
39 #define APMF_FUNC_AUTO_MODE					5
40 #define APMF_FUNC_SET_FAN_IDX				7
41 #define APMF_FUNC_OS_POWER_SLIDER_UPDATE		8
42 #define APMF_FUNC_STATIC_SLIDER_GRANULAR       9
43 #define APMF_FUNC_DYN_SLIDER_AC				11
44 #define APMF_FUNC_DYN_SLIDER_DC				12
45 #define APMF_FUNC_NOTIFY_SMART_PC_UPDATES		14
46 #define APMF_FUNC_SBIOS_HEARTBEAT_V2			16
47 
48 /* Message Definitions */
49 #define SET_SPL				0x03 /* SPL: Sustained Power Limit */
50 #define SET_SPPT			0x05 /* SPPT: Slow Package Power Tracking */
51 #define SET_FPPT			0x07 /* FPPT: Fast Package Power Tracking */
52 #define GET_SPL				0x0B
53 #define GET_SPPT			0x0D
54 #define GET_FPPT			0x0F
55 #define SET_DRAM_ADDR_HIGH	0x14
56 #define SET_DRAM_ADDR_LOW	0x15
57 #define SET_TRANSFER_TABLE	0x16
58 #define SET_STT_MIN_LIMIT	0x18 /* STT: Skin Temperature Tracking */
59 #define SET_STT_LIMIT_APU	0x19
60 #define SET_STT_LIMIT_HS2	0x1A
61 #define SET_SPPT_APU_ONLY	0x1D
62 #define GET_SPPT_APU_ONLY	0x1E
63 #define GET_STT_MIN_LIMIT	0x1F
64 #define GET_STT_LIMIT_APU	0x20
65 #define GET_STT_LIMIT_HS2	0x21
66 #define SET_P3T				0x23 /* P3T: Peak Package Power Limit */
67 #define SET_PMF_PPT            0x25
68 #define SET_PMF_PPT_APU_ONLY   0x26
69 
70 /* OS slider update notification */
71 #define DC_BEST_PERF		0
72 #define DC_BETTER_PERF		1
73 #define DC_BATTERY_SAVER	3
74 #define AC_BEST_PERF		4
75 #define AC_BETTER_PERF		5
76 #define AC_BETTER_BATTERY	6
77 
78 /* Fan Index for Auto Mode */
79 #define FAN_INDEX_AUTO		0xFFFFFFFF
80 
81 #define ARG_NONE 0
82 #define AVG_SAMPLE_SIZE 3
83 
84 /* Policy Actions */
85 #define PMF_POLICY_SPL						2
86 #define PMF_POLICY_SPPT						3
87 #define PMF_POLICY_FPPT						4
88 #define PMF_POLICY_SPPT_APU_ONLY				5
89 #define PMF_POLICY_STT_MIN					6
90 #define PMF_POLICY_STT_SKINTEMP_APU				7
91 #define PMF_POLICY_STT_SKINTEMP_HS2				8
92 #define PMF_POLICY_SYSTEM_STATE					9
93 #define PMF_POLICY_BIOS_OUTPUT_1				10
94 #define PMF_POLICY_BIOS_OUTPUT_2				11
95 #define PMF_POLICY_P3T						38
96 #define PMF_POLICY_BIOS_OUTPUT_3				57
97 #define PMF_POLICY_BIOS_OUTPUT_4				58
98 #define PMF_POLICY_BIOS_OUTPUT_5				59
99 #define PMF_POLICY_BIOS_OUTPUT_6				60
100 #define PMF_POLICY_BIOS_OUTPUT_7				61
101 #define PMF_POLICY_BIOS_OUTPUT_8				62
102 #define PMF_POLICY_BIOS_OUTPUT_9				63
103 #define PMF_POLICY_BIOS_OUTPUT_10				64
104 
105 /* TA macros */
106 #define PMF_TA_IF_VERSION_MAJOR				1
107 #define TA_PMF_ACTION_MAX					32
108 #define TA_PMF_UNDO_MAX						8
109 #define TA_OUTPUT_RESERVED_MEM				906
110 #define MAX_OPERATION_PARAMS					4
111 
112 #define PMF_IF_V1		1
113 #define PMF_IF_V2		2
114 
115 #define APTS_MAX_STATES		16
116 
117 /* APTS PMF BIOS Interface */
118 struct amd_pmf_apts_output {
119 	u16 table_version;
120 	u32 fan_table_idx;
121 	u32 pmf_ppt;
122 	u32 ppt_pmf_apu_only;
123 	u32 stt_min_limit;
124 	u8 stt_skin_temp_limit_apu;
125 	u8 stt_skin_temp_limit_hs2;
126 } __packed;
127 
128 struct amd_pmf_apts_granular_output {
129 	u16 size;
130 	struct amd_pmf_apts_output val;
131 } __packed;
132 
133 struct amd_pmf_apts_granular {
134 	u16 size;
135 	struct amd_pmf_apts_output val[APTS_MAX_STATES];
136 };
137 
138 struct sbios_hb_event_v2 {
139 	u16 size;
140 	u8 load;
141 	u8 unload;
142 	u8 suspend;
143 	u8 resume;
144 } __packed;
145 
146 enum sbios_hb_v2 {
147 	ON_LOAD,
148 	ON_UNLOAD,
149 	ON_SUSPEND,
150 	ON_RESUME,
151 };
152 
153 /* AMD PMF BIOS interfaces */
154 struct apmf_verify_interface {
155 	u16 size;
156 	u16 version;
157 	u32 notification_mask;
158 	u32 supported_functions;
159 } __packed;
160 
161 struct apmf_system_params {
162 	u16 size;
163 	u32 valid_mask;
164 	u32 flags;
165 	u8 command_code;
166 	u32 heartbeat_int;
167 } __packed;
168 
169 struct apmf_sbios_req {
170 	u16 size;
171 	u32 pending_req;
172 	u8 rsd;
173 	u8 cql_event;
174 	u8 amt_event;
175 	u32 fppt;
176 	u32 sppt;
177 	u32 fppt_apu_only;
178 	u32 spl;
179 	u32 stt_min_limit;
180 	u8 skin_temp_apu;
181 	u8 skin_temp_hs2;
182 } __packed;
183 
184 struct apmf_sbios_req_v2 {
185 	u16 size;
186 	u32 pending_req;
187 	u8 rsd;
188 	u32 ppt_pmf;
189 	u32 ppt_pmf_apu_only;
190 	u32 stt_min_limit;
191 	u8 skin_temp_apu;
192 	u8 skin_temp_hs2;
193 	u32 custom_policy[10];
194 } __packed;
195 
196 struct apmf_fan_idx {
197 	u16 size;
198 	u8 fan_ctl_mode;
199 	u32 fan_ctl_idx;
200 } __packed;
201 
202 struct smu_pmf_metrics_v2 {
203 	u16 core_frequency[16];		/* MHz */
204 	u16 core_power[16];		/* mW */
205 	u16 core_temp[16];		/* centi-C */
206 	u16 gfx_temp;			/* centi-C */
207 	u16 soc_temp;			/* centi-C */
208 	u16 stapm_opn_limit;		/* mW */
209 	u16 stapm_cur_limit;		/* mW */
210 	u16 infra_cpu_maxfreq;		/* MHz */
211 	u16 infra_gfx_maxfreq;		/* MHz */
212 	u16 skin_temp;			/* centi-C */
213 	u16 gfxclk_freq;		/* MHz */
214 	u16 fclk_freq;			/* MHz */
215 	u16 gfx_activity;		/* GFX busy % [0-100] */
216 	u16 socclk_freq;		/* MHz */
217 	u16 vclk_freq;			/* MHz */
218 	u16 vcn_activity;		/* VCN busy % [0-100] */
219 	u16 vpeclk_freq;		/* MHz */
220 	u16 ipuclk_freq;		/* MHz */
221 	u16 ipu_busy[8];		/* NPU busy % [0-100] */
222 	u16 dram_reads;			/* MB/sec */
223 	u16 dram_writes;		/* MB/sec */
224 	u16 core_c0residency[16];	/* C0 residency % [0-100] */
225 	u16 ipu_power;			/* mW */
226 	u32 apu_power;			/* mW */
227 	u32 gfx_power;			/* mW */
228 	u32 dgpu_power;			/* mW */
229 	u32 socket_power;		/* mW */
230 	u32 all_core_power;		/* mW */
231 	u32 filter_alpha_value;		/* time constant [us] */
232 	u32 metrics_counter;
233 	u16 memclk_freq;		/* MHz */
234 	u16 mpipuclk_freq;		/* MHz */
235 	u16 ipu_reads;			/* MB/sec */
236 	u16 ipu_writes;			/* MB/sec */
237 	u32 throttle_residency_prochot;
238 	u32 throttle_residency_spl;
239 	u32 throttle_residency_fppt;
240 	u32 throttle_residency_sppt;
241 	u32 throttle_residency_thm_core;
242 	u32 throttle_residency_thm_gfx;
243 	u32 throttle_residency_thm_soc;
244 	u16 psys;
245 	u16 spare1;
246 	u32 spare[6];
247 } __packed;
248 
249 struct smu_pmf_metrics {
250 	u16 gfxclk_freq; /* in MHz */
251 	u16 socclk_freq; /* in MHz */
252 	u16 vclk_freq; /* in MHz */
253 	u16 dclk_freq; /* in MHz */
254 	u16 memclk_freq; /* in MHz */
255 	u16 spare;
256 	u16 gfx_activity; /* in Centi */
257 	u16 uvd_activity; /* in Centi */
258 	u16 voltage[2]; /* in mV */
259 	u16 currents[2]; /* in mA */
260 	u16 power[2];/* in mW */
261 	u16 core_freq[8]; /* in MHz */
262 	u16 core_power[8]; /* in mW */
263 	u16 core_temp[8]; /* in centi-Celsius */
264 	u16 l3_freq; /* in MHz */
265 	u16 l3_temp; /* in centi-Celsius */
266 	u16 gfx_temp; /* in centi-Celsius */
267 	u16 soc_temp; /* in centi-Celsius */
268 	u16 throttler_status;
269 	u16 current_socketpower; /* in mW */
270 	u16 stapm_orig_limit; /* in W */
271 	u16 stapm_cur_limit; /* in W */
272 	u32 apu_power; /* in mW */
273 	u32 dgpu_power; /* in mW */
274 	u16 vdd_tdc_val; /* in mA */
275 	u16 soc_tdc_val; /* in mA */
276 	u16 vdd_edc_val; /* in mA */
277 	u16 soc_edcv_al; /* in mA */
278 	u16 infra_cpu_maxfreq; /* in MHz */
279 	u16 infra_gfx_maxfreq; /* in MHz */
280 	u16 skin_temp; /* in centi-Celsius */
281 	u16 device_state;
282 	u16 curtemp; /* in centi-Celsius */
283 	u16 filter_alpha_value;
284 	u16 avg_gfx_clkfrequency;
285 	u16 avg_fclk_frequency;
286 	u16 avg_gfx_activity;
287 	u16 avg_socclk_frequency;
288 	u16 avg_vclk_frequency;
289 	u16 avg_vcn_activity;
290 	u16 avg_dram_reads;
291 	u16 avg_dram_writes;
292 	u16 avg_socket_power;
293 	u16 avg_core_power[2];
294 	u16 avg_core_c0residency[16];
295 	u16 spare1;
296 	u32 metrics_counter;
297 } __packed;
298 
299 enum amd_stt_skin_temp {
300 	STT_TEMP_APU,
301 	STT_TEMP_HS2,
302 	STT_TEMP_COUNT,
303 };
304 
305 enum amd_slider_op {
306 	SLIDER_OP_GET,
307 	SLIDER_OP_SET,
308 };
309 
310 enum power_source {
311 	POWER_SOURCE_AC,
312 	POWER_SOURCE_DC,
313 	POWER_SOURCE_MAX,
314 };
315 
316 enum power_modes {
317 	POWER_MODE_PERFORMANCE,
318 	POWER_MODE_BALANCED_POWER,
319 	POWER_MODE_POWER_SAVER,
320 	POWER_MODE_MAX,
321 };
322 
323 enum power_modes_v2 {
324 	POWER_MODE_BEST_PERFORMANCE,
325 	POWER_MODE_BALANCED,
326 	POWER_MODE_BEST_POWER_EFFICIENCY,
327 	POWER_MODE_ENERGY_SAVE,
328 	POWER_MODE_V2_MAX,
329 };
330 
331 struct amd_pmf_dev {
332 	void __iomem *regbase;
333 	void __iomem *smu_virt_addr;
334 	void *buf;
335 	u32 base_addr;
336 	u32 cpu_id;
337 	struct device *dev;
338 	struct mutex lock; /* protects the PMF interface */
339 	u32 supported_func;
340 	enum platform_profile_option current_profile;
341 	struct platform_profile_handler pprof;
342 	struct dentry *dbgfs_dir;
343 	int hb_interval; /* SBIOS heartbeat interval */
344 	struct delayed_work heart_beat;
345 	struct smu_pmf_metrics m_table;
346 	struct smu_pmf_metrics_v2 m_table_v2;
347 	struct delayed_work work_buffer;
348 	ktime_t start_time;
349 	int socket_power_history[AVG_SAMPLE_SIZE];
350 	int socket_power_history_idx;
351 	bool amt_enabled;
352 	struct mutex update_mutex; /* protects race between ACPI handler and metrics thread */
353 	bool cnqf_enabled;
354 	bool cnqf_supported;
355 	struct notifier_block pwr_src_notifier;
356 	/* Smart PC solution builder */
357 	struct dentry *esbin;
358 	unsigned char *policy_buf;
359 	resource_size_t policy_sz;
360 	struct tee_context *tee_ctx;
361 	struct tee_shm *fw_shm_pool;
362 	u32 session_id;
363 	void *shbuf;
364 	struct delayed_work pb_work;
365 	struct pmf_action_table *prev_data;
366 	resource_size_t policy_addr;
367 	void __iomem *policy_base;
368 	bool smart_pc_enabled;
369 	u16 pmf_if_version;
370 	struct input_dev *pmf_idev;
371 	size_t mtable_size;
372 	struct resource *res;
373 };
374 
375 struct apmf_sps_prop_granular_v2 {
376 	u8 power_states[POWER_SOURCE_MAX][POWER_MODE_V2_MAX];
377 } __packed;
378 
379 struct apmf_sps_prop_granular {
380 	u32 fppt;
381 	u32 sppt;
382 	u32 sppt_apu_only;
383 	u32 spl;
384 	u32 stt_min;
385 	u8 stt_skin_temp[STT_TEMP_COUNT];
386 	u32 fan_id;
387 } __packed;
388 
389 /* Static Slider */
390 struct apmf_static_slider_granular_output {
391 	u16 size;
392 	struct apmf_sps_prop_granular prop[POWER_SOURCE_MAX * POWER_MODE_MAX];
393 } __packed;
394 
395 struct amd_pmf_static_slider_granular {
396 	u16 size;
397 	struct apmf_sps_prop_granular prop[POWER_SOURCE_MAX][POWER_MODE_MAX];
398 };
399 
400 struct apmf_static_slider_granular_output_v2 {
401 	u16 size;
402 	struct apmf_sps_prop_granular_v2 sps_idx;
403 } __packed;
404 
405 struct amd_pmf_static_slider_granular_v2 {
406 	u16 size;
407 	struct apmf_sps_prop_granular_v2 sps_idx;
408 };
409 
410 struct os_power_slider {
411 	u16 size;
412 	u8 slider_event;
413 } __packed;
414 
415 struct amd_pmf_notify_smart_pc_update {
416 	u16 size;
417 	u32 pending_req;
418 	u32 custom_bios[10];
419 } __packed;
420 
421 struct fan_table_control {
422 	bool manual;
423 	unsigned long fan_id;
424 };
425 
426 struct power_table_control {
427 	u32 spl;
428 	u32 sppt;
429 	u32 fppt;
430 	u32 sppt_apu_only;
431 	u32 stt_min;
432 	u32 stt_skin_temp[STT_TEMP_COUNT];
433 	u32 reserved[16];
434 };
435 
436 /* Auto Mode Layer */
437 enum auto_mode_transition_priority {
438 	AUTO_TRANSITION_TO_PERFORMANCE, /* Any other mode to Performance Mode */
439 	AUTO_TRANSITION_FROM_QUIET_TO_BALANCE, /* Quiet Mode to Balance Mode */
440 	AUTO_TRANSITION_TO_QUIET, /* Any other mode to Quiet Mode */
441 	AUTO_TRANSITION_FROM_PERFORMANCE_TO_BALANCE, /* Performance Mode to Balance Mode */
442 	AUTO_TRANSITION_MAX,
443 };
444 
445 enum auto_mode_mode {
446 	AUTO_QUIET,
447 	AUTO_BALANCE,
448 	AUTO_PERFORMANCE_ON_LAP,
449 	AUTO_PERFORMANCE,
450 	AUTO_MODE_MAX,
451 };
452 
453 struct auto_mode_trans_params {
454 	u32 time_constant; /* minimum time required to switch to next mode */
455 	u32 power_delta; /* delta power to shift mode */
456 	u32 power_threshold;
457 	u32 timer; /* elapsed time. if timer > TimeThreshold, it will move to next mode */
458 	u32 applied;
459 	enum auto_mode_mode target_mode;
460 	u32 shifting_up;
461 };
462 
463 struct auto_mode_mode_settings {
464 	struct power_table_control power_control;
465 	struct fan_table_control fan_control;
466 	u32 power_floor;
467 };
468 
469 struct auto_mode_mode_config {
470 	struct auto_mode_trans_params transition[AUTO_TRANSITION_MAX];
471 	struct auto_mode_mode_settings mode_set[AUTO_MODE_MAX];
472 	enum auto_mode_mode current_mode;
473 };
474 
475 struct apmf_auto_mode {
476 	u16 size;
477 	/* time constant */
478 	u32 balanced_to_perf;
479 	u32 perf_to_balanced;
480 	u32 quiet_to_balanced;
481 	u32 balanced_to_quiet;
482 	/* power floor */
483 	u32 pfloor_perf;
484 	u32 pfloor_balanced;
485 	u32 pfloor_quiet;
486 	/* Power delta for mode change */
487 	u32 pd_balanced_to_perf;
488 	u32 pd_perf_to_balanced;
489 	u32 pd_quiet_to_balanced;
490 	u32 pd_balanced_to_quiet;
491 	/* skin temperature limits */
492 	u8 stt_apu_perf_on_lap; /* CQL ON */
493 	u8 stt_hs2_perf_on_lap; /* CQL ON */
494 	u8 stt_apu_perf;
495 	u8 stt_hs2_perf;
496 	u8 stt_apu_balanced;
497 	u8 stt_hs2_balanced;
498 	u8 stt_apu_quiet;
499 	u8 stt_hs2_quiet;
500 	u32 stt_min_limit_perf_on_lap; /* CQL ON */
501 	u32 stt_min_limit_perf;
502 	u32 stt_min_limit_balanced;
503 	u32 stt_min_limit_quiet;
504 	/* SPL based */
505 	u32 fppt_perf_on_lap; /* CQL ON */
506 	u32 sppt_perf_on_lap; /* CQL ON */
507 	u32 spl_perf_on_lap; /* CQL ON */
508 	u32 sppt_apu_only_perf_on_lap; /* CQL ON */
509 	u32 fppt_perf;
510 	u32 sppt_perf;
511 	u32 spl_perf;
512 	u32 sppt_apu_only_perf;
513 	u32 fppt_balanced;
514 	u32 sppt_balanced;
515 	u32 spl_balanced;
516 	u32 sppt_apu_only_balanced;
517 	u32 fppt_quiet;
518 	u32 sppt_quiet;
519 	u32 spl_quiet;
520 	u32 sppt_apu_only_quiet;
521 	/* Fan ID */
522 	u32 fan_id_perf;
523 	u32 fan_id_balanced;
524 	u32 fan_id_quiet;
525 } __packed;
526 
527 /* CnQF Layer */
528 enum cnqf_trans_priority {
529 	CNQF_TRANSITION_TO_TURBO, /* Any other mode to Turbo Mode */
530 	CNQF_TRANSITION_FROM_BALANCE_TO_PERFORMANCE, /* quiet/balance to Performance Mode */
531 	CNQF_TRANSITION_FROM_QUIET_TO_BALANCE, /* Quiet Mode to Balance Mode */
532 	CNQF_TRANSITION_TO_QUIET, /* Any other mode to Quiet Mode */
533 	CNQF_TRANSITION_FROM_PERFORMANCE_TO_BALANCE, /* Performance/Turbo to Balance Mode */
534 	CNQF_TRANSITION_FROM_TURBO_TO_PERFORMANCE, /* Turbo mode to Performance Mode */
535 	CNQF_TRANSITION_MAX,
536 };
537 
538 enum cnqf_mode {
539 	CNQF_MODE_QUIET,
540 	CNQF_MODE_BALANCE,
541 	CNQF_MODE_PERFORMANCE,
542 	CNQF_MODE_TURBO,
543 	CNQF_MODE_MAX,
544 };
545 
546 enum apmf_cnqf_pos {
547 	APMF_CNQF_TURBO,
548 	APMF_CNQF_PERFORMANCE,
549 	APMF_CNQF_BALANCE,
550 	APMF_CNQF_QUIET,
551 	APMF_CNQF_MAX,
552 };
553 
554 struct cnqf_mode_settings {
555 	struct power_table_control power_control;
556 	struct fan_table_control fan_control;
557 	u32 power_floor;
558 };
559 
560 struct cnqf_tran_params {
561 	u32 time_constant; /* minimum time required to switch to next mode */
562 	u32 power_threshold;
563 	u32 timer; /* elapsed time. if timer > timethreshold, it will move to next mode */
564 	u32 total_power;
565 	u32 count;
566 	bool priority;
567 	bool shifting_up;
568 	enum cnqf_mode target_mode;
569 };
570 
571 struct cnqf_config {
572 	struct cnqf_tran_params trans_param[POWER_SOURCE_MAX][CNQF_TRANSITION_MAX];
573 	struct cnqf_mode_settings mode_set[POWER_SOURCE_MAX][CNQF_MODE_MAX];
574 	struct power_table_control defaults;
575 	enum cnqf_mode current_mode;
576 	u32 power_src;
577 	u32 avg_power;
578 };
579 
580 struct apmf_cnqf_power_set {
581 	u32 pfloor;
582 	u32 fppt;
583 	u32 sppt;
584 	u32 sppt_apu_only;
585 	u32 spl;
586 	u32 stt_min_limit;
587 	u8 stt_skintemp[STT_TEMP_COUNT];
588 	u32 fan_id;
589 } __packed;
590 
591 struct apmf_dyn_slider_output {
592 	u16 size;
593 	u16 flags;
594 	u32 t_perf_to_turbo;
595 	u32 t_balanced_to_perf;
596 	u32 t_quiet_to_balanced;
597 	u32 t_balanced_to_quiet;
598 	u32 t_perf_to_balanced;
599 	u32 t_turbo_to_perf;
600 	struct apmf_cnqf_power_set ps[APMF_CNQF_MAX];
601 } __packed;
602 
603 /* Smart PC - TA internals */
604 enum system_state {
605 	SYSTEM_STATE_S0i3,
606 	SYSTEM_STATE_S4,
607 	SYSTEM_STATE_SCREEN_LOCK,
608 	SYSTEM_STATE_MAX,
609 };
610 
611 enum ta_slider {
612 	TA_BEST_BATTERY,
613 	TA_BETTER_BATTERY,
614 	TA_BETTER_PERFORMANCE,
615 	TA_BEST_PERFORMANCE,
616 	TA_MAX,
617 };
618 
619 /* Command ids for TA communication */
620 enum ta_pmf_command {
621 	TA_PMF_COMMAND_POLICY_BUILDER_INITIALIZE,
622 	TA_PMF_COMMAND_POLICY_BUILDER_ENACT_POLICIES,
623 };
624 
625 enum ta_pmf_error_type {
626 	TA_PMF_TYPE_SUCCESS,
627 	TA_PMF_ERROR_TYPE_GENERIC,
628 	TA_PMF_ERROR_TYPE_CRYPTO,
629 	TA_PMF_ERROR_TYPE_CRYPTO_VALIDATE,
630 	TA_PMF_ERROR_TYPE_CRYPTO_VERIFY_OEM,
631 	TA_PMF_ERROR_TYPE_POLICY_BUILDER,
632 	TA_PMF_ERROR_TYPE_PB_CONVERT,
633 	TA_PMF_ERROR_TYPE_PB_SETUP,
634 	TA_PMF_ERROR_TYPE_PB_ENACT,
635 	TA_PMF_ERROR_TYPE_ASD_GET_DEVICE_INFO,
636 	TA_PMF_ERROR_TYPE_ASD_GET_DEVICE_PCIE_INFO,
637 	TA_PMF_ERROR_TYPE_SYS_DRV_FW_VALIDATION,
638 	TA_PMF_ERROR_TYPE_MAX,
639 };
640 
641 struct pmf_action_table {
642 	enum system_state system_state;
643 	u32 spl;		/* in mW */
644 	u32 sppt;		/* in mW */
645 	u32 sppt_apuonly;	/* in mW */
646 	u32 fppt;		/* in mW */
647 	u32 stt_minlimit;	/* in mW */
648 	u32 stt_skintemp_apu;	/* in C */
649 	u32 stt_skintemp_hs2;	/* in C */
650 	u32 p3t_limit;		/* in mW */
651 };
652 
653 /* Input conditions */
654 struct ta_pmf_condition_info {
655 	u32 power_source;
656 	u32 bat_percentage;
657 	u32 power_slider;
658 	u32 lid_state;
659 	bool user_present;
660 	u32 rsvd1[2];
661 	u32 monitor_count;
662 	u32 rsvd2[2];
663 	u32 bat_design;
664 	u32 full_charge_capacity;
665 	int drain_rate;
666 	bool user_engaged;
667 	u32 device_state;
668 	u32 socket_power;
669 	u32 skin_temperature;
670 	u32 rsvd3[5];
671 	u32 ambient_light;
672 	u32 length;
673 	u32 avg_c0residency;
674 	u32 max_c0residency;
675 	u32 s0i3_entry;
676 	u32 gfx_busy;
677 	u32 rsvd4[7];
678 	bool camera_state;
679 	u32 workload_type;
680 	u32 display_type;
681 	u32 display_state;
682 	u32 rsvd5[150];
683 };
684 
685 struct ta_pmf_load_policy_table {
686 	u32 table_size;
687 	u8 table[POLICY_BUF_MAX_SZ];
688 };
689 
690 /* TA initialization params */
691 struct ta_pmf_init_table {
692 	u32 frequency; /* SMU sampling frequency */
693 	bool validate;
694 	bool sku_check;
695 	bool metadata_macrocheck;
696 	struct ta_pmf_load_policy_table policies_table;
697 };
698 
699 /* Everything the TA needs to Enact Policies */
700 struct ta_pmf_enact_table {
701 	struct ta_pmf_condition_info ev_info;
702 	u32 name;
703 };
704 
705 struct ta_pmf_action {
706 	u32 action_index;
707 	u32 value;
708 };
709 
710 /* Output actions from TA */
711 struct ta_pmf_enact_result {
712 	u32 actions_count;
713 	struct ta_pmf_action actions_list[TA_PMF_ACTION_MAX];
714 	u32 undo_count;
715 	struct ta_pmf_action undo_list[TA_PMF_UNDO_MAX];
716 };
717 
718 union ta_pmf_input {
719 	struct ta_pmf_enact_table enact_table;
720 	struct ta_pmf_init_table init_table;
721 };
722 
723 union ta_pmf_output {
724 	struct ta_pmf_enact_result policy_apply_table;
725 	u32 rsvd[TA_OUTPUT_RESERVED_MEM];
726 };
727 
728 struct ta_pmf_shared_memory {
729 	int command_id;
730 	int resp_id;
731 	u32 pmf_result;
732 	u32 if_version;
733 	union ta_pmf_output pmf_output;
734 	union ta_pmf_input pmf_input;
735 };
736 
737 /* Core Layer */
738 int apmf_acpi_init(struct amd_pmf_dev *pmf_dev);
739 void apmf_acpi_deinit(struct amd_pmf_dev *pmf_dev);
740 int is_apmf_func_supported(struct amd_pmf_dev *pdev, unsigned long index);
741 int amd_pmf_send_cmd(struct amd_pmf_dev *dev, u8 message, bool get, u32 arg, u32 *data);
742 int amd_pmf_init_metrics_table(struct amd_pmf_dev *dev);
743 int amd_pmf_get_power_source(void);
744 int apmf_install_handler(struct amd_pmf_dev *pmf_dev);
745 int apmf_os_power_slider_update(struct amd_pmf_dev *dev, u8 flag);
746 int amd_pmf_set_dram_addr(struct amd_pmf_dev *dev, bool alloc_buffer);
747 int amd_pmf_notify_sbios_heartbeat_event_v2(struct amd_pmf_dev *dev, u8 flag);
748 
749 /* SPS Layer */
750 int amd_pmf_get_pprof_modes(struct amd_pmf_dev *pmf);
751 void amd_pmf_update_slider(struct amd_pmf_dev *dev, bool op, int idx,
752 			   struct amd_pmf_static_slider_granular *table);
753 int amd_pmf_init_sps(struct amd_pmf_dev *dev);
754 void amd_pmf_deinit_sps(struct amd_pmf_dev *dev);
755 int apmf_get_static_slider_granular(struct amd_pmf_dev *pdev,
756 				    struct apmf_static_slider_granular_output *output);
757 bool is_pprof_balanced(struct amd_pmf_dev *pmf);
758 int amd_pmf_power_slider_update_event(struct amd_pmf_dev *dev);
759 const char *amd_pmf_source_as_str(unsigned int state);
760 
761 const char *amd_pmf_source_as_str(unsigned int state);
762 
763 int apmf_update_fan_idx(struct amd_pmf_dev *pdev, bool manual, u32 idx);
764 int amd_pmf_set_sps_power_limits(struct amd_pmf_dev *pmf);
765 int apmf_get_static_slider_granular_v2(struct amd_pmf_dev *dev,
766 				       struct apmf_static_slider_granular_output_v2 *data);
767 int apts_get_static_slider_granular_v2(struct amd_pmf_dev *pdev,
768 				       struct amd_pmf_apts_granular_output *data, u32 apts_idx);
769 
770 /* Auto Mode Layer */
771 int apmf_get_auto_mode_def(struct amd_pmf_dev *pdev, struct apmf_auto_mode *data);
772 void amd_pmf_init_auto_mode(struct amd_pmf_dev *dev);
773 void amd_pmf_deinit_auto_mode(struct amd_pmf_dev *dev);
774 void amd_pmf_trans_automode(struct amd_pmf_dev *dev, int socket_power, ktime_t time_elapsed_ms);
775 int apmf_get_sbios_requests(struct amd_pmf_dev *pdev, struct apmf_sbios_req *req);
776 int apmf_get_sbios_requests_v2(struct amd_pmf_dev *pdev, struct apmf_sbios_req_v2 *req);
777 
778 void amd_pmf_update_2_cql(struct amd_pmf_dev *dev, bool is_cql_event);
779 int amd_pmf_reset_amt(struct amd_pmf_dev *dev);
780 void amd_pmf_handle_amt(struct amd_pmf_dev *dev);
781 
782 /* CnQF Layer */
783 int apmf_get_dyn_slider_def_ac(struct amd_pmf_dev *pdev, struct apmf_dyn_slider_output *data);
784 int apmf_get_dyn_slider_def_dc(struct amd_pmf_dev *pdev, struct apmf_dyn_slider_output *data);
785 int amd_pmf_init_cnqf(struct amd_pmf_dev *dev);
786 void amd_pmf_deinit_cnqf(struct amd_pmf_dev *dev);
787 int amd_pmf_trans_cnqf(struct amd_pmf_dev *dev, int socket_power, ktime_t time_lapsed_ms);
788 extern const struct attribute_group cnqf_feature_attribute_group;
789 
790 /* Smart PC builder Layer */
791 int amd_pmf_init_smart_pc(struct amd_pmf_dev *dev);
792 void amd_pmf_deinit_smart_pc(struct amd_pmf_dev *dev);
793 int apmf_check_smart_pc(struct amd_pmf_dev *pmf_dev);
794 int amd_pmf_smartpc_apply_bios_output(struct amd_pmf_dev *dev, u32 val, u32 preq, u32 idx);
795 
796 /* Smart PC - TA interfaces */
797 void amd_pmf_populate_ta_inputs(struct amd_pmf_dev *dev, struct ta_pmf_enact_table *in);
798 void amd_pmf_dump_ta_inputs(struct amd_pmf_dev *dev, struct ta_pmf_enact_table *in);
799 
800 /* Quirk infrastructure */
801 void amd_pmf_quirks_init(struct amd_pmf_dev *dev);
802 
803 #endif /* PMF_H */
804