1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 *
24 * Copyright 2007 Sun Microsystems, Inc. All rights reserved.
25 * Use is subject to license terms.
26 */
27
28 #include <mcamd_api.h>
29 #include <mcamd_err.h>
30 #include <mcamd_rowcol_impl.h>
31
32 /*
33 * =========== Chip-Select Bank Address Mode Encodings =======================
34 */
35
36 /* Individual table declarations */
37 static const struct rct_bnkaddrmode bnkaddr_tbls_pre_d[];
38 static const struct rct_bnkaddrmode bnkaddr_tbls_d_e[];
39 static const struct rct_bnkaddrmode bnkaddr_tbls_f[];
40
41 /* Managing bank address mode tables */
42 static const struct _bnkaddrmode_tbldesc {
43 uint_t revmask;
44 int nmodes;
45 const struct rct_bnkaddrmode *modetbl;
46 } bnkaddr_tbls[] = {
47 { MC_F_REVS_BC, 7, bnkaddr_tbls_pre_d },
48 { MC_F_REVS_DE, 11, bnkaddr_tbls_d_e },
49 { MC_F_REVS_FG, 12, bnkaddr_tbls_f },
50 };
51
52 /*
53 * =========== DRAM Address Mappings for bank/row/column =====================
54 */
55
56
57 /* Individual table declarations */
58 struct _rcbmap_tbl {
59 uint_t mt_revmask; /* revision to which this applies */
60 int mt_width; /* MC mode (64 or 128) */
61 const struct rct_rcbmap mt_csmap[MC_RC_CSMODES];
62 };
63
64 static const struct _rcbmap_tbl dram_addrmap_pre_d_64;
65 static const struct _rcbmap_tbl dram_addrmap_pre_d_128;
66 static const struct _rcbmap_tbl dram_addrmap_d_e_64;
67 static const struct _rcbmap_tbl dram_addrmap_d_e_128;
68 static const struct _rcbmap_tbl dram_addrmap_f_64;
69 static const struct _rcbmap_tbl dram_addrmap_f_128;
70
71 /* Managing row/column/bank tables */
72 static const struct _rcbmap_tbldesc {
73 int nmodes;
74 const struct _rcbmap_tbl *rcbmap;
75 } rcbmap_tbls[] = {
76 { 7, &dram_addrmap_pre_d_64 },
77 { 7, &dram_addrmap_pre_d_128 },
78 { 11, &dram_addrmap_d_e_64 },
79 { 11, &dram_addrmap_d_e_128 },
80 { 12, &dram_addrmap_f_64 },
81 { 12, &dram_addrmap_f_128 },
82 };
83
84 /*
85 * =========== Bank swizzling information ====================================
86 */
87
88 /* Individual table declarations */
89 struct _bnkswzl_tbl {
90 uint_t swzt_revmask; /* revision to which this applies */
91 int swzt_width; /* MC mode (64 or 128) */
92 const struct rct_bnkswzlinfo swzt_bits;
93 };
94
95 static const struct _bnkswzl_tbl bnswzl_info_e_64;
96 static const struct _bnkswzl_tbl bnswzl_info_e_128;
97 static const struct _bnkswzl_tbl bnswzl_info_f_64;
98 static const struct _bnkswzl_tbl bnswzl_info_f_128;
99
100 /* Managing bank swizzle tables */
101 static const struct _bnkswzl_tbl *bnkswzl_tbls[] = {
102 &bnswzl_info_e_64,
103 &bnswzl_info_e_128,
104 &bnswzl_info_f_64,
105 &bnswzl_info_f_128,
106 };
107
108 /*
109 * ======================================================================
110 * | Tables reflecting those in the BKDG |
111 * ======================================================================
112 */
113
114 /*
115 * DRAM Address Mapping in Interleaving Mode
116 *
117 * Chip-select interleave is performed by addressing across the columns
118 * of the first row of internal bank-select 0 on a chip-select, then the
119 * next row on internal bank-select 1, then 2 then 3; instead of then
120 * moving on to the next row of this chip-select we then rotate across
121 * other chip-selects in the interleave. The row/column/bank mappings
122 * described elsewhere in this file show that a DRAM InputAddr breaks down
123 * as follows, using an example for CS Mode 0000 revision CG and earlier 64-bit
124 * mode; the cs size is 32MB, requiring 25 bits to address all of it.
125 *
126 * chip-selection bits | offset within chip-select bits |
127 * | row bits | bank bits | column bits | - |
128 * 24 13 12 11 10 3 2 0
129 *
130 * The high-order chip-selection bits select the chip-select and the
131 * offset bits offset within the chosen chip-select.
132 *
133 * To establish say a 2-way interleave in which we consume all of one
134 * row number and all internal bank numbers on one cs before moving on
135 * to the next to do the same we will target the first row bit - bit 13;
136 * a 4-way interleave would use bits 14 and 13, and an 8-way interleave
137 * bits 15, 14 and 13. We swap the chosen bits with the least significant
138 * high order chip-selection bits.
139 *
140 * The BKDG interleave tables really just describe the above. Working
141 * out the high-order bits to swap is easy since that is derived directly
142 * from the chip-select size. The low-order bits depend on the device
143 * parameters since we need to target the least significant row address bits -
144 * but we have that information from the rcbmap_tbls since the first row bit
145 * simply follows the last bank address bit.
146 */
147
148 /*
149 * General notes for CS Bank Address Mode Encoding tables.
150 *
151 * These are indexed by chip-select mode. Where the numbers of rows and
152 * columns is ambiguous (as it is for a number of rev CG and earlier cases)
153 * the bam_config should be initialized to 1 and the numbers of rows
154 * and columns should be the maximums.
155 */
156
157 /*
158 * Chip Select Bank Address Mode Encoding for rev CG and earlier.
159 */
160 static const struct rct_bnkaddrmode bnkaddr_tbls_pre_d[] = {
161 { /* 000 */
162 32, 12, 8
163 },
164 { /* 001 */
165 64, 12, 9
166 },
167 { /* 010 */
168 128, 13, 10, 1 /* AMBIG */
169 },
170 { /* 011 */
171 256, 13, 11, 1 /* AMBIG */
172 },
173 { /* 100 */
174 512, 14, 11, 1 /* AMBIG */
175 },
176 { /* 101 */
177 1024, 14, 12, 1 /* AMBIG */
178 },
179 { /* 110 */
180 2048, 14, 12
181 }
182 };
183
184 /*
185 * Chip Select Bank Address Mode Encoding for revs D and E.
186 */
187 static const struct rct_bnkaddrmode bnkaddr_tbls_d_e[] = {
188 { /* 0000 */
189 32, 12, 8
190 },
191 { /* 0001 */
192 64, 12, 9
193 },
194 { /* 0010 */
195 128, 13, 9
196 },
197 { /* 0011 */
198 128, 12, 10
199 },
200 { /* 0100 */
201 256, 13, 10
202 },
203 { /* 0101 */
204 512, 14, 10
205 },
206 { /* 0110 */
207 256, 12, 11
208 },
209 { /* 0111 */
210 512, 13, 11
211 },
212 { /* 1000 */
213 1024, 14, 11
214 },
215 { /* 1001 */
216 1024, 13, 12
217 },
218 { /* 1010 */
219 2048, 14, 12
220 }
221 };
222
223 /*
224 * Chip Select Bank Address Mode Encoding for rev F
225 */
226 static const struct rct_bnkaddrmode bnkaddr_tbls_f[] = {
227 { /* 0000 */
228 128, 13, 9
229 },
230 { /* 0001 */
231 256, 13, 10
232 },
233 { /* 0010 */
234 512, 14, 10
235 },
236 { /* 0011 */
237 512, 13, 11
238 },
239 { /* 0100 */
240 512, 13, 10
241 },
242 { /* 0101 */
243 1024, 14, 10
244 },
245 { /* 0110 */
246 1024, 14, 11
247 },
248 { /* 0111 */
249 2048, 15, 10
250 },
251 { /* 1000 */
252 2048, 14, 11
253 },
254 { /* 1001 */
255 4096, 15, 11
256 },
257 { /* 1010 */
258 4096, 16, 10
259 },
260 { /* 1011 */
261 8192, 16, 11
262 }
263
264 };
265
266 /*
267 * General notes on Row/Column/Bank table initialisation.
268 *
269 * These are the tables 7, 8, 9, 10, 11 and 12 of BKDG 3.29 section 3.5.6.1.
270 * They apply in non-interleave (node or cs) mode and describe how for
271 * a given revision, access width, bank-swizzle mode, and current chip-select
272 * mode the row, column and internal sdram bank are derived from the
273 * normalizied InputAddr presented to the DRAM controller.
274 *
275 * The mt_csmap array is indexed by chip-select mode. Within it the
276 * bankargs, rowbits and colbits arrays are indexed by bit number, so
277 * match the BKDG tables if the latter are read right-to-left.
278 *
279 * The bankargs list up to three bit numbers per bank bit. For revisions
280 * CG and earlier there is no bank swizzling, so just a single number
281 * should be listed. Revisions D and E have the same row/column/bank mapping,
282 * but rev E has the additional feature of being able to xor two row bits
283 * into each bank bit. The consumer will know whether they are using bank
284 * swizzling - if so then they should xor the bankargs bits together.
285 * The first argument must be the bit number not already used in forming
286 * part of the row address - eg in table 12 for csmode 0000b bank address
287 * bit 0 is bit 12 xor bit 18 xor bit 21, and 18 and 21 are also mentioned in
288 * the row address (bits 10 and 1) so we must list bit 12 first. We will
289 * use this information in chip-select interleave decoding in which we need
290 * to know which is the first bit after column and bank address bits.
291 *
292 * Column address A10 is always used for the Precharge All signal. Where
293 * "PC" appears in the BKDG tables we will include MC_PC_ALL in the
294 * corresponding bit position.
295 *
296 * For some rev CG and earlier chipselect modes the number of rows and columns
297 * is ambiguous. This is reflected in these tables by some bit being
298 * duplicated between row and column address. In practice we will follow
299 * the convention of always assigning the floating bit to the row address.
300 */
301
302 /*
303 * Row/Column/Bank address mappings for rev CG in 64-bit mode, no interleave.
304 * See BKDG 3.29 3.5.6 Table 7.
305 */
306 static const struct _rcbmap_tbl dram_addrmap_pre_d_64 = {
307 MC_F_REVS_BC,
308 64,
309 {
310 { /* 000 */
311 2, { 11, 12 },
312 { 19, 20, 21, 22, 23, 24, 13, 14, 15, 16, 17, 18 },
313 { 3, 4, 5, 6, 7, 8, 9, 10 }
314 },
315 { /* 001 */
316 2, { 13, 12 },
317 { 19, 20, 21, 22, 23, 24, 25, 14, 15, 16, 17, 18 },
318 { 3, 4, 5, 6, 7, 8, 9, 10, 11 }
319 },
320 { /* 010 */
321 2, { 13, 12 },
322 { 19, 20, 21, 22, 23, 24, 25, 14, 15, 16, 17, 18, 26 },
323 { 3, 4, 5, 6, 7, 8, 9, 10, 11, 26 }
324 },
325 { /* 011 */
326 2, { 13, 14 },
327 { 19, 20, 21, 22, 23, 24, 25, 26, 15, 16, 17, 18, 27 },
328 { 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, MC_PC_ALL, 27 }
329 },
330 { /* 100 */
331 2, { 13, 14 },
332 { 19, 20, 21, 22, 23, 24, 25, 26, 15, 16, 17, 18, 27, 28 },
333 { 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, MC_PC_ALL, 28 }
334 },
335 { /* 101 */
336 2, { 15, 14 },
337 { 19, 20, 21, 22, 23, 24, 25, 26, 29, 16, 17, 18, 27, 28 },
338 { 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, MC_PC_ALL, 13, 28 }
339 },
340 { /* 110 */
341 2, { 15, 14 },
342 { 19, 20, 21, 22, 23, 24, 25, 26, 29, 16, 17, 18, 27, 28 },
343 { 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, MC_PC_ALL, 13, 30 }
344 },
345 /*
346 * remainder unused
347 */
348 }
349
350 };
351
352 /*
353 * Row/Column/Bank address mappings for rev CG in 128-bit mode, no interleave.
354 * See BKDG 3.29 3.5.6 Table 8.
355 */
356 static const struct _rcbmap_tbl dram_addrmap_pre_d_128 = {
357 MC_F_REVS_BC,
358 128,
359 {
360 { /* 000 */
361 2, { 12, 13 },
362 { 20, 21, 22, 23, 24, 25, 14, 15, 16, 17, 18, 19 },
363 { 4, 5, 6, 7, 8, 9, 10, 11 }
364 },
365 { /* 001 */
366 2, { 14, 13 },
367 { 20, 21, 22, 23, 24, 25, 26, 15, 16, 17, 18, 19 },
368 { 4, 5, 6, 7, 8, 9, 10, 11, 12 }
369 },
370 { /* 010 */
371 2, { 14, 13 },
372 { 20, 21, 22, 23, 24, 25, 26, 15, 16, 17, 18, 19, 27 },
373 { 4, 5, 6, 7, 8, 9, 10, 11, 12, 27 }
374 },
375 { /* 011 */
376 2, { 14, 15 },
377 { 20, 21, 22, 23, 24, 25, 26, 27, 16, 17, 18, 19, 28 },
378 { 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, MC_PC_ALL, 28 }
379 },
380 { /* 100 */
381 2, { 14, 15 },
382 { 20, 21, 22, 23, 24, 25, 26, 27, 16, 17, 18, 19, 28, 29 },
383 { 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, MC_PC_ALL, 29 }
384 },
385 { /* 101 */
386 2, { 16, 15 },
387 { 20, 21, 22, 23, 24, 25, 26, 27, 30, 17, 18, 19, 28, 29 },
388 { 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, MC_PC_ALL, 14, 29 }
389 },
390 { /* 110 */
391 2, { 16, 15 },
392 { 20, 21, 22, 23, 24, 25, 26, 27, 30, 17, 18, 19, 28, 29 },
393 { 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, MC_PC_ALL, 14, 31 }
394 },
395 /*
396 * remainder unused
397 */
398 }
399 };
400
401 /*
402 * Row/Column/Bank address mappings for rev D/E in 64-bit mode, no interleave.
403 * See BKDG 3.29 3.5.6 Table 9.
404 */
405 static const struct _rcbmap_tbl dram_addrmap_d_e_64 = {
406 MC_F_REVS_DE,
407 64,
408 {
409 { /* 0000 */
410 2, { 11, 12 },
411 { 19, 20, 21, 22, 23, 24, 13, 14, 15, 16, 17, 18 },
412 { 3, 4, 5, 6, 7, 8, 9, 10 }
413 },
414 { /* 0001 */
415 2, { 12, 13 },
416 { 19, 20, 21, 22, 23, 24, 25, 14, 15, 16, 17, 18, 26 },
417 { 3, 4, 5, 6, 7, 8, 9, 10, 11 }
418 },
419 { /* 0010 */
420 2, { 12, 13 },
421 { 19, 20, 21, 22, 23, 24, 25, 14, 15, 16, 17, 18, 26 },
422 { 3, 4, 5, 6, 7, 8, 9, 10, 11 }
423 },
424 { /* 0011 */
425 2, { 13, 14 },
426 { 19, 20, 21, 22, 23, 24, 25, 26, 15, 16, 17, 18, 27, 28 },
427 { 3, 4, 5, 6, 7, 8, 9, 10, 11, 12 }
428 },
429 { /* 0100 */
430 2, { 13, 14 },
431 { 19, 20, 21, 22, 23, 24, 25, 26, 15, 16, 17, 18, 27, 28 },
432 { 3, 4, 5, 6, 7, 8, 9, 10, 11, 12 }
433 },
434 { /* 0101 */
435 2, { 13, 14 },
436 { 19, 20, 21, 22, 23, 24, 25, 26, 15, 16, 17, 18, 27, 28 },
437 { 3, 4, 5, 6, 7, 8, 9, 10, 11, 12 }
438 },
439 { /* 0110 */
440 2, { 14, 15 },
441 { 19, 20, 21, 22, 23, 24, 25, 26, 27, 16, 17, 18, 28, 29 },
442 { 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, MC_PC_ALL, 13 }
443 },
444 { /* 0111 */
445 2, { 14, 15 },
446 { 19, 20, 21, 22, 23, 24, 25, 26, 27, 16, 17, 18, 28, 29 },
447 { 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, MC_PC_ALL, 13 }
448 },
449 { /* 1000 */
450 2, { 14, 15 },
451 { 19, 20, 21, 22, 23, 24, 25, 26, 27, 16, 17, 18, 28, 29 },
452 { 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, MC_PC_ALL, 13 }
453 },
454 { /* 1001 */
455 2, { 15, 16 },
456 { 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 17, 18, 29, 30 },
457 { 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, MC_PC_ALL, 13, 14 }
458 },
459 { /* 1010 */
460 2, { 15, 16 },
461 { 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 17, 18, 29, 30 },
462 { 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, MC_PC_ALL, 13, 14 }
463 },
464 /*
465 * remainder unused
466 */
467 }
468 };
469
470 /*
471 * Row/Column/Bank address mappings for rev D/E in 128-bit mode, no interleave.
472 * See BKDG 3.29 3.5.6 Table 9.
473 */
474 static const struct _rcbmap_tbl dram_addrmap_d_e_128 = {
475 MC_F_REVS_DE,
476 128,
477 {
478 { /* 0000 */
479 2, { 12, 13 },
480 { 20, 21, 22, 23, 24, 25, 14, 15, 16, 17, 18, 19 },
481 { 4, 5, 6, 7, 8, 9, 10, 11 }
482 },
483 { /* 0001 */
484 2, { 13, 14 },
485 { 20, 21, 22, 23, 24, 25, 26, 15, 16, 17, 18, 19, 27 },
486 { 4, 5, 6, 7, 8, 9, 10, 11, 12 }
487 },
488 { /* 0010 */
489 2, { 13, 14 },
490 { 20, 21, 22, 23, 24, 25, 26, 15, 16, 17, 18, 19, 27 },
491 { 4, 5, 6, 7, 8, 9, 10, 11, 12 }
492 },
493 { /* 0011 */
494 2, { 14, 15 },
495 { 20, 21, 22, 23, 24, 25, 26, 27, 16, 17, 18, 19, 28, 29 },
496 { 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 }
497 },
498 { /* 0100 */
499 2, { 14, 15 },
500 { 20, 21, 22, 23, 24, 25, 26, 27, 16, 17, 18, 19, 28, 29 },
501 { 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 }
502 },
503 { /* 0101 */
504 2, { 14, 15 },
505 { 20, 21, 22, 23, 24, 25, 26, 27, 16, 17, 18, 19, 28, 29 },
506 { 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 }
507 },
508 { /* 0110 */
509 2, { 15, 16 },
510 { 20, 21, 22, 23, 24, 25, 26, 27, 28, 17, 18, 19, 29, 30 },
511 { 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, MC_PC_ALL, 14 }
512 },
513 { /* 0111 */
514 2, { 15, 16 },
515 { 20, 21, 22, 23, 24, 25, 26, 27, 28, 17, 18, 19, 29, 30 },
516 { 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, MC_PC_ALL, 14 }
517 },
518 { /* 1000 */
519 2, { 15, 16 },
520 { 20, 21, 22, 23, 24, 25, 26, 27, 28, 17, 18, 19, 29, 30 },
521 { 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, MC_PC_ALL, 14 }
522 },
523 { /* 1001 */
524 2, { 16, 17 },
525 { 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 18, 19, 30, 31 },
526 { 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, MC_PC_ALL, 14, 15 }
527 },
528 { /* 1010 */
529 2, { 16, 17 },
530 { 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 18, 19, 30, 31 },
531 { 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, MC_PC_ALL, 14, 15 }
532 },
533 /*
534 * remainder unused
535 */
536 }
537 };
538
539 /*
540 * Row/Column/Bank address mappings for revs F/G in 64-bit mode, no interleave.
541 */
542 static const struct _rcbmap_tbl dram_addrmap_f_64 = {
543 MC_F_REVS_FG,
544 64,
545 {
546 { /* 0000 */
547 2, { 12, 13 },
548 { 18, 19, 20, 21, 22, 23, 24, 25, 26, 14, 15, 16, 17 },
549 { 3, 4, 5, 6, 7, 8, 9, 10, 11 },
550 },
551 { /* 0001 */
552 2, { 13, 14 },
553 { 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 15, 16, 17 },
554 { 3, 4, 5, 6, 7, 8, 9, 10, 11, 12 },
555 },
556 { /* 0010 */
557 2, { 13, 14 },
558 { 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 15, 16, 17 },
559 { 3, 4, 5, 6, 7, 8, 9, 10, 11, 12 },
560 },
561 { /* 0011 */
562 2, { 14, 15 },
563 { 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 16, 17 },
564 { 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, MC_PC_ALL, 13 },
565 },
566 { /* 0100 */
567 3, { 13, 14, 15 },
568 { 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 16, 17 },
569 { 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, MC_PC_ALL, 13 },
570 },
571 { /* 0101 */
572 3, { 13, 14, 15 },
573 { 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 16, 17 },
574 { 3, 4, 5, 6, 7, 8, 9, 10, 11, 12 }
575 },
576 { /* 0110 */
577 2, { 14, 15 },
578 { 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 16, 17 },
579 { 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, MC_PC_ALL, 13 },
580 },
581 { /* 0111 */
582 3, { 13, 14, 15 },
583 { 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 16, 17 },
584 { 3, 4, 5, 6, 7, 8, 9, 10, 11, 12 }
585 },
586 { /* 1000 */
587 3, { 14, 15, 16 },
588 { 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 17 },
589 { 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, MC_PC_ALL, 13 },
590 },
591 { /* 1001 */
592 3, { 14, 15, 16 },
593 { 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 17 },
594 { 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, MC_PC_ALL, 13 },
595 },
596 { /* 1010 */
597 3, { 13, 14, 15 },
598 { 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
599 16, 17 },
600 { 3, 4, 5, 6, 7, 8, 9, 10, 11, 12 }
601 },
602 { /* 1011 */
603 3, { 14, 15, 16 },
604 { 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
605 17 },
606 { 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, MC_PC_ALL, 13 },
607 },
608 /*
609 * remainder unused
610 */
611 }
612 };
613
614 /*
615 * Row/Column/Bank address mappings for revs F/G in 128-bit mode, no interleave.
616 */
617 static const struct _rcbmap_tbl dram_addrmap_f_128 = {
618 MC_F_REVS_FG,
619 128,
620 {
621 { /* 0000 */
622 2, { 13, 14 },
623 { 19, 20, 21, 22, 23, 24, 25, 26, 27, 15, 16, 17, 18 },
624 { 4, 5, 6, 7, 8, 9, 10, 11, 12 },
625 },
626 { /* 0001 */
627 2, { 14, 15 },
628 { 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 16, 17, 18 },
629 { 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 },
630 },
631 { /* 0010 */
632 2, { 14, 15 },
633 { 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 16, 17, 18 },
634 { 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 },
635 },
636 { /* 0011 */
637 2, { 15, 16 },
638 { 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 17, 18 },
639 { 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, MC_PC_ALL, 14 },
640 },
641 { /* 0100 */
642 3, { 14, 15, 16 },
643 { 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 17, 18 },
644 { 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 },
645 },
646 { /* 0101 */
647 3, { 14, 15, 16 },
648 { 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 17, 18 },
649 { 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 },
650 },
651 { /* 0110 */
652 2, { 15, 16 },
653 { 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 17, 18 },
654 { 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, MC_PC_ALL, 14 },
655 },
656 { /* 0111 */
657 3, { 14, 15, 16 },
658 { 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
659 17, 18 },
660 { 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 },
661 },
662 { /* 1000 */
663 3, { 15, 16, 17 },
664 { 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
665 18 },
666 { 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, MC_PC_ALL, 14 },
667 },
668 { /* 1001 */
669 3, { 15, 16, 17 },
670 { 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
671 18 },
672 { 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, MC_PC_ALL, 14 },
673 },
674 { /* 1010 */
675 3, { 14, 15, 16 },
676 { 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
677 17, 18 },
678 { 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 },
679 },
680 { /* 1011 */
681 3, { 15, 16, 17 },
682 { 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33,
683 18 },
684 { 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, MC_PC_ALL, 14 },
685 },
686 /*
687 * remainder unused
688 */
689 }
690 };
691
692 /*
693 * Bank swizzling is an option in revisions E and later. Each internal-bank-
694 * select address bit is xor'd with two row address bits. Which row
695 * address bits to use is not dependent on bank address mode but on
696 * revision and dram controller width alone.
697 *
698 * While rev E only supports 2 bank address bits, rev F supports 3 but not
699 * all chip-select bank address modes use all 3. These tables will list
700 * the row bits to use in swizzling for the maximum number of supported
701 * bank address bits - the consumer musr determine how many should be
702 * applied (listed in the above row/col/bank tables).
703 */
704
705 static const struct _bnkswzl_tbl bnswzl_info_e_64 = {
706 MC_F_REV_E,
707 64,
708 {
709 {
710 { 17, 20 }, /* rows bits to swizzle with BA0 */
711 { 18, 21 }, /* rows bits to swizzle with BA1 */
712 /* only 2 bankaddr bits on rev E */
713 }
714 }
715 };
716
717 static const struct _bnkswzl_tbl bnswzl_info_e_128 = {
718 MC_F_REV_E,
719 128,
720 {
721 {
722 { 18, 21 }, /* rows bits to swizzle with BA0 */
723 { 19, 22 }, /* rows bits to swizzle with BA1 */
724 /* only 2 bankaddr bits on rev E */
725 }
726 }
727 };
728
729 static const struct _bnkswzl_tbl bnswzl_info_f_64 = {
730 MC_F_REVS_FG,
731 64,
732 {
733 {
734 { 17, 22 }, /* rows bits to swizzle with BA0 */
735 { 18, 23 }, /* rows bits to swizzle with BA1 */
736 { 19, 24 }, /* rows bits to swizzle with BA2 */
737 }
738 }
739 };
740
741 static const struct _bnkswzl_tbl bnswzl_info_f_128 = {
742 MC_F_REVS_FG,
743 128,
744 {
745 {
746 { 18, 23 }, /* rows bits to swizzle with BA0 */
747 { 19, 24 }, /* rows bits to swizzle with BA1 */
748 { 20, 25 }, /* rows bits to swizzle with BA2 */
749 }
750 }
751 };
752
753 /*
754 * Yet another highbit function. This really needs to go to common source.
755 * Returns range 0 to 64 inclusive;
756 */
757 static int
topbit(uint64_t i)758 topbit(uint64_t i)
759 {
760 int h = 1;
761
762 if (i == 0)
763 return (0);
764
765 if (i & 0xffffffff00000000ULL) {
766 h += 32;
767 i >>= 32;
768 }
769
770 if (i & 0xffff0000) {
771 h += 16;
772 i >>= 16;
773 }
774
775 if (i & 0xff00) {
776 h += 8;
777 i >>= 8;
778 }
779
780 if (i & 0xf0) {
781 h += 4;
782 i >>= 4;
783 }
784
785 if (i & 0xc) {
786 h += 2;
787 i >>= 2;
788 }
789
790 if (i & 0x2)
791 h += 1;
792
793 return (h);
794 }
795
796 /*
797 * Lookup the Chip-Select Bank Address Mode Encoding table for a given
798 * chip revision and chip-select mode.
799 */
800 const struct rct_bnkaddrmode *
rct_bnkaddrmode(uint_t mcrev,uint_t csmode)801 rct_bnkaddrmode(uint_t mcrev, uint_t csmode)
802 {
803 int i;
804 const struct _bnkaddrmode_tbldesc *bdp = bnkaddr_tbls;
805
806 for (i = 0; i < sizeof (bnkaddr_tbls) /
807 sizeof (struct _bnkaddrmode_tbldesc);
808 i++, bdp++) {
809 if (MC_REV_MATCH(mcrev, bdp->revmask) && csmode < bdp->nmodes)
810 return (&bdp->modetbl[csmode]);
811
812 }
813
814 return (NULL);
815 }
816
817 /*
818 * Lookup the DRAM Address Mapping table for a given chip revision, access
819 * width, bank-swizzle and chip-select mode.
820 */
821 const struct rct_rcbmap *
rct_rcbmap(uint_t mcrev,int width,uint_t csmode)822 rct_rcbmap(uint_t mcrev, int width, uint_t csmode)
823 {
824 const struct _rcbmap_tbl *rcbm;
825 int i;
826
827 for (i = 0; i < sizeof (rcbmap_tbls) /
828 sizeof (struct _rcbmap_tbldesc); i++) {
829 rcbm = rcbmap_tbls[i].rcbmap;
830 if (MC_REV_MATCH(mcrev, rcbm->mt_revmask) &&
831 rcbm->mt_width == width && csmode < rcbmap_tbls[i].nmodes)
832 return (&rcbm->mt_csmap[csmode]);
833 }
834
835 return (NULL);
836 }
837
838 /*
839 * Lookup the bank swizzling information for a given chip revision and
840 * access width.
841 */
842 const struct rct_bnkswzlinfo *
rct_bnkswzlinfo(uint_t mcrev,int width)843 rct_bnkswzlinfo(uint_t mcrev, int width)
844 {
845 int i;
846 const struct _bnkswzl_tbl *swztp;
847
848 for (i = 0; i < sizeof (bnkswzl_tbls) /
849 sizeof (struct rcb_bnkswzl_tbl *); i++) {
850 swztp = bnkswzl_tbls[i];
851 if (MC_REV_MATCH(mcrev, swztp->swzt_revmask) &&
852 swztp->swzt_width == width)
853 return (&swztp->swzt_bits);
854 }
855
856 return (NULL);
857 }
858
859 void
rct_csintlv_bits(uint_t mcrev,int width,uint_t csmode,int factor,struct rct_csintlv * csid)860 rct_csintlv_bits(uint_t mcrev, int width, uint_t csmode, int factor,
861 struct rct_csintlv *csid)
862 {
863 int i, lstbnkbit;
864 size_t csz;
865 const struct rct_bnkaddrmode *bam;
866 const struct rct_rcbmap *rcm;
867
868 /*
869 * 8-way cs interleave for some large cs sizes in 128-bit mode is
870 * not implemented prior to rev F.
871 */
872 if (factor == 8 && width == 128 &&
873 ((MC_REV_MATCH(mcrev, MC_F_REVS_BC) && csmode == 0x6) ||
874 (MC_REV_MATCH(mcrev, MC_F_REVS_DE) &&
875 (csmode == 0x9 || csmode == 0xa)))) {
876 csid->csi_factor = 0;
877 return;
878 }
879
880 if ((bam = rct_bnkaddrmode(mcrev, csmode)) == NULL ||
881 (rcm = rct_rcbmap(mcrev, width, csmode)) == NULL) {
882 csid->csi_factor = 0;
883 return;
884 }
885
886 csz = MC_CS_SIZE(bam, width);
887
888 switch (factor) {
889 case 2:
890 csid->csi_nbits = 1;
891 break;
892 case 4:
893 csid->csi_nbits = 2;
894 break;
895 case 8:
896 csid->csi_nbits = 3;
897 break;
898 default:
899 csid->csi_factor = 0;
900 return;
901 }
902
903 csid->csi_hibit = topbit(csz) - 1;
904
905 /*
906 * The first row bit is immediately after the last bank bit.
907 */
908 lstbnkbit = 0;
909 for (i = 0; i < rcm->rcb_nbankbits; i++)
910 if (rcm->rcb_bankbit[i] > lstbnkbit)
911 lstbnkbit = rcm->rcb_bankbit[i];
912
913 csid->csi_lobit = lstbnkbit + 1;
914
915 csid->csi_factor = factor;
916 }
917