1 // SPDX-License-Identifier: ISC
2 /*
3 * Copyright (C) 2022 MediaTek Inc.
4 */
5
6 #if defined(__FreeBSD__)
7 #define LINUXKPI_PARAM_PREFIX mt7996_
8 #endif
9
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/pci.h>
13 #include <linux/rtnetlink.h>
14
15 #include "mt7996.h"
16 #include "mac.h"
17 #include "mcu.h"
18 #include "../trace.h"
19 #include "../dma.h"
20
21 static bool wed_enable;
22 module_param(wed_enable, bool, 0644);
23 #if defined(__FreeBSD__)
24 MODULE_PARM_DESC(wed_enable, "Enable Wireless Ethernet Dispatch support");
25 #endif
26
27 static const struct __base mt7996_reg_base[] = {
28 [WF_AGG_BASE] = { { 0x820e2000, 0x820f2000, 0x830e2000 } },
29 [WF_ARB_BASE] = { { 0x820e3000, 0x820f3000, 0x830e3000 } },
30 [WF_TMAC_BASE] = { { 0x820e4000, 0x820f4000, 0x830e4000 } },
31 [WF_RMAC_BASE] = { { 0x820e5000, 0x820f5000, 0x830e5000 } },
32 [WF_DMA_BASE] = { { 0x820e7000, 0x820f7000, 0x830e7000 } },
33 [WF_WTBLOFF_BASE] = { { 0x820e9000, 0x820f9000, 0x830e9000 } },
34 [WF_ETBF_BASE] = { { 0x820ea000, 0x820fa000, 0x830ea000 } },
35 [WF_LPON_BASE] = { { 0x820eb000, 0x820fb000, 0x830eb000 } },
36 [WF_MIB_BASE] = { { 0x820ed000, 0x820fd000, 0x830ed000 } },
37 [WF_RATE_BASE] = { { 0x820ee000, 0x820fe000, 0x830ee000 } },
38 };
39
40 static const u32 mt7996_offs[] = {
41 [MIB_RVSR0] = 0x720,
42 [MIB_RVSR1] = 0x724,
43 [MIB_BTSCR5] = 0x788,
44 [MIB_BTSCR6] = 0x798,
45 [MIB_RSCR1] = 0x7ac,
46 [MIB_RSCR27] = 0x954,
47 [MIB_RSCR28] = 0x958,
48 [MIB_RSCR29] = 0x95c,
49 [MIB_RSCR30] = 0x960,
50 [MIB_RSCR31] = 0x964,
51 [MIB_RSCR33] = 0x96c,
52 [MIB_RSCR35] = 0x974,
53 [MIB_RSCR36] = 0x978,
54 [MIB_BSCR0] = 0x9cc,
55 [MIB_BSCR1] = 0x9d0,
56 [MIB_BSCR2] = 0x9d4,
57 [MIB_BSCR3] = 0x9d8,
58 [MIB_BSCR4] = 0x9dc,
59 [MIB_BSCR5] = 0x9e0,
60 [MIB_BSCR6] = 0x9e4,
61 [MIB_BSCR7] = 0x9e8,
62 [MIB_BSCR17] = 0xa10,
63 [MIB_TRDR1] = 0xa28,
64 [HIF_REMAP_L1] = 0x24,
65 [HIF_REMAP_BASE_L1] = 0x130000,
66 [HIF_REMAP_L2] = 0x1b4,
67 [HIF_REMAP_BASE_L2] = 0x1000,
68 [CBTOP1_PHY_END] = 0x77ffffff,
69 [INFRA_MCU_END] = 0x7c3fffff,
70 [WTBLON_WDUCR] = 0x370,
71 [WTBL_UPDATE] = 0x380,
72 [WTBL_ITCR] = 0x3b0,
73 [WTBL_ITCR0] = 0x3b8,
74 [WTBL_ITCR1] = 0x3bc,
75 };
76
77 static const u32 mt7992_offs[] = {
78 [MIB_RVSR0] = 0x760,
79 [MIB_RVSR1] = 0x764,
80 [MIB_BTSCR5] = 0x7c8,
81 [MIB_BTSCR6] = 0x7d8,
82 [MIB_RSCR1] = 0x7f0,
83 [MIB_RSCR27] = 0x998,
84 [MIB_RSCR28] = 0x99c,
85 [MIB_RSCR29] = 0x9a0,
86 [MIB_RSCR30] = 0x9a4,
87 [MIB_RSCR31] = 0x9a8,
88 [MIB_RSCR33] = 0x9b0,
89 [MIB_RSCR35] = 0x9b8,
90 [MIB_RSCR36] = 0x9bc,
91 [MIB_BSCR0] = 0xac8,
92 [MIB_BSCR1] = 0xacc,
93 [MIB_BSCR2] = 0xad0,
94 [MIB_BSCR3] = 0xad4,
95 [MIB_BSCR4] = 0xad8,
96 [MIB_BSCR5] = 0xadc,
97 [MIB_BSCR6] = 0xae0,
98 [MIB_BSCR7] = 0xae4,
99 [MIB_BSCR17] = 0xb0c,
100 [MIB_TRDR1] = 0xb24,
101 [HIF_REMAP_L1] = 0x8,
102 [HIF_REMAP_BASE_L1] = 0x40000,
103 [HIF_REMAP_L2] = 0x1b4,
104 [HIF_REMAP_BASE_L2] = 0x1000,
105 [CBTOP1_PHY_END] = 0x77ffffff,
106 [INFRA_MCU_END] = 0x7c3fffff,
107 [WTBLON_WDUCR] = 0x370,
108 [WTBL_UPDATE] = 0x380,
109 [WTBL_ITCR] = 0x3b0,
110 [WTBL_ITCR0] = 0x3b8,
111 [WTBL_ITCR1] = 0x3bc,
112 };
113
114 static const u32 mt7990_offs[] = {
115 [MIB_RVSR0] = 0x800,
116 [MIB_RVSR1] = 0x804,
117 [MIB_BTSCR5] = 0x868,
118 [MIB_BTSCR6] = 0x878,
119 [MIB_RSCR1] = 0x890,
120 [MIB_RSCR27] = 0xa38,
121 [MIB_RSCR28] = 0xa3c,
122 [MIB_RSCR29] = 0xa40,
123 [MIB_RSCR30] = 0xa44,
124 [MIB_RSCR31] = 0xa48,
125 [MIB_RSCR33] = 0xa50,
126 [MIB_RSCR35] = 0xa58,
127 [MIB_RSCR36] = 0xa5c,
128 [MIB_BSCR0] = 0xbb8,
129 [MIB_BSCR1] = 0xbbc,
130 [MIB_BSCR2] = 0xbc0,
131 [MIB_BSCR3] = 0xbc4,
132 [MIB_BSCR4] = 0xbc8,
133 [MIB_BSCR5] = 0xbcc,
134 [MIB_BSCR6] = 0xbd0,
135 [MIB_BSCR7] = 0xbd4,
136 [MIB_BSCR17] = 0xbfc,
137 [MIB_TRDR1] = 0xc14,
138 [HIF_REMAP_L1] = 0x8,
139 [HIF_REMAP_BASE_L1] = 0x40000,
140 [HIF_REMAP_L2] = 0x1b8,
141 [HIF_REMAP_BASE_L2] = 0x110000,
142 [CBTOP1_PHY_END] = 0x7fffffff,
143 [INFRA_MCU_END] = 0x7cffffff,
144 [WTBLON_WDUCR] = 0x400,
145 [WTBL_UPDATE] = 0x410,
146 [WTBL_ITCR] = 0x440,
147 [WTBL_ITCR0] = 0x448,
148 [WTBL_ITCR1] = 0x44c,
149 };
150
151 static const struct __map mt7996_reg_map[] = {
152 { 0x54000000, 0x02000, 0x1000 }, /* WFDMA_0 (PCIE0 MCU DMA0) */
153 { 0x55000000, 0x03000, 0x1000 }, /* WFDMA_1 (PCIE0 MCU DMA1) */
154 { 0x56000000, 0x04000, 0x1000 }, /* WFDMA reserved */
155 { 0x57000000, 0x05000, 0x1000 }, /* WFDMA MCU wrap CR */
156 { 0x58000000, 0x06000, 0x1000 }, /* WFDMA PCIE1 MCU DMA0 (MEM_DMA) */
157 { 0x59000000, 0x07000, 0x1000 }, /* WFDMA PCIE1 MCU DMA1 */
158 { 0x820c0000, 0x08000, 0x4000 }, /* WF_UMAC_TOP (PLE) */
159 { 0x820c8000, 0x0c000, 0x2000 }, /* WF_UMAC_TOP (PSE) */
160 { 0x820cc000, 0x0e000, 0x1000 }, /* WF_UMAC_TOP (PP) */
161 { 0x74030000, 0x10000, 0x1000 }, /* PCIe MAC */
162 { 0x820e0000, 0x20000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */
163 { 0x820e1000, 0x20400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */
164 { 0x820e2000, 0x20800, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */
165 { 0x820e3000, 0x20c00, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */
166 { 0x820e4000, 0x21000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */
167 { 0x820e5000, 0x21400, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */
168 { 0x820ce000, 0x21c00, 0x0200 }, /* WF_LMAC_TOP (WF_SEC) */
169 { 0x820e7000, 0x21e00, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */
170 { 0x820cf000, 0x22000, 0x1000 }, /* WF_LMAC_TOP (WF_PF) */
171 { 0x820e9000, 0x23400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */
172 { 0x820ea000, 0x24000, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */
173 { 0x820eb000, 0x24200, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */
174 { 0x820ec000, 0x24600, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_INT) */
175 { 0x820ed000, 0x24800, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */
176 { 0x820ca000, 0x26000, 0x2000 }, /* WF_LMAC_TOP BN0 (WF_MUCOP) */
177 { 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */
178 { 0x40000000, 0x70000, 0x10000 }, /* WF_UMAC_SYSRAM */
179 { 0x00400000, 0x80000, 0x10000 }, /* WF_MCU_SYSRAM */
180 { 0x00410000, 0x90000, 0x10000 }, /* WF_MCU_SYSRAM (configure register) */
181 { 0x820f0000, 0xa0000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */
182 { 0x820f1000, 0xa0600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */
183 { 0x820f2000, 0xa0800, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */
184 { 0x820f3000, 0xa0c00, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */
185 { 0x820f4000, 0xa1000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */
186 { 0x820f5000, 0xa1400, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */
187 { 0x820f7000, 0xa1e00, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */
188 { 0x820f9000, 0xa3400, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */
189 { 0x820fa000, 0xa4000, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */
190 { 0x820fb000, 0xa4200, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */
191 { 0x820fc000, 0xa4600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_INT) */
192 { 0x820fd000, 0xa4800, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */
193 { 0x820cc000, 0xa5000, 0x2000 }, /* WF_LMAC_TOP BN1 (WF_MUCOP) */
194 { 0x820c4000, 0xa8000, 0x4000 }, /* WF_LMAC_TOP BN1 (WF_MUCOP) */
195 { 0x820b0000, 0xae000, 0x1000 }, /* [APB2] WFSYS_ON */
196 { 0x80020000, 0xb0000, 0x10000 }, /* WF_TOP_MISC_OFF */
197 { 0x81020000, 0xc0000, 0x10000 }, /* WF_TOP_MISC_ON */
198 { 0x7c020000, 0xd0000, 0x10000 }, /* CONN_INFRA, wfdma */
199 { 0x7c060000, 0xe0000, 0x10000 }, /* CONN_INFRA, conn_host_csr_top */
200 { 0x7c000000, 0xf0000, 0x10000 }, /* CONN_INFRA */
201 { 0x0, 0x0, 0x0 }, /* imply end of search */
202 };
203
204 static const struct __map mt7990_reg_map[] = {
205 {0x54000000, 0x02000, 0x1000}, /* WFDMA_0 (PCIE0 MCU DMA0) */
206 {0x55000000, 0x03000, 0x1000}, /* WFDMA_1 (PCIE0 MCU DMA1) */
207 {0x56000000, 0x04000, 0x1000}, /* WFDMA_2 (Reserved) */
208 {0x57000000, 0x05000, 0x1000}, /* WFDMA_3 (MCU wrap CR) */
209 {0x58000000, 0x06000, 0x1000}, /* WFDMA_4 (PCIE1 MCU DMA0 (MEM_DMA)) */
210 {0x59000000, 0x07000, 0x1000}, /* WFDMA_5 (PCIE1 MCU DMA1) */
211 {0x820c0000, 0x08000, 0x4000}, /* WF_UMAC_TOP (PLE) */
212 {0x820c8000, 0x0c000, 0x2000}, /* WF_UMAC_TOP (PSE) */
213 {0x820cc000, 0x0e000, 0x2000}, /* WF_UMAC_TOP (PP) */
214 {0x820e0000, 0x20000, 0x0400}, /* WF_LMAC_TOP BN0 (WF_CFG) */
215 {0x820e1000, 0x20400, 0x0200}, /* WF_LMAC_TOP BN0 (WF_TRB) */
216 {0x820e2000, 0x20800, 0x0400}, /* WF_LMAC_TOP BN0 (WF_AGG) */
217 {0x820e3000, 0x20c00, 0x0400}, /* WF_LMAC_TOP BN0 (WF_ARB) */
218 {0x820e4000, 0x21000, 0x0400}, /* WF_LMAC_TOP BN0 (WF_TMAC) */
219 {0x820e5000, 0x21400, 0x0800}, /* WF_LMAC_TOP BN0 (WF_RMAC) */
220 {0x820ce000, 0x21c00, 0x0200}, /* WF_LMAC_TOP (WF_SEC) */
221 {0x820e7000, 0x21e00, 0x0200}, /* WF_LMAC_TOP BN0 (WF_DMA) */
222 {0x820cf000, 0x22000, 0x1000}, /* WF_LMAC_TOP (WF_PF) */
223 {0x820e9000, 0x23400, 0x0200}, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */
224 {0x820ea000, 0x24000, 0x0200}, /* WF_LMAC_TOP BN0 (WF_ETBF) */
225 {0x820eb000, 0x24200, 0x0400}, /* WF_LMAC_TOP BN0 (WF_LPON) */
226 {0x820ec000, 0x24600, 0x0200}, /* WF_LMAC_TOP BN0 (WF_INT) */
227 {0x820ed000, 0x24800, 0x0800}, /* WF_LMAC_TOP BN0 (WF_MIB) */
228 {0x820ca000, 0x26000, 0x2000}, /* WF_LMAC_TOP BN0 (WF_MUCOP) */
229 {0x820d0000, 0x30000, 0x10000}, /* WF_LMAC_TOP (WF_WTBLON) */
230 {0x00400000, 0x80000, 0x10000}, /* WF_MCU_SYSRAM */
231 {0x820f0000, 0xa0000, 0x0400}, /* WF_LMAC_TOP BN1 (WF_CFG) */
232 {0x820f1000, 0xa0600, 0x0200}, /* WF_LMAC_TOP BN1 (WF_TRB) */
233 {0x820f2000, 0xa0800, 0x0400}, /* WF_LMAC_TOP BN1 (WF_AGG) */
234 {0x820f3000, 0xa0c00, 0x0400}, /* WF_LMAC_TOP BN1 (WF_ARB) */
235 {0x820f4000, 0xa1000, 0x0400}, /* WF_LMAC_TOP BN1 (WF_TMAC) */
236 {0x820f5000, 0xa1400, 0x0800}, /* WF_LMAC_TOP BN1 (WF_RMAC) */
237 {0x820f7000, 0xa1e00, 0x0200}, /* WF_LMAC_TOP BN1 (WF_DMA) */
238 {0x820f9000, 0xa3400, 0x0200}, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */
239 {0x820fa000, 0xa4000, 0x0200}, /* WF_LMAC_TOP BN1 (WF_ETBF) */
240 {0x820fb000, 0xa4200, 0x0400}, /* WF_LMAC_TOP BN1 (WF_LPON) */
241 {0x820fc000, 0xa4600, 0x0200}, /* WF_LMAC_TOP BN1 (WF_INT) */
242 {0x820fd000, 0xa4800, 0x0800}, /* WF_LMAC_TOP BN1 (WF_MIB) */
243 {0x820cc000, 0xa5000, 0x2000}, /* WF_LMAC_TOP BN1 (WF_MUCOP) */
244 {0x820c4000, 0xa8000, 0x4000}, /* WF_LMAC_TOP (WF_UWTBL) */
245 {0x81030000, 0xae000, 0x100}, /* WFSYS_AON part 1 */
246 {0x81031000, 0xae100, 0x100}, /* WFSYS_AON part 2 */
247 {0x81032000, 0xae200, 0x100}, /* WFSYS_AON part 3 */
248 {0x81033000, 0xae300, 0x100}, /* WFSYS_AON part 4 */
249 {0x81034000, 0xae400, 0x100}, /* WFSYS_AON part 5 */
250 {0x80020000, 0xb0000, 0x10000}, /* WF_TOP_MISC_OFF */
251 {0x81020000, 0xc0000, 0x10000}, /* WF_TOP_MISC_ON */
252 {0x81040000, 0x120000, 0x1000}, /* WF_MCU_CFG_ON */
253 {0x81050000, 0x121000, 0x1000}, /* WF_MCU_EINT */
254 {0x81060000, 0x122000, 0x1000}, /* WF_MCU_GPT */
255 {0x81070000, 0x123000, 0x1000}, /* WF_MCU_WDT */
256 {0x80010000, 0x124000, 0x1000}, /* WF_AXIDMA */
257 {0x7c020000, 0xd0000, 0x10000}, /* CONN_INFRA, wfdma for from CODA flow use */
258 {0x7c060000, 0xe0000, 0x10000}, /* CONN_INFRA, conn_host_csr_top for from CODA flow use */
259 {0x20020000, 0xd0000, 0x10000}, /* CONN_INFRA, wfdma */
260 {0x20060000, 0xe0000, 0x10000}, /* CONN_INFRA, conn_host_csr_top */
261 {0x7c000000, 0xf0000, 0x10000}, /* CONN_INFRA */
262 {0x70020000, 0x1f0000, 0x9000}, /* PCIE remapping (AP2CONN) */
263 {0x0, 0x0, 0x0}, /* imply end of search */
264 };
265
mt7996_reg_map_l1(struct mt7996_dev * dev,u32 addr)266 static u32 mt7996_reg_map_l1(struct mt7996_dev *dev, u32 addr)
267 {
268 u32 offset = FIELD_GET(MT_HIF_REMAP_L1_OFFSET, addr);
269 u32 base = FIELD_GET(MT_HIF_REMAP_L1_BASE, addr);
270 u32 l1_mask, val;
271
272 if (is_mt7996(&dev->mt76)) {
273 l1_mask = MT_HIF_REMAP_L1_MASK_7996;
274 val = FIELD_PREP(MT_HIF_REMAP_L1_MASK_7996, base);
275 } else {
276 l1_mask = MT_HIF_REMAP_L1_MASK;
277 val = FIELD_PREP(MT_HIF_REMAP_L1_MASK, base);
278 }
279
280 dev->bus_ops->rmw(&dev->mt76, MT_HIF_REMAP_L1, l1_mask, val);
281 /* use read to push write */
282 dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_L1);
283
284 return MT_HIF_REMAP_BASE_L1 + offset;
285 }
286
mt7996_reg_map_l2(struct mt7996_dev * dev,u32 addr)287 static u32 mt7996_reg_map_l2(struct mt7996_dev *dev, u32 addr)
288 {
289 u32 offset, base, l2_mask, val;
290
291 if (is_mt7990(&dev->mt76)) {
292 offset = FIELD_GET(MT_HIF_REMAP_L2_OFFSET_7990, addr);
293 base = FIELD_GET(MT_HIF_REMAP_L2_BASE_7990, addr);
294 l2_mask = MT_HIF_REMAP_L2_MASK_7990;
295 val = FIELD_PREP(MT_HIF_REMAP_L2_MASK_7990, base);
296 } else {
297 offset = FIELD_GET(MT_HIF_REMAP_L2_OFFSET, addr);
298 base = FIELD_GET(MT_HIF_REMAP_L2_BASE, addr);
299 l2_mask = MT_HIF_REMAP_L2_MASK;
300 val = FIELD_PREP(MT_HIF_REMAP_L2_MASK, base);
301 }
302
303 dev->bus_ops->rmw(&dev->mt76, MT_HIF_REMAP_L2, l2_mask, val);
304 /* use read to push write */
305 dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_L2);
306
307 return MT_HIF_REMAP_BASE_L2 + offset;
308 }
309
mt7996_reg_map_cbtop(struct mt7996_dev * dev,u32 addr)310 static u32 mt7996_reg_map_cbtop(struct mt7996_dev *dev, u32 addr)
311 {
312 u32 offset = FIELD_GET(MT_HIF_REMAP_CBTOP_OFFSET, addr);
313 u32 base = FIELD_GET(MT_HIF_REMAP_CBTOP_BASE, addr);
314
315 dev->bus_ops->rmw(&dev->mt76, MT_HIF_REMAP_CBTOP,
316 MT_HIF_REMAP_CBTOP_MASK,
317 FIELD_PREP(MT_HIF_REMAP_CBTOP_MASK, base));
318 /* use read to push write */
319 dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_CBTOP);
320
321 return MT_HIF_REMAP_BASE_CBTOP + offset;
322 }
323
__mt7996_reg_addr(struct mt7996_dev * dev,u32 addr)324 static u32 __mt7996_reg_addr(struct mt7996_dev *dev, u32 addr)
325 {
326 int i;
327
328 if (addr < 0x100000)
329 return addr;
330
331 for (i = 0; i < dev->reg.map_size; i++) {
332 u32 ofs;
333
334 if (addr < dev->reg.map[i].phys)
335 continue;
336
337 ofs = addr - dev->reg.map[i].phys;
338 if (ofs >= dev->reg.map[i].size)
339 continue;
340
341 return dev->reg.map[i].mapped + ofs;
342 }
343
344 return 0;
345 }
346
__mt7996_reg_remap_addr(struct mt7996_dev * dev,u32 addr)347 static u32 __mt7996_reg_remap_addr(struct mt7996_dev *dev, u32 addr)
348 {
349 if ((addr >= MT_INFRA_BASE && addr < MT_WFSYS0_PHY_START) ||
350 (addr >= MT_WFSYS0_PHY_START && addr < MT_WFSYS1_PHY_START) ||
351 (addr >= MT_WFSYS1_PHY_START && addr <= MT_WFSYS1_PHY_END))
352 return mt7996_reg_map_l1(dev, addr);
353
354 /* CONN_INFRA: covert to phyiscal addr and use layer 1 remap */
355 if (addr >= MT_INFRA_MCU_START && addr <= MT_INFRA_MCU_END) {
356 addr = addr - MT_INFRA_MCU_START + MT_INFRA_BASE;
357 return mt7996_reg_map_l1(dev, addr);
358 }
359
360 if (dev_is_pci(dev->mt76.dev) &&
361 ((addr >= MT_CBTOP1_PHY_START && addr <= MT_CBTOP1_PHY_END) ||
362 addr >= MT_CBTOP2_PHY_START)) {
363 if (is_mt7990(&dev->mt76))
364 return mt7996_reg_map_cbtop(dev, addr);
365 return mt7996_reg_map_l1(dev, addr);
366 }
367
368 return mt7996_reg_map_l2(dev, addr);
369 }
370
mt7996_memcpy_fromio(struct mt7996_dev * dev,void * buf,u32 offset,size_t len)371 void mt7996_memcpy_fromio(struct mt7996_dev *dev, void *buf, u32 offset,
372 size_t len)
373 {
374 u32 addr = __mt7996_reg_addr(dev, offset);
375
376 if (addr) {
377 #if defined(__linux__)
378 memcpy_fromio(buf, dev->mt76.mmio.regs + addr, len);
379 #elif defined(__FreeBSD__)
380 memcpy_fromio(buf, (u8 *)dev->mt76.mmio.regs + addr, len);
381 #endif
382 return;
383 }
384
385 spin_lock_bh(&dev->reg_lock);
386 #if defined(__linux__)
387 memcpy_fromio(buf, dev->mt76.mmio.regs +
388 #elif defined(__FreeBSD__)
389 memcpy_fromio(buf, (u8 *)dev->mt76.mmio.regs +
390 #endif
391 __mt7996_reg_remap_addr(dev, offset), len);
392 spin_unlock_bh(&dev->reg_lock);
393 }
394
mt7996_rr(struct mt76_dev * mdev,u32 offset)395 static u32 mt7996_rr(struct mt76_dev *mdev, u32 offset)
396 {
397 struct mt7996_dev *dev = container_of(mdev, struct mt7996_dev, mt76);
398 u32 addr = __mt7996_reg_addr(dev, offset), val;
399
400 if (addr)
401 return dev->bus_ops->rr(mdev, addr);
402
403 spin_lock_bh(&dev->reg_lock);
404 val = dev->bus_ops->rr(mdev, __mt7996_reg_remap_addr(dev, offset));
405 spin_unlock_bh(&dev->reg_lock);
406
407 return val;
408 }
409
mt7996_wr(struct mt76_dev * mdev,u32 offset,u32 val)410 static void mt7996_wr(struct mt76_dev *mdev, u32 offset, u32 val)
411 {
412 struct mt7996_dev *dev = container_of(mdev, struct mt7996_dev, mt76);
413 u32 addr = __mt7996_reg_addr(dev, offset);
414
415 if (addr) {
416 dev->bus_ops->wr(mdev, addr, val);
417 return;
418 }
419
420 spin_lock_bh(&dev->reg_lock);
421 dev->bus_ops->wr(mdev, __mt7996_reg_remap_addr(dev, offset), val);
422 spin_unlock_bh(&dev->reg_lock);
423 }
424
mt7996_rmw(struct mt76_dev * mdev,u32 offset,u32 mask,u32 val)425 static u32 mt7996_rmw(struct mt76_dev *mdev, u32 offset, u32 mask, u32 val)
426 {
427 struct mt7996_dev *dev = container_of(mdev, struct mt7996_dev, mt76);
428 u32 addr = __mt7996_reg_addr(dev, offset);
429
430 if (addr)
431 return dev->bus_ops->rmw(mdev, addr, mask, val);
432
433 spin_lock_bh(&dev->reg_lock);
434 val = dev->bus_ops->rmw(mdev, __mt7996_reg_remap_addr(dev, offset), mask, val);
435 spin_unlock_bh(&dev->reg_lock);
436
437 return val;
438 }
439
440 #ifdef CONFIG_NET_MEDIATEK_SOC_WED
mt7996_mmio_wed_reset(struct mtk_wed_device * wed)441 static int mt7996_mmio_wed_reset(struct mtk_wed_device *wed)
442 {
443 struct mt76_dev *mdev = container_of(wed, struct mt76_dev, mmio.wed);
444 struct mt7996_dev *dev = container_of(mdev, struct mt7996_dev, mt76);
445 struct mt76_phy *mphy = &dev->mphy;
446 int ret;
447
448 ASSERT_RTNL();
449
450 if (test_and_set_bit(MT76_STATE_WED_RESET, &mphy->state))
451 return -EBUSY;
452
453 ret = mt7996_mcu_set_ser(dev, UNI_CMD_SER_TRIGGER, UNI_CMD_SER_SET_RECOVER_FROM_ETH,
454 mphy->band_idx);
455 if (ret)
456 goto out;
457
458 rtnl_unlock();
459 if (!wait_for_completion_timeout(&mdev->mmio.wed_reset, 20 * HZ)) {
460 dev_err(mdev->dev, "wed reset timeout\n");
461 ret = -ETIMEDOUT;
462 }
463 rtnl_lock();
464 out:
465 clear_bit(MT76_STATE_WED_RESET, &mphy->state);
466
467 return ret;
468 }
469 #endif
470
mt7996_mmio_wed_init(struct mt7996_dev * dev,void * pdev_ptr,bool hif2,int * irq)471 int mt7996_mmio_wed_init(struct mt7996_dev *dev, void *pdev_ptr,
472 bool hif2, int *irq)
473 {
474 #ifdef CONFIG_NET_MEDIATEK_SOC_WED
475 struct mtk_wed_device *wed = &dev->mt76.mmio.wed;
476 struct pci_dev *pci_dev = pdev_ptr;
477 u32 hif1_ofs = 0;
478
479 if (!wed_enable)
480 return 0;
481
482 dev->has_rro = true;
483
484 hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0);
485
486 if (hif2)
487 wed = &dev->mt76.mmio.wed_hif2;
488
489 wed->wlan.pci_dev = pci_dev;
490 wed->wlan.bus_type = MTK_WED_BUS_PCIE;
491
492 wed->wlan.base = devm_ioremap(dev->mt76.dev,
493 pci_resource_start(pci_dev, 0),
494 pci_resource_len(pci_dev, 0));
495 if (!wed->wlan.base)
496 return -ENOMEM;
497
498 wed->wlan.phy_base = pci_resource_start(pci_dev, 0);
499
500 if (hif2) {
501 wed->wlan.wpdma_int = wed->wlan.phy_base +
502 MT_INT_PCIE1_SOURCE_CSR_EXT;
503 wed->wlan.wpdma_mask = wed->wlan.phy_base +
504 MT_INT_PCIE1_MASK_CSR;
505 wed->wlan.wpdma_tx = wed->wlan.phy_base + hif1_ofs +
506 MT_TXQ_RING_BASE(0) +
507 MT7996_TXQ_BAND2 * MT_RING_SIZE;
508 if (dev->has_rro) {
509 wed->wlan.wpdma_txfree = wed->wlan.phy_base + hif1_ofs +
510 MT_RXQ_RING_BASE(0) +
511 MT7996_RXQ_TXFREE2 * MT_RING_SIZE;
512 wed->wlan.txfree_tbit = ffs(MT_INT_RX_TXFREE_EXT) - 1;
513 } else {
514 wed->wlan.wpdma_txfree = wed->wlan.phy_base + hif1_ofs +
515 MT_RXQ_RING_BASE(0) +
516 MT7996_RXQ_MCU_WA_TRI * MT_RING_SIZE;
517 wed->wlan.txfree_tbit = ffs(MT_INT_RX_DONE_WA_TRI) - 1;
518 }
519
520 wed->wlan.wpdma_rx_glo = wed->wlan.phy_base + hif1_ofs + MT_WFDMA0_GLO_CFG;
521 wed->wlan.wpdma_rx = wed->wlan.phy_base + hif1_ofs +
522 MT_RXQ_RING_BASE(MT7996_RXQ_BAND0) +
523 MT7996_RXQ_BAND0 * MT_RING_SIZE;
524
525 wed->wlan.id = MT7996_DEVICE_ID_2;
526 wed->wlan.tx_tbit[0] = ffs(MT_INT_TX_DONE_BAND2) - 1;
527 } else {
528 wed->wlan.hw_rro = dev->has_rro; /* default on */
529 wed->wlan.wpdma_int = wed->wlan.phy_base + MT_INT_SOURCE_CSR;
530 wed->wlan.wpdma_mask = wed->wlan.phy_base + MT_INT_MASK_CSR;
531 wed->wlan.wpdma_tx = wed->wlan.phy_base + MT_TXQ_RING_BASE(0) +
532 MT7996_TXQ_BAND0 * MT_RING_SIZE;
533
534 wed->wlan.wpdma_rx_glo = wed->wlan.phy_base + MT_WFDMA0_GLO_CFG;
535
536 wed->wlan.wpdma_rx = wed->wlan.phy_base +
537 MT_RXQ_RING_BASE(MT7996_RXQ_BAND0) +
538 MT7996_RXQ_BAND0 * MT_RING_SIZE;
539
540 wed->wlan.wpdma_rx_rro[0] = wed->wlan.phy_base +
541 MT_RXQ_RING_BASE(MT7996_RXQ_RRO_BAND0) +
542 MT7996_RXQ_RRO_BAND0 * MT_RING_SIZE;
543 wed->wlan.wpdma_rx_rro[1] = wed->wlan.phy_base + hif1_ofs +
544 MT_RXQ_RING_BASE(MT7996_RXQ_RRO_BAND2) +
545 MT7996_RXQ_RRO_BAND2 * MT_RING_SIZE;
546 wed->wlan.wpdma_rx_pg = wed->wlan.phy_base +
547 MT_RXQ_RING_BASE(MT7996_RXQ_MSDU_PG_BAND0) +
548 MT7996_RXQ_MSDU_PG_BAND0 * MT_RING_SIZE;
549
550 wed->wlan.rx_nbuf = 65536;
551 wed->wlan.rx_npkt = dev->hif2 ? 32768 : 24576;
552 wed->wlan.rx_size = SKB_WITH_OVERHEAD(MT_RX_BUF_SIZE);
553
554 wed->wlan.rx_tbit[0] = ffs(MT_INT_RX_DONE_BAND0) - 1;
555 wed->wlan.rx_tbit[1] = ffs(MT_INT_RX_DONE_BAND2) - 1;
556
557 wed->wlan.rro_rx_tbit[0] = ffs(MT_INT_RX_DONE_RRO_BAND0) - 1;
558 wed->wlan.rro_rx_tbit[1] = ffs(MT_INT_RX_DONE_RRO_BAND2) - 1;
559
560 wed->wlan.rx_pg_tbit[0] = ffs(MT_INT_RX_DONE_MSDU_PG_BAND0) - 1;
561 wed->wlan.rx_pg_tbit[1] = ffs(MT_INT_RX_DONE_MSDU_PG_BAND1) - 1;
562 wed->wlan.rx_pg_tbit[2] = ffs(MT_INT_RX_DONE_MSDU_PG_BAND2) - 1;
563
564 wed->wlan.tx_tbit[0] = ffs(MT_INT_TX_DONE_BAND0) - 1;
565 wed->wlan.tx_tbit[1] = ffs(MT_INT_TX_DONE_BAND1) - 1;
566 if (dev->has_rro) {
567 wed->wlan.wpdma_txfree = wed->wlan.phy_base + MT_RXQ_RING_BASE(0) +
568 MT7996_RXQ_TXFREE0 * MT_RING_SIZE;
569 wed->wlan.txfree_tbit = ffs(MT_INT_RX_TXFREE_MAIN) - 1;
570 } else {
571 wed->wlan.txfree_tbit = ffs(MT_INT_RX_DONE_WA_MAIN) - 1;
572 wed->wlan.wpdma_txfree = wed->wlan.phy_base + MT_RXQ_RING_BASE(0) +
573 MT7996_RXQ_MCU_WA_MAIN * MT_RING_SIZE;
574 }
575 dev->mt76.rx_token_size = MT7996_TOKEN_SIZE + wed->wlan.rx_npkt;
576 }
577
578 wed->wlan.nbuf = MT7996_HW_TOKEN_SIZE;
579 wed->wlan.token_start = MT7996_TOKEN_SIZE - wed->wlan.nbuf;
580
581 wed->wlan.amsdu_max_subframes = 8;
582 wed->wlan.amsdu_max_len = 1536;
583
584 wed->wlan.init_buf = mt7996_wed_init_buf;
585 wed->wlan.init_rx_buf = mt76_wed_init_rx_buf;
586 wed->wlan.release_rx_buf = mt76_wed_release_rx_buf;
587 wed->wlan.offload_enable = mt76_wed_offload_enable;
588 wed->wlan.offload_disable = mt76_wed_offload_disable;
589 if (!hif2) {
590 wed->wlan.reset = mt7996_mmio_wed_reset;
591 wed->wlan.reset_complete = mt76_wed_reset_complete;
592 }
593
594 if (mtk_wed_device_attach(wed))
595 return 0;
596
597 *irq = wed->irq;
598 dev->mt76.dma_dev = wed->dev;
599
600 return 1;
601 #else
602 return 0;
603 #endif
604 }
605
mt7996_mmio_init(struct mt76_dev * mdev,void __iomem * mem_base,u32 device_id)606 static int mt7996_mmio_init(struct mt76_dev *mdev,
607 void __iomem *mem_base,
608 u32 device_id)
609 {
610 struct mt76_bus_ops *bus_ops;
611 struct mt7996_dev *dev;
612
613 dev = container_of(mdev, struct mt7996_dev, mt76);
614 mt76_mmio_init(&dev->mt76, mem_base);
615 spin_lock_init(&dev->reg_lock);
616
617 switch (device_id) {
618 case MT7996_DEVICE_ID:
619 dev->reg.base = mt7996_reg_base;
620 dev->reg.offs_rev = mt7996_offs;
621 dev->reg.map = mt7996_reg_map;
622 dev->reg.map_size = ARRAY_SIZE(mt7996_reg_map);
623 break;
624 case MT7992_DEVICE_ID:
625 dev->reg.base = mt7996_reg_base;
626 dev->reg.offs_rev = mt7992_offs;
627 dev->reg.map = mt7996_reg_map;
628 dev->reg.map_size = ARRAY_SIZE(mt7996_reg_map);
629 break;
630 case MT7990_DEVICE_ID:
631 dev->reg.base = mt7996_reg_base;
632 dev->reg.offs_rev = mt7990_offs;
633 dev->reg.map = mt7990_reg_map;
634 dev->reg.map_size = ARRAY_SIZE(mt7990_reg_map);
635 break;
636 default:
637 return -EINVAL;
638 }
639
640 dev->bus_ops = dev->mt76.bus;
641 bus_ops = devm_kmemdup(dev->mt76.dev, dev->bus_ops, sizeof(*bus_ops),
642 GFP_KERNEL);
643 if (!bus_ops)
644 return -ENOMEM;
645
646 bus_ops->rr = mt7996_rr;
647 bus_ops->wr = mt7996_wr;
648 bus_ops->rmw = mt7996_rmw;
649 dev->mt76.bus = bus_ops;
650
651 mdev->rev = (device_id << 16) | (mt76_rr(dev, MT_HW_REV) & 0xff);
652
653 dev_dbg(mdev->dev, "ASIC revision: %04x\n", mdev->rev);
654
655 return 0;
656 }
657
mt7996_dual_hif_set_irq_mask(struct mt7996_dev * dev,bool write_reg,u32 clear,u32 set)658 void mt7996_dual_hif_set_irq_mask(struct mt7996_dev *dev, bool write_reg,
659 u32 clear, u32 set)
660 {
661 struct mt76_dev *mdev = &dev->mt76;
662 unsigned long flags;
663
664 spin_lock_irqsave(&mdev->mmio.irq_lock, flags);
665
666 mdev->mmio.irqmask &= ~clear;
667 mdev->mmio.irqmask |= set;
668
669 if (write_reg) {
670 if (mtk_wed_device_active(&mdev->mmio.wed)) {
671 mtk_wed_device_irq_set_mask(&mdev->mmio.wed,
672 mdev->mmio.irqmask);
673 if (mtk_wed_device_active(&mdev->mmio.wed_hif2)) {
674 mtk_wed_device_irq_set_mask(&mdev->mmio.wed_hif2,
675 mdev->mmio.irqmask);
676 }
677 } else {
678 mt76_wr(dev, MT_INT_MASK_CSR, mdev->mmio.irqmask);
679 mt76_wr(dev, MT_INT1_MASK_CSR, mdev->mmio.irqmask);
680 }
681 }
682
683 spin_unlock_irqrestore(&mdev->mmio.irq_lock, flags);
684 }
685
mt7996_rx_poll_complete(struct mt76_dev * mdev,enum mt76_rxq_id q)686 static void mt7996_rx_poll_complete(struct mt76_dev *mdev,
687 enum mt76_rxq_id q)
688 {
689 struct mt7996_dev *dev = container_of(mdev, struct mt7996_dev, mt76);
690
691 mt7996_irq_enable(dev, MT_INT_RX(q));
692 }
693
694 /* TODO: support 2/4/6/8 MSI-X vectors */
mt7996_irq_tasklet(struct tasklet_struct * t)695 static void mt7996_irq_tasklet(struct tasklet_struct *t)
696 {
697 struct mt7996_dev *dev = from_tasklet(dev, t, mt76.irq_tasklet);
698 struct mtk_wed_device *wed = &dev->mt76.mmio.wed;
699 struct mtk_wed_device *wed_hif2 = &dev->mt76.mmio.wed_hif2;
700 u32 i, intr, mask, intr1 = 0;
701
702 if (dev->hif2 && mtk_wed_device_active(wed_hif2)) {
703 mtk_wed_device_irq_set_mask(wed_hif2, 0);
704 intr1 = mtk_wed_device_irq_get(wed_hif2,
705 dev->mt76.mmio.irqmask);
706 if (intr1 & MT_INT_RX_TXFREE_EXT)
707 napi_schedule(&dev->mt76.napi[MT_RXQ_TXFREE_BAND2]);
708 }
709
710 if (mtk_wed_device_active(wed)) {
711 mtk_wed_device_irq_set_mask(wed, 0);
712 intr = mtk_wed_device_irq_get(wed, dev->mt76.mmio.irqmask);
713 intr |= (intr1 & ~MT_INT_RX_TXFREE_EXT);
714 } else {
715 mt76_wr(dev, MT_INT_MASK_CSR, 0);
716 if (dev->hif2)
717 mt76_wr(dev, MT_INT1_MASK_CSR, 0);
718
719 intr = mt76_rr(dev, MT_INT_SOURCE_CSR);
720 intr &= dev->mt76.mmio.irqmask;
721 mt76_wr(dev, MT_INT_SOURCE_CSR, intr);
722 if (dev->hif2) {
723 intr1 = mt76_rr(dev, MT_INT1_SOURCE_CSR);
724 intr1 &= dev->mt76.mmio.irqmask;
725 mt76_wr(dev, MT_INT1_SOURCE_CSR, intr1);
726 intr |= intr1;
727 }
728 }
729
730 trace_dev_irq(&dev->mt76, intr, dev->mt76.mmio.irqmask);
731
732 mask = intr & MT_INT_RX_DONE_ALL;
733 if (intr & MT_INT_TX_DONE_MCU)
734 mask |= MT_INT_TX_DONE_MCU;
735 mt7996_irq_disable(dev, mask);
736
737 if (intr & MT_INT_TX_DONE_MCU)
738 napi_schedule(&dev->mt76.tx_napi);
739
740 for (i = 0; i < __MT_RXQ_MAX; i++) {
741 if ((intr & MT_INT_RX(i)))
742 napi_schedule(&dev->mt76.napi[i]);
743 }
744
745 if (intr & MT_INT_MCU_CMD) {
746 u32 val = mt76_rr(dev, MT_MCU_CMD);
747
748 mt76_wr(dev, MT_MCU_CMD, val);
749 if (val & (MT_MCU_CMD_ERROR_MASK | MT_MCU_CMD_WDT_MASK)) {
750 dev->recovery.state = val;
751 mt7996_reset(dev);
752 }
753 }
754 }
755
mt7996_irq_handler(int irq,void * dev_instance)756 irqreturn_t mt7996_irq_handler(int irq, void *dev_instance)
757 {
758 struct mt7996_dev *dev = dev_instance;
759
760 if (mtk_wed_device_active(&dev->mt76.mmio.wed))
761 mtk_wed_device_irq_set_mask(&dev->mt76.mmio.wed, 0);
762 else
763 mt76_wr(dev, MT_INT_MASK_CSR, 0);
764
765 if (dev->hif2) {
766 if (mtk_wed_device_active(&dev->mt76.mmio.wed_hif2))
767 mtk_wed_device_irq_set_mask(&dev->mt76.mmio.wed_hif2, 0);
768 else
769 mt76_wr(dev, MT_INT1_MASK_CSR, 0);
770 }
771
772 if (!test_bit(MT76_STATE_INITIALIZED, &dev->mphy.state))
773 return IRQ_NONE;
774
775 tasklet_schedule(&dev->mt76.irq_tasklet);
776
777 return IRQ_HANDLED;
778 }
779
mt7996_mmio_probe(struct device * pdev,void __iomem * mem_base,u32 device_id)780 struct mt7996_dev *mt7996_mmio_probe(struct device *pdev,
781 void __iomem *mem_base, u32 device_id)
782 {
783 static const struct mt76_driver_ops drv_ops = {
784 /* txwi_size = txd size + txp size */
785 .txwi_size = MT_TXD_SIZE + sizeof(struct mt76_connac_fw_txp),
786 .link_data_size = sizeof(struct mt7996_vif_link),
787 .drv_flags = MT_DRV_TXWI_NO_FREE |
788 MT_DRV_AMSDU_OFFLOAD |
789 MT_DRV_HW_MGMT_TXQ,
790 .survey_flags = SURVEY_INFO_TIME_TX |
791 SURVEY_INFO_TIME_RX |
792 SURVEY_INFO_TIME_BSS_RX,
793 .token_size = MT7996_TOKEN_SIZE,
794 .tx_prepare_skb = mt7996_tx_prepare_skb,
795 .tx_complete_skb = mt76_connac_tx_complete_skb,
796 .rx_skb = mt7996_queue_rx_skb,
797 .rx_check = mt7996_rx_check,
798 .rx_poll_complete = mt7996_rx_poll_complete,
799 .update_survey = mt7996_update_channel,
800 .set_channel = mt7996_set_channel,
801 .vif_link_add = mt7996_vif_link_add,
802 .vif_link_remove = mt7996_vif_link_remove,
803 };
804 struct mt7996_dev *dev;
805 struct mt76_dev *mdev;
806 int ret;
807
808 mdev = mt76_alloc_device(pdev, sizeof(*dev), &mt7996_ops, &drv_ops);
809 if (!mdev)
810 return ERR_PTR(-ENOMEM);
811
812 dev = container_of(mdev, struct mt7996_dev, mt76);
813
814 ret = mt7996_mmio_init(mdev, mem_base, device_id);
815 if (ret)
816 goto error;
817
818 tasklet_setup(&mdev->irq_tasklet, mt7996_irq_tasklet);
819
820 mt76_wr(dev, MT_INT_MASK_CSR, 0);
821
822 return dev;
823
824 error:
825 mt76_free_device(&dev->mt76);
826
827 return ERR_PTR(ret);
828 }
829
mt7996_init(void)830 static int __init mt7996_init(void)
831 {
832 int ret;
833
834 ret = pci_register_driver(&mt7996_hif_driver);
835 if (ret)
836 return ret;
837
838 ret = pci_register_driver(&mt7996_pci_driver);
839 if (ret)
840 pci_unregister_driver(&mt7996_hif_driver);
841
842 return ret;
843 }
844
mt7996_exit(void)845 static void __exit mt7996_exit(void)
846 {
847 pci_unregister_driver(&mt7996_pci_driver);
848 pci_unregister_driver(&mt7996_hif_driver);
849 }
850
851 module_init(mt7996_init);
852 module_exit(mt7996_exit);
853 MODULE_DESCRIPTION("MediaTek MT7996 MMIO helpers");
854 MODULE_LICENSE("Dual BSD/GPL");
855