1 // SPDX-License-Identifier: ISC
2 /*
3 * Copyright (C) 2022 MediaTek Inc.
4 */
5
6 #include <linux/etherdevice.h>
7 #include <linux/of.h>
8 #include <linux/hwmon.h>
9 #include <linux/hwmon-sysfs.h>
10 #include <linux/thermal.h>
11 #include "mt7996.h"
12 #include "mac.h"
13 #include "mcu.h"
14 #include "coredump.h"
15 #include "eeprom.h"
16 #if defined(__FreeBSD__)
17 #include <linux/delay.h>
18 #endif
19
20 static const struct ieee80211_iface_limit if_limits_global = {
21 .max = MT7996_MAX_INTERFACES * MT7996_MAX_RADIOS,
22 .types = BIT(NL80211_IFTYPE_STATION)
23 | BIT(NL80211_IFTYPE_ADHOC)
24 | BIT(NL80211_IFTYPE_AP)
25 #ifdef CONFIG_MAC80211_MESH
26 | BIT(NL80211_IFTYPE_MESH_POINT)
27 #endif
28 };
29
30 static const struct ieee80211_iface_combination if_comb_global = {
31 .limits = &if_limits_global,
32 .n_limits = 1,
33 .max_interfaces = MT7996_MAX_INTERFACES * MT7996_MAX_RADIOS,
34 .num_different_channels = MT7996_MAX_RADIOS,
35 .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) |
36 BIT(NL80211_CHAN_WIDTH_20) |
37 BIT(NL80211_CHAN_WIDTH_40) |
38 BIT(NL80211_CHAN_WIDTH_80) |
39 BIT(NL80211_CHAN_WIDTH_160),
40 };
41
42 static const struct ieee80211_iface_limit if_limits[] = {
43 {
44 .max = 16,
45 .types = BIT(NL80211_IFTYPE_AP)
46 #ifdef CONFIG_MAC80211_MESH
47 | BIT(NL80211_IFTYPE_MESH_POINT)
48 #endif
49 }, {
50 .max = MT7996_MAX_INTERFACES,
51 .types = BIT(NL80211_IFTYPE_STATION)
52 }
53 };
54
55 static const struct ieee80211_iface_combination if_comb = {
56 .limits = if_limits,
57 .n_limits = ARRAY_SIZE(if_limits),
58 .max_interfaces = MT7996_MAX_INTERFACES,
59 .num_different_channels = 1,
60 .beacon_int_infra_match = true,
61 .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) |
62 BIT(NL80211_CHAN_WIDTH_20) |
63 BIT(NL80211_CHAN_WIDTH_40) |
64 BIT(NL80211_CHAN_WIDTH_80) |
65 BIT(NL80211_CHAN_WIDTH_160),
66 .beacon_int_min_gcd = 100,
67 };
68
69 #if defined(CONFIG_HWMON)
mt7996_thermal_temp_show(struct device * dev,struct device_attribute * attr,char * buf)70 static ssize_t mt7996_thermal_temp_show(struct device *dev,
71 struct device_attribute *attr,
72 char *buf)
73 {
74 struct mt7996_phy *phy = dev_get_drvdata(dev);
75 int i = to_sensor_dev_attr(attr)->index;
76 int temperature;
77
78 switch (i) {
79 case 0:
80 temperature = mt7996_mcu_get_temperature(phy);
81 if (temperature < 0)
82 return temperature;
83 /* display in millidegree celcius */
84 return sprintf(buf, "%u\n", temperature * 1000);
85 case 1:
86 case 2:
87 return sprintf(buf, "%u\n",
88 phy->throttle_temp[i - 1] * 1000);
89 case 3:
90 return sprintf(buf, "%hhu\n", phy->throttle_state);
91 default:
92 return -EINVAL;
93 }
94 }
95
mt7996_thermal_temp_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)96 static ssize_t mt7996_thermal_temp_store(struct device *dev,
97 struct device_attribute *attr,
98 const char *buf, size_t count)
99 {
100 struct mt7996_phy *phy = dev_get_drvdata(dev);
101 int ret, i = to_sensor_dev_attr(attr)->index;
102 long val;
103
104 ret = kstrtol(buf, 10, &val);
105 if (ret < 0)
106 return ret;
107
108 mutex_lock(&phy->dev->mt76.mutex);
109 val = DIV_ROUND_CLOSEST(clamp_val(val, 40 * 1000, 130 * 1000), 1000);
110
111 /* add a safety margin ~10 */
112 if ((i - 1 == MT7996_CRIT_TEMP_IDX &&
113 val > phy->throttle_temp[MT7996_MAX_TEMP_IDX] - 10) ||
114 (i - 1 == MT7996_MAX_TEMP_IDX &&
115 val - 10 < phy->throttle_temp[MT7996_CRIT_TEMP_IDX])) {
116 dev_err(phy->dev->mt76.dev,
117 "temp1_max shall be 10 degrees higher than temp1_crit.");
118 mutex_unlock(&phy->dev->mt76.mutex);
119 return -EINVAL;
120 }
121
122 phy->throttle_temp[i - 1] = val;
123 mutex_unlock(&phy->dev->mt76.mutex);
124
125 ret = mt7996_mcu_set_thermal_protect(phy, true);
126 if (ret)
127 return ret;
128
129 return count;
130 }
131
132 static SENSOR_DEVICE_ATTR_RO(temp1_input, mt7996_thermal_temp, 0);
133 static SENSOR_DEVICE_ATTR_RW(temp1_crit, mt7996_thermal_temp, 1);
134 static SENSOR_DEVICE_ATTR_RW(temp1_max, mt7996_thermal_temp, 2);
135 static SENSOR_DEVICE_ATTR_RO(throttle1, mt7996_thermal_temp, 3);
136
137 static struct attribute *mt7996_hwmon_attrs[] = {
138 &sensor_dev_attr_temp1_input.dev_attr.attr,
139 &sensor_dev_attr_temp1_crit.dev_attr.attr,
140 &sensor_dev_attr_temp1_max.dev_attr.attr,
141 &sensor_dev_attr_throttle1.dev_attr.attr,
142 NULL,
143 };
144 ATTRIBUTE_GROUPS(mt7996_hwmon);
145
146 static int
mt7996_thermal_get_max_throttle_state(struct thermal_cooling_device * cdev,unsigned long * state)147 mt7996_thermal_get_max_throttle_state(struct thermal_cooling_device *cdev,
148 unsigned long *state)
149 {
150 *state = MT7996_CDEV_THROTTLE_MAX;
151
152 return 0;
153 }
154
155 static int
mt7996_thermal_get_cur_throttle_state(struct thermal_cooling_device * cdev,unsigned long * state)156 mt7996_thermal_get_cur_throttle_state(struct thermal_cooling_device *cdev,
157 unsigned long *state)
158 {
159 struct mt7996_phy *phy = cdev->devdata;
160
161 *state = phy->cdev_state;
162
163 return 0;
164 }
165
166 static int
mt7996_thermal_set_cur_throttle_state(struct thermal_cooling_device * cdev,unsigned long state)167 mt7996_thermal_set_cur_throttle_state(struct thermal_cooling_device *cdev,
168 unsigned long state)
169 {
170 struct mt7996_phy *phy = cdev->devdata;
171 u8 throttling = MT7996_THERMAL_THROTTLE_MAX - state;
172 int ret;
173
174 if (state > MT7996_CDEV_THROTTLE_MAX) {
175 dev_err(phy->dev->mt76.dev,
176 "please specify a valid throttling state\n");
177 return -EINVAL;
178 }
179
180 if (state == phy->cdev_state)
181 return 0;
182
183 /* cooling_device convention: 0 = no cooling, more = more cooling
184 * mcu convention: 1 = max cooling, more = less cooling
185 */
186 ret = mt7996_mcu_set_thermal_throttling(phy, throttling);
187 if (ret)
188 return ret;
189
190 phy->cdev_state = state;
191
192 return 0;
193 }
194
195 static const struct thermal_cooling_device_ops mt7996_thermal_ops = {
196 .get_max_state = mt7996_thermal_get_max_throttle_state,
197 .get_cur_state = mt7996_thermal_get_cur_throttle_state,
198 .set_cur_state = mt7996_thermal_set_cur_throttle_state,
199 };
200
mt7996_unregister_thermal(struct mt7996_phy * phy)201 static void mt7996_unregister_thermal(struct mt7996_phy *phy)
202 {
203 struct wiphy *wiphy = phy->mt76->hw->wiphy;
204 char name[sizeof("cooling_deviceXXX")];
205
206 if (!phy->cdev)
207 return;
208
209 snprintf(name, sizeof(name), "cooling_device%d", phy->mt76->band_idx);
210 sysfs_remove_link(&wiphy->dev.kobj, name);
211 thermal_cooling_device_unregister(phy->cdev);
212 }
213
mt7996_thermal_init(struct mt7996_phy * phy)214 static int mt7996_thermal_init(struct mt7996_phy *phy)
215 {
216 struct wiphy *wiphy = phy->mt76->hw->wiphy;
217 char cname[sizeof("cooling_deviceXXX")];
218 struct thermal_cooling_device *cdev;
219 struct device *hwmon;
220 const char *name;
221
222 name = devm_kasprintf(&wiphy->dev, GFP_KERNEL, "mt7996_%s.%d",
223 wiphy_name(wiphy), phy->mt76->band_idx);
224 snprintf(cname, sizeof(cname), "cooling_device%d", phy->mt76->band_idx);
225
226 cdev = thermal_cooling_device_register(name, phy, &mt7996_thermal_ops);
227 if (!IS_ERR(cdev)) {
228 if (sysfs_create_link(&wiphy->dev.kobj, &cdev->device.kobj,
229 cname) < 0)
230 thermal_cooling_device_unregister(cdev);
231 else
232 phy->cdev = cdev;
233 }
234
235 /* initialize critical/maximum high temperature */
236 phy->throttle_temp[MT7996_CRIT_TEMP_IDX] = MT7996_CRIT_TEMP;
237 phy->throttle_temp[MT7996_MAX_TEMP_IDX] = MT7996_MAX_TEMP;
238
239 if (!IS_REACHABLE(CONFIG_HWMON))
240 return 0;
241
242 hwmon = devm_hwmon_device_register_with_groups(&wiphy->dev, name, phy,
243 mt7996_hwmon_groups);
244
245 if (IS_ERR(hwmon))
246 return PTR_ERR(hwmon);
247
248 return 0;
249 }
250 #endif
251
mt7996_led_set_config(struct led_classdev * led_cdev,u8 delay_on,u8 delay_off)252 static void mt7996_led_set_config(struct led_classdev *led_cdev,
253 u8 delay_on, u8 delay_off)
254 {
255 struct mt7996_dev *dev;
256 struct mt76_phy *mphy;
257 u32 val;
258
259 mphy = container_of(led_cdev, struct mt76_phy, leds.cdev);
260 dev = container_of(mphy->dev, struct mt7996_dev, mt76);
261
262 /* select TX blink mode, 2: only data frames */
263 mt76_rmw_field(dev, MT_TMAC_TCR0(mphy->band_idx), MT_TMAC_TCR0_TX_BLINK, 2);
264
265 /* enable LED */
266 mt76_wr(dev, MT_LED_EN(mphy->band_idx), 1);
267
268 /* set LED Tx blink on/off time */
269 val = FIELD_PREP(MT_LED_TX_BLINK_ON_MASK, delay_on) |
270 FIELD_PREP(MT_LED_TX_BLINK_OFF_MASK, delay_off);
271 mt76_wr(dev, MT_LED_TX_BLINK(mphy->band_idx), val);
272
273 /* turn LED off */
274 if (delay_off == 0xff && delay_on == 0x0) {
275 val = MT_LED_CTRL_POLARITY | MT_LED_CTRL_KICK;
276 } else {
277 /* control LED */
278 val = MT_LED_CTRL_BLINK_MODE | MT_LED_CTRL_KICK;
279 if (mphy->band_idx == MT_BAND1)
280 val |= MT_LED_CTRL_BLINK_BAND_SEL;
281 }
282
283 if (mphy->leds.al)
284 val |= MT_LED_CTRL_POLARITY;
285
286 mt76_wr(dev, MT_LED_CTRL(mphy->band_idx), val);
287 mt76_clear(dev, MT_LED_CTRL(mphy->band_idx), MT_LED_CTRL_KICK);
288 }
289
mt7996_led_set_blink(struct led_classdev * led_cdev,unsigned long * delay_on,unsigned long * delay_off)290 static int mt7996_led_set_blink(struct led_classdev *led_cdev,
291 unsigned long *delay_on,
292 unsigned long *delay_off)
293 {
294 u16 delta_on = 0, delta_off = 0;
295
296 #define HW_TICK 10
297 #define TO_HW_TICK(_t) (((_t) > HW_TICK) ? ((_t) / HW_TICK) : HW_TICK)
298
299 if (*delay_on)
300 delta_on = TO_HW_TICK(*delay_on);
301 if (*delay_off)
302 delta_off = TO_HW_TICK(*delay_off);
303
304 mt7996_led_set_config(led_cdev, delta_on, delta_off);
305
306 return 0;
307 }
308
mt7996_led_set_brightness(struct led_classdev * led_cdev,enum led_brightness brightness)309 static void mt7996_led_set_brightness(struct led_classdev *led_cdev,
310 enum led_brightness brightness)
311 {
312 if (!brightness)
313 mt7996_led_set_config(led_cdev, 0, 0xff);
314 else
315 mt7996_led_set_config(led_cdev, 0xff, 0);
316 }
317
__mt7996_init_txpower(struct mt7996_phy * phy,struct ieee80211_supported_band * sband)318 static void __mt7996_init_txpower(struct mt7996_phy *phy,
319 struct ieee80211_supported_band *sband)
320 {
321 struct mt7996_dev *dev = phy->dev;
322 int i, nss = hweight16(phy->mt76->chainmask);
323 int nss_delta = mt76_tx_power_nss_delta(nss);
324 int pwr_delta = mt7996_eeprom_get_power_delta(dev, sband->band);
325 struct mt76_power_limits limits;
326
327 for (i = 0; i < sband->n_channels; i++) {
328 struct ieee80211_channel *chan = &sband->channels[i];
329 int target_power = mt7996_eeprom_get_target_power(dev, chan);
330
331 target_power += pwr_delta;
332 target_power = mt76_get_rate_power_limits(phy->mt76, chan,
333 &limits,
334 target_power);
335 target_power += nss_delta;
336 target_power = DIV_ROUND_UP(target_power, 2);
337 chan->max_power = min_t(int, chan->max_reg_power,
338 target_power);
339 chan->orig_mpwr = target_power;
340 }
341 }
342
mt7996_init_txpower(struct mt7996_phy * phy)343 void mt7996_init_txpower(struct mt7996_phy *phy)
344 {
345 if (!phy)
346 return;
347
348 if (phy->mt76->cap.has_2ghz)
349 __mt7996_init_txpower(phy, &phy->mt76->sband_2g.sband);
350 if (phy->mt76->cap.has_5ghz)
351 __mt7996_init_txpower(phy, &phy->mt76->sband_5g.sband);
352 if (phy->mt76->cap.has_6ghz)
353 __mt7996_init_txpower(phy, &phy->mt76->sband_6g.sband);
354 }
355
356 static void
mt7996_regd_notifier(struct wiphy * wiphy,struct regulatory_request * request)357 mt7996_regd_notifier(struct wiphy *wiphy,
358 struct regulatory_request *request)
359 {
360 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
361 struct mt7996_dev *dev = mt7996_hw_dev(hw);
362 struct mt7996_phy *phy;
363
364 memcpy(dev->mt76.alpha2, request->alpha2, sizeof(dev->mt76.alpha2));
365 dev->mt76.region = request->dfs_region;
366
367 mt7996_for_each_phy(dev, phy) {
368 if (dev->mt76.region == NL80211_DFS_UNSET)
369 mt7996_mcu_rdd_background_enable(phy, NULL);
370
371 mt7996_init_txpower(phy);
372 phy->mt76->dfs_state = MT_DFS_STATE_UNKNOWN;
373 mt7996_dfs_init_radar_detector(phy);
374 }
375 }
376
377 static void
mt7996_init_wiphy_band(struct ieee80211_hw * hw,struct mt7996_phy * phy)378 mt7996_init_wiphy_band(struct ieee80211_hw *hw, struct mt7996_phy *phy)
379 {
380 struct mt7996_dev *dev = phy->dev;
381 struct wiphy *wiphy = hw->wiphy;
382 int n_radios = hw->wiphy->n_radio;
383 struct wiphy_radio_freq_range *freq = &dev->radio_freqs[n_radios];
384 struct wiphy_radio *radio = &dev->radios[n_radios];
385
386 phy->slottime = 9;
387 phy->beacon_rate = -1;
388
389 if (phy->mt76->cap.has_2ghz) {
390 phy->mt76->sband_2g.sband.ht_cap.cap |=
391 IEEE80211_HT_CAP_LDPC_CODING |
392 IEEE80211_HT_CAP_MAX_AMSDU;
393 phy->mt76->sband_2g.sband.ht_cap.ampdu_density =
394 IEEE80211_HT_MPDU_DENSITY_2;
395 freq->start_freq = 2400000;
396 freq->end_freq = 2500000;
397 } else if (phy->mt76->cap.has_5ghz) {
398 phy->mt76->sband_5g.sband.ht_cap.cap |=
399 IEEE80211_HT_CAP_LDPC_CODING |
400 IEEE80211_HT_CAP_MAX_AMSDU;
401
402 phy->mt76->sband_5g.sband.vht_cap.cap |=
403 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 |
404 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK |
405 IEEE80211_VHT_CAP_SHORT_GI_160 |
406 IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ;
407 phy->mt76->sband_5g.sband.ht_cap.ampdu_density =
408 IEEE80211_HT_MPDU_DENSITY_1;
409
410 ieee80211_hw_set(hw, SUPPORTS_VHT_EXT_NSS_BW);
411 freq->start_freq = 5000000;
412 freq->end_freq = 5900000;
413 } else if (phy->mt76->cap.has_6ghz) {
414 freq->start_freq = 5900000;
415 freq->end_freq = 7200000;
416 } else {
417 return;
418 }
419
420 dev->radio_phy[n_radios] = phy;
421 radio->freq_range = freq;
422 radio->n_freq_range = 1;
423 radio->iface_combinations = &if_comb;
424 radio->n_iface_combinations = 1;
425 hw->wiphy->n_radio++;
426
427 wiphy->available_antennas_rx |= phy->mt76->chainmask;
428 wiphy->available_antennas_tx |= phy->mt76->chainmask;
429
430 mt76_set_stream_caps(phy->mt76, true);
431 mt7996_set_stream_vht_txbf_caps(phy);
432 mt7996_set_stream_he_eht_caps(phy);
433 mt7996_init_txpower(phy);
434 }
435
436 static void
mt7996_init_wiphy(struct ieee80211_hw * hw,struct mtk_wed_device * wed)437 mt7996_init_wiphy(struct ieee80211_hw *hw, struct mtk_wed_device *wed)
438 {
439 struct mt7996_dev *dev = mt7996_hw_dev(hw);
440 #if defined(CONFIG_OF)
441 struct mt76_dev *mdev = &dev->mt76;
442 #endif
443 struct wiphy *wiphy = hw->wiphy;
444 u16 max_subframes = dev->has_eht ? IEEE80211_MAX_AMPDU_BUF_EHT :
445 IEEE80211_MAX_AMPDU_BUF_HE;
446
447 hw->queues = 4;
448 hw->max_rx_aggregation_subframes = max_subframes;
449 hw->max_tx_aggregation_subframes = max_subframes;
450 hw->netdev_features = NETIF_F_RXCSUM;
451 if (mtk_wed_device_active(wed))
452 hw->netdev_features |= NETIF_F_HW_TC;
453
454 hw->radiotap_timestamp.units_pos =
455 IEEE80211_RADIOTAP_TIMESTAMP_UNIT_US;
456
457 hw->sta_data_size = sizeof(struct mt7996_sta);
458 hw->vif_data_size = sizeof(struct mt7996_vif);
459 hw->chanctx_data_size = sizeof(struct mt76_chanctx);
460
461 wiphy->iface_combinations = &if_comb_global;
462 wiphy->n_iface_combinations = 1;
463
464 wiphy->radio = dev->radios;
465
466 wiphy->reg_notifier = mt7996_regd_notifier;
467 wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH;
468 wiphy->mbssid_max_interfaces = 16;
469
470 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BSS_COLOR);
471 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_VHT_IBSS);
472 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_LEGACY);
473 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_HT);
474 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_VHT);
475 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_HE);
476 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_UNSOL_BCAST_PROBE_RESP);
477 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_FILS_DISCOVERY);
478 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_ACK_SIGNAL_SUPPORT);
479 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0);
480 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_MU_MIMO_AIR_SNIFFER);
481
482 if (mt7996_has_background_radar(dev) &&
483 #if defined(CONFIG_OF)
484 (!mdev->dev->of_node ||
485 !of_property_read_bool(mdev->dev->of_node,
486 "mediatek,disable-radar-background")))
487 #else
488 1)
489 #endif
490 wiphy_ext_feature_set(wiphy,
491 NL80211_EXT_FEATURE_RADAR_BACKGROUND);
492
493 ieee80211_hw_set(hw, HAS_RATE_CONTROL);
494 ieee80211_hw_set(hw, SUPPORTS_TX_ENCAP_OFFLOAD);
495 ieee80211_hw_set(hw, SUPPORTS_RX_DECAP_OFFLOAD);
496 ieee80211_hw_set(hw, NO_VIRTUAL_MONITOR);
497 ieee80211_hw_set(hw, SUPPORTS_MULTI_BSSID);
498
499 hw->max_tx_fragments = 4;
500
501 /* init led callbacks */
502 if (IS_ENABLED(CONFIG_MT76_LEDS)) {
503 dev->mphy.leds.cdev.brightness_set = mt7996_led_set_brightness;
504 dev->mphy.leds.cdev.blink_set = mt7996_led_set_blink;
505 }
506
507 wiphy->max_scan_ssids = 4;
508 wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN;
509
510 mt7996_init_wiphy_band(hw, &dev->phy);
511 }
512
513 static void
mt7996_mac_init_band(struct mt7996_dev * dev,u8 band)514 mt7996_mac_init_band(struct mt7996_dev *dev, u8 band)
515 {
516 u32 mask, set;
517
518 /* clear estimated value of EIFS for Rx duration & OBSS time */
519 mt76_wr(dev, MT_WF_RMAC_RSVD0(band), MT_WF_RMAC_RSVD0_EIFS_CLR);
520
521 /* clear backoff time for Rx duration */
522 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME1(band),
523 MT_WF_RMAC_MIB_NONQOSD_BACKOFF);
524 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME3(band),
525 MT_WF_RMAC_MIB_QOS01_BACKOFF);
526 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME4(band),
527 MT_WF_RMAC_MIB_QOS23_BACKOFF);
528
529 /* clear backoff time for Tx duration */
530 mt76_clear(dev, MT_WTBLOFF_ACR(band),
531 MT_WTBLOFF_ADM_BACKOFFTIME);
532
533 /* clear backoff time and set software compensation for OBSS time */
534 mask = MT_WF_RMAC_MIB_OBSS_BACKOFF | MT_WF_RMAC_MIB_ED_OFFSET;
535 set = FIELD_PREP(MT_WF_RMAC_MIB_OBSS_BACKOFF, 0) |
536 FIELD_PREP(MT_WF_RMAC_MIB_ED_OFFSET, 4);
537 mt76_rmw(dev, MT_WF_RMAC_MIB_AIRTIME0(band), mask, set);
538
539 /* filter out non-resp frames and get instanstaeous signal reporting */
540 mask = MT_WTBLOFF_RSCR_RCPI_MODE | MT_WTBLOFF_RSCR_RCPI_PARAM;
541 set = FIELD_PREP(MT_WTBLOFF_RSCR_RCPI_MODE, 0) |
542 FIELD_PREP(MT_WTBLOFF_RSCR_RCPI_PARAM, 0x3);
543 mt76_rmw(dev, MT_WTBLOFF_RSCR(band), mask, set);
544
545 /* MT_TXD5_TX_STATUS_HOST (MPDU format) has higher priority than
546 * MT_AGG_ACR_PPDU_TXS2H (PPDU format) even though ACR bit is set.
547 */
548 mt76_set(dev, MT_AGG_ACR4(band), MT_AGG_ACR_PPDU_TXS2H);
549 }
550
mt7996_mac_init_basic_rates(struct mt7996_dev * dev)551 static void mt7996_mac_init_basic_rates(struct mt7996_dev *dev)
552 {
553 int i;
554
555 for (i = 0; i < ARRAY_SIZE(mt76_rates); i++) {
556 u16 rate = mt76_rates[i].hw_value;
557 /* odd index for driver, even index for firmware */
558 u16 idx = MT7996_BASIC_RATES_TBL + 2 * i;
559
560 rate = FIELD_PREP(MT_TX_RATE_MODE, rate >> 8) |
561 FIELD_PREP(MT_TX_RATE_IDX, rate & GENMASK(7, 0));
562 mt7996_mcu_set_fixed_rate_table(&dev->phy, idx, rate, false);
563 }
564 }
565
mt7996_mac_init(struct mt7996_dev * dev)566 void mt7996_mac_init(struct mt7996_dev *dev)
567 {
568 #define HIF_TXD_V2_1 0x21
569 int i;
570
571 mt76_clear(dev, MT_MDP_DCR2, MT_MDP_DCR2_RX_TRANS_SHORT);
572
573 for (i = 0; i < mt7996_wtbl_size(dev); i++)
574 mt7996_mac_wtbl_update(dev, i,
575 MT_WTBL_UPDATE_ADM_COUNT_CLEAR);
576
577 if (IS_ENABLED(CONFIG_MT76_LEDS)) {
578 i = dev->mphy.leds.pin ? MT_LED_GPIO_MUX3 : MT_LED_GPIO_MUX2;
579 mt76_rmw_field(dev, i, MT_LED_GPIO_SEL_MASK, 4);
580 }
581
582 /* rro module init */
583 if (is_mt7996(&dev->mt76))
584 mt7996_mcu_set_rro(dev, UNI_RRO_SET_PLATFORM_TYPE, 2);
585 else
586 mt7996_mcu_set_rro(dev, UNI_RRO_SET_PLATFORM_TYPE,
587 dev->hif2 ? 7 : 0);
588
589 if (dev->has_rro) {
590 u16 timeout;
591
592 timeout = mt76_rr(dev, MT_HW_REV) == MT_HW_REV1 ? 512 : 128;
593 mt7996_mcu_set_rro(dev, UNI_RRO_SET_FLUSH_TIMEOUT, timeout);
594 mt7996_mcu_set_rro(dev, UNI_RRO_SET_BYPASS_MODE, 1);
595 mt7996_mcu_set_rro(dev, UNI_RRO_SET_TXFREE_PATH, 0);
596 } else {
597 mt7996_mcu_set_rro(dev, UNI_RRO_SET_BYPASS_MODE, 3);
598 mt7996_mcu_set_rro(dev, UNI_RRO_SET_TXFREE_PATH, 1);
599 }
600
601 mt7996_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(SET),
602 MCU_WA_PARAM_HW_PATH_HIF_VER,
603 HIF_TXD_V2_1, 0);
604
605 for (i = MT_BAND0; i <= MT_BAND2; i++)
606 mt7996_mac_init_band(dev, i);
607
608 mt7996_mac_init_basic_rates(dev);
609 }
610
mt7996_txbf_init(struct mt7996_dev * dev)611 int mt7996_txbf_init(struct mt7996_dev *dev)
612 {
613 int ret;
614
615 if (mt7996_band_valid(dev, MT_BAND1) ||
616 mt7996_band_valid(dev, MT_BAND2)) {
617 ret = mt7996_mcu_set_txbf(dev, BF_MOD_EN_CTRL);
618 if (ret)
619 return ret;
620 }
621
622 /* trigger sounding packets */
623 ret = mt7996_mcu_set_txbf(dev, BF_SOUNDING_ON);
624 if (ret)
625 return ret;
626
627 /* enable eBF */
628 return mt7996_mcu_set_txbf(dev, BF_HW_EN_UPDATE);
629 }
630
mt7996_register_phy(struct mt7996_dev * dev,enum mt76_band_id band)631 static int mt7996_register_phy(struct mt7996_dev *dev, enum mt76_band_id band)
632 {
633 struct mt7996_phy *phy;
634 struct mt76_phy *mphy;
635 u32 mac_ofs, hif1_ofs = 0;
636 int ret;
637 struct mtk_wed_device *wed = &dev->mt76.mmio.wed;
638
639 if (!mt7996_band_valid(dev, band))
640 return 0;
641
642 if (is_mt7996(&dev->mt76) && band == MT_BAND2 && dev->hif2) {
643 hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0);
644 wed = &dev->mt76.mmio.wed_hif2;
645 }
646
647 mphy = mt76_alloc_radio_phy(&dev->mt76, sizeof(*phy), band);
648 if (!mphy)
649 return -ENOMEM;
650
651 phy = mphy->priv;
652 phy->dev = dev;
653 phy->mt76 = mphy;
654 mphy->dev->phys[band] = mphy;
655
656 INIT_DELAYED_WORK(&mphy->mac_work, mt7996_mac_work);
657
658 ret = mt7996_eeprom_parse_hw_cap(dev, phy);
659 if (ret)
660 goto error;
661
662 mac_ofs = band == MT_BAND2 ? MT_EE_MAC_ADDR3 : MT_EE_MAC_ADDR2;
663 #if defined(__linux__)
664 memcpy(mphy->macaddr, dev->mt76.eeprom.data + mac_ofs, ETH_ALEN);
665 #elif defined(__FreeBSD__)
666 memcpy(mphy->macaddr, (u8 *)dev->mt76.eeprom.data + mac_ofs, ETH_ALEN);
667 #endif
668 /* Make the extra PHY MAC address local without overlapping with
669 * the usual MAC address allocation scheme on multiple virtual interfaces
670 */
671 if (!is_valid_ether_addr(mphy->macaddr)) {
672 #if defined(__linux__)
673 memcpy(mphy->macaddr, dev->mt76.eeprom.data + MT_EE_MAC_ADDR,
674 #elif defined(__FreeBSD__)
675 memcpy(mphy->macaddr, (u8 *)dev->mt76.eeprom.data + MT_EE_MAC_ADDR,
676 #endif
677 ETH_ALEN);
678 mphy->macaddr[0] |= 2;
679 mphy->macaddr[0] ^= BIT(7);
680 if (band == MT_BAND2)
681 mphy->macaddr[0] ^= BIT(6);
682 }
683 mt76_eeprom_override(mphy);
684
685 /* init wiphy according to mphy and phy */
686 mt7996_init_wiphy_band(mphy->hw, phy);
687 ret = mt7996_init_tx_queues(mphy->priv,
688 MT_TXQ_ID(band),
689 MT7996_TX_RING_SIZE,
690 MT_TXQ_RING_BASE(band) + hif1_ofs,
691 wed);
692 if (ret)
693 goto error;
694
695 ret = mt76_register_phy(mphy, true, mt76_rates,
696 ARRAY_SIZE(mt76_rates));
697 if (ret)
698 goto error;
699
700 if (wed == &dev->mt76.mmio.wed_hif2 && mtk_wed_device_active(wed)) {
701 u32 irq_mask = dev->mt76.mmio.irqmask | MT_INT_TX_DONE_BAND2;
702
703 mt76_wr(dev, MT_INT1_MASK_CSR, irq_mask);
704 mtk_wed_device_start(&dev->mt76.mmio.wed_hif2, irq_mask);
705 }
706
707 return 0;
708
709 error:
710 mphy->dev->phys[band] = NULL;
711 return ret;
712 }
713
714 static void
mt7996_unregister_phy(struct mt7996_phy * phy)715 mt7996_unregister_phy(struct mt7996_phy *phy)
716 {
717 #if defined(CONFIG_HWMON)
718 if (phy)
719 mt7996_unregister_thermal(phy);
720 #endif
721 }
722
mt7996_init_work(struct work_struct * work)723 static void mt7996_init_work(struct work_struct *work)
724 {
725 struct mt7996_dev *dev = container_of(work, struct mt7996_dev,
726 init_work);
727
728 mt7996_mcu_set_eeprom(dev);
729 mt7996_mac_init(dev);
730 mt7996_txbf_init(dev);
731 }
732
mt7996_wfsys_reset(struct mt7996_dev * dev)733 void mt7996_wfsys_reset(struct mt7996_dev *dev)
734 {
735 mt76_set(dev, MT_WF_SUBSYS_RST, 0x1);
736 msleep(20);
737
738 mt76_clear(dev, MT_WF_SUBSYS_RST, 0x1);
739 msleep(20);
740 }
741
mt7996_wed_rro_init(struct mt7996_dev * dev)742 static int mt7996_wed_rro_init(struct mt7996_dev *dev)
743 {
744 #ifdef CONFIG_NET_MEDIATEK_SOC_WED
745 struct mtk_wed_device *wed = &dev->mt76.mmio.wed;
746 u32 reg = MT_RRO_ADDR_ELEM_SEG_ADDR0;
747 struct mt7996_wed_rro_addr *addr;
748 void *ptr;
749 int i;
750
751 if (!dev->has_rro)
752 return 0;
753
754 if (!mtk_wed_device_active(wed))
755 return 0;
756
757 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.ba_bitmap); i++) {
758 ptr = dmam_alloc_coherent(dev->mt76.dma_dev,
759 MT7996_RRO_BA_BITMAP_CR_SIZE,
760 &dev->wed_rro.ba_bitmap[i].phy_addr,
761 GFP_KERNEL);
762 if (!ptr)
763 return -ENOMEM;
764
765 dev->wed_rro.ba_bitmap[i].ptr = ptr;
766 }
767
768 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.addr_elem); i++) {
769 int j;
770
771 ptr = dmam_alloc_coherent(dev->mt76.dma_dev,
772 MT7996_RRO_WINDOW_MAX_SIZE * sizeof(*addr),
773 &dev->wed_rro.addr_elem[i].phy_addr,
774 GFP_KERNEL);
775 if (!ptr)
776 return -ENOMEM;
777
778 dev->wed_rro.addr_elem[i].ptr = ptr;
779 memset(dev->wed_rro.addr_elem[i].ptr, 0,
780 MT7996_RRO_WINDOW_MAX_SIZE * sizeof(*addr));
781
782 addr = dev->wed_rro.addr_elem[i].ptr;
783 for (j = 0; j < MT7996_RRO_WINDOW_MAX_SIZE; j++) {
784 addr->signature = 0xff;
785 addr++;
786 }
787
788 wed->wlan.ind_cmd.addr_elem_phys[i] =
789 dev->wed_rro.addr_elem[i].phy_addr;
790 }
791
792 ptr = dmam_alloc_coherent(dev->mt76.dma_dev,
793 MT7996_RRO_WINDOW_MAX_LEN * sizeof(*addr),
794 &dev->wed_rro.session.phy_addr,
795 GFP_KERNEL);
796 if (!ptr)
797 return -ENOMEM;
798
799 dev->wed_rro.session.ptr = ptr;
800 addr = dev->wed_rro.session.ptr;
801 for (i = 0; i < MT7996_RRO_WINDOW_MAX_LEN; i++) {
802 addr->signature = 0xff;
803 addr++;
804 }
805
806 /* rro hw init */
807 /* TODO: remove line after WM has set */
808 mt76_clear(dev, WF_RRO_AXI_MST_CFG, WF_RRO_AXI_MST_CFG_DIDX_OK);
809
810 /* setup BA bitmap cache address */
811 mt76_wr(dev, MT_RRO_BA_BITMAP_BASE0,
812 dev->wed_rro.ba_bitmap[0].phy_addr);
813 mt76_wr(dev, MT_RRO_BA_BITMAP_BASE1, 0);
814 mt76_wr(dev, MT_RRO_BA_BITMAP_BASE_EXT0,
815 dev->wed_rro.ba_bitmap[1].phy_addr);
816 mt76_wr(dev, MT_RRO_BA_BITMAP_BASE_EXT1, 0);
817
818 /* setup Address element address */
819 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.addr_elem); i++) {
820 mt76_wr(dev, reg, dev->wed_rro.addr_elem[i].phy_addr >> 4);
821 reg += 4;
822 }
823
824 /* setup Address element address - separate address segment mode */
825 mt76_wr(dev, MT_RRO_ADDR_ARRAY_BASE1,
826 MT_RRO_ADDR_ARRAY_ELEM_ADDR_SEG_MODE);
827
828 wed->wlan.ind_cmd.win_size = ffs(MT7996_RRO_WINDOW_MAX_LEN) - 6;
829 wed->wlan.ind_cmd.particular_sid = MT7996_RRO_MAX_SESSION;
830 wed->wlan.ind_cmd.particular_se_phys = dev->wed_rro.session.phy_addr;
831 wed->wlan.ind_cmd.se_group_nums = MT7996_RRO_ADDR_ELEM_LEN;
832 wed->wlan.ind_cmd.ack_sn_addr = MT_RRO_ACK_SN_CTRL;
833
834 mt76_wr(dev, MT_RRO_IND_CMD_SIGNATURE_BASE0, 0x15010e00);
835 mt76_set(dev, MT_RRO_IND_CMD_SIGNATURE_BASE1,
836 MT_RRO_IND_CMD_SIGNATURE_BASE1_EN);
837
838 /* particular session configure */
839 /* use max session idx + 1 as particular session id */
840 mt76_wr(dev, MT_RRO_PARTICULAR_CFG0, dev->wed_rro.session.phy_addr);
841 mt76_wr(dev, MT_RRO_PARTICULAR_CFG1,
842 MT_RRO_PARTICULAR_CONFG_EN |
843 FIELD_PREP(MT_RRO_PARTICULAR_SID, MT7996_RRO_MAX_SESSION));
844
845 /* interrupt enable */
846 mt76_wr(dev, MT_RRO_HOST_INT_ENA,
847 MT_RRO_HOST_INT_ENA_HOST_RRO_DONE_ENA);
848
849 /* rro ind cmd queue init */
850 return mt7996_dma_rro_init(dev);
851 #else
852 return 0;
853 #endif
854 }
855
mt7996_wed_rro_free(struct mt7996_dev * dev)856 static void mt7996_wed_rro_free(struct mt7996_dev *dev)
857 {
858 #ifdef CONFIG_NET_MEDIATEK_SOC_WED
859 int i;
860
861 if (!dev->has_rro)
862 return;
863
864 if (!mtk_wed_device_active(&dev->mt76.mmio.wed))
865 return;
866
867 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.ba_bitmap); i++) {
868 if (!dev->wed_rro.ba_bitmap[i].ptr)
869 continue;
870
871 dmam_free_coherent(dev->mt76.dma_dev,
872 MT7996_RRO_BA_BITMAP_CR_SIZE,
873 dev->wed_rro.ba_bitmap[i].ptr,
874 dev->wed_rro.ba_bitmap[i].phy_addr);
875 }
876
877 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.addr_elem); i++) {
878 if (!dev->wed_rro.addr_elem[i].ptr)
879 continue;
880
881 dmam_free_coherent(dev->mt76.dma_dev,
882 MT7996_RRO_WINDOW_MAX_SIZE *
883 sizeof(struct mt7996_wed_rro_addr),
884 dev->wed_rro.addr_elem[i].ptr,
885 dev->wed_rro.addr_elem[i].phy_addr);
886 }
887
888 if (!dev->wed_rro.session.ptr)
889 return;
890
891 dmam_free_coherent(dev->mt76.dma_dev,
892 MT7996_RRO_WINDOW_MAX_LEN *
893 sizeof(struct mt7996_wed_rro_addr),
894 dev->wed_rro.session.ptr,
895 dev->wed_rro.session.phy_addr);
896 #endif
897 }
898
mt7996_wed_rro_work(struct work_struct * work)899 static void mt7996_wed_rro_work(struct work_struct *work)
900 {
901 #ifdef CONFIG_NET_MEDIATEK_SOC_WED
902 struct mt7996_dev *dev;
903 LIST_HEAD(list);
904
905 dev = (struct mt7996_dev *)container_of(work, struct mt7996_dev,
906 wed_rro.work);
907
908 spin_lock_bh(&dev->wed_rro.lock);
909 list_splice_init(&dev->wed_rro.poll_list, &list);
910 spin_unlock_bh(&dev->wed_rro.lock);
911
912 while (!list_empty(&list)) {
913 struct mt7996_wed_rro_session_id *e;
914 int i;
915
916 e = list_first_entry(&list, struct mt7996_wed_rro_session_id,
917 list);
918 list_del_init(&e->list);
919
920 for (i = 0; i < MT7996_RRO_WINDOW_MAX_LEN; i++) {
921 void *ptr = dev->wed_rro.session.ptr;
922 struct mt7996_wed_rro_addr *elem;
923 u32 idx, elem_id = i;
924
925 if (e->id == MT7996_RRO_MAX_SESSION)
926 goto reset;
927
928 idx = e->id / MT7996_RRO_BA_BITMAP_SESSION_SIZE;
929 if (idx >= ARRAY_SIZE(dev->wed_rro.addr_elem))
930 goto out;
931
932 ptr = dev->wed_rro.addr_elem[idx].ptr;
933 elem_id +=
934 (e->id % MT7996_RRO_BA_BITMAP_SESSION_SIZE) *
935 MT7996_RRO_WINDOW_MAX_LEN;
936 reset:
937 elem = ptr + elem_id * sizeof(*elem);
938 elem->signature = 0xff;
939 }
940 mt7996_mcu_wed_rro_reset_sessions(dev, e->id);
941 out:
942 kfree(e);
943 }
944 #endif
945 }
946
mt7996_variant_type_init(struct mt7996_dev * dev)947 static int mt7996_variant_type_init(struct mt7996_dev *dev)
948 {
949 u32 val = mt76_rr(dev, MT_PAD_GPIO);
950 u8 var_type;
951
952 switch (mt76_chip(&dev->mt76)) {
953 case 0x7990:
954 if (val & MT_PAD_GPIO_2ADIE_TBTC)
955 var_type = MT7996_VAR_TYPE_233;
956 else
957 var_type = MT7996_VAR_TYPE_444;
958 break;
959 case 0x7992:
960 if (val & MT_PAD_GPIO_ADIE_SINGLE)
961 var_type = MT7992_VAR_TYPE_23;
962 else if (u32_get_bits(val, MT_PAD_GPIO_ADIE_COMB_7992))
963 var_type = MT7992_VAR_TYPE_44;
964 else
965 return -EINVAL;
966 break;
967 default:
968 return -EINVAL;
969 }
970
971 dev->var.type = var_type;
972 return 0;
973 }
974
mt7996_variant_fem_init(struct mt7996_dev * dev)975 static int mt7996_variant_fem_init(struct mt7996_dev *dev)
976 {
977 #define MT7976C_EFUSE_OFFSET 0x470
978 u8 buf[MT7996_EEPROM_BLOCK_SIZE], idx, adie_idx, adie_comb;
979 u32 regval, val = mt76_rr(dev, MT_PAD_GPIO);
980 u16 adie_id, adie_ver;
981 bool is_7976c;
982 int ret;
983
984 if (is_mt7992(&dev->mt76)) {
985 adie_idx = (val & MT_PAD_GPIO_ADIE_SINGLE) ? 0 : 1;
986 adie_comb = u32_get_bits(val, MT_PAD_GPIO_ADIE_COMB_7992);
987 } else {
988 adie_idx = 0;
989 adie_comb = u32_get_bits(val, MT_PAD_GPIO_ADIE_COMB);
990 }
991
992 ret = mt7996_mcu_rf_regval(dev, MT_ADIE_CHIP_ID(adie_idx), ®val, false);
993 if (ret)
994 return ret;
995
996 ret = mt7996_mcu_get_eeprom(dev, MT7976C_EFUSE_OFFSET, buf, sizeof(buf));
997 if (ret && ret != -EINVAL)
998 return ret;
999
1000 adie_ver = u32_get_bits(regval, MT_ADIE_VERSION_MASK);
1001 idx = MT7976C_EFUSE_OFFSET % MT7996_EEPROM_BLOCK_SIZE;
1002 is_7976c = adie_ver == 0x8a10 || adie_ver == 0x8b00 ||
1003 adie_ver == 0x8c10 || buf[idx] == 0xc;
1004
1005 adie_id = u32_get_bits(regval, MT_ADIE_CHIP_ID_MASK);
1006 if (adie_id == 0x7975 || adie_id == 0x7979 ||
1007 (adie_id == 0x7976 && is_7976c))
1008 dev->var.fem = MT7996_FEM_INT;
1009 else if (adie_id == 0x7977 && adie_comb == 1)
1010 dev->var.fem = MT7996_FEM_MIX;
1011 else
1012 dev->var.fem = MT7996_FEM_EXT;
1013
1014 return 0;
1015 }
1016
mt7996_init_hardware(struct mt7996_dev * dev)1017 static int mt7996_init_hardware(struct mt7996_dev *dev)
1018 {
1019 int ret, idx;
1020
1021 mt76_wr(dev, MT_INT_SOURCE_CSR, ~0);
1022 if (is_mt7992(&dev->mt76)) {
1023 mt76_rmw(dev, MT_AFE_CTL_BAND_PLL_03(MT_BAND0), MT_AFE_CTL_BAND_PLL_03_MSB_EN, 0);
1024 mt76_rmw(dev, MT_AFE_CTL_BAND_PLL_03(MT_BAND1), MT_AFE_CTL_BAND_PLL_03_MSB_EN, 0);
1025 }
1026
1027 INIT_WORK(&dev->init_work, mt7996_init_work);
1028 INIT_WORK(&dev->wed_rro.work, mt7996_wed_rro_work);
1029 INIT_LIST_HEAD(&dev->wed_rro.poll_list);
1030 spin_lock_init(&dev->wed_rro.lock);
1031
1032 ret = mt7996_variant_type_init(dev);
1033 if (ret)
1034 return ret;
1035
1036 ret = mt7996_dma_init(dev);
1037 if (ret)
1038 return ret;
1039
1040 set_bit(MT76_STATE_INITIALIZED, &dev->mphy.state);
1041
1042 ret = mt7996_mcu_init(dev);
1043 if (ret)
1044 return ret;
1045
1046 ret = mt7996_wed_rro_init(dev);
1047 if (ret)
1048 return ret;
1049
1050 ret = mt7996_variant_fem_init(dev);
1051 if (ret)
1052 return ret;
1053
1054 ret = mt7996_eeprom_init(dev);
1055 if (ret < 0)
1056 return ret;
1057
1058 /* Beacon and mgmt frames should occupy wcid 0 */
1059 idx = mt76_wcid_alloc(dev->mt76.wcid_mask, MT7996_WTBL_STA);
1060 if (idx)
1061 return -ENOSPC;
1062
1063 dev->mt76.global_wcid.idx = idx;
1064 dev->mt76.global_wcid.hw_key_idx = -1;
1065 dev->mt76.global_wcid.tx_info |= MT_WCID_TX_INFO_SET;
1066 rcu_assign_pointer(dev->mt76.wcid[idx], &dev->mt76.global_wcid);
1067
1068 return 0;
1069 }
1070
mt7996_set_stream_vht_txbf_caps(struct mt7996_phy * phy)1071 void mt7996_set_stream_vht_txbf_caps(struct mt7996_phy *phy)
1072 {
1073 int sts;
1074 u32 *cap;
1075
1076 if (!phy->mt76->cap.has_5ghz)
1077 return;
1078
1079 sts = hweight16(phy->mt76->chainmask);
1080 cap = &phy->mt76->sband_5g.sband.vht_cap.cap;
1081
1082 *cap |= IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE |
1083 IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE;
1084
1085 if (is_mt7996(phy->mt76->dev))
1086 *cap |= FIELD_PREP(IEEE80211_VHT_CAP_BEAMFORMEE_STS_MASK, 3);
1087 else
1088 *cap |= FIELD_PREP(IEEE80211_VHT_CAP_BEAMFORMEE_STS_MASK, 4);
1089
1090 *cap &= ~(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK |
1091 IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE |
1092 IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE);
1093
1094 if (sts < 2)
1095 return;
1096
1097 *cap |= IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE |
1098 IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE |
1099 FIELD_PREP(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK, sts - 1);
1100 }
1101
1102 static void
mt7996_set_stream_he_txbf_caps(struct mt7996_phy * phy,struct ieee80211_sta_he_cap * he_cap,int vif,enum nl80211_band band)1103 mt7996_set_stream_he_txbf_caps(struct mt7996_phy *phy,
1104 struct ieee80211_sta_he_cap *he_cap, int vif,
1105 enum nl80211_band band)
1106 {
1107 struct ieee80211_he_cap_elem *elem = &he_cap->he_cap_elem;
1108 int sts = hweight16(phy->mt76->chainmask);
1109 bool non_2g = band != NL80211_BAND_2GHZ;
1110 u8 c;
1111
1112 #ifdef CONFIG_MAC80211_MESH
1113 if (vif == NL80211_IFTYPE_MESH_POINT)
1114 return;
1115 #endif
1116
1117 elem->phy_cap_info[3] &= ~IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER;
1118 elem->phy_cap_info[4] &= ~IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER;
1119
1120 c = IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK |
1121 IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_MASK;
1122 elem->phy_cap_info[5] &= ~c;
1123
1124 c = IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB |
1125 IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB;
1126 elem->phy_cap_info[6] &= ~c;
1127
1128 elem->phy_cap_info[7] &= ~IEEE80211_HE_PHY_CAP7_MAX_NC_MASK;
1129
1130 c = IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US |
1131 IEEE80211_HE_PHY_CAP2_UL_MU_FULL_MU_MIMO |
1132 IEEE80211_HE_PHY_CAP2_UL_MU_PARTIAL_MU_MIMO;
1133 elem->phy_cap_info[2] |= c;
1134
1135 c = IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE;
1136
1137 if (is_mt7996(phy->mt76->dev))
1138 c |= IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_4 |
1139 (IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_4 * non_2g);
1140 else
1141 c |= IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_5 |
1142 (IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_5 * non_2g);
1143
1144 elem->phy_cap_info[4] |= c;
1145
1146 /* do not support NG16 due to spec D4.0 changes subcarrier idx */
1147 c = IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_42_SU |
1148 IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_75_MU;
1149
1150 if (vif == NL80211_IFTYPE_STATION)
1151 c |= IEEE80211_HE_PHY_CAP6_PARTIAL_BANDWIDTH_DL_MUMIMO;
1152
1153 elem->phy_cap_info[6] |= c;
1154
1155 if (sts < 2)
1156 return;
1157
1158 /* the maximum cap is 4 x 3, (Nr, Nc) = (3, 2) */
1159 elem->phy_cap_info[7] |= min_t(int, sts - 1, 2) << 3;
1160
1161 if (!(vif == NL80211_IFTYPE_AP || vif == NL80211_IFTYPE_STATION))
1162 return;
1163
1164 elem->phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER;
1165
1166 c = FIELD_PREP(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK,
1167 sts - 1) |
1168 (FIELD_PREP(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_MASK,
1169 sts - 1) * non_2g);
1170
1171 elem->phy_cap_info[5] |= c;
1172
1173 if (vif != NL80211_IFTYPE_AP)
1174 return;
1175
1176 elem->phy_cap_info[4] |= IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER;
1177
1178 c = IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB |
1179 IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB;
1180 elem->phy_cap_info[6] |= c;
1181
1182 c = 0;
1183 if (non_2g)
1184 c |= IEEE80211_HE_PHY_CAP7_STBC_TX_ABOVE_80MHZ |
1185 IEEE80211_HE_PHY_CAP7_STBC_RX_ABOVE_80MHZ;
1186 elem->phy_cap_info[7] |= c;
1187 }
1188
1189 static void
mt7996_init_he_caps(struct mt7996_phy * phy,enum nl80211_band band,struct ieee80211_sband_iftype_data * data,enum nl80211_iftype iftype)1190 mt7996_init_he_caps(struct mt7996_phy *phy, enum nl80211_band band,
1191 struct ieee80211_sband_iftype_data *data,
1192 enum nl80211_iftype iftype)
1193 {
1194 struct ieee80211_sta_he_cap *he_cap = &data->he_cap;
1195 struct ieee80211_he_cap_elem *he_cap_elem = &he_cap->he_cap_elem;
1196 struct ieee80211_he_mcs_nss_supp *he_mcs = &he_cap->he_mcs_nss_supp;
1197 int i, nss = hweight8(phy->mt76->antenna_mask);
1198 u16 mcs_map = 0;
1199
1200 for (i = 0; i < 8; i++) {
1201 if (i < nss)
1202 mcs_map |= (IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2));
1203 else
1204 mcs_map |= (IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2));
1205 }
1206
1207 he_cap->has_he = true;
1208
1209 he_cap_elem->mac_cap_info[0] = IEEE80211_HE_MAC_CAP0_HTC_HE;
1210 he_cap_elem->mac_cap_info[3] = IEEE80211_HE_MAC_CAP3_OMI_CONTROL |
1211 IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_3;
1212 he_cap_elem->mac_cap_info[4] = IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU;
1213
1214 if (band == NL80211_BAND_2GHZ)
1215 he_cap_elem->phy_cap_info[0] =
1216 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G;
1217 else
1218 he_cap_elem->phy_cap_info[0] =
1219 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G |
1220 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G;
1221
1222 he_cap_elem->phy_cap_info[1] = IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD;
1223 he_cap_elem->phy_cap_info[2] = IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ |
1224 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ;
1225
1226 he_cap_elem->phy_cap_info[7] =
1227 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI;
1228
1229 switch (iftype) {
1230 case NL80211_IFTYPE_AP:
1231 he_cap_elem->mac_cap_info[0] |= IEEE80211_HE_MAC_CAP0_TWT_RES;
1232 he_cap_elem->mac_cap_info[2] |= IEEE80211_HE_MAC_CAP2_BSR;
1233 he_cap_elem->mac_cap_info[4] |= IEEE80211_HE_MAC_CAP4_BQR;
1234 he_cap_elem->mac_cap_info[5] |=
1235 IEEE80211_HE_MAC_CAP5_OM_CTRL_UL_MU_DATA_DIS_RX;
1236 he_cap_elem->phy_cap_info[3] |=
1237 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_QPSK |
1238 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_QPSK;
1239 he_cap_elem->phy_cap_info[6] |=
1240 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE |
1241 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT;
1242 he_cap_elem->phy_cap_info[9] |=
1243 IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU |
1244 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU;
1245 break;
1246 case NL80211_IFTYPE_STATION:
1247 he_cap_elem->mac_cap_info[1] |=
1248 IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US;
1249
1250 if (band == NL80211_BAND_2GHZ)
1251 he_cap_elem->phy_cap_info[0] |=
1252 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_RU_MAPPING_IN_2G;
1253 else
1254 he_cap_elem->phy_cap_info[0] |=
1255 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_RU_MAPPING_IN_5G;
1256
1257 he_cap_elem->phy_cap_info[1] |=
1258 IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A |
1259 IEEE80211_HE_PHY_CAP1_HE_LTF_AND_GI_FOR_HE_PPDUS_0_8US;
1260 he_cap_elem->phy_cap_info[3] |=
1261 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_QPSK |
1262 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_QPSK;
1263 he_cap_elem->phy_cap_info[6] |=
1264 IEEE80211_HE_PHY_CAP6_TRIG_CQI_FB |
1265 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE |
1266 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT;
1267 he_cap_elem->phy_cap_info[7] |=
1268 IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPP;
1269 he_cap_elem->phy_cap_info[8] |=
1270 IEEE80211_HE_PHY_CAP8_20MHZ_IN_40MHZ_HE_PPDU_IN_2G |
1271 IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU |
1272 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU |
1273 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_484;
1274 he_cap_elem->phy_cap_info[9] |=
1275 IEEE80211_HE_PHY_CAP9_LONGER_THAN_16_SIGB_OFDM_SYM |
1276 IEEE80211_HE_PHY_CAP9_NON_TRIGGERED_CQI_FEEDBACK |
1277 IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU |
1278 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU |
1279 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB |
1280 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB;
1281 break;
1282 default:
1283 break;
1284 }
1285
1286 he_mcs->rx_mcs_80 = cpu_to_le16(mcs_map);
1287 he_mcs->tx_mcs_80 = cpu_to_le16(mcs_map);
1288 he_mcs->rx_mcs_160 = cpu_to_le16(mcs_map);
1289 he_mcs->tx_mcs_160 = cpu_to_le16(mcs_map);
1290
1291 mt7996_set_stream_he_txbf_caps(phy, he_cap, iftype, band);
1292
1293 memset(he_cap->ppe_thres, 0, sizeof(he_cap->ppe_thres));
1294 if (he_cap_elem->phy_cap_info[6] &
1295 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT) {
1296 mt76_connac_gen_ppe_thresh(he_cap->ppe_thres, nss, band);
1297 } else {
1298 he_cap_elem->phy_cap_info[9] |=
1299 u8_encode_bits(IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_16US,
1300 IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_MASK);
1301 }
1302
1303 if (band == NL80211_BAND_6GHZ) {
1304 u16 cap = IEEE80211_HE_6GHZ_CAP_TX_ANTPAT_CONS |
1305 IEEE80211_HE_6GHZ_CAP_RX_ANTPAT_CONS;
1306
1307 cap |= u16_encode_bits(IEEE80211_HT_MPDU_DENSITY_0_5,
1308 IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START) |
1309 u16_encode_bits(IEEE80211_VHT_MAX_AMPDU_1024K,
1310 IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP) |
1311 u16_encode_bits(IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454,
1312 IEEE80211_HE_6GHZ_CAP_MAX_MPDU_LEN);
1313
1314 data->he_6ghz_capa.capa = cpu_to_le16(cap);
1315 }
1316 }
1317
1318 static void
mt7996_init_eht_caps(struct mt7996_phy * phy,enum nl80211_band band,struct ieee80211_sband_iftype_data * data,enum nl80211_iftype iftype)1319 mt7996_init_eht_caps(struct mt7996_phy *phy, enum nl80211_band band,
1320 struct ieee80211_sband_iftype_data *data,
1321 enum nl80211_iftype iftype)
1322 {
1323 struct ieee80211_sta_eht_cap *eht_cap = &data->eht_cap;
1324 struct ieee80211_eht_cap_elem_fixed *eht_cap_elem = &eht_cap->eht_cap_elem;
1325 struct ieee80211_eht_mcs_nss_supp *eht_nss = &eht_cap->eht_mcs_nss_supp;
1326 enum nl80211_chan_width width = phy->mt76->chandef.width;
1327 int nss = hweight8(phy->mt76->antenna_mask);
1328 int sts = hweight16(phy->mt76->chainmask);
1329 u8 val;
1330
1331 if (!phy->dev->has_eht)
1332 return;
1333
1334 eht_cap->has_eht = true;
1335
1336 eht_cap_elem->mac_cap_info[0] =
1337 IEEE80211_EHT_MAC_CAP0_EPCS_PRIO_ACCESS |
1338 IEEE80211_EHT_MAC_CAP0_OM_CONTROL |
1339 u8_encode_bits(IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_11454,
1340 IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_MASK);
1341
1342 eht_cap_elem->phy_cap_info[0] =
1343 IEEE80211_EHT_PHY_CAP0_NDP_4_EHT_LFT_32_GI |
1344 IEEE80211_EHT_PHY_CAP0_SU_BEAMFORMER |
1345 IEEE80211_EHT_PHY_CAP0_SU_BEAMFORMEE;
1346
1347 /* Set the maximum capability regardless of the antenna configuration. */
1348 val = is_mt7992(phy->mt76->dev) ? 4 : 3;
1349 eht_cap_elem->phy_cap_info[0] |=
1350 u8_encode_bits(u8_get_bits(val, BIT(0)),
1351 IEEE80211_EHT_PHY_CAP0_BEAMFORMEE_SS_80MHZ_MASK);
1352
1353 eht_cap_elem->phy_cap_info[1] =
1354 u8_encode_bits(u8_get_bits(val, GENMASK(2, 1)),
1355 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_80MHZ_MASK);
1356
1357 eht_cap_elem->phy_cap_info[2] =
1358 u8_encode_bits(sts - 1, IEEE80211_EHT_PHY_CAP2_SOUNDING_DIM_80MHZ_MASK);
1359
1360 if (band != NL80211_BAND_2GHZ) {
1361 eht_cap_elem->phy_cap_info[1] |=
1362 u8_encode_bits(val,
1363 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_160MHZ_MASK);
1364
1365 eht_cap_elem->phy_cap_info[2] |=
1366 u8_encode_bits(sts - 1,
1367 IEEE80211_EHT_PHY_CAP2_SOUNDING_DIM_160MHZ_MASK);
1368 }
1369
1370 if (band == NL80211_BAND_6GHZ) {
1371 eht_cap_elem->phy_cap_info[0] |=
1372 IEEE80211_EHT_PHY_CAP0_320MHZ_IN_6GHZ;
1373
1374 eht_cap_elem->phy_cap_info[1] |=
1375 u8_encode_bits(val,
1376 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_320MHZ_MASK);
1377
1378 eht_cap_elem->phy_cap_info[2] |=
1379 u8_encode_bits(sts - 1,
1380 IEEE80211_EHT_PHY_CAP2_SOUNDING_DIM_320MHZ_MASK);
1381 }
1382
1383 eht_cap_elem->phy_cap_info[3] =
1384 IEEE80211_EHT_PHY_CAP3_NG_16_SU_FEEDBACK |
1385 IEEE80211_EHT_PHY_CAP3_NG_16_MU_FEEDBACK |
1386 IEEE80211_EHT_PHY_CAP3_CODEBOOK_4_2_SU_FDBK |
1387 IEEE80211_EHT_PHY_CAP3_CODEBOOK_7_5_MU_FDBK;
1388
1389 eht_cap_elem->phy_cap_info[4] =
1390 IEEE80211_EHT_PHY_CAP4_EHT_MU_PPDU_4_EHT_LTF_08_GI |
1391 u8_encode_bits(min_t(int, sts - 1, 2),
1392 IEEE80211_EHT_PHY_CAP4_MAX_NC_MASK);
1393
1394 eht_cap_elem->phy_cap_info[5] =
1395 u8_encode_bits(IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_16US,
1396 IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_MASK) |
1397 u8_encode_bits(u8_get_bits(1, GENMASK(1, 0)),
1398 IEEE80211_EHT_PHY_CAP5_MAX_NUM_SUPP_EHT_LTF_MASK);
1399
1400 val = width == NL80211_CHAN_WIDTH_320 ? 0xf :
1401 width == NL80211_CHAN_WIDTH_160 ? 0x7 :
1402 width == NL80211_CHAN_WIDTH_80 ? 0x3 : 0x1;
1403 eht_cap_elem->phy_cap_info[6] =
1404 u8_encode_bits(val, IEEE80211_EHT_PHY_CAP6_MCS15_SUPP_MASK);
1405
1406 val = u8_encode_bits(nss, IEEE80211_EHT_MCS_NSS_RX) |
1407 u8_encode_bits(nss, IEEE80211_EHT_MCS_NSS_TX);
1408 #define SET_EHT_MAX_NSS(_bw, _val) do { \
1409 eht_nss->bw._##_bw.rx_tx_mcs9_max_nss = _val; \
1410 eht_nss->bw._##_bw.rx_tx_mcs11_max_nss = _val; \
1411 eht_nss->bw._##_bw.rx_tx_mcs13_max_nss = _val; \
1412 } while (0)
1413
1414 SET_EHT_MAX_NSS(80, val);
1415 SET_EHT_MAX_NSS(160, val);
1416 if (band == NL80211_BAND_6GHZ)
1417 SET_EHT_MAX_NSS(320, val);
1418 #undef SET_EHT_MAX_NSS
1419
1420 if (iftype != NL80211_IFTYPE_AP)
1421 return;
1422
1423 eht_cap_elem->phy_cap_info[3] |=
1424 IEEE80211_EHT_PHY_CAP3_TRIG_SU_BF_FDBK |
1425 IEEE80211_EHT_PHY_CAP3_TRIG_MU_BF_PART_BW_FDBK;
1426
1427 eht_cap_elem->phy_cap_info[7] =
1428 IEEE80211_EHT_PHY_CAP7_NON_OFDMA_UL_MU_MIMO_80MHZ |
1429 IEEE80211_EHT_PHY_CAP7_MU_BEAMFORMER_80MHZ;
1430
1431 if (band == NL80211_BAND_2GHZ)
1432 return;
1433
1434 eht_cap_elem->phy_cap_info[7] |=
1435 IEEE80211_EHT_PHY_CAP7_NON_OFDMA_UL_MU_MIMO_160MHZ |
1436 IEEE80211_EHT_PHY_CAP7_MU_BEAMFORMER_160MHZ;
1437
1438 if (band != NL80211_BAND_6GHZ)
1439 return;
1440
1441 eht_cap_elem->phy_cap_info[7] |=
1442 IEEE80211_EHT_PHY_CAP7_NON_OFDMA_UL_MU_MIMO_320MHZ |
1443 IEEE80211_EHT_PHY_CAP7_MU_BEAMFORMER_320MHZ;
1444 }
1445
1446 static void
__mt7996_set_stream_he_eht_caps(struct mt7996_phy * phy,struct ieee80211_supported_band * sband,enum nl80211_band band)1447 __mt7996_set_stream_he_eht_caps(struct mt7996_phy *phy,
1448 struct ieee80211_supported_band *sband,
1449 enum nl80211_band band)
1450 {
1451 struct ieee80211_sband_iftype_data *data = phy->iftype[band];
1452 int i, n = 0;
1453
1454 for (i = 0; i < NUM_NL80211_IFTYPES; i++) {
1455 switch (i) {
1456 case NL80211_IFTYPE_STATION:
1457 case NL80211_IFTYPE_AP:
1458 #ifdef CONFIG_MAC80211_MESH
1459 case NL80211_IFTYPE_MESH_POINT:
1460 #endif
1461 break;
1462 default:
1463 continue;
1464 }
1465
1466 data[n].types_mask = BIT(i);
1467 mt7996_init_he_caps(phy, band, &data[n], i);
1468 mt7996_init_eht_caps(phy, band, &data[n], i);
1469
1470 n++;
1471 }
1472
1473 _ieee80211_set_sband_iftype_data(sband, data, n);
1474 }
1475
mt7996_set_stream_he_eht_caps(struct mt7996_phy * phy)1476 void mt7996_set_stream_he_eht_caps(struct mt7996_phy *phy)
1477 {
1478 if (phy->mt76->cap.has_2ghz)
1479 __mt7996_set_stream_he_eht_caps(phy, &phy->mt76->sband_2g.sband,
1480 NL80211_BAND_2GHZ);
1481
1482 if (phy->mt76->cap.has_5ghz)
1483 __mt7996_set_stream_he_eht_caps(phy, &phy->mt76->sband_5g.sband,
1484 NL80211_BAND_5GHZ);
1485
1486 if (phy->mt76->cap.has_6ghz)
1487 __mt7996_set_stream_he_eht_caps(phy, &phy->mt76->sband_6g.sband,
1488 NL80211_BAND_6GHZ);
1489 }
1490
mt7996_register_device(struct mt7996_dev * dev)1491 int mt7996_register_device(struct mt7996_dev *dev)
1492 {
1493 struct ieee80211_hw *hw = mt76_hw(dev);
1494 #if defined(CONFIG_HWMON)
1495 struct mt7996_phy *phy;
1496 #endif
1497 int ret;
1498
1499 dev->phy.dev = dev;
1500 dev->phy.mt76 = &dev->mt76.phy;
1501 dev->mt76.phy.priv = &dev->phy;
1502 INIT_WORK(&dev->rc_work, mt7996_mac_sta_rc_work);
1503 INIT_DELAYED_WORK(&dev->mphy.mac_work, mt7996_mac_work);
1504 INIT_LIST_HEAD(&dev->sta_rc_list);
1505 INIT_LIST_HEAD(&dev->twt_list);
1506
1507 init_waitqueue_head(&dev->reset_wait);
1508 INIT_WORK(&dev->reset_work, mt7996_mac_reset_work);
1509 INIT_WORK(&dev->dump_work, mt7996_mac_dump_work);
1510 mutex_init(&dev->dump_mutex);
1511
1512 ret = mt7996_init_hardware(dev);
1513 if (ret)
1514 return ret;
1515
1516 mt7996_init_wiphy(hw, &dev->mt76.mmio.wed);
1517
1518 ret = mt7996_register_phy(dev, MT_BAND1);
1519 if (ret)
1520 return ret;
1521
1522 ret = mt7996_register_phy(dev, MT_BAND2);
1523 if (ret)
1524 return ret;
1525
1526 ret = mt76_register_device(&dev->mt76, true, mt76_rates,
1527 ARRAY_SIZE(mt76_rates));
1528 if (ret)
1529 return ret;
1530
1531 #if defined(CONFIG_HWMON)
1532 mt7996_for_each_phy(dev, phy)
1533 mt7996_thermal_init(phy);
1534 #endif
1535
1536 ieee80211_queue_work(mt76_hw(dev), &dev->init_work);
1537
1538 dev->recovery.hw_init_done = true;
1539
1540 #if defined(CONFIG_MT7996_DEBUGFS)
1541 ret = mt7996_init_debugfs(dev);
1542 if (ret)
1543 goto error;
1544 #endif
1545
1546 ret = mt7996_coredump_register(dev);
1547 if (ret)
1548 goto error;
1549
1550 return 0;
1551
1552 error:
1553 cancel_work_sync(&dev->init_work);
1554
1555 return ret;
1556 }
1557
mt7996_unregister_device(struct mt7996_dev * dev)1558 void mt7996_unregister_device(struct mt7996_dev *dev)
1559 {
1560 cancel_work_sync(&dev->wed_rro.work);
1561 mt7996_unregister_phy(mt7996_phy3(dev));
1562 mt7996_unregister_phy(mt7996_phy2(dev));
1563 #if defined(CONFIG_HWMON)
1564 mt7996_unregister_thermal(&dev->phy);
1565 #endif
1566 mt7996_coredump_unregister(dev);
1567 mt76_unregister_device(&dev->mt76);
1568 mt7996_wed_rro_free(dev);
1569 mt7996_mcu_exit(dev);
1570 mt7996_tx_token_put(dev);
1571 mt7996_dma_cleanup(dev);
1572 tasklet_disable(&dev->mt76.irq_tasklet);
1573
1574 mt76_free_device(&dev->mt76);
1575 }
1576