1 // SPDX-License-Identifier: BSD-3-Clause-Clear
2 /*
3 * Copyright (C) 2022 MediaTek Inc.
4 */
5
6 #include <linux/kernel.h>
7 #include <linux/module.h>
8 #include <linux/pci.h>
9 #include <linux/rtnetlink.h>
10
11 #include "mt7996.h"
12 #include "mac.h"
13 #include "mcu.h"
14 #include "../trace.h"
15 #include "../dma.h"
16
17 static bool wed_enable;
18 module_param(wed_enable, bool, 0644);
19
20 #define INVALID_REG_ADDR 0xffffffff
21
22 static const struct __base mt7996_reg_base[] = {
23 [WF_AGG_BASE] = { { 0x820e2000, 0x820f2000, 0x830e2000 } },
24 [WF_ARB_BASE] = { { 0x820e3000, 0x820f3000, 0x830e3000 } },
25 [WF_TMAC_BASE] = { { 0x820e4000, 0x820f4000, 0x830e4000 } },
26 [WF_RMAC_BASE] = { { 0x820e5000, 0x820f5000, 0x830e5000 } },
27 [WF_DMA_BASE] = { { 0x820e7000, 0x820f7000, 0x830e7000 } },
28 [WF_WTBLOFF_BASE] = { { 0x820e9000, 0x820f9000, 0x830e9000 } },
29 [WF_ETBF_BASE] = { { 0x820ea000, 0x820fa000, 0x830ea000 } },
30 [WF_LPON_BASE] = { { 0x820eb000, 0x820fb000, 0x830eb000 } },
31 [WF_MIB_BASE] = { { 0x820ed000, 0x820fd000, 0x830ed000 } },
32 [WF_RATE_BASE] = { { 0x820ee000, 0x820fe000, 0x830ee000 } },
33 };
34
35 static const u32 mt7996_offs[] = {
36 [MIB_RVSR0] = 0x720,
37 [MIB_RVSR1] = 0x724,
38 [MIB_BTSCR5] = 0x788,
39 [MIB_BTSCR6] = 0x798,
40 [MIB_RSCR1] = 0x7ac,
41 [MIB_RSCR27] = 0x954,
42 [MIB_RSCR28] = 0x958,
43 [MIB_RSCR29] = 0x95c,
44 [MIB_RSCR30] = 0x960,
45 [MIB_RSCR31] = 0x964,
46 [MIB_RSCR33] = 0x96c,
47 [MIB_RSCR35] = 0x974,
48 [MIB_RSCR36] = 0x978,
49 [MIB_BSCR0] = 0x9cc,
50 [MIB_BSCR1] = 0x9d0,
51 [MIB_BSCR2] = 0x9d4,
52 [MIB_BSCR3] = 0x9d8,
53 [MIB_BSCR4] = 0x9dc,
54 [MIB_BSCR5] = 0x9e0,
55 [MIB_BSCR6] = 0x9e4,
56 [MIB_BSCR7] = 0x9e8,
57 [MIB_BSCR17] = 0xa10,
58 [MIB_TRDR1] = 0xa28,
59 [MIB_TSCR0] = 0x6b0,
60 [MIB_TSCR1] = 0x6b4,
61 [MIB_TSCR2] = 0x6b8,
62 [MIB_TSCR3] = 0x6bc,
63 [MIB_TSCR4] = 0x6c0,
64 [MIB_TSCR5] = 0x6c4,
65 [MIB_TSCR6] = 0x6c8,
66 [MIB_TSCR7] = 0x6d0,
67 [HIF_REMAP_L1] = 0x24,
68 [HIF_REMAP_BASE_L1] = 0x130000,
69 [HIF_REMAP_L2] = 0x1b4,
70 [HIF_REMAP_BASE_L2] = 0x1000,
71 [CBTOP1_PHY_END] = 0x77ffffff,
72 [INFRA_MCU_END] = 0x7c3fffff,
73 [WTBLON_WDUCR] = 0x370,
74 [WTBL_UPDATE] = 0x380,
75 [WTBL_ITCR] = 0x3b0,
76 [WTBL_ITCR0] = 0x3b8,
77 [WTBL_ITCR1] = 0x3bc,
78 };
79
80 static const u32 mt7992_offs[] = {
81 [MIB_RVSR0] = 0x760,
82 [MIB_RVSR1] = 0x764,
83 [MIB_BTSCR5] = 0x7c8,
84 [MIB_BTSCR6] = 0x7d8,
85 [MIB_RSCR1] = 0x7f0,
86 [MIB_RSCR27] = 0x998,
87 [MIB_RSCR28] = 0x99c,
88 [MIB_RSCR29] = 0x9a0,
89 [MIB_RSCR30] = 0x9a4,
90 [MIB_RSCR31] = 0x9a8,
91 [MIB_RSCR33] = 0x9b0,
92 [MIB_RSCR35] = 0x9b8,
93 [MIB_RSCR36] = 0x9bc,
94 [MIB_BSCR0] = 0xac8,
95 [MIB_BSCR1] = 0xacc,
96 [MIB_BSCR2] = 0xad0,
97 [MIB_BSCR3] = 0xad4,
98 [MIB_BSCR4] = 0xad8,
99 [MIB_BSCR5] = 0xadc,
100 [MIB_BSCR6] = 0xae0,
101 [MIB_BSCR7] = 0xae4,
102 [MIB_BSCR17] = 0xb0c,
103 [MIB_TRDR1] = 0xb24,
104 [MIB_TSCR0] = 0x6b0,
105 [MIB_TSCR1] = 0x6b4,
106 [MIB_TSCR2] = 0x6b8,
107 [MIB_TSCR3] = 0x6bc,
108 [MIB_TSCR4] = 0x6c0,
109 [MIB_TSCR5] = 0x6c4,
110 [MIB_TSCR6] = 0x6c8,
111 [MIB_TSCR7] = 0x6d0,
112 [HIF_REMAP_L1] = 0x8,
113 [HIF_REMAP_BASE_L1] = 0x40000,
114 [HIF_REMAP_L2] = 0x1b4,
115 [HIF_REMAP_BASE_L2] = 0x1000,
116 [CBTOP1_PHY_END] = 0x77ffffff,
117 [INFRA_MCU_END] = 0x7c3fffff,
118 [WTBLON_WDUCR] = 0x370,
119 [WTBL_UPDATE] = 0x380,
120 [WTBL_ITCR] = 0x3b0,
121 [WTBL_ITCR0] = 0x3b8,
122 [WTBL_ITCR1] = 0x3bc,
123 };
124
125 static const u32 mt7990_offs[] = {
126 [MIB_RVSR0] = 0x800,
127 [MIB_RVSR1] = 0x804,
128 [MIB_BTSCR5] = 0x868,
129 [MIB_BTSCR6] = 0x878,
130 [MIB_RSCR1] = 0x890,
131 [MIB_RSCR27] = 0xa38,
132 [MIB_RSCR28] = 0xa3c,
133 [MIB_RSCR29] = 0xa40,
134 [MIB_RSCR30] = 0xa44,
135 [MIB_RSCR31] = 0xa48,
136 [MIB_RSCR33] = 0xa50,
137 [MIB_RSCR35] = 0xa58,
138 [MIB_RSCR36] = 0xa5c,
139 [MIB_BSCR0] = 0xbb8,
140 [MIB_BSCR1] = 0xbbc,
141 [MIB_BSCR2] = 0xbc0,
142 [MIB_BSCR3] = 0xbc4,
143 [MIB_BSCR4] = 0xbc8,
144 [MIB_BSCR5] = 0xbcc,
145 [MIB_BSCR6] = 0xbd0,
146 [MIB_BSCR7] = 0xbd4,
147 [MIB_BSCR17] = 0xbfc,
148 [MIB_TRDR1] = 0xc14,
149 [MIB_TSCR0] = 0x750,
150 [MIB_TSCR1] = 0x754,
151 [MIB_TSCR2] = 0x758,
152 [MIB_TSCR3] = 0x75c,
153 [MIB_TSCR4] = 0x760,
154 [MIB_TSCR5] = 0x764,
155 [MIB_TSCR6] = 0x768,
156 [MIB_TSCR7] = 0x770,
157 [HIF_REMAP_L1] = 0x8,
158 [HIF_REMAP_BASE_L1] = 0x40000,
159 [HIF_REMAP_L2] = 0x1b8,
160 [HIF_REMAP_BASE_L2] = 0x110000,
161 [CBTOP1_PHY_END] = 0x7fffffff,
162 [INFRA_MCU_END] = 0x7cffffff,
163 [WTBLON_WDUCR] = 0x400,
164 [WTBL_UPDATE] = 0x410,
165 [WTBL_ITCR] = 0x440,
166 [WTBL_ITCR0] = 0x448,
167 [WTBL_ITCR1] = 0x44c,
168 };
169
170 static const struct __map mt7996_reg_map[] = {
171 { 0x54000000, 0x02000, 0x1000 }, /* WFDMA_0 (PCIE0 MCU DMA0) */
172 { 0x55000000, 0x03000, 0x1000 }, /* WFDMA_1 (PCIE0 MCU DMA1) */
173 { 0x56000000, 0x04000, 0x1000 }, /* WFDMA reserved */
174 { 0x57000000, 0x05000, 0x1000 }, /* WFDMA MCU wrap CR */
175 { 0x58000000, 0x06000, 0x1000 }, /* WFDMA PCIE1 MCU DMA0 (MEM_DMA) */
176 { 0x59000000, 0x07000, 0x1000 }, /* WFDMA PCIE1 MCU DMA1 */
177 { 0x820c0000, 0x08000, 0x4000 }, /* WF_UMAC_TOP (PLE) */
178 { 0x820c8000, 0x0c000, 0x2000 }, /* WF_UMAC_TOP (PSE) */
179 { 0x820cc000, 0x0e000, 0x1000 }, /* WF_UMAC_TOP (PP) */
180 { 0x74030000, 0x10000, 0x1000 }, /* PCIe MAC */
181 { 0x820e0000, 0x20000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */
182 { 0x820e1000, 0x20400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */
183 { 0x820e2000, 0x20800, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */
184 { 0x820e3000, 0x20c00, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */
185 { 0x820e4000, 0x21000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */
186 { 0x820e5000, 0x21400, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */
187 { 0x820ce000, 0x21c00, 0x0200 }, /* WF_LMAC_TOP (WF_SEC) */
188 { 0x820e7000, 0x21e00, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */
189 { 0x820cf000, 0x22000, 0x1000 }, /* WF_LMAC_TOP (WF_PF) */
190 { 0x820e9000, 0x23400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */
191 { 0x820ea000, 0x24000, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */
192 { 0x820eb000, 0x24200, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */
193 { 0x820ec000, 0x24600, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_INT) */
194 { 0x820ed000, 0x24800, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */
195 { 0x820ca000, 0x26000, 0x2000 }, /* WF_LMAC_TOP BN0 (WF_MUCOP) */
196 { 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */
197 { 0x40000000, 0x70000, 0x10000 }, /* WF_UMAC_SYSRAM */
198 { 0x00400000, 0x80000, 0x10000 }, /* WF_MCU_SYSRAM */
199 { 0x00410000, 0x90000, 0x10000 }, /* WF_MCU_SYSRAM (configure register) */
200 { 0x820f0000, 0xa0000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */
201 { 0x820f1000, 0xa0600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */
202 { 0x820f2000, 0xa0800, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */
203 { 0x820f3000, 0xa0c00, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */
204 { 0x820f4000, 0xa1000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */
205 { 0x820f5000, 0xa1400, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */
206 { 0x820f7000, 0xa1e00, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */
207 { 0x820f9000, 0xa3400, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */
208 { 0x820fa000, 0xa4000, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */
209 { 0x820fb000, 0xa4200, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */
210 { 0x820fc000, 0xa4600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_INT) */
211 { 0x820fd000, 0xa4800, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */
212 { 0x820cc000, 0xa5000, 0x2000 }, /* WF_LMAC_TOP BN1 (WF_MUCOP) */
213 { 0x820c4000, 0xa8000, 0x4000 }, /* WF_LMAC_TOP BN1 (WF_MUCOP) */
214 { 0x820b0000, 0xae000, 0x1000 }, /* [APB2] WFSYS_ON */
215 { 0x80020000, 0xb0000, 0x10000 }, /* WF_TOP_MISC_OFF */
216 { 0x81020000, 0xc0000, 0x10000 }, /* WF_TOP_MISC_ON */
217 { 0x7c020000, 0xd0000, 0x10000 }, /* CONN_INFRA, wfdma */
218 { 0x7c060000, 0xe0000, 0x10000 }, /* CONN_INFRA, conn_host_csr_top */
219 { 0x7c000000, 0xf0000, 0x10000 }, /* CONN_INFRA */
220 { 0x0, 0x0, 0x0 }, /* imply end of search */
221 };
222
223 static const struct __map mt7990_reg_map[] = {
224 {0x54000000, 0x02000, 0x1000}, /* WFDMA_0 (PCIE0 MCU DMA0) */
225 {0x55000000, 0x03000, 0x1000}, /* WFDMA_1 (PCIE0 MCU DMA1) */
226 {0x56000000, 0x04000, 0x1000}, /* WFDMA_2 (Reserved) */
227 {0x57000000, 0x05000, 0x1000}, /* WFDMA_3 (MCU wrap CR) */
228 {0x58000000, 0x06000, 0x1000}, /* WFDMA_4 (PCIE1 MCU DMA0 (MEM_DMA)) */
229 {0x59000000, 0x07000, 0x1000}, /* WFDMA_5 (PCIE1 MCU DMA1) */
230 {0x820c0000, 0x08000, 0x4000}, /* WF_UMAC_TOP (PLE) */
231 {0x820c8000, 0x0c000, 0x2000}, /* WF_UMAC_TOP (PSE) */
232 {0x820cc000, 0x0e000, 0x2000}, /* WF_UMAC_TOP (PP) */
233 {0x820e0000, 0x20000, 0x0400}, /* WF_LMAC_TOP BN0 (WF_CFG) */
234 {0x820e1000, 0x20400, 0x0200}, /* WF_LMAC_TOP BN0 (WF_TRB) */
235 {0x820e2000, 0x20800, 0x0400}, /* WF_LMAC_TOP BN0 (WF_AGG) */
236 {0x820e3000, 0x20c00, 0x0400}, /* WF_LMAC_TOP BN0 (WF_ARB) */
237 {0x820e4000, 0x21000, 0x0400}, /* WF_LMAC_TOP BN0 (WF_TMAC) */
238 {0x820e5000, 0x21400, 0x0800}, /* WF_LMAC_TOP BN0 (WF_RMAC) */
239 {0x820ce000, 0x21c00, 0x0200}, /* WF_LMAC_TOP (WF_SEC) */
240 {0x820e7000, 0x21e00, 0x0200}, /* WF_LMAC_TOP BN0 (WF_DMA) */
241 {0x820cf000, 0x22000, 0x1000}, /* WF_LMAC_TOP (WF_PF) */
242 {0x820e9000, 0x23400, 0x0200}, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */
243 {0x820ea000, 0x24000, 0x0200}, /* WF_LMAC_TOP BN0 (WF_ETBF) */
244 {0x820eb000, 0x24200, 0x0400}, /* WF_LMAC_TOP BN0 (WF_LPON) */
245 {0x820ec000, 0x24600, 0x0200}, /* WF_LMAC_TOP BN0 (WF_INT) */
246 {0x820ed000, 0x24800, 0x0800}, /* WF_LMAC_TOP BN0 (WF_MIB) */
247 {0x820ca000, 0x26000, 0x2000}, /* WF_LMAC_TOP BN0 (WF_MUCOP) */
248 {0x820d0000, 0x30000, 0x10000}, /* WF_LMAC_TOP (WF_WTBLON) */
249 {0x00400000, 0x80000, 0x10000}, /* WF_MCU_SYSRAM */
250 {0x820f0000, 0xa0000, 0x0400}, /* WF_LMAC_TOP BN1 (WF_CFG) */
251 {0x820f1000, 0xa0600, 0x0200}, /* WF_LMAC_TOP BN1 (WF_TRB) */
252 {0x820f2000, 0xa0800, 0x0400}, /* WF_LMAC_TOP BN1 (WF_AGG) */
253 {0x820f3000, 0xa0c00, 0x0400}, /* WF_LMAC_TOP BN1 (WF_ARB) */
254 {0x820f4000, 0xa1000, 0x0400}, /* WF_LMAC_TOP BN1 (WF_TMAC) */
255 {0x820f5000, 0xa1400, 0x0800}, /* WF_LMAC_TOP BN1 (WF_RMAC) */
256 {0x820f7000, 0xa1e00, 0x0200}, /* WF_LMAC_TOP BN1 (WF_DMA) */
257 {0x820f9000, 0xa3400, 0x0200}, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */
258 {0x820fa000, 0xa4000, 0x0200}, /* WF_LMAC_TOP BN1 (WF_ETBF) */
259 {0x820fb000, 0xa4200, 0x0400}, /* WF_LMAC_TOP BN1 (WF_LPON) */
260 {0x820fc000, 0xa4600, 0x0200}, /* WF_LMAC_TOP BN1 (WF_INT) */
261 {0x820fd000, 0xa4800, 0x0800}, /* WF_LMAC_TOP BN1 (WF_MIB) */
262 {0x820cc000, 0xa5000, 0x2000}, /* WF_LMAC_TOP BN1 (WF_MUCOP) */
263 {0x820c4000, 0xa8000, 0x4000}, /* WF_LMAC_TOP (WF_UWTBL) */
264 {0x81030000, 0xae000, 0x100}, /* WFSYS_AON part 1 */
265 {0x81031000, 0xae100, 0x100}, /* WFSYS_AON part 2 */
266 {0x81032000, 0xae200, 0x100}, /* WFSYS_AON part 3 */
267 {0x81033000, 0xae300, 0x100}, /* WFSYS_AON part 4 */
268 {0x81034000, 0xae400, 0x100}, /* WFSYS_AON part 5 */
269 {0x80020000, 0xb0000, 0x10000}, /* WF_TOP_MISC_OFF */
270 {0x81020000, 0xc0000, 0x10000}, /* WF_TOP_MISC_ON */
271 {0x81040000, 0x120000, 0x1000}, /* WF_MCU_CFG_ON */
272 {0x81050000, 0x121000, 0x1000}, /* WF_MCU_EINT */
273 {0x81060000, 0x122000, 0x1000}, /* WF_MCU_GPT */
274 {0x81070000, 0x123000, 0x1000}, /* WF_MCU_WDT */
275 {0x80010000, 0x124000, 0x1000}, /* WF_AXIDMA */
276 {0x7c020000, 0xd0000, 0x10000}, /* CONN_INFRA, wfdma for from CODA flow use */
277 {0x7c060000, 0xe0000, 0x10000}, /* CONN_INFRA, conn_host_csr_top for from CODA flow use */
278 {0x20020000, 0xd0000, 0x10000}, /* CONN_INFRA, wfdma */
279 {0x20060000, 0xe0000, 0x10000}, /* CONN_INFRA, conn_host_csr_top */
280 {0x7c000000, 0xf0000, 0x10000}, /* CONN_INFRA */
281 {0x70020000, 0x1f0000, 0x9000}, /* PCIE remapping (AP2CONN) */
282 {0x0, 0x0, 0x0}, /* imply end of search */
283 };
284
mt7996_reg_map_l1(struct mt7996_dev * dev,u32 addr)285 static u32 mt7996_reg_map_l1(struct mt7996_dev *dev, u32 addr)
286 {
287 u32 offset = FIELD_GET(MT_HIF_REMAP_L1_OFFSET, addr);
288 u32 base = FIELD_GET(MT_HIF_REMAP_L1_BASE, addr);
289 u32 l1_mask, val;
290
291 if (is_mt7996(&dev->mt76)) {
292 l1_mask = MT_HIF_REMAP_L1_MASK_7996;
293 val = FIELD_PREP(MT_HIF_REMAP_L1_MASK_7996, base);
294 } else {
295 l1_mask = MT_HIF_REMAP_L1_MASK;
296 val = FIELD_PREP(MT_HIF_REMAP_L1_MASK, base);
297 }
298
299 dev->bus_ops->rmw(&dev->mt76, MT_HIF_REMAP_L1, l1_mask, val);
300 /* use read to push write */
301 dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_L1);
302
303 return MT_HIF_REMAP_BASE_L1 + offset;
304 }
305
mt7996_reg_map_l2(struct mt7996_dev * dev,u32 addr)306 static u32 mt7996_reg_map_l2(struct mt7996_dev *dev, u32 addr)
307 {
308 u32 offset, base, l2_mask, val;
309
310 if (is_mt7990(&dev->mt76)) {
311 offset = FIELD_GET(MT_HIF_REMAP_L2_OFFSET_7990, addr);
312 base = FIELD_GET(MT_HIF_REMAP_L2_BASE_7990, addr);
313 l2_mask = MT_HIF_REMAP_L2_MASK_7990;
314 val = FIELD_PREP(MT_HIF_REMAP_L2_MASK_7990, base);
315 } else {
316 offset = FIELD_GET(MT_HIF_REMAP_L2_OFFSET, addr);
317 base = FIELD_GET(MT_HIF_REMAP_L2_BASE, addr);
318 l2_mask = MT_HIF_REMAP_L2_MASK;
319 val = FIELD_PREP(MT_HIF_REMAP_L2_MASK, base);
320 }
321
322 dev->bus_ops->rmw(&dev->mt76, MT_HIF_REMAP_L2, l2_mask, val);
323 /* use read to push write */
324 dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_L2);
325
326 return MT_HIF_REMAP_BASE_L2 + offset;
327 }
328
mt7996_reg_map_cbtop(struct mt7996_dev * dev,u32 addr)329 static u32 mt7996_reg_map_cbtop(struct mt7996_dev *dev, u32 addr)
330 {
331 u32 offset = FIELD_GET(MT_HIF_REMAP_CBTOP_OFFSET, addr);
332 u32 base = FIELD_GET(MT_HIF_REMAP_CBTOP_BASE, addr);
333
334 dev->bus_ops->rmw(&dev->mt76, MT_HIF_REMAP_CBTOP,
335 MT_HIF_REMAP_CBTOP_MASK,
336 FIELD_PREP(MT_HIF_REMAP_CBTOP_MASK, base));
337 /* use read to push write */
338 dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_CBTOP);
339
340 return MT_HIF_REMAP_BASE_CBTOP + offset;
341 }
342
__mt7996_reg_addr(struct mt7996_dev * dev,u32 addr)343 static u32 __mt7996_reg_addr(struct mt7996_dev *dev, u32 addr)
344 {
345 int i;
346
347 if (addr < 0x100000)
348 return addr;
349
350 for (i = 0; i < dev->reg.map_size; i++) {
351 u32 ofs;
352
353 if (addr < dev->reg.map[i].phys)
354 continue;
355
356 ofs = addr - dev->reg.map[i].phys;
357 if (ofs >= dev->reg.map[i].size)
358 continue;
359
360 return dev->reg.map[i].mapped + ofs;
361 }
362
363 return INVALID_REG_ADDR;
364 }
365
__mt7996_reg_remap_addr(struct mt7996_dev * dev,u32 addr)366 static u32 __mt7996_reg_remap_addr(struct mt7996_dev *dev, u32 addr)
367 {
368 if ((addr >= MT_INFRA_BASE && addr < MT_WFSYS0_PHY_START) ||
369 (addr >= MT_WFSYS0_PHY_START && addr < MT_WFSYS1_PHY_START) ||
370 (addr >= MT_WFSYS1_PHY_START && addr <= MT_WFSYS1_PHY_END))
371 return mt7996_reg_map_l1(dev, addr);
372
373 /* CONN_INFRA: covert to phyiscal addr and use layer 1 remap */
374 if (addr >= MT_INFRA_MCU_START && addr <= MT_INFRA_MCU_END) {
375 addr = addr - MT_INFRA_MCU_START + MT_INFRA_BASE;
376 return mt7996_reg_map_l1(dev, addr);
377 }
378
379 if (dev_is_pci(dev->mt76.dev) &&
380 ((addr >= MT_CBTOP1_PHY_START && addr <= MT_CBTOP1_PHY_END) ||
381 addr >= MT_CBTOP2_PHY_START)) {
382 if (is_mt7990(&dev->mt76))
383 return mt7996_reg_map_cbtop(dev, addr);
384 return mt7996_reg_map_l1(dev, addr);
385 }
386
387 return mt7996_reg_map_l2(dev, addr);
388 }
389
mt7996_memcpy_fromio(struct mt7996_dev * dev,void * buf,u32 offset,size_t len)390 void mt7996_memcpy_fromio(struct mt7996_dev *dev, void *buf, u32 offset,
391 size_t len)
392 {
393 u32 addr = __mt7996_reg_addr(dev, offset);
394
395 if (addr != INVALID_REG_ADDR) {
396 memcpy_fromio(buf, dev->mt76.mmio.regs + addr, len);
397 return;
398 }
399
400 spin_lock_bh(&dev->reg_lock);
401 memcpy_fromio(buf, dev->mt76.mmio.regs +
402 __mt7996_reg_remap_addr(dev, offset), len);
403 spin_unlock_bh(&dev->reg_lock);
404 }
405
mt7996_rr(struct mt76_dev * mdev,u32 offset)406 static u32 mt7996_rr(struct mt76_dev *mdev, u32 offset)
407 {
408 struct mt7996_dev *dev = container_of(mdev, struct mt7996_dev, mt76);
409 u32 addr = __mt7996_reg_addr(dev, offset), val;
410
411 if (addr != INVALID_REG_ADDR)
412 return dev->bus_ops->rr(mdev, addr);
413
414 spin_lock_bh(&dev->reg_lock);
415 val = dev->bus_ops->rr(mdev, __mt7996_reg_remap_addr(dev, offset));
416 spin_unlock_bh(&dev->reg_lock);
417
418 return val;
419 }
420
mt7996_wr(struct mt76_dev * mdev,u32 offset,u32 val)421 static void mt7996_wr(struct mt76_dev *mdev, u32 offset, u32 val)
422 {
423 struct mt7996_dev *dev = container_of(mdev, struct mt7996_dev, mt76);
424 u32 addr = __mt7996_reg_addr(dev, offset);
425
426 if (addr != INVALID_REG_ADDR) {
427 dev->bus_ops->wr(mdev, addr, val);
428 return;
429 }
430
431 spin_lock_bh(&dev->reg_lock);
432 dev->bus_ops->wr(mdev, __mt7996_reg_remap_addr(dev, offset), val);
433 spin_unlock_bh(&dev->reg_lock);
434 }
435
mt7996_rmw(struct mt76_dev * mdev,u32 offset,u32 mask,u32 val)436 static u32 mt7996_rmw(struct mt76_dev *mdev, u32 offset, u32 mask, u32 val)
437 {
438 struct mt7996_dev *dev = container_of(mdev, struct mt7996_dev, mt76);
439 u32 addr = __mt7996_reg_addr(dev, offset);
440
441 if (addr != INVALID_REG_ADDR)
442 return dev->bus_ops->rmw(mdev, addr, mask, val);
443
444 spin_lock_bh(&dev->reg_lock);
445 val = dev->bus_ops->rmw(mdev, __mt7996_reg_remap_addr(dev, offset), mask, val);
446 spin_unlock_bh(&dev->reg_lock);
447
448 return val;
449 }
450
451 #ifdef CONFIG_NET_MEDIATEK_SOC_WED
mt7996_mmio_wed_reset(struct mtk_wed_device * wed)452 static int mt7996_mmio_wed_reset(struct mtk_wed_device *wed)
453 {
454 struct mt76_dev *mdev = container_of(wed, struct mt76_dev, mmio.wed);
455 struct mt7996_dev *dev = container_of(mdev, struct mt7996_dev, mt76);
456 struct mt76_phy *mphy = &dev->mphy;
457 int ret;
458
459 ASSERT_RTNL();
460
461 if (test_and_set_bit(MT76_STATE_WED_RESET, &mphy->state))
462 return -EBUSY;
463
464 ret = mt7996_mcu_set_ser(dev, UNI_CMD_SER_TRIGGER, UNI_CMD_SER_SET_RECOVER_FROM_ETH,
465 mphy->band_idx);
466 if (ret)
467 goto out;
468
469 rtnl_unlock();
470 if (!wait_for_completion_timeout(&mdev->mmio.wed_reset, 20 * HZ)) {
471 dev_err(mdev->dev, "wed reset timeout\n");
472 ret = -ETIMEDOUT;
473 }
474 rtnl_lock();
475 out:
476 clear_bit(MT76_STATE_WED_RESET, &mphy->state);
477
478 return ret;
479 }
480 #endif
481
mt7996_mmio_wed_init(struct mt7996_dev * dev,void * pdev_ptr,bool hif2,int * irq)482 int mt7996_mmio_wed_init(struct mt7996_dev *dev, void *pdev_ptr,
483 bool hif2, int *irq)
484 {
485 #ifdef CONFIG_NET_MEDIATEK_SOC_WED
486 struct mtk_wed_device *wed = &dev->mt76.mmio.wed;
487 struct pci_dev *pci_dev = pdev_ptr;
488 u32 hif1_ofs;
489
490 if (!wed_enable)
491 return 0;
492
493 if (hif2 && !mtk_wed_device_active(&dev->mt76.mmio.wed))
494 return 0;
495
496 hif1_ofs = dev->hif2 ? MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0) : 0;
497
498 if (hif2)
499 wed = &dev->mt76.mmio.wed_hif2;
500
501 wed->wlan.pci_dev = pci_dev;
502 wed->wlan.bus_type = MTK_WED_BUS_PCIE;
503
504 wed->wlan.base = devm_ioremap(dev->mt76.dev,
505 pci_resource_start(pci_dev, 0),
506 pci_resource_len(pci_dev, 0));
507 if (!wed->wlan.base)
508 return -ENOMEM;
509
510 wed->wlan.phy_base = pci_resource_start(pci_dev, 0);
511
512 if (hif2) {
513 wed->wlan.wpdma_int = wed->wlan.phy_base +
514 MT_INT_PCIE1_SOURCE_CSR_EXT;
515 wed->wlan.wpdma_mask = wed->wlan.phy_base +
516 MT_INT_PCIE1_MASK_CSR;
517 wed->wlan.wpdma_tx = wed->wlan.phy_base + hif1_ofs +
518 MT_TXQ_RING_BASE(0) +
519 MT7996_TXQ_BAND2 * MT_RING_SIZE;
520 if (is_mt7996(&dev->mt76)) {
521 wed->wlan.txfree_tbit = ffs(MT_INT_RX_TXFREE_EXT) - 1;
522 wed->wlan.wpdma_txfree = wed->wlan.phy_base + hif1_ofs +
523 MT_RXQ_RING_BASE(0) +
524 MT7996_RXQ_TXFREE2 * MT_RING_SIZE;
525 } else {
526 wed->wlan.txfree_tbit = ffs(MT_INT_RX_TXFREE_BAND1_EXT) - 1;
527 wed->wlan.wpdma_txfree = wed->wlan.phy_base + hif1_ofs +
528 MT_RXQ_RING_BASE(0) +
529 MT7996_RXQ_MCU_WA_EXT * MT_RING_SIZE;
530 }
531
532 wed->wlan.wpdma_rx_glo = wed->wlan.phy_base + hif1_ofs + MT_WFDMA0_GLO_CFG;
533 wed->wlan.wpdma_rx[0] = wed->wlan.phy_base + hif1_ofs +
534 MT_RXQ_RING_BASE(MT7996_RXQ_BAND2) +
535 MT7996_RXQ_BAND2 * MT_RING_SIZE;
536
537 wed->wlan.id = MT7996_DEVICE_ID_2;
538 wed->wlan.tx_tbit[0] = ffs(MT_INT_TX_DONE_BAND2) - 1;
539 } else {
540 wed->wlan.hw_rro = true;
541 wed->wlan.wpdma_int = wed->wlan.phy_base + MT_INT_SOURCE_CSR;
542 wed->wlan.wpdma_mask = wed->wlan.phy_base + MT_INT_MASK_CSR;
543 wed->wlan.wpdma_tx = wed->wlan.phy_base + MT_TXQ_RING_BASE(0) +
544 MT7996_TXQ_BAND0 * MT_RING_SIZE;
545
546 wed->wlan.wpdma_rx_glo = wed->wlan.phy_base + MT_WFDMA0_GLO_CFG;
547
548 wed->wlan.wpdma_rx[0] = wed->wlan.phy_base +
549 MT_RXQ_RING_BASE(MT7996_RXQ_BAND0) +
550 MT7996_RXQ_BAND0 * MT_RING_SIZE;
551
552 wed->wlan.wpdma_rx_rro[0] = wed->wlan.phy_base +
553 MT_RXQ_RING_BASE(MT7996_RXQ_RRO_BAND0) +
554 MT7996_RXQ_RRO_BAND0 * MT_RING_SIZE;
555 if (is_mt7996(&dev->mt76)) {
556 wed->wlan.wpdma_rx_rro[1] = wed->wlan.phy_base + hif1_ofs +
557 MT_RXQ_RING_BASE(MT7996_RXQ_RRO_BAND2) +
558 MT7996_RXQ_RRO_BAND2 * MT_RING_SIZE;
559 } else {
560 wed->wlan.wpdma_rx_rro[1] = wed->wlan.phy_base + hif1_ofs +
561 MT_RXQ_RING_BASE(MT7996_RXQ_RRO_BAND1) +
562 MT7996_RXQ_RRO_BAND1 * MT_RING_SIZE;
563 wed->wlan.wpdma_rx[1] = wed->wlan.phy_base + hif1_ofs +
564 MT_RXQ_RING_BASE(MT7996_RXQ_BAND1) +
565 MT7996_RXQ_BAND1 * MT_RING_SIZE;
566 }
567
568 wed->wlan.wpdma_rx_pg = wed->wlan.phy_base +
569 MT_RXQ_RING_BASE(MT7996_RXQ_MSDU_PG_BAND0) +
570 MT7996_RXQ_MSDU_PG_BAND0 * MT_RING_SIZE;
571
572 wed->wlan.rx_nbuf = 65536;
573 wed->wlan.rx_npkt = dev->hif2 ? 32768 : 24576;
574 wed->wlan.rx_size = SKB_WITH_OVERHEAD(MT_RX_BUF_SIZE);
575
576 wed->wlan.rx_tbit[0] = ffs(MT_INT_RX_DONE_BAND0) - 1;
577 wed->wlan.rro_rx_tbit[0] = ffs(MT_INT_RX_DONE_RRO_BAND0) - 1;
578 if (is_mt7996(&dev->mt76)) {
579 wed->wlan.rx_tbit[1] = ffs(MT_INT_RX_DONE_BAND2) - 1;
580 wed->wlan.rro_rx_tbit[1] = ffs(MT_INT_RX_DONE_RRO_BAND2) - 1;
581 } else {
582 wed->wlan.rx_tbit[1] = ffs(MT_INT_RX_DONE_BAND1) - 1;
583 wed->wlan.rro_rx_tbit[1] = ffs(MT_INT_RX_DONE_RRO_BAND1) - 1;
584 }
585
586 wed->wlan.rx_pg_tbit[0] = ffs(MT_INT_RX_DONE_MSDU_PG_BAND0) - 1;
587 wed->wlan.rx_pg_tbit[1] = ffs(MT_INT_RX_DONE_MSDU_PG_BAND1) - 1;
588 wed->wlan.rx_pg_tbit[2] = ffs(MT_INT_RX_DONE_MSDU_PG_BAND2) - 1;
589
590 wed->wlan.tx_tbit[0] = ffs(MT_INT_TX_DONE_BAND0) - 1;
591 wed->wlan.tx_tbit[1] = ffs(MT_INT_TX_DONE_BAND1) - 1;
592 if (is_mt7996(&dev->mt76)) {
593 wed->wlan.wpdma_txfree = wed->wlan.phy_base +
594 MT_RXQ_RING_BASE(0) +
595 MT7996_RXQ_TXFREE0 * MT_RING_SIZE;
596 wed->wlan.txfree_tbit = ffs(MT_INT_RX_TXFREE_MAIN) - 1;
597 } else {
598 wed->wlan.txfree_tbit = ffs(MT_INT_RX_DONE_WA_MAIN) - 1;
599 wed->wlan.wpdma_txfree = wed->wlan.phy_base + MT_RXQ_RING_BASE(0) +
600 MT7996_RXQ_MCU_WA_MAIN * MT_RING_SIZE;
601 }
602
603 if (dev->hif2 && is_mt7992(&dev->mt76))
604 wed->wlan.id = 0x7992;
605 }
606
607 wed->wlan.nbuf = MT7996_HW_TOKEN_SIZE;
608 wed->wlan.token_start = MT7996_TOKEN_SIZE - wed->wlan.nbuf;
609 wed->wlan.hif2 = hif2;
610
611 wed->wlan.amsdu_max_subframes = 8;
612 wed->wlan.amsdu_max_len = 1536;
613
614 wed->wlan.init_buf = mt7996_wed_init_buf;
615 wed->wlan.init_rx_buf = mt76_wed_init_rx_buf;
616 wed->wlan.release_rx_buf = mt76_wed_release_rx_buf;
617 wed->wlan.offload_enable = mt76_wed_offload_enable;
618 wed->wlan.offload_disable = mt76_wed_offload_disable;
619 if (!hif2) {
620 wed->wlan.reset = mt7996_mmio_wed_reset;
621 wed->wlan.reset_complete = mt76_wed_reset_complete;
622 }
623
624 if (mtk_wed_device_attach(wed))
625 return 0;
626
627 if (!hif2) {
628 dev->mt76.hwrro_mode = is_mt7996(&dev->mt76) ? MT76_HWRRO_V3
629 : MT76_HWRRO_V3_1;
630 dev->mt76.rx_token_size = MT7996_TOKEN_SIZE +
631 wed->wlan.rx_npkt;
632 }
633
634 *irq = wed->irq;
635 dev->mt76.dma_dev = wed->dev;
636
637 return 1;
638 #else
639 return 0;
640 #endif
641 }
642
mt7996_mmio_init(struct mt76_dev * mdev,void __iomem * mem_base,u32 device_id)643 static int mt7996_mmio_init(struct mt76_dev *mdev,
644 void __iomem *mem_base,
645 u32 device_id)
646 {
647 struct mt76_bus_ops *bus_ops;
648 struct mt7996_dev *dev;
649
650 dev = container_of(mdev, struct mt7996_dev, mt76);
651 mt76_mmio_init(&dev->mt76, mem_base);
652 spin_lock_init(&dev->reg_lock);
653
654 switch (device_id) {
655 case MT7996_DEVICE_ID:
656 dev->reg.base = mt7996_reg_base;
657 dev->reg.offs_rev = mt7996_offs;
658 dev->reg.map = mt7996_reg_map;
659 dev->reg.map_size = ARRAY_SIZE(mt7996_reg_map);
660 break;
661 case MT7992_DEVICE_ID:
662 dev->reg.base = mt7996_reg_base;
663 dev->reg.offs_rev = mt7992_offs;
664 dev->reg.map = mt7996_reg_map;
665 dev->reg.map_size = ARRAY_SIZE(mt7996_reg_map);
666 break;
667 case MT7990_DEVICE_ID:
668 dev->reg.base = mt7996_reg_base;
669 dev->reg.offs_rev = mt7990_offs;
670 dev->reg.map = mt7990_reg_map;
671 dev->reg.map_size = ARRAY_SIZE(mt7990_reg_map);
672 break;
673 default:
674 return -EINVAL;
675 }
676
677 dev->bus_ops = dev->mt76.bus;
678 bus_ops = devm_kmemdup(dev->mt76.dev, dev->bus_ops, sizeof(*bus_ops),
679 GFP_KERNEL);
680 if (!bus_ops)
681 return -ENOMEM;
682
683 bus_ops->rr = mt7996_rr;
684 bus_ops->wr = mt7996_wr;
685 bus_ops->rmw = mt7996_rmw;
686 dev->mt76.bus = bus_ops;
687
688 mdev->rev = (device_id << 16) | (mt76_rr(dev, MT_HW_REV) & 0xff);
689
690 dev_dbg(mdev->dev, "ASIC revision: %04x\n", mdev->rev);
691
692 return 0;
693 }
694
mt7996_dual_hif_set_irq_mask(struct mt7996_dev * dev,bool write_reg,u32 clear,u32 set)695 void mt7996_dual_hif_set_irq_mask(struct mt7996_dev *dev, bool write_reg,
696 u32 clear, u32 set)
697 {
698 struct mt76_dev *mdev = &dev->mt76;
699 unsigned long flags;
700
701 spin_lock_irqsave(&mdev->mmio.irq_lock, flags);
702
703 mdev->mmio.irqmask &= ~clear;
704 mdev->mmio.irqmask |= set;
705
706 if (write_reg) {
707 if (mtk_wed_device_active(&mdev->mmio.wed)) {
708 mtk_wed_device_irq_set_mask(&mdev->mmio.wed,
709 mdev->mmio.irqmask);
710 if (mtk_wed_device_active(&mdev->mmio.wed_hif2)) {
711 mtk_wed_device_irq_set_mask(&mdev->mmio.wed_hif2,
712 mdev->mmio.irqmask);
713 }
714 } else {
715 mt76_wr(dev, MT_INT_MASK_CSR, mdev->mmio.irqmask);
716 mt76_wr(dev, MT_INT1_MASK_CSR, mdev->mmio.irqmask);
717 }
718 }
719
720 spin_unlock_irqrestore(&mdev->mmio.irq_lock, flags);
721 }
722
mt7996_rx_poll_complete(struct mt76_dev * mdev,enum mt76_rxq_id q)723 static void mt7996_rx_poll_complete(struct mt76_dev *mdev,
724 enum mt76_rxq_id q)
725 {
726 if (q == MT_RXQ_NPU0 || q == MT_RXQ_NPU1) {
727 struct airoha_npu *npu;
728
729 npu = rcu_dereference(mdev->mmio.npu);
730 if (npu)
731 airoha_npu_wlan_enable_irq(npu, q - MT_RXQ_NPU0);
732 } else {
733 struct mt7996_dev *dev = container_of(mdev, struct mt7996_dev,
734 mt76);
735
736 mt7996_irq_enable(dev, MT_INT_RX(q));
737 }
738 }
739
740 /* TODO: support 2/4/6/8 MSI-X vectors */
mt7996_irq_tasklet(struct tasklet_struct * t)741 static void mt7996_irq_tasklet(struct tasklet_struct *t)
742 {
743 struct mt7996_dev *dev = from_tasklet(dev, t, mt76.irq_tasklet);
744 struct mtk_wed_device *wed = &dev->mt76.mmio.wed;
745 struct mtk_wed_device *wed_hif2 = &dev->mt76.mmio.wed_hif2;
746 u32 i, intr, mask, intr1 = 0;
747
748 if (dev->hif2 && mtk_wed_device_active(wed_hif2)) {
749 mtk_wed_device_irq_set_mask(wed_hif2, 0);
750 intr1 = mtk_wed_device_irq_get(wed_hif2,
751 dev->mt76.mmio.irqmask);
752 if (intr1 & MT_INT_RX_TXFREE_EXT)
753 napi_schedule(&dev->mt76.napi[MT_RXQ_TXFREE_BAND2]);
754
755 if (intr1 & MT_INT_RX_DONE_BAND2_EXT)
756 napi_schedule(&dev->mt76.napi[MT_RXQ_BAND2]);
757
758 if (intr1 & MT_INT_RX_TXFREE_BAND1_EXT)
759 napi_schedule(&dev->mt76.napi[MT_RXQ_BAND1_WA]);
760 }
761
762 if (mtk_wed_device_active(wed)) {
763 mtk_wed_device_irq_set_mask(wed, 0);
764 intr = mtk_wed_device_irq_get(wed, dev->mt76.mmio.irqmask);
765 intr |= (intr1 & ~MT_INT_TX_RX_DONE_EXT);
766 } else {
767 mt76_wr(dev, MT_INT_MASK_CSR, 0);
768 if (dev->hif2)
769 mt76_wr(dev, MT_INT1_MASK_CSR, 0);
770
771 intr = mt76_rr(dev, MT_INT_SOURCE_CSR);
772 intr &= dev->mt76.mmio.irqmask;
773 mt76_wr(dev, MT_INT_SOURCE_CSR, intr);
774 if (dev->hif2) {
775 intr1 = mt76_rr(dev, MT_INT1_SOURCE_CSR);
776 intr1 &= dev->mt76.mmio.irqmask;
777 mt76_wr(dev, MT_INT1_SOURCE_CSR, intr1);
778 intr |= intr1;
779 }
780 }
781
782 trace_dev_irq(&dev->mt76, intr, dev->mt76.mmio.irqmask);
783
784 mask = intr & MT_INT_RX_DONE_ALL;
785 if (intr & MT_INT_TX_DONE_MCU)
786 mask |= MT_INT_TX_DONE_MCU;
787 mt7996_irq_disable(dev, mask);
788
789 if (intr & MT_INT_TX_DONE_MCU)
790 napi_schedule(&dev->mt76.tx_napi);
791
792 for (i = 0; i < __MT_RXQ_MAX; i++) {
793 if ((intr & MT_INT_RX(i)))
794 napi_schedule(&dev->mt76.napi[i]);
795 }
796
797 if (intr & MT_INT_MCU_CMD) {
798 u32 val = mt76_rr(dev, MT_MCU_CMD);
799
800 mt76_wr(dev, MT_MCU_CMD, val);
801 if (val & (MT_MCU_CMD_ERROR_MASK | MT_MCU_CMD_WDT_MASK)) {
802 dev->recovery.state = val;
803 mt7996_reset(dev);
804 }
805 }
806 }
807
mt7996_irq_handler(int irq,void * dev_instance)808 irqreturn_t mt7996_irq_handler(int irq, void *dev_instance)
809 {
810 struct mt7996_dev *dev = dev_instance;
811
812 if (mtk_wed_device_active(&dev->mt76.mmio.wed))
813 mtk_wed_device_irq_set_mask(&dev->mt76.mmio.wed, 0);
814 else
815 mt76_wr(dev, MT_INT_MASK_CSR, 0);
816
817 if (dev->hif2) {
818 if (mtk_wed_device_active(&dev->mt76.mmio.wed_hif2))
819 mtk_wed_device_irq_set_mask(&dev->mt76.mmio.wed_hif2, 0);
820 else
821 mt76_wr(dev, MT_INT1_MASK_CSR, 0);
822 }
823
824 if (!test_bit(MT76_STATE_INITIALIZED, &dev->mphy.state))
825 return IRQ_NONE;
826
827 tasklet_schedule(&dev->mt76.irq_tasklet);
828
829 return IRQ_HANDLED;
830 }
831
mt7996_mmio_probe(struct device * pdev,void __iomem * mem_base,u32 device_id)832 struct mt7996_dev *mt7996_mmio_probe(struct device *pdev,
833 void __iomem *mem_base, u32 device_id)
834 {
835 static const struct mt76_driver_ops drv_ops = {
836 /* txwi_size = txd size + txp size */
837 .txwi_size = MT_TXD_SIZE + sizeof(struct mt76_connac_fw_txp),
838 .link_data_size = sizeof(struct mt7996_vif_link),
839 .drv_flags = MT_DRV_TXWI_NO_FREE |
840 MT_DRV_AMSDU_OFFLOAD |
841 MT_DRV_HW_MGMT_TXQ |
842 MT_DRV_HW_PS_BUFFERING,
843 .survey_flags = SURVEY_INFO_TIME_TX |
844 SURVEY_INFO_TIME_RX |
845 SURVEY_INFO_TIME_BSS_RX,
846 .token_size = MT7996_TOKEN_SIZE,
847 .tx_prepare_skb = mt7996_tx_prepare_skb,
848 .tx_complete_skb = mt76_connac_tx_complete_skb,
849 .rx_skb = mt7996_queue_rx_skb,
850 .rx_check = mt7996_rx_check,
851 .rx_poll_complete = mt7996_rx_poll_complete,
852 .rx_rro_ind_process = mt7996_rro_rx_process,
853 .rx_rro_add_msdu_page = mt7996_rro_msdu_page_add,
854 .update_survey = mt7996_update_channel,
855 .set_channel = mt7996_set_channel,
856 .vif_link_add = mt7996_vif_link_add,
857 .vif_link_remove = mt7996_vif_link_remove,
858 };
859 struct mt7996_dev *dev;
860 struct mt76_dev *mdev;
861 int ret;
862
863 mdev = mt76_alloc_device(pdev, sizeof(*dev), &mt7996_ops, &drv_ops);
864 if (!mdev)
865 return ERR_PTR(-ENOMEM);
866
867 dev = container_of(mdev, struct mt7996_dev, mt76);
868
869 ret = mt7996_mmio_init(mdev, mem_base, device_id);
870 if (ret)
871 goto error;
872
873 tasklet_setup(&mdev->irq_tasklet, mt7996_irq_tasklet);
874
875 mt76_wr(dev, MT_INT_MASK_CSR, 0);
876
877 return dev;
878
879 error:
880 mt76_free_device(&dev->mt76);
881
882 return ERR_PTR(ret);
883 }
884
mt7996_init(void)885 static int __init mt7996_init(void)
886 {
887 int ret;
888
889 ret = pci_register_driver(&mt7996_hif_driver);
890 if (ret)
891 return ret;
892
893 ret = pci_register_driver(&mt7996_pci_driver);
894 if (ret)
895 pci_unregister_driver(&mt7996_hif_driver);
896
897 return ret;
898 }
899
mt7996_exit(void)900 static void __exit mt7996_exit(void)
901 {
902 pci_unregister_driver(&mt7996_pci_driver);
903 pci_unregister_driver(&mt7996_hif_driver);
904 }
905
906 module_init(mt7996_init);
907 module_exit(mt7996_exit);
908 MODULE_DESCRIPTION("MediaTek MT7996 MMIO helpers");
909 MODULE_LICENSE("Dual BSD/GPL");
910