1 // SPDX-License-Identifier: ISC
2 /*
3 * Copyright (C) 2022 MediaTek Inc.
4 */
5
6 #include <linux/relay.h>
7 #include "mt7996.h"
8 #include "eeprom.h"
9 #include "mcu.h"
10 #include "mac.h"
11
12 #define FW_BIN_LOG_MAGIC 0x44d9c99a
13
14 /** global debugfs **/
15
16 struct hw_queue_map {
17 const char *name;
18 u8 index;
19 u8 pid;
20 u8 qid;
21 };
22
23 static int
mt7996_implicit_txbf_set(void * data,u64 val)24 mt7996_implicit_txbf_set(void *data, u64 val)
25 {
26 struct mt7996_dev *dev = data;
27
28 /* The existing connected stations shall reconnect to apply
29 * new implicit txbf configuration.
30 */
31 dev->ibf = !!val;
32
33 return mt7996_mcu_set_txbf(dev, BF_HW_EN_UPDATE);
34 }
35
36 static int
mt7996_implicit_txbf_get(void * data,u64 * val)37 mt7996_implicit_txbf_get(void *data, u64 *val)
38 {
39 struct mt7996_dev *dev = data;
40
41 *val = dev->ibf;
42
43 return 0;
44 }
45
46 DEFINE_DEBUGFS_ATTRIBUTE(fops_implicit_txbf, mt7996_implicit_txbf_get,
47 mt7996_implicit_txbf_set, "%lld\n");
48
49 /* test knob of system error recovery */
50 static ssize_t
mt7996_sys_recovery_set(struct file * file,const char __user * user_buf,size_t count,loff_t * ppos)51 mt7996_sys_recovery_set(struct file *file, const char __user *user_buf,
52 size_t count, loff_t *ppos)
53 {
54 struct mt7996_dev *dev = file->private_data;
55 char buf[16], *sep;
56 int ret = 0;
57 u16 band, val;
58
59 if (count >= sizeof(buf))
60 return -EINVAL;
61
62 if (copy_from_user(buf, user_buf, count))
63 return -EFAULT;
64
65 if (count && buf[count - 1] == '\n')
66 buf[count - 1] = '\0';
67 else
68 buf[count] = '\0';
69
70 sep = strchr(buf, ',');
71 if (!sep)
72 return -EINVAL;
73
74 *sep = 0;
75 if (kstrtou16(buf, 0, &band) || kstrtou16(sep + 1, 0, &val))
76 return -EINVAL;
77
78 switch (val) {
79 /*
80 * <band>,0: grab firmware current SER state.
81 * <band>,1: trigger & enable system error L1 recovery.
82 * <band>,2: trigger & enable system error L2 recovery.
83 * <band>,3: trigger & enable system error L3 rx abort.
84 * <band>,4: trigger & enable system error L3 tx abort
85 * <band>,5: trigger & enable system error L3 tx disable.
86 * <band>,6: trigger & enable system error L3 bf recovery.
87 * <band>,7: trigger & enable system error L4 mdp recovery.
88 * <band>,8: trigger & enable system error full recovery.
89 * <band>,9: trigger firmware crash.
90 */
91 case UNI_CMD_SER_QUERY:
92 ret = mt7996_mcu_set_ser(dev, UNI_CMD_SER_QUERY, 0, band);
93 break;
94 case UNI_CMD_SER_SET_RECOVER_L1:
95 case UNI_CMD_SER_SET_RECOVER_L2:
96 case UNI_CMD_SER_SET_RECOVER_L3_RX_ABORT:
97 case UNI_CMD_SER_SET_RECOVER_L3_TX_ABORT:
98 case UNI_CMD_SER_SET_RECOVER_L3_TX_DISABLE:
99 case UNI_CMD_SER_SET_RECOVER_L3_BF:
100 case UNI_CMD_SER_SET_RECOVER_L4_MDP:
101 ret = mt7996_mcu_set_ser(dev, UNI_CMD_SER_SET, BIT(val), band);
102 if (ret)
103 return ret;
104
105 ret = mt7996_mcu_set_ser(dev, UNI_CMD_SER_TRIGGER, val, band);
106 break;
107
108 /* enable full chip reset */
109 case UNI_CMD_SER_SET_RECOVER_FULL:
110 mt76_set(dev, MT_WFDMA0_MCU_HOST_INT_ENA, MT_MCU_CMD_WDT_MASK);
111 dev->recovery.state |= MT_MCU_CMD_WDT_MASK;
112 mt7996_reset(dev);
113 break;
114
115 /* WARNING: trigger firmware crash */
116 case UNI_CMD_SER_SET_SYSTEM_ASSERT:
117 ret = mt7996_mcu_trigger_assert(dev);
118 if (ret)
119 return ret;
120 break;
121 default:
122 break;
123 }
124
125 return ret ? ret : count;
126 }
127
128 static ssize_t
mt7996_sys_recovery_get(struct file * file,char __user * user_buf,size_t count,loff_t * ppos)129 mt7996_sys_recovery_get(struct file *file, char __user *user_buf,
130 size_t count, loff_t *ppos)
131 {
132 struct mt7996_dev *dev = file->private_data;
133 char *buff;
134 int desc = 0;
135 ssize_t ret;
136 static const size_t bufsz = 1024;
137
138 buff = kmalloc(bufsz, GFP_KERNEL);
139 if (!buff)
140 return -ENOMEM;
141
142 /* HELP */
143 desc += scnprintf(buff + desc, bufsz - desc,
144 "Please echo the correct value ...\n");
145 desc += scnprintf(buff + desc, bufsz - desc,
146 "<band>,0: grab firmware transient SER state\n");
147 desc += scnprintf(buff + desc, bufsz - desc,
148 "<band>,1: trigger system error L1 recovery\n");
149 desc += scnprintf(buff + desc, bufsz - desc,
150 "<band>,2: trigger system error L2 recovery\n");
151 desc += scnprintf(buff + desc, bufsz - desc,
152 "<band>,3: trigger system error L3 rx abort\n");
153 desc += scnprintf(buff + desc, bufsz - desc,
154 "<band>,4: trigger system error L3 tx abort\n");
155 desc += scnprintf(buff + desc, bufsz - desc,
156 "<band>,5: trigger system error L3 tx disable\n");
157 desc += scnprintf(buff + desc, bufsz - desc,
158 "<band>,6: trigger system error L3 bf recovery\n");
159 desc += scnprintf(buff + desc, bufsz - desc,
160 "<band>,7: trigger system error L4 mdp recovery\n");
161 desc += scnprintf(buff + desc, bufsz - desc,
162 "<band>,8: trigger system error full recovery\n");
163 desc += scnprintf(buff + desc, bufsz - desc,
164 "<band>,9: trigger firmware crash\n");
165
166 /* SER statistics */
167 desc += scnprintf(buff + desc, bufsz - desc,
168 "\nlet's dump firmware SER statistics...\n");
169 desc += scnprintf(buff + desc, bufsz - desc,
170 "::E R , SER_STATUS = 0x%08x\n",
171 mt76_rr(dev, MT_SWDEF_SER_STATS));
172 desc += scnprintf(buff + desc, bufsz - desc,
173 "::E R , SER_PLE_ERR = 0x%08x\n",
174 mt76_rr(dev, MT_SWDEF_PLE_STATS));
175 desc += scnprintf(buff + desc, bufsz - desc,
176 "::E R , SER_PLE_ERR_1 = 0x%08x\n",
177 mt76_rr(dev, MT_SWDEF_PLE1_STATS));
178 desc += scnprintf(buff + desc, bufsz - desc,
179 "::E R , SER_PLE_ERR_AMSDU = 0x%08x\n",
180 mt76_rr(dev, MT_SWDEF_PLE_AMSDU_STATS));
181 desc += scnprintf(buff + desc, bufsz - desc,
182 "::E R , SER_PSE_ERR = 0x%08x\n",
183 mt76_rr(dev, MT_SWDEF_PSE_STATS));
184 desc += scnprintf(buff + desc, bufsz - desc,
185 "::E R , SER_PSE_ERR_1 = 0x%08x\n",
186 mt76_rr(dev, MT_SWDEF_PSE1_STATS));
187 desc += scnprintf(buff + desc, bufsz - desc,
188 "::E R , SER_LMAC_WISR6_B0 = 0x%08x\n",
189 mt76_rr(dev, MT_SWDEF_LAMC_WISR6_BN0_STATS));
190 desc += scnprintf(buff + desc, bufsz - desc,
191 "::E R , SER_LMAC_WISR6_B1 = 0x%08x\n",
192 mt76_rr(dev, MT_SWDEF_LAMC_WISR6_BN1_STATS));
193 desc += scnprintf(buff + desc, bufsz - desc,
194 "::E R , SER_LMAC_WISR6_B2 = 0x%08x\n",
195 mt76_rr(dev, MT_SWDEF_LAMC_WISR6_BN2_STATS));
196 desc += scnprintf(buff + desc, bufsz - desc,
197 "::E R , SER_LMAC_WISR7_B0 = 0x%08x\n",
198 mt76_rr(dev, MT_SWDEF_LAMC_WISR7_BN0_STATS));
199 desc += scnprintf(buff + desc, bufsz - desc,
200 "::E R , SER_LMAC_WISR7_B1 = 0x%08x\n",
201 mt76_rr(dev, MT_SWDEF_LAMC_WISR7_BN1_STATS));
202 desc += scnprintf(buff + desc, bufsz - desc,
203 "::E R , SER_LMAC_WISR7_B2 = 0x%08x\n",
204 mt76_rr(dev, MT_SWDEF_LAMC_WISR7_BN2_STATS));
205 desc += scnprintf(buff + desc, bufsz - desc,
206 "\nSYS_RESET_COUNT: WM %d, WA %d\n",
207 dev->recovery.wm_reset_count,
208 dev->recovery.wa_reset_count);
209
210 ret = simple_read_from_buffer(user_buf, count, ppos, buff, desc);
211 kfree(buff);
212 return ret;
213 }
214
215 static const struct file_operations mt7996_sys_recovery_ops = {
216 .write = mt7996_sys_recovery_set,
217 .read = mt7996_sys_recovery_get,
218 .open = simple_open,
219 .llseek = default_llseek,
220 };
221
222 static int
mt7996_radar_trigger(void * data,u64 val)223 mt7996_radar_trigger(void *data, u64 val)
224 {
225 #define RADAR_MAIN_CHAIN 1
226 #define RADAR_BACKGROUND 2
227 struct mt7996_dev *dev = data;
228 struct mt7996_phy *phy = mt7996_band_phy(dev, NL80211_BAND_5GHZ);
229 int rdd_idx;
230
231 if (!phy || !val || val > RADAR_BACKGROUND)
232 return -EINVAL;
233
234 if (val == RADAR_BACKGROUND && !dev->rdd2_phy) {
235 dev_err(dev->mt76.dev, "Background radar is not enabled\n");
236 return -EINVAL;
237 }
238
239 rdd_idx = mt7996_get_rdd_idx(phy, val == RADAR_BACKGROUND);
240 if (rdd_idx < 0) {
241 dev_err(dev->mt76.dev, "No RDD found\n");
242 return -EINVAL;
243 }
244
245 return mt7996_mcu_rdd_cmd(dev, RDD_RADAR_EMULATE, rdd_idx, 0);
246 }
247
248 DEFINE_DEBUGFS_ATTRIBUTE(fops_radar_trigger, NULL,
249 mt7996_radar_trigger, "%lld\n");
250
251 static int
mt7996_rdd_monitor(struct seq_file * s,void * data)252 mt7996_rdd_monitor(struct seq_file *s, void *data)
253 {
254 struct mt7996_dev *dev = dev_get_drvdata(s->private);
255 struct cfg80211_chan_def *chandef = &dev->rdd2_chandef;
256 const char *bw;
257 int ret = 0;
258
259 mutex_lock(&dev->mt76.mutex);
260
261 if (!cfg80211_chandef_valid(chandef)) {
262 ret = -EINVAL;
263 goto out;
264 }
265
266 if (!dev->rdd2_phy) {
267 seq_puts(s, "not running\n");
268 goto out;
269 }
270
271 switch (chandef->width) {
272 case NL80211_CHAN_WIDTH_40:
273 bw = "40";
274 break;
275 case NL80211_CHAN_WIDTH_80:
276 bw = "80";
277 break;
278 case NL80211_CHAN_WIDTH_160:
279 bw = "160";
280 break;
281 case NL80211_CHAN_WIDTH_80P80:
282 bw = "80P80";
283 break;
284 default:
285 bw = "20";
286 break;
287 }
288
289 seq_printf(s, "channel %d (%d MHz) width %s MHz center1: %d MHz\n",
290 chandef->chan->hw_value, chandef->chan->center_freq,
291 bw, chandef->center_freq1);
292 out:
293 mutex_unlock(&dev->mt76.mutex);
294
295 return ret;
296 }
297
298 static int
mt7996_fw_debug_wm_set(void * data,u64 val)299 mt7996_fw_debug_wm_set(void *data, u64 val)
300 {
301 struct mt7996_dev *dev = data;
302 enum {
303 DEBUG_TXCMD = 62,
304 DEBUG_CMD_RPT_TX,
305 DEBUG_CMD_RPT_TRIG,
306 DEBUG_SPL,
307 DEBUG_RPT_RX,
308 DEBUG_RPT_RA = 68,
309 } debug;
310 bool tx, rx, en;
311 int ret;
312
313 dev->fw_debug_wm = val ? MCU_FW_LOG_TO_HOST : 0;
314
315 if (dev->fw_debug_bin)
316 val = MCU_FW_LOG_RELAY;
317 else
318 val = dev->fw_debug_wm;
319
320 tx = dev->fw_debug_wm || (dev->fw_debug_bin & BIT(1));
321 rx = dev->fw_debug_wm || (dev->fw_debug_bin & BIT(2));
322 en = dev->fw_debug_wm || (dev->fw_debug_bin & BIT(0));
323
324 ret = mt7996_mcu_fw_log_2_host(dev, MCU_FW_LOG_WM, val);
325 if (ret)
326 return ret;
327
328 for (debug = DEBUG_TXCMD; debug <= DEBUG_RPT_RA; debug++) {
329 if (debug == 67)
330 continue;
331
332 if (debug == DEBUG_RPT_RX)
333 val = en && rx;
334 else
335 val = en && tx;
336
337 ret = mt7996_mcu_fw_dbg_ctrl(dev, debug, val);
338 if (ret)
339 return ret;
340 }
341
342 return 0;
343 }
344
345 static int
mt7996_fw_debug_wm_get(void * data,u64 * val)346 mt7996_fw_debug_wm_get(void *data, u64 *val)
347 {
348 struct mt7996_dev *dev = data;
349
350 *val = dev->fw_debug_wm;
351
352 return 0;
353 }
354
355 DEFINE_DEBUGFS_ATTRIBUTE(fops_fw_debug_wm, mt7996_fw_debug_wm_get,
356 mt7996_fw_debug_wm_set, "%lld\n");
357
358 static int
mt7996_fw_debug_wa_set(void * data,u64 val)359 mt7996_fw_debug_wa_set(void *data, u64 val)
360 {
361 struct mt7996_dev *dev = data;
362 int ret;
363
364 dev->fw_debug_wa = val ? MCU_FW_LOG_TO_HOST : 0;
365
366 ret = mt7996_mcu_fw_log_2_host(dev, MCU_FW_LOG_WA, dev->fw_debug_wa);
367 if (ret)
368 return ret;
369
370 return mt7996_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(SET), MCU_WA_PARAM_PDMA_RX,
371 !!dev->fw_debug_wa, 0);
372 }
373
374 static int
mt7996_fw_debug_wa_get(void * data,u64 * val)375 mt7996_fw_debug_wa_get(void *data, u64 *val)
376 {
377 struct mt7996_dev *dev = data;
378
379 *val = dev->fw_debug_wa;
380
381 return 0;
382 }
383
384 DEFINE_DEBUGFS_ATTRIBUTE(fops_fw_debug_wa, mt7996_fw_debug_wa_get,
385 mt7996_fw_debug_wa_set, "%lld\n");
386
387 static struct dentry *
create_buf_file_cb(const char * filename,struct dentry * parent,umode_t mode,struct rchan_buf * buf,int * is_global)388 create_buf_file_cb(const char *filename, struct dentry *parent, umode_t mode,
389 struct rchan_buf *buf, int *is_global)
390 {
391 struct dentry *f;
392
393 f = debugfs_create_file("fwlog_data", mode, parent, buf,
394 &relay_file_operations);
395 if (IS_ERR(f))
396 return NULL;
397
398 *is_global = 1;
399
400 return f;
401 }
402
403 static int
remove_buf_file_cb(struct dentry * f)404 remove_buf_file_cb(struct dentry *f)
405 {
406 debugfs_remove(f);
407
408 return 0;
409 }
410
411 static int
mt7996_fw_debug_bin_set(void * data,u64 val)412 mt7996_fw_debug_bin_set(void *data, u64 val)
413 {
414 static struct rchan_callbacks relay_cb = {
415 .create_buf_file = create_buf_file_cb,
416 .remove_buf_file = remove_buf_file_cb,
417 };
418 struct mt7996_dev *dev = data;
419
420 if (!dev->relay_fwlog)
421 dev->relay_fwlog = relay_open("fwlog_data", dev->debugfs_dir,
422 1500, 512, &relay_cb, NULL);
423 if (!dev->relay_fwlog)
424 return -ENOMEM;
425
426 dev->fw_debug_bin = val;
427
428 relay_reset(dev->relay_fwlog);
429
430 return mt7996_fw_debug_wm_set(dev, dev->fw_debug_wm);
431 }
432
433 static int
mt7996_fw_debug_bin_get(void * data,u64 * val)434 mt7996_fw_debug_bin_get(void *data, u64 *val)
435 {
436 struct mt7996_dev *dev = data;
437
438 *val = dev->fw_debug_bin;
439
440 return 0;
441 }
442
443 DEFINE_DEBUGFS_ATTRIBUTE(fops_fw_debug_bin, mt7996_fw_debug_bin_get,
444 mt7996_fw_debug_bin_set, "%lld\n");
445
446 static int
mt7996_fw_util_wa_show(struct seq_file * file,void * data)447 mt7996_fw_util_wa_show(struct seq_file *file, void *data)
448 {
449 struct mt7996_dev *dev = file->private;
450
451 if (dev->fw_debug_wa)
452 return mt7996_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(QUERY),
453 MCU_WA_PARAM_CPU_UTIL, 0, 0);
454
455 return 0;
456 }
457
458 DEFINE_SHOW_ATTRIBUTE(mt7996_fw_util_wa);
459
460 static void
mt7996_ampdu_stat_read_phy(struct mt7996_phy * phy,struct seq_file * file)461 mt7996_ampdu_stat_read_phy(struct mt7996_phy *phy, struct seq_file *file)
462 {
463 struct mt7996_dev *dev = phy->dev;
464 int bound[15], range[8], i;
465 u8 band_idx = phy->mt76->band_idx;
466
467 /* Tx ampdu stat */
468 for (i = 0; i < ARRAY_SIZE(range); i++)
469 range[i] = mt76_rr(dev, MT_MIB_ARNG(band_idx, i));
470
471 for (i = 0; i < ARRAY_SIZE(bound); i++)
472 bound[i] = MT_MIB_ARNCR_RANGE(range[i / 2], i % 2) + 1;
473
474 seq_printf(file, "\nPhy %s, Phy band %d\n",
475 wiphy_name(phy->mt76->hw->wiphy), band_idx);
476
477 seq_printf(file, "Length: %8d | ", bound[0]);
478 for (i = 0; i < ARRAY_SIZE(bound) - 1; i++)
479 seq_printf(file, "%3d -%3d | ",
480 bound[i] + 1, bound[i + 1]);
481
482 seq_puts(file, "\nCount: ");
483 for (i = 0; i < ARRAY_SIZE(bound); i++)
484 seq_printf(file, "%8d | ", phy->mt76->aggr_stats[i]);
485 seq_puts(file, "\n");
486
487 seq_printf(file, "BA miss count: %d\n", phy->mib.ba_miss_cnt);
488 }
489
490 static void
mt7996_txbf_stat_read_phy(struct mt7996_phy * phy,struct seq_file * s)491 mt7996_txbf_stat_read_phy(struct mt7996_phy *phy, struct seq_file *s)
492 {
493 struct mt76_mib_stats *mib = &phy->mib;
494 static const char * const bw[] = {
495 "BW20", "BW40", "BW80", "BW160", "BW320"
496 };
497
498 /* Tx Beamformer monitor */
499 seq_puts(s, "\nTx Beamformer applied PPDU counts: ");
500
501 seq_printf(s, "iBF: %d, eBF: %d\n",
502 mib->tx_bf_ibf_ppdu_cnt,
503 mib->tx_bf_ebf_ppdu_cnt);
504
505 /* Tx Beamformer Rx feedback monitor */
506 seq_puts(s, "Tx Beamformer Rx feedback statistics: ");
507
508 seq_printf(s, "All: %d, EHT: %d, HE: %d, VHT: %d, HT: %d, ",
509 mib->tx_bf_rx_fb_all_cnt,
510 mib->tx_bf_rx_fb_eht_cnt,
511 mib->tx_bf_rx_fb_he_cnt,
512 mib->tx_bf_rx_fb_vht_cnt,
513 mib->tx_bf_rx_fb_ht_cnt);
514
515 seq_printf(s, "%s, NC: %d, NR: %d\n",
516 bw[mib->tx_bf_rx_fb_bw],
517 mib->tx_bf_rx_fb_nc_cnt,
518 mib->tx_bf_rx_fb_nr_cnt);
519
520 /* Tx Beamformee Rx NDPA & Tx feedback report */
521 seq_printf(s, "Tx Beamformee successful feedback frames: %d\n",
522 mib->tx_bf_fb_cpl_cnt);
523 seq_printf(s, "Tx Beamformee feedback triggered counts: %d\n",
524 mib->tx_bf_fb_trig_cnt);
525
526 /* Tx SU & MU counters */
527 seq_printf(s, "Tx multi-user Beamforming counts: %d\n",
528 mib->tx_mu_bf_cnt);
529 seq_printf(s, "Tx multi-user MPDU counts: %d\n", mib->tx_mu_mpdu_cnt);
530 seq_printf(s, "Tx multi-user successful MPDU counts: %d\n",
531 mib->tx_mu_acked_mpdu_cnt);
532 seq_printf(s, "Tx single-user successful MPDU counts: %d\n",
533 mib->tx_su_acked_mpdu_cnt);
534
535 seq_puts(s, "\n");
536 }
537
538 static void
mt7996_tx_stats_show_phy(struct seq_file * file,struct mt7996_phy * phy)539 mt7996_tx_stats_show_phy(struct seq_file *file, struct mt7996_phy *phy)
540 {
541 struct mt76_mib_stats *mib = &phy->mib;
542 u32 attempts, success, per;
543 int i;
544
545 mt7996_mac_update_stats(phy);
546 mt7996_ampdu_stat_read_phy(phy, file);
547
548 attempts = mib->tx_mpdu_attempts_cnt;
549 success = mib->tx_mpdu_success_cnt;
550 per = attempts ? 100 - success * 100 / attempts : 100;
551 seq_printf(file, "Tx attempts: %8u (MPDUs)\n", attempts);
552 seq_printf(file, "Tx success: %8u (MPDUs)\n", success);
553 seq_printf(file, "Tx PER: %u%%\n", per);
554
555 mt7996_txbf_stat_read_phy(phy, file);
556
557 /* Tx amsdu info */
558 seq_puts(file, "Tx MSDU statistics:\n");
559 for (i = 0; i < ARRAY_SIZE(mib->tx_amsdu); i++) {
560 seq_printf(file, "AMSDU pack count of %d MSDU in TXD: %8d ",
561 i + 1, mib->tx_amsdu[i]);
562 if (mib->tx_amsdu_cnt)
563 seq_printf(file, "(%3d%%)\n",
564 mib->tx_amsdu[i] * 100 / mib->tx_amsdu_cnt);
565 else
566 seq_puts(file, "\n");
567 }
568 }
569
570 static int
mt7996_tx_stats_show(struct seq_file * file,void * data)571 mt7996_tx_stats_show(struct seq_file *file, void *data)
572 {
573 struct mt7996_dev *dev = file->private;
574 struct mt7996_phy *phy = &dev->phy;
575
576 mutex_lock(&dev->mt76.mutex);
577
578 mt7996_tx_stats_show_phy(file, phy);
579 phy = mt7996_phy2(dev);
580 if (phy)
581 mt7996_tx_stats_show_phy(file, phy);
582 phy = mt7996_phy3(dev);
583 if (phy)
584 mt7996_tx_stats_show_phy(file, phy);
585
586 mutex_unlock(&dev->mt76.mutex);
587
588 return 0;
589 }
590
591 DEFINE_SHOW_ATTRIBUTE(mt7996_tx_stats);
592
593 static void
mt7996_hw_queue_read(struct seq_file * s,u32 size,const struct hw_queue_map * map)594 mt7996_hw_queue_read(struct seq_file *s, u32 size,
595 const struct hw_queue_map *map)
596 {
597 struct mt7996_phy *phy = s->private;
598 struct mt7996_dev *dev = phy->dev;
599 u32 i, val;
600
601 val = mt76_rr(dev, MT_FL_Q_EMPTY);
602 for (i = 0; i < size; i++) {
603 u32 ctrl, head, tail, queued;
604
605 if (val & BIT(map[i].index))
606 continue;
607
608 ctrl = BIT(31) | (map[i].pid << 10) | ((u32)map[i].qid << 24);
609 mt76_wr(dev, MT_FL_Q0_CTRL, ctrl);
610
611 head = mt76_get_field(dev, MT_FL_Q2_CTRL,
612 GENMASK(11, 0));
613 tail = mt76_get_field(dev, MT_FL_Q2_CTRL,
614 GENMASK(27, 16));
615 queued = mt76_get_field(dev, MT_FL_Q3_CTRL,
616 GENMASK(11, 0));
617
618 seq_printf(s, "\t%s: ", map[i].name);
619 seq_printf(s, "queued:0x%03x head:0x%03x tail:0x%03x\n",
620 queued, head, tail);
621 }
622 }
623
624 static void
mt7996_sta_hw_queue_read(void * data,struct ieee80211_sta * sta)625 mt7996_sta_hw_queue_read(void *data, struct ieee80211_sta *sta)
626 {
627 struct mt7996_sta *msta = (struct mt7996_sta *)sta->drv_priv;
628 struct mt7996_vif *mvif = msta->vif;
629 struct mt7996_dev *dev = mvif->deflink.phy->dev;
630 struct ieee80211_link_sta *link_sta;
631 struct seq_file *s = data;
632 struct ieee80211_vif *vif;
633 unsigned int link_id;
634
635 vif = container_of((void *)mvif, struct ieee80211_vif, drv_priv);
636
637 rcu_read_lock();
638
639 for_each_sta_active_link(vif, sta, link_sta, link_id) {
640 struct mt7996_sta_link *msta_link;
641 struct mt76_vif_link *mlink;
642 u8 ac;
643
644 mlink = rcu_dereference(mvif->mt76.link[link_id]);
645 if (!mlink)
646 continue;
647
648 msta_link = rcu_dereference(msta->link[link_id]);
649 if (!msta_link)
650 continue;
651
652 for (ac = 0; ac < 4; ac++) {
653 u32 idx = msta_link->wcid.idx >> 5, qlen, ctrl, val;
654 u8 offs = msta_link->wcid.idx & GENMASK(4, 0);
655
656 ctrl = BIT(31) | BIT(11) | (ac << 24);
657 val = mt76_rr(dev, MT_PLE_AC_QEMPTY(ac, idx));
658
659 if (val & BIT(offs))
660 continue;
661
662 mt76_wr(dev,
663 MT_FL_Q0_CTRL, ctrl | msta_link->wcid.idx);
664 qlen = mt76_get_field(dev, MT_FL_Q3_CTRL,
665 GENMASK(11, 0));
666 seq_printf(s, "\tSTA %pM wcid %d: AC%d%d queued:%d\n",
667 sta->addr, msta_link->wcid.idx,
668 mlink->wmm_idx, ac, qlen);
669 }
670 }
671
672 rcu_read_unlock();
673 }
674
675 static int
mt7996_hw_queues_show(struct seq_file * file,void * data)676 mt7996_hw_queues_show(struct seq_file *file, void *data)
677 {
678 struct mt7996_dev *dev = file->private;
679 struct mt7996_phy *phy = &dev->phy;
680 static const struct hw_queue_map ple_queue_map[] = {
681 { "CPU_Q0", 0, 1, MT_CTX0 },
682 { "CPU_Q1", 1, 1, MT_CTX0 + 1 },
683 { "CPU_Q2", 2, 1, MT_CTX0 + 2 },
684 { "CPU_Q3", 3, 1, MT_CTX0 + 3 },
685 { "ALTX_Q0", 8, 2, MT_LMAC_ALTX0 },
686 { "BMC_Q0", 9, 2, MT_LMAC_BMC0 },
687 { "BCN_Q0", 10, 2, MT_LMAC_BCN0 },
688 { "PSMP_Q0", 11, 2, MT_LMAC_PSMP0 },
689 { "ALTX_Q1", 12, 2, MT_LMAC_ALTX0 + 4 },
690 { "BMC_Q1", 13, 2, MT_LMAC_BMC0 + 4 },
691 { "BCN_Q1", 14, 2, MT_LMAC_BCN0 + 4 },
692 { "PSMP_Q1", 15, 2, MT_LMAC_PSMP0 + 4 },
693 };
694 static const struct hw_queue_map pse_queue_map[] = {
695 { "CPU Q0", 0, 1, MT_CTX0 },
696 { "CPU Q1", 1, 1, MT_CTX0 + 1 },
697 { "CPU Q2", 2, 1, MT_CTX0 + 2 },
698 { "CPU Q3", 3, 1, MT_CTX0 + 3 },
699 { "HIF_Q0", 8, 0, MT_HIF0 },
700 { "HIF_Q1", 9, 0, MT_HIF0 + 1 },
701 { "HIF_Q2", 10, 0, MT_HIF0 + 2 },
702 { "HIF_Q3", 11, 0, MT_HIF0 + 3 },
703 { "HIF_Q4", 12, 0, MT_HIF0 + 4 },
704 { "HIF_Q5", 13, 0, MT_HIF0 + 5 },
705 { "LMAC_Q", 16, 2, 0 },
706 { "MDP_TXQ", 17, 2, 1 },
707 { "MDP_RXQ", 18, 2, 2 },
708 { "SEC_TXQ", 19, 2, 3 },
709 { "SEC_RXQ", 20, 2, 4 },
710 };
711 u32 val, head, tail;
712
713 /* ple queue */
714 val = mt76_rr(dev, MT_PLE_FREEPG_CNT);
715 head = mt76_get_field(dev, MT_PLE_FREEPG_HEAD_TAIL, GENMASK(11, 0));
716 tail = mt76_get_field(dev, MT_PLE_FREEPG_HEAD_TAIL, GENMASK(27, 16));
717 seq_puts(file, "PLE page info:\n");
718 seq_printf(file,
719 "\tTotal free page: 0x%08x head: 0x%03x tail: 0x%03x\n",
720 val, head, tail);
721
722 val = mt76_rr(dev, MT_PLE_PG_HIF_GROUP);
723 head = mt76_get_field(dev, MT_PLE_HIF_PG_INFO, GENMASK(11, 0));
724 tail = mt76_get_field(dev, MT_PLE_HIF_PG_INFO, GENMASK(27, 16));
725 seq_printf(file, "\tHIF free page: 0x%03x res: 0x%03x used: 0x%03x\n",
726 val, head, tail);
727
728 seq_puts(file, "PLE non-empty queue info:\n");
729 mt7996_hw_queue_read(file, ARRAY_SIZE(ple_queue_map),
730 &ple_queue_map[0]);
731
732 /* iterate per-sta ple queue */
733 ieee80211_iterate_stations_atomic(phy->mt76->hw,
734 mt7996_sta_hw_queue_read, file);
735 phy = mt7996_phy2(dev);
736 if (phy)
737 ieee80211_iterate_stations_atomic(phy->mt76->hw,
738 mt7996_sta_hw_queue_read, file);
739 phy = mt7996_phy3(dev);
740 if (phy)
741 ieee80211_iterate_stations_atomic(phy->mt76->hw,
742 mt7996_sta_hw_queue_read, file);
743
744 /* pse queue */
745 seq_puts(file, "PSE non-empty queue info:\n");
746 mt7996_hw_queue_read(file, ARRAY_SIZE(pse_queue_map),
747 &pse_queue_map[0]);
748
749 return 0;
750 }
751
752 DEFINE_SHOW_ATTRIBUTE(mt7996_hw_queues);
753
754 static int
mt7996_xmit_queues_show(struct seq_file * file,void * data)755 mt7996_xmit_queues_show(struct seq_file *file, void *data)
756 {
757 struct mt7996_dev *dev = file->private;
758 struct mt7996_phy *phy;
759 struct {
760 struct mt76_queue *q;
761 char *queue;
762 } queue_map[] = {
763 { dev->mphy.q_tx[MT_TXQ_BE], " MAIN0" },
764 { NULL, " MAIN1" },
765 { NULL, " MAIN2" },
766 { dev->mt76.q_mcu[MT_MCUQ_WM], " MCUWM" },
767 { dev->mt76.q_mcu[MT_MCUQ_WA], " MCUWA" },
768 { dev->mt76.q_mcu[MT_MCUQ_FWDL], "MCUFWDL" },
769 };
770 int i;
771
772 phy = mt7996_phy2(dev);
773 if (phy)
774 queue_map[1].q = phy->mt76->q_tx[MT_TXQ_BE];
775
776 phy = mt7996_phy3(dev);
777 if (phy)
778 queue_map[2].q = phy->mt76->q_tx[MT_TXQ_BE];
779
780 seq_puts(file, " queue | hw-queued | head | tail |\n");
781 for (i = 0; i < ARRAY_SIZE(queue_map); i++) {
782 struct mt76_queue *q = queue_map[i].q;
783
784 if (!q)
785 continue;
786
787 seq_printf(file, " %s | %9d | %9d | %9d |\n",
788 queue_map[i].queue, q->queued, q->head,
789 q->tail);
790 }
791
792 return 0;
793 }
794
795 DEFINE_SHOW_ATTRIBUTE(mt7996_xmit_queues);
796
797 static int
mt7996_twt_stats(struct seq_file * s,void * data)798 mt7996_twt_stats(struct seq_file *s, void *data)
799 {
800 struct mt7996_dev *dev = dev_get_drvdata(s->private);
801 struct mt7996_twt_flow *iter;
802
803 rcu_read_lock();
804
805 seq_puts(s, " wcid | id | flags | exp | mantissa");
806 seq_puts(s, " | duration | tsf |\n");
807 list_for_each_entry_rcu(iter, &dev->twt_list, list)
808 seq_printf(s,
809 "%9d | %8d | %5c%c%c%c | %8d | %8d | %8d | %14lld |\n",
810 iter->wcid, iter->id,
811 iter->sched ? 's' : 'u',
812 iter->protection ? 'p' : '-',
813 iter->trigger ? 't' : '-',
814 iter->flowtype ? '-' : 'a',
815 iter->exp, iter->mantissa,
816 iter->duration, iter->tsf);
817
818 rcu_read_unlock();
819
820 return 0;
821 }
822
823 /* The index of RF registers use the generic regidx, combined with two parts:
824 * WF selection [31:24] and offset [23:0].
825 */
826 static int
mt7996_rf_regval_get(void * data,u64 * val)827 mt7996_rf_regval_get(void *data, u64 *val)
828 {
829 struct mt7996_dev *dev = data;
830 u32 regval;
831 int ret;
832
833 ret = mt7996_mcu_rf_regval(dev, dev->mt76.debugfs_reg, ®val, false);
834 if (ret)
835 return ret;
836
837 *val = regval;
838
839 return 0;
840 }
841
842 static int
mt7996_rf_regval_set(void * data,u64 val)843 mt7996_rf_regval_set(void *data, u64 val)
844 {
845 struct mt7996_dev *dev = data;
846 u32 val32 = val;
847
848 return mt7996_mcu_rf_regval(dev, dev->mt76.debugfs_reg, &val32, true);
849 }
850
851 DEFINE_DEBUGFS_ATTRIBUTE(fops_rf_regval, mt7996_rf_regval_get,
852 mt7996_rf_regval_set, "0x%08llx\n");
853
mt7996_init_debugfs(struct mt7996_dev * dev)854 int mt7996_init_debugfs(struct mt7996_dev *dev)
855 {
856 struct dentry *dir;
857
858 dir = mt76_register_debugfs_fops(&dev->mphy, NULL);
859 if (!dir)
860 return -ENOMEM;
861
862 debugfs_create_file("hw-queues", 0400, dir, dev,
863 &mt7996_hw_queues_fops);
864 debugfs_create_file("xmit-queues", 0400, dir, dev,
865 &mt7996_xmit_queues_fops);
866 debugfs_create_file("tx_stats", 0400, dir, dev, &mt7996_tx_stats_fops);
867 debugfs_create_file("sys_recovery", 0600, dir, dev,
868 &mt7996_sys_recovery_ops);
869 debugfs_create_file("fw_debug_wm", 0600, dir, dev, &fops_fw_debug_wm);
870 debugfs_create_file("fw_debug_wa", 0600, dir, dev, &fops_fw_debug_wa);
871 debugfs_create_file("fw_debug_bin", 0600, dir, dev, &fops_fw_debug_bin);
872 /* TODO: wm fw cpu utilization */
873 debugfs_create_file("fw_util_wa", 0400, dir, dev,
874 &mt7996_fw_util_wa_fops);
875 debugfs_create_file("implicit_txbf", 0600, dir, dev,
876 &fops_implicit_txbf);
877 debugfs_create_devm_seqfile(dev->mt76.dev, "twt_stats", dir,
878 mt7996_twt_stats);
879 debugfs_create_file("rf_regval", 0600, dir, dev, &fops_rf_regval);
880
881 debugfs_create_u32("dfs_hw_pattern", 0400, dir, &dev->hw_pattern);
882 debugfs_create_file("radar_trigger", 0200, dir, dev,
883 &fops_radar_trigger);
884 debugfs_create_devm_seqfile(dev->mt76.dev, "rdd_monitor", dir,
885 mt7996_rdd_monitor);
886
887 dev->debugfs_dir = dir;
888
889 return 0;
890 }
891
892 static void
mt7996_debugfs_write_fwlog(struct mt7996_dev * dev,const void * hdr,int hdrlen,const void * data,int len)893 mt7996_debugfs_write_fwlog(struct mt7996_dev *dev, const void *hdr, int hdrlen,
894 const void *data, int len)
895 {
896 static DEFINE_SPINLOCK(lock);
897 unsigned long flags;
898 void *dest;
899
900 spin_lock_irqsave(&lock, flags);
901 dest = relay_reserve(dev->relay_fwlog, hdrlen + len + 4);
902 if (dest) {
903 *(u32 *)dest = hdrlen + len;
904 dest += 4;
905
906 if (hdrlen) {
907 memcpy(dest, hdr, hdrlen);
908 dest += hdrlen;
909 }
910
911 memcpy(dest, data, len);
912 relay_flush(dev->relay_fwlog);
913 }
914 spin_unlock_irqrestore(&lock, flags);
915 }
916
mt7996_debugfs_rx_fw_monitor(struct mt7996_dev * dev,const void * data,int len)917 void mt7996_debugfs_rx_fw_monitor(struct mt7996_dev *dev, const void *data, int len)
918 {
919 struct {
920 __le32 magic;
921 u8 version;
922 u8 _rsv;
923 __le16 serial_id;
924 __le32 timestamp;
925 __le16 msg_type;
926 __le16 len;
927 } hdr = {
928 .version = 0x1,
929 .magic = cpu_to_le32(FW_BIN_LOG_MAGIC),
930 .msg_type = cpu_to_le16(PKT_TYPE_RX_FW_MONITOR),
931 };
932
933 if (!dev->relay_fwlog)
934 return;
935
936 hdr.serial_id = cpu_to_le16(dev->fw_debug_seq++);
937 hdr.timestamp = cpu_to_le32(mt76_rr(dev, MT_LPON_FRCR(0)));
938 hdr.len = *(__le16 *)data;
939 mt7996_debugfs_write_fwlog(dev, &hdr, sizeof(hdr), data, len);
940 }
941
mt7996_debugfs_rx_log(struct mt7996_dev * dev,const void * data,int len)942 bool mt7996_debugfs_rx_log(struct mt7996_dev *dev, const void *data, int len)
943 {
944 if (get_unaligned_le32(data) != FW_BIN_LOG_MAGIC)
945 return false;
946
947 if (dev->relay_fwlog)
948 mt7996_debugfs_write_fwlog(dev, NULL, 0, data, len);
949
950 return true;
951 }
952
953 #ifdef CONFIG_MAC80211_DEBUGFS
954 /** per-station debugfs **/
955
mt7996_sta_fixed_rate_set(struct file * file,const char __user * user_buf,size_t count,loff_t * ppos)956 static ssize_t mt7996_sta_fixed_rate_set(struct file *file,
957 const char __user *user_buf,
958 size_t count, loff_t *ppos)
959 {
960 #define SHORT_PREAMBLE 0
961 #define LONG_PREAMBLE 1
962 struct ieee80211_sta *sta = file->private_data;
963 struct mt7996_sta *msta = (struct mt7996_sta *)sta->drv_priv;
964 struct mt7996_dev *dev = msta->vif->deflink.phy->dev;
965 struct mt7996_sta_link *msta_link = &msta->deflink;
966 struct ra_rate phy = {};
967 char buf[100];
968 int ret;
969 u16 gi, ltf;
970
971 if (count >= sizeof(buf))
972 return -EINVAL;
973
974 if (copy_from_user(buf, user_buf, count))
975 return -EFAULT;
976
977 if (count && buf[count - 1] == '\n')
978 buf[count - 1] = '\0';
979 else
980 buf[count] = '\0';
981
982 /* mode - cck: 0, ofdm: 1, ht: 2, gf: 3, vht: 4, he_su: 8, he_er: 9 EHT: 15
983 * bw - bw20: 0, bw40: 1, bw80: 2, bw160: 3, BW320: 4
984 * nss - vht: 1~4, he: 1~4, eht: 1~4, others: ignore
985 * mcs - cck: 0~4, ofdm: 0~7, ht: 0~32, vht: 0~9, he_su: 0~11, he_er: 0~2, eht: 0~13
986 * gi - (ht/vht) lgi: 0, sgi: 1; (he) 0.8us: 0, 1.6us: 1, 3.2us: 2
987 * preamble - short: 1, long: 0
988 * ldpc - off: 0, on: 1
989 * stbc - off: 0, on: 1
990 * ltf - 1xltf: 0, 2xltf: 1, 4xltf: 2
991 */
992 if (sscanf(buf, "%hhu %hhu %hhu %hhu %hu %hhu %hhu %hhu %hhu %hu",
993 &phy.mode, &phy.bw, &phy.mcs, &phy.nss, &gi,
994 &phy.preamble, &phy.stbc, &phy.ldpc, &phy.spe, <f) != 10) {
995 dev_warn(dev->mt76.dev,
996 "format: Mode BW MCS NSS GI Preamble STBC LDPC SPE ltf\n");
997 goto out;
998 }
999
1000 phy.wlan_idx = cpu_to_le16(msta_link->wcid.idx);
1001 phy.gi = cpu_to_le16(gi);
1002 phy.ltf = cpu_to_le16(ltf);
1003 phy.ldpc = phy.ldpc ? 7 : 0;
1004 phy.preamble = phy.preamble ? SHORT_PREAMBLE : LONG_PREAMBLE;
1005
1006 ret = mt7996_mcu_set_fixed_rate_ctrl(dev, &phy, 0);
1007 if (ret)
1008 return -EFAULT;
1009
1010 out:
1011 return count;
1012 }
1013
1014 static const struct file_operations fops_fixed_rate = {
1015 .write = mt7996_sta_fixed_rate_set,
1016 .open = simple_open,
1017 .owner = THIS_MODULE,
1018 .llseek = default_llseek,
1019 };
1020
1021 static int
mt7996_queues_show(struct seq_file * s,void * data)1022 mt7996_queues_show(struct seq_file *s, void *data)
1023 {
1024 struct ieee80211_sta *sta = s->private;
1025
1026 mt7996_sta_hw_queue_read(s, sta);
1027
1028 return 0;
1029 }
1030
1031 DEFINE_SHOW_ATTRIBUTE(mt7996_queues);
1032
mt7996_sta_add_debugfs(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_sta * sta,struct dentry * dir)1033 void mt7996_sta_add_debugfs(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1034 struct ieee80211_sta *sta, struct dentry *dir)
1035 {
1036 debugfs_create_file("fixed_rate", 0600, dir, sta, &fops_fixed_rate);
1037 debugfs_create_file("hw-queues", 0400, dir, sta, &mt7996_queues_fops);
1038 }
1039
1040 #endif
1041