1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2015 Linaro Ltd.
4 * Author: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
5 */
6
7 #include <linux/clk.h>
8 #include <linux/cpu.h>
9 #include <linux/cpufreq.h>
10 #include <linux/cpumask.h>
11 #include <linux/minmax.h>
12 #include <linux/module.h>
13 #include <linux/of.h>
14 #include <linux/of_platform.h>
15 #include <linux/platform_device.h>
16 #include <linux/pm_opp.h>
17 #include <linux/regulator/consumer.h>
18
19 struct mtk_cpufreq_platform_data {
20 int min_volt_shift;
21 int max_volt_shift;
22 int proc_max_volt;
23 int sram_min_volt;
24 int sram_max_volt;
25 bool ccifreq_supported;
26 };
27
28 /*
29 * The struct mtk_cpu_dvfs_info holds necessary information for doing CPU DVFS
30 * on each CPU power/clock domain of Mediatek SoCs. Each CPU cluster in
31 * Mediatek SoCs has two voltage inputs, Vproc and Vsram. In some cases the two
32 * voltage inputs need to be controlled under a hardware limitation:
33 * 100mV < Vsram - Vproc < 200mV
34 *
35 * When scaling the clock frequency of a CPU clock domain, the clock source
36 * needs to be switched to another stable PLL clock temporarily until
37 * the original PLL becomes stable at target frequency.
38 */
39 struct mtk_cpu_dvfs_info {
40 struct cpumask cpus;
41 struct device *cpu_dev;
42 struct device *cci_dev;
43 struct regulator *proc_reg;
44 struct regulator *sram_reg;
45 struct clk *cpu_clk;
46 struct clk *inter_clk;
47 struct list_head list_head;
48 int intermediate_voltage;
49 bool need_voltage_tracking;
50 int vproc_on_boot;
51 int pre_vproc;
52 /* Avoid race condition for regulators between notify and policy */
53 struct mutex reg_lock;
54 struct notifier_block opp_nb;
55 unsigned int opp_cpu;
56 unsigned long current_freq;
57 const struct mtk_cpufreq_platform_data *soc_data;
58 int vtrack_max;
59 bool ccifreq_bound;
60 };
61
62 static struct platform_device *cpufreq_pdev;
63
64 static LIST_HEAD(dvfs_info_list);
65
mtk_cpu_dvfs_info_lookup(int cpu)66 static struct mtk_cpu_dvfs_info *mtk_cpu_dvfs_info_lookup(int cpu)
67 {
68 struct mtk_cpu_dvfs_info *info;
69
70 list_for_each_entry(info, &dvfs_info_list, list_head) {
71 if (cpumask_test_cpu(cpu, &info->cpus))
72 return info;
73 }
74
75 return NULL;
76 }
77
mtk_cpufreq_voltage_tracking(struct mtk_cpu_dvfs_info * info,int new_vproc)78 static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_dvfs_info *info,
79 int new_vproc)
80 {
81 const struct mtk_cpufreq_platform_data *soc_data = info->soc_data;
82 struct regulator *proc_reg = info->proc_reg;
83 struct regulator *sram_reg = info->sram_reg;
84 int pre_vproc, pre_vsram, new_vsram, vsram, vproc, ret;
85 int retry = info->vtrack_max;
86
87 pre_vproc = regulator_get_voltage(proc_reg);
88 if (pre_vproc < 0) {
89 dev_err(info->cpu_dev,
90 "invalid Vproc value: %d\n", pre_vproc);
91 return pre_vproc;
92 }
93
94 pre_vsram = regulator_get_voltage(sram_reg);
95 if (pre_vsram < 0) {
96 dev_err(info->cpu_dev, "invalid Vsram value: %d\n", pre_vsram);
97 return pre_vsram;
98 }
99
100 new_vsram = clamp(new_vproc + soc_data->min_volt_shift,
101 soc_data->sram_min_volt, soc_data->sram_max_volt);
102
103 do {
104 if (pre_vproc <= new_vproc) {
105 vsram = clamp(pre_vproc + soc_data->max_volt_shift,
106 soc_data->sram_min_volt, new_vsram);
107 ret = regulator_set_voltage(sram_reg, vsram,
108 soc_data->sram_max_volt);
109
110 if (ret)
111 return ret;
112
113 if (vsram == soc_data->sram_max_volt ||
114 new_vsram == soc_data->sram_min_volt)
115 vproc = new_vproc;
116 else
117 vproc = vsram - soc_data->min_volt_shift;
118
119 ret = regulator_set_voltage(proc_reg, vproc,
120 soc_data->proc_max_volt);
121 if (ret) {
122 regulator_set_voltage(sram_reg, pre_vsram,
123 soc_data->sram_max_volt);
124 return ret;
125 }
126 } else {
127 vproc = max(new_vproc,
128 pre_vsram - soc_data->max_volt_shift);
129 ret = regulator_set_voltage(proc_reg, vproc,
130 soc_data->proc_max_volt);
131 if (ret)
132 return ret;
133
134 if (vproc == new_vproc)
135 vsram = new_vsram;
136 else
137 vsram = max(new_vsram,
138 vproc + soc_data->min_volt_shift);
139
140 ret = regulator_set_voltage(sram_reg, vsram,
141 soc_data->sram_max_volt);
142 if (ret) {
143 regulator_set_voltage(proc_reg, pre_vproc,
144 soc_data->proc_max_volt);
145 return ret;
146 }
147 }
148
149 pre_vproc = vproc;
150 pre_vsram = vsram;
151
152 if (--retry < 0) {
153 dev_err(info->cpu_dev,
154 "over loop count, failed to set voltage\n");
155 return -EINVAL;
156 }
157 } while (vproc != new_vproc || vsram != new_vsram);
158
159 return 0;
160 }
161
mtk_cpufreq_set_voltage(struct mtk_cpu_dvfs_info * info,int vproc)162 static int mtk_cpufreq_set_voltage(struct mtk_cpu_dvfs_info *info, int vproc)
163 {
164 const struct mtk_cpufreq_platform_data *soc_data = info->soc_data;
165 int ret;
166
167 if (info->need_voltage_tracking)
168 ret = mtk_cpufreq_voltage_tracking(info, vproc);
169 else
170 ret = regulator_set_voltage(info->proc_reg, vproc,
171 soc_data->proc_max_volt);
172 if (!ret)
173 info->pre_vproc = vproc;
174
175 return ret;
176 }
177
is_ccifreq_ready(struct mtk_cpu_dvfs_info * info)178 static bool is_ccifreq_ready(struct mtk_cpu_dvfs_info *info)
179 {
180 struct device_link *sup_link;
181
182 if (info->ccifreq_bound)
183 return true;
184
185 sup_link = device_link_add(info->cpu_dev, info->cci_dev,
186 DL_FLAG_AUTOREMOVE_CONSUMER);
187 if (!sup_link) {
188 dev_err(info->cpu_dev, "cpu%d: sup_link is NULL\n", info->opp_cpu);
189 return false;
190 }
191
192 if (sup_link->supplier->links.status != DL_DEV_DRIVER_BOUND)
193 return false;
194
195 info->ccifreq_bound = true;
196
197 return true;
198 }
199
mtk_cpufreq_set_target(struct cpufreq_policy * policy,unsigned int index)200 static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
201 unsigned int index)
202 {
203 struct cpufreq_frequency_table *freq_table = policy->freq_table;
204 struct clk *cpu_clk = policy->clk;
205 struct clk *armpll = clk_get_parent(cpu_clk);
206 struct mtk_cpu_dvfs_info *info = policy->driver_data;
207 struct device *cpu_dev = info->cpu_dev;
208 struct dev_pm_opp *opp;
209 long freq_hz, pre_freq_hz;
210 int vproc, pre_vproc, inter_vproc, target_vproc, ret;
211
212 inter_vproc = info->intermediate_voltage;
213
214 pre_freq_hz = clk_get_rate(cpu_clk);
215
216 mutex_lock(&info->reg_lock);
217
218 if (unlikely(info->pre_vproc <= 0))
219 pre_vproc = regulator_get_voltage(info->proc_reg);
220 else
221 pre_vproc = info->pre_vproc;
222
223 if (pre_vproc < 0) {
224 dev_err(cpu_dev, "invalid Vproc value: %d\n", pre_vproc);
225 ret = pre_vproc;
226 goto out;
227 }
228
229 freq_hz = freq_table[index].frequency * 1000;
230
231 opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz);
232 if (IS_ERR(opp)) {
233 dev_err(cpu_dev, "cpu%d: failed to find OPP for %ld\n",
234 policy->cpu, freq_hz);
235 ret = PTR_ERR(opp);
236 goto out;
237 }
238 vproc = dev_pm_opp_get_voltage(opp);
239 dev_pm_opp_put(opp);
240
241 /*
242 * If MediaTek cci is supported but is not ready, we will use the value
243 * of max(target cpu voltage, booting voltage) to prevent high freqeuncy
244 * low voltage crash.
245 */
246 if (info->soc_data->ccifreq_supported && !is_ccifreq_ready(info))
247 vproc = max(vproc, info->vproc_on_boot);
248
249 /*
250 * If the new voltage or the intermediate voltage is higher than the
251 * current voltage, scale up voltage first.
252 */
253 target_vproc = max(inter_vproc, vproc);
254 if (pre_vproc <= target_vproc) {
255 ret = mtk_cpufreq_set_voltage(info, target_vproc);
256 if (ret) {
257 dev_err(cpu_dev,
258 "cpu%d: failed to scale up voltage!\n", policy->cpu);
259 mtk_cpufreq_set_voltage(info, pre_vproc);
260 goto out;
261 }
262 }
263
264 /* Reparent the CPU clock to intermediate clock. */
265 ret = clk_set_parent(cpu_clk, info->inter_clk);
266 if (ret) {
267 dev_err(cpu_dev,
268 "cpu%d: failed to re-parent cpu clock!\n", policy->cpu);
269 mtk_cpufreq_set_voltage(info, pre_vproc);
270 goto out;
271 }
272
273 /* Set the original PLL to target rate. */
274 ret = clk_set_rate(armpll, freq_hz);
275 if (ret) {
276 dev_err(cpu_dev,
277 "cpu%d: failed to scale cpu clock rate!\n", policy->cpu);
278 clk_set_parent(cpu_clk, armpll);
279 mtk_cpufreq_set_voltage(info, pre_vproc);
280 goto out;
281 }
282
283 /* Set parent of CPU clock back to the original PLL. */
284 ret = clk_set_parent(cpu_clk, armpll);
285 if (ret) {
286 dev_err(cpu_dev,
287 "cpu%d: failed to re-parent cpu clock!\n", policy->cpu);
288 mtk_cpufreq_set_voltage(info, inter_vproc);
289 goto out;
290 }
291
292 /*
293 * If the new voltage is lower than the intermediate voltage or the
294 * original voltage, scale down to the new voltage.
295 */
296 if (vproc < inter_vproc || vproc < pre_vproc) {
297 ret = mtk_cpufreq_set_voltage(info, vproc);
298 if (ret) {
299 dev_err(cpu_dev,
300 "cpu%d: failed to scale down voltage!\n", policy->cpu);
301 clk_set_parent(cpu_clk, info->inter_clk);
302 clk_set_rate(armpll, pre_freq_hz);
303 clk_set_parent(cpu_clk, armpll);
304 goto out;
305 }
306 }
307
308 info->current_freq = freq_hz;
309
310 out:
311 mutex_unlock(&info->reg_lock);
312
313 return ret;
314 }
315
mtk_cpufreq_opp_notifier(struct notifier_block * nb,unsigned long event,void * data)316 static int mtk_cpufreq_opp_notifier(struct notifier_block *nb,
317 unsigned long event, void *data)
318 {
319 struct dev_pm_opp *opp = data;
320 struct dev_pm_opp *new_opp;
321 struct mtk_cpu_dvfs_info *info;
322 unsigned long freq, volt;
323 int ret = 0;
324
325 info = container_of(nb, struct mtk_cpu_dvfs_info, opp_nb);
326
327 if (event == OPP_EVENT_ADJUST_VOLTAGE) {
328 freq = dev_pm_opp_get_freq(opp);
329
330 mutex_lock(&info->reg_lock);
331 if (info->current_freq == freq) {
332 volt = dev_pm_opp_get_voltage(opp);
333 ret = mtk_cpufreq_set_voltage(info, volt);
334 if (ret)
335 dev_err(info->cpu_dev,
336 "failed to scale voltage: %d\n", ret);
337 }
338 mutex_unlock(&info->reg_lock);
339 } else if (event == OPP_EVENT_DISABLE) {
340 freq = dev_pm_opp_get_freq(opp);
341
342 /* case of current opp item is disabled */
343 if (info->current_freq == freq) {
344 freq = 1;
345 new_opp = dev_pm_opp_find_freq_ceil(info->cpu_dev,
346 &freq);
347 if (IS_ERR(new_opp)) {
348 dev_err(info->cpu_dev,
349 "all opp items are disabled\n");
350 ret = PTR_ERR(new_opp);
351 return notifier_from_errno(ret);
352 }
353
354 dev_pm_opp_put(new_opp);
355
356 struct cpufreq_policy *policy __free(put_cpufreq_policy)
357 = cpufreq_cpu_get(info->opp_cpu);
358 if (policy)
359 cpufreq_driver_target(policy, freq / 1000,
360 CPUFREQ_RELATION_L);
361 }
362 }
363
364 return notifier_from_errno(ret);
365 }
366
of_get_cci(struct device * cpu_dev)367 static struct device *of_get_cci(struct device *cpu_dev)
368 {
369 struct device_node *np;
370 struct platform_device *pdev;
371
372 np = of_parse_phandle(cpu_dev->of_node, "mediatek,cci", 0);
373 if (!np)
374 return ERR_PTR(-ENODEV);
375
376 pdev = of_find_device_by_node(np);
377 of_node_put(np);
378 if (!pdev)
379 return ERR_PTR(-ENODEV);
380
381 return &pdev->dev;
382 }
383
mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info * info,int cpu)384 static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu)
385 {
386 struct device *cpu_dev;
387 struct dev_pm_opp *opp;
388 unsigned long rate;
389 int ret;
390
391 cpu_dev = get_cpu_device(cpu);
392 if (!cpu_dev)
393 return dev_err_probe(cpu_dev, -ENODEV, "failed to get cpu%d device\n", cpu);
394 info->cpu_dev = cpu_dev;
395
396 info->ccifreq_bound = false;
397 if (info->soc_data->ccifreq_supported) {
398 info->cci_dev = of_get_cci(info->cpu_dev);
399 if (IS_ERR(info->cci_dev))
400 return dev_err_probe(cpu_dev, PTR_ERR(info->cci_dev),
401 "cpu%d: failed to get cci device\n",
402 cpu);
403 }
404
405 info->cpu_clk = clk_get(cpu_dev, "cpu");
406 if (IS_ERR(info->cpu_clk)) {
407 ret = PTR_ERR(info->cpu_clk);
408 dev_err_probe(cpu_dev, ret, "cpu%d: failed to get cpu clk\n", cpu);
409 goto out_put_cci_dev;
410 }
411
412 info->inter_clk = clk_get(cpu_dev, "intermediate");
413 if (IS_ERR(info->inter_clk)) {
414 ret = PTR_ERR(info->inter_clk);
415 dev_err_probe(cpu_dev, ret,
416 "cpu%d: failed to get intermediate clk\n", cpu);
417 goto out_free_mux_clock;
418 }
419
420 info->proc_reg = regulator_get_optional(cpu_dev, "proc");
421 if (IS_ERR(info->proc_reg)) {
422 ret = PTR_ERR(info->proc_reg);
423 dev_err_probe(cpu_dev, ret,
424 "cpu%d: failed to get proc regulator\n", cpu);
425 goto out_free_inter_clock;
426 }
427
428 ret = regulator_enable(info->proc_reg);
429 if (ret) {
430 dev_err_probe(cpu_dev, ret, "cpu%d: failed to enable vproc\n", cpu);
431 goto out_free_proc_reg;
432 }
433
434 /* Both presence and absence of sram regulator are valid cases. */
435 info->sram_reg = regulator_get_optional(cpu_dev, "sram");
436 if (IS_ERR(info->sram_reg)) {
437 ret = PTR_ERR(info->sram_reg);
438 if (ret == -EPROBE_DEFER) {
439 dev_err_probe(cpu_dev, ret,
440 "cpu%d: Failed to get sram regulator\n", cpu);
441 goto out_disable_proc_reg;
442 }
443
444 info->sram_reg = NULL;
445 } else {
446 ret = regulator_enable(info->sram_reg);
447 if (ret) {
448 dev_err_probe(cpu_dev, ret, "cpu%d: failed to enable vsram\n", cpu);
449 goto out_free_sram_reg;
450 }
451 }
452
453 /* Get OPP-sharing information from "operating-points-v2" bindings */
454 ret = dev_pm_opp_of_get_sharing_cpus(cpu_dev, &info->cpus);
455 if (ret) {
456 dev_err_probe(cpu_dev, ret,
457 "cpu%d: failed to get OPP-sharing information\n", cpu);
458 goto out_disable_sram_reg;
459 }
460
461 ret = dev_pm_opp_of_cpumask_add_table(&info->cpus);
462 if (ret) {
463 dev_err_probe(cpu_dev, ret, "cpu%d: no OPP table\n", cpu);
464 goto out_disable_sram_reg;
465 }
466
467 ret = clk_prepare_enable(info->cpu_clk);
468 if (ret) {
469 dev_err_probe(cpu_dev, ret, "cpu%d: failed to enable cpu clk\n", cpu);
470 goto out_free_opp_table;
471 }
472
473 ret = clk_prepare_enable(info->inter_clk);
474 if (ret) {
475 dev_err_probe(cpu_dev, ret, "cpu%d: failed to enable inter clk\n", cpu);
476 goto out_disable_mux_clock;
477 }
478
479 if (info->soc_data->ccifreq_supported) {
480 info->vproc_on_boot = regulator_get_voltage(info->proc_reg);
481 if (info->vproc_on_boot < 0) {
482 ret = dev_err_probe(info->cpu_dev, info->vproc_on_boot,
483 "invalid Vproc value\n");
484 goto out_disable_inter_clock;
485 }
486 }
487
488 /* Search a safe voltage for intermediate frequency. */
489 rate = clk_get_rate(info->inter_clk);
490 opp = dev_pm_opp_find_freq_ceil(cpu_dev, &rate);
491 if (IS_ERR(opp)) {
492 ret = dev_err_probe(cpu_dev, PTR_ERR(opp),
493 "cpu%d: failed to get intermediate opp\n", cpu);
494 goto out_disable_inter_clock;
495 }
496 info->intermediate_voltage = dev_pm_opp_get_voltage(opp);
497 dev_pm_opp_put(opp);
498
499 mutex_init(&info->reg_lock);
500 info->current_freq = clk_get_rate(info->cpu_clk);
501
502 info->opp_cpu = cpu;
503 info->opp_nb.notifier_call = mtk_cpufreq_opp_notifier;
504 ret = dev_pm_opp_register_notifier(cpu_dev, &info->opp_nb);
505 if (ret) {
506 dev_err_probe(cpu_dev, ret, "cpu%d: failed to register opp notifier\n", cpu);
507 goto out_disable_inter_clock;
508 }
509
510 /*
511 * If SRAM regulator is present, software "voltage tracking" is needed
512 * for this CPU power domain.
513 */
514 info->need_voltage_tracking = (info->sram_reg != NULL);
515
516 /*
517 * We assume min voltage is 0 and tracking target voltage using
518 * min_volt_shift for each iteration.
519 * The vtrack_max is 3 times of expeted iteration count.
520 */
521 info->vtrack_max = 3 * DIV_ROUND_UP(max(info->soc_data->sram_max_volt,
522 info->soc_data->proc_max_volt),
523 info->soc_data->min_volt_shift);
524
525 return 0;
526
527 out_disable_inter_clock:
528 clk_disable_unprepare(info->inter_clk);
529
530 out_disable_mux_clock:
531 clk_disable_unprepare(info->cpu_clk);
532
533 out_free_opp_table:
534 dev_pm_opp_of_cpumask_remove_table(&info->cpus);
535
536 out_disable_sram_reg:
537 if (info->sram_reg)
538 regulator_disable(info->sram_reg);
539
540 out_free_sram_reg:
541 if (info->sram_reg)
542 regulator_put(info->sram_reg);
543
544 out_disable_proc_reg:
545 regulator_disable(info->proc_reg);
546
547 out_free_proc_reg:
548 regulator_put(info->proc_reg);
549
550 out_free_inter_clock:
551 clk_put(info->inter_clk);
552
553 out_free_mux_clock:
554 clk_put(info->cpu_clk);
555
556 out_put_cci_dev:
557 if (info->soc_data->ccifreq_supported)
558 put_device(info->cci_dev);
559
560 return ret;
561 }
562
mtk_cpu_dvfs_info_release(struct mtk_cpu_dvfs_info * info)563 static void mtk_cpu_dvfs_info_release(struct mtk_cpu_dvfs_info *info)
564 {
565 regulator_disable(info->proc_reg);
566 regulator_put(info->proc_reg);
567 if (info->sram_reg) {
568 regulator_disable(info->sram_reg);
569 regulator_put(info->sram_reg);
570 }
571 clk_disable_unprepare(info->cpu_clk);
572 clk_put(info->cpu_clk);
573 clk_disable_unprepare(info->inter_clk);
574 clk_put(info->inter_clk);
575 dev_pm_opp_of_cpumask_remove_table(&info->cpus);
576 dev_pm_opp_unregister_notifier(info->cpu_dev, &info->opp_nb);
577 if (info->soc_data->ccifreq_supported)
578 put_device(info->cci_dev);
579 }
580
mtk_cpufreq_init(struct cpufreq_policy * policy)581 static int mtk_cpufreq_init(struct cpufreq_policy *policy)
582 {
583 struct mtk_cpu_dvfs_info *info;
584 struct cpufreq_frequency_table *freq_table;
585 int ret;
586
587 info = mtk_cpu_dvfs_info_lookup(policy->cpu);
588 if (!info) {
589 pr_err("dvfs info for cpu%d is not initialized.\n",
590 policy->cpu);
591 return -EINVAL;
592 }
593
594 ret = dev_pm_opp_init_cpufreq_table(info->cpu_dev, &freq_table);
595 if (ret) {
596 dev_err(info->cpu_dev,
597 "failed to init cpufreq table for cpu%d: %d\n",
598 policy->cpu, ret);
599 return ret;
600 }
601
602 cpumask_copy(policy->cpus, &info->cpus);
603 policy->freq_table = freq_table;
604 policy->driver_data = info;
605 policy->clk = info->cpu_clk;
606
607 return 0;
608 }
609
mtk_cpufreq_exit(struct cpufreq_policy * policy)610 static void mtk_cpufreq_exit(struct cpufreq_policy *policy)
611 {
612 struct mtk_cpu_dvfs_info *info = policy->driver_data;
613
614 dev_pm_opp_free_cpufreq_table(info->cpu_dev, &policy->freq_table);
615 }
616
617 static struct cpufreq_driver mtk_cpufreq_driver = {
618 .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK |
619 CPUFREQ_HAVE_GOVERNOR_PER_POLICY |
620 CPUFREQ_IS_COOLING_DEV,
621 .verify = cpufreq_generic_frequency_table_verify,
622 .target_index = mtk_cpufreq_set_target,
623 .get = cpufreq_generic_get,
624 .init = mtk_cpufreq_init,
625 .exit = mtk_cpufreq_exit,
626 .register_em = cpufreq_register_em_with_opp,
627 .name = "mtk-cpufreq",
628 };
629
mtk_cpufreq_probe(struct platform_device * pdev)630 static int mtk_cpufreq_probe(struct platform_device *pdev)
631 {
632 const struct mtk_cpufreq_platform_data *data;
633 struct mtk_cpu_dvfs_info *info, *tmp;
634 int cpu, ret;
635
636 data = dev_get_platdata(&pdev->dev);
637 if (!data)
638 return dev_err_probe(&pdev->dev, -ENODEV,
639 "failed to get mtk cpufreq platform data\n");
640
641 for_each_present_cpu(cpu) {
642 info = mtk_cpu_dvfs_info_lookup(cpu);
643 if (info)
644 continue;
645
646 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
647 if (!info) {
648 ret = dev_err_probe(&pdev->dev, -ENOMEM,
649 "Failed to allocate dvfs_info\n");
650 goto release_dvfs_info_list;
651 }
652
653 info->soc_data = data;
654 ret = mtk_cpu_dvfs_info_init(info, cpu);
655 if (ret)
656 goto release_dvfs_info_list;
657
658 list_add(&info->list_head, &dvfs_info_list);
659 }
660
661 ret = cpufreq_register_driver(&mtk_cpufreq_driver);
662 if (ret) {
663 dev_err_probe(&pdev->dev, ret, "failed to register mtk cpufreq driver\n");
664 goto release_dvfs_info_list;
665 }
666
667 return 0;
668
669 release_dvfs_info_list:
670 list_for_each_entry_safe(info, tmp, &dvfs_info_list, list_head) {
671 mtk_cpu_dvfs_info_release(info);
672 list_del(&info->list_head);
673 }
674
675 return ret;
676 }
677
678 static struct platform_driver mtk_cpufreq_platdrv = {
679 .driver = {
680 .name = "mtk-cpufreq",
681 },
682 .probe = mtk_cpufreq_probe,
683 };
684
685 static const struct mtk_cpufreq_platform_data mt2701_platform_data = {
686 .min_volt_shift = 100000,
687 .max_volt_shift = 200000,
688 .proc_max_volt = 1150000,
689 .sram_min_volt = 0,
690 .sram_max_volt = 1150000,
691 .ccifreq_supported = false,
692 };
693
694 static const struct mtk_cpufreq_platform_data mt7622_platform_data = {
695 .min_volt_shift = 100000,
696 .max_volt_shift = 200000,
697 .proc_max_volt = 1350000,
698 .sram_min_volt = 0,
699 .sram_max_volt = 1350000,
700 .ccifreq_supported = false,
701 };
702
703 static const struct mtk_cpufreq_platform_data mt7623_platform_data = {
704 .min_volt_shift = 100000,
705 .max_volt_shift = 200000,
706 .proc_max_volt = 1300000,
707 .ccifreq_supported = false,
708 };
709
710 static const struct mtk_cpufreq_platform_data mt7988_platform_data = {
711 .min_volt_shift = 100000,
712 .max_volt_shift = 200000,
713 .proc_max_volt = 900000,
714 .sram_min_volt = 0,
715 .sram_max_volt = 1150000,
716 .ccifreq_supported = true,
717 };
718
719 static const struct mtk_cpufreq_platform_data mt8183_platform_data = {
720 .min_volt_shift = 100000,
721 .max_volt_shift = 200000,
722 .proc_max_volt = 1150000,
723 .sram_min_volt = 0,
724 .sram_max_volt = 1150000,
725 .ccifreq_supported = true,
726 };
727
728 static const struct mtk_cpufreq_platform_data mt8186_platform_data = {
729 .min_volt_shift = 100000,
730 .max_volt_shift = 250000,
731 .proc_max_volt = 1118750,
732 .sram_min_volt = 850000,
733 .sram_max_volt = 1118750,
734 .ccifreq_supported = true,
735 };
736
737 static const struct mtk_cpufreq_platform_data mt8516_platform_data = {
738 .min_volt_shift = 100000,
739 .max_volt_shift = 200000,
740 .proc_max_volt = 1310000,
741 .sram_min_volt = 0,
742 .sram_max_volt = 1310000,
743 .ccifreq_supported = false,
744 };
745
746 /* List of machines supported by this driver */
747 static const struct of_device_id mtk_cpufreq_machines[] __initconst __maybe_unused = {
748 { .compatible = "mediatek,mt2701", .data = &mt2701_platform_data },
749 { .compatible = "mediatek,mt2712", .data = &mt2701_platform_data },
750 { .compatible = "mediatek,mt7622", .data = &mt7622_platform_data },
751 { .compatible = "mediatek,mt7623", .data = &mt7623_platform_data },
752 { .compatible = "mediatek,mt7988a", .data = &mt7988_platform_data },
753 { .compatible = "mediatek,mt8167", .data = &mt8516_platform_data },
754 { .compatible = "mediatek,mt817x", .data = &mt2701_platform_data },
755 { .compatible = "mediatek,mt8173", .data = &mt2701_platform_data },
756 { .compatible = "mediatek,mt8176", .data = &mt2701_platform_data },
757 { .compatible = "mediatek,mt8183", .data = &mt8183_platform_data },
758 { .compatible = "mediatek,mt8186", .data = &mt8186_platform_data },
759 { .compatible = "mediatek,mt8365", .data = &mt2701_platform_data },
760 { .compatible = "mediatek,mt8516", .data = &mt8516_platform_data },
761 { }
762 };
763 MODULE_DEVICE_TABLE(of, mtk_cpufreq_machines);
764
mtk_cpufreq_driver_init(void)765 static int __init mtk_cpufreq_driver_init(void)
766 {
767 struct device_node *np;
768 const struct of_device_id *match;
769 const struct mtk_cpufreq_platform_data *data;
770 int err;
771
772 np = of_find_node_by_path("/");
773 if (!np)
774 return -ENODEV;
775
776 match = of_match_node(mtk_cpufreq_machines, np);
777 of_node_put(np);
778 if (!match) {
779 pr_debug("Machine is not compatible with mtk-cpufreq\n");
780 return -ENODEV;
781 }
782 data = match->data;
783
784 err = platform_driver_register(&mtk_cpufreq_platdrv);
785 if (err)
786 return err;
787
788 /*
789 * Since there's no place to hold device registration code and no
790 * device tree based way to match cpufreq driver yet, both the driver
791 * and the device registration codes are put here to handle defer
792 * probing.
793 */
794 cpufreq_pdev = platform_device_register_data(NULL, "mtk-cpufreq", -1,
795 data, sizeof(*data));
796 if (IS_ERR(cpufreq_pdev)) {
797 pr_err("failed to register mtk-cpufreq platform device\n");
798 platform_driver_unregister(&mtk_cpufreq_platdrv);
799 return PTR_ERR(cpufreq_pdev);
800 }
801
802 return 0;
803 }
module_init(mtk_cpufreq_driver_init)804 module_init(mtk_cpufreq_driver_init)
805
806 static void __exit mtk_cpufreq_driver_exit(void)
807 {
808 platform_device_unregister(cpufreq_pdev);
809 platform_driver_unregister(&mtk_cpufreq_platdrv);
810 }
811 module_exit(mtk_cpufreq_driver_exit)
812
813 MODULE_DESCRIPTION("MediaTek CPUFreq driver");
814 MODULE_AUTHOR("Pi-Cheng Chen <pi-cheng.chen@linaro.org>");
815 MODULE_LICENSE("GPL v2");
816