1 // SPDX-License-Identifier: ISC
2 /* Copyright (C) 2023 MediaTek Inc. */
3
4 #if defined(__FreeBSD__)
5 #define LINUXKPI_PARAM_PREFIX mt7925_pci_
6 #endif
7
8 #include <linux/kernel.h>
9 #include <linux/module.h>
10 #include <linux/pci.h>
11
12 #include "mt7925.h"
13 #include "mac.h"
14 #include "mcu.h"
15 #include "../dma.h"
16
17 static const struct pci_device_id mt7925_pci_device_table[] = {
18 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7925),
19 .driver_data = (kernel_ulong_t)MT7925_FIRMWARE_WM },
20 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x0717),
21 .driver_data = (kernel_ulong_t)MT7925_FIRMWARE_WM },
22 { },
23 };
24
25 static bool mt7925_disable_aspm;
26 module_param_named(disable_aspm, mt7925_disable_aspm, bool, 0644);
27 MODULE_PARM_DESC(disable_aspm, "disable PCI ASPM support");
28
mt7925e_init_reset(struct mt792x_dev * dev)29 static int mt7925e_init_reset(struct mt792x_dev *dev)
30 {
31 return mt792x_wpdma_reset(dev, true);
32 }
33
mt7925e_unregister_device(struct mt792x_dev * dev)34 static void mt7925e_unregister_device(struct mt792x_dev *dev)
35 {
36 int i;
37 struct mt76_connac_pm *pm = &dev->pm;
38 struct ieee80211_hw *hw = mt76_hw(dev);
39
40 if (dev->phy.chip_cap & MT792x_CHIP_CAP_WF_RF_PIN_CTRL_EVT_EN)
41 wiphy_rfkill_stop_polling(hw->wiphy);
42
43 cancel_work_sync(&dev->init_work);
44 mt76_unregister_device(&dev->mt76);
45 mt76_for_each_q_rx(&dev->mt76, i)
46 napi_disable(&dev->mt76.napi[i]);
47 cancel_delayed_work_sync(&pm->ps_work);
48 cancel_work_sync(&pm->wake_work);
49 cancel_work_sync(&dev->reset_work);
50
51 mt7925_tx_token_put(dev);
52 __mt792x_mcu_drv_pmctrl(dev);
53 mt792x_dma_cleanup(dev);
54 mt792x_wfsys_reset(dev);
55 skb_queue_purge(&dev->mt76.mcu.res_q);
56
57 tasklet_disable(&dev->mt76.irq_tasklet);
58 }
59
mt7925_reg_remap_restore(struct mt792x_dev * dev)60 static void mt7925_reg_remap_restore(struct mt792x_dev *dev)
61 {
62 /* remap to ori status */
63 if (unlikely(dev->backup_l1)) {
64 dev->bus_ops->wr(&dev->mt76, MT_HIF_REMAP_L1, dev->backup_l1);
65 dev->backup_l1 = 0;
66 }
67
68 if (dev->backup_l2) {
69 dev->bus_ops->wr(&dev->mt76, MT_HIF_REMAP_L2, dev->backup_l2);
70 dev->backup_l2 = 0;
71 }
72 }
73
mt7925_reg_map_l1(struct mt792x_dev * dev,u32 addr)74 static u32 mt7925_reg_map_l1(struct mt792x_dev *dev, u32 addr)
75 {
76 u32 offset = FIELD_GET(MT_HIF_REMAP_L1_OFFSET, addr);
77 u32 base = FIELD_GET(MT_HIF_REMAP_L1_BASE, addr);
78
79 dev->backup_l1 = dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_L1);
80
81 dev->bus_ops->rmw(&dev->mt76, MT_HIF_REMAP_L1,
82 MT_HIF_REMAP_L1_MASK,
83 FIELD_PREP(MT_HIF_REMAP_L1_MASK, base));
84
85 /* use read to push write */
86 dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_L1);
87
88 return MT_HIF_REMAP_BASE_L1 + offset;
89 }
90
mt7925_reg_map_l2(struct mt792x_dev * dev,u32 addr)91 static u32 mt7925_reg_map_l2(struct mt792x_dev *dev, u32 addr)
92 {
93 u32 base = FIELD_GET(MT_HIF_REMAP_L1_BASE, MT_HIF_REMAP_BASE_L2);
94
95 dev->backup_l2 = dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_L1);
96
97 dev->bus_ops->rmw(&dev->mt76, MT_HIF_REMAP_L1,
98 MT_HIF_REMAP_L1_MASK,
99 FIELD_PREP(MT_HIF_REMAP_L1_MASK, base));
100
101 dev->bus_ops->wr(&dev->mt76, MT_HIF_REMAP_L2, addr);
102 /* use read to push write */
103 dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_L1);
104
105 return MT_HIF_REMAP_BASE_L1;
106 }
107
__mt7925_reg_addr(struct mt792x_dev * dev,u32 addr)108 static u32 __mt7925_reg_addr(struct mt792x_dev *dev, u32 addr)
109 {
110 static const struct mt76_connac_reg_map fixed_map[] = {
111 { 0x830c0000, 0x000000, 0x0001000 }, /* WF_MCU_BUS_CR_REMAP */
112 { 0x54000000, 0x002000, 0x0001000 }, /* WFDMA PCIE0 MCU DMA0 */
113 { 0x55000000, 0x003000, 0x0001000 }, /* WFDMA PCIE0 MCU DMA1 */
114 { 0x56000000, 0x004000, 0x0001000 }, /* WFDMA reserved */
115 { 0x57000000, 0x005000, 0x0001000 }, /* WFDMA MCU wrap CR */
116 { 0x58000000, 0x006000, 0x0001000 }, /* WFDMA PCIE1 MCU DMA0 (MEM_DMA) */
117 { 0x59000000, 0x007000, 0x0001000 }, /* WFDMA PCIE1 MCU DMA1 */
118 { 0x820c0000, 0x008000, 0x0004000 }, /* WF_UMAC_TOP (PLE) */
119 { 0x820c8000, 0x00c000, 0x0002000 }, /* WF_UMAC_TOP (PSE) */
120 { 0x820cc000, 0x00e000, 0x0002000 }, /* WF_UMAC_TOP (PP) */
121 { 0x74030000, 0x010000, 0x0001000 }, /* PCIe MAC */
122 { 0x820e0000, 0x020000, 0x0000400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */
123 { 0x820e1000, 0x020400, 0x0000200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */
124 { 0x820e2000, 0x020800, 0x0000400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */
125 { 0x820e3000, 0x020c00, 0x0000400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */
126 { 0x820e4000, 0x021000, 0x0000400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */
127 { 0x820e5000, 0x021400, 0x0000800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */
128 { 0x820ce000, 0x021c00, 0x0000200 }, /* WF_LMAC_TOP (WF_SEC) */
129 { 0x820e7000, 0x021e00, 0x0000200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */
130 { 0x820cf000, 0x022000, 0x0001000 }, /* WF_LMAC_TOP (WF_PF) */
131 { 0x820e9000, 0x023400, 0x0000200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */
132 { 0x820ea000, 0x024000, 0x0000200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */
133 { 0x820eb000, 0x024200, 0x0000400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */
134 { 0x820ec000, 0x024600, 0x0000200 }, /* WF_LMAC_TOP BN0 (WF_INT) */
135 { 0x820ed000, 0x024800, 0x0000800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */
136 { 0x820ca000, 0x026000, 0x0002000 }, /* WF_LMAC_TOP BN0 (WF_MUCOP) */
137 { 0x820d0000, 0x030000, 0x0010000 }, /* WF_LMAC_TOP (WF_WTBLON) */
138 { 0x40000000, 0x070000, 0x0010000 }, /* WF_UMAC_SYSRAM */
139 { 0x00400000, 0x080000, 0x0010000 }, /* WF_MCU_SYSRAM */
140 { 0x00410000, 0x090000, 0x0010000 }, /* WF_MCU_SYSRAM (configure register) */
141 { 0x820f0000, 0x0a0000, 0x0000400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */
142 { 0x820f1000, 0x0a0600, 0x0000200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */
143 { 0x820f2000, 0x0a0800, 0x0000400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */
144 { 0x820f3000, 0x0a0c00, 0x0000400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */
145 { 0x820f4000, 0x0a1000, 0x0000400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */
146 { 0x820f5000, 0x0a1400, 0x0000800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */
147 { 0x820f7000, 0x0a1e00, 0x0000200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */
148 { 0x820f9000, 0x0a3400, 0x0000200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */
149 { 0x820fa000, 0x0a4000, 0x0000200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */
150 { 0x820fb000, 0x0a4200, 0x0000400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */
151 { 0x820fc000, 0x0a4600, 0x0000200 }, /* WF_LMAC_TOP BN1 (WF_INT) */
152 { 0x820fd000, 0x0a4800, 0x0000800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */
153 { 0x820c4000, 0x0a8000, 0x0004000 }, /* WF_LMAC_TOP BN1 (WF_MUCOP) */
154 { 0x820b0000, 0x0ae000, 0x0001000 }, /* [APB2] WFSYS_ON */
155 { 0x80020000, 0x0b0000, 0x0010000 }, /* WF_TOP_MISC_OFF */
156 { 0x81020000, 0x0c0000, 0x0010000 }, /* WF_TOP_MISC_ON */
157 { 0x7c020000, 0x0d0000, 0x0010000 }, /* CONN_INFRA, wfdma */
158 { 0x7c060000, 0x0e0000, 0x0010000 }, /* CONN_INFRA, conn_host_csr_top */
159 { 0x7c000000, 0x0f0000, 0x0010000 }, /* CONN_INFRA */
160 { 0x70020000, 0x1f0000, 0x0010000 }, /* Reserved for CBTOP, can't switch */
161 { 0x7c500000, 0x060000, 0x2000000 }, /* remap */
162 { 0x0, 0x0, 0x0 } /* End */
163 };
164 int i;
165
166 if (addr < 0x200000)
167 return addr;
168
169 mt7925_reg_remap_restore(dev);
170
171 for (i = 0; i < ARRAY_SIZE(fixed_map); i++) {
172 u32 ofs;
173
174 if (addr < fixed_map[i].phys)
175 continue;
176
177 ofs = addr - fixed_map[i].phys;
178 if (ofs > fixed_map[i].size)
179 continue;
180
181 return fixed_map[i].maps + ofs;
182 }
183
184 if ((addr >= 0x18000000 && addr < 0x18c00000) ||
185 (addr >= 0x70000000 && addr < 0x78000000) ||
186 (addr >= 0x7c000000 && addr < 0x7c400000))
187 return mt7925_reg_map_l1(dev, addr);
188
189 return mt7925_reg_map_l2(dev, addr);
190 }
191
mt7925_rr(struct mt76_dev * mdev,u32 offset)192 static u32 mt7925_rr(struct mt76_dev *mdev, u32 offset)
193 {
194 struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76);
195 u32 addr = __mt7925_reg_addr(dev, offset);
196
197 return dev->bus_ops->rr(mdev, addr);
198 }
199
mt7925_wr(struct mt76_dev * mdev,u32 offset,u32 val)200 static void mt7925_wr(struct mt76_dev *mdev, u32 offset, u32 val)
201 {
202 struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76);
203 u32 addr = __mt7925_reg_addr(dev, offset);
204
205 dev->bus_ops->wr(mdev, addr, val);
206 }
207
mt7925_rmw(struct mt76_dev * mdev,u32 offset,u32 mask,u32 val)208 static u32 mt7925_rmw(struct mt76_dev *mdev, u32 offset, u32 mask, u32 val)
209 {
210 struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76);
211 u32 addr = __mt7925_reg_addr(dev, offset);
212
213 return dev->bus_ops->rmw(mdev, addr, mask, val);
214 }
215
mt7925_dma_init(struct mt792x_dev * dev)216 static int mt7925_dma_init(struct mt792x_dev *dev)
217 {
218 int ret;
219
220 mt76_dma_attach(&dev->mt76);
221
222 ret = mt792x_dma_disable(dev, true);
223 if (ret)
224 return ret;
225
226 /* init tx queue */
227 ret = mt76_connac_init_tx_queues(dev->phy.mt76, MT7925_TXQ_BAND0,
228 MT7925_TX_RING_SIZE,
229 MT_TX_RING_BASE, NULL, 0);
230 if (ret)
231 return ret;
232
233 mt76_wr(dev, MT_WFDMA0_TX_RING0_EXT_CTRL, 0x4);
234
235 /* command to WM */
236 ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_WM, MT7925_TXQ_MCU_WM,
237 MT7925_TX_MCU_RING_SIZE, MT_TX_RING_BASE);
238 if (ret)
239 return ret;
240
241 /* firmware download */
242 ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_FWDL, MT7925_TXQ_FWDL,
243 MT7925_TX_FWDL_RING_SIZE, MT_TX_RING_BASE);
244 if (ret)
245 return ret;
246
247 /* rx event */
248 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU],
249 MT7925_RXQ_MCU_WM, MT7925_RX_MCU_RING_SIZE,
250 MT_RX_BUF_SIZE, MT_RX_EVENT_RING_BASE);
251 if (ret)
252 return ret;
253
254 /* rx data */
255 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MAIN],
256 MT7925_RXQ_BAND0, MT7925_RX_RING_SIZE,
257 MT_RX_BUF_SIZE, MT_RX_DATA_RING_BASE);
258 if (ret)
259 return ret;
260
261 ret = mt76_init_queues(dev, mt792x_poll_rx);
262 if (ret < 0)
263 return ret;
264
265 netif_napi_add_tx(dev->mt76.tx_napi_dev, &dev->mt76.tx_napi,
266 mt792x_poll_tx);
267 napi_enable(&dev->mt76.tx_napi);
268
269 return mt792x_dma_enable(dev);
270 }
271
mt7925_pci_probe(struct pci_dev * pdev,const struct pci_device_id * id)272 static int mt7925_pci_probe(struct pci_dev *pdev,
273 const struct pci_device_id *id)
274 {
275 static const struct mt76_driver_ops drv_ops = {
276 /* txwi_size = txd size + txp size */
277 .txwi_size = MT_TXD_SIZE + sizeof(struct mt76_connac_hw_txp),
278 .drv_flags = MT_DRV_TXWI_NO_FREE | MT_DRV_HW_MGMT_TXQ |
279 MT_DRV_AMSDU_OFFLOAD,
280 .survey_flags = SURVEY_INFO_TIME_TX |
281 SURVEY_INFO_TIME_RX |
282 SURVEY_INFO_TIME_BSS_RX,
283 .token_size = MT7925_TOKEN_SIZE,
284 .tx_prepare_skb = mt7925e_tx_prepare_skb,
285 .tx_complete_skb = mt76_connac_tx_complete_skb,
286 .rx_check = mt7925_rx_check,
287 .rx_skb = mt7925_queue_rx_skb,
288 .rx_poll_complete = mt792x_rx_poll_complete,
289 .sta_add = mt7925_mac_sta_add,
290 .sta_event = mt7925_mac_sta_event,
291 .sta_remove = mt7925_mac_sta_remove,
292 .update_survey = mt792x_update_channel,
293 };
294 static const struct mt792x_hif_ops mt7925_pcie_ops = {
295 .init_reset = mt7925e_init_reset,
296 .reset = mt7925e_mac_reset,
297 .mcu_init = mt7925e_mcu_init,
298 .drv_own = mt792xe_mcu_drv_pmctrl,
299 .fw_own = mt792xe_mcu_fw_pmctrl,
300 };
301 static const struct mt792x_irq_map irq_map = {
302 .host_irq_enable = MT_WFDMA0_HOST_INT_ENA,
303 .tx = {
304 .all_complete_mask = MT_INT_TX_DONE_ALL,
305 .mcu_complete_mask = MT_INT_TX_DONE_MCU,
306 },
307 .rx = {
308 .data_complete_mask = HOST_RX_DONE_INT_ENA2,
309 .wm_complete_mask = HOST_RX_DONE_INT_ENA0,
310 },
311 };
312 struct ieee80211_ops *ops;
313 struct mt76_bus_ops *bus_ops;
314 struct mt792x_dev *dev;
315 struct mt76_dev *mdev;
316 u8 features;
317 int ret;
318 u16 cmd;
319
320 ret = pcim_enable_device(pdev);
321 if (ret)
322 return ret;
323
324 ret = pcim_iomap_regions(pdev, BIT(0), pci_name(pdev));
325 if (ret)
326 return ret;
327
328 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
329 if (!(cmd & PCI_COMMAND_MEMORY)) {
330 cmd |= PCI_COMMAND_MEMORY;
331 pci_write_config_word(pdev, PCI_COMMAND, cmd);
332 }
333 pci_set_master(pdev);
334
335 ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
336 if (ret < 0)
337 return ret;
338
339 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
340 if (ret)
341 goto err_free_pci_vec;
342
343 if (mt7925_disable_aspm)
344 mt76_pci_disable_aspm(pdev);
345
346 ops = mt792x_get_mac80211_ops(&pdev->dev, &mt7925_ops,
347 (void *)id->driver_data, &features);
348 if (!ops) {
349 ret = -ENOMEM;
350 goto err_free_pci_vec;
351 }
352
353 mdev = mt76_alloc_device(&pdev->dev, sizeof(*dev), ops, &drv_ops);
354 if (!mdev) {
355 ret = -ENOMEM;
356 goto err_free_pci_vec;
357 }
358
359 pci_set_drvdata(pdev, mdev);
360
361 dev = container_of(mdev, struct mt792x_dev, mt76);
362 dev->fw_features = features;
363 dev->hif_ops = &mt7925_pcie_ops;
364 dev->irq_map = &irq_map;
365 mt76_mmio_init(&dev->mt76, pcim_iomap_table(pdev)[0]);
366 tasklet_init(&mdev->irq_tasklet, mt792x_irq_tasklet, (unsigned long)dev);
367
368 dev->phy.dev = dev;
369 dev->phy.mt76 = &dev->mt76.phy;
370 dev->mt76.phy.priv = &dev->phy;
371 dev->bus_ops = dev->mt76.bus;
372 bus_ops = devm_kmemdup(dev->mt76.dev, dev->bus_ops, sizeof(*bus_ops),
373 GFP_KERNEL);
374 if (!bus_ops) {
375 ret = -ENOMEM;
376 goto err_free_dev;
377 }
378
379 bus_ops->rr = mt7925_rr;
380 bus_ops->wr = mt7925_wr;
381 bus_ops->rmw = mt7925_rmw;
382 dev->mt76.bus = bus_ops;
383
384 if (!mt7925_disable_aspm && mt76_pci_aspm_supported(pdev))
385 dev->aspm_supported = true;
386
387 ret = __mt792x_mcu_fw_pmctrl(dev);
388 if (ret)
389 goto err_free_dev;
390
391 ret = __mt792xe_mcu_drv_pmctrl(dev);
392 if (ret)
393 goto err_free_dev;
394
395 mdev->rev = (mt76_rr(dev, MT_HW_CHIPID) << 16) |
396 (mt76_rr(dev, MT_HW_REV) & 0xff);
397
398 dev_info(mdev->dev, "ASIC revision: %04x\n", mdev->rev);
399
400 mt76_rmw_field(dev, MT_HW_EMI_CTL, MT_HW_EMI_CTL_SLPPROT_EN, 1);
401
402 ret = mt792x_wfsys_reset(dev);
403 if (ret)
404 goto err_free_dev;
405
406 mt76_wr(dev, irq_map.host_irq_enable, 0);
407
408 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0xff);
409
410 ret = devm_request_irq(mdev->dev, pdev->irq, mt792x_irq_handler,
411 IRQF_SHARED, KBUILD_MODNAME, dev);
412 if (ret)
413 goto err_free_dev;
414
415 ret = mt7925_dma_init(dev);
416 if (ret)
417 goto err_free_irq;
418
419 ret = mt7925_register_device(dev);
420 if (ret)
421 goto err_free_irq;
422
423 return 0;
424
425 err_free_irq:
426 devm_free_irq(&pdev->dev, pdev->irq, dev);
427 err_free_dev:
428 mt76_free_device(&dev->mt76);
429 err_free_pci_vec:
430 pci_free_irq_vectors(pdev);
431
432 return ret;
433 }
434
mt7925_pci_remove(struct pci_dev * pdev)435 static void mt7925_pci_remove(struct pci_dev *pdev)
436 {
437 struct mt76_dev *mdev = pci_get_drvdata(pdev);
438 struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76);
439
440 mt7925e_unregister_device(dev);
441 set_bit(MT76_REMOVED, &mdev->phy.state);
442 devm_free_irq(&pdev->dev, pdev->irq, dev);
443 mt76_free_device(&dev->mt76);
444 pci_free_irq_vectors(pdev);
445 }
446
447 #if !defined(__FreeBSD__) || defined(CONFIG_PM_SLEEP)
mt7925_pci_suspend(struct device * device)448 static int mt7925_pci_suspend(struct device *device)
449 {
450 struct pci_dev *pdev = to_pci_dev(device);
451 struct mt76_dev *mdev = pci_get_drvdata(pdev);
452 struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76);
453 struct mt76_connac_pm *pm = &dev->pm;
454 int i, err, ret;
455
456 pm->suspended = true;
457 dev->hif_resumed = false;
458 flush_work(&dev->reset_work);
459 cancel_delayed_work_sync(&pm->ps_work);
460 cancel_work_sync(&pm->wake_work);
461
462 mt7925_roc_abort_sync(dev);
463
464 err = mt792x_mcu_drv_pmctrl(dev);
465 if (err < 0)
466 goto restore_suspend;
467
468 wait_event_timeout(dev->wait,
469 !dev->regd_in_progress, 5 * HZ);
470
471 /* always enable deep sleep during suspend to reduce
472 * power consumption
473 */
474 mt7925_mcu_set_deep_sleep(dev, true);
475
476 mt76_connac_mcu_set_hif_suspend(mdev, true, false);
477 ret = wait_event_timeout(dev->wait,
478 dev->hif_idle, 3 * HZ);
479 if (!ret) {
480 err = -ETIMEDOUT;
481 goto restore_suspend;
482 }
483
484 napi_disable(&mdev->tx_napi);
485 mt76_worker_disable(&mdev->tx_worker);
486
487 mt76_for_each_q_rx(mdev, i) {
488 napi_disable(&mdev->napi[i]);
489 }
490
491 /* wait until dma is idle */
492 mt76_poll(dev, MT_WFDMA0_GLO_CFG,
493 MT_WFDMA0_GLO_CFG_TX_DMA_BUSY |
494 MT_WFDMA0_GLO_CFG_RX_DMA_BUSY, 0, 1000);
495
496 /* put dma disabled */
497 mt76_clear(dev, MT_WFDMA0_GLO_CFG,
498 MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN);
499
500 /* disable interrupt */
501 mt76_wr(dev, dev->irq_map->host_irq_enable, 0);
502
503 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0x0);
504
505 synchronize_irq(pdev->irq);
506 tasklet_kill(&mdev->irq_tasklet);
507
508 err = mt792x_mcu_fw_pmctrl(dev);
509 if (err)
510 goto restore_napi;
511
512 return 0;
513
514 restore_napi:
515 mt76_for_each_q_rx(mdev, i) {
516 napi_enable(&mdev->napi[i]);
517 }
518 napi_enable(&mdev->tx_napi);
519
520 if (!pm->ds_enable)
521 mt7925_mcu_set_deep_sleep(dev, false);
522
523 mt76_connac_mcu_set_hif_suspend(mdev, false, false);
524 ret = wait_event_timeout(dev->wait,
525 dev->hif_resumed, 3 * HZ);
526 if (!ret)
527 err = -ETIMEDOUT;
528 restore_suspend:
529 pm->suspended = false;
530
531 if (err < 0)
532 mt792x_reset(&dev->mt76);
533
534 return err;
535 }
536
mt7925_pci_resume(struct device * device)537 static int mt7925_pci_resume(struct device *device)
538 {
539 struct pci_dev *pdev = to_pci_dev(device);
540 struct mt76_dev *mdev = pci_get_drvdata(pdev);
541 struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76);
542 struct mt76_connac_pm *pm = &dev->pm;
543 int i, err, ret;
544
545 dev->hif_idle = false;
546 err = mt792x_mcu_drv_pmctrl(dev);
547 if (err < 0)
548 goto failed;
549
550 mt792x_wpdma_reinit_cond(dev);
551
552 /* enable interrupt */
553 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0xff);
554 mt76_connac_irq_enable(&dev->mt76,
555 dev->irq_map->tx.all_complete_mask |
556 MT_INT_RX_DONE_ALL | MT_INT_MCU_CMD);
557 mt76_set(dev, MT_MCU2HOST_SW_INT_ENA, MT_MCU_CMD_WAKE_RX_PCIE);
558
559 /* put dma enabled */
560 mt76_set(dev, MT_WFDMA0_GLO_CFG,
561 MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN);
562
563 mt76_worker_enable(&mdev->tx_worker);
564
565 mt76_for_each_q_rx(mdev, i) {
566 napi_enable(&mdev->napi[i]);
567 }
568 napi_enable(&mdev->tx_napi);
569
570 local_bh_disable();
571 mt76_for_each_q_rx(mdev, i) {
572 napi_schedule(&mdev->napi[i]);
573 }
574 napi_schedule(&mdev->tx_napi);
575 local_bh_enable();
576
577 mt76_connac_mcu_set_hif_suspend(mdev, false, false);
578 ret = wait_event_timeout(dev->wait,
579 dev->hif_resumed, 3 * HZ);
580 if (!ret) {
581 err = -ETIMEDOUT;
582 goto failed;
583 }
584
585 /* restore previous ds setting */
586 if (!pm->ds_enable)
587 mt7925_mcu_set_deep_sleep(dev, false);
588
589 mt7925_regd_update(dev);
590 failed:
591 pm->suspended = false;
592
593 if (err < 0)
594 mt792x_reset(&dev->mt76);
595
596 return err;
597 }
598 #endif
599
mt7925_pci_shutdown(struct pci_dev * pdev)600 static void mt7925_pci_shutdown(struct pci_dev *pdev)
601 {
602 mt7925_pci_remove(pdev);
603 }
604
605 static DEFINE_SIMPLE_DEV_PM_OPS(mt7925_pm_ops, mt7925_pci_suspend, mt7925_pci_resume);
606
607 static struct pci_driver mt7925_pci_driver = {
608 .name = KBUILD_MODNAME,
609 .id_table = mt7925_pci_device_table,
610 .probe = mt7925_pci_probe,
611 .remove = mt7925_pci_remove,
612 .shutdown = mt7925_pci_shutdown,
613 .driver.pm = pm_sleep_ptr(&mt7925_pm_ops),
614 };
615
616 module_pci_driver(mt7925_pci_driver);
617
618 MODULE_DEVICE_TABLE(pci, mt7925_pci_device_table);
619 MODULE_FIRMWARE(MT7925_FIRMWARE_WM);
620 MODULE_FIRMWARE(MT7925_ROM_PATCH);
621 MODULE_AUTHOR("Deren Wu <deren.wu@mediatek.com>");
622 MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>");
623 MODULE_DESCRIPTION("MediaTek MT7925E (PCIe) wireless driver");
624 MODULE_LICENSE("Dual BSD/GPL");
625 #if defined(__FreeBSD__)
626 MODULE_VERSION(mt7925_pci, 1);
627 MODULE_DEPEND(mt7925_pci, linuxkpi, 1, 1, 1);
628 MODULE_DEPEND(mt7925_pci, linuxkpi_wlan, 1, 1, 1);
629 MODULE_DEPEND(mt7925_pci, mt76_core, 1, 1, 1);
630 #endif
631