1 // SPDX-License-Identifier: ISC
2 /* Copyright (C) 2020 MediaTek Inc. */
3
4 #if defined(__FreeBSD__)
5 #define LINUXKPI_PARAM_PREFIX mt7915_
6 #endif
7
8 #include <linux/kernel.h>
9 #include <linux/module.h>
10 #include <linux/platform_device.h>
11 #include <linux/rtnetlink.h>
12 #include <linux/pci.h>
13
14 #include "mt7915.h"
15 #include "mac.h"
16 #include "mcu.h"
17 #include "../trace.h"
18 #include "../dma.h"
19
20 static bool wed_enable;
21 module_param(wed_enable, bool, 0644);
22 MODULE_PARM_DESC(wed_enable, "Enable Wireless Ethernet Dispatch support");
23
24 static const u32 mt7915_reg[] = {
25 [INT_SOURCE_CSR] = 0xd7010,
26 [INT_MASK_CSR] = 0xd7014,
27 [INT1_SOURCE_CSR] = 0xd7088,
28 [INT1_MASK_CSR] = 0xd708c,
29 [INT_MCU_CMD_SOURCE] = 0xd51f0,
30 [INT_MCU_CMD_EVENT] = 0x3108,
31 [WFDMA0_ADDR] = 0xd4000,
32 [WFDMA0_PCIE1_ADDR] = 0xd8000,
33 [WFDMA_EXT_CSR_ADDR] = 0xd7000,
34 [CBTOP1_PHY_END] = 0x77ffffff,
35 [INFRA_MCU_ADDR_END] = 0x7c3fffff,
36 [FW_ASSERT_STAT_ADDR] = 0x219848,
37 [FW_EXCEPT_TYPE_ADDR] = 0x21987c,
38 [FW_EXCEPT_COUNT_ADDR] = 0x219848,
39 [FW_CIRQ_COUNT_ADDR] = 0x216f94,
40 [FW_CIRQ_IDX_ADDR] = 0x216ef8,
41 [FW_CIRQ_LISR_ADDR] = 0x2170ac,
42 [FW_TASK_ID_ADDR] = 0x216f90,
43 [FW_TASK_IDX_ADDR] = 0x216f9c,
44 [FW_TASK_QID1_ADDR] = 0x219680,
45 [FW_TASK_QID2_ADDR] = 0x219760,
46 [FW_TASK_START_ADDR] = 0x219558,
47 [FW_TASK_END_ADDR] = 0x219554,
48 [FW_TASK_SIZE_ADDR] = 0x219560,
49 [FW_LAST_MSG_ID_ADDR] = 0x216f70,
50 [FW_EINT_INFO_ADDR] = 0x219818,
51 [FW_SCHED_INFO_ADDR] = 0x219828,
52 [SWDEF_BASE_ADDR] = 0x41f200,
53 [TXQ_WED_RING_BASE] = 0xd7300,
54 [RXQ_WED_RING_BASE] = 0xd7410,
55 [RXQ_WED_DATA_RING_BASE] = 0xd4500,
56 };
57
58 static const u32 mt7916_reg[] = {
59 [INT_SOURCE_CSR] = 0xd4200,
60 [INT_MASK_CSR] = 0xd4204,
61 [INT1_SOURCE_CSR] = 0xd8200,
62 [INT1_MASK_CSR] = 0xd8204,
63 [INT_MCU_CMD_SOURCE] = 0xd41f0,
64 [INT_MCU_CMD_EVENT] = 0x2108,
65 [WFDMA0_ADDR] = 0xd4000,
66 [WFDMA0_PCIE1_ADDR] = 0xd8000,
67 [WFDMA_EXT_CSR_ADDR] = 0xd7000,
68 [CBTOP1_PHY_END] = 0x7fffffff,
69 [INFRA_MCU_ADDR_END] = 0x7c085fff,
70 [FW_ASSERT_STAT_ADDR] = 0x02204c14,
71 [FW_EXCEPT_TYPE_ADDR] = 0x022051a4,
72 [FW_EXCEPT_COUNT_ADDR] = 0x022050bc,
73 [FW_CIRQ_COUNT_ADDR] = 0x022001ac,
74 [FW_CIRQ_IDX_ADDR] = 0x02204f84,
75 [FW_CIRQ_LISR_ADDR] = 0x022050d0,
76 [FW_TASK_ID_ADDR] = 0x0220406c,
77 [FW_TASK_IDX_ADDR] = 0x0220500c,
78 [FW_TASK_QID1_ADDR] = 0x022028c8,
79 [FW_TASK_QID2_ADDR] = 0x02202a38,
80 [FW_TASK_START_ADDR] = 0x0220286c,
81 [FW_TASK_END_ADDR] = 0x02202870,
82 [FW_TASK_SIZE_ADDR] = 0x02202878,
83 [FW_LAST_MSG_ID_ADDR] = 0x02204fe8,
84 [FW_EINT_INFO_ADDR] = 0x0220525c,
85 [FW_SCHED_INFO_ADDR] = 0x0220516c,
86 [SWDEF_BASE_ADDR] = 0x411400,
87 [TXQ_WED_RING_BASE] = 0xd7300,
88 [RXQ_WED_RING_BASE] = 0xd7410,
89 [RXQ_WED_DATA_RING_BASE] = 0xd4540,
90 };
91
92 static const u32 mt7986_reg[] = {
93 [INT_SOURCE_CSR] = 0x24200,
94 [INT_MASK_CSR] = 0x24204,
95 [INT1_SOURCE_CSR] = 0x28200,
96 [INT1_MASK_CSR] = 0x28204,
97 [INT_MCU_CMD_SOURCE] = 0x241f0,
98 [INT_MCU_CMD_EVENT] = 0x54000108,
99 [WFDMA0_ADDR] = 0x24000,
100 [WFDMA0_PCIE1_ADDR] = 0x28000,
101 [WFDMA_EXT_CSR_ADDR] = 0x27000,
102 [CBTOP1_PHY_END] = 0x7fffffff,
103 [INFRA_MCU_ADDR_END] = 0x7c085fff,
104 [FW_ASSERT_STAT_ADDR] = 0x02204b54,
105 [FW_EXCEPT_TYPE_ADDR] = 0x022050dc,
106 [FW_EXCEPT_COUNT_ADDR] = 0x02204ffc,
107 [FW_CIRQ_COUNT_ADDR] = 0x022001ac,
108 [FW_CIRQ_IDX_ADDR] = 0x02204ec4,
109 [FW_CIRQ_LISR_ADDR] = 0x02205010,
110 [FW_TASK_ID_ADDR] = 0x02204fac,
111 [FW_TASK_IDX_ADDR] = 0x02204f4c,
112 [FW_TASK_QID1_ADDR] = 0x02202814,
113 [FW_TASK_QID2_ADDR] = 0x02202984,
114 [FW_TASK_START_ADDR] = 0x022027b8,
115 [FW_TASK_END_ADDR] = 0x022027bc,
116 [FW_TASK_SIZE_ADDR] = 0x022027c4,
117 [FW_LAST_MSG_ID_ADDR] = 0x02204f28,
118 [FW_EINT_INFO_ADDR] = 0x02205194,
119 [FW_SCHED_INFO_ADDR] = 0x022051a4,
120 [SWDEF_BASE_ADDR] = 0x411400,
121 [TXQ_WED_RING_BASE] = 0x24420,
122 [RXQ_WED_RING_BASE] = 0x24520,
123 [RXQ_WED_DATA_RING_BASE] = 0x24540,
124 };
125
126 static const u32 mt7915_offs[] = {
127 [TMAC_CDTR] = 0x090,
128 [TMAC_ODTR] = 0x094,
129 [TMAC_ATCR] = 0x098,
130 [TMAC_TRCR0] = 0x09c,
131 [TMAC_ICR0] = 0x0a4,
132 [TMAC_ICR1] = 0x0b4,
133 [TMAC_CTCR0] = 0x0f4,
134 [TMAC_TFCR0] = 0x1e0,
135 [MDP_BNRCFR0] = 0x070,
136 [MDP_BNRCFR1] = 0x074,
137 [ARB_DRNGR0] = 0x194,
138 [ARB_SCR] = 0x080,
139 [RMAC_MIB_AIRTIME14] = 0x3b8,
140 [AGG_AWSCR0] = 0x05c,
141 [AGG_PCR0] = 0x06c,
142 [AGG_ACR0] = 0x084,
143 [AGG_ACR4] = 0x08c,
144 [AGG_MRCR] = 0x098,
145 [AGG_ATCR0] = 0x0ec,
146 [AGG_ATCR1] = 0x0f0,
147 [AGG_ATCR3] = 0x0f4,
148 [LPON_UTTR0] = 0x080,
149 [LPON_UTTR1] = 0x084,
150 [LPON_FRCR] = 0x314,
151 [MIB_SDR3] = 0x014,
152 [MIB_SDR4] = 0x018,
153 [MIB_SDR5] = 0x01c,
154 [MIB_SDR7] = 0x024,
155 [MIB_SDR8] = 0x028,
156 [MIB_SDR9] = 0x02c,
157 [MIB_SDR10] = 0x030,
158 [MIB_SDR11] = 0x034,
159 [MIB_SDR12] = 0x038,
160 [MIB_SDR13] = 0x03c,
161 [MIB_SDR14] = 0x040,
162 [MIB_SDR15] = 0x044,
163 [MIB_SDR16] = 0x048,
164 [MIB_SDR17] = 0x04c,
165 [MIB_SDR18] = 0x050,
166 [MIB_SDR19] = 0x054,
167 [MIB_SDR20] = 0x058,
168 [MIB_SDR21] = 0x05c,
169 [MIB_SDR22] = 0x060,
170 [MIB_SDR23] = 0x064,
171 [MIB_SDR24] = 0x068,
172 [MIB_SDR25] = 0x06c,
173 [MIB_SDR27] = 0x074,
174 [MIB_SDR28] = 0x078,
175 [MIB_SDR29] = 0x07c,
176 [MIB_SDRVEC] = 0x080,
177 [MIB_SDR31] = 0x084,
178 [MIB_SDR32] = 0x088,
179 [MIB_SDRMUBF] = 0x090,
180 [MIB_DR8] = 0x0c0,
181 [MIB_DR9] = 0x0c4,
182 [MIB_DR11] = 0x0cc,
183 [MIB_MB_SDR0] = 0x100,
184 [MIB_MB_SDR1] = 0x104,
185 [TX_AGG_CNT] = 0x0a8,
186 [TX_AGG_CNT2] = 0x164,
187 [MIB_ARNG] = 0x4b8,
188 [WTBLON_TOP_WDUCR] = 0x0,
189 [WTBL_UPDATE] = 0x030,
190 [PLE_FL_Q_EMPTY] = 0x0b0,
191 [PLE_FL_Q_CTRL] = 0x1b0,
192 [PLE_AC_QEMPTY] = 0x500,
193 [PLE_FREEPG_CNT] = 0x100,
194 [PLE_FREEPG_HEAD_TAIL] = 0x104,
195 [PLE_PG_HIF_GROUP] = 0x110,
196 [PLE_HIF_PG_INFO] = 0x114,
197 [AC_OFFSET] = 0x040,
198 [ETBF_PAR_RPT0] = 0x068,
199 };
200
201 static const u32 mt7916_offs[] = {
202 [TMAC_CDTR] = 0x0c8,
203 [TMAC_ODTR] = 0x0cc,
204 [TMAC_ATCR] = 0x00c,
205 [TMAC_TRCR0] = 0x010,
206 [TMAC_ICR0] = 0x014,
207 [TMAC_ICR1] = 0x018,
208 [TMAC_CTCR0] = 0x114,
209 [TMAC_TFCR0] = 0x0e4,
210 [MDP_BNRCFR0] = 0x090,
211 [MDP_BNRCFR1] = 0x094,
212 [ARB_DRNGR0] = 0x1e0,
213 [ARB_SCR] = 0x000,
214 [RMAC_MIB_AIRTIME14] = 0x0398,
215 [AGG_AWSCR0] = 0x030,
216 [AGG_PCR0] = 0x040,
217 [AGG_ACR0] = 0x054,
218 [AGG_ACR4] = 0x05c,
219 [AGG_MRCR] = 0x068,
220 [AGG_ATCR0] = 0x1a4,
221 [AGG_ATCR1] = 0x1a8,
222 [AGG_ATCR3] = 0x080,
223 [LPON_UTTR0] = 0x360,
224 [LPON_UTTR1] = 0x364,
225 [LPON_FRCR] = 0x37c,
226 [MIB_SDR3] = 0x698,
227 [MIB_SDR4] = 0x788,
228 [MIB_SDR5] = 0x780,
229 [MIB_SDR7] = 0x5a8,
230 [MIB_SDR8] = 0x78c,
231 [MIB_SDR9] = 0x024,
232 [MIB_SDR10] = 0x76c,
233 [MIB_SDR11] = 0x790,
234 [MIB_SDR12] = 0x558,
235 [MIB_SDR13] = 0x560,
236 [MIB_SDR14] = 0x564,
237 [MIB_SDR15] = 0x568,
238 [MIB_SDR16] = 0x7fc,
239 [MIB_SDR17] = 0x800,
240 [MIB_SDR18] = 0x030,
241 [MIB_SDR19] = 0x5ac,
242 [MIB_SDR20] = 0x5b0,
243 [MIB_SDR21] = 0x5b4,
244 [MIB_SDR22] = 0x770,
245 [MIB_SDR23] = 0x774,
246 [MIB_SDR24] = 0x778,
247 [MIB_SDR25] = 0x77c,
248 [MIB_SDR27] = 0x080,
249 [MIB_SDR28] = 0x084,
250 [MIB_SDR29] = 0x650,
251 [MIB_SDRVEC] = 0x5a8,
252 [MIB_SDR31] = 0x55c,
253 [MIB_SDR32] = 0x7a8,
254 [MIB_SDRMUBF] = 0x7ac,
255 [MIB_DR8] = 0x56c,
256 [MIB_DR9] = 0x570,
257 [MIB_DR11] = 0x574,
258 [MIB_MB_SDR0] = 0x688,
259 [MIB_MB_SDR1] = 0x690,
260 [TX_AGG_CNT] = 0x7dc,
261 [TX_AGG_CNT2] = 0x7ec,
262 [MIB_ARNG] = 0x0b0,
263 [WTBLON_TOP_WDUCR] = 0x200,
264 [WTBL_UPDATE] = 0x230,
265 [PLE_FL_Q_EMPTY] = 0x360,
266 [PLE_FL_Q_CTRL] = 0x3e0,
267 [PLE_AC_QEMPTY] = 0x600,
268 [PLE_FREEPG_CNT] = 0x380,
269 [PLE_FREEPG_HEAD_TAIL] = 0x384,
270 [PLE_PG_HIF_GROUP] = 0x00c,
271 [PLE_HIF_PG_INFO] = 0x388,
272 [AC_OFFSET] = 0x080,
273 [ETBF_PAR_RPT0] = 0x100,
274 };
275
276 static const struct mt76_connac_reg_map mt7915_reg_map[] = {
277 { 0x00400000, 0x80000, 0x10000 }, /* WF_MCU_SYSRAM */
278 { 0x00410000, 0x90000, 0x10000 }, /* WF_MCU_SYSRAM (configure regs) */
279 { 0x40000000, 0x70000, 0x10000 }, /* WF_UMAC_SYSRAM */
280 { 0x54000000, 0x02000, 0x01000 }, /* WFDMA PCIE0 MCU DMA0 */
281 { 0x55000000, 0x03000, 0x01000 }, /* WFDMA PCIE0 MCU DMA1 */
282 { 0x58000000, 0x06000, 0x01000 }, /* WFDMA PCIE1 MCU DMA0 (MEM_DMA) */
283 { 0x59000000, 0x07000, 0x01000 }, /* WFDMA PCIE1 MCU DMA1 */
284 { 0x7c000000, 0xf0000, 0x10000 }, /* CONN_INFRA */
285 { 0x7c020000, 0xd0000, 0x10000 }, /* CONN_INFRA, WFDMA */
286 { 0x80020000, 0xb0000, 0x10000 }, /* WF_TOP_MISC_OFF */
287 { 0x81020000, 0xc0000, 0x10000 }, /* WF_TOP_MISC_ON */
288 { 0x820c0000, 0x08000, 0x04000 }, /* WF_UMAC_TOP (PLE) */
289 { 0x820c8000, 0x0c000, 0x02000 }, /* WF_UMAC_TOP (PSE) */
290 { 0x820cc000, 0x0e000, 0x02000 }, /* WF_UMAC_TOP (PP) */
291 { 0x820ce000, 0x21c00, 0x00200 }, /* WF_LMAC_TOP (WF_SEC) */
292 { 0x820cf000, 0x22000, 0x01000 }, /* WF_LMAC_TOP (WF_PF) */
293 { 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */
294 { 0x820e0000, 0x20000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */
295 { 0x820e1000, 0x20400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */
296 { 0x820e2000, 0x20800, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */
297 { 0x820e3000, 0x20c00, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */
298 { 0x820e4000, 0x21000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */
299 { 0x820e5000, 0x21400, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */
300 { 0x820e7000, 0x21e00, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */
301 { 0x820e9000, 0x23400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */
302 { 0x820ea000, 0x24000, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */
303 { 0x820eb000, 0x24200, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */
304 { 0x820ec000, 0x24600, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_INT) */
305 { 0x820ed000, 0x24800, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */
306 { 0x820f0000, 0xa0000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */
307 { 0x820f1000, 0xa0600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */
308 { 0x820f2000, 0xa0800, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */
309 { 0x820f3000, 0xa0c00, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */
310 { 0x820f4000, 0xa1000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */
311 { 0x820f5000, 0xa1400, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */
312 { 0x820f7000, 0xa1e00, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */
313 { 0x820f9000, 0xa3400, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */
314 { 0x820fa000, 0xa4000, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */
315 { 0x820fb000, 0xa4200, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */
316 { 0x820fc000, 0xa4600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_INT) */
317 { 0x820fd000, 0xa4800, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */
318 { 0x0, 0x0, 0x0 }, /* imply end of search */
319 };
320
321 static const struct mt76_connac_reg_map mt7916_reg_map[] = {
322 { 0x54000000, 0x02000, 0x01000 }, /* WFDMA_0 (PCIE0 MCU DMA0) */
323 { 0x55000000, 0x03000, 0x01000 }, /* WFDMA_1 (PCIE0 MCU DMA1) */
324 { 0x56000000, 0x04000, 0x01000 }, /* WFDMA_2 (Reserved) */
325 { 0x57000000, 0x05000, 0x01000 }, /* WFDMA_3 (MCU wrap CR) */
326 { 0x58000000, 0x06000, 0x01000 }, /* WFDMA_4 (PCIE1 MCU DMA0) */
327 { 0x59000000, 0x07000, 0x01000 }, /* WFDMA_5 (PCIE1 MCU DMA1) */
328 { 0x820c0000, 0x08000, 0x04000 }, /* WF_UMAC_TOP (PLE) */
329 { 0x820c8000, 0x0c000, 0x02000 }, /* WF_UMAC_TOP (PSE) */
330 { 0x820cc000, 0x0e000, 0x02000 }, /* WF_UMAC_TOP (PP) */
331 { 0x820e0000, 0x20000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */
332 { 0x820e1000, 0x20400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */
333 { 0x820e2000, 0x20800, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */
334 { 0x820e3000, 0x20c00, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */
335 { 0x820e4000, 0x21000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */
336 { 0x820e5000, 0x21400, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */
337 { 0x820ce000, 0x21c00, 0x00200 }, /* WF_LMAC_TOP (WF_SEC) */
338 { 0x820e7000, 0x21e00, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */
339 { 0x820cf000, 0x22000, 0x01000 }, /* WF_LMAC_TOP (WF_PF) */
340 { 0x820e9000, 0x23400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */
341 { 0x820ea000, 0x24000, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */
342 { 0x820eb000, 0x24200, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */
343 { 0x820ec000, 0x24600, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_INT) */
344 { 0x820ed000, 0x24800, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */
345 { 0x820ca000, 0x26000, 0x02000 }, /* WF_LMAC_TOP BN0 (WF_MUCOP) */
346 { 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */
347 { 0x00400000, 0x80000, 0x10000 }, /* WF_MCU_SYSRAM */
348 { 0x00410000, 0x90000, 0x10000 }, /* WF_MCU_SYSRAM (configure cr) */
349 { 0x820f0000, 0xa0000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */
350 { 0x820f1000, 0xa0600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */
351 { 0x820f2000, 0xa0800, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */
352 { 0x820f3000, 0xa0c00, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */
353 { 0x820f4000, 0xa1000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */
354 { 0x820f5000, 0xa1400, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */
355 { 0x820f7000, 0xa1e00, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */
356 { 0x820f9000, 0xa3400, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */
357 { 0x820fa000, 0xa4000, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */
358 { 0x820fb000, 0xa4200, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */
359 { 0x820fc000, 0xa4600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_INT) */
360 { 0x820fd000, 0xa4800, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */
361 { 0x820c4000, 0xa8000, 0x01000 }, /* WF_LMAC_TOP (WF_UWTBL ) */
362 { 0x820b0000, 0xae000, 0x01000 }, /* [APB2] WFSYS_ON */
363 { 0x80020000, 0xb0000, 0x10000 }, /* WF_TOP_MISC_OFF */
364 { 0x81020000, 0xc0000, 0x10000 }, /* WF_TOP_MISC_ON */
365 { 0x0, 0x0, 0x0 }, /* imply end of search */
366 };
367
368 static const struct mt76_connac_reg_map mt7986_reg_map[] = {
369 { 0x54000000, 0x402000, 0x01000 }, /* WFDMA_0 (PCIE0 MCU DMA0) */
370 { 0x55000000, 0x403000, 0x01000 }, /* WFDMA_1 (PCIE0 MCU DMA1) */
371 { 0x56000000, 0x404000, 0x01000 }, /* WFDMA_2 (Reserved) */
372 { 0x57000000, 0x405000, 0x01000 }, /* WFDMA_3 (MCU wrap CR) */
373 { 0x58000000, 0x406000, 0x01000 }, /* WFDMA_4 (PCIE1 MCU DMA0) */
374 { 0x59000000, 0x407000, 0x01000 }, /* WFDMA_5 (PCIE1 MCU DMA1) */
375 { 0x820c0000, 0x408000, 0x04000 }, /* WF_UMAC_TOP (PLE) */
376 { 0x820c8000, 0x40c000, 0x02000 }, /* WF_UMAC_TOP (PSE) */
377 { 0x820cc000, 0x40e000, 0x02000 }, /* WF_UMAC_TOP (PP) */
378 { 0x820e0000, 0x420000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */
379 { 0x820e1000, 0x420400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */
380 { 0x820e2000, 0x420800, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */
381 { 0x820e3000, 0x420c00, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */
382 { 0x820e4000, 0x421000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */
383 { 0x820e5000, 0x421400, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */
384 { 0x820ce000, 0x421c00, 0x00200 }, /* WF_LMAC_TOP (WF_SEC) */
385 { 0x820e7000, 0x421e00, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */
386 { 0x820cf000, 0x422000, 0x01000 }, /* WF_LMAC_TOP (WF_PF) */
387 { 0x820e9000, 0x423400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */
388 { 0x820ea000, 0x424000, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */
389 { 0x820eb000, 0x424200, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */
390 { 0x820ec000, 0x424600, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_INT) */
391 { 0x820ed000, 0x424800, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */
392 { 0x820ca000, 0x426000, 0x02000 }, /* WF_LMAC_TOP BN0 (WF_MUCOP) */
393 { 0x820d0000, 0x430000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */
394 { 0x00400000, 0x480000, 0x10000 }, /* WF_MCU_SYSRAM */
395 { 0x00410000, 0x490000, 0x10000 }, /* WF_MCU_SYSRAM */
396 { 0x820f0000, 0x4a0000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */
397 { 0x820f1000, 0x4a0600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */
398 { 0x820f2000, 0x4a0800, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */
399 { 0x820f3000, 0x4a0c00, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */
400 { 0x820f4000, 0x4a1000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */
401 { 0x820f5000, 0x4a1400, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */
402 { 0x820f7000, 0x4a1e00, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */
403 { 0x820f9000, 0x4a3400, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */
404 { 0x820fa000, 0x4a4000, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */
405 { 0x820fb000, 0x4a4200, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */
406 { 0x820fc000, 0x4a4600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_INT) */
407 { 0x820fd000, 0x4a4800, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */
408 { 0x820c4000, 0x4a8000, 0x01000 }, /* WF_LMAC_TOP (WF_UWTBL ) */
409 { 0x820b0000, 0x4ae000, 0x01000 }, /* [APB2] WFSYS_ON */
410 { 0x80020000, 0x4b0000, 0x10000 }, /* WF_TOP_MISC_OFF */
411 { 0x81020000, 0x4c0000, 0x10000 }, /* WF_TOP_MISC_ON */
412 { 0x89000000, 0x4d0000, 0x01000 }, /* WF_MCU_CFG_ON */
413 { 0x89010000, 0x4d1000, 0x01000 }, /* WF_MCU_CIRQ */
414 { 0x89020000, 0x4d2000, 0x01000 }, /* WF_MCU_GPT */
415 { 0x89030000, 0x4d3000, 0x01000 }, /* WF_MCU_WDT */
416 { 0x80010000, 0x4d4000, 0x01000 }, /* WF_AXIDMA */
417 { 0x0, 0x0, 0x0 }, /* imply end of search */
418 };
419
mt7915_reg_map_l1(struct mt7915_dev * dev,u32 addr)420 static u32 mt7915_reg_map_l1(struct mt7915_dev *dev, u32 addr)
421 {
422 u32 offset = FIELD_GET(MT_HIF_REMAP_L1_OFFSET, addr);
423 u32 base = FIELD_GET(MT_HIF_REMAP_L1_BASE, addr);
424 u32 l1_remap;
425
426 if (is_mt798x(&dev->mt76))
427 return MT_CONN_INFRA_OFFSET(addr);
428
429 l1_remap = is_mt7915(&dev->mt76) ?
430 MT_HIF_REMAP_L1 : MT_HIF_REMAP_L1_MT7916;
431
432 dev->bus_ops->rmw(&dev->mt76, l1_remap,
433 MT_HIF_REMAP_L1_MASK,
434 FIELD_PREP(MT_HIF_REMAP_L1_MASK, base));
435 /* use read to push write */
436 dev->bus_ops->rr(&dev->mt76, l1_remap);
437
438 return MT_HIF_REMAP_BASE_L1 + offset;
439 }
440
mt7915_reg_map_l2(struct mt7915_dev * dev,u32 addr)441 static u32 mt7915_reg_map_l2(struct mt7915_dev *dev, u32 addr)
442 {
443 u32 offset, base;
444
445 if (is_mt7915(&dev->mt76)) {
446 offset = FIELD_GET(MT_HIF_REMAP_L2_OFFSET, addr);
447 base = FIELD_GET(MT_HIF_REMAP_L2_BASE, addr);
448
449 dev->bus_ops->rmw(&dev->mt76, MT_HIF_REMAP_L2,
450 MT_HIF_REMAP_L2_MASK,
451 FIELD_PREP(MT_HIF_REMAP_L2_MASK, base));
452
453 /* use read to push write */
454 dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_L2);
455 } else {
456 u32 ofs = is_mt798x(&dev->mt76) ? 0x400000 : 0;
457
458 offset = FIELD_GET(MT_HIF_REMAP_L2_OFFSET_MT7916, addr);
459 base = FIELD_GET(MT_HIF_REMAP_L2_BASE_MT7916, addr);
460
461 dev->bus_ops->rmw(&dev->mt76, MT_HIF_REMAP_L2_MT7916 + ofs,
462 MT_HIF_REMAP_L2_MASK_MT7916,
463 FIELD_PREP(MT_HIF_REMAP_L2_MASK_MT7916, base));
464
465 /* use read to push write */
466 dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_L2_MT7916 + ofs);
467
468 offset += (MT_HIF_REMAP_BASE_L2_MT7916 + ofs);
469 }
470
471 return offset;
472 }
473
__mt7915_reg_addr(struct mt7915_dev * dev,u32 addr)474 static u32 __mt7915_reg_addr(struct mt7915_dev *dev, u32 addr)
475 {
476 int i;
477
478 if (addr < 0x100000)
479 return addr;
480
481 if (!dev->reg.map) {
482 dev_err(dev->mt76.dev, "err: reg_map is null\n");
483 return addr;
484 }
485
486 for (i = 0; i < dev->reg.map_size; i++) {
487 u32 ofs;
488
489 if (addr < dev->reg.map[i].phys)
490 continue;
491
492 ofs = addr - dev->reg.map[i].phys;
493 if (ofs >= dev->reg.map[i].size)
494 continue;
495
496 return dev->reg.map[i].maps + ofs;
497 }
498
499 return 0;
500 }
501
__mt7915_reg_remap_addr(struct mt7915_dev * dev,u32 addr)502 static u32 __mt7915_reg_remap_addr(struct mt7915_dev *dev, u32 addr)
503 {
504 if ((addr >= MT_INFRA_BASE && addr < MT_WFSYS0_PHY_START) ||
505 (addr >= MT_WFSYS0_PHY_START && addr < MT_WFSYS1_PHY_START) ||
506 (addr >= MT_WFSYS1_PHY_START && addr <= MT_WFSYS1_PHY_END))
507 return mt7915_reg_map_l1(dev, addr);
508
509 if (dev_is_pci(dev->mt76.dev) &&
510 ((addr >= MT_CBTOP1_PHY_START && addr <= MT_CBTOP1_PHY_END) ||
511 addr >= MT_CBTOP2_PHY_START))
512 return mt7915_reg_map_l1(dev, addr);
513
514 /* CONN_INFRA: covert to phyiscal addr and use layer 1 remap */
515 if (addr >= MT_INFRA_MCU_START && addr <= MT_INFRA_MCU_END) {
516 addr = addr - MT_INFRA_MCU_START + MT_INFRA_BASE;
517 return mt7915_reg_map_l1(dev, addr);
518 }
519
520 return mt7915_reg_map_l2(dev, addr);
521 }
522
mt7915_memcpy_fromio(struct mt7915_dev * dev,void * buf,u32 offset,size_t len)523 void mt7915_memcpy_fromio(struct mt7915_dev *dev, void *buf, u32 offset,
524 size_t len)
525 {
526 u32 addr = __mt7915_reg_addr(dev, offset);
527
528 if (addr) {
529 #if defined(__linux__)
530 memcpy_fromio(buf, dev->mt76.mmio.regs + addr, len);
531 #elif defined(__FreeBSD__)
532 memcpy_fromio(buf, (u8 *)dev->mt76.mmio.regs + addr, len);
533 #endif
534 return;
535 }
536
537 spin_lock_bh(&dev->reg_lock);
538 #if defined(__linux__)
539 memcpy_fromio(buf, dev->mt76.mmio.regs +
540 #elif defined(__FreeBSD__)
541 memcpy_fromio(buf, (u8 *)dev->mt76.mmio.regs +
542 #endif
543 __mt7915_reg_remap_addr(dev, offset), len);
544 spin_unlock_bh(&dev->reg_lock);
545 }
546
mt7915_rr(struct mt76_dev * mdev,u32 offset)547 static u32 mt7915_rr(struct mt76_dev *mdev, u32 offset)
548 {
549 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76);
550 u32 addr = __mt7915_reg_addr(dev, offset), val;
551
552 if (addr)
553 return dev->bus_ops->rr(mdev, addr);
554
555 spin_lock_bh(&dev->reg_lock);
556 val = dev->bus_ops->rr(mdev, __mt7915_reg_remap_addr(dev, offset));
557 spin_unlock_bh(&dev->reg_lock);
558
559 return val;
560 }
561
mt7915_wr(struct mt76_dev * mdev,u32 offset,u32 val)562 static void mt7915_wr(struct mt76_dev *mdev, u32 offset, u32 val)
563 {
564 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76);
565 u32 addr = __mt7915_reg_addr(dev, offset);
566
567 if (addr) {
568 dev->bus_ops->wr(mdev, addr, val);
569 return;
570 }
571
572 spin_lock_bh(&dev->reg_lock);
573 dev->bus_ops->wr(mdev, __mt7915_reg_remap_addr(dev, offset), val);
574 spin_unlock_bh(&dev->reg_lock);
575 }
576
mt7915_rmw(struct mt76_dev * mdev,u32 offset,u32 mask,u32 val)577 static u32 mt7915_rmw(struct mt76_dev *mdev, u32 offset, u32 mask, u32 val)
578 {
579 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76);
580 u32 addr = __mt7915_reg_addr(dev, offset);
581
582 if (addr)
583 return dev->bus_ops->rmw(mdev, addr, mask, val);
584
585 spin_lock_bh(&dev->reg_lock);
586 val = dev->bus_ops->rmw(mdev, __mt7915_reg_remap_addr(dev, offset), mask, val);
587 spin_unlock_bh(&dev->reg_lock);
588
589 return val;
590 }
591
592 #ifdef CONFIG_NET_MEDIATEK_SOC_WED
mt7915_mmio_wed_update_rx_stats(struct mtk_wed_device * wed,struct mtk_wed_wo_rx_stats * stats)593 static void mt7915_mmio_wed_update_rx_stats(struct mtk_wed_device *wed,
594 struct mtk_wed_wo_rx_stats *stats)
595 {
596 int idx = le16_to_cpu(stats->wlan_idx);
597 struct mt7915_dev *dev;
598 struct mt76_wcid *wcid;
599
600 dev = container_of(wed, struct mt7915_dev, mt76.mmio.wed);
601
602 rcu_read_lock();
603
604 wcid = mt76_wcid_ptr(dev, idx);
605 if (wcid) {
606 wcid->stats.rx_bytes += le32_to_cpu(stats->rx_byte_cnt);
607 wcid->stats.rx_packets += le32_to_cpu(stats->rx_pkt_cnt);
608 wcid->stats.rx_errors += le32_to_cpu(stats->rx_err_cnt);
609 wcid->stats.rx_drops += le32_to_cpu(stats->rx_drop_cnt);
610 }
611
612 rcu_read_unlock();
613 }
614
mt7915_mmio_wed_reset(struct mtk_wed_device * wed)615 static int mt7915_mmio_wed_reset(struct mtk_wed_device *wed)
616 {
617 struct mt76_dev *mdev = container_of(wed, struct mt76_dev, mmio.wed);
618 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76);
619 struct mt76_phy *mphy = &dev->mphy;
620 int ret;
621
622 ASSERT_RTNL();
623
624 if (test_and_set_bit(MT76_STATE_WED_RESET, &mphy->state))
625 return -EBUSY;
626
627 ret = mt7915_mcu_set_ser(dev, SER_RECOVER, SER_SET_RECOVER_L1,
628 mphy->band_idx);
629 if (ret)
630 goto out;
631
632 rtnl_unlock();
633 if (!wait_for_completion_timeout(&mdev->mmio.wed_reset, 20 * HZ)) {
634 dev_err(mdev->dev, "wed reset timeout\n");
635 ret = -ETIMEDOUT;
636 }
637 rtnl_lock();
638 out:
639 clear_bit(MT76_STATE_WED_RESET, &mphy->state);
640
641 return ret;
642 }
643 #endif
644
mt7915_mmio_wed_init(struct mt7915_dev * dev,void * pdev_ptr,bool pci,int * irq)645 int mt7915_mmio_wed_init(struct mt7915_dev *dev, void *pdev_ptr,
646 bool pci, int *irq)
647 {
648 #ifdef CONFIG_NET_MEDIATEK_SOC_WED
649 struct mtk_wed_device *wed = &dev->mt76.mmio.wed;
650 int ret;
651
652 if (!wed_enable)
653 return 0;
654
655 if (pci) {
656 struct pci_dev *pci_dev = pdev_ptr;
657
658 wed->wlan.pci_dev = pci_dev;
659 wed->wlan.bus_type = MTK_WED_BUS_PCIE;
660 wed->wlan.base = devm_ioremap(dev->mt76.dev,
661 pci_resource_start(pci_dev, 0),
662 pci_resource_len(pci_dev, 0));
663 if (!wed->wlan.base)
664 return -ENOMEM;
665
666 wed->wlan.phy_base = pci_resource_start(pci_dev, 0);
667 wed->wlan.wpdma_int = pci_resource_start(pci_dev, 0) +
668 MT_INT_WED_SOURCE_CSR;
669 wed->wlan.wpdma_mask = pci_resource_start(pci_dev, 0) +
670 MT_INT_WED_MASK_CSR;
671 wed->wlan.wpdma_phys = pci_resource_start(pci_dev, 0) +
672 MT_WFDMA_EXT_CSR_BASE;
673 wed->wlan.wpdma_tx = pci_resource_start(pci_dev, 0) +
674 MT_TXQ_WED_RING_BASE;
675 wed->wlan.wpdma_txfree = pci_resource_start(pci_dev, 0) +
676 MT_RXQ_WED_RING_BASE;
677 wed->wlan.wpdma_rx_glo = pci_resource_start(pci_dev, 0) +
678 MT_WPDMA_GLO_CFG;
679 wed->wlan.wpdma_rx = pci_resource_start(pci_dev, 0) +
680 MT_RXQ_WED_DATA_RING_BASE;
681 } else {
682 struct platform_device *plat_dev = pdev_ptr;
683 struct resource *res;
684
685 res = platform_get_resource(plat_dev, IORESOURCE_MEM, 0);
686 if (!res)
687 return 0;
688
689 wed->wlan.platform_dev = plat_dev;
690 wed->wlan.bus_type = MTK_WED_BUS_AXI;
691 wed->wlan.base = devm_ioremap(dev->mt76.dev, res->start,
692 resource_size(res));
693 if (!wed->wlan.base)
694 return -ENOMEM;
695
696 wed->wlan.phy_base = res->start;
697 wed->wlan.wpdma_int = res->start + MT_INT_SOURCE_CSR;
698 wed->wlan.wpdma_mask = res->start + MT_INT_MASK_CSR;
699 wed->wlan.wpdma_tx = res->start + MT_TXQ_WED_RING_BASE;
700 wed->wlan.wpdma_txfree = res->start + MT_RXQ_WED_RING_BASE;
701 wed->wlan.wpdma_rx_glo = res->start + MT_WPDMA_GLO_CFG;
702 wed->wlan.wpdma_rx = res->start + MT_RXQ_WED_DATA_RING_BASE;
703 }
704 wed->wlan.nbuf = MT7915_HW_TOKEN_SIZE;
705 wed->wlan.tx_tbit[0] = is_mt7915(&dev->mt76) ? 4 : 30;
706 wed->wlan.tx_tbit[1] = is_mt7915(&dev->mt76) ? 5 : 31;
707 wed->wlan.txfree_tbit = is_mt798x(&dev->mt76) ? 2 : 1;
708 wed->wlan.token_start = MT7915_TOKEN_SIZE - wed->wlan.nbuf;
709 wed->wlan.wcid_512 = !is_mt7915(&dev->mt76);
710
711 wed->wlan.rx_nbuf = 65536;
712 wed->wlan.rx_npkt = MT7915_WED_RX_TOKEN_SIZE;
713 wed->wlan.rx_size = SKB_WITH_OVERHEAD(MT_RX_BUF_SIZE);
714 if (is_mt7915(&dev->mt76)) {
715 wed->wlan.rx_tbit[0] = 16;
716 wed->wlan.rx_tbit[1] = 17;
717 } else if (is_mt798x(&dev->mt76)) {
718 wed->wlan.rx_tbit[0] = 22;
719 wed->wlan.rx_tbit[1] = 23;
720 } else {
721 wed->wlan.rx_tbit[0] = 18;
722 wed->wlan.rx_tbit[1] = 19;
723 }
724
725 wed->wlan.init_buf = mt7915_wed_init_buf;
726 wed->wlan.offload_enable = mt76_wed_offload_enable;
727 wed->wlan.offload_disable = mt76_wed_offload_disable;
728 wed->wlan.init_rx_buf = mt76_wed_init_rx_buf;
729 wed->wlan.release_rx_buf = mt76_wed_release_rx_buf;
730 wed->wlan.update_wo_rx_stats = mt7915_mmio_wed_update_rx_stats;
731 wed->wlan.reset = mt7915_mmio_wed_reset;
732 wed->wlan.reset_complete = mt76_wed_reset_complete;
733
734 dev->mt76.rx_token_size = wed->wlan.rx_npkt;
735
736 if (mtk_wed_device_attach(wed))
737 return 0;
738
739 *irq = wed->irq;
740 dev->mt76.dma_dev = wed->dev;
741
742 ret = dma_set_mask(wed->dev, DMA_BIT_MASK(32));
743 if (ret)
744 return ret;
745
746 return 1;
747 #else
748 return 0;
749 #endif
750 }
751
mt7915_mmio_init(struct mt76_dev * mdev,void __iomem * mem_base,u32 device_id)752 static int mt7915_mmio_init(struct mt76_dev *mdev,
753 void __iomem *mem_base,
754 u32 device_id)
755 {
756 struct mt76_bus_ops *bus_ops;
757 struct mt7915_dev *dev;
758
759 dev = container_of(mdev, struct mt7915_dev, mt76);
760 mt76_mmio_init(&dev->mt76, mem_base);
761 spin_lock_init(&dev->reg_lock);
762
763 switch (device_id) {
764 case 0x7915:
765 dev->reg.reg_rev = mt7915_reg;
766 dev->reg.offs_rev = mt7915_offs;
767 dev->reg.map = mt7915_reg_map;
768 dev->reg.map_size = ARRAY_SIZE(mt7915_reg_map);
769 break;
770 case 0x7906:
771 dev->reg.reg_rev = mt7916_reg;
772 dev->reg.offs_rev = mt7916_offs;
773 dev->reg.map = mt7916_reg_map;
774 dev->reg.map_size = ARRAY_SIZE(mt7916_reg_map);
775 break;
776 case 0x7981:
777 case 0x7986:
778 dev->reg.reg_rev = mt7986_reg;
779 dev->reg.offs_rev = mt7916_offs;
780 dev->reg.map = mt7986_reg_map;
781 dev->reg.map_size = ARRAY_SIZE(mt7986_reg_map);
782 break;
783 default:
784 return -EINVAL;
785 }
786
787 dev->bus_ops = dev->mt76.bus;
788 bus_ops = devm_kmemdup(dev->mt76.dev, dev->bus_ops, sizeof(*bus_ops),
789 GFP_KERNEL);
790 if (!bus_ops)
791 return -ENOMEM;
792
793 bus_ops->rr = mt7915_rr;
794 bus_ops->wr = mt7915_wr;
795 bus_ops->rmw = mt7915_rmw;
796 dev->mt76.bus = bus_ops;
797
798 mdev->rev = (device_id << 16) |
799 (mt76_rr(dev, MT_HW_REV) & 0xff);
800 dev_dbg(mdev->dev, "ASIC revision: %04x\n", mdev->rev);
801
802 return 0;
803 }
804
mt7915_dual_hif_set_irq_mask(struct mt7915_dev * dev,bool write_reg,u32 clear,u32 set)805 void mt7915_dual_hif_set_irq_mask(struct mt7915_dev *dev,
806 bool write_reg,
807 u32 clear, u32 set)
808 {
809 struct mt76_dev *mdev = &dev->mt76;
810 unsigned long flags;
811
812 spin_lock_irqsave(&mdev->mmio.irq_lock, flags);
813
814 mdev->mmio.irqmask &= ~clear;
815 mdev->mmio.irqmask |= set;
816
817 if (write_reg) {
818 if (mtk_wed_device_active(&mdev->mmio.wed))
819 mtk_wed_device_irq_set_mask(&mdev->mmio.wed,
820 mdev->mmio.irqmask);
821 else
822 mt76_wr(dev, MT_INT_MASK_CSR, mdev->mmio.irqmask);
823 mt76_wr(dev, MT_INT1_MASK_CSR, mdev->mmio.irqmask);
824 }
825
826 spin_unlock_irqrestore(&mdev->mmio.irq_lock, flags);
827 }
828
mt7915_rx_poll_complete(struct mt76_dev * mdev,enum mt76_rxq_id q)829 static void mt7915_rx_poll_complete(struct mt76_dev *mdev,
830 enum mt76_rxq_id q)
831 {
832 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76);
833
834 mt7915_irq_enable(dev, MT_INT_RX(q));
835 }
836
837 /* TODO: support 2/4/6/8 MSI-X vectors */
mt7915_irq_tasklet(struct tasklet_struct * t)838 static void mt7915_irq_tasklet(struct tasklet_struct *t)
839 {
840 struct mt7915_dev *dev = from_tasklet(dev, t, mt76.irq_tasklet);
841 struct mtk_wed_device *wed = &dev->mt76.mmio.wed;
842 u32 intr, intr1, mask;
843
844 if (mtk_wed_device_active(wed)) {
845 mtk_wed_device_irq_set_mask(wed, 0);
846 if (dev->hif2)
847 mt76_wr(dev, MT_INT1_MASK_CSR, 0);
848 intr = mtk_wed_device_irq_get(wed, dev->mt76.mmio.irqmask);
849 } else {
850 mt76_wr(dev, MT_INT_MASK_CSR, 0);
851 if (dev->hif2)
852 mt76_wr(dev, MT_INT1_MASK_CSR, 0);
853
854 intr = mt76_rr(dev, MT_INT_SOURCE_CSR);
855 intr &= dev->mt76.mmio.irqmask;
856 mt76_wr(dev, MT_INT_SOURCE_CSR, intr);
857 }
858
859 if (dev->hif2) {
860 intr1 = mt76_rr(dev, MT_INT1_SOURCE_CSR);
861 intr1 &= dev->mt76.mmio.irqmask;
862 mt76_wr(dev, MT_INT1_SOURCE_CSR, intr1);
863
864 intr |= intr1;
865 }
866
867 trace_dev_irq(&dev->mt76, intr, dev->mt76.mmio.irqmask);
868
869 mask = intr & MT_INT_RX_DONE_ALL;
870 if (intr & MT_INT_TX_DONE_MCU)
871 mask |= MT_INT_TX_DONE_MCU;
872
873 mt7915_irq_disable(dev, mask);
874
875 if (intr & MT_INT_TX_DONE_MCU)
876 napi_schedule(&dev->mt76.tx_napi);
877
878 if (intr & MT_INT_RX(MT_RXQ_MAIN))
879 napi_schedule(&dev->mt76.napi[MT_RXQ_MAIN]);
880
881 if (intr & MT_INT_RX(MT_RXQ_BAND1))
882 napi_schedule(&dev->mt76.napi[MT_RXQ_BAND1]);
883
884 if (intr & MT_INT_RX(MT_RXQ_MCU))
885 napi_schedule(&dev->mt76.napi[MT_RXQ_MCU]);
886
887 if (intr & MT_INT_RX(MT_RXQ_MCU_WA))
888 napi_schedule(&dev->mt76.napi[MT_RXQ_MCU_WA]);
889
890 if (!is_mt7915(&dev->mt76) &&
891 (intr & MT_INT_RX(MT_RXQ_MAIN_WA)))
892 napi_schedule(&dev->mt76.napi[MT_RXQ_MAIN_WA]);
893
894 if (intr & MT_INT_RX(MT_RXQ_BAND1_WA))
895 napi_schedule(&dev->mt76.napi[MT_RXQ_BAND1_WA]);
896
897 if (intr & MT_INT_MCU_CMD) {
898 u32 val = mt76_rr(dev, MT_MCU_CMD);
899
900 mt76_wr(dev, MT_MCU_CMD, val);
901 if (val & (MT_MCU_CMD_ERROR_MASK | MT_MCU_CMD_WDT_MASK)) {
902 dev->recovery.state = val;
903 mt7915_reset(dev);
904 }
905 }
906 }
907
mt7915_irq_handler(int irq,void * dev_instance)908 irqreturn_t mt7915_irq_handler(int irq, void *dev_instance)
909 {
910 struct mt7915_dev *dev = dev_instance;
911 struct mtk_wed_device *wed = &dev->mt76.mmio.wed;
912
913 if (mtk_wed_device_active(wed))
914 mtk_wed_device_irq_set_mask(wed, 0);
915 else
916 mt76_wr(dev, MT_INT_MASK_CSR, 0);
917
918 if (dev->hif2)
919 mt76_wr(dev, MT_INT1_MASK_CSR, 0);
920
921 if (!test_bit(MT76_STATE_INITIALIZED, &dev->mphy.state))
922 return IRQ_NONE;
923
924 tasklet_schedule(&dev->mt76.irq_tasklet);
925
926 return IRQ_HANDLED;
927 }
928
mt7915_mmio_probe(struct device * pdev,void __iomem * mem_base,u32 device_id)929 struct mt7915_dev *mt7915_mmio_probe(struct device *pdev,
930 void __iomem *mem_base, u32 device_id)
931 {
932 static const struct mt76_driver_ops drv_ops = {
933 /* txwi_size = txd size + txp size */
934 .txwi_size = MT_TXD_SIZE + sizeof(struct mt76_connac_fw_txp),
935 .drv_flags = MT_DRV_TXWI_NO_FREE | MT_DRV_HW_MGMT_TXQ |
936 MT_DRV_AMSDU_OFFLOAD,
937 .survey_flags = SURVEY_INFO_TIME_TX |
938 SURVEY_INFO_TIME_RX |
939 SURVEY_INFO_TIME_BSS_RX,
940 .token_size = MT7915_TOKEN_SIZE,
941 .tx_prepare_skb = mt7915_tx_prepare_skb,
942 .tx_complete_skb = mt76_connac_tx_complete_skb,
943 .rx_skb = mt7915_queue_rx_skb,
944 .rx_check = mt7915_rx_check,
945 .rx_poll_complete = mt7915_rx_poll_complete,
946 .sta_add = mt7915_mac_sta_add,
947 .sta_event = mt7915_mac_sta_event,
948 .sta_remove = mt7915_mac_sta_remove,
949 .update_survey = mt7915_update_channel,
950 .set_channel = mt7915_set_channel,
951 };
952 struct mt7915_dev *dev;
953 struct mt76_dev *mdev;
954 int ret;
955
956 mdev = mt76_alloc_device(pdev, sizeof(*dev), &mt7915_ops, &drv_ops);
957 if (!mdev)
958 return ERR_PTR(-ENOMEM);
959
960 dev = container_of(mdev, struct mt7915_dev, mt76);
961
962 ret = mt7915_mmio_init(mdev, mem_base, device_id);
963 if (ret)
964 goto error;
965
966 tasklet_setup(&mdev->irq_tasklet, mt7915_irq_tasklet);
967
968 return dev;
969
970 error:
971 mt76_free_device(&dev->mt76);
972
973 return ERR_PTR(ret);
974 }
975
mt7915_init(void)976 static int __init mt7915_init(void)
977 {
978 int ret;
979
980 ret = pci_register_driver(&mt7915_hif_driver);
981 if (ret)
982 return ret;
983
984 ret = pci_register_driver(&mt7915_pci_driver);
985 if (ret)
986 goto error_pci;
987
988 if (IS_ENABLED(CONFIG_MT798X_WMAC)) {
989 ret = platform_driver_register(&mt798x_wmac_driver);
990 if (ret)
991 goto error_wmac;
992 }
993
994 return 0;
995
996 error_wmac:
997 pci_unregister_driver(&mt7915_pci_driver);
998 error_pci:
999 pci_unregister_driver(&mt7915_hif_driver);
1000
1001 return ret;
1002 }
1003
mt7915_exit(void)1004 static void __exit mt7915_exit(void)
1005 {
1006 if (IS_ENABLED(CONFIG_MT798X_WMAC))
1007 platform_driver_unregister(&mt798x_wmac_driver);
1008
1009 pci_unregister_driver(&mt7915_pci_driver);
1010 pci_unregister_driver(&mt7915_hif_driver);
1011 }
1012
1013 module_init(mt7915_init);
1014 module_exit(mt7915_exit);
1015 MODULE_DESCRIPTION("MediaTek MT7915E MMIO helpers");
1016 MODULE_LICENSE("Dual BSD/GPL");
1017