1 // SPDX-License-Identifier: ISC
2 /* Copyright (C) 2020 MediaTek Inc. */
3
4 #include <linux/kernel.h>
5 #include <linux/module.h>
6 #include <linux/platform_device.h>
7 #include <linux/rtnetlink.h>
8 #include <linux/pci.h>
9
10 #include "mt7915.h"
11 #include "mac.h"
12 #include "mcu.h"
13 #include "../trace.h"
14 #include "../dma.h"
15
16 static bool wed_enable;
17 module_param(wed_enable, bool, 0644);
18 MODULE_PARM_DESC(wed_enable, "Enable Wireless Ethernet Dispatch support");
19
20 static const u32 mt7915_reg[] = {
21 [INT_SOURCE_CSR] = 0xd7010,
22 [INT_MASK_CSR] = 0xd7014,
23 [INT1_SOURCE_CSR] = 0xd7088,
24 [INT1_MASK_CSR] = 0xd708c,
25 [INT_MCU_CMD_SOURCE] = 0xd51f0,
26 [INT_MCU_CMD_EVENT] = 0x3108,
27 [WFDMA0_ADDR] = 0xd4000,
28 [WFDMA0_PCIE1_ADDR] = 0xd8000,
29 [WFDMA_EXT_CSR_ADDR] = 0xd7000,
30 [CBTOP1_PHY_END] = 0x77ffffff,
31 [INFRA_MCU_ADDR_END] = 0x7c3fffff,
32 [FW_ASSERT_STAT_ADDR] = 0x219848,
33 [FW_EXCEPT_TYPE_ADDR] = 0x21987c,
34 [FW_EXCEPT_COUNT_ADDR] = 0x219848,
35 [FW_CIRQ_COUNT_ADDR] = 0x216f94,
36 [FW_CIRQ_IDX_ADDR] = 0x216ef8,
37 [FW_CIRQ_LISR_ADDR] = 0x2170ac,
38 [FW_TASK_ID_ADDR] = 0x216f90,
39 [FW_TASK_IDX_ADDR] = 0x216f9c,
40 [FW_TASK_QID1_ADDR] = 0x219680,
41 [FW_TASK_QID2_ADDR] = 0x219760,
42 [FW_TASK_START_ADDR] = 0x219558,
43 [FW_TASK_END_ADDR] = 0x219554,
44 [FW_TASK_SIZE_ADDR] = 0x219560,
45 [FW_LAST_MSG_ID_ADDR] = 0x216f70,
46 [FW_EINT_INFO_ADDR] = 0x219818,
47 [FW_SCHED_INFO_ADDR] = 0x219828,
48 [SWDEF_BASE_ADDR] = 0x41f200,
49 [TXQ_WED_RING_BASE] = 0xd7300,
50 [RXQ_WED_RING_BASE] = 0xd7410,
51 [RXQ_WED_DATA_RING_BASE] = 0xd4500,
52 };
53
54 static const u32 mt7916_reg[] = {
55 [INT_SOURCE_CSR] = 0xd4200,
56 [INT_MASK_CSR] = 0xd4204,
57 [INT1_SOURCE_CSR] = 0xd8200,
58 [INT1_MASK_CSR] = 0xd8204,
59 [INT_MCU_CMD_SOURCE] = 0xd41f0,
60 [INT_MCU_CMD_EVENT] = 0x2108,
61 [WFDMA0_ADDR] = 0xd4000,
62 [WFDMA0_PCIE1_ADDR] = 0xd8000,
63 [WFDMA_EXT_CSR_ADDR] = 0xd7000,
64 [CBTOP1_PHY_END] = 0x7fffffff,
65 [INFRA_MCU_ADDR_END] = 0x7c085fff,
66 [FW_ASSERT_STAT_ADDR] = 0x02204c14,
67 [FW_EXCEPT_TYPE_ADDR] = 0x022051a4,
68 [FW_EXCEPT_COUNT_ADDR] = 0x022050bc,
69 [FW_CIRQ_COUNT_ADDR] = 0x022001ac,
70 [FW_CIRQ_IDX_ADDR] = 0x02204f84,
71 [FW_CIRQ_LISR_ADDR] = 0x022050d0,
72 [FW_TASK_ID_ADDR] = 0x0220406c,
73 [FW_TASK_IDX_ADDR] = 0x0220500c,
74 [FW_TASK_QID1_ADDR] = 0x022028c8,
75 [FW_TASK_QID2_ADDR] = 0x02202a38,
76 [FW_TASK_START_ADDR] = 0x0220286c,
77 [FW_TASK_END_ADDR] = 0x02202870,
78 [FW_TASK_SIZE_ADDR] = 0x02202878,
79 [FW_LAST_MSG_ID_ADDR] = 0x02204fe8,
80 [FW_EINT_INFO_ADDR] = 0x0220525c,
81 [FW_SCHED_INFO_ADDR] = 0x0220516c,
82 [SWDEF_BASE_ADDR] = 0x411400,
83 [TXQ_WED_RING_BASE] = 0xd7300,
84 [RXQ_WED_RING_BASE] = 0xd7410,
85 [RXQ_WED_DATA_RING_BASE] = 0xd4540,
86 };
87
88 static const u32 mt7986_reg[] = {
89 [INT_SOURCE_CSR] = 0x24200,
90 [INT_MASK_CSR] = 0x24204,
91 [INT1_SOURCE_CSR] = 0x28200,
92 [INT1_MASK_CSR] = 0x28204,
93 [INT_MCU_CMD_SOURCE] = 0x241f0,
94 [INT_MCU_CMD_EVENT] = 0x54000108,
95 [WFDMA0_ADDR] = 0x24000,
96 [WFDMA0_PCIE1_ADDR] = 0x28000,
97 [WFDMA_EXT_CSR_ADDR] = 0x27000,
98 [CBTOP1_PHY_END] = 0x7fffffff,
99 [INFRA_MCU_ADDR_END] = 0x7c085fff,
100 [FW_ASSERT_STAT_ADDR] = 0x02204b54,
101 [FW_EXCEPT_TYPE_ADDR] = 0x022050dc,
102 [FW_EXCEPT_COUNT_ADDR] = 0x02204ffc,
103 [FW_CIRQ_COUNT_ADDR] = 0x022001ac,
104 [FW_CIRQ_IDX_ADDR] = 0x02204ec4,
105 [FW_CIRQ_LISR_ADDR] = 0x02205010,
106 [FW_TASK_ID_ADDR] = 0x02204fac,
107 [FW_TASK_IDX_ADDR] = 0x02204f4c,
108 [FW_TASK_QID1_ADDR] = 0x02202814,
109 [FW_TASK_QID2_ADDR] = 0x02202984,
110 [FW_TASK_START_ADDR] = 0x022027b8,
111 [FW_TASK_END_ADDR] = 0x022027bc,
112 [FW_TASK_SIZE_ADDR] = 0x022027c4,
113 [FW_LAST_MSG_ID_ADDR] = 0x02204f28,
114 [FW_EINT_INFO_ADDR] = 0x02205194,
115 [FW_SCHED_INFO_ADDR] = 0x022051a4,
116 [SWDEF_BASE_ADDR] = 0x411400,
117 [TXQ_WED_RING_BASE] = 0x24420,
118 [RXQ_WED_RING_BASE] = 0x24520,
119 [RXQ_WED_DATA_RING_BASE] = 0x24540,
120 };
121
122 static const u32 mt7915_offs[] = {
123 [TMAC_CDTR] = 0x090,
124 [TMAC_ODTR] = 0x094,
125 [TMAC_ATCR] = 0x098,
126 [TMAC_TRCR0] = 0x09c,
127 [TMAC_ICR0] = 0x0a4,
128 [TMAC_ICR1] = 0x0b4,
129 [TMAC_CTCR0] = 0x0f4,
130 [TMAC_TFCR0] = 0x1e0,
131 [MDP_BNRCFR0] = 0x070,
132 [MDP_BNRCFR1] = 0x074,
133 [ARB_DRNGR0] = 0x194,
134 [ARB_SCR] = 0x080,
135 [RMAC_MIB_AIRTIME14] = 0x3b8,
136 [AGG_AWSCR0] = 0x05c,
137 [AGG_PCR0] = 0x06c,
138 [AGG_ACR0] = 0x084,
139 [AGG_ACR4] = 0x08c,
140 [AGG_MRCR] = 0x098,
141 [AGG_ATCR0] = 0x0ec,
142 [AGG_ATCR1] = 0x0f0,
143 [AGG_ATCR3] = 0x0f4,
144 [LPON_UTTR0] = 0x080,
145 [LPON_UTTR1] = 0x084,
146 [LPON_FRCR] = 0x314,
147 [MIB_SDR3] = 0x014,
148 [MIB_SDR4] = 0x018,
149 [MIB_SDR5] = 0x01c,
150 [MIB_SDR7] = 0x024,
151 [MIB_SDR8] = 0x028,
152 [MIB_SDR9] = 0x02c,
153 [MIB_SDR10] = 0x030,
154 [MIB_SDR11] = 0x034,
155 [MIB_SDR12] = 0x038,
156 [MIB_SDR13] = 0x03c,
157 [MIB_SDR14] = 0x040,
158 [MIB_SDR15] = 0x044,
159 [MIB_SDR16] = 0x048,
160 [MIB_SDR17] = 0x04c,
161 [MIB_SDR18] = 0x050,
162 [MIB_SDR19] = 0x054,
163 [MIB_SDR20] = 0x058,
164 [MIB_SDR21] = 0x05c,
165 [MIB_SDR22] = 0x060,
166 [MIB_SDR23] = 0x064,
167 [MIB_SDR24] = 0x068,
168 [MIB_SDR25] = 0x06c,
169 [MIB_SDR27] = 0x074,
170 [MIB_SDR28] = 0x078,
171 [MIB_SDR29] = 0x07c,
172 [MIB_SDRVEC] = 0x080,
173 [MIB_SDR31] = 0x084,
174 [MIB_SDR32] = 0x088,
175 [MIB_SDRMUBF] = 0x090,
176 [MIB_DR8] = 0x0c0,
177 [MIB_DR9] = 0x0c4,
178 [MIB_DR11] = 0x0cc,
179 [MIB_MB_SDR0] = 0x100,
180 [MIB_MB_SDR1] = 0x104,
181 [TX_AGG_CNT] = 0x0a8,
182 [TX_AGG_CNT2] = 0x164,
183 [MIB_ARNG] = 0x4b8,
184 [WTBLON_TOP_WDUCR] = 0x0,
185 [WTBL_UPDATE] = 0x030,
186 [PLE_FL_Q_EMPTY] = 0x0b0,
187 [PLE_FL_Q_CTRL] = 0x1b0,
188 [PLE_AC_QEMPTY] = 0x500,
189 [PLE_FREEPG_CNT] = 0x100,
190 [PLE_FREEPG_HEAD_TAIL] = 0x104,
191 [PLE_PG_HIF_GROUP] = 0x110,
192 [PLE_HIF_PG_INFO] = 0x114,
193 [AC_OFFSET] = 0x040,
194 [ETBF_PAR_RPT0] = 0x068,
195 };
196
197 static const u32 mt7916_offs[] = {
198 [TMAC_CDTR] = 0x0c8,
199 [TMAC_ODTR] = 0x0cc,
200 [TMAC_ATCR] = 0x00c,
201 [TMAC_TRCR0] = 0x010,
202 [TMAC_ICR0] = 0x014,
203 [TMAC_ICR1] = 0x018,
204 [TMAC_CTCR0] = 0x114,
205 [TMAC_TFCR0] = 0x0e4,
206 [MDP_BNRCFR0] = 0x090,
207 [MDP_BNRCFR1] = 0x094,
208 [ARB_DRNGR0] = 0x1e0,
209 [ARB_SCR] = 0x000,
210 [RMAC_MIB_AIRTIME14] = 0x0398,
211 [AGG_AWSCR0] = 0x030,
212 [AGG_PCR0] = 0x040,
213 [AGG_ACR0] = 0x054,
214 [AGG_ACR4] = 0x05c,
215 [AGG_MRCR] = 0x068,
216 [AGG_ATCR0] = 0x1a4,
217 [AGG_ATCR1] = 0x1a8,
218 [AGG_ATCR3] = 0x080,
219 [LPON_UTTR0] = 0x360,
220 [LPON_UTTR1] = 0x364,
221 [LPON_FRCR] = 0x37c,
222 [MIB_SDR3] = 0x698,
223 [MIB_SDR4] = 0x788,
224 [MIB_SDR5] = 0x780,
225 [MIB_SDR7] = 0x5a8,
226 [MIB_SDR8] = 0x78c,
227 [MIB_SDR9] = 0x024,
228 [MIB_SDR10] = 0x76c,
229 [MIB_SDR11] = 0x790,
230 [MIB_SDR12] = 0x558,
231 [MIB_SDR13] = 0x560,
232 [MIB_SDR14] = 0x564,
233 [MIB_SDR15] = 0x568,
234 [MIB_SDR16] = 0x7fc,
235 [MIB_SDR17] = 0x800,
236 [MIB_SDR18] = 0x030,
237 [MIB_SDR19] = 0x5ac,
238 [MIB_SDR20] = 0x5b0,
239 [MIB_SDR21] = 0x5b4,
240 [MIB_SDR22] = 0x770,
241 [MIB_SDR23] = 0x774,
242 [MIB_SDR24] = 0x778,
243 [MIB_SDR25] = 0x77c,
244 [MIB_SDR27] = 0x080,
245 [MIB_SDR28] = 0x084,
246 [MIB_SDR29] = 0x650,
247 [MIB_SDRVEC] = 0x5a8,
248 [MIB_SDR31] = 0x55c,
249 [MIB_SDR32] = 0x7a8,
250 [MIB_SDRMUBF] = 0x7ac,
251 [MIB_DR8] = 0x56c,
252 [MIB_DR9] = 0x570,
253 [MIB_DR11] = 0x574,
254 [MIB_MB_SDR0] = 0x688,
255 [MIB_MB_SDR1] = 0x690,
256 [TX_AGG_CNT] = 0x7dc,
257 [TX_AGG_CNT2] = 0x7ec,
258 [MIB_ARNG] = 0x0b0,
259 [WTBLON_TOP_WDUCR] = 0x200,
260 [WTBL_UPDATE] = 0x230,
261 [PLE_FL_Q_EMPTY] = 0x360,
262 [PLE_FL_Q_CTRL] = 0x3e0,
263 [PLE_AC_QEMPTY] = 0x600,
264 [PLE_FREEPG_CNT] = 0x380,
265 [PLE_FREEPG_HEAD_TAIL] = 0x384,
266 [PLE_PG_HIF_GROUP] = 0x00c,
267 [PLE_HIF_PG_INFO] = 0x388,
268 [AC_OFFSET] = 0x080,
269 [ETBF_PAR_RPT0] = 0x100,
270 };
271
272 static const struct mt76_connac_reg_map mt7915_reg_map[] = {
273 { 0x00400000, 0x80000, 0x10000 }, /* WF_MCU_SYSRAM */
274 { 0x00410000, 0x90000, 0x10000 }, /* WF_MCU_SYSRAM (configure regs) */
275 { 0x40000000, 0x70000, 0x10000 }, /* WF_UMAC_SYSRAM */
276 { 0x54000000, 0x02000, 0x01000 }, /* WFDMA PCIE0 MCU DMA0 */
277 { 0x55000000, 0x03000, 0x01000 }, /* WFDMA PCIE0 MCU DMA1 */
278 { 0x58000000, 0x06000, 0x01000 }, /* WFDMA PCIE1 MCU DMA0 (MEM_DMA) */
279 { 0x59000000, 0x07000, 0x01000 }, /* WFDMA PCIE1 MCU DMA1 */
280 { 0x7c000000, 0xf0000, 0x10000 }, /* CONN_INFRA */
281 { 0x7c020000, 0xd0000, 0x10000 }, /* CONN_INFRA, WFDMA */
282 { 0x80020000, 0xb0000, 0x10000 }, /* WF_TOP_MISC_OFF */
283 { 0x81020000, 0xc0000, 0x10000 }, /* WF_TOP_MISC_ON */
284 { 0x820c0000, 0x08000, 0x04000 }, /* WF_UMAC_TOP (PLE) */
285 { 0x820c8000, 0x0c000, 0x02000 }, /* WF_UMAC_TOP (PSE) */
286 { 0x820cc000, 0x0e000, 0x02000 }, /* WF_UMAC_TOP (PP) */
287 { 0x820ce000, 0x21c00, 0x00200 }, /* WF_LMAC_TOP (WF_SEC) */
288 { 0x820cf000, 0x22000, 0x01000 }, /* WF_LMAC_TOP (WF_PF) */
289 { 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */
290 { 0x820e0000, 0x20000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */
291 { 0x820e1000, 0x20400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */
292 { 0x820e2000, 0x20800, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */
293 { 0x820e3000, 0x20c00, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */
294 { 0x820e4000, 0x21000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */
295 { 0x820e5000, 0x21400, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */
296 { 0x820e7000, 0x21e00, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */
297 { 0x820e9000, 0x23400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */
298 { 0x820ea000, 0x24000, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */
299 { 0x820eb000, 0x24200, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */
300 { 0x820ec000, 0x24600, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_INT) */
301 { 0x820ed000, 0x24800, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */
302 { 0x820f0000, 0xa0000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */
303 { 0x820f1000, 0xa0600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */
304 { 0x820f2000, 0xa0800, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */
305 { 0x820f3000, 0xa0c00, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */
306 { 0x820f4000, 0xa1000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */
307 { 0x820f5000, 0xa1400, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */
308 { 0x820f7000, 0xa1e00, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */
309 { 0x820f9000, 0xa3400, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */
310 { 0x820fa000, 0xa4000, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */
311 { 0x820fb000, 0xa4200, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */
312 { 0x820fc000, 0xa4600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_INT) */
313 { 0x820fd000, 0xa4800, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */
314 { 0x0, 0x0, 0x0 }, /* imply end of search */
315 };
316
317 static const struct mt76_connac_reg_map mt7916_reg_map[] = {
318 { 0x54000000, 0x02000, 0x01000 }, /* WFDMA_0 (PCIE0 MCU DMA0) */
319 { 0x55000000, 0x03000, 0x01000 }, /* WFDMA_1 (PCIE0 MCU DMA1) */
320 { 0x56000000, 0x04000, 0x01000 }, /* WFDMA_2 (Reserved) */
321 { 0x57000000, 0x05000, 0x01000 }, /* WFDMA_3 (MCU wrap CR) */
322 { 0x58000000, 0x06000, 0x01000 }, /* WFDMA_4 (PCIE1 MCU DMA0) */
323 { 0x59000000, 0x07000, 0x01000 }, /* WFDMA_5 (PCIE1 MCU DMA1) */
324 { 0x820c0000, 0x08000, 0x04000 }, /* WF_UMAC_TOP (PLE) */
325 { 0x820c8000, 0x0c000, 0x02000 }, /* WF_UMAC_TOP (PSE) */
326 { 0x820cc000, 0x0e000, 0x02000 }, /* WF_UMAC_TOP (PP) */
327 { 0x820e0000, 0x20000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */
328 { 0x820e1000, 0x20400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */
329 { 0x820e2000, 0x20800, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */
330 { 0x820e3000, 0x20c00, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */
331 { 0x820e4000, 0x21000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */
332 { 0x820e5000, 0x21400, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */
333 { 0x820ce000, 0x21c00, 0x00200 }, /* WF_LMAC_TOP (WF_SEC) */
334 { 0x820e7000, 0x21e00, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */
335 { 0x820cf000, 0x22000, 0x01000 }, /* WF_LMAC_TOP (WF_PF) */
336 { 0x820e9000, 0x23400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */
337 { 0x820ea000, 0x24000, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */
338 { 0x820eb000, 0x24200, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */
339 { 0x820ec000, 0x24600, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_INT) */
340 { 0x820ed000, 0x24800, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */
341 { 0x820ca000, 0x26000, 0x02000 }, /* WF_LMAC_TOP BN0 (WF_MUCOP) */
342 { 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */
343 { 0x00400000, 0x80000, 0x10000 }, /* WF_MCU_SYSRAM */
344 { 0x00410000, 0x90000, 0x10000 }, /* WF_MCU_SYSRAM (configure cr) */
345 { 0x820f0000, 0xa0000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */
346 { 0x820f1000, 0xa0600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */
347 { 0x820f2000, 0xa0800, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */
348 { 0x820f3000, 0xa0c00, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */
349 { 0x820f4000, 0xa1000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */
350 { 0x820f5000, 0xa1400, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */
351 { 0x820f7000, 0xa1e00, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */
352 { 0x820f9000, 0xa3400, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */
353 { 0x820fa000, 0xa4000, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */
354 { 0x820fb000, 0xa4200, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */
355 { 0x820fc000, 0xa4600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_INT) */
356 { 0x820fd000, 0xa4800, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */
357 { 0x820c4000, 0xa8000, 0x01000 }, /* WF_LMAC_TOP (WF_UWTBL ) */
358 { 0x820b0000, 0xae000, 0x01000 }, /* [APB2] WFSYS_ON */
359 { 0x80020000, 0xb0000, 0x10000 }, /* WF_TOP_MISC_OFF */
360 { 0x81020000, 0xc0000, 0x10000 }, /* WF_TOP_MISC_ON */
361 { 0x0, 0x0, 0x0 }, /* imply end of search */
362 };
363
364 static const struct mt76_connac_reg_map mt7986_reg_map[] = {
365 { 0x54000000, 0x402000, 0x01000 }, /* WFDMA_0 (PCIE0 MCU DMA0) */
366 { 0x55000000, 0x403000, 0x01000 }, /* WFDMA_1 (PCIE0 MCU DMA1) */
367 { 0x56000000, 0x404000, 0x01000 }, /* WFDMA_2 (Reserved) */
368 { 0x57000000, 0x405000, 0x01000 }, /* WFDMA_3 (MCU wrap CR) */
369 { 0x58000000, 0x406000, 0x01000 }, /* WFDMA_4 (PCIE1 MCU DMA0) */
370 { 0x59000000, 0x407000, 0x01000 }, /* WFDMA_5 (PCIE1 MCU DMA1) */
371 { 0x820c0000, 0x408000, 0x04000 }, /* WF_UMAC_TOP (PLE) */
372 { 0x820c8000, 0x40c000, 0x02000 }, /* WF_UMAC_TOP (PSE) */
373 { 0x820cc000, 0x40e000, 0x02000 }, /* WF_UMAC_TOP (PP) */
374 { 0x820e0000, 0x420000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */
375 { 0x820e1000, 0x420400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */
376 { 0x820e2000, 0x420800, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */
377 { 0x820e3000, 0x420c00, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */
378 { 0x820e4000, 0x421000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */
379 { 0x820e5000, 0x421400, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */
380 { 0x820ce000, 0x421c00, 0x00200 }, /* WF_LMAC_TOP (WF_SEC) */
381 { 0x820e7000, 0x421e00, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */
382 { 0x820cf000, 0x422000, 0x01000 }, /* WF_LMAC_TOP (WF_PF) */
383 { 0x820e9000, 0x423400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */
384 { 0x820ea000, 0x424000, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */
385 { 0x820eb000, 0x424200, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */
386 { 0x820ec000, 0x424600, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_INT) */
387 { 0x820ed000, 0x424800, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */
388 { 0x820ca000, 0x426000, 0x02000 }, /* WF_LMAC_TOP BN0 (WF_MUCOP) */
389 { 0x820d0000, 0x430000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */
390 { 0x00400000, 0x480000, 0x10000 }, /* WF_MCU_SYSRAM */
391 { 0x00410000, 0x490000, 0x10000 }, /* WF_MCU_SYSRAM */
392 { 0x820f0000, 0x4a0000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */
393 { 0x820f1000, 0x4a0600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */
394 { 0x820f2000, 0x4a0800, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */
395 { 0x820f3000, 0x4a0c00, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */
396 { 0x820f4000, 0x4a1000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */
397 { 0x820f5000, 0x4a1400, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */
398 { 0x820f7000, 0x4a1e00, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */
399 { 0x820f9000, 0x4a3400, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */
400 { 0x820fa000, 0x4a4000, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */
401 { 0x820fb000, 0x4a4200, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */
402 { 0x820fc000, 0x4a4600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_INT) */
403 { 0x820fd000, 0x4a4800, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */
404 { 0x820c4000, 0x4a8000, 0x01000 }, /* WF_LMAC_TOP (WF_UWTBL ) */
405 { 0x820b0000, 0x4ae000, 0x01000 }, /* [APB2] WFSYS_ON */
406 { 0x80020000, 0x4b0000, 0x10000 }, /* WF_TOP_MISC_OFF */
407 { 0x81020000, 0x4c0000, 0x10000 }, /* WF_TOP_MISC_ON */
408 { 0x89000000, 0x4d0000, 0x01000 }, /* WF_MCU_CFG_ON */
409 { 0x89010000, 0x4d1000, 0x01000 }, /* WF_MCU_CIRQ */
410 { 0x89020000, 0x4d2000, 0x01000 }, /* WF_MCU_GPT */
411 { 0x89030000, 0x4d3000, 0x01000 }, /* WF_MCU_WDT */
412 { 0x80010000, 0x4d4000, 0x01000 }, /* WF_AXIDMA */
413 { 0x0, 0x0, 0x0 }, /* imply end of search */
414 };
415
mt7915_reg_map_l1(struct mt7915_dev * dev,u32 addr)416 static u32 mt7915_reg_map_l1(struct mt7915_dev *dev, u32 addr)
417 {
418 u32 offset = FIELD_GET(MT_HIF_REMAP_L1_OFFSET, addr);
419 u32 base = FIELD_GET(MT_HIF_REMAP_L1_BASE, addr);
420 u32 l1_remap;
421
422 if (is_mt798x(&dev->mt76))
423 return MT_CONN_INFRA_OFFSET(addr);
424
425 l1_remap = is_mt7915(&dev->mt76) ?
426 MT_HIF_REMAP_L1 : MT_HIF_REMAP_L1_MT7916;
427
428 dev->bus_ops->rmw(&dev->mt76, l1_remap,
429 MT_HIF_REMAP_L1_MASK,
430 FIELD_PREP(MT_HIF_REMAP_L1_MASK, base));
431 /* use read to push write */
432 dev->bus_ops->rr(&dev->mt76, l1_remap);
433
434 return MT_HIF_REMAP_BASE_L1 + offset;
435 }
436
mt7915_reg_map_l2(struct mt7915_dev * dev,u32 addr)437 static u32 mt7915_reg_map_l2(struct mt7915_dev *dev, u32 addr)
438 {
439 u32 offset, base;
440
441 if (is_mt7915(&dev->mt76)) {
442 offset = FIELD_GET(MT_HIF_REMAP_L2_OFFSET, addr);
443 base = FIELD_GET(MT_HIF_REMAP_L2_BASE, addr);
444
445 dev->bus_ops->rmw(&dev->mt76, MT_HIF_REMAP_L2,
446 MT_HIF_REMAP_L2_MASK,
447 FIELD_PREP(MT_HIF_REMAP_L2_MASK, base));
448
449 /* use read to push write */
450 dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_L2);
451 } else {
452 u32 ofs = is_mt798x(&dev->mt76) ? 0x400000 : 0;
453
454 offset = FIELD_GET(MT_HIF_REMAP_L2_OFFSET_MT7916, addr);
455 base = FIELD_GET(MT_HIF_REMAP_L2_BASE_MT7916, addr);
456
457 dev->bus_ops->rmw(&dev->mt76, MT_HIF_REMAP_L2_MT7916 + ofs,
458 MT_HIF_REMAP_L2_MASK_MT7916,
459 FIELD_PREP(MT_HIF_REMAP_L2_MASK_MT7916, base));
460
461 /* use read to push write */
462 dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_L2_MT7916 + ofs);
463
464 offset += (MT_HIF_REMAP_BASE_L2_MT7916 + ofs);
465 }
466
467 return offset;
468 }
469
__mt7915_reg_addr(struct mt7915_dev * dev,u32 addr)470 static u32 __mt7915_reg_addr(struct mt7915_dev *dev, u32 addr)
471 {
472 int i;
473
474 if (addr < 0x100000)
475 return addr;
476
477 if (!dev->reg.map) {
478 dev_err(dev->mt76.dev, "err: reg_map is null\n");
479 return addr;
480 }
481
482 for (i = 0; i < dev->reg.map_size; i++) {
483 u32 ofs;
484
485 if (addr < dev->reg.map[i].phys)
486 continue;
487
488 ofs = addr - dev->reg.map[i].phys;
489 if (ofs >= dev->reg.map[i].size)
490 continue;
491
492 return dev->reg.map[i].maps + ofs;
493 }
494
495 return 0;
496 }
497
__mt7915_reg_remap_addr(struct mt7915_dev * dev,u32 addr)498 static u32 __mt7915_reg_remap_addr(struct mt7915_dev *dev, u32 addr)
499 {
500 if ((addr >= MT_INFRA_BASE && addr < MT_WFSYS0_PHY_START) ||
501 (addr >= MT_WFSYS0_PHY_START && addr < MT_WFSYS1_PHY_START) ||
502 (addr >= MT_WFSYS1_PHY_START && addr <= MT_WFSYS1_PHY_END))
503 return mt7915_reg_map_l1(dev, addr);
504
505 if (dev_is_pci(dev->mt76.dev) &&
506 ((addr >= MT_CBTOP1_PHY_START && addr <= MT_CBTOP1_PHY_END) ||
507 addr >= MT_CBTOP2_PHY_START))
508 return mt7915_reg_map_l1(dev, addr);
509
510 /* CONN_INFRA: covert to phyiscal addr and use layer 1 remap */
511 if (addr >= MT_INFRA_MCU_START && addr <= MT_INFRA_MCU_END) {
512 addr = addr - MT_INFRA_MCU_START + MT_INFRA_BASE;
513 return mt7915_reg_map_l1(dev, addr);
514 }
515
516 return mt7915_reg_map_l2(dev, addr);
517 }
518
mt7915_memcpy_fromio(struct mt7915_dev * dev,void * buf,u32 offset,size_t len)519 void mt7915_memcpy_fromio(struct mt7915_dev *dev, void *buf, u32 offset,
520 size_t len)
521 {
522 u32 addr = __mt7915_reg_addr(dev, offset);
523
524 if (addr) {
525 #if defined(__linux__)
526 memcpy_fromio(buf, dev->mt76.mmio.regs + addr, len);
527 #elif defined(__FreeBSD__)
528 memcpy_fromio(buf, (u8 *)dev->mt76.mmio.regs + addr, len);
529 #endif
530 return;
531 }
532
533 spin_lock_bh(&dev->reg_lock);
534 #if defined(__linux__)
535 memcpy_fromio(buf, dev->mt76.mmio.regs +
536 #elif defined(__FreeBSD__)
537 memcpy_fromio(buf, (u8 *)dev->mt76.mmio.regs +
538 #endif
539 __mt7915_reg_remap_addr(dev, offset), len);
540 spin_unlock_bh(&dev->reg_lock);
541 }
542
mt7915_rr(struct mt76_dev * mdev,u32 offset)543 static u32 mt7915_rr(struct mt76_dev *mdev, u32 offset)
544 {
545 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76);
546 u32 addr = __mt7915_reg_addr(dev, offset), val;
547
548 if (addr)
549 return dev->bus_ops->rr(mdev, addr);
550
551 spin_lock_bh(&dev->reg_lock);
552 val = dev->bus_ops->rr(mdev, __mt7915_reg_remap_addr(dev, offset));
553 spin_unlock_bh(&dev->reg_lock);
554
555 return val;
556 }
557
mt7915_wr(struct mt76_dev * mdev,u32 offset,u32 val)558 static void mt7915_wr(struct mt76_dev *mdev, u32 offset, u32 val)
559 {
560 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76);
561 u32 addr = __mt7915_reg_addr(dev, offset);
562
563 if (addr) {
564 dev->bus_ops->wr(mdev, addr, val);
565 return;
566 }
567
568 spin_lock_bh(&dev->reg_lock);
569 dev->bus_ops->wr(mdev, __mt7915_reg_remap_addr(dev, offset), val);
570 spin_unlock_bh(&dev->reg_lock);
571 }
572
mt7915_rmw(struct mt76_dev * mdev,u32 offset,u32 mask,u32 val)573 static u32 mt7915_rmw(struct mt76_dev *mdev, u32 offset, u32 mask, u32 val)
574 {
575 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76);
576 u32 addr = __mt7915_reg_addr(dev, offset);
577
578 if (addr)
579 return dev->bus_ops->rmw(mdev, addr, mask, val);
580
581 spin_lock_bh(&dev->reg_lock);
582 val = dev->bus_ops->rmw(mdev, __mt7915_reg_remap_addr(dev, offset), mask, val);
583 spin_unlock_bh(&dev->reg_lock);
584
585 return val;
586 }
587
588 #ifdef CONFIG_NET_MEDIATEK_SOC_WED
mt7915_mmio_wed_update_rx_stats(struct mtk_wed_device * wed,struct mtk_wed_wo_rx_stats * stats)589 static void mt7915_mmio_wed_update_rx_stats(struct mtk_wed_device *wed,
590 struct mtk_wed_wo_rx_stats *stats)
591 {
592 int idx = le16_to_cpu(stats->wlan_idx);
593 struct mt7915_dev *dev;
594 struct mt76_wcid *wcid;
595
596 dev = container_of(wed, struct mt7915_dev, mt76.mmio.wed);
597
598 if (idx >= mt7915_wtbl_size(dev))
599 return;
600
601 rcu_read_lock();
602
603 wcid = rcu_dereference(dev->mt76.wcid[idx]);
604 if (wcid) {
605 wcid->stats.rx_bytes += le32_to_cpu(stats->rx_byte_cnt);
606 wcid->stats.rx_packets += le32_to_cpu(stats->rx_pkt_cnt);
607 wcid->stats.rx_errors += le32_to_cpu(stats->rx_err_cnt);
608 wcid->stats.rx_drops += le32_to_cpu(stats->rx_drop_cnt);
609 }
610
611 rcu_read_unlock();
612 }
613
mt7915_mmio_wed_reset(struct mtk_wed_device * wed)614 static int mt7915_mmio_wed_reset(struct mtk_wed_device *wed)
615 {
616 struct mt76_dev *mdev = container_of(wed, struct mt76_dev, mmio.wed);
617 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76);
618 struct mt76_phy *mphy = &dev->mphy;
619 int ret;
620
621 ASSERT_RTNL();
622
623 if (test_and_set_bit(MT76_STATE_WED_RESET, &mphy->state))
624 return -EBUSY;
625
626 ret = mt7915_mcu_set_ser(dev, SER_RECOVER, SER_SET_RECOVER_L1,
627 mphy->band_idx);
628 if (ret)
629 goto out;
630
631 rtnl_unlock();
632 if (!wait_for_completion_timeout(&mdev->mmio.wed_reset, 20 * HZ)) {
633 dev_err(mdev->dev, "wed reset timeout\n");
634 ret = -ETIMEDOUT;
635 }
636 rtnl_lock();
637 out:
638 clear_bit(MT76_STATE_WED_RESET, &mphy->state);
639
640 return ret;
641 }
642 #endif
643
mt7915_mmio_wed_init(struct mt7915_dev * dev,void * pdev_ptr,bool pci,int * irq)644 int mt7915_mmio_wed_init(struct mt7915_dev *dev, void *pdev_ptr,
645 bool pci, int *irq)
646 {
647 #ifdef CONFIG_NET_MEDIATEK_SOC_WED
648 struct mtk_wed_device *wed = &dev->mt76.mmio.wed;
649 int ret;
650
651 if (!wed_enable)
652 return 0;
653
654 if (pci) {
655 struct pci_dev *pci_dev = pdev_ptr;
656
657 wed->wlan.pci_dev = pci_dev;
658 wed->wlan.bus_type = MTK_WED_BUS_PCIE;
659 wed->wlan.base = devm_ioremap(dev->mt76.dev,
660 pci_resource_start(pci_dev, 0),
661 pci_resource_len(pci_dev, 0));
662 wed->wlan.phy_base = pci_resource_start(pci_dev, 0);
663 wed->wlan.wpdma_int = pci_resource_start(pci_dev, 0) +
664 MT_INT_WED_SOURCE_CSR;
665 wed->wlan.wpdma_mask = pci_resource_start(pci_dev, 0) +
666 MT_INT_WED_MASK_CSR;
667 wed->wlan.wpdma_phys = pci_resource_start(pci_dev, 0) +
668 MT_WFDMA_EXT_CSR_BASE;
669 wed->wlan.wpdma_tx = pci_resource_start(pci_dev, 0) +
670 MT_TXQ_WED_RING_BASE;
671 wed->wlan.wpdma_txfree = pci_resource_start(pci_dev, 0) +
672 MT_RXQ_WED_RING_BASE;
673 wed->wlan.wpdma_rx_glo = pci_resource_start(pci_dev, 0) +
674 MT_WPDMA_GLO_CFG;
675 wed->wlan.wpdma_rx = pci_resource_start(pci_dev, 0) +
676 MT_RXQ_WED_DATA_RING_BASE;
677 } else {
678 struct platform_device *plat_dev = pdev_ptr;
679 struct resource *res;
680
681 res = platform_get_resource(plat_dev, IORESOURCE_MEM, 0);
682 if (!res)
683 return 0;
684
685 wed->wlan.platform_dev = plat_dev;
686 wed->wlan.bus_type = MTK_WED_BUS_AXI;
687 wed->wlan.base = devm_ioremap(dev->mt76.dev, res->start,
688 resource_size(res));
689 wed->wlan.phy_base = res->start;
690 wed->wlan.wpdma_int = res->start + MT_INT_SOURCE_CSR;
691 wed->wlan.wpdma_mask = res->start + MT_INT_MASK_CSR;
692 wed->wlan.wpdma_tx = res->start + MT_TXQ_WED_RING_BASE;
693 wed->wlan.wpdma_txfree = res->start + MT_RXQ_WED_RING_BASE;
694 wed->wlan.wpdma_rx_glo = res->start + MT_WPDMA_GLO_CFG;
695 wed->wlan.wpdma_rx = res->start + MT_RXQ_WED_DATA_RING_BASE;
696 }
697 wed->wlan.nbuf = MT7915_HW_TOKEN_SIZE;
698 wed->wlan.tx_tbit[0] = is_mt7915(&dev->mt76) ? 4 : 30;
699 wed->wlan.tx_tbit[1] = is_mt7915(&dev->mt76) ? 5 : 31;
700 wed->wlan.txfree_tbit = is_mt798x(&dev->mt76) ? 2 : 1;
701 wed->wlan.token_start = MT7915_TOKEN_SIZE - wed->wlan.nbuf;
702 wed->wlan.wcid_512 = !is_mt7915(&dev->mt76);
703
704 wed->wlan.rx_nbuf = 65536;
705 wed->wlan.rx_npkt = MT7915_WED_RX_TOKEN_SIZE;
706 wed->wlan.rx_size = SKB_WITH_OVERHEAD(MT_RX_BUF_SIZE);
707 if (is_mt7915(&dev->mt76)) {
708 wed->wlan.rx_tbit[0] = 16;
709 wed->wlan.rx_tbit[1] = 17;
710 } else if (is_mt798x(&dev->mt76)) {
711 wed->wlan.rx_tbit[0] = 22;
712 wed->wlan.rx_tbit[1] = 23;
713 } else {
714 wed->wlan.rx_tbit[0] = 18;
715 wed->wlan.rx_tbit[1] = 19;
716 }
717
718 wed->wlan.init_buf = mt7915_wed_init_buf;
719 wed->wlan.offload_enable = mt76_wed_offload_enable;
720 wed->wlan.offload_disable = mt76_wed_offload_disable;
721 wed->wlan.init_rx_buf = mt76_wed_init_rx_buf;
722 wed->wlan.release_rx_buf = mt76_wed_release_rx_buf;
723 wed->wlan.update_wo_rx_stats = mt7915_mmio_wed_update_rx_stats;
724 wed->wlan.reset = mt7915_mmio_wed_reset;
725 wed->wlan.reset_complete = mt76_wed_reset_complete;
726
727 dev->mt76.rx_token_size = wed->wlan.rx_npkt;
728
729 if (mtk_wed_device_attach(wed))
730 return 0;
731
732 *irq = wed->irq;
733 dev->mt76.dma_dev = wed->dev;
734
735 ret = dma_set_mask(wed->dev, DMA_BIT_MASK(32));
736 if (ret)
737 return ret;
738
739 return 1;
740 #else
741 return 0;
742 #endif
743 }
744
mt7915_mmio_init(struct mt76_dev * mdev,void __iomem * mem_base,u32 device_id)745 static int mt7915_mmio_init(struct mt76_dev *mdev,
746 void __iomem *mem_base,
747 u32 device_id)
748 {
749 struct mt76_bus_ops *bus_ops;
750 struct mt7915_dev *dev;
751
752 dev = container_of(mdev, struct mt7915_dev, mt76);
753 mt76_mmio_init(&dev->mt76, mem_base);
754 spin_lock_init(&dev->reg_lock);
755
756 switch (device_id) {
757 case 0x7915:
758 dev->reg.reg_rev = mt7915_reg;
759 dev->reg.offs_rev = mt7915_offs;
760 dev->reg.map = mt7915_reg_map;
761 dev->reg.map_size = ARRAY_SIZE(mt7915_reg_map);
762 break;
763 case 0x7906:
764 dev->reg.reg_rev = mt7916_reg;
765 dev->reg.offs_rev = mt7916_offs;
766 dev->reg.map = mt7916_reg_map;
767 dev->reg.map_size = ARRAY_SIZE(mt7916_reg_map);
768 break;
769 case 0x7981:
770 case 0x7986:
771 dev->reg.reg_rev = mt7986_reg;
772 dev->reg.offs_rev = mt7916_offs;
773 dev->reg.map = mt7986_reg_map;
774 dev->reg.map_size = ARRAY_SIZE(mt7986_reg_map);
775 break;
776 default:
777 return -EINVAL;
778 }
779
780 dev->bus_ops = dev->mt76.bus;
781 bus_ops = devm_kmemdup(dev->mt76.dev, dev->bus_ops, sizeof(*bus_ops),
782 GFP_KERNEL);
783 if (!bus_ops)
784 return -ENOMEM;
785
786 bus_ops->rr = mt7915_rr;
787 bus_ops->wr = mt7915_wr;
788 bus_ops->rmw = mt7915_rmw;
789 dev->mt76.bus = bus_ops;
790
791 mdev->rev = (device_id << 16) |
792 (mt76_rr(dev, MT_HW_REV) & 0xff);
793 dev_dbg(mdev->dev, "ASIC revision: %04x\n", mdev->rev);
794
795 return 0;
796 }
797
mt7915_dual_hif_set_irq_mask(struct mt7915_dev * dev,bool write_reg,u32 clear,u32 set)798 void mt7915_dual_hif_set_irq_mask(struct mt7915_dev *dev,
799 bool write_reg,
800 u32 clear, u32 set)
801 {
802 struct mt76_dev *mdev = &dev->mt76;
803 unsigned long flags;
804
805 spin_lock_irqsave(&mdev->mmio.irq_lock, flags);
806
807 mdev->mmio.irqmask &= ~clear;
808 mdev->mmio.irqmask |= set;
809
810 if (write_reg) {
811 if (mtk_wed_device_active(&mdev->mmio.wed))
812 mtk_wed_device_irq_set_mask(&mdev->mmio.wed,
813 mdev->mmio.irqmask);
814 else
815 mt76_wr(dev, MT_INT_MASK_CSR, mdev->mmio.irqmask);
816 mt76_wr(dev, MT_INT1_MASK_CSR, mdev->mmio.irqmask);
817 }
818
819 spin_unlock_irqrestore(&mdev->mmio.irq_lock, flags);
820 }
821
mt7915_rx_poll_complete(struct mt76_dev * mdev,enum mt76_rxq_id q)822 static void mt7915_rx_poll_complete(struct mt76_dev *mdev,
823 enum mt76_rxq_id q)
824 {
825 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76);
826
827 mt7915_irq_enable(dev, MT_INT_RX(q));
828 }
829
830 /* TODO: support 2/4/6/8 MSI-X vectors */
mt7915_irq_tasklet(struct tasklet_struct * t)831 static void mt7915_irq_tasklet(struct tasklet_struct *t)
832 {
833 struct mt7915_dev *dev = from_tasklet(dev, t, mt76.irq_tasklet);
834 struct mtk_wed_device *wed = &dev->mt76.mmio.wed;
835 u32 intr, intr1, mask;
836
837 if (mtk_wed_device_active(wed)) {
838 mtk_wed_device_irq_set_mask(wed, 0);
839 if (dev->hif2)
840 mt76_wr(dev, MT_INT1_MASK_CSR, 0);
841 intr = mtk_wed_device_irq_get(wed, dev->mt76.mmio.irqmask);
842 } else {
843 mt76_wr(dev, MT_INT_MASK_CSR, 0);
844 if (dev->hif2)
845 mt76_wr(dev, MT_INT1_MASK_CSR, 0);
846
847 intr = mt76_rr(dev, MT_INT_SOURCE_CSR);
848 intr &= dev->mt76.mmio.irqmask;
849 mt76_wr(dev, MT_INT_SOURCE_CSR, intr);
850 }
851
852 if (dev->hif2) {
853 intr1 = mt76_rr(dev, MT_INT1_SOURCE_CSR);
854 intr1 &= dev->mt76.mmio.irqmask;
855 mt76_wr(dev, MT_INT1_SOURCE_CSR, intr1);
856
857 intr |= intr1;
858 }
859
860 trace_dev_irq(&dev->mt76, intr, dev->mt76.mmio.irqmask);
861
862 mask = intr & MT_INT_RX_DONE_ALL;
863 if (intr & MT_INT_TX_DONE_MCU)
864 mask |= MT_INT_TX_DONE_MCU;
865
866 mt7915_irq_disable(dev, mask);
867
868 if (intr & MT_INT_TX_DONE_MCU)
869 napi_schedule(&dev->mt76.tx_napi);
870
871 if (intr & MT_INT_RX(MT_RXQ_MAIN))
872 napi_schedule(&dev->mt76.napi[MT_RXQ_MAIN]);
873
874 if (intr & MT_INT_RX(MT_RXQ_BAND1))
875 napi_schedule(&dev->mt76.napi[MT_RXQ_BAND1]);
876
877 if (intr & MT_INT_RX(MT_RXQ_MCU))
878 napi_schedule(&dev->mt76.napi[MT_RXQ_MCU]);
879
880 if (intr & MT_INT_RX(MT_RXQ_MCU_WA))
881 napi_schedule(&dev->mt76.napi[MT_RXQ_MCU_WA]);
882
883 if (!is_mt7915(&dev->mt76) &&
884 (intr & MT_INT_RX(MT_RXQ_MAIN_WA)))
885 napi_schedule(&dev->mt76.napi[MT_RXQ_MAIN_WA]);
886
887 if (intr & MT_INT_RX(MT_RXQ_BAND1_WA))
888 napi_schedule(&dev->mt76.napi[MT_RXQ_BAND1_WA]);
889
890 if (intr & MT_INT_MCU_CMD) {
891 u32 val = mt76_rr(dev, MT_MCU_CMD);
892
893 mt76_wr(dev, MT_MCU_CMD, val);
894 if (val & (MT_MCU_CMD_ERROR_MASK | MT_MCU_CMD_WDT_MASK)) {
895 dev->recovery.state = val;
896 mt7915_reset(dev);
897 }
898 }
899 }
900
mt7915_irq_handler(int irq,void * dev_instance)901 irqreturn_t mt7915_irq_handler(int irq, void *dev_instance)
902 {
903 struct mt7915_dev *dev = dev_instance;
904 struct mtk_wed_device *wed = &dev->mt76.mmio.wed;
905
906 if (mtk_wed_device_active(wed))
907 mtk_wed_device_irq_set_mask(wed, 0);
908 else
909 mt76_wr(dev, MT_INT_MASK_CSR, 0);
910
911 if (dev->hif2)
912 mt76_wr(dev, MT_INT1_MASK_CSR, 0);
913
914 if (!test_bit(MT76_STATE_INITIALIZED, &dev->mphy.state))
915 return IRQ_NONE;
916
917 tasklet_schedule(&dev->mt76.irq_tasklet);
918
919 return IRQ_HANDLED;
920 }
921
mt7915_mmio_probe(struct device * pdev,void __iomem * mem_base,u32 device_id)922 struct mt7915_dev *mt7915_mmio_probe(struct device *pdev,
923 void __iomem *mem_base, u32 device_id)
924 {
925 static const struct mt76_driver_ops drv_ops = {
926 /* txwi_size = txd size + txp size */
927 .txwi_size = MT_TXD_SIZE + sizeof(struct mt76_connac_fw_txp),
928 .drv_flags = MT_DRV_TXWI_NO_FREE | MT_DRV_HW_MGMT_TXQ |
929 MT_DRV_AMSDU_OFFLOAD,
930 .survey_flags = SURVEY_INFO_TIME_TX |
931 SURVEY_INFO_TIME_RX |
932 SURVEY_INFO_TIME_BSS_RX,
933 .token_size = MT7915_TOKEN_SIZE,
934 .tx_prepare_skb = mt7915_tx_prepare_skb,
935 .tx_complete_skb = mt76_connac_tx_complete_skb,
936 .rx_skb = mt7915_queue_rx_skb,
937 .rx_check = mt7915_rx_check,
938 .rx_poll_complete = mt7915_rx_poll_complete,
939 .sta_add = mt7915_mac_sta_add,
940 .sta_event = mt7915_mac_sta_event,
941 .sta_remove = mt7915_mac_sta_remove,
942 .update_survey = mt7915_update_channel,
943 .set_channel = mt7915_set_channel,
944 };
945 struct mt7915_dev *dev;
946 struct mt76_dev *mdev;
947 int ret;
948
949 mdev = mt76_alloc_device(pdev, sizeof(*dev), &mt7915_ops, &drv_ops);
950 if (!mdev)
951 return ERR_PTR(-ENOMEM);
952
953 dev = container_of(mdev, struct mt7915_dev, mt76);
954
955 ret = mt7915_mmio_init(mdev, mem_base, device_id);
956 if (ret)
957 goto error;
958
959 tasklet_setup(&mdev->irq_tasklet, mt7915_irq_tasklet);
960
961 return dev;
962
963 error:
964 mt76_free_device(&dev->mt76);
965
966 return ERR_PTR(ret);
967 }
968
mt7915_init(void)969 static int __init mt7915_init(void)
970 {
971 int ret;
972
973 ret = pci_register_driver(&mt7915_hif_driver);
974 if (ret)
975 return ret;
976
977 ret = pci_register_driver(&mt7915_pci_driver);
978 if (ret)
979 goto error_pci;
980
981 if (IS_ENABLED(CONFIG_MT798X_WMAC)) {
982 ret = platform_driver_register(&mt798x_wmac_driver);
983 if (ret)
984 goto error_wmac;
985 }
986
987 return 0;
988
989 error_wmac:
990 pci_unregister_driver(&mt7915_pci_driver);
991 error_pci:
992 pci_unregister_driver(&mt7915_hif_driver);
993
994 return ret;
995 }
996
mt7915_exit(void)997 static void __exit mt7915_exit(void)
998 {
999 if (IS_ENABLED(CONFIG_MT798X_WMAC))
1000 platform_driver_unregister(&mt798x_wmac_driver);
1001
1002 pci_unregister_driver(&mt7915_pci_driver);
1003 pci_unregister_driver(&mt7915_hif_driver);
1004 }
1005
1006 module_init(mt7915_init);
1007 module_exit(mt7915_exit);
1008 MODULE_DESCRIPTION("MediaTek MT7915E MMIO helpers");
1009 MODULE_LICENSE("Dual BSD/GPL");
1010