1 // SPDX-License-Identifier: ISC
2 /*
3 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name>
4 * Copyright (C) 2018 Lorenzo Bianconi <lorenzo.bianconi83@gmail.com>
5 */
6
7 #include "mt76x2.h"
8 #include "eeprom.h"
9 #include "../mt76x02_phy.h"
10
mt76x2_set_sar_specs(struct ieee80211_hw * hw,const struct cfg80211_sar_specs * sar)11 int mt76x2_set_sar_specs(struct ieee80211_hw *hw,
12 const struct cfg80211_sar_specs *sar)
13 {
14 int err = -EINVAL, power = hw->conf.power_level * 2;
15 struct mt76x02_dev *dev = hw->priv;
16 struct mt76_phy *mphy = &dev->mphy;
17
18 mutex_lock(&dev->mt76.mutex);
19 if (!cfg80211_chandef_valid(&mphy->chandef))
20 goto out;
21
22 err = mt76_init_sar_power(hw, sar);
23 if (err)
24 goto out;
25
26 dev->txpower_conf = mt76_get_sar_power(mphy, mphy->chandef.chan,
27 power);
28 /* convert to per-chain power for 2x2 devices */
29 dev->txpower_conf -= 6;
30
31 if (test_bit(MT76_STATE_RUNNING, &mphy->state))
32 mt76x2_phy_set_txpower(dev);
33 out:
34 mutex_unlock(&dev->mt76.mutex);
35
36 return err;
37 }
38 EXPORT_SYMBOL_GPL(mt76x2_set_sar_specs);
39
40 static void
mt76x2_set_wlan_state(struct mt76x02_dev * dev,bool enable)41 mt76x2_set_wlan_state(struct mt76x02_dev *dev, bool enable)
42 {
43 u32 val = mt76_rr(dev, MT_WLAN_FUN_CTRL);
44
45 if (enable)
46 val |= (MT_WLAN_FUN_CTRL_WLAN_EN |
47 MT_WLAN_FUN_CTRL_WLAN_CLK_EN);
48 else
49 val &= ~(MT_WLAN_FUN_CTRL_WLAN_EN |
50 MT_WLAN_FUN_CTRL_WLAN_CLK_EN);
51
52 mt76_wr(dev, MT_WLAN_FUN_CTRL, val);
53 udelay(20);
54 }
55
mt76x2_reset_wlan(struct mt76x02_dev * dev,bool enable)56 void mt76x2_reset_wlan(struct mt76x02_dev *dev, bool enable)
57 {
58 u32 val;
59
60 if (!enable)
61 goto out;
62
63 val = mt76_rr(dev, MT_WLAN_FUN_CTRL);
64
65 val &= ~MT_WLAN_FUN_CTRL_FRC_WL_ANT_SEL;
66
67 if (val & MT_WLAN_FUN_CTRL_WLAN_EN) {
68 val |= MT_WLAN_FUN_CTRL_WLAN_RESET_RF;
69 mt76_wr(dev, MT_WLAN_FUN_CTRL, val);
70 udelay(20);
71
72 val &= ~MT_WLAN_FUN_CTRL_WLAN_RESET_RF;
73 }
74
75 mt76_wr(dev, MT_WLAN_FUN_CTRL, val);
76 udelay(20);
77
78 out:
79 mt76x2_set_wlan_state(dev, enable);
80 }
81 EXPORT_SYMBOL_GPL(mt76x2_reset_wlan);
82
mt76_write_mac_initvals(struct mt76x02_dev * dev)83 void mt76_write_mac_initvals(struct mt76x02_dev *dev)
84 {
85 #define DEFAULT_PROT_CFG_CCK \
86 (FIELD_PREP(MT_PROT_CFG_RATE, 0x3) | \
87 FIELD_PREP(MT_PROT_CFG_NAV, 1) | \
88 FIELD_PREP(MT_PROT_CFG_TXOP_ALLOW, 0x3f) | \
89 MT_PROT_CFG_RTS_THRESH)
90
91 #define DEFAULT_PROT_CFG_OFDM \
92 (FIELD_PREP(MT_PROT_CFG_RATE, 0x2004) | \
93 FIELD_PREP(MT_PROT_CFG_NAV, 1) | \
94 FIELD_PREP(MT_PROT_CFG_TXOP_ALLOW, 0x3f) | \
95 MT_PROT_CFG_RTS_THRESH)
96
97 #define DEFAULT_PROT_CFG_20 \
98 (FIELD_PREP(MT_PROT_CFG_RATE, 0x2004) | \
99 FIELD_PREP(MT_PROT_CFG_CTRL, 1) | \
100 FIELD_PREP(MT_PROT_CFG_NAV, 1) | \
101 FIELD_PREP(MT_PROT_CFG_TXOP_ALLOW, 0x17))
102
103 #define DEFAULT_PROT_CFG_40 \
104 (FIELD_PREP(MT_PROT_CFG_RATE, 0x2084) | \
105 FIELD_PREP(MT_PROT_CFG_CTRL, 1) | \
106 FIELD_PREP(MT_PROT_CFG_NAV, 1) | \
107 FIELD_PREP(MT_PROT_CFG_TXOP_ALLOW, 0x3f))
108
109 static const struct mt76_reg_pair vals[] = {
110 /* Copied from MediaTek reference source */
111 { MT_PBF_SYS_CTRL, 0x00080c00 },
112 { MT_PBF_CFG, 0x1efebcff },
113 { MT_FCE_PSE_CTRL, 0x00000001 },
114 { MT_MAC_SYS_CTRL, 0x00000000 },
115 { MT_MAX_LEN_CFG, 0x003e3f00 },
116 { MT_AMPDU_MAX_LEN_20M1S, 0xaaa99887 },
117 { MT_AMPDU_MAX_LEN_20M2S, 0x000000aa },
118 { MT_XIFS_TIME_CFG, 0x33a40d0a },
119 { MT_BKOFF_SLOT_CFG, 0x00000209 },
120 { MT_TBTT_SYNC_CFG, 0x00422010 },
121 { MT_PWR_PIN_CFG, 0x00000000 },
122 { 0x1238, 0x001700c8 },
123 { MT_TX_SW_CFG0, 0x00101001 },
124 { MT_TX_SW_CFG1, 0x00010000 },
125 { MT_TX_SW_CFG2, 0x00000000 },
126 { MT_TXOP_CTRL_CFG, 0x0400583f },
127 { MT_TX_RTS_CFG, 0x00ffff20 },
128 { MT_TX_TIMEOUT_CFG, 0x000a2290 },
129 { MT_TX_RETRY_CFG, 0x47f01f0f },
130 { MT_EXP_ACK_TIME, 0x002c00dc },
131 { MT_TX_PROT_CFG6, 0xe3f42004 },
132 { MT_TX_PROT_CFG7, 0xe3f42084 },
133 { MT_TX_PROT_CFG8, 0xe3f42104 },
134 { MT_PIFS_TX_CFG, 0x00060fff },
135 { MT_RX_FILTR_CFG, 0x00015f97 },
136 { MT_LEGACY_BASIC_RATE, 0x0000017f },
137 { MT_HT_BASIC_RATE, 0x00004003 },
138 { MT_PN_PAD_MODE, 0x00000003 },
139 { MT_TXOP_HLDR_ET, 0x00000002 },
140 { 0xa44, 0x00000000 },
141 { MT_HEADER_TRANS_CTRL_REG, 0x00000000 },
142 { MT_TSO_CTRL, 0x00000000 },
143 { MT_AUX_CLK_CFG, 0x00000000 },
144 { MT_DACCLK_EN_DLY_CFG, 0x00000000 },
145 { MT_TX_ALC_CFG_4, 0x00000000 },
146 { MT_TX_ALC_VGA3, 0x00000000 },
147 { MT_TX_PWR_CFG_0, 0x3a3a3a3a },
148 { MT_TX_PWR_CFG_1, 0x3a3a3a3a },
149 { MT_TX_PWR_CFG_2, 0x3a3a3a3a },
150 { MT_TX_PWR_CFG_3, 0x3a3a3a3a },
151 { MT_TX_PWR_CFG_4, 0x3a3a3a3a },
152 { MT_TX_PWR_CFG_7, 0x3a3a3a3a },
153 { MT_TX_PWR_CFG_8, 0x0000003a },
154 { MT_TX_PWR_CFG_9, 0x0000003a },
155 { MT_EFUSE_CTRL, 0x0000d000 },
156 { MT_PAUSE_ENABLE_CONTROL1, 0x0000000a },
157 { MT_FCE_WLAN_FLOW_CONTROL1, 0x60401c18 },
158 { MT_WPDMA_DELAY_INT_CFG, 0x94ff0000 },
159 { MT_TX_SW_CFG3, 0x00000004 },
160 { MT_HT_FBK_TO_LEGACY, 0x00001818 },
161 { MT_VHT_HT_FBK_CFG1, 0xedcba980 },
162 { MT_PROT_AUTO_TX_CFG, 0x00830083 },
163 { MT_HT_CTRL_CFG, 0x000001ff },
164 { MT_TX_LINK_CFG, 0x00001020 },
165 };
166 struct mt76_reg_pair prot_vals[] = {
167 { MT_CCK_PROT_CFG, DEFAULT_PROT_CFG_CCK },
168 { MT_OFDM_PROT_CFG, DEFAULT_PROT_CFG_OFDM },
169 { MT_MM20_PROT_CFG, DEFAULT_PROT_CFG_20 },
170 { MT_MM40_PROT_CFG, DEFAULT_PROT_CFG_40 },
171 { MT_GF20_PROT_CFG, DEFAULT_PROT_CFG_20 },
172 { MT_GF40_PROT_CFG, DEFAULT_PROT_CFG_40 },
173 };
174
175 mt76_wr_rp(dev, 0, vals, ARRAY_SIZE(vals));
176 mt76_wr_rp(dev, 0, prot_vals, ARRAY_SIZE(prot_vals));
177 }
178 EXPORT_SYMBOL_GPL(mt76_write_mac_initvals);
179
mt76x2_init_txpower(struct mt76x02_dev * dev,struct ieee80211_supported_band * sband)180 void mt76x2_init_txpower(struct mt76x02_dev *dev,
181 struct ieee80211_supported_band *sband)
182 {
183 struct ieee80211_channel *chan;
184 struct mt76x2_tx_power_info txp;
185 struct mt76x02_rate_power t = {};
186 int i;
187
188 for (i = 0; i < sband->n_channels; i++) {
189 chan = &sband->channels[i];
190
191 mt76x2_get_power_info(dev, &txp, chan);
192 mt76x2_get_rate_power(dev, &t, chan);
193
194 chan->orig_mpwr = mt76x02_get_max_rate_power(&t) +
195 txp.target_power;
196 chan->orig_mpwr = DIV_ROUND_UP(chan->orig_mpwr, 2);
197
198 /* convert to combined output power on 2x2 devices */
199 chan->orig_mpwr += 3;
200 chan->max_power = min_t(int, chan->max_reg_power,
201 chan->orig_mpwr);
202 }
203 }
204 EXPORT_SYMBOL_GPL(mt76x2_init_txpower);
205