1 // SPDX-License-Identifier: ISC
2
3 #include "mt7603.h"
4 #include "mac.h"
5 #include "../dma.h"
6
7 static void
mt7603_rx_loopback_skb(struct mt7603_dev * dev,struct sk_buff * skb)8 mt7603_rx_loopback_skb(struct mt7603_dev *dev, struct sk_buff *skb)
9 {
10 static const u8 tid_to_ac[8] = {
11 IEEE80211_AC_BE,
12 IEEE80211_AC_BK,
13 IEEE80211_AC_BK,
14 IEEE80211_AC_BE,
15 IEEE80211_AC_VI,
16 IEEE80211_AC_VI,
17 IEEE80211_AC_VO,
18 IEEE80211_AC_VO
19 };
20 __le32 *txd = (__le32 *)skb->data;
21 struct ieee80211_hdr *hdr;
22 struct ieee80211_sta *sta;
23 struct mt7603_sta *msta;
24 struct mt76_wcid *wcid;
25 void *priv;
26 int idx;
27 u32 val;
28 u8 tid = 0;
29
30 if (skb->len < MT_TXD_SIZE + sizeof(struct ieee80211_hdr))
31 goto free;
32
33 val = le32_to_cpu(txd[1]);
34 idx = FIELD_GET(MT_TXD1_WLAN_IDX, val);
35 skb->priority = FIELD_GET(MT_TXD1_TID, val);
36
37 if (idx >= MT7603_WTBL_STA - 1)
38 goto free;
39
40 wcid = rcu_dereference(dev->mt76.wcid[idx]);
41 if (!wcid)
42 goto free;
43
44 priv = msta = container_of(wcid, struct mt7603_sta, wcid);
45 val = le32_to_cpu(txd[0]);
46 val &= ~(MT_TXD0_P_IDX | MT_TXD0_Q_IDX);
47 val |= FIELD_PREP(MT_TXD0_Q_IDX, MT_TX_HW_QUEUE_MGMT);
48 txd[0] = cpu_to_le32(val);
49
50 sta = container_of(priv, struct ieee80211_sta, drv_priv);
51 hdr = (struct ieee80211_hdr *)&skb->data[MT_TXD_SIZE];
52 if (ieee80211_is_data_qos(hdr->frame_control))
53 tid = *ieee80211_get_qos_ctl(hdr) &
54 IEEE80211_QOS_CTL_TAG1D_MASK;
55 skb_set_queue_mapping(skb, tid_to_ac[tid]);
56 ieee80211_sta_set_buffered(sta, tid, true);
57
58 spin_lock_bh(&dev->ps_lock);
59 __skb_queue_tail(&msta->psq, skb);
60 if (skb_queue_len(&msta->psq) >= 64) {
61 skb = __skb_dequeue(&msta->psq);
62 dev_kfree_skb(skb);
63 }
64 spin_unlock_bh(&dev->ps_lock);
65 return;
66
67 free:
68 dev_kfree_skb(skb);
69 }
70
mt7603_queue_rx_skb(struct mt76_dev * mdev,enum mt76_rxq_id q,struct sk_buff * skb,u32 * info)71 void mt7603_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
72 struct sk_buff *skb, u32 *info)
73 {
74 struct mt7603_dev *dev = container_of(mdev, struct mt7603_dev, mt76);
75 __le32 *rxd = (__le32 *)skb->data;
76 __le32 *end = (__le32 *)&skb->data[skb->len];
77 enum rx_pkt_type type;
78
79 type = le32_get_bits(rxd[0], MT_RXD0_PKT_TYPE);
80
81 if (q == MT_RXQ_MCU) {
82 if (type == PKT_TYPE_RX_EVENT)
83 mt76_mcu_rx_event(&dev->mt76, skb);
84 else
85 mt7603_rx_loopback_skb(dev, skb);
86 return;
87 }
88
89 switch (type) {
90 case PKT_TYPE_TXS:
91 for (rxd++; rxd + 5 <= end; rxd += 5)
92 mt7603_mac_add_txs(dev, rxd);
93 dev_kfree_skb(skb);
94 break;
95 case PKT_TYPE_RX_EVENT:
96 mt76_mcu_rx_event(&dev->mt76, skb);
97 return;
98 case PKT_TYPE_NORMAL:
99 if (mt7603_mac_fill_rx(dev, skb) == 0) {
100 mt76_rx(&dev->mt76, q, skb);
101 return;
102 }
103 fallthrough;
104 default:
105 dev_kfree_skb(skb);
106 break;
107 }
108 }
109
110 static int
mt7603_init_rx_queue(struct mt7603_dev * dev,struct mt76_queue * q,int idx,int n_desc,int bufsize)111 mt7603_init_rx_queue(struct mt7603_dev *dev, struct mt76_queue *q,
112 int idx, int n_desc, int bufsize)
113 {
114 int err;
115
116 err = mt76_queue_alloc(dev, q, idx, n_desc, bufsize,
117 MT_RX_RING_BASE);
118 if (err < 0)
119 return err;
120
121 mt7603_irq_enable(dev, MT_INT_RX_DONE(idx));
122
123 return 0;
124 }
125
mt7603_poll_tx(struct napi_struct * napi,int budget)126 static int mt7603_poll_tx(struct napi_struct *napi, int budget)
127 {
128 struct mt7603_dev *dev;
129 int i;
130
131 dev = container_of(napi, struct mt7603_dev, mt76.tx_napi);
132 dev->tx_dma_check = 0;
133
134 mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[MT_MCUQ_WM], false);
135 for (i = MT_TXQ_PSD; i >= 0; i--)
136 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[i], false);
137
138 if (napi_complete_done(napi, 0))
139 mt7603_irq_enable(dev, MT_INT_TX_DONE_ALL);
140
141 mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[MT_MCUQ_WM], false);
142 for (i = MT_TXQ_PSD; i >= 0; i--)
143 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[i], false);
144
145 mt7603_mac_sta_poll(dev);
146
147 mt76_worker_schedule(&dev->mt76.tx_worker);
148
149 return 0;
150 }
151
mt7603_dma_init(struct mt7603_dev * dev)152 int mt7603_dma_init(struct mt7603_dev *dev)
153 {
154 static const u8 wmm_queue_map[] = {
155 [IEEE80211_AC_BK] = 0,
156 [IEEE80211_AC_BE] = 1,
157 [IEEE80211_AC_VI] = 2,
158 [IEEE80211_AC_VO] = 3,
159 };
160 int ret;
161 int i;
162
163 mt76_dma_attach(&dev->mt76);
164
165 mt76_clear(dev, MT_WPDMA_GLO_CFG,
166 MT_WPDMA_GLO_CFG_TX_DMA_EN |
167 MT_WPDMA_GLO_CFG_RX_DMA_EN |
168 MT_WPDMA_GLO_CFG_DMA_BURST_SIZE |
169 MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE);
170
171 mt76_wr(dev, MT_WPDMA_RST_IDX, ~0);
172 mt7603_pse_client_reset(dev);
173
174 for (i = 0; i < ARRAY_SIZE(wmm_queue_map); i++) {
175 ret = mt76_init_tx_queue(&dev->mphy, i, wmm_queue_map[i],
176 MT7603_TX_RING_SIZE, MT_TX_RING_BASE, 0);
177 if (ret)
178 return ret;
179 }
180
181 ret = mt76_init_tx_queue(&dev->mphy, MT_TXQ_PSD, MT_TX_HW_QUEUE_MGMT,
182 MT7603_PSD_RING_SIZE, MT_TX_RING_BASE, 0);
183 if (ret)
184 return ret;
185
186 ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_WM, MT_TX_HW_QUEUE_MCU,
187 MT_MCU_RING_SIZE, MT_TX_RING_BASE);
188 if (ret)
189 return ret;
190
191 ret = mt76_init_tx_queue(&dev->mphy, MT_TXQ_BEACON, MT_TX_HW_QUEUE_BCN,
192 MT_MCU_RING_SIZE, MT_TX_RING_BASE, 0);
193 if (ret)
194 return ret;
195
196 ret = mt76_init_tx_queue(&dev->mphy, MT_TXQ_CAB, MT_TX_HW_QUEUE_BMC,
197 MT_MCU_RING_SIZE, MT_TX_RING_BASE, 0);
198 if (ret)
199 return ret;
200
201 mt7603_irq_enable(dev,
202 MT_INT_TX_DONE(IEEE80211_AC_VO) |
203 MT_INT_TX_DONE(IEEE80211_AC_VI) |
204 MT_INT_TX_DONE(IEEE80211_AC_BE) |
205 MT_INT_TX_DONE(IEEE80211_AC_BK) |
206 MT_INT_TX_DONE(MT_TX_HW_QUEUE_MGMT) |
207 MT_INT_TX_DONE(MT_TX_HW_QUEUE_MCU) |
208 MT_INT_TX_DONE(MT_TX_HW_QUEUE_BCN) |
209 MT_INT_TX_DONE(MT_TX_HW_QUEUE_BMC));
210
211 ret = mt7603_init_rx_queue(dev, &dev->mt76.q_rx[MT_RXQ_MCU], 1,
212 MT7603_MCU_RX_RING_SIZE, MT_RX_BUF_SIZE);
213 if (ret)
214 return ret;
215
216 ret = mt7603_init_rx_queue(dev, &dev->mt76.q_rx[MT_RXQ_MAIN], 0,
217 MT7603_RX_RING_SIZE, MT_RX_BUF_SIZE);
218 if (ret)
219 return ret;
220
221 mt76_wr(dev, MT_DELAY_INT_CFG, 0);
222 ret = mt76_init_queues(dev, mt76_dma_rx_poll);
223 if (ret)
224 return ret;
225
226 netif_napi_add_tx(&dev->mt76.tx_napi_dev, &dev->mt76.tx_napi,
227 mt7603_poll_tx);
228 napi_enable(&dev->mt76.tx_napi);
229
230 return 0;
231 }
232
mt7603_dma_cleanup(struct mt7603_dev * dev)233 void mt7603_dma_cleanup(struct mt7603_dev *dev)
234 {
235 mt76_clear(dev, MT_WPDMA_GLO_CFG,
236 MT_WPDMA_GLO_CFG_TX_DMA_EN |
237 MT_WPDMA_GLO_CFG_RX_DMA_EN |
238 MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE);
239
240 mt76_dma_cleanup(&dev->mt76);
241 }
242