1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
4 * Copyright (c) 2023, Linaro Limited
5 */
6
7 #include <linux/module.h>
8 #include <linux/of.h>
9 #include <linux/platform_device.h>
10
11 #include "pinctrl-msm.h"
12
13 #define REG_BASE 0x100000
14 #define REG_SIZE 0x1000
15 #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9)\
16 { \
17 .grp = PINCTRL_PINGROUP("gpio" #id, \
18 gpio##id##_pins, \
19 ARRAY_SIZE(gpio##id##_pins)), \
20 .funcs = (int[]){ \
21 msm_mux_gpio, /* gpio mode */ \
22 msm_mux_##f1, \
23 msm_mux_##f2, \
24 msm_mux_##f3, \
25 msm_mux_##f4, \
26 msm_mux_##f5, \
27 msm_mux_##f6, \
28 msm_mux_##f7, \
29 msm_mux_##f8, \
30 msm_mux_##f9 \
31 }, \
32 .nfuncs = 10, \
33 .ctl_reg = REG_BASE + REG_SIZE * id, \
34 .io_reg = REG_BASE + 0x4 + REG_SIZE * id, \
35 .intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \
36 .intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \
37 .intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \
38 .mux_bit = 2, \
39 .pull_bit = 0, \
40 .drv_bit = 6, \
41 .egpio_enable = 12, \
42 .egpio_present = 11, \
43 .oe_bit = 9, \
44 .in_bit = 0, \
45 .out_bit = 1, \
46 .intr_enable_bit = 0, \
47 .intr_status_bit = 0, \
48 .intr_target_bit = 5, \
49 .intr_target_width = 4, \
50 .intr_target_kpss_val = 3, \
51 .intr_raw_status_bit = 4, \
52 .intr_polarity_bit = 1, \
53 .intr_detection_bit = 2, \
54 .intr_detection_width = 2, \
55 }
56
57 #define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
58 { \
59 .grp = PINCTRL_PINGROUP(#pg_name, \
60 pg_name##_pins, \
61 ARRAY_SIZE(pg_name##_pins)), \
62 .ctl_reg = ctl, \
63 .io_reg = 0, \
64 .intr_cfg_reg = 0, \
65 .intr_status_reg = 0, \
66 .intr_target_reg = 0, \
67 .mux_bit = -1, \
68 .pull_bit = pull, \
69 .drv_bit = drv, \
70 .oe_bit = -1, \
71 .in_bit = -1, \
72 .out_bit = -1, \
73 .intr_enable_bit = -1, \
74 .intr_status_bit = -1, \
75 .intr_target_bit = -1, \
76 .intr_raw_status_bit = -1, \
77 .intr_polarity_bit = -1, \
78 .intr_detection_bit = -1, \
79 .intr_detection_width = -1, \
80 }
81
82 #define UFS_RESET(pg_name, offset) \
83 { \
84 .grp = PINCTRL_PINGROUP(#pg_name, \
85 pg_name##_pins, \
86 ARRAY_SIZE(pg_name##_pins)), \
87 .ctl_reg = offset, \
88 .io_reg = offset + 0x4, \
89 .intr_cfg_reg = 0, \
90 .intr_status_reg = 0, \
91 .intr_target_reg = 0, \
92 .mux_bit = -1, \
93 .pull_bit = 3, \
94 .drv_bit = 0, \
95 .oe_bit = -1, \
96 .in_bit = -1, \
97 .out_bit = 0, \
98 .intr_enable_bit = -1, \
99 .intr_status_bit = -1, \
100 .intr_target_bit = -1, \
101 .intr_raw_status_bit = -1, \
102 .intr_polarity_bit = -1, \
103 .intr_detection_bit = -1, \
104 .intr_detection_width = -1, \
105 }
106
107 #define QUP_I3C(qup_mode, qup_offset) \
108 { \
109 .mode = qup_mode, \
110 .offset = qup_offset, \
111 }
112
113 #define QUP_I3C_6_MODE_OFFSET 0xAF000
114 #define QUP_I3C_7_MODE_OFFSET 0xB0000
115 #define QUP_I3C_13_MODE_OFFSET 0xB1000
116 #define QUP_I3C_14_MODE_OFFSET 0xB2000
117
118 static const struct pinctrl_pin_desc sa8775p_pins[] = {
119 PINCTRL_PIN(0, "GPIO_0"),
120 PINCTRL_PIN(1, "GPIO_1"),
121 PINCTRL_PIN(2, "GPIO_2"),
122 PINCTRL_PIN(3, "GPIO_3"),
123 PINCTRL_PIN(4, "GPIO_4"),
124 PINCTRL_PIN(5, "GPIO_5"),
125 PINCTRL_PIN(6, "GPIO_6"),
126 PINCTRL_PIN(7, "GPIO_7"),
127 PINCTRL_PIN(8, "GPIO_8"),
128 PINCTRL_PIN(9, "GPIO_9"),
129 PINCTRL_PIN(10, "GPIO_10"),
130 PINCTRL_PIN(11, "GPIO_11"),
131 PINCTRL_PIN(12, "GPIO_12"),
132 PINCTRL_PIN(13, "GPIO_13"),
133 PINCTRL_PIN(14, "GPIO_14"),
134 PINCTRL_PIN(15, "GPIO_15"),
135 PINCTRL_PIN(16, "GPIO_16"),
136 PINCTRL_PIN(17, "GPIO_17"),
137 PINCTRL_PIN(18, "GPIO_18"),
138 PINCTRL_PIN(19, "GPIO_19"),
139 PINCTRL_PIN(20, "GPIO_20"),
140 PINCTRL_PIN(21, "GPIO_21"),
141 PINCTRL_PIN(22, "GPIO_22"),
142 PINCTRL_PIN(23, "GPIO_23"),
143 PINCTRL_PIN(24, "GPIO_24"),
144 PINCTRL_PIN(25, "GPIO_25"),
145 PINCTRL_PIN(26, "GPIO_26"),
146 PINCTRL_PIN(27, "GPIO_27"),
147 PINCTRL_PIN(28, "GPIO_28"),
148 PINCTRL_PIN(29, "GPIO_29"),
149 PINCTRL_PIN(30, "GPIO_30"),
150 PINCTRL_PIN(31, "GPIO_31"),
151 PINCTRL_PIN(32, "GPIO_32"),
152 PINCTRL_PIN(33, "GPIO_33"),
153 PINCTRL_PIN(34, "GPIO_34"),
154 PINCTRL_PIN(35, "GPIO_35"),
155 PINCTRL_PIN(36, "GPIO_36"),
156 PINCTRL_PIN(37, "GPIO_37"),
157 PINCTRL_PIN(38, "GPIO_38"),
158 PINCTRL_PIN(39, "GPIO_39"),
159 PINCTRL_PIN(40, "GPIO_40"),
160 PINCTRL_PIN(41, "GPIO_41"),
161 PINCTRL_PIN(42, "GPIO_42"),
162 PINCTRL_PIN(43, "GPIO_43"),
163 PINCTRL_PIN(44, "GPIO_44"),
164 PINCTRL_PIN(45, "GPIO_45"),
165 PINCTRL_PIN(46, "GPIO_46"),
166 PINCTRL_PIN(47, "GPIO_47"),
167 PINCTRL_PIN(48, "GPIO_48"),
168 PINCTRL_PIN(49, "GPIO_49"),
169 PINCTRL_PIN(50, "GPIO_50"),
170 PINCTRL_PIN(51, "GPIO_51"),
171 PINCTRL_PIN(52, "GPIO_52"),
172 PINCTRL_PIN(53, "GPIO_53"),
173 PINCTRL_PIN(54, "GPIO_54"),
174 PINCTRL_PIN(55, "GPIO_55"),
175 PINCTRL_PIN(56, "GPIO_56"),
176 PINCTRL_PIN(57, "GPIO_57"),
177 PINCTRL_PIN(58, "GPIO_58"),
178 PINCTRL_PIN(59, "GPIO_59"),
179 PINCTRL_PIN(60, "GPIO_60"),
180 PINCTRL_PIN(61, "GPIO_61"),
181 PINCTRL_PIN(62, "GPIO_62"),
182 PINCTRL_PIN(63, "GPIO_63"),
183 PINCTRL_PIN(64, "GPIO_64"),
184 PINCTRL_PIN(65, "GPIO_65"),
185 PINCTRL_PIN(66, "GPIO_66"),
186 PINCTRL_PIN(67, "GPIO_67"),
187 PINCTRL_PIN(68, "GPIO_68"),
188 PINCTRL_PIN(69, "GPIO_69"),
189 PINCTRL_PIN(70, "GPIO_70"),
190 PINCTRL_PIN(71, "GPIO_71"),
191 PINCTRL_PIN(72, "GPIO_72"),
192 PINCTRL_PIN(73, "GPIO_73"),
193 PINCTRL_PIN(74, "GPIO_74"),
194 PINCTRL_PIN(75, "GPIO_75"),
195 PINCTRL_PIN(76, "GPIO_76"),
196 PINCTRL_PIN(77, "GPIO_77"),
197 PINCTRL_PIN(78, "GPIO_78"),
198 PINCTRL_PIN(79, "GPIO_79"),
199 PINCTRL_PIN(80, "GPIO_80"),
200 PINCTRL_PIN(81, "GPIO_81"),
201 PINCTRL_PIN(82, "GPIO_82"),
202 PINCTRL_PIN(83, "GPIO_83"),
203 PINCTRL_PIN(84, "GPIO_84"),
204 PINCTRL_PIN(85, "GPIO_85"),
205 PINCTRL_PIN(86, "GPIO_86"),
206 PINCTRL_PIN(87, "GPIO_87"),
207 PINCTRL_PIN(88, "GPIO_88"),
208 PINCTRL_PIN(89, "GPIO_89"),
209 PINCTRL_PIN(90, "GPIO_90"),
210 PINCTRL_PIN(91, "GPIO_91"),
211 PINCTRL_PIN(92, "GPIO_92"),
212 PINCTRL_PIN(93, "GPIO_93"),
213 PINCTRL_PIN(94, "GPIO_94"),
214 PINCTRL_PIN(95, "GPIO_95"),
215 PINCTRL_PIN(96, "GPIO_96"),
216 PINCTRL_PIN(97, "GPIO_97"),
217 PINCTRL_PIN(98, "GPIO_98"),
218 PINCTRL_PIN(99, "GPIO_99"),
219 PINCTRL_PIN(100, "GPIO_100"),
220 PINCTRL_PIN(101, "GPIO_101"),
221 PINCTRL_PIN(102, "GPIO_102"),
222 PINCTRL_PIN(103, "GPIO_103"),
223 PINCTRL_PIN(104, "GPIO_104"),
224 PINCTRL_PIN(105, "GPIO_105"),
225 PINCTRL_PIN(106, "GPIO_106"),
226 PINCTRL_PIN(107, "GPIO_107"),
227 PINCTRL_PIN(108, "GPIO_108"),
228 PINCTRL_PIN(109, "GPIO_109"),
229 PINCTRL_PIN(110, "GPIO_110"),
230 PINCTRL_PIN(111, "GPIO_111"),
231 PINCTRL_PIN(112, "GPIO_112"),
232 PINCTRL_PIN(113, "GPIO_113"),
233 PINCTRL_PIN(114, "GPIO_114"),
234 PINCTRL_PIN(115, "GPIO_115"),
235 PINCTRL_PIN(116, "GPIO_116"),
236 PINCTRL_PIN(117, "GPIO_117"),
237 PINCTRL_PIN(118, "GPIO_118"),
238 PINCTRL_PIN(119, "GPIO_119"),
239 PINCTRL_PIN(120, "GPIO_120"),
240 PINCTRL_PIN(121, "GPIO_121"),
241 PINCTRL_PIN(122, "GPIO_122"),
242 PINCTRL_PIN(123, "GPIO_123"),
243 PINCTRL_PIN(124, "GPIO_124"),
244 PINCTRL_PIN(125, "GPIO_125"),
245 PINCTRL_PIN(126, "GPIO_126"),
246 PINCTRL_PIN(127, "GPIO_127"),
247 PINCTRL_PIN(128, "GPIO_128"),
248 PINCTRL_PIN(129, "GPIO_129"),
249 PINCTRL_PIN(130, "GPIO_130"),
250 PINCTRL_PIN(131, "GPIO_131"),
251 PINCTRL_PIN(132, "GPIO_132"),
252 PINCTRL_PIN(133, "GPIO_133"),
253 PINCTRL_PIN(134, "GPIO_134"),
254 PINCTRL_PIN(135, "GPIO_135"),
255 PINCTRL_PIN(136, "GPIO_136"),
256 PINCTRL_PIN(137, "GPIO_137"),
257 PINCTRL_PIN(138, "GPIO_138"),
258 PINCTRL_PIN(139, "GPIO_139"),
259 PINCTRL_PIN(140, "GPIO_140"),
260 PINCTRL_PIN(141, "GPIO_141"),
261 PINCTRL_PIN(142, "GPIO_142"),
262 PINCTRL_PIN(143, "GPIO_143"),
263 PINCTRL_PIN(144, "GPIO_144"),
264 PINCTRL_PIN(145, "GPIO_145"),
265 PINCTRL_PIN(146, "GPIO_146"),
266 PINCTRL_PIN(147, "GPIO_147"),
267 PINCTRL_PIN(148, "GPIO_148"),
268 PINCTRL_PIN(149, "UFS_RESET"),
269 PINCTRL_PIN(150, "SDC1_RCLK"),
270 PINCTRL_PIN(151, "SDC1_CLK"),
271 PINCTRL_PIN(152, "SDC1_CMD"),
272 PINCTRL_PIN(153, "SDC1_DATA"),
273 };
274
275 #define DECLARE_MSM_GPIO_PINS(pin) \
276 static const unsigned int gpio##pin##_pins[] = { pin }
277 DECLARE_MSM_GPIO_PINS(0);
278 DECLARE_MSM_GPIO_PINS(1);
279 DECLARE_MSM_GPIO_PINS(2);
280 DECLARE_MSM_GPIO_PINS(3);
281 DECLARE_MSM_GPIO_PINS(4);
282 DECLARE_MSM_GPIO_PINS(5);
283 DECLARE_MSM_GPIO_PINS(6);
284 DECLARE_MSM_GPIO_PINS(7);
285 DECLARE_MSM_GPIO_PINS(8);
286 DECLARE_MSM_GPIO_PINS(9);
287 DECLARE_MSM_GPIO_PINS(10);
288 DECLARE_MSM_GPIO_PINS(11);
289 DECLARE_MSM_GPIO_PINS(12);
290 DECLARE_MSM_GPIO_PINS(13);
291 DECLARE_MSM_GPIO_PINS(14);
292 DECLARE_MSM_GPIO_PINS(15);
293 DECLARE_MSM_GPIO_PINS(16);
294 DECLARE_MSM_GPIO_PINS(17);
295 DECLARE_MSM_GPIO_PINS(18);
296 DECLARE_MSM_GPIO_PINS(19);
297 DECLARE_MSM_GPIO_PINS(20);
298 DECLARE_MSM_GPIO_PINS(21);
299 DECLARE_MSM_GPIO_PINS(22);
300 DECLARE_MSM_GPIO_PINS(23);
301 DECLARE_MSM_GPIO_PINS(24);
302 DECLARE_MSM_GPIO_PINS(25);
303 DECLARE_MSM_GPIO_PINS(26);
304 DECLARE_MSM_GPIO_PINS(27);
305 DECLARE_MSM_GPIO_PINS(28);
306 DECLARE_MSM_GPIO_PINS(29);
307 DECLARE_MSM_GPIO_PINS(30);
308 DECLARE_MSM_GPIO_PINS(31);
309 DECLARE_MSM_GPIO_PINS(32);
310 DECLARE_MSM_GPIO_PINS(33);
311 DECLARE_MSM_GPIO_PINS(34);
312 DECLARE_MSM_GPIO_PINS(35);
313 DECLARE_MSM_GPIO_PINS(36);
314 DECLARE_MSM_GPIO_PINS(37);
315 DECLARE_MSM_GPIO_PINS(38);
316 DECLARE_MSM_GPIO_PINS(39);
317 DECLARE_MSM_GPIO_PINS(40);
318 DECLARE_MSM_GPIO_PINS(41);
319 DECLARE_MSM_GPIO_PINS(42);
320 DECLARE_MSM_GPIO_PINS(43);
321 DECLARE_MSM_GPIO_PINS(44);
322 DECLARE_MSM_GPIO_PINS(45);
323 DECLARE_MSM_GPIO_PINS(46);
324 DECLARE_MSM_GPIO_PINS(47);
325 DECLARE_MSM_GPIO_PINS(48);
326 DECLARE_MSM_GPIO_PINS(49);
327 DECLARE_MSM_GPIO_PINS(50);
328 DECLARE_MSM_GPIO_PINS(51);
329 DECLARE_MSM_GPIO_PINS(52);
330 DECLARE_MSM_GPIO_PINS(53);
331 DECLARE_MSM_GPIO_PINS(54);
332 DECLARE_MSM_GPIO_PINS(55);
333 DECLARE_MSM_GPIO_PINS(56);
334 DECLARE_MSM_GPIO_PINS(57);
335 DECLARE_MSM_GPIO_PINS(58);
336 DECLARE_MSM_GPIO_PINS(59);
337 DECLARE_MSM_GPIO_PINS(60);
338 DECLARE_MSM_GPIO_PINS(61);
339 DECLARE_MSM_GPIO_PINS(62);
340 DECLARE_MSM_GPIO_PINS(63);
341 DECLARE_MSM_GPIO_PINS(64);
342 DECLARE_MSM_GPIO_PINS(65);
343 DECLARE_MSM_GPIO_PINS(66);
344 DECLARE_MSM_GPIO_PINS(67);
345 DECLARE_MSM_GPIO_PINS(68);
346 DECLARE_MSM_GPIO_PINS(69);
347 DECLARE_MSM_GPIO_PINS(70);
348 DECLARE_MSM_GPIO_PINS(71);
349 DECLARE_MSM_GPIO_PINS(72);
350 DECLARE_MSM_GPIO_PINS(73);
351 DECLARE_MSM_GPIO_PINS(74);
352 DECLARE_MSM_GPIO_PINS(75);
353 DECLARE_MSM_GPIO_PINS(76);
354 DECLARE_MSM_GPIO_PINS(77);
355 DECLARE_MSM_GPIO_PINS(78);
356 DECLARE_MSM_GPIO_PINS(79);
357 DECLARE_MSM_GPIO_PINS(80);
358 DECLARE_MSM_GPIO_PINS(81);
359 DECLARE_MSM_GPIO_PINS(82);
360 DECLARE_MSM_GPIO_PINS(83);
361 DECLARE_MSM_GPIO_PINS(84);
362 DECLARE_MSM_GPIO_PINS(85);
363 DECLARE_MSM_GPIO_PINS(86);
364 DECLARE_MSM_GPIO_PINS(87);
365 DECLARE_MSM_GPIO_PINS(88);
366 DECLARE_MSM_GPIO_PINS(89);
367 DECLARE_MSM_GPIO_PINS(90);
368 DECLARE_MSM_GPIO_PINS(91);
369 DECLARE_MSM_GPIO_PINS(92);
370 DECLARE_MSM_GPIO_PINS(93);
371 DECLARE_MSM_GPIO_PINS(94);
372 DECLARE_MSM_GPIO_PINS(95);
373 DECLARE_MSM_GPIO_PINS(96);
374 DECLARE_MSM_GPIO_PINS(97);
375 DECLARE_MSM_GPIO_PINS(98);
376 DECLARE_MSM_GPIO_PINS(99);
377 DECLARE_MSM_GPIO_PINS(100);
378 DECLARE_MSM_GPIO_PINS(101);
379 DECLARE_MSM_GPIO_PINS(102);
380 DECLARE_MSM_GPIO_PINS(103);
381 DECLARE_MSM_GPIO_PINS(104);
382 DECLARE_MSM_GPIO_PINS(105);
383 DECLARE_MSM_GPIO_PINS(106);
384 DECLARE_MSM_GPIO_PINS(107);
385 DECLARE_MSM_GPIO_PINS(108);
386 DECLARE_MSM_GPIO_PINS(109);
387 DECLARE_MSM_GPIO_PINS(110);
388 DECLARE_MSM_GPIO_PINS(111);
389 DECLARE_MSM_GPIO_PINS(112);
390 DECLARE_MSM_GPIO_PINS(113);
391 DECLARE_MSM_GPIO_PINS(114);
392 DECLARE_MSM_GPIO_PINS(115);
393 DECLARE_MSM_GPIO_PINS(116);
394 DECLARE_MSM_GPIO_PINS(117);
395 DECLARE_MSM_GPIO_PINS(118);
396 DECLARE_MSM_GPIO_PINS(119);
397 DECLARE_MSM_GPIO_PINS(120);
398 DECLARE_MSM_GPIO_PINS(121);
399 DECLARE_MSM_GPIO_PINS(122);
400 DECLARE_MSM_GPIO_PINS(123);
401 DECLARE_MSM_GPIO_PINS(124);
402 DECLARE_MSM_GPIO_PINS(125);
403 DECLARE_MSM_GPIO_PINS(126);
404 DECLARE_MSM_GPIO_PINS(127);
405 DECLARE_MSM_GPIO_PINS(128);
406 DECLARE_MSM_GPIO_PINS(129);
407 DECLARE_MSM_GPIO_PINS(130);
408 DECLARE_MSM_GPIO_PINS(131);
409 DECLARE_MSM_GPIO_PINS(132);
410 DECLARE_MSM_GPIO_PINS(133);
411 DECLARE_MSM_GPIO_PINS(134);
412 DECLARE_MSM_GPIO_PINS(135);
413 DECLARE_MSM_GPIO_PINS(136);
414 DECLARE_MSM_GPIO_PINS(137);
415 DECLARE_MSM_GPIO_PINS(138);
416 DECLARE_MSM_GPIO_PINS(139);
417 DECLARE_MSM_GPIO_PINS(140);
418 DECLARE_MSM_GPIO_PINS(141);
419 DECLARE_MSM_GPIO_PINS(142);
420 DECLARE_MSM_GPIO_PINS(143);
421 DECLARE_MSM_GPIO_PINS(144);
422 DECLARE_MSM_GPIO_PINS(145);
423 DECLARE_MSM_GPIO_PINS(146);
424 DECLARE_MSM_GPIO_PINS(147);
425 DECLARE_MSM_GPIO_PINS(148);
426
427 static const unsigned int ufs_reset_pins[] = { 149 };
428 static const unsigned int sdc1_rclk_pins[] = { 150 };
429 static const unsigned int sdc1_clk_pins[] = { 151 };
430 static const unsigned int sdc1_cmd_pins[] = { 152 };
431 static const unsigned int sdc1_data_pins[] = { 153 };
432
433 enum sa8775p_functions {
434 msm_mux_gpio,
435 msm_mux_atest_char,
436 msm_mux_atest_usb2,
437 msm_mux_audio_ref,
438 msm_mux_cam_mclk,
439 msm_mux_cci_async,
440 msm_mux_cci_i2c,
441 msm_mux_cci_timer0,
442 msm_mux_cci_timer1,
443 msm_mux_cci_timer2,
444 msm_mux_cci_timer3,
445 msm_mux_cci_timer4,
446 msm_mux_cci_timer5,
447 msm_mux_cci_timer6,
448 msm_mux_cci_timer7,
449 msm_mux_cci_timer8,
450 msm_mux_cci_timer9,
451 msm_mux_cri_trng,
452 msm_mux_cri_trng0,
453 msm_mux_cri_trng1,
454 msm_mux_dbg_out,
455 msm_mux_ddr_bist,
456 msm_mux_ddr_pxi0,
457 msm_mux_ddr_pxi1,
458 msm_mux_ddr_pxi2,
459 msm_mux_ddr_pxi3,
460 msm_mux_ddr_pxi4,
461 msm_mux_ddr_pxi5,
462 msm_mux_edp0_hot,
463 msm_mux_edp0_lcd,
464 msm_mux_edp1_hot,
465 msm_mux_edp1_lcd,
466 msm_mux_edp2_hot,
467 msm_mux_edp2_lcd,
468 msm_mux_edp3_hot,
469 msm_mux_edp3_lcd,
470 msm_mux_emac0_mcg0,
471 msm_mux_emac0_mcg1,
472 msm_mux_emac0_mcg2,
473 msm_mux_emac0_mcg3,
474 msm_mux_emac0_mdc,
475 msm_mux_emac0_mdio,
476 msm_mux_emac0_ptp_aux,
477 msm_mux_emac0_ptp_pps,
478 msm_mux_emac1_mcg0,
479 msm_mux_emac1_mcg1,
480 msm_mux_emac1_mcg2,
481 msm_mux_emac1_mcg3,
482 msm_mux_emac1_mdc,
483 msm_mux_emac1_mdio,
484 msm_mux_emac1_ptp_aux,
485 msm_mux_emac1_ptp_pps,
486 msm_mux_gcc_gp1,
487 msm_mux_gcc_gp2,
488 msm_mux_gcc_gp3,
489 msm_mux_gcc_gp4,
490 msm_mux_gcc_gp5,
491 msm_mux_hs0_mi2s,
492 msm_mux_hs1_mi2s,
493 msm_mux_hs2_mi2s,
494 msm_mux_ibi_i3c,
495 msm_mux_jitter_bist,
496 msm_mux_mdp0_vsync0,
497 msm_mux_mdp0_vsync1,
498 msm_mux_mdp0_vsync2,
499 msm_mux_mdp0_vsync3,
500 msm_mux_mdp0_vsync4,
501 msm_mux_mdp0_vsync5,
502 msm_mux_mdp0_vsync6,
503 msm_mux_mdp0_vsync7,
504 msm_mux_mdp0_vsync8,
505 msm_mux_mdp1_vsync0,
506 msm_mux_mdp1_vsync1,
507 msm_mux_mdp1_vsync2,
508 msm_mux_mdp1_vsync3,
509 msm_mux_mdp1_vsync4,
510 msm_mux_mdp1_vsync5,
511 msm_mux_mdp1_vsync6,
512 msm_mux_mdp1_vsync7,
513 msm_mux_mdp1_vsync8,
514 msm_mux_mdp_vsync,
515 msm_mux_mi2s1_data0,
516 msm_mux_mi2s1_data1,
517 msm_mux_mi2s1_sck,
518 msm_mux_mi2s1_ws,
519 msm_mux_mi2s2_data0,
520 msm_mux_mi2s2_data1,
521 msm_mux_mi2s2_sck,
522 msm_mux_mi2s2_ws,
523 msm_mux_mi2s_mclk0,
524 msm_mux_mi2s_mclk1,
525 msm_mux_pcie0_clkreq,
526 msm_mux_pcie1_clkreq,
527 msm_mux_phase_flag,
528 msm_mux_pll_bist,
529 msm_mux_pll_clk,
530 msm_mux_prng_rosc0,
531 msm_mux_prng_rosc1,
532 msm_mux_prng_rosc2,
533 msm_mux_prng_rosc3,
534 msm_mux_qdss_cti,
535 msm_mux_qdss_gpio,
536 msm_mux_qup0_se0,
537 msm_mux_qup0_se1,
538 msm_mux_qup0_se2,
539 msm_mux_qup0_se3,
540 msm_mux_qup0_se4,
541 msm_mux_qup0_se5,
542 msm_mux_qup1_se0,
543 msm_mux_qup1_se1,
544 msm_mux_qup1_se2,
545 msm_mux_qup1_se3,
546 msm_mux_qup1_se4,
547 msm_mux_qup1_se5,
548 msm_mux_qup1_se6,
549 msm_mux_qup2_se0,
550 msm_mux_qup2_se1,
551 msm_mux_qup2_se2,
552 msm_mux_qup2_se3,
553 msm_mux_qup2_se4,
554 msm_mux_qup2_se5,
555 msm_mux_qup2_se6,
556 msm_mux_qup3_se0,
557 msm_mux_sail_top,
558 msm_mux_sailss_emac0,
559 msm_mux_sailss_ospi,
560 msm_mux_sgmii_phy,
561 msm_mux_tb_trig,
562 msm_mux_tgu_ch0,
563 msm_mux_tgu_ch1,
564 msm_mux_tgu_ch2,
565 msm_mux_tgu_ch3,
566 msm_mux_tgu_ch4,
567 msm_mux_tgu_ch5,
568 msm_mux_tsense_pwm1,
569 msm_mux_tsense_pwm2,
570 msm_mux_tsense_pwm3,
571 msm_mux_tsense_pwm4,
572 msm_mux_usb2phy_ac,
573 msm_mux_vsense_trigger,
574 msm_mux__,
575 };
576
577 static const char * const gpio_groups[] = {
578 "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
579 "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
580 "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
581 "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
582 "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
583 "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
584 "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
585 "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
586 "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
587 "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70",
588 "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
589 "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
590 "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91",
591 "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98",
592 "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104",
593 "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110",
594 "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116",
595 "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122",
596 "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128",
597 "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134",
598 "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140",
599 "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146",
600 "gpio147", "gpio148",
601 };
602
603 static const char * const atest_char_groups[] = {
604 "gpio27", "gpio58", "gpio59", "gpio89", "gpio90",
605 };
606
607 static const char * const atest_usb2_groups[] = {
608 "gpio58", "gpio59", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90",
609 "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97",
610 "gpio105",
611 };
612
613 static const char * const audio_ref_groups[] = {
614 "gpio113",
615 };
616
617 static const char * const cam_mclk_groups[] = {
618 "gpio72", "gpio73", "gpio74", "gpio75",
619 };
620
621 static const char * const cci_async_groups[] = {
622 "gpio50", "gpio66", "gpio68", "gpio69", "gpio70", "gpio71",
623 };
624
625 static const char * const cci_i2c_groups[] = {
626 "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", "gpio57", "gpio58",
627 "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", "gpio64", "gpio65",
628 "gpio66", "gpio67",
629 };
630
631 static const char * const cci_timer0_groups[] = {
632 "gpio68",
633 };
634
635 static const char * const cci_timer1_groups[] = {
636 "gpio69",
637 };
638
639 static const char * const cci_timer2_groups[] = {
640 "gpio70",
641 };
642
643 static const char * const cci_timer3_groups[] = {
644 "gpio71",
645 };
646
647 static const char * const cci_timer4_groups[] = {
648 "gpio52",
649 };
650
651 static const char * const cci_timer5_groups[] = {
652 "gpio53",
653 };
654
655 static const char * const cci_timer6_groups[] = {
656 "gpio54",
657 };
658
659 static const char * const cci_timer7_groups[] = {
660 "gpio55",
661 };
662
663 static const char * const cci_timer8_groups[] = {
664 "gpio56",
665 };
666
667 static const char * const cci_timer9_groups[] = {
668 "gpio57",
669 };
670
671 static const char * const cri_trng_groups[] = {
672 "gpio99",
673 };
674
675 static const char * const cri_trng0_groups[] = {
676 "gpio97",
677 };
678
679 static const char * const cri_trng1_groups[] = {
680 "gpio98",
681 };
682
683 static const char * const dbg_out_groups[] = {
684 "gpio144",
685 };
686
687 static const char * const ddr_bist_groups[] = {
688 "gpio56", "gpio57", "gpio58", "gpio59",
689 };
690
691 static const char * const ddr_pxi0_groups[] = {
692 "gpio33", "gpio34",
693 };
694
695 static const char * const ddr_pxi1_groups[] = {
696 "gpio52", "gpio53",
697 };
698
699 static const char * const ddr_pxi2_groups[] = {
700 "gpio55", "gpio86",
701 };
702
703 static const char * const ddr_pxi3_groups[] = {
704 "gpio87", "gpio88",
705 };
706
707 static const char * const ddr_pxi4_groups[] = {
708 "gpio89", "gpio90",
709 };
710
711 static const char * const ddr_pxi5_groups[] = {
712 "gpio118", "gpio119",
713 };
714
715 static const char * const edp0_hot_groups[] = {
716 "gpio101",
717 };
718
719 static const char * const edp0_lcd_groups[] = {
720 "gpio44",
721 };
722
723 static const char * const edp1_hot_groups[] = {
724 "gpio102",
725 };
726
727 static const char * const edp1_lcd_groups[] = {
728 "gpio45",
729 };
730
731 static const char * const edp2_hot_groups[] = {
732 "gpio104",
733 };
734
735 static const char * const edp2_lcd_groups[] = {
736 "gpio48",
737 };
738
739 static const char * const edp3_hot_groups[] = {
740 "gpio103",
741 };
742
743 static const char * const edp3_lcd_groups[] = {
744 "gpio49",
745 };
746
747 static const char * const emac0_mcg0_groups[] = {
748 "gpio12",
749 };
750
751 static const char * const emac0_mcg1_groups[] = {
752 "gpio13",
753 };
754
755 static const char * const emac0_mcg2_groups[] = {
756 "gpio14",
757 };
758
759 static const char * const emac0_mcg3_groups[] = {
760 "gpio15",
761 };
762
763 static const char * const emac0_mdc_groups[] = {
764 "gpio8",
765 };
766
767 static const char * const emac0_mdio_groups[] = {
768 "gpio9",
769 };
770
771 static const char * const emac0_ptp_aux_groups[] = {
772 "gpio6", "gpio10", "gpio11", "gpio12",
773 };
774
775 static const char * const emac0_ptp_pps_groups[] = {
776 "gpio6", "gpio10", "gpio11", "gpio12",
777 };
778
779 static const char * const emac1_mcg0_groups[] = {
780 "gpio16",
781
782 };
783
784 static const char * const emac1_mcg1_groups[] = {
785 "gpio17",
786 };
787
788 static const char * const emac1_mcg2_groups[] = {
789 "gpio18",
790 };
791
792 static const char * const emac1_mcg3_groups[] = {
793 "gpio19",
794 };
795
796 static const char * const emac1_mdc_groups[] = {
797 "gpio20",
798 };
799
800 static const char * const emac1_mdio_groups[] = {
801 "gpio21",
802 };
803
804 static const char * const emac1_ptp_aux_groups[] = {
805 "gpio6", "gpio10", "gpio11", "gpio12",
806 };
807
808 static const char * const emac1_ptp_pps_groups[] = {
809 "gpio6", "gpio10", "gpio11", "gpio12",
810 };
811
812 static const char * const gcc_gp1_groups[] = {
813 "gpio51", "gpio82",
814 };
815
816 static const char * const gcc_gp2_groups[] = {
817 "gpio52", "gpio83",
818 };
819
820 static const char * const gcc_gp3_groups[] = {
821 "gpio53", "gpio84",
822 };
823
824 static const char * const gcc_gp4_groups[] = {
825 "gpio33", "gpio55",
826 };
827
828 static const char * const gcc_gp5_groups[] = {
829 "gpio34", "gpio42",
830 };
831
832 static const char * const hs0_mi2s_groups[] = {
833 "gpio114", "gpio115", "gpio116", "gpio117",
834 };
835
836 static const char * const hs1_mi2s_groups[] = {
837 "gpio118", "gpio119", "gpio120", "gpio121",
838 };
839
840 static const char * const hs2_mi2s_groups[] = {
841 "gpio122", "gpio123", "gpio124", "gpio125",
842 };
843
844 static const char * const ibi_i3c_groups[] = {
845 "gpio40", "gpio41", "gpio42", "gpio43", "gpio80", "gpio81", "gpio84",
846 "gpio85",
847 };
848
849 static const char * const jitter_bist_groups[] = {
850 "gpio86",
851 };
852
853 static const char * const mdp0_vsync0_groups[] = {
854 "gpio57",
855 };
856
857 static const char * const mdp0_vsync1_groups[] = {
858 "gpio58",
859 };
860
861 static const char * const mdp0_vsync2_groups[] = {
862 "gpio59",
863 };
864
865 static const char * const mdp0_vsync3_groups[] = {
866 "gpio80",
867 };
868
869 static const char * const mdp0_vsync4_groups[] = {
870 "gpio81",
871 };
872
873 static const char * const mdp0_vsync5_groups[] = {
874 "gpio91",
875 };
876
877 static const char * const mdp0_vsync6_groups[] = {
878 "gpio92",
879 };
880
881 static const char * const mdp0_vsync7_groups[] = {
882 "gpio93",
883 };
884
885 static const char * const mdp0_vsync8_groups[] = {
886 "gpio94",
887 };
888
889 static const char * const mdp1_vsync0_groups[] = {
890 "gpio40",
891 };
892
893 static const char * const mdp1_vsync1_groups[] = {
894 "gpio41",
895 };
896
897 static const char * const mdp1_vsync2_groups[] = {
898 "gpio42",
899 };
900
901 static const char * const mdp1_vsync3_groups[] = {
902 "gpio43",
903 };
904
905 static const char * const mdp1_vsync4_groups[] = {
906 "gpio46",
907 };
908
909 static const char * const mdp1_vsync5_groups[] = {
910 "gpio47",
911 };
912
913 static const char * const mdp1_vsync6_groups[] = {
914 "gpio51",
915 };
916
917 static const char * const mdp1_vsync7_groups[] = {
918 "gpio52",
919 };
920
921 static const char * const mdp1_vsync8_groups[] = {
922 "gpio50",
923 };
924
925 static const char * const mdp_vsync_groups[] = {
926 "gpio82", "gpio83", "gpio84",
927 };
928
929 static const char * const mi2s1_data0_groups[] = {
930 "gpio108",
931 };
932
933 static const char * const mi2s1_data1_groups[] = {
934 "gpio109",
935 };
936
937 static const char * const mi2s1_sck_groups[] = {
938 "gpio106",
939 };
940
941 static const char * const mi2s1_ws_groups[] = {
942 "gpio107",
943 };
944
945 static const char * const mi2s2_data0_groups[] = {
946 "gpio112",
947 };
948
949 static const char * const mi2s2_data1_groups[] = {
950 "gpio113",
951 };
952
953 static const char * const mi2s2_sck_groups[] = {
954 "gpio110",
955 };
956
957 static const char * const mi2s2_ws_groups[] = {
958 "gpio111",
959 };
960
961 static const char * const mi2s_mclk0_groups[] = {
962 "gpio105",
963 };
964
965 static const char * const mi2s_mclk1_groups[] = {
966 "gpio117",
967 };
968
969 static const char * const pcie0_clkreq_groups[] = {
970 "gpio1",
971 };
972
973 static const char * const pcie1_clkreq_groups[] = {
974 "gpio3",
975 };
976
977 static const char * const phase_flag_groups[] = {
978 "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", "gpio30", "gpio31",
979 "gpio32", "gpio35", "gpio36", "gpio37", "gpio38", "gpio39", "gpio56",
980 "gpio57", "gpio98", "gpio99", "gpio106", "gpio107", "gpio108",
981 "gpio109", "gpio110", "gpio111", "gpio112", "gpio113", "gpio114",
982 "gpio120", "gpio121", "gpio122", "gpio123", "gpio124", "gpio125",
983 };
984
985 static const char * const pll_bist_groups[] = {
986 "gpio114",
987 };
988
989 static const char * const pll_clk_groups[] = {
990 "gpio87",
991 };
992
993 static const char * const prng_rosc0_groups[] = {
994 "gpio101",
995 };
996
997 static const char * const prng_rosc1_groups[] = {
998 "gpio102",
999 };
1000
1001 static const char * const prng_rosc2_groups[] = {
1002 "gpio103",
1003 };
1004
1005 static const char * const prng_rosc3_groups[] = {
1006 "gpio104",
1007 };
1008
1009 static const char * const qdss_cti_groups[] = {
1010 "gpio26", "gpio27", "gpio38", "gpio39", "gpio48", "gpio49", "gpio50",
1011 "gpio51",
1012 };
1013
1014 static const char * const qdss_gpio_groups[] = {
1015 "gpio20", "gpio21", "gpio22", "gpio23", "gpio24", "gpio25", "gpio28",
1016 "gpio29", "gpio30", "gpio31", "gpio60", "gpio61", "gpio62", "gpio63",
1017 "gpio64", "gpio65", "gpio66", "gpio67", "gpio105", "gpio106", "gpio107",
1018 "gpio108", "gpio109", "gpio110", "gpio111", "gpio112", "gpio113",
1019 "gpio114", "gpio115", "gpio116", "gpio117", "gpio118", "gpio119",
1020 "gpio120", "gpio121", "gpio122",
1021 };
1022
1023 static const char * const qup0_se0_groups[] = {
1024 "gpio20", "gpio21", "gpio22", "gpio23",
1025 };
1026
1027 static const char * const qup0_se1_groups[] = {
1028 "gpio24", "gpio25", "gpio26", "gpio27",
1029 };
1030
1031 static const char * const qup0_se2_groups[] = {
1032 "gpio36", "gpio37", "gpio38", "gpio39",
1033 };
1034
1035 static const char * const qup0_se3_groups[] = {
1036 "gpio28", "gpio29", "gpio30", "gpio31",
1037 };
1038
1039 static const char * const qup0_se4_groups[] = {
1040 "gpio32", "gpio33", "gpio34", "gpio35",
1041 };
1042
1043 static const char * const qup0_se5_groups[] = {
1044 "gpio36", "gpio37", "gpio38", "gpio39",
1045 };
1046
1047 static const char * const qup1_se0_groups[] = {
1048 "gpio40", "gpio41", "gpio42", "gpio43",
1049 };
1050
1051 static const char * const qup1_se1_groups[] = {
1052 "gpio40", "gpio41", "gpio42", "gpio43",
1053 };
1054
1055 static const char * const qup1_se2_groups[] = {
1056 "gpio44", "gpio45", "gpio46", "gpio47",
1057 };
1058
1059 static const char * const qup1_se3_groups[] = {
1060 "gpio44", "gpio45", "gpio46", "gpio47",
1061 };
1062
1063 static const char * const qup1_se4_groups[] = {
1064 "gpio48", "gpio49", "gpio50", "gpio51",
1065 };
1066
1067 static const char * const qup1_se5_groups[] = {
1068 "gpio52", "gpio53", "gpio54", "gpio55",
1069 };
1070
1071 static const char * const qup1_se6_groups[] = {
1072 "gpio56", "gpio56", "gpio57", "gpio57",
1073 };
1074
1075 static const char * const qup2_se0_groups[] = {
1076 "gpio80", "gpio81", "gpio82", "gpio83",
1077 };
1078
1079 static const char * const qup2_se1_groups[] = {
1080 "gpio84", "gpio85", "gpio99", "gpio100",
1081 };
1082
1083 static const char * const qup2_se2_groups[] = {
1084 "gpio86", "gpio87", "gpio88", "gpio89", "gpio90",
1085 };
1086
1087 static const char * const qup2_se3_groups[] = {
1088 "gpio91", "gpio92", "gpio93", "gpio94",
1089 };
1090
1091 static const char * const qup2_se4_groups[] = {
1092 "gpio95", "gpio96", "gpio97", "gpio98",
1093 };
1094
1095 static const char * const qup2_se5_groups[] = {
1096 "gpio84", "gpio85", "gpio99", "gpio100",
1097 };
1098
1099 static const char * const qup2_se6_groups[] = {
1100 "gpio95", "gpio96", "gpio97", "gpio98",
1101 };
1102
1103 static const char * const qup3_se0_groups[] = {
1104 "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19",
1105 };
1106
1107 static const char * const sail_top_groups[] = {
1108 "gpio13", "gpio14", "gpio15", "gpio16",
1109 };
1110
1111 static const char * const sailss_emac0_groups[] = {
1112 "gpio18", "gpio19",
1113 };
1114
1115 static const char * const sailss_ospi_groups[] = {
1116 "gpio18", "gpio19",
1117 };
1118
1119 static const char * const sgmii_phy_groups[] = {
1120 "gpio7", "gpio26",
1121 };
1122
1123 static const char * const tb_trig_groups[] = {
1124 "gpio17", "gpio17",
1125 };
1126
1127 static const char * const tgu_ch0_groups[] = {
1128 "gpio46",
1129 };
1130
1131 static const char * const tgu_ch1_groups[] = {
1132 "gpio47",
1133 };
1134
1135 static const char * const tgu_ch2_groups[] = {
1136 "gpio36",
1137 };
1138
1139 static const char * const tgu_ch3_groups[] = {
1140 "gpio37",
1141 };
1142
1143 static const char * const tgu_ch4_groups[] = {
1144 "gpio38",
1145 };
1146
1147 static const char * const tgu_ch5_groups[] = {
1148 "gpio39",
1149 };
1150
1151 static const char * const tsense_pwm1_groups[] = {
1152 "gpio104",
1153 };
1154
1155 static const char * const tsense_pwm2_groups[] = {
1156 "gpio103",
1157 };
1158
1159 static const char * const tsense_pwm3_groups[] = {
1160 "gpio102",
1161 };
1162
1163 static const char * const tsense_pwm4_groups[] = {
1164 "gpio101",
1165 };
1166
1167 static const char * const usb2phy_ac_groups[] = {
1168 "gpio10", "gpio11", "gpio12",
1169 };
1170
1171 static const char * const vsense_trigger_groups[] = {
1172 "gpio111",
1173 };
1174
1175 static const struct pinfunction sa8775p_functions[] = {
1176 MSM_PIN_FUNCTION(gpio),
1177 MSM_PIN_FUNCTION(atest_char),
1178 MSM_PIN_FUNCTION(atest_usb2),
1179 MSM_PIN_FUNCTION(audio_ref),
1180 MSM_PIN_FUNCTION(cam_mclk),
1181 MSM_PIN_FUNCTION(cci_async),
1182 MSM_PIN_FUNCTION(cci_i2c),
1183 MSM_PIN_FUNCTION(cci_timer0),
1184 MSM_PIN_FUNCTION(cci_timer1),
1185 MSM_PIN_FUNCTION(cci_timer2),
1186 MSM_PIN_FUNCTION(cci_timer3),
1187 MSM_PIN_FUNCTION(cci_timer4),
1188 MSM_PIN_FUNCTION(cci_timer5),
1189 MSM_PIN_FUNCTION(cci_timer6),
1190 MSM_PIN_FUNCTION(cci_timer7),
1191 MSM_PIN_FUNCTION(cci_timer8),
1192 MSM_PIN_FUNCTION(cci_timer9),
1193 MSM_PIN_FUNCTION(cri_trng),
1194 MSM_PIN_FUNCTION(cri_trng0),
1195 MSM_PIN_FUNCTION(cri_trng1),
1196 MSM_PIN_FUNCTION(dbg_out),
1197 MSM_PIN_FUNCTION(ddr_bist),
1198 MSM_PIN_FUNCTION(ddr_pxi0),
1199 MSM_PIN_FUNCTION(ddr_pxi1),
1200 MSM_PIN_FUNCTION(ddr_pxi2),
1201 MSM_PIN_FUNCTION(ddr_pxi3),
1202 MSM_PIN_FUNCTION(ddr_pxi4),
1203 MSM_PIN_FUNCTION(ddr_pxi5),
1204 MSM_PIN_FUNCTION(edp0_hot),
1205 MSM_PIN_FUNCTION(edp0_lcd),
1206 MSM_PIN_FUNCTION(edp1_hot),
1207 MSM_PIN_FUNCTION(edp1_lcd),
1208 MSM_PIN_FUNCTION(edp2_hot),
1209 MSM_PIN_FUNCTION(edp2_lcd),
1210 MSM_PIN_FUNCTION(edp3_hot),
1211 MSM_PIN_FUNCTION(edp3_lcd),
1212 MSM_PIN_FUNCTION(emac0_mcg0),
1213 MSM_PIN_FUNCTION(emac0_mcg1),
1214 MSM_PIN_FUNCTION(emac0_mcg2),
1215 MSM_PIN_FUNCTION(emac0_mcg3),
1216 MSM_PIN_FUNCTION(emac0_mdc),
1217 MSM_PIN_FUNCTION(emac0_mdio),
1218 MSM_PIN_FUNCTION(emac0_ptp_aux),
1219 MSM_PIN_FUNCTION(emac0_ptp_pps),
1220 MSM_PIN_FUNCTION(emac1_mcg0),
1221 MSM_PIN_FUNCTION(emac1_mcg1),
1222 MSM_PIN_FUNCTION(emac1_mcg2),
1223 MSM_PIN_FUNCTION(emac1_mcg3),
1224 MSM_PIN_FUNCTION(emac1_mdc),
1225 MSM_PIN_FUNCTION(emac1_mdio),
1226 MSM_PIN_FUNCTION(emac1_ptp_aux),
1227 MSM_PIN_FUNCTION(emac1_ptp_pps),
1228 MSM_PIN_FUNCTION(gcc_gp1),
1229 MSM_PIN_FUNCTION(gcc_gp2),
1230 MSM_PIN_FUNCTION(gcc_gp3),
1231 MSM_PIN_FUNCTION(gcc_gp4),
1232 MSM_PIN_FUNCTION(gcc_gp5),
1233 MSM_PIN_FUNCTION(hs0_mi2s),
1234 MSM_PIN_FUNCTION(hs1_mi2s),
1235 MSM_PIN_FUNCTION(hs2_mi2s),
1236 MSM_PIN_FUNCTION(ibi_i3c),
1237 MSM_PIN_FUNCTION(jitter_bist),
1238 MSM_PIN_FUNCTION(mdp0_vsync0),
1239 MSM_PIN_FUNCTION(mdp0_vsync1),
1240 MSM_PIN_FUNCTION(mdp0_vsync2),
1241 MSM_PIN_FUNCTION(mdp0_vsync3),
1242 MSM_PIN_FUNCTION(mdp0_vsync4),
1243 MSM_PIN_FUNCTION(mdp0_vsync5),
1244 MSM_PIN_FUNCTION(mdp0_vsync6),
1245 MSM_PIN_FUNCTION(mdp0_vsync7),
1246 MSM_PIN_FUNCTION(mdp0_vsync8),
1247 MSM_PIN_FUNCTION(mdp1_vsync0),
1248 MSM_PIN_FUNCTION(mdp1_vsync1),
1249 MSM_PIN_FUNCTION(mdp1_vsync2),
1250 MSM_PIN_FUNCTION(mdp1_vsync3),
1251 MSM_PIN_FUNCTION(mdp1_vsync4),
1252 MSM_PIN_FUNCTION(mdp1_vsync5),
1253 MSM_PIN_FUNCTION(mdp1_vsync6),
1254 MSM_PIN_FUNCTION(mdp1_vsync7),
1255 MSM_PIN_FUNCTION(mdp1_vsync8),
1256 MSM_PIN_FUNCTION(mdp_vsync),
1257 MSM_PIN_FUNCTION(mi2s1_data0),
1258 MSM_PIN_FUNCTION(mi2s1_data1),
1259 MSM_PIN_FUNCTION(mi2s1_sck),
1260 MSM_PIN_FUNCTION(mi2s1_ws),
1261 MSM_PIN_FUNCTION(mi2s2_data0),
1262 MSM_PIN_FUNCTION(mi2s2_data1),
1263 MSM_PIN_FUNCTION(mi2s2_sck),
1264 MSM_PIN_FUNCTION(mi2s2_ws),
1265 MSM_PIN_FUNCTION(mi2s_mclk0),
1266 MSM_PIN_FUNCTION(mi2s_mclk1),
1267 MSM_PIN_FUNCTION(pcie0_clkreq),
1268 MSM_PIN_FUNCTION(pcie1_clkreq),
1269 MSM_PIN_FUNCTION(phase_flag),
1270 MSM_PIN_FUNCTION(pll_bist),
1271 MSM_PIN_FUNCTION(pll_clk),
1272 MSM_PIN_FUNCTION(prng_rosc0),
1273 MSM_PIN_FUNCTION(prng_rosc1),
1274 MSM_PIN_FUNCTION(prng_rosc2),
1275 MSM_PIN_FUNCTION(prng_rosc3),
1276 MSM_PIN_FUNCTION(qdss_cti),
1277 MSM_PIN_FUNCTION(qdss_gpio),
1278 MSM_PIN_FUNCTION(qup0_se0),
1279 MSM_PIN_FUNCTION(qup0_se1),
1280 MSM_PIN_FUNCTION(qup0_se2),
1281 MSM_PIN_FUNCTION(qup0_se3),
1282 MSM_PIN_FUNCTION(qup0_se4),
1283 MSM_PIN_FUNCTION(qup0_se5),
1284 MSM_PIN_FUNCTION(qup1_se0),
1285 MSM_PIN_FUNCTION(qup1_se1),
1286 MSM_PIN_FUNCTION(qup1_se2),
1287 MSM_PIN_FUNCTION(qup1_se3),
1288 MSM_PIN_FUNCTION(qup1_se4),
1289 MSM_PIN_FUNCTION(qup1_se5),
1290 MSM_PIN_FUNCTION(qup1_se6),
1291 MSM_PIN_FUNCTION(qup2_se0),
1292 MSM_PIN_FUNCTION(qup2_se1),
1293 MSM_PIN_FUNCTION(qup2_se2),
1294 MSM_PIN_FUNCTION(qup2_se3),
1295 MSM_PIN_FUNCTION(qup2_se4),
1296 MSM_PIN_FUNCTION(qup2_se5),
1297 MSM_PIN_FUNCTION(qup2_se6),
1298 MSM_PIN_FUNCTION(qup3_se0),
1299 MSM_PIN_FUNCTION(sail_top),
1300 MSM_PIN_FUNCTION(sailss_emac0),
1301 MSM_PIN_FUNCTION(sailss_ospi),
1302 MSM_PIN_FUNCTION(sgmii_phy),
1303 MSM_PIN_FUNCTION(tb_trig),
1304 MSM_PIN_FUNCTION(tgu_ch0),
1305 MSM_PIN_FUNCTION(tgu_ch1),
1306 MSM_PIN_FUNCTION(tgu_ch2),
1307 MSM_PIN_FUNCTION(tgu_ch3),
1308 MSM_PIN_FUNCTION(tgu_ch4),
1309 MSM_PIN_FUNCTION(tgu_ch5),
1310 MSM_PIN_FUNCTION(tsense_pwm1),
1311 MSM_PIN_FUNCTION(tsense_pwm2),
1312 MSM_PIN_FUNCTION(tsense_pwm3),
1313 MSM_PIN_FUNCTION(tsense_pwm4),
1314 MSM_PIN_FUNCTION(usb2phy_ac),
1315 MSM_PIN_FUNCTION(vsense_trigger),
1316 };
1317
1318 /*
1319 * Every pin is maintained as a single group, and missing or non-existing pin
1320 * would be maintained as dummy group to synchronize pin group index with
1321 * pin descriptor registered with pinctrl core.
1322 * Clients would not be able to request these dummy pin groups.
1323 */
1324 static const struct msm_pingroup sa8775p_groups[] = {
1325 [0] = PINGROUP(0, _, _, _, _, _, _, _, _, _),
1326 [1] = PINGROUP(1, pcie0_clkreq, _, _, _, _, _, _, _, _),
1327 [2] = PINGROUP(2, _, _, _, _, _, _, _, _, _),
1328 [3] = PINGROUP(3, pcie1_clkreq, _, _, _, _, _, _, _, _),
1329 [4] = PINGROUP(4, _, _, _, _, _, _, _, _, _),
1330 [5] = PINGROUP(5, _, _, _, _, _, _, _, _, _),
1331 [6] = PINGROUP(6, emac0_ptp_aux, emac0_ptp_pps, emac1_ptp_aux, emac1_ptp_pps,
1332 _, _, _, _, _),
1333 [7] = PINGROUP(7, sgmii_phy, _, _, _, _, _, _, _, _),
1334 [8] = PINGROUP(8, emac0_mdc, _, _, _, _, _, _, _, _),
1335 [9] = PINGROUP(9, emac0_mdio, _, _, _, _, _, _, _, _),
1336 [10] = PINGROUP(10, usb2phy_ac, emac0_ptp_aux, emac0_ptp_pps, emac1_ptp_aux, emac1_ptp_pps,
1337 _, _, _, _),
1338 [11] = PINGROUP(11, usb2phy_ac, emac0_ptp_aux, emac0_ptp_pps, emac1_ptp_aux, emac1_ptp_pps,
1339 _, _, _, _),
1340 [12] = PINGROUP(12, usb2phy_ac, emac0_ptp_aux, emac0_ptp_pps, emac1_ptp_aux, emac1_ptp_pps,
1341 emac0_mcg0, _, _, _),
1342 [13] = PINGROUP(13, qup3_se0, emac0_mcg1, _, _, sail_top, _, _, _, _),
1343 [14] = PINGROUP(14, qup3_se0, emac0_mcg2, _, _, sail_top, _, _, _, _),
1344 [15] = PINGROUP(15, qup3_se0, emac0_mcg3, _, _, sail_top, _, _, _, _),
1345 [16] = PINGROUP(16, qup3_se0, emac1_mcg0, _, _, sail_top, _, _, _, _),
1346 [17] = PINGROUP(17, qup3_se0, tb_trig, tb_trig, emac1_mcg1, _, _, _, _, _),
1347 [18] = PINGROUP(18, qup3_se0, emac1_mcg2, _, _, sailss_ospi, sailss_emac0, _, _, _),
1348 [19] = PINGROUP(19, qup3_se0, emac1_mcg3, _, _, sailss_ospi, sailss_emac0, _, _, _),
1349 [20] = PINGROUP(20, qup0_se0, emac1_mdc, qdss_gpio, _, _, _, _, _, _),
1350 [21] = PINGROUP(21, qup0_se0, emac1_mdio, qdss_gpio, _, _, _, _, _, _),
1351 [22] = PINGROUP(22, qup0_se0, qdss_gpio, _, _, _, _, _, _, _),
1352 [23] = PINGROUP(23, qup0_se0, qdss_gpio, _, _, _, _, _, _, _),
1353 [24] = PINGROUP(24, qup0_se1, qdss_gpio, _, _, _, _, _, _, _),
1354 [25] = PINGROUP(25, qup0_se1, phase_flag, _, qdss_gpio, _, _, _, _, _),
1355 [26] = PINGROUP(26, sgmii_phy, qup0_se1, qdss_cti, phase_flag, _, _, _, _, _),
1356 [27] = PINGROUP(27, qup0_se1, qdss_cti, phase_flag, _, atest_char, _, _, _, _),
1357 [28] = PINGROUP(28, qup0_se3, phase_flag, _, qdss_gpio, _, _, _, _, _),
1358 [29] = PINGROUP(29, qup0_se3, phase_flag, _, qdss_gpio, _, _, _, _, _),
1359 [30] = PINGROUP(30, qup0_se3, phase_flag, _, qdss_gpio, _, _, _, _, _),
1360 [31] = PINGROUP(31, qup0_se3, phase_flag, _, qdss_gpio, _, _, _, _, _),
1361 [32] = PINGROUP(32, qup0_se4, phase_flag, _, _, _, _, _, _, _),
1362 [33] = PINGROUP(33, qup0_se4, gcc_gp4, _, ddr_pxi0, _, _, _, _, _),
1363 [34] = PINGROUP(34, qup0_se4, gcc_gp5, _, ddr_pxi0, _, _, _, _, _),
1364 [35] = PINGROUP(35, qup0_se4, phase_flag, _, _, _, _, _, _, _),
1365 [36] = PINGROUP(36, qup0_se2, qup0_se5, phase_flag, tgu_ch2, _, _, _, _, _),
1366 [37] = PINGROUP(37, qup0_se2, qup0_se5, phase_flag, tgu_ch3, _, _, _, _, _),
1367 [38] = PINGROUP(38, qup0_se5, qup0_se2, qdss_cti, phase_flag, tgu_ch4, _, _, _, _),
1368 [39] = PINGROUP(39, qup0_se5, qup0_se2, qdss_cti, phase_flag, tgu_ch5, _, _, _, _),
1369 [40] = PINGROUP(40, qup1_se0, qup1_se1, ibi_i3c, mdp1_vsync0, _, _, _, _, _),
1370 [41] = PINGROUP(41, qup1_se0, qup1_se1, ibi_i3c, mdp1_vsync1, _, _, _, _, _),
1371 [42] = PINGROUP(42, qup1_se1, qup1_se0, ibi_i3c, mdp1_vsync2, gcc_gp5, _, _, _, _),
1372 [43] = PINGROUP(43, qup1_se1, qup1_se0, ibi_i3c, mdp1_vsync3, _, _, _, _, _),
1373 [44] = PINGROUP(44, qup1_se2, qup1_se3, edp0_lcd, _, _, _, _, _, _),
1374 [45] = PINGROUP(45, qup1_se2, qup1_se3, edp1_lcd, _, _, _, _, _, _),
1375 [46] = PINGROUP(46, qup1_se3, qup1_se2, mdp1_vsync4, tgu_ch0, _, _, _, _, _),
1376 [47] = PINGROUP(47, qup1_se3, qup1_se2, mdp1_vsync5, tgu_ch1, _, _, _, _, _),
1377 [48] = PINGROUP(48, qup1_se4, qdss_cti, edp2_lcd, _, _, _, _, _, _),
1378 [49] = PINGROUP(49, qup1_se4, qdss_cti, edp3_lcd, _, _, _, _, _, _),
1379 [50] = PINGROUP(50, qup1_se4, cci_async, qdss_cti, mdp1_vsync8, _, _, _, _, _),
1380 [51] = PINGROUP(51, qup1_se4, qdss_cti, mdp1_vsync6, gcc_gp1, _, _, _, _, _),
1381 [52] = PINGROUP(52, qup1_se5, cci_timer4, cci_i2c, mdp1_vsync7, gcc_gp2, _, ddr_pxi1, _, _),
1382 [53] = PINGROUP(53, qup1_se5, cci_timer5, cci_i2c, gcc_gp3, _, ddr_pxi1, _, _, _),
1383 [54] = PINGROUP(54, qup1_se5, cci_timer6, cci_i2c, _, _, _, _, _, _),
1384 [55] = PINGROUP(55, qup1_se5, cci_timer7, cci_i2c, gcc_gp4, _, ddr_pxi2, _, _, _),
1385 [56] = PINGROUP(56, qup1_se6, qup1_se6, cci_timer8, cci_i2c, phase_flag,
1386 ddr_bist, _, _, _),
1387 [57] = PINGROUP(57, qup1_se6, qup1_se6, cci_timer9, cci_i2c, mdp0_vsync0,
1388 phase_flag, ddr_bist, _, _),
1389 [58] = PINGROUP(58, cci_i2c, mdp0_vsync1, ddr_bist, _, atest_usb2, atest_char, _, _, _),
1390 [59] = PINGROUP(59, cci_i2c, mdp0_vsync2, ddr_bist, _, atest_usb2, atest_char, _, _, _),
1391 [60] = PINGROUP(60, cci_i2c, qdss_gpio, _, _, _, _, _, _, _),
1392 [61] = PINGROUP(61, cci_i2c, qdss_gpio, _, _, _, _, _, _, _),
1393 [62] = PINGROUP(62, cci_i2c, qdss_gpio, _, _, _, _, _, _, _),
1394 [63] = PINGROUP(63, cci_i2c, qdss_gpio, _, _, _, _, _, _, _),
1395 [64] = PINGROUP(64, cci_i2c, qdss_gpio, _, _, _, _, _, _, _),
1396 [65] = PINGROUP(65, cci_i2c, qdss_gpio, _, _, _, _, _, _, _),
1397 [66] = PINGROUP(66, cci_i2c, cci_async, qdss_gpio, _, _, _, _, _, _),
1398 [67] = PINGROUP(67, cci_i2c, qdss_gpio, _, _, _, _, _, _, _),
1399 [68] = PINGROUP(68, cci_timer0, cci_async, _, _, _, _, _, _, _),
1400 [69] = PINGROUP(69, cci_timer1, cci_async, _, _, _, _, _, _, _),
1401 [70] = PINGROUP(70, cci_timer2, cci_async, _, _, _, _, _, _, _),
1402 [71] = PINGROUP(71, cci_timer3, cci_async, _, _, _, _, _, _, _),
1403 [72] = PINGROUP(72, cam_mclk, _, _, _, _, _, _, _, _),
1404 [73] = PINGROUP(73, cam_mclk, _, _, _, _, _, _, _, _),
1405 [74] = PINGROUP(74, cam_mclk, _, _, _, _, _, _, _, _),
1406 [75] = PINGROUP(75, cam_mclk, _, _, _, _, _, _, _, _),
1407 [76] = PINGROUP(76, _, _, _, _, _, _, _, _, _),
1408 [77] = PINGROUP(77, _, _, _, _, _, _, _, _, _),
1409 [78] = PINGROUP(78, _, _, _, _, _, _, _, _, _),
1410 [79] = PINGROUP(79, _, _, _, _, _, _, _, _, _),
1411 [80] = PINGROUP(80, qup2_se0, ibi_i3c, mdp0_vsync3, _, _, _, _, _, _),
1412 [81] = PINGROUP(81, qup2_se0, ibi_i3c, mdp0_vsync4, _, _, _, _, _, _),
1413 [82] = PINGROUP(82, qup2_se0, mdp_vsync, gcc_gp1, _, _, _, _, _, _),
1414 [83] = PINGROUP(83, qup2_se0, mdp_vsync, gcc_gp2, _, _, _, _, _, _),
1415 [84] = PINGROUP(84, qup2_se1, qup2_se5, ibi_i3c, mdp_vsync, gcc_gp3, _, _, _, _),
1416 [85] = PINGROUP(85, qup2_se1, qup2_se5, ibi_i3c, _, _, _, _, _, _),
1417 [86] = PINGROUP(86, qup2_se2, jitter_bist, atest_usb2, ddr_pxi2, _, _, _, _, _),
1418 [87] = PINGROUP(87, qup2_se2, pll_clk, atest_usb2, ddr_pxi3, _, _, _, _, _),
1419 [88] = PINGROUP(88, qup2_se2, _, atest_usb2, ddr_pxi3, _, _, _, _, _),
1420 [89] = PINGROUP(89, qup2_se2, _, atest_usb2, ddr_pxi4, atest_char, _, _, _, _),
1421 [90] = PINGROUP(90, qup2_se2, _, atest_usb2, ddr_pxi4, atest_char, _, _, _, _),
1422 [91] = PINGROUP(91, qup2_se3, mdp0_vsync5, _, atest_usb2, _, _, _, _, _),
1423 [92] = PINGROUP(92, qup2_se3, mdp0_vsync6, _, atest_usb2, _, _, _, _, _),
1424 [93] = PINGROUP(93, qup2_se3, mdp0_vsync7, _, atest_usb2, _, _, _, _, _),
1425 [94] = PINGROUP(94, qup2_se3, mdp0_vsync8, _, atest_usb2, _, _, _, _, _),
1426 [95] = PINGROUP(95, qup2_se4, qup2_se6, _, atest_usb2, _, _, _, _, _),
1427 [96] = PINGROUP(96, qup2_se4, qup2_se6, _, atest_usb2, _, _, _, _, _),
1428 [97] = PINGROUP(97, qup2_se6, qup2_se4, cri_trng0, _, atest_usb2, _, _, _, _),
1429 [98] = PINGROUP(98, qup2_se6, qup2_se4, phase_flag, cri_trng1, _, _, _, _, _),
1430 [99] = PINGROUP(99, qup2_se5, qup2_se1, phase_flag, cri_trng, _, _, _, _, _),
1431 [100] = PINGROUP(100, qup2_se5, qup2_se1, _, _, _, _, _, _, _),
1432 [101] = PINGROUP(101, edp0_hot, prng_rosc0, tsense_pwm4, _, _, _, _, _, _),
1433 [102] = PINGROUP(102, edp1_hot, prng_rosc1, tsense_pwm3, _, _, _, _, _, _),
1434 [103] = PINGROUP(103, edp3_hot, prng_rosc2, tsense_pwm2, _, _, _, _, _, _),
1435 [104] = PINGROUP(104, edp2_hot, prng_rosc3, tsense_pwm1, _, _, _, _, _, _),
1436 [105] = PINGROUP(105, mi2s_mclk0, _, qdss_gpio, atest_usb2, _, _, _, _, _),
1437 [106] = PINGROUP(106, mi2s1_sck, phase_flag, _, qdss_gpio, _, _, _, _, _),
1438 [107] = PINGROUP(107, mi2s1_ws, phase_flag, _, qdss_gpio, _, _, _, _, _),
1439 [108] = PINGROUP(108, mi2s1_data0, phase_flag, _, qdss_gpio, _, _, _, _, _),
1440 [109] = PINGROUP(109, mi2s1_data1, phase_flag, _, qdss_gpio, _, _, _, _, _),
1441 [110] = PINGROUP(110, mi2s2_sck, phase_flag, _, qdss_gpio, _, _, _, _, _),
1442 [111] = PINGROUP(111, mi2s2_ws, phase_flag, _, qdss_gpio, vsense_trigger, _, _, _, _),
1443 [112] = PINGROUP(112, mi2s2_data0, phase_flag, _, qdss_gpio, _, _, _, _, _),
1444 [113] = PINGROUP(113, mi2s2_data1, audio_ref, phase_flag, _, qdss_gpio, _, _, _, _),
1445 [114] = PINGROUP(114, hs0_mi2s, pll_bist, phase_flag, _, qdss_gpio, _, _, _, _),
1446 [115] = PINGROUP(115, hs0_mi2s, _, qdss_gpio, _, _, _, _, _, _),
1447 [116] = PINGROUP(116, hs0_mi2s, _, qdss_gpio, _, _, _, _, _, _),
1448 [117] = PINGROUP(117, hs0_mi2s, mi2s_mclk1, _, qdss_gpio, _, _, _, _, _),
1449 [118] = PINGROUP(118, hs1_mi2s, _, qdss_gpio, ddr_pxi5, _, _, _, _, _),
1450 [119] = PINGROUP(119, hs1_mi2s, _, qdss_gpio, ddr_pxi5, _, _, _, _, _),
1451 [120] = PINGROUP(120, hs1_mi2s, phase_flag, _, qdss_gpio, _, _, _, _, _),
1452 [121] = PINGROUP(121, hs1_mi2s, phase_flag, _, qdss_gpio, _, _, _, _, _),
1453 [122] = PINGROUP(122, hs2_mi2s, phase_flag, _, qdss_gpio, _, _, _, _, _),
1454 [123] = PINGROUP(123, hs2_mi2s, phase_flag, _, _, _, _, _, _, _),
1455 [124] = PINGROUP(124, hs2_mi2s, phase_flag, _, _, _, _, _, _, _),
1456 [125] = PINGROUP(125, hs2_mi2s, phase_flag, _, _, _, _, _, _, _),
1457 [126] = PINGROUP(126, _, _, _, _, _, _, _, _, _),
1458 [127] = PINGROUP(127, _, _, _, _, _, _, _, _, _),
1459 [128] = PINGROUP(128, _, _, _, _, _, _, _, _, _),
1460 [129] = PINGROUP(129, _, _, _, _, _, _, _, _, _),
1461 [130] = PINGROUP(130, _, _, _, _, _, _, _, _, _),
1462 [131] = PINGROUP(131, _, _, _, _, _, _, _, _, _),
1463 [132] = PINGROUP(132, _, _, _, _, _, _, _, _, _),
1464 [133] = PINGROUP(133, _, _, _, _, _, _, _, _, _),
1465 [134] = PINGROUP(134, _, _, _, _, _, _, _, _, _),
1466 [135] = PINGROUP(135, _, _, _, _, _, _, _, _, _),
1467 [136] = PINGROUP(136, _, _, _, _, _, _, _, _, _),
1468 [137] = PINGROUP(137, _, _, _, _, _, _, _, _, _),
1469 [138] = PINGROUP(138, _, _, _, _, _, _, _, _, _),
1470 [139] = PINGROUP(139, _, _, _, _, _, _, _, _, _),
1471 [140] = PINGROUP(140, _, _, _, _, _, _, _, _, _),
1472 [141] = PINGROUP(141, _, _, _, _, _, _, _, _, _),
1473 [142] = PINGROUP(142, _, _, _, _, _, _, _, _, _),
1474 [143] = PINGROUP(143, _, _, _, _, _, _, _, _, _),
1475 [144] = PINGROUP(144, dbg_out, _, _, _, _, _, _, _, _),
1476 [145] = PINGROUP(145, _, _, _, _, _, _, _, _, _),
1477 [146] = PINGROUP(146, _, _, _, _, _, _, _, _, _),
1478 [147] = PINGROUP(147, _, _, _, _, _, _, _, _, _),
1479 [148] = PINGROUP(148, _, _, _, _, _, _, _, _, _),
1480 [149] = UFS_RESET(ufs_reset, 0x1a2000),
1481 [150] = SDC_QDSD_PINGROUP(sdc1_rclk, 0x199000, 15, 0),
1482 [151] = SDC_QDSD_PINGROUP(sdc1_clk, 0x199000, 13, 6),
1483 [152] = SDC_QDSD_PINGROUP(sdc1_cmd, 0x199000, 11, 3),
1484 [153] = SDC_QDSD_PINGROUP(sdc1_data, 0x199000, 9, 0),
1485 };
1486
1487 static const struct msm_gpio_wakeirq_map sa8775p_pdc_map[] = {
1488 { 0, 169 }, { 1, 174 }, { 2, 170 }, { 3, 175 }, { 4, 171 }, { 5, 173 },
1489 { 6, 172 }, { 7, 182 }, { 10, 220 }, { 11, 213 }, { 12, 221 },
1490 { 16, 230 }, { 19, 231 }, { 20, 232 }, { 23, 233 }, { 24, 234 },
1491 { 26, 223 }, { 27, 235 }, { 28, 209 }, { 29, 176 }, { 30, 200 },
1492 { 31, 201 }, { 32, 212 }, { 35, 177 }, { 36, 178 }, { 39, 184 },
1493 { 40, 185 }, { 41, 227 }, { 42, 186 }, { 43, 228 }, { 45, 187 },
1494 { 47, 188 }, { 48, 194 }, { 51, 195 }, { 52, 196 }, { 55, 197 },
1495 { 56, 198 }, { 57, 236 }, { 58, 192 }, { 59, 193 }, { 72, 179 },
1496 { 73, 180 }, { 74, 181 }, { 75, 202 }, { 76, 183 }, { 77, 189 },
1497 { 78, 190 }, { 79, 191 }, { 80, 199 }, { 83, 204 }, { 84, 205 },
1498 { 85, 229 }, { 86, 206 }, { 89, 207 }, { 91, 208 }, { 94, 214 },
1499 { 95, 215 }, { 96, 237 }, { 97, 216 }, { 98, 238 }, { 99, 217 },
1500 { 100, 239 }, { 105, 219 }, { 106, 210 }, { 107, 211 }, { 108, 222 },
1501 { 109, 203 }, { 145, 225 }, { 146, 226 },
1502 };
1503
1504 static const struct msm_pinctrl_soc_data sa8775p_pinctrl = {
1505 .pins = sa8775p_pins,
1506 .npins = ARRAY_SIZE(sa8775p_pins),
1507 .functions = sa8775p_functions,
1508 .nfunctions = ARRAY_SIZE(sa8775p_functions),
1509 .groups = sa8775p_groups,
1510 .ngroups = ARRAY_SIZE(sa8775p_groups),
1511 .ngpios = 150,
1512 .wakeirq_map = sa8775p_pdc_map,
1513 .nwakeirq_map = ARRAY_SIZE(sa8775p_pdc_map),
1514 };
1515
sa8775p_pinctrl_probe(struct platform_device * pdev)1516 static int sa8775p_pinctrl_probe(struct platform_device *pdev)
1517 {
1518 return msm_pinctrl_probe(pdev, &sa8775p_pinctrl);
1519 }
1520
1521 static const struct of_device_id sa8775p_pinctrl_of_match[] = {
1522 { .compatible = "qcom,sa8775p-tlmm", },
1523 { },
1524 };
1525 MODULE_DEVICE_TABLE(of, sa8775p_pinctrl_of_match);
1526
1527 static struct platform_driver sa8775p_pinctrl_driver = {
1528 .driver = {
1529 .name = "sa8775p-tlmm",
1530 .of_match_table = sa8775p_pinctrl_of_match,
1531 },
1532 .probe = sa8775p_pinctrl_probe,
1533 .remove = msm_pinctrl_remove,
1534 };
1535
sa8775p_pinctrl_init(void)1536 static int __init sa8775p_pinctrl_init(void)
1537 {
1538 return platform_driver_register(&sa8775p_pinctrl_driver);
1539 }
1540 arch_initcall(sa8775p_pinctrl_init);
1541
sa8775p_pinctrl_exit(void)1542 static void __exit sa8775p_pinctrl_exit(void)
1543 {
1544 platform_driver_unregister(&sa8775p_pinctrl_driver);
1545 }
1546 module_exit(sa8775p_pinctrl_exit);
1547
1548 MODULE_DESCRIPTION("QTI SA8775P pinctrl driver");
1549 MODULE_LICENSE("GPL");
1550