xref: /linux/drivers/gpu/drm/msm/msm_drv.c (revision e70140ba0d2b1a30467d4af6bcfe761327b9ec95)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2016-2018, 2020-2021 The Linux Foundation. All rights reserved.
4  * Copyright (C) 2013 Red Hat
5  * Author: Rob Clark <robdclark@gmail.com>
6  */
7 
8 #include <linux/dma-mapping.h>
9 #include <linux/fault-inject.h>
10 #include <linux/debugfs.h>
11 #include <linux/of_address.h>
12 #include <linux/uaccess.h>
13 
14 #include <drm/drm_client_setup.h>
15 #include <drm/drm_drv.h>
16 #include <drm/drm_file.h>
17 #include <drm/drm_ioctl.h>
18 #include <drm/drm_of.h>
19 
20 #include "msm_drv.h"
21 #include "msm_debugfs.h"
22 #include "msm_gem.h"
23 #include "msm_gpu.h"
24 #include "msm_kms.h"
25 
26 /*
27  * MSM driver version:
28  * - 1.0.0 - initial interface
29  * - 1.1.0 - adds madvise, and support for submits with > 4 cmd buffers
30  * - 1.2.0 - adds explicit fence support for submit ioctl
31  * - 1.3.0 - adds GMEM_BASE + NR_RINGS params, SUBMITQUEUE_NEW +
32  *           SUBMITQUEUE_CLOSE ioctls, and MSM_INFO_IOVA flag for
33  *           MSM_GEM_INFO ioctl.
34  * - 1.4.0 - softpin, MSM_RELOC_BO_DUMP, and GEM_INFO support to set/get
35  *           GEM object's debug name
36  * - 1.5.0 - Add SUBMITQUERY_QUERY ioctl
37  * - 1.6.0 - Syncobj support
38  * - 1.7.0 - Add MSM_PARAM_SUSPENDS to access suspend count
39  * - 1.8.0 - Add MSM_BO_CACHED_COHERENT for supported GPUs (a6xx)
40  * - 1.9.0 - Add MSM_SUBMIT_FENCE_SN_IN
41  * - 1.10.0 - Add MSM_SUBMIT_BO_NO_IMPLICIT
42  * - 1.11.0 - Add wait boost (MSM_WAIT_FENCE_BOOST, MSM_PREP_BOOST)
43  * - 1.12.0 - Add MSM_INFO_SET_METADATA and MSM_INFO_GET_METADATA
44  */
45 #define MSM_VERSION_MAJOR	1
46 #define MSM_VERSION_MINOR	12
47 #define MSM_VERSION_PATCHLEVEL	0
48 
49 static void msm_deinit_vram(struct drm_device *ddev);
50 
51 static char *vram = "16m";
52 MODULE_PARM_DESC(vram, "Configure VRAM size (for devices without IOMMU/GPUMMU)");
53 module_param(vram, charp, 0);
54 
55 bool dumpstate;
56 MODULE_PARM_DESC(dumpstate, "Dump KMS state on errors");
57 module_param(dumpstate, bool, 0600);
58 
59 static bool modeset = true;
60 MODULE_PARM_DESC(modeset, "Use kernel modesetting [KMS] (1=on (default), 0=disable)");
61 module_param(modeset, bool, 0600);
62 
63 DECLARE_FAULT_ATTR(fail_gem_alloc);
64 DECLARE_FAULT_ATTR(fail_gem_iova);
65 
msm_drm_uninit(struct device * dev)66 static int msm_drm_uninit(struct device *dev)
67 {
68 	struct platform_device *pdev = to_platform_device(dev);
69 	struct msm_drm_private *priv = platform_get_drvdata(pdev);
70 	struct drm_device *ddev = priv->dev;
71 
72 	/*
73 	 * Shutdown the hw if we're far enough along where things might be on.
74 	 * If we run this too early, we'll end up panicking in any variety of
75 	 * places. Since we don't register the drm device until late in
76 	 * msm_drm_init, drm_dev->registered is used as an indicator that the
77 	 * shutdown will be successful.
78 	 */
79 	if (ddev->registered) {
80 		drm_dev_unregister(ddev);
81 		if (priv->kms)
82 			drm_atomic_helper_shutdown(ddev);
83 	}
84 
85 	/* We must cancel and cleanup any pending vblank enable/disable
86 	 * work before msm_irq_uninstall() to avoid work re-enabling an
87 	 * irq after uninstall has disabled it.
88 	 */
89 
90 	flush_workqueue(priv->wq);
91 
92 	msm_gem_shrinker_cleanup(ddev);
93 
94 	msm_perf_debugfs_cleanup(priv);
95 	msm_rd_debugfs_cleanup(priv);
96 
97 	if (priv->kms)
98 		msm_drm_kms_uninit(dev);
99 
100 	msm_deinit_vram(ddev);
101 
102 	component_unbind_all(dev, ddev);
103 
104 	ddev->dev_private = NULL;
105 	drm_dev_put(ddev);
106 
107 	destroy_workqueue(priv->wq);
108 
109 	return 0;
110 }
111 
msm_use_mmu(struct drm_device * dev)112 bool msm_use_mmu(struct drm_device *dev)
113 {
114 	struct msm_drm_private *priv = dev->dev_private;
115 
116 	/*
117 	 * a2xx comes with its own MMU
118 	 * On other platforms IOMMU can be declared specified either for the
119 	 * MDP/DPU device or for its parent, MDSS device.
120 	 */
121 	return priv->is_a2xx ||
122 		device_iommu_mapped(dev->dev) ||
123 		device_iommu_mapped(dev->dev->parent);
124 }
125 
msm_init_vram(struct drm_device * dev)126 static int msm_init_vram(struct drm_device *dev)
127 {
128 	struct msm_drm_private *priv = dev->dev_private;
129 	struct device_node *node;
130 	unsigned long size = 0;
131 	int ret = 0;
132 
133 	/* In the device-tree world, we could have a 'memory-region'
134 	 * phandle, which gives us a link to our "vram".  Allocating
135 	 * is all nicely abstracted behind the dma api, but we need
136 	 * to know the entire size to allocate it all in one go. There
137 	 * are two cases:
138 	 *  1) device with no IOMMU, in which case we need exclusive
139 	 *     access to a VRAM carveout big enough for all gpu
140 	 *     buffers
141 	 *  2) device with IOMMU, but where the bootloader puts up
142 	 *     a splash screen.  In this case, the VRAM carveout
143 	 *     need only be large enough for fbdev fb.  But we need
144 	 *     exclusive access to the buffer to avoid the kernel
145 	 *     using those pages for other purposes (which appears
146 	 *     as corruption on screen before we have a chance to
147 	 *     load and do initial modeset)
148 	 */
149 
150 	node = of_parse_phandle(dev->dev->of_node, "memory-region", 0);
151 	if (node) {
152 		struct resource r;
153 		ret = of_address_to_resource(node, 0, &r);
154 		of_node_put(node);
155 		if (ret)
156 			return ret;
157 		size = r.end - r.start + 1;
158 		DRM_INFO("using VRAM carveout: %lx@%pa\n", size, &r.start);
159 
160 		/* if we have no IOMMU, then we need to use carveout allocator.
161 		 * Grab the entire DMA chunk carved out in early startup in
162 		 * mach-msm:
163 		 */
164 	} else if (!msm_use_mmu(dev)) {
165 		DRM_INFO("using %s VRAM carveout\n", vram);
166 		size = memparse(vram, NULL);
167 	}
168 
169 	if (size) {
170 		unsigned long attrs = 0;
171 		void *p;
172 
173 		priv->vram.size = size;
174 
175 		drm_mm_init(&priv->vram.mm, 0, (size >> PAGE_SHIFT) - 1);
176 		spin_lock_init(&priv->vram.lock);
177 
178 		attrs |= DMA_ATTR_NO_KERNEL_MAPPING;
179 		attrs |= DMA_ATTR_WRITE_COMBINE;
180 
181 		/* note that for no-kernel-mapping, the vaddr returned
182 		 * is bogus, but non-null if allocation succeeded:
183 		 */
184 		p = dma_alloc_attrs(dev->dev, size,
185 				&priv->vram.paddr, GFP_KERNEL, attrs);
186 		if (!p) {
187 			DRM_DEV_ERROR(dev->dev, "failed to allocate VRAM\n");
188 			priv->vram.paddr = 0;
189 			return -ENOMEM;
190 		}
191 
192 		DRM_DEV_INFO(dev->dev, "VRAM: %08x->%08x\n",
193 				(uint32_t)priv->vram.paddr,
194 				(uint32_t)(priv->vram.paddr + size));
195 	}
196 
197 	return ret;
198 }
199 
msm_deinit_vram(struct drm_device * ddev)200 static void msm_deinit_vram(struct drm_device *ddev)
201 {
202 	struct msm_drm_private *priv = ddev->dev_private;
203 	unsigned long attrs = DMA_ATTR_NO_KERNEL_MAPPING;
204 
205 	if (!priv->vram.paddr)
206 		return;
207 
208 	drm_mm_takedown(&priv->vram.mm);
209 	dma_free_attrs(ddev->dev, priv->vram.size, NULL, priv->vram.paddr,
210 			attrs);
211 }
212 
msm_drm_init(struct device * dev,const struct drm_driver * drv)213 static int msm_drm_init(struct device *dev, const struct drm_driver *drv)
214 {
215 	struct msm_drm_private *priv = dev_get_drvdata(dev);
216 	struct drm_device *ddev;
217 	int ret;
218 
219 	if (drm_firmware_drivers_only())
220 		return -ENODEV;
221 
222 	ddev = drm_dev_alloc(drv, dev);
223 	if (IS_ERR(ddev)) {
224 		DRM_DEV_ERROR(dev, "failed to allocate drm_device\n");
225 		return PTR_ERR(ddev);
226 	}
227 	ddev->dev_private = priv;
228 	priv->dev = ddev;
229 
230 	priv->wq = alloc_ordered_workqueue("msm", 0);
231 	if (!priv->wq) {
232 		ret = -ENOMEM;
233 		goto err_put_dev;
234 	}
235 
236 	INIT_LIST_HEAD(&priv->objects);
237 	mutex_init(&priv->obj_lock);
238 
239 	/*
240 	 * Initialize the LRUs:
241 	 */
242 	mutex_init(&priv->lru.lock);
243 	drm_gem_lru_init(&priv->lru.unbacked, &priv->lru.lock);
244 	drm_gem_lru_init(&priv->lru.pinned,   &priv->lru.lock);
245 	drm_gem_lru_init(&priv->lru.willneed, &priv->lru.lock);
246 	drm_gem_lru_init(&priv->lru.dontneed, &priv->lru.lock);
247 
248 	/* Teach lockdep about lock ordering wrt. shrinker: */
249 	fs_reclaim_acquire(GFP_KERNEL);
250 	might_lock(&priv->lru.lock);
251 	fs_reclaim_release(GFP_KERNEL);
252 
253 	if (priv->kms_init) {
254 		ret = drmm_mode_config_init(ddev);
255 		if (ret)
256 			goto err_destroy_wq;
257 	}
258 
259 	ret = msm_init_vram(ddev);
260 	if (ret)
261 		goto err_destroy_wq;
262 
263 	dma_set_max_seg_size(dev, UINT_MAX);
264 
265 	/* Bind all our sub-components: */
266 	ret = component_bind_all(dev, ddev);
267 	if (ret)
268 		goto err_deinit_vram;
269 
270 	ret = msm_gem_shrinker_init(ddev);
271 	if (ret)
272 		goto err_msm_uninit;
273 
274 	if (priv->kms_init) {
275 		ret = msm_drm_kms_init(dev, drv);
276 		if (ret)
277 			goto err_msm_uninit;
278 	} else {
279 		/* valid only for the dummy headless case, where of_node=NULL */
280 		WARN_ON(dev->of_node);
281 		ddev->driver_features &= ~DRIVER_MODESET;
282 		ddev->driver_features &= ~DRIVER_ATOMIC;
283 	}
284 
285 	ret = drm_dev_register(ddev, 0);
286 	if (ret)
287 		goto err_msm_uninit;
288 
289 	ret = msm_debugfs_late_init(ddev);
290 	if (ret)
291 		goto err_msm_uninit;
292 
293 	if (priv->kms_init) {
294 		drm_kms_helper_poll_init(ddev);
295 		drm_client_setup(ddev, NULL);
296 	}
297 
298 	return 0;
299 
300 err_msm_uninit:
301 	msm_drm_uninit(dev);
302 
303 	return ret;
304 
305 err_deinit_vram:
306 	msm_deinit_vram(ddev);
307 err_destroy_wq:
308 	destroy_workqueue(priv->wq);
309 err_put_dev:
310 	drm_dev_put(ddev);
311 
312 	return ret;
313 }
314 
315 /*
316  * DRM operations:
317  */
318 
load_gpu(struct drm_device * dev)319 static void load_gpu(struct drm_device *dev)
320 {
321 	static DEFINE_MUTEX(init_lock);
322 	struct msm_drm_private *priv = dev->dev_private;
323 
324 	mutex_lock(&init_lock);
325 
326 	if (!priv->gpu)
327 		priv->gpu = adreno_load_gpu(dev);
328 
329 	mutex_unlock(&init_lock);
330 }
331 
context_init(struct drm_device * dev,struct drm_file * file)332 static int context_init(struct drm_device *dev, struct drm_file *file)
333 {
334 	static atomic_t ident = ATOMIC_INIT(0);
335 	struct msm_drm_private *priv = dev->dev_private;
336 	struct msm_file_private *ctx;
337 
338 	ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
339 	if (!ctx)
340 		return -ENOMEM;
341 
342 	INIT_LIST_HEAD(&ctx->submitqueues);
343 	rwlock_init(&ctx->queuelock);
344 
345 	kref_init(&ctx->ref);
346 	msm_submitqueue_init(dev, ctx);
347 
348 	ctx->aspace = msm_gpu_create_private_address_space(priv->gpu, current);
349 	file->driver_priv = ctx;
350 
351 	ctx->seqno = atomic_inc_return(&ident);
352 
353 	return 0;
354 }
355 
msm_open(struct drm_device * dev,struct drm_file * file)356 static int msm_open(struct drm_device *dev, struct drm_file *file)
357 {
358 	/* For now, load gpu on open.. to avoid the requirement of having
359 	 * firmware in the initrd.
360 	 */
361 	load_gpu(dev);
362 
363 	return context_init(dev, file);
364 }
365 
context_close(struct msm_file_private * ctx)366 static void context_close(struct msm_file_private *ctx)
367 {
368 	msm_submitqueue_close(ctx);
369 	msm_file_private_put(ctx);
370 }
371 
msm_postclose(struct drm_device * dev,struct drm_file * file)372 static void msm_postclose(struct drm_device *dev, struct drm_file *file)
373 {
374 	struct msm_drm_private *priv = dev->dev_private;
375 	struct msm_file_private *ctx = file->driver_priv;
376 
377 	/*
378 	 * It is not possible to set sysprof param to non-zero if gpu
379 	 * is not initialized:
380 	 */
381 	if (priv->gpu)
382 		msm_file_private_set_sysprof(ctx, priv->gpu, 0);
383 
384 	context_close(ctx);
385 }
386 
387 /*
388  * DRM ioctls:
389  */
390 
msm_ioctl_get_param(struct drm_device * dev,void * data,struct drm_file * file)391 static int msm_ioctl_get_param(struct drm_device *dev, void *data,
392 		struct drm_file *file)
393 {
394 	struct msm_drm_private *priv = dev->dev_private;
395 	struct drm_msm_param *args = data;
396 	struct msm_gpu *gpu;
397 
398 	/* for now, we just have 3d pipe.. eventually this would need to
399 	 * be more clever to dispatch to appropriate gpu module:
400 	 */
401 	if ((args->pipe != MSM_PIPE_3D0) || (args->pad != 0))
402 		return -EINVAL;
403 
404 	gpu = priv->gpu;
405 
406 	if (!gpu)
407 		return -ENXIO;
408 
409 	return gpu->funcs->get_param(gpu, file->driver_priv,
410 				     args->param, &args->value, &args->len);
411 }
412 
msm_ioctl_set_param(struct drm_device * dev,void * data,struct drm_file * file)413 static int msm_ioctl_set_param(struct drm_device *dev, void *data,
414 		struct drm_file *file)
415 {
416 	struct msm_drm_private *priv = dev->dev_private;
417 	struct drm_msm_param *args = data;
418 	struct msm_gpu *gpu;
419 
420 	if ((args->pipe != MSM_PIPE_3D0) || (args->pad != 0))
421 		return -EINVAL;
422 
423 	gpu = priv->gpu;
424 
425 	if (!gpu)
426 		return -ENXIO;
427 
428 	return gpu->funcs->set_param(gpu, file->driver_priv,
429 				     args->param, args->value, args->len);
430 }
431 
msm_ioctl_gem_new(struct drm_device * dev,void * data,struct drm_file * file)432 static int msm_ioctl_gem_new(struct drm_device *dev, void *data,
433 		struct drm_file *file)
434 {
435 	struct drm_msm_gem_new *args = data;
436 	uint32_t flags = args->flags;
437 
438 	if (args->flags & ~MSM_BO_FLAGS) {
439 		DRM_ERROR("invalid flags: %08x\n", args->flags);
440 		return -EINVAL;
441 	}
442 
443 	/*
444 	 * Uncached CPU mappings are deprecated, as of:
445 	 *
446 	 * 9ef364432db4 ("drm/msm: deprecate MSM_BO_UNCACHED (map as writecombine instead)")
447 	 *
448 	 * So promote them to WC.
449 	 */
450 	if (flags & MSM_BO_UNCACHED) {
451 		flags &= ~MSM_BO_CACHED;
452 		flags |= MSM_BO_WC;
453 	}
454 
455 	if (should_fail(&fail_gem_alloc, args->size))
456 		return -ENOMEM;
457 
458 	return msm_gem_new_handle(dev, file, args->size,
459 			args->flags, &args->handle, NULL);
460 }
461 
to_ktime(struct drm_msm_timespec timeout)462 static inline ktime_t to_ktime(struct drm_msm_timespec timeout)
463 {
464 	return ktime_set(timeout.tv_sec, timeout.tv_nsec);
465 }
466 
msm_ioctl_gem_cpu_prep(struct drm_device * dev,void * data,struct drm_file * file)467 static int msm_ioctl_gem_cpu_prep(struct drm_device *dev, void *data,
468 		struct drm_file *file)
469 {
470 	struct drm_msm_gem_cpu_prep *args = data;
471 	struct drm_gem_object *obj;
472 	ktime_t timeout = to_ktime(args->timeout);
473 	int ret;
474 
475 	if (args->op & ~MSM_PREP_FLAGS) {
476 		DRM_ERROR("invalid op: %08x\n", args->op);
477 		return -EINVAL;
478 	}
479 
480 	obj = drm_gem_object_lookup(file, args->handle);
481 	if (!obj)
482 		return -ENOENT;
483 
484 	ret = msm_gem_cpu_prep(obj, args->op, &timeout);
485 
486 	drm_gem_object_put(obj);
487 
488 	return ret;
489 }
490 
msm_ioctl_gem_cpu_fini(struct drm_device * dev,void * data,struct drm_file * file)491 static int msm_ioctl_gem_cpu_fini(struct drm_device *dev, void *data,
492 		struct drm_file *file)
493 {
494 	struct drm_msm_gem_cpu_fini *args = data;
495 	struct drm_gem_object *obj;
496 	int ret;
497 
498 	obj = drm_gem_object_lookup(file, args->handle);
499 	if (!obj)
500 		return -ENOENT;
501 
502 	ret = msm_gem_cpu_fini(obj);
503 
504 	drm_gem_object_put(obj);
505 
506 	return ret;
507 }
508 
msm_ioctl_gem_info_iova(struct drm_device * dev,struct drm_file * file,struct drm_gem_object * obj,uint64_t * iova)509 static int msm_ioctl_gem_info_iova(struct drm_device *dev,
510 		struct drm_file *file, struct drm_gem_object *obj,
511 		uint64_t *iova)
512 {
513 	struct msm_drm_private *priv = dev->dev_private;
514 	struct msm_file_private *ctx = file->driver_priv;
515 
516 	if (!priv->gpu)
517 		return -EINVAL;
518 
519 	if (should_fail(&fail_gem_iova, obj->size))
520 		return -ENOMEM;
521 
522 	/*
523 	 * Don't pin the memory here - just get an address so that userspace can
524 	 * be productive
525 	 */
526 	return msm_gem_get_iova(obj, ctx->aspace, iova);
527 }
528 
msm_ioctl_gem_info_set_iova(struct drm_device * dev,struct drm_file * file,struct drm_gem_object * obj,uint64_t iova)529 static int msm_ioctl_gem_info_set_iova(struct drm_device *dev,
530 		struct drm_file *file, struct drm_gem_object *obj,
531 		uint64_t iova)
532 {
533 	struct msm_drm_private *priv = dev->dev_private;
534 	struct msm_file_private *ctx = file->driver_priv;
535 
536 	if (!priv->gpu)
537 		return -EINVAL;
538 
539 	/* Only supported if per-process address space is supported: */
540 	if (priv->gpu->aspace == ctx->aspace)
541 		return -EOPNOTSUPP;
542 
543 	if (should_fail(&fail_gem_iova, obj->size))
544 		return -ENOMEM;
545 
546 	return msm_gem_set_iova(obj, ctx->aspace, iova);
547 }
548 
msm_ioctl_gem_info_set_metadata(struct drm_gem_object * obj,__user void * metadata,u32 metadata_size)549 static int msm_ioctl_gem_info_set_metadata(struct drm_gem_object *obj,
550 					   __user void *metadata,
551 					   u32 metadata_size)
552 {
553 	struct msm_gem_object *msm_obj = to_msm_bo(obj);
554 	void *buf;
555 	int ret;
556 
557 	/* Impose a moderate upper bound on metadata size: */
558 	if (metadata_size > 128) {
559 		return -EOVERFLOW;
560 	}
561 
562 	/* Use a temporary buf to keep copy_from_user() outside of gem obj lock: */
563 	buf = memdup_user(metadata, metadata_size);
564 	if (IS_ERR(buf))
565 		return PTR_ERR(buf);
566 
567 	ret = msm_gem_lock_interruptible(obj);
568 	if (ret)
569 		goto out;
570 
571 	msm_obj->metadata =
572 		krealloc(msm_obj->metadata, metadata_size, GFP_KERNEL);
573 	msm_obj->metadata_size = metadata_size;
574 	memcpy(msm_obj->metadata, buf, metadata_size);
575 
576 	msm_gem_unlock(obj);
577 
578 out:
579 	kfree(buf);
580 
581 	return ret;
582 }
583 
msm_ioctl_gem_info_get_metadata(struct drm_gem_object * obj,__user void * metadata,u32 * metadata_size)584 static int msm_ioctl_gem_info_get_metadata(struct drm_gem_object *obj,
585 					   __user void *metadata,
586 					   u32 *metadata_size)
587 {
588 	struct msm_gem_object *msm_obj = to_msm_bo(obj);
589 	void *buf;
590 	int ret, len;
591 
592 	if (!metadata) {
593 		/*
594 		 * Querying the size is inherently racey, but
595 		 * EXT_external_objects expects the app to confirm
596 		 * via device and driver UUIDs that the exporter and
597 		 * importer versions match.  All we can do from the
598 		 * kernel side is check the length under obj lock
599 		 * when userspace tries to retrieve the metadata
600 		 */
601 		*metadata_size = msm_obj->metadata_size;
602 		return 0;
603 	}
604 
605 	ret = msm_gem_lock_interruptible(obj);
606 	if (ret)
607 		return ret;
608 
609 	/* Avoid copy_to_user() under gem obj lock: */
610 	len = msm_obj->metadata_size;
611 	buf = kmemdup(msm_obj->metadata, len, GFP_KERNEL);
612 
613 	msm_gem_unlock(obj);
614 
615 	if (*metadata_size < len) {
616 		ret = -ETOOSMALL;
617 	} else if (copy_to_user(metadata, buf, len)) {
618 		ret = -EFAULT;
619 	} else {
620 		*metadata_size = len;
621 	}
622 
623 	kfree(buf);
624 
625 	return 0;
626 }
627 
msm_ioctl_gem_info(struct drm_device * dev,void * data,struct drm_file * file)628 static int msm_ioctl_gem_info(struct drm_device *dev, void *data,
629 		struct drm_file *file)
630 {
631 	struct drm_msm_gem_info *args = data;
632 	struct drm_gem_object *obj;
633 	struct msm_gem_object *msm_obj;
634 	int i, ret = 0;
635 
636 	if (args->pad)
637 		return -EINVAL;
638 
639 	switch (args->info) {
640 	case MSM_INFO_GET_OFFSET:
641 	case MSM_INFO_GET_IOVA:
642 	case MSM_INFO_SET_IOVA:
643 	case MSM_INFO_GET_FLAGS:
644 		/* value returned as immediate, not pointer, so len==0: */
645 		if (args->len)
646 			return -EINVAL;
647 		break;
648 	case MSM_INFO_SET_NAME:
649 	case MSM_INFO_GET_NAME:
650 	case MSM_INFO_SET_METADATA:
651 	case MSM_INFO_GET_METADATA:
652 		break;
653 	default:
654 		return -EINVAL;
655 	}
656 
657 	obj = drm_gem_object_lookup(file, args->handle);
658 	if (!obj)
659 		return -ENOENT;
660 
661 	msm_obj = to_msm_bo(obj);
662 
663 	switch (args->info) {
664 	case MSM_INFO_GET_OFFSET:
665 		args->value = msm_gem_mmap_offset(obj);
666 		break;
667 	case MSM_INFO_GET_IOVA:
668 		ret = msm_ioctl_gem_info_iova(dev, file, obj, &args->value);
669 		break;
670 	case MSM_INFO_SET_IOVA:
671 		ret = msm_ioctl_gem_info_set_iova(dev, file, obj, args->value);
672 		break;
673 	case MSM_INFO_GET_FLAGS:
674 		if (obj->import_attach) {
675 			ret = -EINVAL;
676 			break;
677 		}
678 		/* Hide internal kernel-only flags: */
679 		args->value = to_msm_bo(obj)->flags & MSM_BO_FLAGS;
680 		ret = 0;
681 		break;
682 	case MSM_INFO_SET_NAME:
683 		/* length check should leave room for terminating null: */
684 		if (args->len >= sizeof(msm_obj->name)) {
685 			ret = -EINVAL;
686 			break;
687 		}
688 		if (copy_from_user(msm_obj->name, u64_to_user_ptr(args->value),
689 				   args->len)) {
690 			msm_obj->name[0] = '\0';
691 			ret = -EFAULT;
692 			break;
693 		}
694 		msm_obj->name[args->len] = '\0';
695 		for (i = 0; i < args->len; i++) {
696 			if (!isprint(msm_obj->name[i])) {
697 				msm_obj->name[i] = '\0';
698 				break;
699 			}
700 		}
701 		break;
702 	case MSM_INFO_GET_NAME:
703 		if (args->value && (args->len < strlen(msm_obj->name))) {
704 			ret = -ETOOSMALL;
705 			break;
706 		}
707 		args->len = strlen(msm_obj->name);
708 		if (args->value) {
709 			if (copy_to_user(u64_to_user_ptr(args->value),
710 					 msm_obj->name, args->len))
711 				ret = -EFAULT;
712 		}
713 		break;
714 	case MSM_INFO_SET_METADATA:
715 		ret = msm_ioctl_gem_info_set_metadata(
716 			obj, u64_to_user_ptr(args->value), args->len);
717 		break;
718 	case MSM_INFO_GET_METADATA:
719 		ret = msm_ioctl_gem_info_get_metadata(
720 			obj, u64_to_user_ptr(args->value), &args->len);
721 		break;
722 	}
723 
724 	drm_gem_object_put(obj);
725 
726 	return ret;
727 }
728 
wait_fence(struct msm_gpu_submitqueue * queue,uint32_t fence_id,ktime_t timeout,uint32_t flags)729 static int wait_fence(struct msm_gpu_submitqueue *queue, uint32_t fence_id,
730 		      ktime_t timeout, uint32_t flags)
731 {
732 	struct dma_fence *fence;
733 	int ret;
734 
735 	if (fence_after(fence_id, queue->last_fence)) {
736 		DRM_ERROR_RATELIMITED("waiting on invalid fence: %u (of %u)\n",
737 				      fence_id, queue->last_fence);
738 		return -EINVAL;
739 	}
740 
741 	/*
742 	 * Map submitqueue scoped "seqno" (which is actually an idr key)
743 	 * back to underlying dma-fence
744 	 *
745 	 * The fence is removed from the fence_idr when the submit is
746 	 * retired, so if the fence is not found it means there is nothing
747 	 * to wait for
748 	 */
749 	spin_lock(&queue->idr_lock);
750 	fence = idr_find(&queue->fence_idr, fence_id);
751 	if (fence)
752 		fence = dma_fence_get_rcu(fence);
753 	spin_unlock(&queue->idr_lock);
754 
755 	if (!fence)
756 		return 0;
757 
758 	if (flags & MSM_WAIT_FENCE_BOOST)
759 		dma_fence_set_deadline(fence, ktime_get());
760 
761 	ret = dma_fence_wait_timeout(fence, true, timeout_to_jiffies(&timeout));
762 	if (ret == 0) {
763 		ret = -ETIMEDOUT;
764 	} else if (ret != -ERESTARTSYS) {
765 		ret = 0;
766 	}
767 
768 	dma_fence_put(fence);
769 
770 	return ret;
771 }
772 
msm_ioctl_wait_fence(struct drm_device * dev,void * data,struct drm_file * file)773 static int msm_ioctl_wait_fence(struct drm_device *dev, void *data,
774 		struct drm_file *file)
775 {
776 	struct msm_drm_private *priv = dev->dev_private;
777 	struct drm_msm_wait_fence *args = data;
778 	struct msm_gpu_submitqueue *queue;
779 	int ret;
780 
781 	if (args->flags & ~MSM_WAIT_FENCE_FLAGS) {
782 		DRM_ERROR("invalid flags: %08x\n", args->flags);
783 		return -EINVAL;
784 	}
785 
786 	if (!priv->gpu)
787 		return 0;
788 
789 	queue = msm_submitqueue_get(file->driver_priv, args->queueid);
790 	if (!queue)
791 		return -ENOENT;
792 
793 	ret = wait_fence(queue, args->fence, to_ktime(args->timeout), args->flags);
794 
795 	msm_submitqueue_put(queue);
796 
797 	return ret;
798 }
799 
msm_ioctl_gem_madvise(struct drm_device * dev,void * data,struct drm_file * file)800 static int msm_ioctl_gem_madvise(struct drm_device *dev, void *data,
801 		struct drm_file *file)
802 {
803 	struct drm_msm_gem_madvise *args = data;
804 	struct drm_gem_object *obj;
805 	int ret;
806 
807 	switch (args->madv) {
808 	case MSM_MADV_DONTNEED:
809 	case MSM_MADV_WILLNEED:
810 		break;
811 	default:
812 		return -EINVAL;
813 	}
814 
815 	obj = drm_gem_object_lookup(file, args->handle);
816 	if (!obj) {
817 		return -ENOENT;
818 	}
819 
820 	ret = msm_gem_madvise(obj, args->madv);
821 	if (ret >= 0) {
822 		args->retained = ret;
823 		ret = 0;
824 	}
825 
826 	drm_gem_object_put(obj);
827 
828 	return ret;
829 }
830 
831 
msm_ioctl_submitqueue_new(struct drm_device * dev,void * data,struct drm_file * file)832 static int msm_ioctl_submitqueue_new(struct drm_device *dev, void *data,
833 		struct drm_file *file)
834 {
835 	struct drm_msm_submitqueue *args = data;
836 
837 	if (args->flags & ~MSM_SUBMITQUEUE_FLAGS)
838 		return -EINVAL;
839 
840 	return msm_submitqueue_create(dev, file->driver_priv, args->prio,
841 		args->flags, &args->id);
842 }
843 
msm_ioctl_submitqueue_query(struct drm_device * dev,void * data,struct drm_file * file)844 static int msm_ioctl_submitqueue_query(struct drm_device *dev, void *data,
845 		struct drm_file *file)
846 {
847 	return msm_submitqueue_query(dev, file->driver_priv, data);
848 }
849 
msm_ioctl_submitqueue_close(struct drm_device * dev,void * data,struct drm_file * file)850 static int msm_ioctl_submitqueue_close(struct drm_device *dev, void *data,
851 		struct drm_file *file)
852 {
853 	u32 id = *(u32 *) data;
854 
855 	return msm_submitqueue_remove(file->driver_priv, id);
856 }
857 
858 static const struct drm_ioctl_desc msm_ioctls[] = {
859 	DRM_IOCTL_DEF_DRV(MSM_GET_PARAM,    msm_ioctl_get_param,    DRM_RENDER_ALLOW),
860 	DRM_IOCTL_DEF_DRV(MSM_SET_PARAM,    msm_ioctl_set_param,    DRM_RENDER_ALLOW),
861 	DRM_IOCTL_DEF_DRV(MSM_GEM_NEW,      msm_ioctl_gem_new,      DRM_RENDER_ALLOW),
862 	DRM_IOCTL_DEF_DRV(MSM_GEM_INFO,     msm_ioctl_gem_info,     DRM_RENDER_ALLOW),
863 	DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_PREP, msm_ioctl_gem_cpu_prep, DRM_RENDER_ALLOW),
864 	DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_FINI, msm_ioctl_gem_cpu_fini, DRM_RENDER_ALLOW),
865 	DRM_IOCTL_DEF_DRV(MSM_GEM_SUBMIT,   msm_ioctl_gem_submit,   DRM_RENDER_ALLOW),
866 	DRM_IOCTL_DEF_DRV(MSM_WAIT_FENCE,   msm_ioctl_wait_fence,   DRM_RENDER_ALLOW),
867 	DRM_IOCTL_DEF_DRV(MSM_GEM_MADVISE,  msm_ioctl_gem_madvise,  DRM_RENDER_ALLOW),
868 	DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_NEW,   msm_ioctl_submitqueue_new,   DRM_RENDER_ALLOW),
869 	DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_CLOSE, msm_ioctl_submitqueue_close, DRM_RENDER_ALLOW),
870 	DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_QUERY, msm_ioctl_submitqueue_query, DRM_RENDER_ALLOW),
871 };
872 
msm_show_fdinfo(struct drm_printer * p,struct drm_file * file)873 static void msm_show_fdinfo(struct drm_printer *p, struct drm_file *file)
874 {
875 	struct drm_device *dev = file->minor->dev;
876 	struct msm_drm_private *priv = dev->dev_private;
877 
878 	if (!priv->gpu)
879 		return;
880 
881 	msm_gpu_show_fdinfo(priv->gpu, file->driver_priv, p);
882 
883 	drm_show_memory_stats(p, file);
884 }
885 
886 static const struct file_operations fops = {
887 	.owner = THIS_MODULE,
888 	DRM_GEM_FOPS,
889 	.show_fdinfo = drm_show_fdinfo,
890 };
891 
892 static const struct drm_driver msm_driver = {
893 	.driver_features    = DRIVER_GEM |
894 				DRIVER_RENDER |
895 				DRIVER_ATOMIC |
896 				DRIVER_MODESET |
897 				DRIVER_SYNCOBJ,
898 	.open               = msm_open,
899 	.postclose          = msm_postclose,
900 	.dumb_create        = msm_gem_dumb_create,
901 	.dumb_map_offset    = msm_gem_dumb_map_offset,
902 	.gem_prime_import_sg_table = msm_gem_prime_import_sg_table,
903 #ifdef CONFIG_DEBUG_FS
904 	.debugfs_init       = msm_debugfs_init,
905 #endif
906 	MSM_FBDEV_DRIVER_OPS,
907 	.show_fdinfo        = msm_show_fdinfo,
908 	.ioctls             = msm_ioctls,
909 	.num_ioctls         = ARRAY_SIZE(msm_ioctls),
910 	.fops               = &fops,
911 	.name               = "msm",
912 	.desc               = "MSM Snapdragon DRM",
913 	.date               = "20130625",
914 	.major              = MSM_VERSION_MAJOR,
915 	.minor              = MSM_VERSION_MINOR,
916 	.patchlevel         = MSM_VERSION_PATCHLEVEL,
917 };
918 
919 /*
920  * Componentized driver support:
921  */
922 
923 /*
924  * Identify what components need to be added by parsing what remote-endpoints
925  * our MDP output ports are connected to. In the case of LVDS on MDP4, there
926  * is no external component that we need to add since LVDS is within MDP4
927  * itself.
928  */
add_components_mdp(struct device * master_dev,struct component_match ** matchptr)929 static int add_components_mdp(struct device *master_dev,
930 			      struct component_match **matchptr)
931 {
932 	struct device_node *np = master_dev->of_node;
933 	struct device_node *ep_node;
934 
935 	for_each_endpoint_of_node(np, ep_node) {
936 		struct device_node *intf;
937 		struct of_endpoint ep;
938 		int ret;
939 
940 		ret = of_graph_parse_endpoint(ep_node, &ep);
941 		if (ret) {
942 			DRM_DEV_ERROR(master_dev, "unable to parse port endpoint\n");
943 			of_node_put(ep_node);
944 			return ret;
945 		}
946 
947 		/*
948 		 * The LCDC/LVDS port on MDP4 is a speacial case where the
949 		 * remote-endpoint isn't a component that we need to add
950 		 */
951 		if (of_device_is_compatible(np, "qcom,mdp4") &&
952 		    ep.port == 0)
953 			continue;
954 
955 		/*
956 		 * It's okay if some of the ports don't have a remote endpoint
957 		 * specified. It just means that the port isn't connected to
958 		 * any external interface.
959 		 */
960 		intf = of_graph_get_remote_port_parent(ep_node);
961 		if (!intf)
962 			continue;
963 
964 		if (of_device_is_available(intf))
965 			drm_of_component_match_add(master_dev, matchptr,
966 						   component_compare_of, intf);
967 
968 		of_node_put(intf);
969 	}
970 
971 	return 0;
972 }
973 
974 #if !IS_REACHABLE(CONFIG_DRM_MSM_MDP5) || !IS_REACHABLE(CONFIG_DRM_MSM_DPU)
msm_disp_drv_should_bind(struct device * dev,bool dpu_driver)975 bool msm_disp_drv_should_bind(struct device *dev, bool dpu_driver)
976 {
977 	/* If just a single driver is enabled, use it no matter what */
978 	return true;
979 }
980 #else
981 
982 static bool prefer_mdp5 = true;
983 MODULE_PARM_DESC(prefer_mdp5, "Select whether MDP5 or DPU driver should be preferred");
984 module_param(prefer_mdp5, bool, 0444);
985 
986 /* list all platforms supported by both mdp5 and dpu drivers */
987 static const char *const msm_mdp5_dpu_migration[] = {
988 	"qcom,msm8917-mdp5",
989 	"qcom,msm8937-mdp5",
990 	"qcom,msm8953-mdp5",
991 	"qcom,msm8996-mdp5",
992 	"qcom,sdm630-mdp5",
993 	"qcom,sdm660-mdp5",
994 	NULL,
995 };
996 
msm_disp_drv_should_bind(struct device * dev,bool dpu_driver)997 bool msm_disp_drv_should_bind(struct device *dev, bool dpu_driver)
998 {
999 	/* If it is not an MDP5 device, do not try MDP5 driver */
1000 	if (!of_device_is_compatible(dev->of_node, "qcom,mdp5"))
1001 		return dpu_driver;
1002 
1003 	/* If it is not in the migration list, use MDP5 */
1004 	if (!of_device_compatible_match(dev->of_node, msm_mdp5_dpu_migration))
1005 		return !dpu_driver;
1006 
1007 	return prefer_mdp5 ? !dpu_driver : dpu_driver;
1008 }
1009 #endif
1010 
1011 /*
1012  * We don't know what's the best binding to link the gpu with the drm device.
1013  * Fow now, we just hunt for all the possible gpus that we support, and add them
1014  * as components.
1015  */
1016 static const struct of_device_id msm_gpu_match[] = {
1017 	{ .compatible = "qcom,adreno" },
1018 	{ .compatible = "qcom,adreno-3xx" },
1019 	{ .compatible = "amd,imageon" },
1020 	{ .compatible = "qcom,kgsl-3d0" },
1021 	{ },
1022 };
1023 
add_gpu_components(struct device * dev,struct component_match ** matchptr)1024 static int add_gpu_components(struct device *dev,
1025 			      struct component_match **matchptr)
1026 {
1027 	struct device_node *np;
1028 
1029 	np = of_find_matching_node(NULL, msm_gpu_match);
1030 	if (!np)
1031 		return 0;
1032 
1033 	if (of_device_is_available(np))
1034 		drm_of_component_match_add(dev, matchptr, component_compare_of, np);
1035 
1036 	of_node_put(np);
1037 
1038 	return 0;
1039 }
1040 
msm_drm_bind(struct device * dev)1041 static int msm_drm_bind(struct device *dev)
1042 {
1043 	return msm_drm_init(dev, &msm_driver);
1044 }
1045 
msm_drm_unbind(struct device * dev)1046 static void msm_drm_unbind(struct device *dev)
1047 {
1048 	msm_drm_uninit(dev);
1049 }
1050 
1051 const struct component_master_ops msm_drm_ops = {
1052 	.bind = msm_drm_bind,
1053 	.unbind = msm_drm_unbind,
1054 };
1055 
msm_drv_probe(struct device * master_dev,int (* kms_init)(struct drm_device * dev),struct msm_kms * kms)1056 int msm_drv_probe(struct device *master_dev,
1057 	int (*kms_init)(struct drm_device *dev),
1058 	struct msm_kms *kms)
1059 {
1060 	struct msm_drm_private *priv;
1061 	struct component_match *match = NULL;
1062 	int ret;
1063 
1064 	priv = devm_kzalloc(master_dev, sizeof(*priv), GFP_KERNEL);
1065 	if (!priv)
1066 		return -ENOMEM;
1067 
1068 	priv->kms = kms;
1069 	priv->kms_init = kms_init;
1070 	dev_set_drvdata(master_dev, priv);
1071 
1072 	/* Add mdp components if we have KMS. */
1073 	if (kms_init) {
1074 		ret = add_components_mdp(master_dev, &match);
1075 		if (ret)
1076 			return ret;
1077 	}
1078 
1079 	ret = add_gpu_components(master_dev, &match);
1080 	if (ret)
1081 		return ret;
1082 
1083 	/* on all devices that I am aware of, iommu's which can map
1084 	 * any address the cpu can see are used:
1085 	 */
1086 	ret = dma_set_mask_and_coherent(master_dev, ~0);
1087 	if (ret)
1088 		return ret;
1089 
1090 	ret = component_master_add_with_match(master_dev, &msm_drm_ops, match);
1091 	if (ret)
1092 		return ret;
1093 
1094 	return 0;
1095 }
1096 
1097 /*
1098  * Platform driver:
1099  * Used only for headlesss GPU instances
1100  */
1101 
msm_pdev_probe(struct platform_device * pdev)1102 static int msm_pdev_probe(struct platform_device *pdev)
1103 {
1104 	return msm_drv_probe(&pdev->dev, NULL, NULL);
1105 }
1106 
msm_pdev_remove(struct platform_device * pdev)1107 static void msm_pdev_remove(struct platform_device *pdev)
1108 {
1109 	component_master_del(&pdev->dev, &msm_drm_ops);
1110 }
1111 
1112 static struct platform_driver msm_platform_driver = {
1113 	.probe      = msm_pdev_probe,
1114 	.remove     = msm_pdev_remove,
1115 	.driver     = {
1116 		.name   = "msm",
1117 	},
1118 };
1119 
msm_drm_register(void)1120 static int __init msm_drm_register(void)
1121 {
1122 	if (!modeset)
1123 		return -EINVAL;
1124 
1125 	DBG("init");
1126 	msm_mdp_register();
1127 	msm_dpu_register();
1128 	msm_dsi_register();
1129 	msm_hdmi_register();
1130 	msm_dp_register();
1131 	adreno_register();
1132 	msm_mdp4_register();
1133 	msm_mdss_register();
1134 	return platform_driver_register(&msm_platform_driver);
1135 }
1136 
msm_drm_unregister(void)1137 static void __exit msm_drm_unregister(void)
1138 {
1139 	DBG("fini");
1140 	platform_driver_unregister(&msm_platform_driver);
1141 	msm_mdss_unregister();
1142 	msm_mdp4_unregister();
1143 	msm_dp_unregister();
1144 	msm_hdmi_unregister();
1145 	adreno_unregister();
1146 	msm_dsi_unregister();
1147 	msm_mdp_unregister();
1148 	msm_dpu_unregister();
1149 }
1150 
1151 module_init(msm_drm_register);
1152 module_exit(msm_drm_unregister);
1153 
1154 MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
1155 MODULE_DESCRIPTION("MSM DRM Driver");
1156 MODULE_LICENSE("GPL");
1157