1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2016-2018, 2020-2021 The Linux Foundation. All rights reserved. 4 * Copyright (C) 2013 Red Hat 5 * Author: Rob Clark <robdclark@gmail.com> 6 */ 7 8 #include <linux/dma-mapping.h> 9 #include <linux/fault-inject.h> 10 #include <linux/debugfs.h> 11 #include <linux/of_address.h> 12 #include <linux/uaccess.h> 13 14 #include <drm/drm_drv.h> 15 #include <drm/drm_file.h> 16 #include <drm/drm_ioctl.h> 17 #include <drm/drm_of.h> 18 19 #include "msm_drv.h" 20 #include "msm_debugfs.h" 21 #include "msm_gem.h" 22 #include "msm_gpu.h" 23 #include "msm_kms.h" 24 25 /* 26 * MSM driver version: 27 * - 1.0.0 - initial interface 28 * - 1.1.0 - adds madvise, and support for submits with > 4 cmd buffers 29 * - 1.2.0 - adds explicit fence support for submit ioctl 30 * - 1.3.0 - adds GMEM_BASE + NR_RINGS params, SUBMITQUEUE_NEW + 31 * SUBMITQUEUE_CLOSE ioctls, and MSM_INFO_IOVA flag for 32 * MSM_GEM_INFO ioctl. 33 * - 1.4.0 - softpin, MSM_RELOC_BO_DUMP, and GEM_INFO support to set/get 34 * GEM object's debug name 35 * - 1.5.0 - Add SUBMITQUERY_QUERY ioctl 36 * - 1.6.0 - Syncobj support 37 * - 1.7.0 - Add MSM_PARAM_SUSPENDS to access suspend count 38 * - 1.8.0 - Add MSM_BO_CACHED_COHERENT for supported GPUs (a6xx) 39 * - 1.9.0 - Add MSM_SUBMIT_FENCE_SN_IN 40 * - 1.10.0 - Add MSM_SUBMIT_BO_NO_IMPLICIT 41 * - 1.11.0 - Add wait boost (MSM_WAIT_FENCE_BOOST, MSM_PREP_BOOST) 42 * - 1.12.0 - Add MSM_INFO_SET_METADATA and MSM_INFO_GET_METADATA 43 * - 1.13.0 - Add VM_BIND 44 */ 45 #define MSM_VERSION_MAJOR 1 46 #define MSM_VERSION_MINOR 13 47 #define MSM_VERSION_PATCHLEVEL 0 48 49 bool dumpstate; 50 MODULE_PARM_DESC(dumpstate, "Dump KMS state on errors"); 51 module_param(dumpstate, bool, 0600); 52 53 static bool modeset = true; 54 MODULE_PARM_DESC(modeset, "Use kernel modesetting [KMS] (1=on (default), 0=disable)"); 55 module_param(modeset, bool, 0600); 56 57 static bool separate_gpu_kms; 58 MODULE_PARM_DESC(separate_gpu_drm, "Use separate DRM device for the GPU (0=single DRM device for both GPU and display (default), 1=two DRM devices)"); 59 module_param(separate_gpu_kms, bool, 0400); 60 61 DECLARE_FAULT_ATTR(fail_gem_alloc); 62 DECLARE_FAULT_ATTR(fail_gem_iova); 63 64 bool msm_gpu_no_components(void) 65 { 66 return separate_gpu_kms; 67 } 68 69 static int msm_drm_uninit(struct device *dev, const struct component_ops *gpu_ops) 70 { 71 struct platform_device *pdev = to_platform_device(dev); 72 struct msm_drm_private *priv = platform_get_drvdata(pdev); 73 struct drm_device *ddev = priv->dev; 74 75 /* 76 * Shutdown the hw if we're far enough along where things might be on. 77 * If we run this too early, we'll end up panicking in any variety of 78 * places. Since we don't register the drm device until late in 79 * msm_drm_init, drm_dev->registered is used as an indicator that the 80 * shutdown will be successful. 81 */ 82 if (ddev->registered) { 83 drm_dev_unregister(ddev); 84 if (priv->kms) 85 msm_drm_kms_unregister(dev); 86 } 87 88 msm_gem_shrinker_cleanup(ddev); 89 90 msm_rd_debugfs_cleanup(priv); 91 92 if (priv->kms) 93 msm_drm_kms_uninit(dev); 94 95 if (gpu_ops) 96 gpu_ops->unbind(dev, dev, NULL); 97 else 98 component_unbind_all(dev, ddev); 99 100 ddev->dev_private = NULL; 101 drm_dev_put(ddev); 102 103 return 0; 104 } 105 106 static int msm_drm_init(struct device *dev, const struct drm_driver *drv, 107 const struct component_ops *gpu_ops) 108 { 109 struct msm_drm_private *priv = dev_get_drvdata(dev); 110 struct drm_device *ddev; 111 int ret; 112 113 if (drm_firmware_drivers_only()) 114 return -ENODEV; 115 116 ddev = drm_dev_alloc(drv, dev); 117 if (IS_ERR(ddev)) { 118 DRM_DEV_ERROR(dev, "failed to allocate drm_device\n"); 119 return PTR_ERR(ddev); 120 } 121 ddev->dev_private = priv; 122 priv->dev = ddev; 123 124 INIT_LIST_HEAD(&priv->objects); 125 mutex_init(&priv->obj_lock); 126 127 /* 128 * Initialize the LRUs: 129 */ 130 drm_gem_lru_init(&priv->lru.unbacked); 131 drm_gem_lru_init(&priv->lru.pinned); 132 drm_gem_lru_init(&priv->lru.willneed); 133 drm_gem_lru_init(&priv->lru.dontneed); 134 135 /* Initialize stall-on-fault */ 136 spin_lock_init(&priv->fault_stall_lock); 137 priv->stall_enabled = true; 138 139 /* Teach lockdep about lock ordering wrt. shrinker: */ 140 fs_reclaim_acquire(GFP_KERNEL); 141 might_lock(&ddev->gem_lru_mutex); 142 fs_reclaim_release(GFP_KERNEL); 143 144 if (priv->kms_init) { 145 ret = drmm_mode_config_init(ddev); 146 if (ret) 147 goto err_put_dev; 148 } 149 150 dma_set_max_seg_size(dev, UINT_MAX); 151 152 /* Bind all our sub-components: */ 153 if (gpu_ops) 154 ret = gpu_ops->bind(dev, dev, NULL); 155 else 156 ret = component_bind_all(dev, ddev); 157 if (ret) 158 goto err_put_dev; 159 160 ret = msm_gem_shrinker_init(ddev); 161 if (ret) 162 goto err_msm_uninit; 163 164 if (priv->kms_init) { 165 ret = msm_drm_kms_init(dev, drv); 166 if (ret) 167 goto err_msm_uninit; 168 } 169 170 ret = drm_dev_register(ddev, 0); 171 if (ret) 172 goto err_msm_uninit; 173 174 ret = msm_debugfs_late_init(ddev); 175 if (ret) 176 goto err_msm_uninit; 177 178 if (priv->kms_init) 179 msm_drm_kms_post_init(dev); 180 181 return 0; 182 183 err_msm_uninit: 184 msm_drm_uninit(dev, gpu_ops); 185 186 return ret; 187 188 err_put_dev: 189 drm_dev_put(ddev); 190 191 return ret; 192 } 193 194 /* 195 * DRM operations: 196 */ 197 198 static void load_gpu(struct drm_device *dev) 199 { 200 static DEFINE_MUTEX(init_lock); 201 struct msm_drm_private *priv = dev->dev_private; 202 203 mutex_lock(&init_lock); 204 205 if (!priv->gpu) 206 priv->gpu = adreno_load_gpu(dev); 207 208 mutex_unlock(&init_lock); 209 } 210 211 /** 212 * msm_context_vm - lazily create the context's VM 213 * 214 * @dev: the drm device 215 * @ctx: the context 216 * 217 * The VM is lazily created, so that userspace has a chance to opt-in to having 218 * a userspace managed VM before the VM is created. 219 * 220 * Note that this does not return a reference to the VM. Once the VM is created, 221 * it exists for the lifetime of the context. 222 */ 223 struct drm_gpuvm *msm_context_vm(struct drm_device *dev, struct msm_context *ctx) 224 { 225 static DEFINE_MUTEX(init_lock); 226 struct msm_drm_private *priv = dev->dev_private; 227 228 /* Once ctx->vm is created it is valid for the lifetime of the context: */ 229 if (ctx->vm) 230 return ctx->vm; 231 232 mutex_lock(&init_lock); 233 if (!ctx->vm) { 234 ctx->vm = msm_gpu_create_private_vm( 235 priv->gpu, current, !ctx->userspace_managed_vm); 236 237 } 238 mutex_unlock(&init_lock); 239 240 return ctx->vm; 241 } 242 243 static int context_init(struct drm_device *dev, struct drm_file *file) 244 { 245 static atomic_t ident = ATOMIC_INIT(0); 246 struct msm_context *ctx; 247 248 ctx = kzalloc_obj(*ctx); 249 if (!ctx) 250 return -ENOMEM; 251 252 INIT_LIST_HEAD(&ctx->submitqueues); 253 rwlock_init(&ctx->queuelock); 254 255 kref_init(&ctx->ref); 256 msm_submitqueue_init(dev, ctx); 257 258 file->driver_priv = ctx; 259 260 ctx->seqno = atomic_inc_return(&ident); 261 262 return 0; 263 } 264 265 static int msm_open(struct drm_device *dev, struct drm_file *file) 266 { 267 /* For now, load gpu on open.. to avoid the requirement of having 268 * firmware in the initrd. 269 */ 270 load_gpu(dev); 271 272 return context_init(dev, file); 273 } 274 275 static void context_close(struct msm_context *ctx) 276 { 277 ctx->closed = true; 278 msm_submitqueue_close(ctx); 279 msm_context_put(ctx); 280 } 281 282 static void msm_postclose(struct drm_device *dev, struct drm_file *file) 283 { 284 struct msm_drm_private *priv = dev->dev_private; 285 struct msm_context *ctx = file->driver_priv; 286 287 /* 288 * It is not possible to set sysprof param to non-zero if gpu 289 * is not initialized: 290 */ 291 if (priv->gpu) 292 msm_context_set_sysprof(ctx, priv->gpu, 0); 293 294 context_close(ctx); 295 } 296 297 /* 298 * DRM ioctls: 299 */ 300 301 static int msm_ioctl_get_param(struct drm_device *dev, void *data, 302 struct drm_file *file) 303 { 304 struct msm_drm_private *priv = dev->dev_private; 305 struct drm_msm_param *args = data; 306 struct msm_gpu *gpu; 307 308 /* for now, we just have 3d pipe.. eventually this would need to 309 * be more clever to dispatch to appropriate gpu module: 310 */ 311 if ((args->pipe != MSM_PIPE_3D0) || (args->pad != 0)) 312 return -EINVAL; 313 314 gpu = priv->gpu; 315 316 if (!gpu) 317 return -ENXIO; 318 319 return gpu->funcs->get_param(gpu, file->driver_priv, 320 args->param, &args->value, &args->len); 321 } 322 323 static int msm_ioctl_set_param(struct drm_device *dev, void *data, 324 struct drm_file *file) 325 { 326 struct msm_drm_private *priv = dev->dev_private; 327 struct drm_msm_param *args = data; 328 struct msm_gpu *gpu; 329 330 if ((args->pipe != MSM_PIPE_3D0) || (args->pad != 0)) 331 return -EINVAL; 332 333 gpu = priv->gpu; 334 335 if (!gpu) 336 return -ENXIO; 337 338 return gpu->funcs->set_param(gpu, file->driver_priv, 339 args->param, args->value, args->len); 340 } 341 342 static int msm_ioctl_gem_new(struct drm_device *dev, void *data, 343 struct drm_file *file) 344 { 345 struct drm_msm_gem_new *args = data; 346 uint32_t flags = args->flags; 347 348 if (args->flags & ~MSM_BO_FLAGS) { 349 DRM_ERROR("invalid flags: %08x\n", args->flags); 350 return -EINVAL; 351 } 352 353 /* 354 * Uncached CPU mappings are deprecated, as of: 355 * 356 * 9ef364432db4 ("drm/msm: deprecate MSM_BO_UNCACHED (map as writecombine instead)") 357 * 358 * So promote them to WC. 359 */ 360 if (flags & MSM_BO_UNCACHED) { 361 flags &= ~MSM_BO_CACHED; 362 flags |= MSM_BO_WC; 363 } 364 365 if (should_fail(&fail_gem_alloc, args->size)) 366 return -ENOMEM; 367 368 return msm_gem_new_handle(dev, file, args->size, 369 args->flags, &args->handle, NULL); 370 } 371 372 static inline ktime_t to_ktime(struct drm_msm_timespec timeout) 373 { 374 return ktime_set(timeout.tv_sec, timeout.tv_nsec); 375 } 376 377 static int msm_ioctl_gem_cpu_prep(struct drm_device *dev, void *data, 378 struct drm_file *file) 379 { 380 struct drm_msm_gem_cpu_prep *args = data; 381 struct drm_gem_object *obj; 382 ktime_t timeout = to_ktime(args->timeout); 383 int ret; 384 385 if (args->op & ~MSM_PREP_FLAGS) { 386 DRM_ERROR("invalid op: %08x\n", args->op); 387 return -EINVAL; 388 } 389 390 obj = drm_gem_object_lookup(file, args->handle); 391 if (!obj) 392 return -ENOENT; 393 394 ret = msm_gem_cpu_prep(obj, args->op, &timeout); 395 396 drm_gem_object_put(obj); 397 398 return ret; 399 } 400 401 static int msm_ioctl_gem_cpu_fini(struct drm_device *dev, void *data, 402 struct drm_file *file) 403 { 404 struct drm_msm_gem_cpu_fini *args = data; 405 struct drm_gem_object *obj; 406 int ret; 407 408 obj = drm_gem_object_lookup(file, args->handle); 409 if (!obj) 410 return -ENOENT; 411 412 ret = msm_gem_cpu_fini(obj); 413 414 drm_gem_object_put(obj); 415 416 return ret; 417 } 418 419 static int msm_ioctl_gem_info_iova(struct drm_device *dev, 420 struct drm_file *file, struct drm_gem_object *obj, 421 uint64_t *iova) 422 { 423 struct msm_drm_private *priv = dev->dev_private; 424 struct msm_context *ctx = file->driver_priv; 425 426 if (!priv->gpu) 427 return -EINVAL; 428 429 if (msm_context_is_vmbind(ctx)) 430 return UERR(EINVAL, dev, "VM_BIND is enabled"); 431 432 if (should_fail(&fail_gem_iova, obj->size)) 433 return -ENOMEM; 434 435 /* 436 * Don't pin the memory here - just get an address so that userspace can 437 * be productive 438 */ 439 return msm_gem_get_iova(obj, msm_context_vm(dev, ctx), iova); 440 } 441 442 static int msm_ioctl_gem_info_set_iova(struct drm_device *dev, 443 struct drm_file *file, struct drm_gem_object *obj, 444 uint64_t iova) 445 { 446 struct msm_drm_private *priv = dev->dev_private; 447 struct msm_context *ctx = file->driver_priv; 448 struct drm_gpuvm *vm = msm_context_vm(dev, ctx); 449 450 if (!priv->gpu) 451 return -EINVAL; 452 453 if (msm_context_is_vmbind(ctx)) 454 return UERR(EINVAL, dev, "VM_BIND is enabled"); 455 456 /* Only supported if per-process address space is supported: */ 457 if (priv->gpu->vm == vm) 458 return UERR(EOPNOTSUPP, dev, "requires per-process pgtables"); 459 460 if (should_fail(&fail_gem_iova, obj->size)) 461 return -ENOMEM; 462 463 return msm_gem_set_iova(obj, vm, iova); 464 } 465 466 static int msm_ioctl_gem_info_set_metadata(struct drm_gem_object *obj, 467 __user void *metadata, 468 u32 metadata_size) 469 { 470 struct msm_gem_object *msm_obj = to_msm_bo(obj); 471 void *new_metadata; 472 void *buf; 473 int ret; 474 475 /* Impose a moderate upper bound on metadata size: */ 476 if (metadata_size > 128) { 477 return -EOVERFLOW; 478 } 479 480 /* Use a temporary buf to keep copy_from_user() outside of gem obj lock: */ 481 buf = memdup_user(metadata, metadata_size); 482 if (IS_ERR(buf)) 483 return PTR_ERR(buf); 484 485 ret = msm_gem_lock_interruptible(obj); 486 if (ret) 487 goto out; 488 489 new_metadata = 490 krealloc(msm_obj->metadata, metadata_size, GFP_KERNEL); 491 if (!new_metadata) { 492 ret = -ENOMEM; 493 goto out; 494 } 495 496 msm_obj->metadata = new_metadata; 497 msm_obj->metadata_size = metadata_size; 498 memcpy(msm_obj->metadata, buf, metadata_size); 499 500 msm_gem_unlock(obj); 501 502 out: 503 kfree(buf); 504 505 return ret; 506 } 507 508 static int msm_ioctl_gem_info_get_metadata(struct drm_gem_object *obj, 509 __user void *metadata, 510 u32 *metadata_size) 511 { 512 struct msm_gem_object *msm_obj = to_msm_bo(obj); 513 void *buf; 514 int ret, len; 515 516 if (!metadata) { 517 /* 518 * Querying the size is inherently racey, but 519 * EXT_external_objects expects the app to confirm 520 * via device and driver UUIDs that the exporter and 521 * importer versions match. All we can do from the 522 * kernel side is check the length under obj lock 523 * when userspace tries to retrieve the metadata 524 */ 525 *metadata_size = msm_obj->metadata_size; 526 return 0; 527 } 528 529 ret = msm_gem_lock_interruptible(obj); 530 if (ret) 531 return ret; 532 533 /* Avoid copy_to_user() under gem obj lock: */ 534 len = msm_obj->metadata_size; 535 buf = kmemdup(msm_obj->metadata, len, GFP_KERNEL); 536 537 if (!buf) { 538 msm_gem_unlock(obj); 539 return -ENOMEM; 540 } 541 542 msm_gem_unlock(obj); 543 544 if (*metadata_size < len) { 545 ret = -ETOOSMALL; 546 } else if (copy_to_user(metadata, buf, len)) { 547 ret = -EFAULT; 548 } else { 549 *metadata_size = len; 550 } 551 552 kfree(buf); 553 554 return ret; 555 } 556 557 static int msm_ioctl_gem_info(struct drm_device *dev, void *data, 558 struct drm_file *file) 559 { 560 struct drm_msm_gem_info *args = data; 561 struct drm_gem_object *obj; 562 struct msm_gem_object *msm_obj; 563 int i, ret = 0; 564 565 if (args->pad) 566 return -EINVAL; 567 568 switch (args->info) { 569 case MSM_INFO_GET_OFFSET: 570 case MSM_INFO_GET_IOVA: 571 case MSM_INFO_SET_IOVA: 572 case MSM_INFO_GET_FLAGS: 573 /* value returned as immediate, not pointer, so len==0: */ 574 if (args->len) 575 return -EINVAL; 576 break; 577 case MSM_INFO_SET_NAME: 578 case MSM_INFO_GET_NAME: 579 case MSM_INFO_SET_METADATA: 580 case MSM_INFO_GET_METADATA: 581 break; 582 default: 583 return -EINVAL; 584 } 585 586 obj = drm_gem_object_lookup(file, args->handle); 587 if (!obj) 588 return -ENOENT; 589 590 msm_obj = to_msm_bo(obj); 591 592 switch (args->info) { 593 case MSM_INFO_GET_OFFSET: 594 ret = drm_gem_create_mmap_offset(obj); 595 if (ret == 0) 596 args->value = drm_vma_node_offset_addr(&obj->vma_node); 597 break; 598 case MSM_INFO_GET_IOVA: 599 ret = msm_ioctl_gem_info_iova(dev, file, obj, &args->value); 600 break; 601 case MSM_INFO_SET_IOVA: 602 ret = msm_ioctl_gem_info_set_iova(dev, file, obj, args->value); 603 break; 604 case MSM_INFO_GET_FLAGS: 605 if (drm_gem_is_imported(obj)) { 606 ret = -EINVAL; 607 break; 608 } 609 /* Hide internal kernel-only flags: */ 610 args->value = to_msm_bo(obj)->flags & MSM_BO_FLAGS; 611 ret = 0; 612 break; 613 case MSM_INFO_SET_NAME: 614 /* length check should leave room for terminating null: */ 615 if (args->len >= sizeof(msm_obj->name)) { 616 ret = -EINVAL; 617 break; 618 } 619 if (copy_from_user(msm_obj->name, u64_to_user_ptr(args->value), 620 args->len)) { 621 msm_obj->name[0] = '\0'; 622 ret = -EFAULT; 623 break; 624 } 625 msm_obj->name[args->len] = '\0'; 626 for (i = 0; i < args->len; i++) { 627 if (!isprint(msm_obj->name[i])) { 628 msm_obj->name[i] = '\0'; 629 break; 630 } 631 } 632 break; 633 case MSM_INFO_GET_NAME: 634 if (args->value && (args->len < strlen(msm_obj->name))) { 635 ret = -ETOOSMALL; 636 break; 637 } 638 args->len = strlen(msm_obj->name); 639 if (args->value) { 640 if (copy_to_user(u64_to_user_ptr(args->value), 641 msm_obj->name, args->len)) 642 ret = -EFAULT; 643 } 644 break; 645 case MSM_INFO_SET_METADATA: 646 ret = msm_ioctl_gem_info_set_metadata( 647 obj, u64_to_user_ptr(args->value), args->len); 648 break; 649 case MSM_INFO_GET_METADATA: 650 ret = msm_ioctl_gem_info_get_metadata( 651 obj, u64_to_user_ptr(args->value), &args->len); 652 break; 653 } 654 655 drm_gem_object_put(obj); 656 657 return ret; 658 } 659 660 static int wait_fence(struct msm_gpu_submitqueue *queue, uint32_t fence_id, 661 ktime_t timeout, uint32_t flags) 662 { 663 struct dma_fence *fence; 664 int ret; 665 666 if (fence_after(fence_id, queue->last_fence)) { 667 DRM_ERROR_RATELIMITED("waiting on invalid fence: %u (of %u)\n", 668 fence_id, queue->last_fence); 669 return -EINVAL; 670 } 671 672 /* 673 * Map submitqueue scoped "seqno" (which is actually an idr key) 674 * back to underlying dma-fence 675 * 676 * The fence is removed from the fence_idr when the submit is 677 * retired, so if the fence is not found it means there is nothing 678 * to wait for 679 */ 680 spin_lock(&queue->idr_lock); 681 fence = idr_find(&queue->fence_idr, fence_id); 682 if (fence) 683 fence = dma_fence_get_rcu(fence); 684 spin_unlock(&queue->idr_lock); 685 686 if (!fence) 687 return 0; 688 689 if (flags & MSM_WAIT_FENCE_BOOST) 690 dma_fence_set_deadline(fence, ktime_get()); 691 692 ret = dma_fence_wait_timeout(fence, true, timeout_to_jiffies(&timeout)); 693 if (ret == 0) { 694 ret = -ETIMEDOUT; 695 } else if (ret != -ERESTARTSYS) { 696 ret = 0; 697 } 698 699 dma_fence_put(fence); 700 701 return ret; 702 } 703 704 static int msm_ioctl_wait_fence(struct drm_device *dev, void *data, 705 struct drm_file *file) 706 { 707 struct msm_drm_private *priv = dev->dev_private; 708 struct drm_msm_wait_fence *args = data; 709 struct msm_gpu_submitqueue *queue; 710 int ret; 711 712 if (args->flags & ~MSM_WAIT_FENCE_FLAGS) { 713 DRM_ERROR("invalid flags: %08x\n", args->flags); 714 return -EINVAL; 715 } 716 717 if (!priv->gpu) 718 return 0; 719 720 queue = msm_submitqueue_get(file->driver_priv, args->queueid); 721 if (!queue) 722 return -ENOENT; 723 724 ret = wait_fence(queue, args->fence, to_ktime(args->timeout), args->flags); 725 726 msm_submitqueue_put(queue); 727 728 return ret; 729 } 730 731 static int msm_ioctl_gem_madvise(struct drm_device *dev, void *data, 732 struct drm_file *file) 733 { 734 struct drm_msm_gem_madvise *args = data; 735 struct drm_gem_object *obj; 736 int ret; 737 738 switch (args->madv) { 739 case MSM_MADV_DONTNEED: 740 case MSM_MADV_WILLNEED: 741 break; 742 default: 743 return -EINVAL; 744 } 745 746 obj = drm_gem_object_lookup(file, args->handle); 747 if (!obj) { 748 return -ENOENT; 749 } 750 751 ret = msm_gem_madvise(obj, args->madv); 752 if (ret >= 0) { 753 args->retained = ret; 754 ret = 0; 755 } 756 757 drm_gem_object_put(obj); 758 759 return ret; 760 } 761 762 763 static int msm_ioctl_submitqueue_new(struct drm_device *dev, void *data, 764 struct drm_file *file) 765 { 766 struct drm_msm_submitqueue *args = data; 767 768 if (args->flags & ~MSM_SUBMITQUEUE_FLAGS) 769 return -EINVAL; 770 771 return msm_submitqueue_create(dev, file->driver_priv, args->prio, 772 args->flags, &args->id); 773 } 774 775 static int msm_ioctl_submitqueue_query(struct drm_device *dev, void *data, 776 struct drm_file *file) 777 { 778 return msm_submitqueue_query(dev, file->driver_priv, data); 779 } 780 781 static int msm_ioctl_submitqueue_close(struct drm_device *dev, void *data, 782 struct drm_file *file) 783 { 784 u32 id = *(u32 *) data; 785 786 return msm_submitqueue_remove(file->driver_priv, id); 787 } 788 789 static const struct drm_ioctl_desc msm_ioctls[] = { 790 DRM_IOCTL_DEF_DRV(MSM_GET_PARAM, msm_ioctl_get_param, DRM_RENDER_ALLOW), 791 DRM_IOCTL_DEF_DRV(MSM_SET_PARAM, msm_ioctl_set_param, DRM_RENDER_ALLOW), 792 DRM_IOCTL_DEF_DRV(MSM_GEM_NEW, msm_ioctl_gem_new, DRM_RENDER_ALLOW), 793 DRM_IOCTL_DEF_DRV(MSM_GEM_INFO, msm_ioctl_gem_info, DRM_RENDER_ALLOW), 794 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_PREP, msm_ioctl_gem_cpu_prep, DRM_RENDER_ALLOW), 795 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_FINI, msm_ioctl_gem_cpu_fini, DRM_RENDER_ALLOW), 796 DRM_IOCTL_DEF_DRV(MSM_GEM_SUBMIT, msm_ioctl_gem_submit, DRM_RENDER_ALLOW), 797 DRM_IOCTL_DEF_DRV(MSM_WAIT_FENCE, msm_ioctl_wait_fence, DRM_RENDER_ALLOW), 798 DRM_IOCTL_DEF_DRV(MSM_GEM_MADVISE, msm_ioctl_gem_madvise, DRM_RENDER_ALLOW), 799 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_NEW, msm_ioctl_submitqueue_new, DRM_RENDER_ALLOW), 800 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_CLOSE, msm_ioctl_submitqueue_close, DRM_RENDER_ALLOW), 801 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_QUERY, msm_ioctl_submitqueue_query, DRM_RENDER_ALLOW), 802 DRM_IOCTL_DEF_DRV(MSM_VM_BIND, msm_ioctl_vm_bind, DRM_RENDER_ALLOW), 803 DRM_IOCTL_DEF_DRV(MSM_PERFCNTR_CONFIG, msm_ioctl_perfcntr_config, DRM_RENDER_ALLOW), 804 }; 805 806 static void msm_show_fdinfo(struct drm_printer *p, struct drm_file *file) 807 { 808 struct drm_device *dev = file->minor->dev; 809 struct msm_drm_private *priv = dev->dev_private; 810 811 if (!priv->gpu) 812 return; 813 814 msm_gpu_show_fdinfo(priv->gpu, file->driver_priv, p); 815 816 drm_show_memory_stats(p, file); 817 } 818 819 static const struct file_operations fops = { 820 .owner = THIS_MODULE, 821 DRM_GEM_FOPS, 822 .show_fdinfo = drm_show_fdinfo, 823 }; 824 825 #define DRIVER_FEATURES_GPU ( \ 826 DRIVER_GEM | \ 827 DRIVER_GEM_GPUVA | \ 828 DRIVER_RENDER | \ 829 DRIVER_SYNCOBJ | \ 830 DRIVER_SYNCOBJ_TIMELINE | \ 831 0 ) 832 833 #define DRIVER_FEATURES_KMS ( \ 834 DRIVER_GEM | \ 835 DRIVER_GEM_GPUVA | \ 836 DRIVER_ATOMIC | \ 837 DRIVER_MODESET | \ 838 0 ) 839 840 static const struct drm_driver msm_driver = { 841 .driver_features = DRIVER_FEATURES_GPU | DRIVER_FEATURES_KMS, 842 .open = msm_open, 843 .postclose = msm_postclose, 844 .dumb_create = msm_gem_dumb_create, 845 .dumb_map_offset = drm_gem_dumb_map_offset, 846 .gem_prime_import = msm_gem_prime_import, 847 .gem_prime_import_sg_table = msm_gem_prime_import_sg_table, 848 #ifdef CONFIG_DEBUG_FS 849 .debugfs_init = msm_debugfs_init, 850 #endif 851 MSM_FBDEV_DRIVER_OPS, 852 .show_fdinfo = msm_show_fdinfo, 853 .ioctls = msm_ioctls, 854 .num_ioctls = ARRAY_SIZE(msm_ioctls), 855 .fops = &fops, 856 .name = "msm", 857 .desc = "MSM Snapdragon DRM", 858 .major = MSM_VERSION_MAJOR, 859 .minor = MSM_VERSION_MINOR, 860 .patchlevel = MSM_VERSION_PATCHLEVEL, 861 }; 862 863 static const struct drm_driver msm_kms_driver = { 864 .driver_features = DRIVER_FEATURES_KMS, 865 .open = msm_open, 866 .postclose = msm_postclose, 867 .dumb_create = msm_gem_dumb_create, 868 .dumb_map_offset = drm_gem_dumb_map_offset, 869 .gem_prime_import_sg_table = msm_gem_prime_import_sg_table, 870 #ifdef CONFIG_DEBUG_FS 871 .debugfs_init = msm_debugfs_init, 872 #endif 873 MSM_FBDEV_DRIVER_OPS, 874 .show_fdinfo = msm_show_fdinfo, 875 .fops = &fops, 876 .name = "msm-kms", 877 .desc = "MSM Snapdragon DRM", 878 .major = MSM_VERSION_MAJOR, 879 .minor = MSM_VERSION_MINOR, 880 .patchlevel = MSM_VERSION_PATCHLEVEL, 881 }; 882 883 static const struct drm_driver msm_gpu_driver = { 884 .driver_features = DRIVER_FEATURES_GPU, 885 .open = msm_open, 886 .postclose = msm_postclose, 887 .gem_prime_import_sg_table = msm_gem_prime_import_sg_table, 888 #ifdef CONFIG_DEBUG_FS 889 .debugfs_init = msm_debugfs_init, 890 #endif 891 .show_fdinfo = msm_show_fdinfo, 892 .ioctls = msm_ioctls, 893 .num_ioctls = ARRAY_SIZE(msm_ioctls), 894 .fops = &fops, 895 .name = "msm", 896 .desc = "MSM Snapdragon DRM", 897 .major = MSM_VERSION_MAJOR, 898 .minor = MSM_VERSION_MINOR, 899 .patchlevel = MSM_VERSION_PATCHLEVEL, 900 }; 901 902 /* 903 * Componentized driver support: 904 */ 905 906 /* 907 * Identify what components need to be added by parsing what remote-endpoints 908 * our MDP output ports are connected to. In the case of LVDS on MDP4, there 909 * is no external component that we need to add since LVDS is within MDP4 910 * itself. 911 */ 912 static int add_mdp_components(struct device *master_dev, 913 struct component_match **matchptr) 914 { 915 struct device_node *np = master_dev->of_node; 916 struct device_node *ep_node; 917 918 for_each_endpoint_of_node(np, ep_node) { 919 struct device_node *intf; 920 struct of_endpoint ep; 921 int ret; 922 923 ret = of_graph_parse_endpoint(ep_node, &ep); 924 if (ret) { 925 DRM_DEV_ERROR(master_dev, "unable to parse port endpoint\n"); 926 of_node_put(ep_node); 927 return ret; 928 } 929 930 /* 931 * The LCDC/LVDS port on MDP4 is a speacial case where the 932 * remote-endpoint isn't a component that we need to add 933 */ 934 if (of_device_is_compatible(np, "qcom,mdp4") && 935 ep.port == 0) 936 continue; 937 938 /* 939 * It's okay if some of the ports don't have a remote endpoint 940 * specified. It just means that the port isn't connected to 941 * any external interface. 942 */ 943 intf = of_graph_get_remote_port_parent(ep_node); 944 if (!intf) 945 continue; 946 947 if (of_device_is_available(intf)) 948 drm_of_component_match_add(master_dev, matchptr, 949 component_compare_of, intf); 950 951 of_node_put(intf); 952 } 953 954 return 0; 955 } 956 957 #if !IS_REACHABLE(CONFIG_DRM_MSM_MDP5) || !IS_REACHABLE(CONFIG_DRM_MSM_DPU) 958 bool msm_disp_drv_should_bind(struct device *dev, bool dpu_driver) 959 { 960 /* If just a single driver is enabled, use it no matter what */ 961 return true; 962 } 963 #else 964 965 static bool prefer_mdp5 = true; 966 MODULE_PARM_DESC(prefer_mdp5, "Select whether MDP5 or DPU driver should be preferred"); 967 module_param(prefer_mdp5, bool, 0444); 968 969 /* list all platforms that have been migrated from mdp5 to dpu driver */ 970 static const char *const msm_mdp5_dpu_migrated[] = { 971 /* there never was qcom,msm8998-mdp5 */ 972 "qcom,sdm630-mdp5", 973 "qcom,sdm660-mdp5", 974 NULL 975 }; 976 977 /* list all platforms supported by both mdp5 and dpu drivers */ 978 static const char *const msm_mdp5_dpu_migration[] = { 979 "qcom,msm8917-mdp5", 980 "qcom,msm8937-mdp5", 981 "qcom,msm8953-mdp5", 982 "qcom,msm8996-mdp5", 983 NULL, 984 }; 985 986 bool msm_disp_drv_should_bind(struct device *dev, bool dpu_driver) 987 { 988 /* If it is not an MDP5 device, use DPU */ 989 if (!of_device_is_compatible(dev->of_node, "qcom,mdp5")) 990 return dpu_driver; 991 992 /* If it is no longer supported by MDP5, use DPU */ 993 if (of_device_compatible_match(dev->of_node, msm_mdp5_dpu_migrated)) 994 return dpu_driver; 995 996 /* If it is not in the migration list, use MDP5 */ 997 if (!of_device_compatible_match(dev->of_node, msm_mdp5_dpu_migration)) 998 return !dpu_driver; 999 1000 return prefer_mdp5 ? !dpu_driver : dpu_driver; 1001 } 1002 #endif 1003 1004 /* 1005 * We don't know what's the best binding to link the gpu with the drm device. 1006 * Fow now, we just hunt for all the possible gpus that we support, and add them 1007 * as components. 1008 */ 1009 static const struct of_device_id msm_gpu_match[] = { 1010 { .compatible = "qcom,adreno" }, 1011 { .compatible = "qcom,adreno-3xx" }, 1012 { .compatible = "amd,imageon" }, 1013 { .compatible = "qcom,kgsl-3d0" }, 1014 { }, 1015 }; 1016 1017 static int add_gpu_components(struct device *dev, 1018 struct component_match **matchptr) 1019 { 1020 struct device_node *np; 1021 1022 np = of_find_matching_node(NULL, msm_gpu_match); 1023 if (!np) 1024 return 0; 1025 1026 if (of_device_is_available(np) && adreno_has_gpu(np)) 1027 drm_of_component_match_add(dev, matchptr, component_compare_of, np); 1028 1029 of_node_put(np); 1030 1031 return 0; 1032 } 1033 1034 static int msm_drm_bind(struct device *dev) 1035 { 1036 return msm_drm_init(dev, 1037 msm_gpu_no_components() ? 1038 &msm_kms_driver : 1039 &msm_driver, 1040 NULL); 1041 } 1042 1043 static void msm_drm_unbind(struct device *dev) 1044 { 1045 msm_drm_uninit(dev, NULL); 1046 } 1047 1048 const struct component_master_ops msm_drm_ops = { 1049 .bind = msm_drm_bind, 1050 .unbind = msm_drm_unbind, 1051 }; 1052 1053 int msm_drv_probe(struct device *master_dev, 1054 int (*kms_init)(struct drm_device *dev), 1055 struct msm_kms *kms) 1056 { 1057 struct msm_drm_private *priv; 1058 struct component_match *match = NULL; 1059 int ret; 1060 1061 priv = devm_kzalloc(master_dev, sizeof(*priv), GFP_KERNEL); 1062 if (!priv) 1063 return -ENOMEM; 1064 1065 priv->kms = kms; 1066 priv->kms_init = kms_init; 1067 dev_set_drvdata(master_dev, priv); 1068 1069 /* Add mdp components if we have KMS. */ 1070 if (kms_init) { 1071 ret = add_mdp_components(master_dev, &match); 1072 if (ret) 1073 return ret; 1074 } 1075 1076 if (!msm_gpu_no_components()) { 1077 ret = add_gpu_components(master_dev, &match); 1078 if (ret) 1079 return ret; 1080 } 1081 1082 /* on all devices that I am aware of, iommu's which can map 1083 * any address the cpu can see are used: 1084 */ 1085 ret = dma_set_mask_and_coherent(master_dev, ~0); 1086 if (ret) 1087 return ret; 1088 1089 ret = component_master_add_with_match(master_dev, &msm_drm_ops, match); 1090 if (ret) 1091 return ret; 1092 1093 return 0; 1094 } 1095 1096 int msm_gpu_probe(struct platform_device *pdev, 1097 const struct component_ops *ops) 1098 { 1099 struct msm_drm_private *priv; 1100 int ret; 1101 1102 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 1103 if (!priv) 1104 return -ENOMEM; 1105 1106 platform_set_drvdata(pdev, priv); 1107 1108 /* on all devices that I am aware of, iommu's which can map 1109 * any address the cpu can see are used: 1110 */ 1111 ret = dma_set_mask_and_coherent(&pdev->dev, ~0); 1112 if (ret) 1113 return ret; 1114 1115 return msm_drm_init(&pdev->dev, &msm_gpu_driver, ops); 1116 } 1117 1118 void msm_gpu_remove(struct platform_device *pdev, 1119 const struct component_ops *ops) 1120 { 1121 msm_drm_uninit(&pdev->dev, ops); 1122 } 1123 1124 static int __init msm_drm_register(void) 1125 { 1126 if (!modeset) 1127 return -EINVAL; 1128 1129 DBG("init"); 1130 msm_mdp_register(); 1131 msm_dpu_register(); 1132 msm_dsi_register(); 1133 msm_hdmi_register(); 1134 msm_dp_register(); 1135 adreno_register(); 1136 msm_mdp4_register(); 1137 msm_mdss_register(); 1138 1139 return 0; 1140 } 1141 1142 static void __exit msm_drm_unregister(void) 1143 { 1144 DBG("fini"); 1145 msm_mdss_unregister(); 1146 msm_mdp4_unregister(); 1147 msm_dp_unregister(); 1148 msm_hdmi_unregister(); 1149 adreno_unregister(); 1150 msm_dsi_unregister(); 1151 msm_mdp_unregister(); 1152 msm_dpu_unregister(); 1153 } 1154 1155 module_init(msm_drm_register); 1156 module_exit(msm_drm_unregister); 1157 1158 MODULE_AUTHOR("Rob Clark <robdclark@gmail.com"); 1159 MODULE_DESCRIPTION("MSM DRM Driver"); 1160 MODULE_LICENSE("GPL"); 1161