1 /*
2 * This file and its contents are supplied under the terms of the
3 * Common Development and Distribution License ("CDDL"), version 1.0.
4 * You may only use this file in accordance with the terms of version
5 * 1.0 of the CDDL.
6 *
7 * A full copy of the text of the CDDL should have accompanied this
8 * source. A copy of the CDDL is also available via the Internet at
9 * http://www.illumos.org/license/CDDL.
10 */
11
12 /*
13 * This file is part of the Chelsio T4 support code.
14 *
15 * Copyright (C) 2010-2013 Chelsio Communications. All rights reserved.
16 *
17 * This program is distributed in the hope that it will be useful, but WITHOUT
18 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
19 * FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this
20 * release for licensing terms and conditions.
21 */
22
23 /*
24 * Copyright 2024 Oxide Computer Company
25 */
26
27 #ifndef __CXGBE_OSDEP_H
28 #define __CXGBE_OSDEP_H
29
30 #include <sys/ddi.h>
31 #include <sys/sunddi.h>
32 #include <sys/byteorder.h>
33 #include <sys/cmn_err.h>
34 #include <sys/pcie.h>
35 #include <sys/sysmacros.h>
36 #include <sys/inttypes.h>
37 #include <sys/stdbool.h>
38 #include <sys/sysmacros.h>
39 #include <sys/mutex.h>
40
41 #define CH_DUMP_MBOX(adap, mbox, data_reg, size) do {} while (0)
42
43 #define PCI_VENDOR_ID 0x00
44 #define PCI_DEVICE_ID 0x02
45
46 #define PCI_BASE_ADDRESS_0 0x10
47 #define PCI_BASE_ADDRESS_1 0x14
48 #define PCI_BASE_ADDRESS_2 0x18
49 #define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL)
50
51 #define PCI_CAP_ID_EXP PCI_CAP_ID_PCI_E
52 #define PCI_EXP_DEVCTL PCIE_DEVCTL
53 #define PCI_EXP_DEVCTL_PAYLOAD PCIE_DEVCTL_MAX_PAYLOAD_MASK
54 #define PCI_EXP_DEVCTL_READRQ PCIE_DEVCTL_MAX_READ_REQ_MASK
55 #define PCI_EXP_LNKCTL PCIE_LINKCTL
56 #define PCI_EXP_LNKSTA PCIE_LINKSTS
57 #define PCI_EXP_LNKSTA_CLS PCIE_LINKSTS_SPEED_MASK
58 #define PCI_EXP_LNKSTA_NLW PCIE_LINKSTS_NEG_WIDTH_MASK
59 #define PCI_EXP_DEVCTL2 0x28
60
61 #define PCI_VPD_ADDR 2
62 #define PCI_VPD_ADDR_F 0x8000
63 #define PCI_VPD_DATA 4
64
65 #define __devinit
66 #define DIV_ROUND_UP(x, y) howmany(x, y)
67
68 #define udelay(x) drv_usecwait(x)
69 #define msleep(x) delay(drv_usectohz(1000ULL * (x)))
70 #define mdelay(x) drv_usecwait(1000UL * (x))
71
72 #define le16_to_cpu(x) LE_16((uint16_t)(x))
73 #define le32_to_cpu(x) LE_32((uint32_t)(x))
74 #define le64_to_cpu(x) LE_64((uint64_t)(x))
75 #define cpu_to_le16(x) LE_16((uint16_t)(x))
76 #define cpu_to_le32(x) LE_32((uint32_t)(x))
77 #define cpu_to_le64(x) LE_64((uint64_t)(x))
78 #define be16_to_cpu(x) BE_16((uint16_t)(x))
79 #define be32_to_cpu(x) BE_32((uint32_t)(x))
80 #define be64_to_cpu(x) BE_64((uint64_t)(x))
81 #define cpu_to_be16(x) BE_16((uint16_t)(x))
82 #define cpu_to_be32(x) BE_32((uint32_t)(x))
83 #define cpu_to_be64(x) BE_64((uint64_t)(x))
84 #define swab32(x) BSWAP_32(x)
85
86 typedef uint8_t u8;
87 typedef uint16_t u16;
88 typedef uint32_t u32;
89 typedef uint64_t u64;
90
91 typedef uint8_t __u8;
92 typedef uint16_t __u16;
93 typedef uint32_t __u32;
94 typedef uint64_t __u64;
95 typedef uint8_t __be8;
96 typedef uint16_t __be16;
97 typedef uint32_t __be32;
98 typedef uint64_t __be64;
99
100 typedef uint32_t __le32;
101
102 typedef int8_t s8;
103 typedef int16_t s16;
104 typedef int32_t s32;
105 typedef int64_t s64;
106
107 #if defined(__sparc)
108 #define __BIG_ENDIAN_BITFIELD
109 #define PAGE_SIZE 8192
110 #define PAGE_SHIFT 13
111 #else
112 #define __LITTLE_ENDIAN_BITFIELD
113 #define PAGE_SIZE 4096
114 #define PAGE_SHIFT 12
115 #endif
116
117 #define ETH_ALEN 6
118
119 #define isspace(x) ((x) == ' ' || (x) == '\t')
120
121 #ifdef _KERNEL
122
123 #define fls(x) ddi_fls(x)
124
125 static inline int
ilog2(long x)126 ilog2(long x)
127 {
128 return (ddi_fls(x) - 1);
129 }
130
131 typedef kmutex_t t4_os_lock_t;
132
133 /*
134 * The common code reaches directly into the adapter flags, so we must conform
135 * our prefix in order to meet its expectations.
136 */
137 #define FW_OK TAF_FW_OK
138
139 /* Exposed by t4_nexus.c */
140 struct adapter;
141
142 int t4_os_find_pci_capability(struct adapter *, uint8_t);
143 void t4_os_portmod_changed(struct adapter *, int);
144 void t4_os_set_hw_addr(struct adapter *, int, const uint8_t *);
145
146 #endif /* _KERNEL */
147
148 #endif /* __CXGBE_OSDEP_H */
149