1 /******************************************************************************
2 *
3 * Name : sky2.c
4 * Project: Gigabit Ethernet Driver for FreeBSD 5.x/6.x
5 * Version: $Revision: 1.23 $
6 * Date : $Date: 2005/12/22 09:04:11 $
7 * Purpose: Main driver source file
8 *
9 *****************************************************************************/
10
11 /******************************************************************************
12 *
13 * LICENSE:
14 * Copyright (C) Marvell International Ltd. and/or its affiliates
15 *
16 * The computer program files contained in this folder ("Files")
17 * are provided to you under the BSD-type license terms provided
18 * below, and any use of such Files and any derivative works
19 * thereof created by you shall be governed by the following terms
20 * and conditions:
21 *
22 * - Redistributions of source code must retain the above copyright
23 * notice, this list of conditions and the following disclaimer.
24 * - Redistributions in binary form must reproduce the above
25 * copyright notice, this list of conditions and the following
26 * disclaimer in the documentation and/or other materials provided
27 * with the distribution.
28 * - Neither the name of Marvell nor the names of its contributors
29 * may be used to endorse or promote products derived from this
30 * software without specific prior written permission.
31 *
32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
33 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
34 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
35 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
36 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
37 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
38 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
39 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
41 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
42 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
43 * OF THE POSSIBILITY OF SUCH DAMAGE.
44 * /LICENSE
45 *
46 *****************************************************************************/
47
48 /*-
49 * SPDX-License-Identifier: BSD-4-Clause AND BSD-3-Clause
50 *
51 * Copyright (c) 1997, 1998, 1999, 2000
52 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
53 *
54 * Redistribution and use in source and binary forms, with or without
55 * modification, are permitted provided that the following conditions
56 * are met:
57 * 1. Redistributions of source code must retain the above copyright
58 * notice, this list of conditions and the following disclaimer.
59 * 2. Redistributions in binary form must reproduce the above copyright
60 * notice, this list of conditions and the following disclaimer in the
61 * documentation and/or other materials provided with the distribution.
62 * 3. All advertising materials mentioning features or use of this software
63 * must display the following acknowledgement:
64 * This product includes software developed by Bill Paul.
65 * 4. Neither the name of the author nor the names of any co-contributors
66 * may be used to endorse or promote products derived from this software
67 * without specific prior written permission.
68 *
69 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
70 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
71 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
72 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
73 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
74 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
75 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
76 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
77 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
78 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
79 * THE POSSIBILITY OF SUCH DAMAGE.
80 */
81 /*-
82 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu>
83 *
84 * Permission to use, copy, modify, and distribute this software for any
85 * purpose with or without fee is hereby granted, provided that the above
86 * copyright notice and this permission notice appear in all copies.
87 *
88 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
89 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
90 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
91 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
92 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
93 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
94 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
95 */
96
97 /*
98 * Device driver for the Marvell Yukon II Ethernet controller.
99 * Due to lack of documentation, this driver is based on the code from
100 * sk(4) and Marvell's myk(4) driver for FreeBSD 5.x.
101 */
102
103 #include <sys/param.h>
104 #include <sys/systm.h>
105 #include <sys/bus.h>
106 #include <sys/endian.h>
107 #include <sys/mbuf.h>
108 #include <sys/malloc.h>
109 #include <sys/kernel.h>
110 #include <sys/module.h>
111 #include <sys/socket.h>
112 #include <sys/sockio.h>
113 #include <sys/queue.h>
114 #include <sys/sysctl.h>
115
116 #include <net/bpf.h>
117 #include <net/ethernet.h>
118 #include <net/if.h>
119 #include <net/if_var.h>
120 #include <net/if_arp.h>
121 #include <net/if_dl.h>
122 #include <net/if_media.h>
123 #include <net/if_types.h>
124 #include <net/if_vlan_var.h>
125
126 #include <netinet/in.h>
127 #include <netinet/in_systm.h>
128 #include <netinet/ip.h>
129 #include <netinet/tcp.h>
130 #include <netinet/udp.h>
131
132 #include <machine/bus.h>
133 #include <machine/in_cksum.h>
134 #include <machine/resource.h>
135 #include <sys/rman.h>
136
137 #include <dev/mii/mii.h>
138 #include <dev/mii/miivar.h>
139
140 #include <dev/pci/pcireg.h>
141 #include <dev/pci/pcivar.h>
142
143 #include <dev/msk/if_mskreg.h>
144
145 MODULE_DEPEND(msk, pci, 1, 1, 1);
146 MODULE_DEPEND(msk, ether, 1, 1, 1);
147 MODULE_DEPEND(msk, miibus, 1, 1, 1);
148
149 /* "device miibus" required. See GENERIC if you get errors here. */
150 #include "miibus_if.h"
151
152 /* Tunables. */
153 static int msi_disable = 0;
154 TUNABLE_INT("hw.msk.msi_disable", &msi_disable);
155 static int legacy_intr = 0;
156 TUNABLE_INT("hw.msk.legacy_intr", &legacy_intr);
157 static int jumbo_disable = 0;
158 TUNABLE_INT("hw.msk.jumbo_disable", &jumbo_disable);
159
160 #define MSK_CSUM_FEATURES (CSUM_TCP | CSUM_UDP)
161
162 /*
163 * Devices supported by this driver.
164 */
165 static const struct msk_product {
166 uint16_t msk_vendorid;
167 uint16_t msk_deviceid;
168 const char *msk_name;
169 } msk_products[] = {
170 { VENDORID_SK, DEVICEID_SK_YUKON2,
171 "SK-9Sxx Gigabit Ethernet" },
172 { VENDORID_SK, DEVICEID_SK_YUKON2_EXPR,
173 "SK-9Exx Gigabit Ethernet"},
174 { VENDORID_MARVELL, DEVICEID_MRVL_8021CU,
175 "Marvell Yukon 88E8021CU Gigabit Ethernet" },
176 { VENDORID_MARVELL, DEVICEID_MRVL_8021X,
177 "Marvell Yukon 88E8021 SX/LX Gigabit Ethernet" },
178 { VENDORID_MARVELL, DEVICEID_MRVL_8022CU,
179 "Marvell Yukon 88E8022CU Gigabit Ethernet" },
180 { VENDORID_MARVELL, DEVICEID_MRVL_8022X,
181 "Marvell Yukon 88E8022 SX/LX Gigabit Ethernet" },
182 { VENDORID_MARVELL, DEVICEID_MRVL_8061CU,
183 "Marvell Yukon 88E8061CU Gigabit Ethernet" },
184 { VENDORID_MARVELL, DEVICEID_MRVL_8061X,
185 "Marvell Yukon 88E8061 SX/LX Gigabit Ethernet" },
186 { VENDORID_MARVELL, DEVICEID_MRVL_8062CU,
187 "Marvell Yukon 88E8062CU Gigabit Ethernet" },
188 { VENDORID_MARVELL, DEVICEID_MRVL_8062X,
189 "Marvell Yukon 88E8062 SX/LX Gigabit Ethernet" },
190 { VENDORID_MARVELL, DEVICEID_MRVL_8035,
191 "Marvell Yukon 88E8035 Fast Ethernet" },
192 { VENDORID_MARVELL, DEVICEID_MRVL_8036,
193 "Marvell Yukon 88E8036 Fast Ethernet" },
194 { VENDORID_MARVELL, DEVICEID_MRVL_8038,
195 "Marvell Yukon 88E8038 Fast Ethernet" },
196 { VENDORID_MARVELL, DEVICEID_MRVL_8039,
197 "Marvell Yukon 88E8039 Fast Ethernet" },
198 { VENDORID_MARVELL, DEVICEID_MRVL_8040,
199 "Marvell Yukon 88E8040 Fast Ethernet" },
200 { VENDORID_MARVELL, DEVICEID_MRVL_8040T,
201 "Marvell Yukon 88E8040T Fast Ethernet" },
202 { VENDORID_MARVELL, DEVICEID_MRVL_8042,
203 "Marvell Yukon 88E8042 Fast Ethernet" },
204 { VENDORID_MARVELL, DEVICEID_MRVL_8048,
205 "Marvell Yukon 88E8048 Fast Ethernet" },
206 { VENDORID_MARVELL, DEVICEID_MRVL_4361,
207 "Marvell Yukon 88E8050 Gigabit Ethernet" },
208 { VENDORID_MARVELL, DEVICEID_MRVL_4360,
209 "Marvell Yukon 88E8052 Gigabit Ethernet" },
210 { VENDORID_MARVELL, DEVICEID_MRVL_4362,
211 "Marvell Yukon 88E8053 Gigabit Ethernet" },
212 { VENDORID_MARVELL, DEVICEID_MRVL_4363,
213 "Marvell Yukon 88E8055 Gigabit Ethernet" },
214 { VENDORID_MARVELL, DEVICEID_MRVL_4364,
215 "Marvell Yukon 88E8056 Gigabit Ethernet" },
216 { VENDORID_MARVELL, DEVICEID_MRVL_4365,
217 "Marvell Yukon 88E8070 Gigabit Ethernet" },
218 { VENDORID_MARVELL, DEVICEID_MRVL_436A,
219 "Marvell Yukon 88E8058 Gigabit Ethernet" },
220 { VENDORID_MARVELL, DEVICEID_MRVL_436B,
221 "Marvell Yukon 88E8071 Gigabit Ethernet" },
222 { VENDORID_MARVELL, DEVICEID_MRVL_436C,
223 "Marvell Yukon 88E8072 Gigabit Ethernet" },
224 { VENDORID_MARVELL, DEVICEID_MRVL_436D,
225 "Marvell Yukon 88E8055 Gigabit Ethernet" },
226 { VENDORID_MARVELL, DEVICEID_MRVL_4370,
227 "Marvell Yukon 88E8075 Gigabit Ethernet" },
228 { VENDORID_MARVELL, DEVICEID_MRVL_4380,
229 "Marvell Yukon 88E8057 Gigabit Ethernet" },
230 { VENDORID_MARVELL, DEVICEID_MRVL_4381,
231 "Marvell Yukon 88E8059 Gigabit Ethernet" },
232 { VENDORID_DLINK, DEVICEID_DLINK_DGE550SX,
233 "D-Link 550SX Gigabit Ethernet" },
234 { VENDORID_DLINK, DEVICEID_DLINK_DGE560SX,
235 "D-Link 560SX Gigabit Ethernet" },
236 { VENDORID_DLINK, DEVICEID_DLINK_DGE560T,
237 "D-Link 560T Gigabit Ethernet" }
238 };
239
240 static const char *model_name[] = {
241 "Yukon XL",
242 "Yukon EC Ultra",
243 "Yukon EX",
244 "Yukon EC",
245 "Yukon FE",
246 "Yukon FE+",
247 "Yukon Supreme",
248 "Yukon Ultra 2",
249 "Yukon Unknown",
250 "Yukon Optima",
251 };
252
253 static int mskc_probe(device_t);
254 static int mskc_attach(device_t);
255 static void mskc_child_deleted(device_t, device_t);
256 static int mskc_detach(device_t);
257 static int mskc_shutdown(device_t);
258 static int mskc_setup_rambuffer(struct msk_softc *);
259 static int mskc_suspend(device_t);
260 static int mskc_resume(device_t);
261 static bus_dma_tag_t mskc_get_dma_tag(device_t, device_t);
262 static void mskc_reset(struct msk_softc *);
263
264 static int msk_probe(device_t);
265 static int msk_attach(device_t);
266 static int msk_detach(device_t);
267
268 static void msk_tick(void *);
269 static void msk_intr(void *);
270 static void msk_intr_phy(struct msk_if_softc *);
271 static void msk_intr_gmac(struct msk_if_softc *);
272 static __inline void msk_rxput(struct msk_if_softc *);
273 static int msk_handle_events(struct msk_softc *);
274 static void msk_handle_hwerr(struct msk_if_softc *, uint32_t);
275 static void msk_intr_hwerr(struct msk_softc *);
276 #ifndef __NO_STRICT_ALIGNMENT
277 static __inline void msk_fixup_rx(struct mbuf *);
278 #endif
279 static __inline void msk_rxcsum(struct msk_if_softc *, uint32_t, struct mbuf *);
280 static void msk_rxeof(struct msk_if_softc *, uint32_t, uint32_t, int);
281 static void msk_jumbo_rxeof(struct msk_if_softc *, uint32_t, uint32_t, int);
282 static void msk_txeof(struct msk_if_softc *, int);
283 static int msk_encap(struct msk_if_softc *, struct mbuf **);
284 static void msk_start(if_t);
285 static void msk_start_locked(if_t);
286 static int msk_ioctl(if_t, u_long, caddr_t);
287 static void msk_set_prefetch(struct msk_softc *, int, bus_addr_t, uint32_t);
288 static void msk_set_rambuffer(struct msk_if_softc *);
289 static void msk_set_tx_stfwd(struct msk_if_softc *);
290 static void msk_init(void *);
291 static void msk_init_locked(struct msk_if_softc *);
292 static void msk_stop(struct msk_if_softc *);
293 static void msk_watchdog(struct msk_if_softc *);
294 static int msk_mediachange(if_t);
295 static void msk_mediastatus(if_t, struct ifmediareq *);
296 static void msk_phy_power(struct msk_softc *, int);
297 static void msk_dmamap_cb(void *, bus_dma_segment_t *, int, int);
298 static int msk_status_dma_alloc(struct msk_softc *);
299 static void msk_status_dma_free(struct msk_softc *);
300 static int msk_txrx_dma_alloc(struct msk_if_softc *);
301 static int msk_rx_dma_jalloc(struct msk_if_softc *);
302 static void msk_txrx_dma_free(struct msk_if_softc *);
303 static void msk_rx_dma_jfree(struct msk_if_softc *);
304 static int msk_rx_fill(struct msk_if_softc *, int);
305 static int msk_init_rx_ring(struct msk_if_softc *);
306 static int msk_init_jumbo_rx_ring(struct msk_if_softc *);
307 static void msk_init_tx_ring(struct msk_if_softc *);
308 static __inline void msk_discard_rxbuf(struct msk_if_softc *, int);
309 static __inline void msk_discard_jumbo_rxbuf(struct msk_if_softc *, int);
310 static int msk_newbuf(struct msk_if_softc *, int);
311 static int msk_jumbo_newbuf(struct msk_if_softc *, int);
312
313 static int msk_phy_readreg(struct msk_if_softc *, int, int);
314 static int msk_phy_writereg(struct msk_if_softc *, int, int, int);
315 static int msk_miibus_readreg(device_t, int, int);
316 static int msk_miibus_writereg(device_t, int, int, int);
317 static void msk_miibus_statchg(device_t);
318
319 static void msk_rxfilter(struct msk_if_softc *);
320 static void msk_setvlan(struct msk_if_softc *, if_t);
321
322 static void msk_stats_clear(struct msk_if_softc *);
323 static void msk_stats_update(struct msk_if_softc *);
324 static int msk_sysctl_stat32(SYSCTL_HANDLER_ARGS);
325 static int msk_sysctl_stat64(SYSCTL_HANDLER_ARGS);
326 static void msk_sysctl_node(struct msk_if_softc *);
327 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int);
328 static int sysctl_hw_msk_proc_limit(SYSCTL_HANDLER_ARGS);
329
330 static device_method_t mskc_methods[] = {
331 /* Device interface */
332 DEVMETHOD(device_probe, mskc_probe),
333 DEVMETHOD(device_attach, mskc_attach),
334 DEVMETHOD(device_detach, mskc_detach),
335 DEVMETHOD(device_suspend, mskc_suspend),
336 DEVMETHOD(device_resume, mskc_resume),
337 DEVMETHOD(device_shutdown, mskc_shutdown),
338
339 DEVMETHOD(bus_child_deleted, mskc_child_deleted),
340 DEVMETHOD(bus_get_dma_tag, mskc_get_dma_tag),
341
342 DEVMETHOD_END
343 };
344
345 static driver_t mskc_driver = {
346 "mskc",
347 mskc_methods,
348 sizeof(struct msk_softc)
349 };
350
351 static device_method_t msk_methods[] = {
352 /* Device interface */
353 DEVMETHOD(device_probe, msk_probe),
354 DEVMETHOD(device_attach, msk_attach),
355 DEVMETHOD(device_detach, msk_detach),
356 DEVMETHOD(device_shutdown, bus_generic_shutdown),
357
358 /* MII interface */
359 DEVMETHOD(miibus_readreg, msk_miibus_readreg),
360 DEVMETHOD(miibus_writereg, msk_miibus_writereg),
361 DEVMETHOD(miibus_statchg, msk_miibus_statchg),
362
363 DEVMETHOD_END
364 };
365
366 static driver_t msk_driver = {
367 "msk",
368 msk_methods,
369 sizeof(struct msk_if_softc)
370 };
371
372 DRIVER_MODULE(mskc, pci, mskc_driver, NULL, NULL);
373 DRIVER_MODULE(msk, mskc, msk_driver, NULL, NULL);
374 DRIVER_MODULE(miibus, msk, miibus_driver, NULL, NULL);
375
376 static struct resource_spec msk_res_spec_io[] = {
377 { SYS_RES_IOPORT, PCIR_BAR(1), RF_ACTIVE },
378 { -1, 0, 0 }
379 };
380
381 static struct resource_spec msk_res_spec_mem[] = {
382 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE },
383 { -1, 0, 0 }
384 };
385
386 static struct resource_spec msk_irq_spec_legacy[] = {
387 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
388 { -1, 0, 0 }
389 };
390
391 static struct resource_spec msk_irq_spec_msi[] = {
392 { SYS_RES_IRQ, 1, RF_ACTIVE },
393 { -1, 0, 0 }
394 };
395
396 static int
msk_miibus_readreg(device_t dev,int phy,int reg)397 msk_miibus_readreg(device_t dev, int phy, int reg)
398 {
399 struct msk_if_softc *sc_if;
400
401 sc_if = device_get_softc(dev);
402
403 return (msk_phy_readreg(sc_if, phy, reg));
404 }
405
406 static int
msk_phy_readreg(struct msk_if_softc * sc_if,int phy,int reg)407 msk_phy_readreg(struct msk_if_softc *sc_if, int phy, int reg)
408 {
409 struct msk_softc *sc;
410 int i, val;
411
412 sc = sc_if->msk_softc;
413
414 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_CTRL,
415 GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
416
417 for (i = 0; i < MSK_TIMEOUT; i++) {
418 DELAY(1);
419 val = GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_CTRL);
420 if ((val & GM_SMI_CT_RD_VAL) != 0) {
421 val = GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_DATA);
422 break;
423 }
424 }
425
426 if (i == MSK_TIMEOUT) {
427 if_printf(sc_if->msk_ifp, "phy failed to come ready\n");
428 val = 0;
429 }
430
431 return (val);
432 }
433
434 static int
msk_miibus_writereg(device_t dev,int phy,int reg,int val)435 msk_miibus_writereg(device_t dev, int phy, int reg, int val)
436 {
437 struct msk_if_softc *sc_if;
438
439 sc_if = device_get_softc(dev);
440
441 return (msk_phy_writereg(sc_if, phy, reg, val));
442 }
443
444 static int
msk_phy_writereg(struct msk_if_softc * sc_if,int phy,int reg,int val)445 msk_phy_writereg(struct msk_if_softc *sc_if, int phy, int reg, int val)
446 {
447 struct msk_softc *sc;
448 int i;
449
450 sc = sc_if->msk_softc;
451
452 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_DATA, val);
453 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_CTRL,
454 GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg));
455 for (i = 0; i < MSK_TIMEOUT; i++) {
456 DELAY(1);
457 if ((GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_CTRL) &
458 GM_SMI_CT_BUSY) == 0)
459 break;
460 }
461 if (i == MSK_TIMEOUT)
462 if_printf(sc_if->msk_ifp, "phy write timeout\n");
463
464 return (0);
465 }
466
467 static void
msk_miibus_statchg(device_t dev)468 msk_miibus_statchg(device_t dev)
469 {
470 struct msk_softc *sc;
471 struct msk_if_softc *sc_if;
472 struct mii_data *mii;
473 if_t ifp;
474 uint32_t gmac;
475
476 sc_if = device_get_softc(dev);
477 sc = sc_if->msk_softc;
478
479 MSK_IF_LOCK_ASSERT(sc_if);
480
481 mii = device_get_softc(sc_if->msk_miibus);
482 ifp = sc_if->msk_ifp;
483 if (mii == NULL || ifp == NULL ||
484 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0)
485 return;
486
487 sc_if->msk_flags &= ~MSK_FLAG_LINK;
488 if ((mii->mii_media_status & (IFM_AVALID | IFM_ACTIVE)) ==
489 (IFM_AVALID | IFM_ACTIVE)) {
490 switch (IFM_SUBTYPE(mii->mii_media_active)) {
491 case IFM_10_T:
492 case IFM_100_TX:
493 sc_if->msk_flags |= MSK_FLAG_LINK;
494 break;
495 case IFM_1000_T:
496 case IFM_1000_SX:
497 case IFM_1000_LX:
498 case IFM_1000_CX:
499 if ((sc_if->msk_flags & MSK_FLAG_FASTETHER) == 0)
500 sc_if->msk_flags |= MSK_FLAG_LINK;
501 break;
502 default:
503 break;
504 }
505 }
506
507 if ((sc_if->msk_flags & MSK_FLAG_LINK) != 0) {
508 /* Enable Tx FIFO Underrun. */
509 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_MSK),
510 GM_IS_TX_FF_UR | GM_IS_RX_FF_OR);
511 /*
512 * Because mii(4) notify msk(4) that it detected link status
513 * change, there is no need to enable automatic
514 * speed/flow-control/duplex updates.
515 */
516 gmac = GM_GPCR_AU_ALL_DIS;
517 switch (IFM_SUBTYPE(mii->mii_media_active)) {
518 case IFM_1000_SX:
519 case IFM_1000_T:
520 gmac |= GM_GPCR_SPEED_1000;
521 break;
522 case IFM_100_TX:
523 gmac |= GM_GPCR_SPEED_100;
524 break;
525 case IFM_10_T:
526 break;
527 }
528
529 if ((IFM_OPTIONS(mii->mii_media_active) &
530 IFM_ETH_RXPAUSE) == 0)
531 gmac |= GM_GPCR_FC_RX_DIS;
532 if ((IFM_OPTIONS(mii->mii_media_active) &
533 IFM_ETH_TXPAUSE) == 0)
534 gmac |= GM_GPCR_FC_TX_DIS;
535 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0)
536 gmac |= GM_GPCR_DUP_FULL;
537 else
538 gmac |= GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS;
539 gmac |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
540 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac);
541 /* Read again to ensure writing. */
542 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL);
543 gmac = GMC_PAUSE_OFF;
544 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
545 if ((IFM_OPTIONS(mii->mii_media_active) &
546 IFM_ETH_RXPAUSE) != 0)
547 gmac = GMC_PAUSE_ON;
548 }
549 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), gmac);
550
551 /* Enable PHY interrupt for FIFO underrun/overflow. */
552 msk_phy_writereg(sc_if, PHY_ADDR_MARV,
553 PHY_MARV_INT_MASK, PHY_M_IS_FIFO_ERROR);
554 } else {
555 /*
556 * Link state changed to down.
557 * Disable PHY interrupts.
558 */
559 msk_phy_writereg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_MASK, 0);
560 /* Disable Rx/Tx MAC. */
561 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL);
562 if ((gmac & (GM_GPCR_RX_ENA | GM_GPCR_TX_ENA)) != 0) {
563 gmac &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
564 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac);
565 /* Read again to ensure writing. */
566 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL);
567 }
568 }
569 }
570
571 static u_int
msk_hash_maddr(void * arg,struct sockaddr_dl * sdl,u_int cnt)572 msk_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
573 {
574 uint32_t *mchash = arg;
575 uint32_t crc;
576
577 crc = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN);
578 /* Just want the 6 least significant bits. */
579 crc &= 0x3f;
580 /* Set the corresponding bit in the hash table. */
581 mchash[crc >> 5] |= 1 << (crc & 0x1f);
582
583 return (1);
584 }
585
586 static void
msk_rxfilter(struct msk_if_softc * sc_if)587 msk_rxfilter(struct msk_if_softc *sc_if)
588 {
589 struct msk_softc *sc;
590 if_t ifp;
591 uint32_t mchash[2];
592 uint16_t mode;
593
594 sc = sc_if->msk_softc;
595
596 MSK_IF_LOCK_ASSERT(sc_if);
597
598 ifp = sc_if->msk_ifp;
599
600 bzero(mchash, sizeof(mchash));
601 mode = GMAC_READ_2(sc, sc_if->msk_port, GM_RX_CTRL);
602 if ((if_getflags(ifp) & IFF_PROMISC) != 0)
603 mode &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
604 else if ((if_getflags(ifp) & IFF_ALLMULTI) != 0) {
605 mode |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
606 mchash[0] = 0xffff;
607 mchash[1] = 0xffff;
608 } else {
609 mode |= GM_RXCR_UCF_ENA;
610 if_foreach_llmaddr(ifp, msk_hash_maddr, mchash);
611 if (mchash[0] != 0 || mchash[1] != 0)
612 mode |= GM_RXCR_MCF_ENA;
613 }
614
615 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H1,
616 mchash[0] & 0xffff);
617 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H2,
618 (mchash[0] >> 16) & 0xffff);
619 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H3,
620 mchash[1] & 0xffff);
621 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H4,
622 (mchash[1] >> 16) & 0xffff);
623 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, mode);
624 }
625
626 static void
msk_setvlan(struct msk_if_softc * sc_if,if_t ifp)627 msk_setvlan(struct msk_if_softc *sc_if, if_t ifp)
628 {
629 struct msk_softc *sc;
630
631 sc = sc_if->msk_softc;
632 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) {
633 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T),
634 RX_VLAN_STRIP_ON);
635 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
636 TX_VLAN_TAG_ON);
637 } else {
638 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T),
639 RX_VLAN_STRIP_OFF);
640 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
641 TX_VLAN_TAG_OFF);
642 }
643 }
644
645 static int
msk_rx_fill(struct msk_if_softc * sc_if,int jumbo)646 msk_rx_fill(struct msk_if_softc *sc_if, int jumbo)
647 {
648 uint16_t idx;
649 int i;
650
651 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 &&
652 (if_getcapenable(sc_if->msk_ifp) & IFCAP_RXCSUM) != 0) {
653 /* Wait until controller executes OP_TCPSTART command. */
654 for (i = 100; i > 0; i--) {
655 DELAY(100);
656 idx = CSR_READ_2(sc_if->msk_softc,
657 Y2_PREF_Q_ADDR(sc_if->msk_rxq,
658 PREF_UNIT_GET_IDX_REG));
659 if (idx != 0)
660 break;
661 }
662 if (i == 0) {
663 device_printf(sc_if->msk_if_dev,
664 "prefetch unit stuck?\n");
665 return (ETIMEDOUT);
666 }
667 /*
668 * Fill consumed LE with free buffer. This can be done
669 * in Rx handler but we don't want to add special code
670 * in fast handler.
671 */
672 if (jumbo > 0) {
673 if (msk_jumbo_newbuf(sc_if, 0) != 0)
674 return (ENOBUFS);
675 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_ring_tag,
676 sc_if->msk_cdata.msk_jumbo_rx_ring_map,
677 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
678 } else {
679 if (msk_newbuf(sc_if, 0) != 0)
680 return (ENOBUFS);
681 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_ring_tag,
682 sc_if->msk_cdata.msk_rx_ring_map,
683 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
684 }
685 sc_if->msk_cdata.msk_rx_prod = 0;
686 CSR_WRITE_2(sc_if->msk_softc,
687 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG),
688 sc_if->msk_cdata.msk_rx_prod);
689 }
690 return (0);
691 }
692
693 static int
msk_init_rx_ring(struct msk_if_softc * sc_if)694 msk_init_rx_ring(struct msk_if_softc *sc_if)
695 {
696 struct msk_ring_data *rd;
697 struct msk_rxdesc *rxd;
698 int i, nbuf, prod;
699
700 MSK_IF_LOCK_ASSERT(sc_if);
701
702 sc_if->msk_cdata.msk_rx_cons = 0;
703 sc_if->msk_cdata.msk_rx_prod = 0;
704 sc_if->msk_cdata.msk_rx_putwm = MSK_PUT_WM;
705
706 rd = &sc_if->msk_rdata;
707 bzero(rd->msk_rx_ring, sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT);
708 for (i = prod = 0; i < MSK_RX_RING_CNT; i++) {
709 rxd = &sc_if->msk_cdata.msk_rxdesc[prod];
710 rxd->rx_m = NULL;
711 rxd->rx_le = &rd->msk_rx_ring[prod];
712 MSK_INC(prod, MSK_RX_RING_CNT);
713 }
714 nbuf = MSK_RX_BUF_CNT;
715 prod = 0;
716 /* Have controller know how to compute Rx checksum. */
717 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 &&
718 (if_getcapenable(sc_if->msk_ifp) & IFCAP_RXCSUM) != 0) {
719 #ifdef MSK_64BIT_DMA
720 rxd = &sc_if->msk_cdata.msk_rxdesc[prod];
721 rxd->rx_m = NULL;
722 rxd->rx_le = &rd->msk_rx_ring[prod];
723 rxd->rx_le->msk_addr = htole32(ETHER_HDR_LEN << 16 |
724 ETHER_HDR_LEN);
725 rxd->rx_le->msk_control = htole32(OP_TCPSTART | HW_OWNER);
726 MSK_INC(prod, MSK_RX_RING_CNT);
727 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_RX_RING_CNT);
728 #endif
729 rxd = &sc_if->msk_cdata.msk_rxdesc[prod];
730 rxd->rx_m = NULL;
731 rxd->rx_le = &rd->msk_rx_ring[prod];
732 rxd->rx_le->msk_addr = htole32(ETHER_HDR_LEN << 16 |
733 ETHER_HDR_LEN);
734 rxd->rx_le->msk_control = htole32(OP_TCPSTART | HW_OWNER);
735 MSK_INC(prod, MSK_RX_RING_CNT);
736 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_RX_RING_CNT);
737 nbuf--;
738 }
739 for (i = 0; i < nbuf; i++) {
740 if (msk_newbuf(sc_if, prod) != 0)
741 return (ENOBUFS);
742 MSK_RX_INC(prod, MSK_RX_RING_CNT);
743 }
744
745 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_ring_tag,
746 sc_if->msk_cdata.msk_rx_ring_map,
747 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
748
749 /* Update prefetch unit. */
750 sc_if->msk_cdata.msk_rx_prod = prod;
751 CSR_WRITE_2(sc_if->msk_softc,
752 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG),
753 (sc_if->msk_cdata.msk_rx_prod + MSK_RX_RING_CNT - 1) %
754 MSK_RX_RING_CNT);
755 if (msk_rx_fill(sc_if, 0) != 0)
756 return (ENOBUFS);
757 return (0);
758 }
759
760 static int
msk_init_jumbo_rx_ring(struct msk_if_softc * sc_if)761 msk_init_jumbo_rx_ring(struct msk_if_softc *sc_if)
762 {
763 struct msk_ring_data *rd;
764 struct msk_rxdesc *rxd;
765 int i, nbuf, prod;
766
767 MSK_IF_LOCK_ASSERT(sc_if);
768
769 sc_if->msk_cdata.msk_rx_cons = 0;
770 sc_if->msk_cdata.msk_rx_prod = 0;
771 sc_if->msk_cdata.msk_rx_putwm = MSK_PUT_WM;
772
773 rd = &sc_if->msk_rdata;
774 bzero(rd->msk_jumbo_rx_ring,
775 sizeof(struct msk_rx_desc) * MSK_JUMBO_RX_RING_CNT);
776 for (i = prod = 0; i < MSK_JUMBO_RX_RING_CNT; i++) {
777 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[prod];
778 rxd->rx_m = NULL;
779 rxd->rx_le = &rd->msk_jumbo_rx_ring[prod];
780 MSK_INC(prod, MSK_JUMBO_RX_RING_CNT);
781 }
782 nbuf = MSK_RX_BUF_CNT;
783 prod = 0;
784 /* Have controller know how to compute Rx checksum. */
785 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 &&
786 (if_getcapenable(sc_if->msk_ifp) & IFCAP_RXCSUM) != 0) {
787 #ifdef MSK_64BIT_DMA
788 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[prod];
789 rxd->rx_m = NULL;
790 rxd->rx_le = &rd->msk_jumbo_rx_ring[prod];
791 rxd->rx_le->msk_addr = htole32(ETHER_HDR_LEN << 16 |
792 ETHER_HDR_LEN);
793 rxd->rx_le->msk_control = htole32(OP_TCPSTART | HW_OWNER);
794 MSK_INC(prod, MSK_JUMBO_RX_RING_CNT);
795 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_JUMBO_RX_RING_CNT);
796 #endif
797 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[prod];
798 rxd->rx_m = NULL;
799 rxd->rx_le = &rd->msk_jumbo_rx_ring[prod];
800 rxd->rx_le->msk_addr = htole32(ETHER_HDR_LEN << 16 |
801 ETHER_HDR_LEN);
802 rxd->rx_le->msk_control = htole32(OP_TCPSTART | HW_OWNER);
803 MSK_INC(prod, MSK_JUMBO_RX_RING_CNT);
804 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_JUMBO_RX_RING_CNT);
805 nbuf--;
806 }
807 for (i = 0; i < nbuf; i++) {
808 if (msk_jumbo_newbuf(sc_if, prod) != 0)
809 return (ENOBUFS);
810 MSK_RX_INC(prod, MSK_JUMBO_RX_RING_CNT);
811 }
812
813 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_ring_tag,
814 sc_if->msk_cdata.msk_jumbo_rx_ring_map,
815 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
816
817 /* Update prefetch unit. */
818 sc_if->msk_cdata.msk_rx_prod = prod;
819 CSR_WRITE_2(sc_if->msk_softc,
820 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG),
821 (sc_if->msk_cdata.msk_rx_prod + MSK_JUMBO_RX_RING_CNT - 1) %
822 MSK_JUMBO_RX_RING_CNT);
823 if (msk_rx_fill(sc_if, 1) != 0)
824 return (ENOBUFS);
825 return (0);
826 }
827
828 static void
msk_init_tx_ring(struct msk_if_softc * sc_if)829 msk_init_tx_ring(struct msk_if_softc *sc_if)
830 {
831 struct msk_ring_data *rd;
832 struct msk_txdesc *txd;
833 int i;
834
835 sc_if->msk_cdata.msk_tso_mtu = 0;
836 sc_if->msk_cdata.msk_last_csum = 0;
837 sc_if->msk_cdata.msk_tx_prod = 0;
838 sc_if->msk_cdata.msk_tx_cons = 0;
839 sc_if->msk_cdata.msk_tx_cnt = 0;
840 sc_if->msk_cdata.msk_tx_high_addr = 0;
841
842 rd = &sc_if->msk_rdata;
843 bzero(rd->msk_tx_ring, sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT);
844 for (i = 0; i < MSK_TX_RING_CNT; i++) {
845 txd = &sc_if->msk_cdata.msk_txdesc[i];
846 txd->tx_m = NULL;
847 txd->tx_le = &rd->msk_tx_ring[i];
848 }
849
850 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag,
851 sc_if->msk_cdata.msk_tx_ring_map,
852 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
853 }
854
855 static __inline void
msk_discard_rxbuf(struct msk_if_softc * sc_if,int idx)856 msk_discard_rxbuf(struct msk_if_softc *sc_if, int idx)
857 {
858 struct msk_rx_desc *rx_le;
859 struct msk_rxdesc *rxd;
860 struct mbuf *m;
861
862 #ifdef MSK_64BIT_DMA
863 rxd = &sc_if->msk_cdata.msk_rxdesc[idx];
864 rx_le = rxd->rx_le;
865 rx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER);
866 MSK_INC(idx, MSK_RX_RING_CNT);
867 #endif
868 rxd = &sc_if->msk_cdata.msk_rxdesc[idx];
869 m = rxd->rx_m;
870 rx_le = rxd->rx_le;
871 rx_le->msk_control = htole32(m->m_len | OP_PACKET | HW_OWNER);
872 }
873
874 static __inline void
msk_discard_jumbo_rxbuf(struct msk_if_softc * sc_if,int idx)875 msk_discard_jumbo_rxbuf(struct msk_if_softc *sc_if, int idx)
876 {
877 struct msk_rx_desc *rx_le;
878 struct msk_rxdesc *rxd;
879 struct mbuf *m;
880
881 #ifdef MSK_64BIT_DMA
882 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx];
883 rx_le = rxd->rx_le;
884 rx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER);
885 MSK_INC(idx, MSK_JUMBO_RX_RING_CNT);
886 #endif
887 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx];
888 m = rxd->rx_m;
889 rx_le = rxd->rx_le;
890 rx_le->msk_control = htole32(m->m_len | OP_PACKET | HW_OWNER);
891 }
892
893 static int
msk_newbuf(struct msk_if_softc * sc_if,int idx)894 msk_newbuf(struct msk_if_softc *sc_if, int idx)
895 {
896 struct msk_rx_desc *rx_le;
897 struct msk_rxdesc *rxd;
898 struct mbuf *m;
899 bus_dma_segment_t segs[1];
900 bus_dmamap_t map;
901 int nsegs;
902
903 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
904 if (m == NULL)
905 return (ENOBUFS);
906
907 m->m_len = m->m_pkthdr.len = MCLBYTES;
908 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0)
909 m_adj(m, ETHER_ALIGN);
910 #ifndef __NO_STRICT_ALIGNMENT
911 else
912 m_adj(m, MSK_RX_BUF_ALIGN);
913 #endif
914
915 if (bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_rx_tag,
916 sc_if->msk_cdata.msk_rx_sparemap, m, segs, &nsegs,
917 BUS_DMA_NOWAIT) != 0) {
918 m_freem(m);
919 return (ENOBUFS);
920 }
921 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
922
923 rxd = &sc_if->msk_cdata.msk_rxdesc[idx];
924 #ifdef MSK_64BIT_DMA
925 rx_le = rxd->rx_le;
926 rx_le->msk_addr = htole32(MSK_ADDR_HI(segs[0].ds_addr));
927 rx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER);
928 MSK_INC(idx, MSK_RX_RING_CNT);
929 rxd = &sc_if->msk_cdata.msk_rxdesc[idx];
930 #endif
931 if (rxd->rx_m != NULL) {
932 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap,
933 BUS_DMASYNC_POSTREAD);
934 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap);
935 rxd->rx_m = NULL;
936 }
937 map = rxd->rx_dmamap;
938 rxd->rx_dmamap = sc_if->msk_cdata.msk_rx_sparemap;
939 sc_if->msk_cdata.msk_rx_sparemap = map;
940 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap,
941 BUS_DMASYNC_PREREAD);
942 rxd->rx_m = m;
943 rx_le = rxd->rx_le;
944 rx_le->msk_addr = htole32(MSK_ADDR_LO(segs[0].ds_addr));
945 rx_le->msk_control =
946 htole32(segs[0].ds_len | OP_PACKET | HW_OWNER);
947
948 return (0);
949 }
950
951 static int
msk_jumbo_newbuf(struct msk_if_softc * sc_if,int idx)952 msk_jumbo_newbuf(struct msk_if_softc *sc_if, int idx)
953 {
954 struct msk_rx_desc *rx_le;
955 struct msk_rxdesc *rxd;
956 struct mbuf *m;
957 bus_dma_segment_t segs[1];
958 bus_dmamap_t map;
959 int nsegs;
960
961 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES);
962 if (m == NULL)
963 return (ENOBUFS);
964 m->m_len = m->m_pkthdr.len = MJUM9BYTES;
965 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0)
966 m_adj(m, ETHER_ALIGN);
967 #ifndef __NO_STRICT_ALIGNMENT
968 else
969 m_adj(m, MSK_RX_BUF_ALIGN);
970 #endif
971
972 if (bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_jumbo_rx_tag,
973 sc_if->msk_cdata.msk_jumbo_rx_sparemap, m, segs, &nsegs,
974 BUS_DMA_NOWAIT) != 0) {
975 m_freem(m);
976 return (ENOBUFS);
977 }
978 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
979
980 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx];
981 #ifdef MSK_64BIT_DMA
982 rx_le = rxd->rx_le;
983 rx_le->msk_addr = htole32(MSK_ADDR_HI(segs[0].ds_addr));
984 rx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER);
985 MSK_INC(idx, MSK_JUMBO_RX_RING_CNT);
986 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx];
987 #endif
988 if (rxd->rx_m != NULL) {
989 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag,
990 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
991 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_tag,
992 rxd->rx_dmamap);
993 rxd->rx_m = NULL;
994 }
995 map = rxd->rx_dmamap;
996 rxd->rx_dmamap = sc_if->msk_cdata.msk_jumbo_rx_sparemap;
997 sc_if->msk_cdata.msk_jumbo_rx_sparemap = map;
998 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, rxd->rx_dmamap,
999 BUS_DMASYNC_PREREAD);
1000 rxd->rx_m = m;
1001 rx_le = rxd->rx_le;
1002 rx_le->msk_addr = htole32(MSK_ADDR_LO(segs[0].ds_addr));
1003 rx_le->msk_control =
1004 htole32(segs[0].ds_len | OP_PACKET | HW_OWNER);
1005
1006 return (0);
1007 }
1008
1009 /*
1010 * Set media options.
1011 */
1012 static int
msk_mediachange(if_t ifp)1013 msk_mediachange(if_t ifp)
1014 {
1015 struct msk_if_softc *sc_if;
1016 struct mii_data *mii;
1017 int error;
1018
1019 sc_if = if_getsoftc(ifp);
1020
1021 MSK_IF_LOCK(sc_if);
1022 mii = device_get_softc(sc_if->msk_miibus);
1023 error = mii_mediachg(mii);
1024 MSK_IF_UNLOCK(sc_if);
1025
1026 return (error);
1027 }
1028
1029 /*
1030 * Report current media status.
1031 */
1032 static void
msk_mediastatus(if_t ifp,struct ifmediareq * ifmr)1033 msk_mediastatus(if_t ifp, struct ifmediareq *ifmr)
1034 {
1035 struct msk_if_softc *sc_if;
1036 struct mii_data *mii;
1037
1038 sc_if = if_getsoftc(ifp);
1039 MSK_IF_LOCK(sc_if);
1040 if ((if_getflags(ifp) & IFF_UP) == 0) {
1041 MSK_IF_UNLOCK(sc_if);
1042 return;
1043 }
1044 mii = device_get_softc(sc_if->msk_miibus);
1045
1046 mii_pollstat(mii);
1047 ifmr->ifm_active = mii->mii_media_active;
1048 ifmr->ifm_status = mii->mii_media_status;
1049 MSK_IF_UNLOCK(sc_if);
1050 }
1051
1052 static int
msk_ioctl(if_t ifp,u_long command,caddr_t data)1053 msk_ioctl(if_t ifp, u_long command, caddr_t data)
1054 {
1055 struct msk_if_softc *sc_if;
1056 struct ifreq *ifr;
1057 struct mii_data *mii;
1058 int error, mask, reinit;
1059
1060 sc_if = if_getsoftc(ifp);
1061 ifr = (struct ifreq *)data;
1062 error = 0;
1063
1064 switch(command) {
1065 case SIOCSIFMTU:
1066 MSK_IF_LOCK(sc_if);
1067 if (ifr->ifr_mtu > MSK_JUMBO_MTU || ifr->ifr_mtu < ETHERMIN)
1068 error = EINVAL;
1069 else if (if_getmtu(ifp) != ifr->ifr_mtu) {
1070 if (ifr->ifr_mtu > ETHERMTU) {
1071 if ((sc_if->msk_flags & MSK_FLAG_JUMBO) == 0) {
1072 error = EINVAL;
1073 MSK_IF_UNLOCK(sc_if);
1074 break;
1075 }
1076 if ((sc_if->msk_flags &
1077 MSK_FLAG_JUMBO_NOCSUM) != 0) {
1078 if_sethwassistbits(ifp, 0,
1079 MSK_CSUM_FEATURES | CSUM_TSO);
1080 if_setcapenablebit(ifp, 0,
1081 IFCAP_TSO4 | IFCAP_TXCSUM);
1082 VLAN_CAPABILITIES(ifp);
1083 }
1084 }
1085 if_setmtu(ifp, ifr->ifr_mtu);
1086 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) {
1087 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1088 msk_init_locked(sc_if);
1089 }
1090 }
1091 MSK_IF_UNLOCK(sc_if);
1092 break;
1093 case SIOCSIFFLAGS:
1094 MSK_IF_LOCK(sc_if);
1095 if ((if_getflags(ifp) & IFF_UP) != 0) {
1096 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0 &&
1097 ((if_getflags(ifp) ^ sc_if->msk_if_flags) &
1098 (IFF_PROMISC | IFF_ALLMULTI)) != 0)
1099 msk_rxfilter(sc_if);
1100 else if ((sc_if->msk_flags & MSK_FLAG_DETACH) == 0)
1101 msk_init_locked(sc_if);
1102 } else if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)
1103 msk_stop(sc_if);
1104 sc_if->msk_if_flags = if_getflags(ifp);
1105 MSK_IF_UNLOCK(sc_if);
1106 break;
1107 case SIOCADDMULTI:
1108 case SIOCDELMULTI:
1109 MSK_IF_LOCK(sc_if);
1110 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)
1111 msk_rxfilter(sc_if);
1112 MSK_IF_UNLOCK(sc_if);
1113 break;
1114 case SIOCGIFMEDIA:
1115 case SIOCSIFMEDIA:
1116 mii = device_get_softc(sc_if->msk_miibus);
1117 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1118 break;
1119 case SIOCSIFCAP:
1120 reinit = 0;
1121 MSK_IF_LOCK(sc_if);
1122 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp);
1123 if ((mask & IFCAP_TXCSUM) != 0 &&
1124 (IFCAP_TXCSUM & if_getcapabilities(ifp)) != 0) {
1125 if_togglecapenable(ifp, IFCAP_TXCSUM);
1126 if ((IFCAP_TXCSUM & if_getcapenable(ifp)) != 0)
1127 if_sethwassistbits(ifp, MSK_CSUM_FEATURES, 0);
1128 else
1129 if_sethwassistbits(ifp, 0, MSK_CSUM_FEATURES);
1130 }
1131 if ((mask & IFCAP_RXCSUM) != 0 &&
1132 (IFCAP_RXCSUM & if_getcapabilities(ifp)) != 0) {
1133 if_togglecapenable(ifp, IFCAP_RXCSUM);
1134 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0)
1135 reinit = 1;
1136 }
1137 if ((mask & IFCAP_VLAN_HWCSUM) != 0 &&
1138 (IFCAP_VLAN_HWCSUM & if_getcapabilities(ifp)) != 0)
1139 if_togglecapenable(ifp, IFCAP_VLAN_HWCSUM);
1140 if ((mask & IFCAP_TSO4) != 0 &&
1141 (IFCAP_TSO4 & if_getcapabilities(ifp)) != 0) {
1142 if_togglecapenable(ifp, IFCAP_TSO4);
1143 if ((IFCAP_TSO4 & if_getcapenable(ifp)) != 0)
1144 if_sethwassistbits(ifp, CSUM_TSO, 0);
1145 else
1146 if_sethwassistbits(ifp, 0, CSUM_TSO);
1147 }
1148 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
1149 (IFCAP_VLAN_HWTSO & if_getcapabilities(ifp)) != 0)
1150 if_togglecapenable(ifp, IFCAP_VLAN_HWTSO);
1151 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
1152 (IFCAP_VLAN_HWTAGGING & if_getcapabilities(ifp)) != 0) {
1153 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING);
1154 if ((IFCAP_VLAN_HWTAGGING & if_getcapenable(ifp)) == 0)
1155 if_setcapenablebit(ifp, 0,
1156 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM);
1157 msk_setvlan(sc_if, ifp);
1158 }
1159 if (if_getmtu(ifp) > ETHERMTU &&
1160 (sc_if->msk_flags & MSK_FLAG_JUMBO_NOCSUM) != 0) {
1161 if_sethwassistbits(ifp, 0, (MSK_CSUM_FEATURES | CSUM_TSO));
1162 if_setcapenablebit(ifp, 0, (IFCAP_TSO4 | IFCAP_TXCSUM));
1163 }
1164 VLAN_CAPABILITIES(ifp);
1165 if (reinit > 0 && (if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) {
1166 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1167 msk_init_locked(sc_if);
1168 }
1169 MSK_IF_UNLOCK(sc_if);
1170 break;
1171 default:
1172 error = ether_ioctl(ifp, command, data);
1173 break;
1174 }
1175
1176 return (error);
1177 }
1178
1179 static int
mskc_probe(device_t dev)1180 mskc_probe(device_t dev)
1181 {
1182 const struct msk_product *mp;
1183 uint16_t vendor, devid;
1184 int i;
1185
1186 vendor = pci_get_vendor(dev);
1187 devid = pci_get_device(dev);
1188 mp = msk_products;
1189 for (i = 0; i < nitems(msk_products); i++, mp++) {
1190 if (vendor == mp->msk_vendorid && devid == mp->msk_deviceid) {
1191 device_set_desc(dev, mp->msk_name);
1192 return (BUS_PROBE_DEFAULT);
1193 }
1194 }
1195
1196 return (ENXIO);
1197 }
1198
1199 static int
mskc_setup_rambuffer(struct msk_softc * sc)1200 mskc_setup_rambuffer(struct msk_softc *sc)
1201 {
1202 int next;
1203 int i;
1204
1205 /* Get adapter SRAM size. */
1206 sc->msk_ramsize = CSR_READ_1(sc, B2_E_0) * 4;
1207 if (bootverbose)
1208 device_printf(sc->msk_dev,
1209 "RAM buffer size : %dKB\n", sc->msk_ramsize);
1210 if (sc->msk_ramsize == 0)
1211 return (0);
1212
1213 sc->msk_pflags |= MSK_FLAG_RAMBUF;
1214 /*
1215 * Give receiver 2/3 of memory and round down to the multiple
1216 * of 1024. Tx/Rx RAM buffer size of Yukon II should be multiple
1217 * of 1024.
1218 */
1219 sc->msk_rxqsize = rounddown((sc->msk_ramsize * 1024 * 2) / 3, 1024);
1220 sc->msk_txqsize = (sc->msk_ramsize * 1024) - sc->msk_rxqsize;
1221 for (i = 0, next = 0; i < sc->msk_num_port; i++) {
1222 sc->msk_rxqstart[i] = next;
1223 sc->msk_rxqend[i] = next + sc->msk_rxqsize - 1;
1224 next = sc->msk_rxqend[i] + 1;
1225 sc->msk_txqstart[i] = next;
1226 sc->msk_txqend[i] = next + sc->msk_txqsize - 1;
1227 next = sc->msk_txqend[i] + 1;
1228 if (bootverbose) {
1229 device_printf(sc->msk_dev,
1230 "Port %d : Rx Queue %dKB(0x%08x:0x%08x)\n", i,
1231 sc->msk_rxqsize / 1024, sc->msk_rxqstart[i],
1232 sc->msk_rxqend[i]);
1233 device_printf(sc->msk_dev,
1234 "Port %d : Tx Queue %dKB(0x%08x:0x%08x)\n", i,
1235 sc->msk_txqsize / 1024, sc->msk_txqstart[i],
1236 sc->msk_txqend[i]);
1237 }
1238 }
1239
1240 return (0);
1241 }
1242
1243 static void
msk_phy_power(struct msk_softc * sc,int mode)1244 msk_phy_power(struct msk_softc *sc, int mode)
1245 {
1246 uint32_t our, val;
1247 int i;
1248
1249 switch (mode) {
1250 case MSK_PHY_POWERUP:
1251 /* Switch power to VCC (WA for VAUX problem). */
1252 CSR_WRITE_1(sc, B0_POWER_CTRL,
1253 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
1254 /* Disable Core Clock Division, set Clock Select to 0. */
1255 CSR_WRITE_4(sc, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
1256
1257 val = 0;
1258 if (sc->msk_hw_id == CHIP_ID_YUKON_XL &&
1259 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) {
1260 /* Enable bits are inverted. */
1261 val = Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
1262 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
1263 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS;
1264 }
1265 /*
1266 * Enable PCI & Core Clock, enable clock gating for both Links.
1267 */
1268 CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val);
1269
1270 our = CSR_PCI_READ_4(sc, PCI_OUR_REG_1);
1271 our &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
1272 if (sc->msk_hw_id == CHIP_ID_YUKON_XL) {
1273 if (sc->msk_hw_rev > CHIP_REV_YU_XL_A1) {
1274 /* Deassert Low Power for 1st PHY. */
1275 our |= PCI_Y2_PHY1_COMA;
1276 if (sc->msk_num_port > 1)
1277 our |= PCI_Y2_PHY2_COMA;
1278 }
1279 }
1280 if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U ||
1281 sc->msk_hw_id == CHIP_ID_YUKON_EX ||
1282 sc->msk_hw_id >= CHIP_ID_YUKON_FE_P) {
1283 val = CSR_PCI_READ_4(sc, PCI_OUR_REG_4);
1284 val &= (PCI_FORCE_ASPM_REQUEST |
1285 PCI_ASPM_GPHY_LINK_DOWN | PCI_ASPM_INT_FIFO_EMPTY |
1286 PCI_ASPM_CLKRUN_REQUEST);
1287 /* Set all bits to 0 except bits 15..12. */
1288 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_4, val);
1289 val = CSR_PCI_READ_4(sc, PCI_OUR_REG_5);
1290 val &= PCI_CTL_TIM_VMAIN_AV_MSK;
1291 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_5, val);
1292 CSR_PCI_WRITE_4(sc, PCI_CFG_REG_1, 0);
1293 CSR_WRITE_2(sc, B0_CTST, Y2_HW_WOL_ON);
1294 /*
1295 * Disable status race, workaround for
1296 * Yukon EC Ultra & Yukon EX.
1297 */
1298 val = CSR_READ_4(sc, B2_GP_IO);
1299 val |= GLB_GPIO_STAT_RACE_DIS;
1300 CSR_WRITE_4(sc, B2_GP_IO, val);
1301 CSR_READ_4(sc, B2_GP_IO);
1302 }
1303 /* Release PHY from PowerDown/COMA mode. */
1304 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_1, our);
1305
1306 for (i = 0; i < sc->msk_num_port; i++) {
1307 CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL),
1308 GMLC_RST_SET);
1309 CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL),
1310 GMLC_RST_CLR);
1311 }
1312 break;
1313 case MSK_PHY_POWERDOWN:
1314 val = CSR_PCI_READ_4(sc, PCI_OUR_REG_1);
1315 val |= PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD;
1316 if (sc->msk_hw_id == CHIP_ID_YUKON_XL &&
1317 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) {
1318 val &= ~PCI_Y2_PHY1_COMA;
1319 if (sc->msk_num_port > 1)
1320 val &= ~PCI_Y2_PHY2_COMA;
1321 }
1322 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_1, val);
1323
1324 val = Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
1325 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
1326 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS;
1327 if (sc->msk_hw_id == CHIP_ID_YUKON_XL &&
1328 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) {
1329 /* Enable bits are inverted. */
1330 val = 0;
1331 }
1332 /*
1333 * Disable PCI & Core Clock, disable clock gating for
1334 * both Links.
1335 */
1336 CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val);
1337 CSR_WRITE_1(sc, B0_POWER_CTRL,
1338 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF);
1339 break;
1340 default:
1341 break;
1342 }
1343 }
1344
1345 static void
mskc_reset(struct msk_softc * sc)1346 mskc_reset(struct msk_softc *sc)
1347 {
1348 bus_addr_t addr;
1349 uint16_t status;
1350 uint32_t val;
1351 int i, initram;
1352
1353 /* Disable ASF. */
1354 if (sc->msk_hw_id >= CHIP_ID_YUKON_XL &&
1355 sc->msk_hw_id <= CHIP_ID_YUKON_SUPR) {
1356 if (sc->msk_hw_id == CHIP_ID_YUKON_EX ||
1357 sc->msk_hw_id == CHIP_ID_YUKON_SUPR) {
1358 CSR_WRITE_4(sc, B28_Y2_CPU_WDOG, 0);
1359 status = CSR_READ_2(sc, B28_Y2_ASF_HCU_CCSR);
1360 /* Clear AHB bridge & microcontroller reset. */
1361 status &= ~(Y2_ASF_HCU_CCSR_AHB_RST |
1362 Y2_ASF_HCU_CCSR_CPU_RST_MODE);
1363 /* Clear ASF microcontroller state. */
1364 status &= ~Y2_ASF_HCU_CCSR_UC_STATE_MSK;
1365 status &= ~Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE_MSK;
1366 CSR_WRITE_2(sc, B28_Y2_ASF_HCU_CCSR, status);
1367 CSR_WRITE_4(sc, B28_Y2_CPU_WDOG, 0);
1368 } else
1369 CSR_WRITE_1(sc, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
1370 CSR_WRITE_2(sc, B0_CTST, Y2_ASF_DISABLE);
1371 /*
1372 * Since we disabled ASF, S/W reset is required for
1373 * Power Management.
1374 */
1375 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET);
1376 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR);
1377 }
1378
1379 /* Clear all error bits in the PCI status register. */
1380 status = pci_read_config(sc->msk_dev, PCIR_STATUS, 2);
1381 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON);
1382
1383 pci_write_config(sc->msk_dev, PCIR_STATUS, status |
1384 PCIM_STATUS_PERR | PCIM_STATUS_SERR | PCIM_STATUS_RMABORT |
1385 PCIM_STATUS_RTABORT | PCIM_STATUS_MDPERR, 2);
1386 CSR_WRITE_2(sc, B0_CTST, CS_MRST_CLR);
1387
1388 switch (sc->msk_bustype) {
1389 case MSK_PEX_BUS:
1390 /* Clear all PEX errors. */
1391 CSR_PCI_WRITE_4(sc, PEX_UNC_ERR_STAT, 0xffffffff);
1392 val = CSR_PCI_READ_4(sc, PEX_UNC_ERR_STAT);
1393 if ((val & PEX_RX_OV) != 0) {
1394 sc->msk_intrmask &= ~Y2_IS_HW_ERR;
1395 sc->msk_intrhwemask &= ~Y2_IS_PCI_EXP;
1396 }
1397 break;
1398 case MSK_PCI_BUS:
1399 case MSK_PCIX_BUS:
1400 /* Set Cache Line Size to 2(8bytes) if configured to 0. */
1401 val = pci_read_config(sc->msk_dev, PCIR_CACHELNSZ, 1);
1402 if (val == 0)
1403 pci_write_config(sc->msk_dev, PCIR_CACHELNSZ, 2, 1);
1404 if (sc->msk_bustype == MSK_PCIX_BUS) {
1405 /* Set Cache Line Size opt. */
1406 val = pci_read_config(sc->msk_dev, PCI_OUR_REG_1, 4);
1407 val |= PCI_CLS_OPT;
1408 pci_write_config(sc->msk_dev, PCI_OUR_REG_1, val, 4);
1409 }
1410 break;
1411 }
1412 /* Set PHY power state. */
1413 msk_phy_power(sc, MSK_PHY_POWERUP);
1414
1415 /* Reset GPHY/GMAC Control */
1416 for (i = 0; i < sc->msk_num_port; i++) {
1417 /* GPHY Control reset. */
1418 CSR_WRITE_1(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_SET);
1419 CSR_WRITE_1(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_CLR);
1420 /* GMAC Control reset. */
1421 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_SET);
1422 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_CLR);
1423 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_F_LOOPB_OFF);
1424 if (sc->msk_hw_id == CHIP_ID_YUKON_EX ||
1425 sc->msk_hw_id == CHIP_ID_YUKON_SUPR)
1426 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL),
1427 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON |
1428 GMC_BYP_RETR_ON);
1429 }
1430
1431 if (sc->msk_hw_id == CHIP_ID_YUKON_SUPR &&
1432 sc->msk_hw_rev > CHIP_REV_YU_SU_B0)
1433 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_3, PCI_CLK_MACSEC_DIS);
1434 if (sc->msk_hw_id == CHIP_ID_YUKON_OPT && sc->msk_hw_rev == 0) {
1435 /* Disable PCIe PHY powerdown(reg 0x80, bit7). */
1436 CSR_WRITE_4(sc, Y2_PEX_PHY_DATA, (0x0080 << 16) | 0x0080);
1437 }
1438 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
1439
1440 /* LED On. */
1441 CSR_WRITE_2(sc, B0_CTST, Y2_LED_STAT_ON);
1442
1443 /* Clear TWSI IRQ. */
1444 CSR_WRITE_4(sc, B2_I2C_IRQ, I2C_CLR_IRQ);
1445
1446 /* Turn off hardware timer. */
1447 CSR_WRITE_1(sc, B2_TI_CTRL, TIM_STOP);
1448 CSR_WRITE_1(sc, B2_TI_CTRL, TIM_CLR_IRQ);
1449
1450 /* Turn off descriptor polling. */
1451 CSR_WRITE_1(sc, B28_DPT_CTRL, DPT_STOP);
1452
1453 /* Turn off time stamps. */
1454 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_STOP);
1455 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
1456
1457 initram = 0;
1458 if (sc->msk_hw_id == CHIP_ID_YUKON_XL ||
1459 sc->msk_hw_id == CHIP_ID_YUKON_EC ||
1460 sc->msk_hw_id == CHIP_ID_YUKON_FE)
1461 initram++;
1462
1463 /* Configure timeout values. */
1464 for (i = 0; initram > 0 && i < sc->msk_num_port; i++) {
1465 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_SET);
1466 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
1467 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_R1),
1468 MSK_RI_TO_53);
1469 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA1),
1470 MSK_RI_TO_53);
1471 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS1),
1472 MSK_RI_TO_53);
1473 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_R1),
1474 MSK_RI_TO_53);
1475 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA1),
1476 MSK_RI_TO_53);
1477 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS1),
1478 MSK_RI_TO_53);
1479 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_R2),
1480 MSK_RI_TO_53);
1481 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA2),
1482 MSK_RI_TO_53);
1483 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS2),
1484 MSK_RI_TO_53);
1485 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_R2),
1486 MSK_RI_TO_53);
1487 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA2),
1488 MSK_RI_TO_53);
1489 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS2),
1490 MSK_RI_TO_53);
1491 }
1492
1493 /* Disable all interrupts. */
1494 CSR_WRITE_4(sc, B0_HWE_IMSK, 0);
1495 CSR_READ_4(sc, B0_HWE_IMSK);
1496 CSR_WRITE_4(sc, B0_IMSK, 0);
1497 CSR_READ_4(sc, B0_IMSK);
1498
1499 /*
1500 * On dual port PCI-X card, there is an problem where status
1501 * can be received out of order due to split transactions.
1502 */
1503 if (sc->msk_pcixcap != 0 && sc->msk_num_port > 1) {
1504 uint16_t pcix_cmd;
1505
1506 pcix_cmd = pci_read_config(sc->msk_dev,
1507 sc->msk_pcixcap + PCIXR_COMMAND, 2);
1508 /* Clear Max Outstanding Split Transactions. */
1509 pcix_cmd &= ~PCIXM_COMMAND_MAX_SPLITS;
1510 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON);
1511 pci_write_config(sc->msk_dev,
1512 sc->msk_pcixcap + PCIXR_COMMAND, pcix_cmd, 2);
1513 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
1514 }
1515 if (sc->msk_expcap != 0) {
1516 /* Change Max. Read Request Size to 2048 bytes. */
1517 if (pci_get_max_read_req(sc->msk_dev) == 512)
1518 pci_set_max_read_req(sc->msk_dev, 2048);
1519 }
1520
1521 /* Clear status list. */
1522 bzero(sc->msk_stat_ring,
1523 sizeof(struct msk_stat_desc) * sc->msk_stat_count);
1524 sc->msk_stat_cons = 0;
1525 bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map,
1526 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1527 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_RST_SET);
1528 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_RST_CLR);
1529 /* Set the status list base address. */
1530 addr = sc->msk_stat_ring_paddr;
1531 CSR_WRITE_4(sc, STAT_LIST_ADDR_LO, MSK_ADDR_LO(addr));
1532 CSR_WRITE_4(sc, STAT_LIST_ADDR_HI, MSK_ADDR_HI(addr));
1533 /* Set the status list last index. */
1534 CSR_WRITE_2(sc, STAT_LAST_IDX, sc->msk_stat_count - 1);
1535 if (sc->msk_hw_id == CHIP_ID_YUKON_EC &&
1536 sc->msk_hw_rev == CHIP_REV_YU_EC_A1) {
1537 /* WA for dev. #4.3 */
1538 CSR_WRITE_2(sc, STAT_TX_IDX_TH, ST_TXTH_IDX_MASK);
1539 /* WA for dev. #4.18 */
1540 CSR_WRITE_1(sc, STAT_FIFO_WM, 0x21);
1541 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x07);
1542 } else {
1543 CSR_WRITE_2(sc, STAT_TX_IDX_TH, 0x0a);
1544 CSR_WRITE_1(sc, STAT_FIFO_WM, 0x10);
1545 if (sc->msk_hw_id == CHIP_ID_YUKON_XL &&
1546 sc->msk_hw_rev == CHIP_REV_YU_XL_A0)
1547 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x04);
1548 else
1549 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x10);
1550 CSR_WRITE_4(sc, STAT_ISR_TIMER_INI, 0x0190);
1551 }
1552 /*
1553 * Use default value for STAT_ISR_TIMER_INI, STAT_LEV_TIMER_INI.
1554 */
1555 CSR_WRITE_4(sc, STAT_TX_TIMER_INI, MSK_USECS(sc, 1000));
1556
1557 /* Enable status unit. */
1558 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_OP_ON);
1559
1560 CSR_WRITE_1(sc, STAT_TX_TIMER_CTRL, TIM_START);
1561 CSR_WRITE_1(sc, STAT_LEV_TIMER_CTRL, TIM_START);
1562 CSR_WRITE_1(sc, STAT_ISR_TIMER_CTRL, TIM_START);
1563 }
1564
1565 static int
msk_probe(device_t dev)1566 msk_probe(device_t dev)
1567 {
1568 struct msk_softc *sc;
1569
1570 sc = device_get_softc(device_get_parent(dev));
1571 /*
1572 * Not much to do here. We always know there will be
1573 * at least one GMAC present, and if there are two,
1574 * mskc_attach() will create a second device instance
1575 * for us.
1576 */
1577 device_set_descf(dev,
1578 "Marvell Technology Group Ltd. %s Id 0x%02x Rev 0x%02x",
1579 model_name[sc->msk_hw_id - CHIP_ID_YUKON_XL], sc->msk_hw_id,
1580 sc->msk_hw_rev);
1581
1582 return (BUS_PROBE_DEFAULT);
1583 }
1584
1585 static int
msk_attach(device_t dev)1586 msk_attach(device_t dev)
1587 {
1588 struct msk_softc *sc;
1589 struct msk_if_softc *sc_if;
1590 if_t ifp;
1591 struct msk_mii_data *mmd;
1592 int i, port, error;
1593 uint8_t eaddr[6];
1594
1595 if (dev == NULL)
1596 return (EINVAL);
1597
1598 error = 0;
1599 sc_if = device_get_softc(dev);
1600 sc = device_get_softc(device_get_parent(dev));
1601 mmd = device_get_ivars(dev);
1602 port = mmd->port;
1603
1604 sc_if->msk_if_dev = dev;
1605 sc_if->msk_port = port;
1606 sc_if->msk_softc = sc;
1607 sc_if->msk_flags = sc->msk_pflags;
1608 sc->msk_if[port] = sc_if;
1609 /* Setup Tx/Rx queue register offsets. */
1610 if (port == MSK_PORT_A) {
1611 sc_if->msk_txq = Q_XA1;
1612 sc_if->msk_txsq = Q_XS1;
1613 sc_if->msk_rxq = Q_R1;
1614 } else {
1615 sc_if->msk_txq = Q_XA2;
1616 sc_if->msk_txsq = Q_XS2;
1617 sc_if->msk_rxq = Q_R2;
1618 }
1619
1620 callout_init_mtx(&sc_if->msk_tick_ch, &sc_if->msk_softc->msk_mtx, 0);
1621 msk_sysctl_node(sc_if);
1622
1623 if ((error = msk_txrx_dma_alloc(sc_if)) != 0)
1624 goto fail;
1625 msk_rx_dma_jalloc(sc_if);
1626
1627 ifp = sc_if->msk_ifp = if_alloc(IFT_ETHER);
1628 if_setsoftc(ifp, sc_if);
1629 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1630 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
1631 if_setcapabilities(ifp, IFCAP_TXCSUM | IFCAP_TSO4);
1632 /*
1633 * Enable Rx checksum offloading if controller supports
1634 * new descriptor formant and controller is not Yukon XL.
1635 */
1636 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 &&
1637 sc->msk_hw_id != CHIP_ID_YUKON_XL)
1638 if_setcapabilitiesbit(ifp, IFCAP_RXCSUM, 0);
1639 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0 &&
1640 (sc_if->msk_flags & MSK_FLAG_NORX_CSUM) == 0)
1641 if_setcapabilitiesbit(ifp, IFCAP_RXCSUM, 0);
1642 if_sethwassist(ifp, MSK_CSUM_FEATURES | CSUM_TSO);
1643 if_setcapenable(ifp, if_getcapabilities(ifp));
1644 if_setioctlfn(ifp, msk_ioctl);
1645 if_setstartfn(ifp, msk_start);
1646 if_setinitfn(ifp, msk_init);
1647 if_setsendqlen(ifp, MSK_TX_RING_CNT - 1);
1648 if_setsendqready(ifp);
1649 /*
1650 * Get station address for this interface. Note that
1651 * dual port cards actually come with three station
1652 * addresses: one for each port, plus an extra. The
1653 * extra one is used by the SysKonnect driver software
1654 * as a 'virtual' station address for when both ports
1655 * are operating in failover mode. Currently we don't
1656 * use this extra address.
1657 */
1658 MSK_IF_LOCK(sc_if);
1659 for (i = 0; i < ETHER_ADDR_LEN; i++)
1660 eaddr[i] = CSR_READ_1(sc, B2_MAC_1 + (port * 8) + i);
1661
1662 /*
1663 * Call MI attach routine. Can't hold locks when calling into ether_*.
1664 */
1665 MSK_IF_UNLOCK(sc_if);
1666 ether_ifattach(ifp, eaddr);
1667 MSK_IF_LOCK(sc_if);
1668
1669 /* VLAN capability setup */
1670 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU, 0);
1671 if ((sc_if->msk_flags & MSK_FLAG_NOHWVLAN) == 0) {
1672 /*
1673 * Due to Tx checksum offload hardware bugs, msk(4) manually
1674 * computes checksum for short frames. For VLAN tagged frames
1675 * this workaround does not work so disable checksum offload
1676 * for VLAN interface.
1677 */
1678 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWTSO, 0);
1679 /*
1680 * Enable Rx checksum offloading for VLAN tagged frames
1681 * if controller support new descriptor format.
1682 */
1683 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0 &&
1684 (sc_if->msk_flags & MSK_FLAG_NORX_CSUM) == 0)
1685 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWCSUM, 0);
1686 }
1687 if_setcapenable(ifp, if_getcapabilities(ifp));
1688 /*
1689 * Disable RX checksum offloading on controllers that don't use
1690 * new descriptor format but give chance to enable it.
1691 */
1692 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0)
1693 if_setcapenablebit(ifp, 0, IFCAP_RXCSUM);
1694
1695 /*
1696 * Tell the upper layer(s) we support long frames.
1697 * Must appear after the call to ether_ifattach() because
1698 * ether_ifattach() sets ifi_hdrlen to the default value.
1699 */
1700 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
1701
1702 /*
1703 * Do miibus setup.
1704 */
1705 MSK_IF_UNLOCK(sc_if);
1706 error = mii_attach(dev, &sc_if->msk_miibus, ifp, msk_mediachange,
1707 msk_mediastatus, BMSR_DEFCAPMASK, PHY_ADDR_MARV, MII_OFFSET_ANY,
1708 mmd->mii_flags);
1709 if (error != 0) {
1710 device_printf(sc_if->msk_if_dev, "attaching PHYs failed\n");
1711 ether_ifdetach(ifp);
1712 error = ENXIO;
1713 goto fail;
1714 }
1715
1716 fail:
1717 if (error != 0) {
1718 /* Access should be ok even though lock has been dropped */
1719 sc->msk_if[port] = NULL;
1720 msk_detach(dev);
1721 }
1722
1723 return (error);
1724 }
1725
1726 /*
1727 * Attach the interface. Allocate softc structures, do ifmedia
1728 * setup and ethernet/BPF attach.
1729 */
1730 static int
mskc_attach(device_t dev)1731 mskc_attach(device_t dev)
1732 {
1733 struct msk_softc *sc;
1734 struct msk_mii_data *mmd;
1735 int error, msic, msir, reg;
1736
1737 sc = device_get_softc(dev);
1738 sc->msk_dev = dev;
1739 mtx_init(&sc->msk_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1740 MTX_DEF);
1741
1742 /*
1743 * Map control/status registers.
1744 */
1745 pci_enable_busmaster(dev);
1746
1747 /* Allocate I/O resource */
1748 #ifdef MSK_USEIOSPACE
1749 sc->msk_res_spec = msk_res_spec_io;
1750 #else
1751 sc->msk_res_spec = msk_res_spec_mem;
1752 #endif
1753 sc->msk_irq_spec = msk_irq_spec_legacy;
1754 error = bus_alloc_resources(dev, sc->msk_res_spec, sc->msk_res);
1755 if (error) {
1756 if (sc->msk_res_spec == msk_res_spec_mem)
1757 sc->msk_res_spec = msk_res_spec_io;
1758 else
1759 sc->msk_res_spec = msk_res_spec_mem;
1760 error = bus_alloc_resources(dev, sc->msk_res_spec, sc->msk_res);
1761 if (error) {
1762 device_printf(dev, "couldn't allocate %s resources\n",
1763 sc->msk_res_spec == msk_res_spec_mem ? "memory" :
1764 "I/O");
1765 mtx_destroy(&sc->msk_mtx);
1766 return (ENXIO);
1767 }
1768 }
1769
1770 /* Enable all clocks before accessing any registers. */
1771 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_3, 0);
1772
1773 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR);
1774 sc->msk_hw_id = CSR_READ_1(sc, B2_CHIP_ID);
1775 sc->msk_hw_rev = (CSR_READ_1(sc, B2_MAC_CFG) >> 4) & 0x0f;
1776 /* Bail out if chip is not recognized. */
1777 if (sc->msk_hw_id < CHIP_ID_YUKON_XL ||
1778 sc->msk_hw_id > CHIP_ID_YUKON_OPT ||
1779 sc->msk_hw_id == CHIP_ID_YUKON_UNKNOWN) {
1780 device_printf(dev, "unknown device: id=0x%02x, rev=0x%02x\n",
1781 sc->msk_hw_id, sc->msk_hw_rev);
1782 mtx_destroy(&sc->msk_mtx);
1783 return (ENXIO);
1784 }
1785
1786 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
1787 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
1788 OID_AUTO, "process_limit",
1789 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
1790 &sc->msk_process_limit, 0, sysctl_hw_msk_proc_limit, "I",
1791 "max number of Rx events to process");
1792
1793 sc->msk_process_limit = MSK_PROC_DEFAULT;
1794 error = resource_int_value(device_get_name(dev), device_get_unit(dev),
1795 "process_limit", &sc->msk_process_limit);
1796 if (error == 0) {
1797 if (sc->msk_process_limit < MSK_PROC_MIN ||
1798 sc->msk_process_limit > MSK_PROC_MAX) {
1799 device_printf(dev, "process_limit value out of range; "
1800 "using default: %d\n", MSK_PROC_DEFAULT);
1801 sc->msk_process_limit = MSK_PROC_DEFAULT;
1802 }
1803 }
1804
1805 sc->msk_int_holdoff = MSK_INT_HOLDOFF_DEFAULT;
1806 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
1807 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
1808 "int_holdoff", CTLFLAG_RW, &sc->msk_int_holdoff, 0,
1809 "Maximum number of time to delay interrupts");
1810 resource_int_value(device_get_name(dev), device_get_unit(dev),
1811 "int_holdoff", &sc->msk_int_holdoff);
1812
1813 sc->msk_pmd = CSR_READ_1(sc, B2_PMD_TYP);
1814 /* Check number of MACs. */
1815 sc->msk_num_port = 1;
1816 if ((CSR_READ_1(sc, B2_Y2_HW_RES) & CFG_DUAL_MAC_MSK) ==
1817 CFG_DUAL_MAC_MSK) {
1818 if (!(CSR_READ_1(sc, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
1819 sc->msk_num_port++;
1820 }
1821
1822 /* Check bus type. */
1823 if (pci_find_cap(sc->msk_dev, PCIY_EXPRESS, ®) == 0) {
1824 sc->msk_bustype = MSK_PEX_BUS;
1825 sc->msk_expcap = reg;
1826 } else if (pci_find_cap(sc->msk_dev, PCIY_PCIX, ®) == 0) {
1827 sc->msk_bustype = MSK_PCIX_BUS;
1828 sc->msk_pcixcap = reg;
1829 } else
1830 sc->msk_bustype = MSK_PCI_BUS;
1831
1832 switch (sc->msk_hw_id) {
1833 case CHIP_ID_YUKON_EC:
1834 sc->msk_clock = 125; /* 125 MHz */
1835 sc->msk_pflags |= MSK_FLAG_JUMBO;
1836 break;
1837 case CHIP_ID_YUKON_EC_U:
1838 sc->msk_clock = 125; /* 125 MHz */
1839 sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_JUMBO_NOCSUM;
1840 break;
1841 case CHIP_ID_YUKON_EX:
1842 sc->msk_clock = 125; /* 125 MHz */
1843 sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_DESCV2 |
1844 MSK_FLAG_AUTOTX_CSUM;
1845 /*
1846 * Yukon Extreme seems to have silicon bug for
1847 * automatic Tx checksum calculation capability.
1848 */
1849 if (sc->msk_hw_rev == CHIP_REV_YU_EX_B0)
1850 sc->msk_pflags &= ~MSK_FLAG_AUTOTX_CSUM;
1851 /*
1852 * Yukon Extreme A0 could not use store-and-forward
1853 * for jumbo frames, so disable Tx checksum
1854 * offloading for jumbo frames.
1855 */
1856 if (sc->msk_hw_rev == CHIP_REV_YU_EX_A0)
1857 sc->msk_pflags |= MSK_FLAG_JUMBO_NOCSUM;
1858 break;
1859 case CHIP_ID_YUKON_FE:
1860 sc->msk_clock = 100; /* 100 MHz */
1861 sc->msk_pflags |= MSK_FLAG_FASTETHER;
1862 break;
1863 case CHIP_ID_YUKON_FE_P:
1864 sc->msk_clock = 50; /* 50 MHz */
1865 sc->msk_pflags |= MSK_FLAG_FASTETHER | MSK_FLAG_DESCV2 |
1866 MSK_FLAG_AUTOTX_CSUM;
1867 if (sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) {
1868 /*
1869 * XXX
1870 * FE+ A0 has status LE writeback bug so msk(4)
1871 * does not rely on status word of received frame
1872 * in msk_rxeof() which in turn disables all
1873 * hardware assistance bits reported by the status
1874 * word as well as validity of the received frame.
1875 * Just pass received frames to upper stack with
1876 * minimal test and let upper stack handle them.
1877 */
1878 sc->msk_pflags |= MSK_FLAG_NOHWVLAN |
1879 MSK_FLAG_NORXCHK | MSK_FLAG_NORX_CSUM;
1880 }
1881 break;
1882 case CHIP_ID_YUKON_XL:
1883 sc->msk_clock = 156; /* 156 MHz */
1884 sc->msk_pflags |= MSK_FLAG_JUMBO;
1885 break;
1886 case CHIP_ID_YUKON_SUPR:
1887 sc->msk_clock = 125; /* 125 MHz */
1888 sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_DESCV2 |
1889 MSK_FLAG_AUTOTX_CSUM;
1890 break;
1891 case CHIP_ID_YUKON_UL_2:
1892 sc->msk_clock = 125; /* 125 MHz */
1893 sc->msk_pflags |= MSK_FLAG_JUMBO;
1894 break;
1895 case CHIP_ID_YUKON_OPT:
1896 sc->msk_clock = 125; /* 125 MHz */
1897 sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_DESCV2;
1898 break;
1899 default:
1900 sc->msk_clock = 156; /* 156 MHz */
1901 break;
1902 }
1903
1904 /* Allocate IRQ resources. */
1905 msic = pci_msi_count(dev);
1906 if (bootverbose)
1907 device_printf(dev, "MSI count : %d\n", msic);
1908 if (legacy_intr != 0)
1909 msi_disable = 1;
1910 if (msi_disable == 0 && msic > 0) {
1911 msir = 1;
1912 if (pci_alloc_msi(dev, &msir) == 0) {
1913 if (msir == 1) {
1914 sc->msk_pflags |= MSK_FLAG_MSI;
1915 sc->msk_irq_spec = msk_irq_spec_msi;
1916 } else
1917 pci_release_msi(dev);
1918 }
1919 }
1920
1921 error = bus_alloc_resources(dev, sc->msk_irq_spec, sc->msk_irq);
1922 if (error) {
1923 device_printf(dev, "couldn't allocate IRQ resources\n");
1924 goto fail;
1925 }
1926
1927 if ((error = msk_status_dma_alloc(sc)) != 0)
1928 goto fail;
1929
1930 /* Set base interrupt mask. */
1931 sc->msk_intrmask = Y2_IS_HW_ERR | Y2_IS_STAT_BMU;
1932 sc->msk_intrhwemask = Y2_IS_TIST_OV | Y2_IS_MST_ERR |
1933 Y2_IS_IRQ_STAT | Y2_IS_PCI_EXP | Y2_IS_PCI_NEXP;
1934
1935 /* Reset the adapter. */
1936 mskc_reset(sc);
1937
1938 if ((error = mskc_setup_rambuffer(sc)) != 0)
1939 goto fail;
1940
1941 sc->msk_devs[MSK_PORT_A] = device_add_child(dev, "msk", DEVICE_UNIT_ANY);
1942 if (sc->msk_devs[MSK_PORT_A] == NULL) {
1943 device_printf(dev, "failed to add child for PORT_A\n");
1944 error = ENXIO;
1945 goto fail;
1946 }
1947 mmd = malloc(sizeof(struct msk_mii_data), M_DEVBUF, M_WAITOK | M_ZERO);
1948 mmd->port = MSK_PORT_A;
1949 mmd->pmd = sc->msk_pmd;
1950 mmd->mii_flags |= MIIF_DOPAUSE;
1951 if (sc->msk_pmd == 'L' || sc->msk_pmd == 'S')
1952 mmd->mii_flags |= MIIF_HAVEFIBER;
1953 if (sc->msk_pmd == 'P')
1954 mmd->mii_flags |= MIIF_HAVEFIBER | MIIF_MACPRIV0;
1955 device_set_ivars(sc->msk_devs[MSK_PORT_A], mmd);
1956
1957 if (sc->msk_num_port > 1) {
1958 sc->msk_devs[MSK_PORT_B] = device_add_child(dev, "msk", DEVICE_UNIT_ANY);
1959 if (sc->msk_devs[MSK_PORT_B] == NULL) {
1960 device_printf(dev, "failed to add child for PORT_B\n");
1961 error = ENXIO;
1962 goto fail;
1963 }
1964 mmd = malloc(sizeof(struct msk_mii_data), M_DEVBUF, M_WAITOK |
1965 M_ZERO);
1966 mmd->port = MSK_PORT_B;
1967 mmd->pmd = sc->msk_pmd;
1968 if (sc->msk_pmd == 'L' || sc->msk_pmd == 'S')
1969 mmd->mii_flags |= MIIF_HAVEFIBER;
1970 if (sc->msk_pmd == 'P')
1971 mmd->mii_flags |= MIIF_HAVEFIBER | MIIF_MACPRIV0;
1972 device_set_ivars(sc->msk_devs[MSK_PORT_B], mmd);
1973 }
1974
1975 error = bus_generic_attach(dev);
1976 if (error) {
1977 device_printf(dev, "failed to attach port(s)\n");
1978 goto fail;
1979 }
1980
1981 /* Hook interrupt last to avoid having to lock softc. */
1982 error = bus_setup_intr(dev, sc->msk_irq[0], INTR_TYPE_NET |
1983 INTR_MPSAFE, NULL, msk_intr, sc, &sc->msk_intrhand);
1984 if (error != 0) {
1985 device_printf(dev, "couldn't set up interrupt handler\n");
1986 goto fail;
1987 }
1988 fail:
1989 if (error != 0)
1990 mskc_detach(dev);
1991
1992 return (error);
1993 }
1994
1995 /*
1996 * Shutdown hardware and free up resources. This can be called any
1997 * time after the mutex has been initialized. It is called in both
1998 * the error case in attach and the normal detach case so it needs
1999 * to be careful about only freeing resources that have actually been
2000 * allocated.
2001 */
2002 static int
msk_detach(device_t dev)2003 msk_detach(device_t dev)
2004 {
2005 struct msk_softc *sc;
2006 struct msk_if_softc *sc_if;
2007 if_t ifp;
2008
2009 sc_if = device_get_softc(dev);
2010 KASSERT(mtx_initialized(&sc_if->msk_softc->msk_mtx),
2011 ("msk mutex not initialized in msk_detach"));
2012 MSK_IF_LOCK(sc_if);
2013
2014 ifp = sc_if->msk_ifp;
2015 if (device_is_attached(dev)) {
2016 /* XXX */
2017 sc_if->msk_flags |= MSK_FLAG_DETACH;
2018 msk_stop(sc_if);
2019 /* Can't hold locks while calling detach. */
2020 MSK_IF_UNLOCK(sc_if);
2021 callout_drain(&sc_if->msk_tick_ch);
2022 if (ifp)
2023 ether_ifdetach(ifp);
2024 MSK_IF_LOCK(sc_if);
2025 }
2026
2027 /*
2028 * We're generally called from mskc_detach() which is using
2029 * device_delete_child() to get to here. It's already trashed
2030 * miibus for us, so don't do it here or we'll panic.
2031 *
2032 * if (sc_if->msk_miibus != NULL) {
2033 * device_delete_child(dev, sc_if->msk_miibus);
2034 * sc_if->msk_miibus = NULL;
2035 * }
2036 */
2037
2038 msk_rx_dma_jfree(sc_if);
2039 msk_txrx_dma_free(sc_if);
2040 bus_generic_detach(dev);
2041
2042 sc = sc_if->msk_softc;
2043 sc->msk_if[sc_if->msk_port] = NULL;
2044 MSK_IF_UNLOCK(sc_if);
2045 if (ifp)
2046 if_free(ifp);
2047
2048 return (0);
2049 }
2050
2051 static void
mskc_child_deleted(device_t dev,device_t child)2052 mskc_child_deleted(device_t dev, device_t child)
2053 {
2054 free(device_get_ivars(child), M_DEVBUF);
2055 }
2056
2057 static int
mskc_detach(device_t dev)2058 mskc_detach(device_t dev)
2059 {
2060 struct msk_softc *sc;
2061
2062 sc = device_get_softc(dev);
2063 KASSERT(mtx_initialized(&sc->msk_mtx), ("msk mutex not initialized"));
2064
2065 if (device_is_alive(dev)) {
2066 if (sc->msk_devs[MSK_PORT_A] != NULL) {
2067 device_delete_child(dev, sc->msk_devs[MSK_PORT_A]);
2068 }
2069 if (sc->msk_devs[MSK_PORT_B] != NULL) {
2070 device_delete_child(dev, sc->msk_devs[MSK_PORT_B]);
2071 }
2072 bus_generic_detach(dev);
2073 }
2074
2075 /* Disable all interrupts. */
2076 CSR_WRITE_4(sc, B0_IMSK, 0);
2077 CSR_READ_4(sc, B0_IMSK);
2078 CSR_WRITE_4(sc, B0_HWE_IMSK, 0);
2079 CSR_READ_4(sc, B0_HWE_IMSK);
2080
2081 /* LED Off. */
2082 CSR_WRITE_2(sc, B0_CTST, Y2_LED_STAT_OFF);
2083
2084 /* Put hardware reset. */
2085 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET);
2086
2087 msk_status_dma_free(sc);
2088
2089 if (sc->msk_intrhand) {
2090 bus_teardown_intr(dev, sc->msk_irq[0], sc->msk_intrhand);
2091 sc->msk_intrhand = NULL;
2092 }
2093 bus_release_resources(dev, sc->msk_irq_spec, sc->msk_irq);
2094 if ((sc->msk_pflags & MSK_FLAG_MSI) != 0)
2095 pci_release_msi(dev);
2096 bus_release_resources(dev, sc->msk_res_spec, sc->msk_res);
2097 mtx_destroy(&sc->msk_mtx);
2098
2099 return (0);
2100 }
2101
2102 static bus_dma_tag_t
mskc_get_dma_tag(device_t bus,device_t child __unused)2103 mskc_get_dma_tag(device_t bus, device_t child __unused)
2104 {
2105
2106 return (bus_get_dma_tag(bus));
2107 }
2108
2109 struct msk_dmamap_arg {
2110 bus_addr_t msk_busaddr;
2111 };
2112
2113 static void
msk_dmamap_cb(void * arg,bus_dma_segment_t * segs,int nseg,int error)2114 msk_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
2115 {
2116 struct msk_dmamap_arg *ctx;
2117
2118 if (error != 0)
2119 return;
2120 ctx = arg;
2121 ctx->msk_busaddr = segs[0].ds_addr;
2122 }
2123
2124 /* Create status DMA region. */
2125 static int
msk_status_dma_alloc(struct msk_softc * sc)2126 msk_status_dma_alloc(struct msk_softc *sc)
2127 {
2128 struct msk_dmamap_arg ctx;
2129 bus_size_t stat_sz;
2130 int count, error;
2131
2132 /*
2133 * It seems controller requires number of status LE entries
2134 * is power of 2 and the maximum number of status LE entries
2135 * is 4096. For dual-port controllers, the number of status
2136 * LE entries should be large enough to hold both port's
2137 * status updates.
2138 */
2139 count = 3 * MSK_RX_RING_CNT + MSK_TX_RING_CNT;
2140 count = imin(4096, roundup2(count, 1024));
2141 sc->msk_stat_count = count;
2142 stat_sz = count * sizeof(struct msk_stat_desc);
2143 error = bus_dma_tag_create(
2144 bus_get_dma_tag(sc->msk_dev), /* parent */
2145 MSK_STAT_ALIGN, 0, /* alignment, boundary */
2146 BUS_SPACE_MAXADDR, /* lowaddr */
2147 BUS_SPACE_MAXADDR, /* highaddr */
2148 NULL, NULL, /* filter, filterarg */
2149 stat_sz, /* maxsize */
2150 1, /* nsegments */
2151 stat_sz, /* maxsegsize */
2152 0, /* flags */
2153 NULL, NULL, /* lockfunc, lockarg */
2154 &sc->msk_stat_tag);
2155 if (error != 0) {
2156 device_printf(sc->msk_dev,
2157 "failed to create status DMA tag\n");
2158 return (error);
2159 }
2160
2161 /* Allocate DMA'able memory and load the DMA map for status ring. */
2162 error = bus_dmamem_alloc(sc->msk_stat_tag,
2163 (void **)&sc->msk_stat_ring, BUS_DMA_WAITOK | BUS_DMA_COHERENT |
2164 BUS_DMA_ZERO, &sc->msk_stat_map);
2165 if (error != 0) {
2166 device_printf(sc->msk_dev,
2167 "failed to allocate DMA'able memory for status ring\n");
2168 return (error);
2169 }
2170
2171 ctx.msk_busaddr = 0;
2172 error = bus_dmamap_load(sc->msk_stat_tag, sc->msk_stat_map,
2173 sc->msk_stat_ring, stat_sz, msk_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
2174 if (error != 0) {
2175 device_printf(sc->msk_dev,
2176 "failed to load DMA'able memory for status ring\n");
2177 return (error);
2178 }
2179 sc->msk_stat_ring_paddr = ctx.msk_busaddr;
2180
2181 return (0);
2182 }
2183
2184 static void
msk_status_dma_free(struct msk_softc * sc)2185 msk_status_dma_free(struct msk_softc *sc)
2186 {
2187
2188 /* Destroy status block. */
2189 if (sc->msk_stat_tag) {
2190 if (sc->msk_stat_ring_paddr) {
2191 bus_dmamap_unload(sc->msk_stat_tag, sc->msk_stat_map);
2192 sc->msk_stat_ring_paddr = 0;
2193 }
2194 if (sc->msk_stat_ring) {
2195 bus_dmamem_free(sc->msk_stat_tag,
2196 sc->msk_stat_ring, sc->msk_stat_map);
2197 sc->msk_stat_ring = NULL;
2198 }
2199 bus_dma_tag_destroy(sc->msk_stat_tag);
2200 sc->msk_stat_tag = NULL;
2201 }
2202 }
2203
2204 static int
msk_txrx_dma_alloc(struct msk_if_softc * sc_if)2205 msk_txrx_dma_alloc(struct msk_if_softc *sc_if)
2206 {
2207 struct msk_dmamap_arg ctx;
2208 struct msk_txdesc *txd;
2209 struct msk_rxdesc *rxd;
2210 bus_size_t rxalign;
2211 int error, i;
2212
2213 /* Create parent DMA tag. */
2214 error = bus_dma_tag_create(
2215 bus_get_dma_tag(sc_if->msk_if_dev), /* parent */
2216 1, 0, /* alignment, boundary */
2217 BUS_SPACE_MAXADDR, /* lowaddr */
2218 BUS_SPACE_MAXADDR, /* highaddr */
2219 NULL, NULL, /* filter, filterarg */
2220 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
2221 0, /* nsegments */
2222 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
2223 0, /* flags */
2224 NULL, NULL, /* lockfunc, lockarg */
2225 &sc_if->msk_cdata.msk_parent_tag);
2226 if (error != 0) {
2227 device_printf(sc_if->msk_if_dev,
2228 "failed to create parent DMA tag\n");
2229 goto fail;
2230 }
2231 /* Create tag for Tx ring. */
2232 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */
2233 MSK_RING_ALIGN, 0, /* alignment, boundary */
2234 BUS_SPACE_MAXADDR, /* lowaddr */
2235 BUS_SPACE_MAXADDR, /* highaddr */
2236 NULL, NULL, /* filter, filterarg */
2237 MSK_TX_RING_SZ, /* maxsize */
2238 1, /* nsegments */
2239 MSK_TX_RING_SZ, /* maxsegsize */
2240 0, /* flags */
2241 NULL, NULL, /* lockfunc, lockarg */
2242 &sc_if->msk_cdata.msk_tx_ring_tag);
2243 if (error != 0) {
2244 device_printf(sc_if->msk_if_dev,
2245 "failed to create Tx ring DMA tag\n");
2246 goto fail;
2247 }
2248
2249 /* Create tag for Rx ring. */
2250 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */
2251 MSK_RING_ALIGN, 0, /* alignment, boundary */
2252 BUS_SPACE_MAXADDR, /* lowaddr */
2253 BUS_SPACE_MAXADDR, /* highaddr */
2254 NULL, NULL, /* filter, filterarg */
2255 MSK_RX_RING_SZ, /* maxsize */
2256 1, /* nsegments */
2257 MSK_RX_RING_SZ, /* maxsegsize */
2258 0, /* flags */
2259 NULL, NULL, /* lockfunc, lockarg */
2260 &sc_if->msk_cdata.msk_rx_ring_tag);
2261 if (error != 0) {
2262 device_printf(sc_if->msk_if_dev,
2263 "failed to create Rx ring DMA tag\n");
2264 goto fail;
2265 }
2266
2267 /* Create tag for Tx buffers. */
2268 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */
2269 1, 0, /* alignment, boundary */
2270 BUS_SPACE_MAXADDR, /* lowaddr */
2271 BUS_SPACE_MAXADDR, /* highaddr */
2272 NULL, NULL, /* filter, filterarg */
2273 MSK_TSO_MAXSIZE, /* maxsize */
2274 MSK_MAXTXSEGS, /* nsegments */
2275 MSK_TSO_MAXSGSIZE, /* maxsegsize */
2276 0, /* flags */
2277 NULL, NULL, /* lockfunc, lockarg */
2278 &sc_if->msk_cdata.msk_tx_tag);
2279 if (error != 0) {
2280 device_printf(sc_if->msk_if_dev,
2281 "failed to create Tx DMA tag\n");
2282 goto fail;
2283 }
2284
2285 rxalign = 1;
2286 /*
2287 * Workaround hardware hang which seems to happen when Rx buffer
2288 * is not aligned on multiple of FIFO word(8 bytes).
2289 */
2290 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0)
2291 rxalign = MSK_RX_BUF_ALIGN;
2292 /* Create tag for Rx buffers. */
2293 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */
2294 rxalign, 0, /* alignment, boundary */
2295 BUS_SPACE_MAXADDR, /* lowaddr */
2296 BUS_SPACE_MAXADDR, /* highaddr */
2297 NULL, NULL, /* filter, filterarg */
2298 MCLBYTES, /* maxsize */
2299 1, /* nsegments */
2300 MCLBYTES, /* maxsegsize */
2301 0, /* flags */
2302 NULL, NULL, /* lockfunc, lockarg */
2303 &sc_if->msk_cdata.msk_rx_tag);
2304 if (error != 0) {
2305 device_printf(sc_if->msk_if_dev,
2306 "failed to create Rx DMA tag\n");
2307 goto fail;
2308 }
2309
2310 /* Allocate DMA'able memory and load the DMA map for Tx ring. */
2311 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_tx_ring_tag,
2312 (void **)&sc_if->msk_rdata.msk_tx_ring, BUS_DMA_WAITOK |
2313 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->msk_cdata.msk_tx_ring_map);
2314 if (error != 0) {
2315 device_printf(sc_if->msk_if_dev,
2316 "failed to allocate DMA'able memory for Tx ring\n");
2317 goto fail;
2318 }
2319
2320 ctx.msk_busaddr = 0;
2321 error = bus_dmamap_load(sc_if->msk_cdata.msk_tx_ring_tag,
2322 sc_if->msk_cdata.msk_tx_ring_map, sc_if->msk_rdata.msk_tx_ring,
2323 MSK_TX_RING_SZ, msk_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
2324 if (error != 0) {
2325 device_printf(sc_if->msk_if_dev,
2326 "failed to load DMA'able memory for Tx ring\n");
2327 goto fail;
2328 }
2329 sc_if->msk_rdata.msk_tx_ring_paddr = ctx.msk_busaddr;
2330
2331 /* Allocate DMA'able memory and load the DMA map for Rx ring. */
2332 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_rx_ring_tag,
2333 (void **)&sc_if->msk_rdata.msk_rx_ring, BUS_DMA_WAITOK |
2334 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->msk_cdata.msk_rx_ring_map);
2335 if (error != 0) {
2336 device_printf(sc_if->msk_if_dev,
2337 "failed to allocate DMA'able memory for Rx ring\n");
2338 goto fail;
2339 }
2340
2341 ctx.msk_busaddr = 0;
2342 error = bus_dmamap_load(sc_if->msk_cdata.msk_rx_ring_tag,
2343 sc_if->msk_cdata.msk_rx_ring_map, sc_if->msk_rdata.msk_rx_ring,
2344 MSK_RX_RING_SZ, msk_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
2345 if (error != 0) {
2346 device_printf(sc_if->msk_if_dev,
2347 "failed to load DMA'able memory for Rx ring\n");
2348 goto fail;
2349 }
2350 sc_if->msk_rdata.msk_rx_ring_paddr = ctx.msk_busaddr;
2351
2352 /* Create DMA maps for Tx buffers. */
2353 for (i = 0; i < MSK_TX_RING_CNT; i++) {
2354 txd = &sc_if->msk_cdata.msk_txdesc[i];
2355 txd->tx_m = NULL;
2356 txd->tx_dmamap = NULL;
2357 error = bus_dmamap_create(sc_if->msk_cdata.msk_tx_tag, 0,
2358 &txd->tx_dmamap);
2359 if (error != 0) {
2360 device_printf(sc_if->msk_if_dev,
2361 "failed to create Tx dmamap\n");
2362 goto fail;
2363 }
2364 }
2365 /* Create DMA maps for Rx buffers. */
2366 if ((error = bus_dmamap_create(sc_if->msk_cdata.msk_rx_tag, 0,
2367 &sc_if->msk_cdata.msk_rx_sparemap)) != 0) {
2368 device_printf(sc_if->msk_if_dev,
2369 "failed to create spare Rx dmamap\n");
2370 goto fail;
2371 }
2372 for (i = 0; i < MSK_RX_RING_CNT; i++) {
2373 rxd = &sc_if->msk_cdata.msk_rxdesc[i];
2374 rxd->rx_m = NULL;
2375 rxd->rx_dmamap = NULL;
2376 error = bus_dmamap_create(sc_if->msk_cdata.msk_rx_tag, 0,
2377 &rxd->rx_dmamap);
2378 if (error != 0) {
2379 device_printf(sc_if->msk_if_dev,
2380 "failed to create Rx dmamap\n");
2381 goto fail;
2382 }
2383 }
2384
2385 fail:
2386 return (error);
2387 }
2388
2389 static int
msk_rx_dma_jalloc(struct msk_if_softc * sc_if)2390 msk_rx_dma_jalloc(struct msk_if_softc *sc_if)
2391 {
2392 struct msk_dmamap_arg ctx;
2393 struct msk_rxdesc *jrxd;
2394 bus_size_t rxalign;
2395 int error, i;
2396
2397 if (jumbo_disable != 0 || (sc_if->msk_flags & MSK_FLAG_JUMBO) == 0) {
2398 sc_if->msk_flags &= ~MSK_FLAG_JUMBO;
2399 device_printf(sc_if->msk_if_dev,
2400 "disabling jumbo frame support\n");
2401 return (0);
2402 }
2403 /* Create tag for jumbo Rx ring. */
2404 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */
2405 MSK_RING_ALIGN, 0, /* alignment, boundary */
2406 BUS_SPACE_MAXADDR, /* lowaddr */
2407 BUS_SPACE_MAXADDR, /* highaddr */
2408 NULL, NULL, /* filter, filterarg */
2409 MSK_JUMBO_RX_RING_SZ, /* maxsize */
2410 1, /* nsegments */
2411 MSK_JUMBO_RX_RING_SZ, /* maxsegsize */
2412 0, /* flags */
2413 NULL, NULL, /* lockfunc, lockarg */
2414 &sc_if->msk_cdata.msk_jumbo_rx_ring_tag);
2415 if (error != 0) {
2416 device_printf(sc_if->msk_if_dev,
2417 "failed to create jumbo Rx ring DMA tag\n");
2418 goto jumbo_fail;
2419 }
2420
2421 rxalign = 1;
2422 /*
2423 * Workaround hardware hang which seems to happen when Rx buffer
2424 * is not aligned on multiple of FIFO word(8 bytes).
2425 */
2426 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0)
2427 rxalign = MSK_RX_BUF_ALIGN;
2428 /* Create tag for jumbo Rx buffers. */
2429 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */
2430 rxalign, 0, /* alignment, boundary */
2431 BUS_SPACE_MAXADDR, /* lowaddr */
2432 BUS_SPACE_MAXADDR, /* highaddr */
2433 NULL, NULL, /* filter, filterarg */
2434 MJUM9BYTES, /* maxsize */
2435 1, /* nsegments */
2436 MJUM9BYTES, /* maxsegsize */
2437 0, /* flags */
2438 NULL, NULL, /* lockfunc, lockarg */
2439 &sc_if->msk_cdata.msk_jumbo_rx_tag);
2440 if (error != 0) {
2441 device_printf(sc_if->msk_if_dev,
2442 "failed to create jumbo Rx DMA tag\n");
2443 goto jumbo_fail;
2444 }
2445
2446 /* Allocate DMA'able memory and load the DMA map for jumbo Rx ring. */
2447 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_jumbo_rx_ring_tag,
2448 (void **)&sc_if->msk_rdata.msk_jumbo_rx_ring,
2449 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO,
2450 &sc_if->msk_cdata.msk_jumbo_rx_ring_map);
2451 if (error != 0) {
2452 device_printf(sc_if->msk_if_dev,
2453 "failed to allocate DMA'able memory for jumbo Rx ring\n");
2454 goto jumbo_fail;
2455 }
2456
2457 ctx.msk_busaddr = 0;
2458 error = bus_dmamap_load(sc_if->msk_cdata.msk_jumbo_rx_ring_tag,
2459 sc_if->msk_cdata.msk_jumbo_rx_ring_map,
2460 sc_if->msk_rdata.msk_jumbo_rx_ring, MSK_JUMBO_RX_RING_SZ,
2461 msk_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
2462 if (error != 0) {
2463 device_printf(sc_if->msk_if_dev,
2464 "failed to load DMA'able memory for jumbo Rx ring\n");
2465 goto jumbo_fail;
2466 }
2467 sc_if->msk_rdata.msk_jumbo_rx_ring_paddr = ctx.msk_busaddr;
2468
2469 /* Create DMA maps for jumbo Rx buffers. */
2470 if ((error = bus_dmamap_create(sc_if->msk_cdata.msk_jumbo_rx_tag, 0,
2471 &sc_if->msk_cdata.msk_jumbo_rx_sparemap)) != 0) {
2472 device_printf(sc_if->msk_if_dev,
2473 "failed to create spare jumbo Rx dmamap\n");
2474 goto jumbo_fail;
2475 }
2476 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) {
2477 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i];
2478 jrxd->rx_m = NULL;
2479 jrxd->rx_dmamap = NULL;
2480 error = bus_dmamap_create(sc_if->msk_cdata.msk_jumbo_rx_tag, 0,
2481 &jrxd->rx_dmamap);
2482 if (error != 0) {
2483 device_printf(sc_if->msk_if_dev,
2484 "failed to create jumbo Rx dmamap\n");
2485 goto jumbo_fail;
2486 }
2487 }
2488
2489 return (0);
2490
2491 jumbo_fail:
2492 msk_rx_dma_jfree(sc_if);
2493 device_printf(sc_if->msk_if_dev, "disabling jumbo frame support "
2494 "due to resource shortage\n");
2495 sc_if->msk_flags &= ~MSK_FLAG_JUMBO;
2496 return (error);
2497 }
2498
2499 static void
msk_txrx_dma_free(struct msk_if_softc * sc_if)2500 msk_txrx_dma_free(struct msk_if_softc *sc_if)
2501 {
2502 struct msk_txdesc *txd;
2503 struct msk_rxdesc *rxd;
2504 int i;
2505
2506 /* Tx ring. */
2507 if (sc_if->msk_cdata.msk_tx_ring_tag) {
2508 if (sc_if->msk_rdata.msk_tx_ring_paddr)
2509 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_ring_tag,
2510 sc_if->msk_cdata.msk_tx_ring_map);
2511 if (sc_if->msk_rdata.msk_tx_ring)
2512 bus_dmamem_free(sc_if->msk_cdata.msk_tx_ring_tag,
2513 sc_if->msk_rdata.msk_tx_ring,
2514 sc_if->msk_cdata.msk_tx_ring_map);
2515 sc_if->msk_rdata.msk_tx_ring = NULL;
2516 sc_if->msk_rdata.msk_tx_ring_paddr = 0;
2517 bus_dma_tag_destroy(sc_if->msk_cdata.msk_tx_ring_tag);
2518 sc_if->msk_cdata.msk_tx_ring_tag = NULL;
2519 }
2520 /* Rx ring. */
2521 if (sc_if->msk_cdata.msk_rx_ring_tag) {
2522 if (sc_if->msk_rdata.msk_rx_ring_paddr)
2523 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_ring_tag,
2524 sc_if->msk_cdata.msk_rx_ring_map);
2525 if (sc_if->msk_rdata.msk_rx_ring)
2526 bus_dmamem_free(sc_if->msk_cdata.msk_rx_ring_tag,
2527 sc_if->msk_rdata.msk_rx_ring,
2528 sc_if->msk_cdata.msk_rx_ring_map);
2529 sc_if->msk_rdata.msk_rx_ring = NULL;
2530 sc_if->msk_rdata.msk_rx_ring_paddr = 0;
2531 bus_dma_tag_destroy(sc_if->msk_cdata.msk_rx_ring_tag);
2532 sc_if->msk_cdata.msk_rx_ring_tag = NULL;
2533 }
2534 /* Tx buffers. */
2535 if (sc_if->msk_cdata.msk_tx_tag) {
2536 for (i = 0; i < MSK_TX_RING_CNT; i++) {
2537 txd = &sc_if->msk_cdata.msk_txdesc[i];
2538 if (txd->tx_dmamap) {
2539 bus_dmamap_destroy(sc_if->msk_cdata.msk_tx_tag,
2540 txd->tx_dmamap);
2541 txd->tx_dmamap = NULL;
2542 }
2543 }
2544 bus_dma_tag_destroy(sc_if->msk_cdata.msk_tx_tag);
2545 sc_if->msk_cdata.msk_tx_tag = NULL;
2546 }
2547 /* Rx buffers. */
2548 if (sc_if->msk_cdata.msk_rx_tag) {
2549 for (i = 0; i < MSK_RX_RING_CNT; i++) {
2550 rxd = &sc_if->msk_cdata.msk_rxdesc[i];
2551 if (rxd->rx_dmamap) {
2552 bus_dmamap_destroy(sc_if->msk_cdata.msk_rx_tag,
2553 rxd->rx_dmamap);
2554 rxd->rx_dmamap = NULL;
2555 }
2556 }
2557 if (sc_if->msk_cdata.msk_rx_sparemap) {
2558 bus_dmamap_destroy(sc_if->msk_cdata.msk_rx_tag,
2559 sc_if->msk_cdata.msk_rx_sparemap);
2560 sc_if->msk_cdata.msk_rx_sparemap = 0;
2561 }
2562 bus_dma_tag_destroy(sc_if->msk_cdata.msk_rx_tag);
2563 sc_if->msk_cdata.msk_rx_tag = NULL;
2564 }
2565 if (sc_if->msk_cdata.msk_parent_tag) {
2566 bus_dma_tag_destroy(sc_if->msk_cdata.msk_parent_tag);
2567 sc_if->msk_cdata.msk_parent_tag = NULL;
2568 }
2569 }
2570
2571 static void
msk_rx_dma_jfree(struct msk_if_softc * sc_if)2572 msk_rx_dma_jfree(struct msk_if_softc *sc_if)
2573 {
2574 struct msk_rxdesc *jrxd;
2575 int i;
2576
2577 /* Jumbo Rx ring. */
2578 if (sc_if->msk_cdata.msk_jumbo_rx_ring_tag) {
2579 if (sc_if->msk_rdata.msk_jumbo_rx_ring_paddr)
2580 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_ring_tag,
2581 sc_if->msk_cdata.msk_jumbo_rx_ring_map);
2582 if (sc_if->msk_rdata.msk_jumbo_rx_ring)
2583 bus_dmamem_free(sc_if->msk_cdata.msk_jumbo_rx_ring_tag,
2584 sc_if->msk_rdata.msk_jumbo_rx_ring,
2585 sc_if->msk_cdata.msk_jumbo_rx_ring_map);
2586 sc_if->msk_rdata.msk_jumbo_rx_ring = NULL;
2587 sc_if->msk_rdata.msk_jumbo_rx_ring_paddr = 0;
2588 bus_dma_tag_destroy(sc_if->msk_cdata.msk_jumbo_rx_ring_tag);
2589 sc_if->msk_cdata.msk_jumbo_rx_ring_tag = NULL;
2590 }
2591 /* Jumbo Rx buffers. */
2592 if (sc_if->msk_cdata.msk_jumbo_rx_tag) {
2593 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) {
2594 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i];
2595 if (jrxd->rx_dmamap) {
2596 bus_dmamap_destroy(
2597 sc_if->msk_cdata.msk_jumbo_rx_tag,
2598 jrxd->rx_dmamap);
2599 jrxd->rx_dmamap = NULL;
2600 }
2601 }
2602 if (sc_if->msk_cdata.msk_jumbo_rx_sparemap) {
2603 bus_dmamap_destroy(sc_if->msk_cdata.msk_jumbo_rx_tag,
2604 sc_if->msk_cdata.msk_jumbo_rx_sparemap);
2605 sc_if->msk_cdata.msk_jumbo_rx_sparemap = 0;
2606 }
2607 bus_dma_tag_destroy(sc_if->msk_cdata.msk_jumbo_rx_tag);
2608 sc_if->msk_cdata.msk_jumbo_rx_tag = NULL;
2609 }
2610 }
2611
2612 static int
msk_encap(struct msk_if_softc * sc_if,struct mbuf ** m_head)2613 msk_encap(struct msk_if_softc *sc_if, struct mbuf **m_head)
2614 {
2615 struct msk_txdesc *txd, *txd_last;
2616 struct msk_tx_desc *tx_le;
2617 struct mbuf *m;
2618 bus_dmamap_t map;
2619 bus_dma_segment_t txsegs[MSK_MAXTXSEGS];
2620 uint32_t control, csum, prod, si;
2621 uint16_t offset, tcp_offset, tso_mtu;
2622 int error, i, nseg, tso;
2623
2624 MSK_IF_LOCK_ASSERT(sc_if);
2625
2626 tcp_offset = offset = 0;
2627 m = *m_head;
2628 if (((sc_if->msk_flags & MSK_FLAG_AUTOTX_CSUM) == 0 &&
2629 (m->m_pkthdr.csum_flags & MSK_CSUM_FEATURES) != 0) ||
2630 ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 &&
2631 (m->m_pkthdr.csum_flags & CSUM_TSO) != 0)) {
2632 /*
2633 * Since mbuf has no protocol specific structure information
2634 * in it we have to inspect protocol information here to
2635 * setup TSO and checksum offload. I don't know why Marvell
2636 * made a such decision in chip design because other GigE
2637 * hardwares normally takes care of all these chores in
2638 * hardware. However, TSO performance of Yukon II is very
2639 * good such that it's worth to implement it.
2640 */
2641 struct ether_header *eh;
2642 struct ip *ip;
2643 struct tcphdr *tcp;
2644
2645 if (M_WRITABLE(m) == 0) {
2646 /* Get a writable copy. */
2647 m = m_dup(*m_head, M_NOWAIT);
2648 m_freem(*m_head);
2649 if (m == NULL) {
2650 *m_head = NULL;
2651 return (ENOBUFS);
2652 }
2653 *m_head = m;
2654 }
2655
2656 offset = sizeof(struct ether_header);
2657 m = m_pullup(m, offset);
2658 if (m == NULL) {
2659 *m_head = NULL;
2660 return (ENOBUFS);
2661 }
2662 eh = mtod(m, struct ether_header *);
2663 /* Check if hardware VLAN insertion is off. */
2664 if (eh->ether_type == htons(ETHERTYPE_VLAN)) {
2665 offset = sizeof(struct ether_vlan_header);
2666 m = m_pullup(m, offset);
2667 if (m == NULL) {
2668 *m_head = NULL;
2669 return (ENOBUFS);
2670 }
2671 }
2672 m = m_pullup(m, offset + sizeof(struct ip));
2673 if (m == NULL) {
2674 *m_head = NULL;
2675 return (ENOBUFS);
2676 }
2677 ip = (struct ip *)(mtod(m, char *) + offset);
2678 offset += (ip->ip_hl << 2);
2679 tcp_offset = offset;
2680 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
2681 m = m_pullup(m, offset + sizeof(struct tcphdr));
2682 if (m == NULL) {
2683 *m_head = NULL;
2684 return (ENOBUFS);
2685 }
2686 tcp = (struct tcphdr *)(mtod(m, char *) + offset);
2687 offset += (tcp->th_off << 2);
2688 } else if ((sc_if->msk_flags & MSK_FLAG_AUTOTX_CSUM) == 0 &&
2689 (m->m_pkthdr.len < MSK_MIN_FRAMELEN) &&
2690 (m->m_pkthdr.csum_flags & CSUM_TCP) != 0) {
2691 /*
2692 * It seems that Yukon II has Tx checksum offload bug
2693 * for small TCP packets that's less than 60 bytes in
2694 * size (e.g. TCP window probe packet, pure ACK packet).
2695 * Common work around like padding with zeros to make
2696 * the frame minimum ethernet frame size didn't work at
2697 * all.
2698 * Instead of disabling checksum offload completely we
2699 * resort to S/W checksum routine when we encounter
2700 * short TCP frames.
2701 * Short UDP packets appear to be handled correctly by
2702 * Yukon II. Also I assume this bug does not happen on
2703 * controllers that use newer descriptor format or
2704 * automatic Tx checksum calculation.
2705 */
2706 m = m_pullup(m, offset + sizeof(struct tcphdr));
2707 if (m == NULL) {
2708 *m_head = NULL;
2709 return (ENOBUFS);
2710 }
2711 *(uint16_t *)(m->m_data + offset +
2712 m->m_pkthdr.csum_data) = in_cksum_skip(m,
2713 m->m_pkthdr.len, offset);
2714 m->m_pkthdr.csum_flags &= ~CSUM_TCP;
2715 }
2716 *m_head = m;
2717 }
2718
2719 prod = sc_if->msk_cdata.msk_tx_prod;
2720 txd = &sc_if->msk_cdata.msk_txdesc[prod];
2721 txd_last = txd;
2722 map = txd->tx_dmamap;
2723 error = bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_tx_tag, map,
2724 *m_head, txsegs, &nseg, BUS_DMA_NOWAIT);
2725 if (error == EFBIG) {
2726 m = m_collapse(*m_head, M_NOWAIT, MSK_MAXTXSEGS);
2727 if (m == NULL) {
2728 m_freem(*m_head);
2729 *m_head = NULL;
2730 return (ENOBUFS);
2731 }
2732 *m_head = m;
2733 error = bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_tx_tag,
2734 map, *m_head, txsegs, &nseg, BUS_DMA_NOWAIT);
2735 if (error != 0) {
2736 m_freem(*m_head);
2737 *m_head = NULL;
2738 return (error);
2739 }
2740 } else if (error != 0)
2741 return (error);
2742 if (nseg == 0) {
2743 m_freem(*m_head);
2744 *m_head = NULL;
2745 return (EIO);
2746 }
2747
2748 /* Check number of available descriptors. */
2749 if (sc_if->msk_cdata.msk_tx_cnt + nseg >=
2750 (MSK_TX_RING_CNT - MSK_RESERVED_TX_DESC_CNT)) {
2751 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, map);
2752 return (ENOBUFS);
2753 }
2754
2755 control = 0;
2756 tso = 0;
2757 tx_le = NULL;
2758
2759 /* Check TSO support. */
2760 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
2761 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0)
2762 tso_mtu = m->m_pkthdr.tso_segsz;
2763 else
2764 tso_mtu = offset + m->m_pkthdr.tso_segsz;
2765 if (tso_mtu != sc_if->msk_cdata.msk_tso_mtu) {
2766 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
2767 tx_le->msk_addr = htole32(tso_mtu);
2768 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0)
2769 tx_le->msk_control = htole32(OP_MSS | HW_OWNER);
2770 else
2771 tx_le->msk_control =
2772 htole32(OP_LRGLEN | HW_OWNER);
2773 sc_if->msk_cdata.msk_tx_cnt++;
2774 MSK_INC(prod, MSK_TX_RING_CNT);
2775 sc_if->msk_cdata.msk_tso_mtu = tso_mtu;
2776 }
2777 tso++;
2778 }
2779 /* Check if we have a VLAN tag to insert. */
2780 if ((m->m_flags & M_VLANTAG) != 0) {
2781 if (tx_le == NULL) {
2782 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
2783 tx_le->msk_addr = htole32(0);
2784 tx_le->msk_control = htole32(OP_VLAN | HW_OWNER |
2785 htons(m->m_pkthdr.ether_vtag));
2786 sc_if->msk_cdata.msk_tx_cnt++;
2787 MSK_INC(prod, MSK_TX_RING_CNT);
2788 } else {
2789 tx_le->msk_control |= htole32(OP_VLAN |
2790 htons(m->m_pkthdr.ether_vtag));
2791 }
2792 control |= INS_VLAN;
2793 }
2794 /* Check if we have to handle checksum offload. */
2795 if (tso == 0 && (m->m_pkthdr.csum_flags & MSK_CSUM_FEATURES) != 0) {
2796 if ((sc_if->msk_flags & MSK_FLAG_AUTOTX_CSUM) != 0)
2797 control |= CALSUM;
2798 else {
2799 control |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
2800 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0)
2801 control |= UDPTCP;
2802 /* Checksum write position. */
2803 csum = (tcp_offset + m->m_pkthdr.csum_data) & 0xffff;
2804 /* Checksum start position. */
2805 csum |= (uint32_t)tcp_offset << 16;
2806 if (csum != sc_if->msk_cdata.msk_last_csum) {
2807 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
2808 tx_le->msk_addr = htole32(csum);
2809 tx_le->msk_control = htole32(1 << 16 |
2810 (OP_TCPLISW | HW_OWNER));
2811 sc_if->msk_cdata.msk_tx_cnt++;
2812 MSK_INC(prod, MSK_TX_RING_CNT);
2813 sc_if->msk_cdata.msk_last_csum = csum;
2814 }
2815 }
2816 }
2817
2818 #ifdef MSK_64BIT_DMA
2819 if (MSK_ADDR_HI(txsegs[0].ds_addr) !=
2820 sc_if->msk_cdata.msk_tx_high_addr) {
2821 sc_if->msk_cdata.msk_tx_high_addr =
2822 MSK_ADDR_HI(txsegs[0].ds_addr);
2823 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
2824 tx_le->msk_addr = htole32(MSK_ADDR_HI(txsegs[0].ds_addr));
2825 tx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER);
2826 sc_if->msk_cdata.msk_tx_cnt++;
2827 MSK_INC(prod, MSK_TX_RING_CNT);
2828 }
2829 #endif
2830 si = prod;
2831 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
2832 tx_le->msk_addr = htole32(MSK_ADDR_LO(txsegs[0].ds_addr));
2833 if (tso == 0)
2834 tx_le->msk_control = htole32(txsegs[0].ds_len | control |
2835 OP_PACKET);
2836 else
2837 tx_le->msk_control = htole32(txsegs[0].ds_len | control |
2838 OP_LARGESEND);
2839 sc_if->msk_cdata.msk_tx_cnt++;
2840 MSK_INC(prod, MSK_TX_RING_CNT);
2841
2842 for (i = 1; i < nseg; i++) {
2843 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
2844 #ifdef MSK_64BIT_DMA
2845 if (MSK_ADDR_HI(txsegs[i].ds_addr) !=
2846 sc_if->msk_cdata.msk_tx_high_addr) {
2847 sc_if->msk_cdata.msk_tx_high_addr =
2848 MSK_ADDR_HI(txsegs[i].ds_addr);
2849 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
2850 tx_le->msk_addr =
2851 htole32(MSK_ADDR_HI(txsegs[i].ds_addr));
2852 tx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER);
2853 sc_if->msk_cdata.msk_tx_cnt++;
2854 MSK_INC(prod, MSK_TX_RING_CNT);
2855 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
2856 }
2857 #endif
2858 tx_le->msk_addr = htole32(MSK_ADDR_LO(txsegs[i].ds_addr));
2859 tx_le->msk_control = htole32(txsegs[i].ds_len | control |
2860 OP_BUFFER | HW_OWNER);
2861 sc_if->msk_cdata.msk_tx_cnt++;
2862 MSK_INC(prod, MSK_TX_RING_CNT);
2863 }
2864 /* Update producer index. */
2865 sc_if->msk_cdata.msk_tx_prod = prod;
2866
2867 /* Set EOP on the last descriptor. */
2868 prod = (prod + MSK_TX_RING_CNT - 1) % MSK_TX_RING_CNT;
2869 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
2870 tx_le->msk_control |= htole32(EOP);
2871
2872 /* Turn the first descriptor ownership to hardware. */
2873 tx_le = &sc_if->msk_rdata.msk_tx_ring[si];
2874 tx_le->msk_control |= htole32(HW_OWNER);
2875
2876 txd = &sc_if->msk_cdata.msk_txdesc[prod];
2877 map = txd_last->tx_dmamap;
2878 txd_last->tx_dmamap = txd->tx_dmamap;
2879 txd->tx_dmamap = map;
2880 txd->tx_m = m;
2881
2882 /* Sync descriptors. */
2883 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, map, BUS_DMASYNC_PREWRITE);
2884 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag,
2885 sc_if->msk_cdata.msk_tx_ring_map,
2886 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2887
2888 return (0);
2889 }
2890
2891 static void
msk_start(if_t ifp)2892 msk_start(if_t ifp)
2893 {
2894 struct msk_if_softc *sc_if;
2895
2896 sc_if = if_getsoftc(ifp);
2897 MSK_IF_LOCK(sc_if);
2898 msk_start_locked(ifp);
2899 MSK_IF_UNLOCK(sc_if);
2900 }
2901
2902 static void
msk_start_locked(if_t ifp)2903 msk_start_locked(if_t ifp)
2904 {
2905 struct msk_if_softc *sc_if;
2906 struct mbuf *m_head;
2907 int enq;
2908
2909 sc_if = if_getsoftc(ifp);
2910 MSK_IF_LOCK_ASSERT(sc_if);
2911
2912 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
2913 IFF_DRV_RUNNING || (sc_if->msk_flags & MSK_FLAG_LINK) == 0)
2914 return;
2915
2916 for (enq = 0; !if_sendq_empty(ifp) &&
2917 sc_if->msk_cdata.msk_tx_cnt <
2918 (MSK_TX_RING_CNT - MSK_RESERVED_TX_DESC_CNT); ) {
2919 m_head = if_dequeue(ifp);
2920 if (m_head == NULL)
2921 break;
2922 /*
2923 * Pack the data into the transmit ring. If we
2924 * don't have room, set the OACTIVE flag and wait
2925 * for the NIC to drain the ring.
2926 */
2927 if (msk_encap(sc_if, &m_head) != 0) {
2928 if (m_head == NULL)
2929 break;
2930 if_sendq_prepend(ifp, m_head);
2931 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
2932 break;
2933 }
2934
2935 enq++;
2936 /*
2937 * If there's a BPF listener, bounce a copy of this frame
2938 * to him.
2939 */
2940 ETHER_BPF_MTAP(ifp, m_head);
2941 }
2942
2943 if (enq > 0) {
2944 /* Transmit */
2945 CSR_WRITE_2(sc_if->msk_softc,
2946 Y2_PREF_Q_ADDR(sc_if->msk_txq, PREF_UNIT_PUT_IDX_REG),
2947 sc_if->msk_cdata.msk_tx_prod);
2948
2949 /* Set a timeout in case the chip goes out to lunch. */
2950 sc_if->msk_watchdog_timer = MSK_TX_TIMEOUT;
2951 }
2952 }
2953
2954 static void
msk_watchdog(struct msk_if_softc * sc_if)2955 msk_watchdog(struct msk_if_softc *sc_if)
2956 {
2957 if_t ifp;
2958
2959 MSK_IF_LOCK_ASSERT(sc_if);
2960
2961 if (sc_if->msk_watchdog_timer == 0 || --sc_if->msk_watchdog_timer)
2962 return;
2963 ifp = sc_if->msk_ifp;
2964 if ((sc_if->msk_flags & MSK_FLAG_LINK) == 0) {
2965 if (bootverbose)
2966 if_printf(sc_if->msk_ifp, "watchdog timeout "
2967 "(missed link)\n");
2968 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
2969 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
2970 msk_init_locked(sc_if);
2971 return;
2972 }
2973
2974 if_printf(ifp, "watchdog timeout\n");
2975 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
2976 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
2977 msk_init_locked(sc_if);
2978 if (!if_sendq_empty(ifp))
2979 msk_start_locked(ifp);
2980 }
2981
2982 static int
mskc_shutdown(device_t dev)2983 mskc_shutdown(device_t dev)
2984 {
2985 struct msk_softc *sc;
2986 int i;
2987
2988 sc = device_get_softc(dev);
2989 MSK_LOCK(sc);
2990 for (i = 0; i < sc->msk_num_port; i++) {
2991 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL &&
2992 ((if_getdrvflags(sc->msk_if[i]->msk_ifp) &
2993 IFF_DRV_RUNNING) != 0))
2994 msk_stop(sc->msk_if[i]);
2995 }
2996 MSK_UNLOCK(sc);
2997
2998 /* Put hardware reset. */
2999 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET);
3000 return (0);
3001 }
3002
3003 static int
mskc_suspend(device_t dev)3004 mskc_suspend(device_t dev)
3005 {
3006 struct msk_softc *sc;
3007 int i;
3008
3009 sc = device_get_softc(dev);
3010
3011 MSK_LOCK(sc);
3012
3013 for (i = 0; i < sc->msk_num_port; i++) {
3014 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL &&
3015 ((if_getdrvflags(sc->msk_if[i]->msk_ifp) &
3016 IFF_DRV_RUNNING) != 0))
3017 msk_stop(sc->msk_if[i]);
3018 }
3019
3020 /* Disable all interrupts. */
3021 CSR_WRITE_4(sc, B0_IMSK, 0);
3022 CSR_READ_4(sc, B0_IMSK);
3023 CSR_WRITE_4(sc, B0_HWE_IMSK, 0);
3024 CSR_READ_4(sc, B0_HWE_IMSK);
3025
3026 msk_phy_power(sc, MSK_PHY_POWERDOWN);
3027
3028 /* Put hardware reset. */
3029 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET);
3030 sc->msk_pflags |= MSK_FLAG_SUSPEND;
3031
3032 MSK_UNLOCK(sc);
3033
3034 return (0);
3035 }
3036
3037 static int
mskc_resume(device_t dev)3038 mskc_resume(device_t dev)
3039 {
3040 struct msk_softc *sc;
3041 int i;
3042
3043 sc = device_get_softc(dev);
3044
3045 MSK_LOCK(sc);
3046
3047 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_3, 0);
3048 mskc_reset(sc);
3049 for (i = 0; i < sc->msk_num_port; i++) {
3050 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL &&
3051 ((if_getflags(sc->msk_if[i]->msk_ifp) & IFF_UP) != 0)) {
3052 if_setdrvflagbits(sc->msk_if[i]->msk_ifp, 0,
3053 IFF_DRV_RUNNING);
3054 msk_init_locked(sc->msk_if[i]);
3055 }
3056 }
3057 sc->msk_pflags &= ~MSK_FLAG_SUSPEND;
3058
3059 MSK_UNLOCK(sc);
3060
3061 return (0);
3062 }
3063
3064 #ifndef __NO_STRICT_ALIGNMENT
3065 static __inline void
msk_fixup_rx(struct mbuf * m)3066 msk_fixup_rx(struct mbuf *m)
3067 {
3068 int i;
3069 uint16_t *src, *dst;
3070
3071 src = mtod(m, uint16_t *);
3072 dst = src - 3;
3073
3074 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++)
3075 *dst++ = *src++;
3076
3077 m->m_data -= (MSK_RX_BUF_ALIGN - ETHER_ALIGN);
3078 }
3079 #endif
3080
3081 static __inline void
msk_rxcsum(struct msk_if_softc * sc_if,uint32_t control,struct mbuf * m)3082 msk_rxcsum(struct msk_if_softc *sc_if, uint32_t control, struct mbuf *m)
3083 {
3084 struct ether_header *eh;
3085 struct ip *ip;
3086 struct udphdr *uh;
3087 int32_t hlen, len, pktlen, temp32;
3088 uint16_t csum, *opts;
3089
3090 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0) {
3091 if ((control & (CSS_IPV4 | CSS_IPFRAG)) == CSS_IPV4) {
3092 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
3093 if ((control & CSS_IPV4_CSUM_OK) != 0)
3094 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
3095 if ((control & (CSS_TCP | CSS_UDP)) != 0 &&
3096 (control & (CSS_TCPUDP_CSUM_OK)) != 0) {
3097 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
3098 CSUM_PSEUDO_HDR;
3099 m->m_pkthdr.csum_data = 0xffff;
3100 }
3101 }
3102 return;
3103 }
3104 /*
3105 * Marvell Yukon controllers that support OP_RXCHKS has known
3106 * to have various Rx checksum offloading bugs. These
3107 * controllers can be configured to compute simple checksum
3108 * at two different positions. So we can compute IP and TCP/UDP
3109 * checksum at the same time. We intentionally have controller
3110 * compute TCP/UDP checksum twice by specifying the same
3111 * checksum start position and compare the result. If the value
3112 * is different it would indicate the hardware logic was wrong.
3113 */
3114 if ((sc_if->msk_csum & 0xFFFF) != (sc_if->msk_csum >> 16)) {
3115 if (bootverbose)
3116 device_printf(sc_if->msk_if_dev,
3117 "Rx checksum value mismatch!\n");
3118 return;
3119 }
3120 pktlen = m->m_pkthdr.len;
3121 if (pktlen < sizeof(struct ether_header) + sizeof(struct ip))
3122 return;
3123 eh = mtod(m, struct ether_header *);
3124 if (eh->ether_type != htons(ETHERTYPE_IP))
3125 return;
3126 ip = (struct ip *)(eh + 1);
3127 if (ip->ip_v != IPVERSION)
3128 return;
3129
3130 hlen = ip->ip_hl << 2;
3131 pktlen -= sizeof(struct ether_header);
3132 if (hlen < sizeof(struct ip))
3133 return;
3134 if (ntohs(ip->ip_len) < hlen)
3135 return;
3136 if (ntohs(ip->ip_len) != pktlen)
3137 return;
3138 if (ip->ip_off & htons(IP_MF | IP_OFFMASK))
3139 return; /* can't handle fragmented packet. */
3140
3141 switch (ip->ip_p) {
3142 case IPPROTO_TCP:
3143 if (pktlen < (hlen + sizeof(struct tcphdr)))
3144 return;
3145 break;
3146 case IPPROTO_UDP:
3147 if (pktlen < (hlen + sizeof(struct udphdr)))
3148 return;
3149 uh = (struct udphdr *)((caddr_t)ip + hlen);
3150 if (uh->uh_sum == 0)
3151 return; /* no checksum */
3152 break;
3153 default:
3154 return;
3155 }
3156 csum = bswap16(sc_if->msk_csum & 0xFFFF);
3157 /* Checksum fixup for IP options. */
3158 len = hlen - sizeof(struct ip);
3159 if (len > 0) {
3160 opts = (uint16_t *)(ip + 1);
3161 for (; len > 0; len -= sizeof(uint16_t), opts++) {
3162 temp32 = csum - *opts;
3163 temp32 = (temp32 >> 16) + (temp32 & 65535);
3164 csum = temp32 & 65535;
3165 }
3166 }
3167 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID;
3168 m->m_pkthdr.csum_data = csum;
3169 }
3170
3171 static void
msk_rxeof(struct msk_if_softc * sc_if,uint32_t status,uint32_t control,int len)3172 msk_rxeof(struct msk_if_softc *sc_if, uint32_t status, uint32_t control,
3173 int len)
3174 {
3175 struct mbuf *m;
3176 if_t ifp;
3177 struct msk_rxdesc *rxd;
3178 int cons, rxlen;
3179
3180 ifp = sc_if->msk_ifp;
3181
3182 MSK_IF_LOCK_ASSERT(sc_if);
3183
3184 cons = sc_if->msk_cdata.msk_rx_cons;
3185 do {
3186 rxlen = status >> 16;
3187 if ((status & GMR_FS_VLAN) != 0 &&
3188 (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0)
3189 rxlen -= ETHER_VLAN_ENCAP_LEN;
3190 if ((sc_if->msk_flags & MSK_FLAG_NORXCHK) != 0) {
3191 /*
3192 * For controllers that returns bogus status code
3193 * just do minimal check and let upper stack
3194 * handle this frame.
3195 */
3196 if (len > MSK_MAX_FRAMELEN || len < ETHER_HDR_LEN) {
3197 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
3198 msk_discard_rxbuf(sc_if, cons);
3199 break;
3200 }
3201 } else if (len > sc_if->msk_framesize ||
3202 ((status & GMR_FS_ANY_ERR) != 0) ||
3203 ((status & GMR_FS_RX_OK) == 0) || (rxlen != len)) {
3204 /* Don't count flow-control packet as errors. */
3205 if ((status & GMR_FS_GOOD_FC) == 0)
3206 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
3207 msk_discard_rxbuf(sc_if, cons);
3208 break;
3209 }
3210 #ifdef MSK_64BIT_DMA
3211 rxd = &sc_if->msk_cdata.msk_rxdesc[(cons + 1) %
3212 MSK_RX_RING_CNT];
3213 #else
3214 rxd = &sc_if->msk_cdata.msk_rxdesc[cons];
3215 #endif
3216 m = rxd->rx_m;
3217 if (msk_newbuf(sc_if, cons) != 0) {
3218 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
3219 /* Reuse old buffer. */
3220 msk_discard_rxbuf(sc_if, cons);
3221 break;
3222 }
3223 m->m_pkthdr.rcvif = ifp;
3224 m->m_pkthdr.len = m->m_len = len;
3225 #ifndef __NO_STRICT_ALIGNMENT
3226 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0)
3227 msk_fixup_rx(m);
3228 #endif
3229 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
3230 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0)
3231 msk_rxcsum(sc_if, control, m);
3232 /* Check for VLAN tagged packets. */
3233 if ((status & GMR_FS_VLAN) != 0 &&
3234 (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) {
3235 m->m_pkthdr.ether_vtag = sc_if->msk_vtag;
3236 m->m_flags |= M_VLANTAG;
3237 }
3238 MSK_IF_UNLOCK(sc_if);
3239 if_input(ifp, m);
3240 MSK_IF_LOCK(sc_if);
3241 } while (0);
3242
3243 MSK_RX_INC(sc_if->msk_cdata.msk_rx_cons, MSK_RX_RING_CNT);
3244 MSK_RX_INC(sc_if->msk_cdata.msk_rx_prod, MSK_RX_RING_CNT);
3245 }
3246
3247 static void
msk_jumbo_rxeof(struct msk_if_softc * sc_if,uint32_t status,uint32_t control,int len)3248 msk_jumbo_rxeof(struct msk_if_softc *sc_if, uint32_t status, uint32_t control,
3249 int len)
3250 {
3251 struct mbuf *m;
3252 if_t ifp;
3253 struct msk_rxdesc *jrxd;
3254 int cons, rxlen;
3255
3256 ifp = sc_if->msk_ifp;
3257
3258 MSK_IF_LOCK_ASSERT(sc_if);
3259
3260 cons = sc_if->msk_cdata.msk_rx_cons;
3261 do {
3262 rxlen = status >> 16;
3263 if ((status & GMR_FS_VLAN) != 0 &&
3264 (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0)
3265 rxlen -= ETHER_VLAN_ENCAP_LEN;
3266 if (len > sc_if->msk_framesize ||
3267 ((status & GMR_FS_ANY_ERR) != 0) ||
3268 ((status & GMR_FS_RX_OK) == 0) || (rxlen != len)) {
3269 /* Don't count flow-control packet as errors. */
3270 if ((status & GMR_FS_GOOD_FC) == 0)
3271 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
3272 msk_discard_jumbo_rxbuf(sc_if, cons);
3273 break;
3274 }
3275 #ifdef MSK_64BIT_DMA
3276 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[(cons + 1) %
3277 MSK_JUMBO_RX_RING_CNT];
3278 #else
3279 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[cons];
3280 #endif
3281 m = jrxd->rx_m;
3282 if (msk_jumbo_newbuf(sc_if, cons) != 0) {
3283 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
3284 /* Reuse old buffer. */
3285 msk_discard_jumbo_rxbuf(sc_if, cons);
3286 break;
3287 }
3288 m->m_pkthdr.rcvif = ifp;
3289 m->m_pkthdr.len = m->m_len = len;
3290 #ifndef __NO_STRICT_ALIGNMENT
3291 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0)
3292 msk_fixup_rx(m);
3293 #endif
3294 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
3295 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0)
3296 msk_rxcsum(sc_if, control, m);
3297 /* Check for VLAN tagged packets. */
3298 if ((status & GMR_FS_VLAN) != 0 &&
3299 (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) {
3300 m->m_pkthdr.ether_vtag = sc_if->msk_vtag;
3301 m->m_flags |= M_VLANTAG;
3302 }
3303 MSK_IF_UNLOCK(sc_if);
3304 if_input(ifp, m);
3305 MSK_IF_LOCK(sc_if);
3306 } while (0);
3307
3308 MSK_RX_INC(sc_if->msk_cdata.msk_rx_cons, MSK_JUMBO_RX_RING_CNT);
3309 MSK_RX_INC(sc_if->msk_cdata.msk_rx_prod, MSK_JUMBO_RX_RING_CNT);
3310 }
3311
3312 static void
msk_txeof(struct msk_if_softc * sc_if,int idx)3313 msk_txeof(struct msk_if_softc *sc_if, int idx)
3314 {
3315 struct msk_txdesc *txd;
3316 struct msk_tx_desc *cur_tx;
3317 if_t ifp;
3318 uint32_t control;
3319 int cons, prog;
3320
3321 MSK_IF_LOCK_ASSERT(sc_if);
3322
3323 ifp = sc_if->msk_ifp;
3324
3325 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag,
3326 sc_if->msk_cdata.msk_tx_ring_map,
3327 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
3328 /*
3329 * Go through our tx ring and free mbufs for those
3330 * frames that have been sent.
3331 */
3332 cons = sc_if->msk_cdata.msk_tx_cons;
3333 prog = 0;
3334 for (; cons != idx; MSK_INC(cons, MSK_TX_RING_CNT)) {
3335 if (sc_if->msk_cdata.msk_tx_cnt <= 0)
3336 break;
3337 prog++;
3338 cur_tx = &sc_if->msk_rdata.msk_tx_ring[cons];
3339 control = le32toh(cur_tx->msk_control);
3340 sc_if->msk_cdata.msk_tx_cnt--;
3341 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
3342 if ((control & EOP) == 0)
3343 continue;
3344 txd = &sc_if->msk_cdata.msk_txdesc[cons];
3345 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, txd->tx_dmamap,
3346 BUS_DMASYNC_POSTWRITE);
3347 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, txd->tx_dmamap);
3348
3349 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
3350 KASSERT(txd->tx_m != NULL, ("%s: freeing NULL mbuf!",
3351 __func__));
3352 m_freem(txd->tx_m);
3353 txd->tx_m = NULL;
3354 }
3355
3356 if (prog > 0) {
3357 sc_if->msk_cdata.msk_tx_cons = cons;
3358 if (sc_if->msk_cdata.msk_tx_cnt == 0)
3359 sc_if->msk_watchdog_timer = 0;
3360 /* No need to sync LEs as we didn't update LEs. */
3361 }
3362 }
3363
3364 static void
msk_tick(void * xsc_if)3365 msk_tick(void *xsc_if)
3366 {
3367 struct epoch_tracker et;
3368 struct msk_if_softc *sc_if;
3369 struct mii_data *mii;
3370
3371 sc_if = xsc_if;
3372
3373 MSK_IF_LOCK_ASSERT(sc_if);
3374
3375 mii = device_get_softc(sc_if->msk_miibus);
3376
3377 mii_tick(mii);
3378 if ((sc_if->msk_flags & MSK_FLAG_LINK) == 0)
3379 msk_miibus_statchg(sc_if->msk_if_dev);
3380 NET_EPOCH_ENTER(et);
3381 msk_handle_events(sc_if->msk_softc);
3382 NET_EPOCH_EXIT(et);
3383 msk_watchdog(sc_if);
3384 callout_reset(&sc_if->msk_tick_ch, hz, msk_tick, sc_if);
3385 }
3386
3387 static void
msk_intr_phy(struct msk_if_softc * sc_if)3388 msk_intr_phy(struct msk_if_softc *sc_if)
3389 {
3390 uint16_t status;
3391
3392 msk_phy_readreg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_STAT);
3393 status = msk_phy_readreg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_STAT);
3394 /* Handle FIFO Underrun/Overflow? */
3395 if ((status & PHY_M_IS_FIFO_ERROR))
3396 device_printf(sc_if->msk_if_dev,
3397 "PHY FIFO underrun/overflow.\n");
3398 }
3399
3400 static void
msk_intr_gmac(struct msk_if_softc * sc_if)3401 msk_intr_gmac(struct msk_if_softc *sc_if)
3402 {
3403 struct msk_softc *sc;
3404 uint8_t status;
3405
3406 sc = sc_if->msk_softc;
3407 status = CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC));
3408
3409 /* GMAC Rx FIFO overrun. */
3410 if ((status & GM_IS_RX_FF_OR) != 0)
3411 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T),
3412 GMF_CLI_RX_FO);
3413 /* GMAC Tx FIFO underrun. */
3414 if ((status & GM_IS_TX_FF_UR) != 0) {
3415 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
3416 GMF_CLI_TX_FU);
3417 device_printf(sc_if->msk_if_dev, "Tx FIFO underrun!\n");
3418 /*
3419 * XXX
3420 * In case of Tx underrun, we may need to flush/reset
3421 * Tx MAC but that would also require resynchronization
3422 * with status LEs. Reinitializing status LEs would
3423 * affect other port in dual MAC configuration so it
3424 * should be avoided as possible as we can.
3425 * Due to lack of documentation it's all vague guess but
3426 * it needs more investigation.
3427 */
3428 }
3429 }
3430
3431 static void
msk_handle_hwerr(struct msk_if_softc * sc_if,uint32_t status)3432 msk_handle_hwerr(struct msk_if_softc *sc_if, uint32_t status)
3433 {
3434 struct msk_softc *sc;
3435
3436 sc = sc_if->msk_softc;
3437 if ((status & Y2_IS_PAR_RD1) != 0) {
3438 device_printf(sc_if->msk_if_dev,
3439 "RAM buffer read parity error\n");
3440 /* Clear IRQ. */
3441 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(sc_if->msk_port, B3_RI_CTRL),
3442 RI_CLR_RD_PERR);
3443 }
3444 if ((status & Y2_IS_PAR_WR1) != 0) {
3445 device_printf(sc_if->msk_if_dev,
3446 "RAM buffer write parity error\n");
3447 /* Clear IRQ. */
3448 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(sc_if->msk_port, B3_RI_CTRL),
3449 RI_CLR_WR_PERR);
3450 }
3451 if ((status & Y2_IS_PAR_MAC1) != 0) {
3452 device_printf(sc_if->msk_if_dev, "Tx MAC parity error\n");
3453 /* Clear IRQ. */
3454 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
3455 GMF_CLI_TX_PE);
3456 }
3457 if ((status & Y2_IS_PAR_RX1) != 0) {
3458 device_printf(sc_if->msk_if_dev, "Rx parity error\n");
3459 /* Clear IRQ. */
3460 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_IRQ_PAR);
3461 }
3462 if ((status & (Y2_IS_TCP_TXS1 | Y2_IS_TCP_TXA1)) != 0) {
3463 device_printf(sc_if->msk_if_dev, "TCP segmentation error\n");
3464 /* Clear IRQ. */
3465 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_IRQ_TCP);
3466 }
3467 }
3468
3469 static void
msk_intr_hwerr(struct msk_softc * sc)3470 msk_intr_hwerr(struct msk_softc *sc)
3471 {
3472 uint32_t status;
3473 uint32_t tlphead[4];
3474
3475 status = CSR_READ_4(sc, B0_HWE_ISRC);
3476 /* Time Stamp timer overflow. */
3477 if ((status & Y2_IS_TIST_OV) != 0)
3478 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
3479 if ((status & Y2_IS_PCI_NEXP) != 0) {
3480 /*
3481 * PCI Express Error occurred which is not described in PEX
3482 * spec.
3483 * This error is also mapped either to Master Abort(
3484 * Y2_IS_MST_ERR) or Target Abort (Y2_IS_IRQ_STAT) bit and
3485 * can only be cleared there.
3486 */
3487 device_printf(sc->msk_dev,
3488 "PCI Express protocol violation error\n");
3489 }
3490
3491 if ((status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) != 0) {
3492 uint16_t v16;
3493
3494 if ((status & Y2_IS_MST_ERR) != 0)
3495 device_printf(sc->msk_dev,
3496 "unexpected IRQ Status error\n");
3497 else
3498 device_printf(sc->msk_dev,
3499 "unexpected IRQ Master error\n");
3500 /* Reset all bits in the PCI status register. */
3501 v16 = pci_read_config(sc->msk_dev, PCIR_STATUS, 2);
3502 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3503 pci_write_config(sc->msk_dev, PCIR_STATUS, v16 |
3504 PCIM_STATUS_PERR | PCIM_STATUS_SERR | PCIM_STATUS_RMABORT |
3505 PCIM_STATUS_RTABORT | PCIM_STATUS_MDPERR, 2);
3506 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3507 }
3508
3509 /* Check for PCI Express Uncorrectable Error. */
3510 if ((status & Y2_IS_PCI_EXP) != 0) {
3511 uint32_t v32;
3512
3513 /*
3514 * On PCI Express bus bridges are called root complexes (RC).
3515 * PCI Express errors are recognized by the root complex too,
3516 * which requests the system to handle the problem. After
3517 * error occurrence it may be that no access to the adapter
3518 * may be performed any longer.
3519 */
3520
3521 v32 = CSR_PCI_READ_4(sc, PEX_UNC_ERR_STAT);
3522 if ((v32 & PEX_UNSUP_REQ) != 0) {
3523 /* Ignore unsupported request error. */
3524 device_printf(sc->msk_dev,
3525 "Uncorrectable PCI Express error\n");
3526 }
3527 if ((v32 & (PEX_FATAL_ERRORS | PEX_POIS_TLP)) != 0) {
3528 int i;
3529
3530 /* Get TLP header form Log Registers. */
3531 for (i = 0; i < 4; i++)
3532 tlphead[i] = CSR_PCI_READ_4(sc,
3533 PEX_HEADER_LOG + i * 4);
3534 /* Check for vendor defined broadcast message. */
3535 if (!(tlphead[0] == 0x73004001 && tlphead[1] == 0x7f)) {
3536 sc->msk_intrhwemask &= ~Y2_IS_PCI_EXP;
3537 CSR_WRITE_4(sc, B0_HWE_IMSK,
3538 sc->msk_intrhwemask);
3539 CSR_READ_4(sc, B0_HWE_IMSK);
3540 }
3541 }
3542 /* Clear the interrupt. */
3543 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3544 CSR_PCI_WRITE_4(sc, PEX_UNC_ERR_STAT, 0xffffffff);
3545 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3546 }
3547
3548 if ((status & Y2_HWE_L1_MASK) != 0 && sc->msk_if[MSK_PORT_A] != NULL)
3549 msk_handle_hwerr(sc->msk_if[MSK_PORT_A], status);
3550 if ((status & Y2_HWE_L2_MASK) != 0 && sc->msk_if[MSK_PORT_B] != NULL)
3551 msk_handle_hwerr(sc->msk_if[MSK_PORT_B], status >> 8);
3552 }
3553
3554 static __inline void
msk_rxput(struct msk_if_softc * sc_if)3555 msk_rxput(struct msk_if_softc *sc_if)
3556 {
3557 struct msk_softc *sc;
3558
3559 sc = sc_if->msk_softc;
3560 if (sc_if->msk_framesize > (MCLBYTES - MSK_RX_BUF_ALIGN))
3561 bus_dmamap_sync(
3562 sc_if->msk_cdata.msk_jumbo_rx_ring_tag,
3563 sc_if->msk_cdata.msk_jumbo_rx_ring_map,
3564 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3565 else
3566 bus_dmamap_sync(
3567 sc_if->msk_cdata.msk_rx_ring_tag,
3568 sc_if->msk_cdata.msk_rx_ring_map,
3569 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3570 CSR_WRITE_2(sc, Y2_PREF_Q_ADDR(sc_if->msk_rxq,
3571 PREF_UNIT_PUT_IDX_REG), sc_if->msk_cdata.msk_rx_prod);
3572 }
3573
3574 static int
msk_handle_events(struct msk_softc * sc)3575 msk_handle_events(struct msk_softc *sc)
3576 {
3577 struct msk_if_softc *sc_if;
3578 int rxput[2];
3579 struct msk_stat_desc *sd;
3580 uint32_t control, status;
3581 int cons, len, port, rxprog;
3582
3583 if (sc->msk_stat_cons == CSR_READ_2(sc, STAT_PUT_IDX))
3584 return (0);
3585
3586 /* Sync status LEs. */
3587 bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map,
3588 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
3589
3590 rxput[MSK_PORT_A] = rxput[MSK_PORT_B] = 0;
3591 rxprog = 0;
3592 cons = sc->msk_stat_cons;
3593 for (;;) {
3594 sd = &sc->msk_stat_ring[cons];
3595 control = le32toh(sd->msk_control);
3596 if ((control & HW_OWNER) == 0)
3597 break;
3598 control &= ~HW_OWNER;
3599 sd->msk_control = htole32(control);
3600 status = le32toh(sd->msk_status);
3601 len = control & STLE_LEN_MASK;
3602 port = (control >> 16) & 0x01;
3603 sc_if = sc->msk_if[port];
3604 if (sc_if == NULL) {
3605 device_printf(sc->msk_dev, "invalid port opcode "
3606 "0x%08x\n", control & STLE_OP_MASK);
3607 continue;
3608 }
3609
3610 switch (control & STLE_OP_MASK) {
3611 case OP_RXVLAN:
3612 sc_if->msk_vtag = ntohs(len);
3613 break;
3614 case OP_RXCHKSVLAN:
3615 sc_if->msk_vtag = ntohs(len);
3616 /* FALLTHROUGH */
3617 case OP_RXCHKS:
3618 sc_if->msk_csum = status;
3619 break;
3620 case OP_RXSTAT:
3621 if (!(if_getdrvflags(sc_if->msk_ifp) & IFF_DRV_RUNNING))
3622 break;
3623 if (sc_if->msk_framesize >
3624 (MCLBYTES - MSK_RX_BUF_ALIGN))
3625 msk_jumbo_rxeof(sc_if, status, control, len);
3626 else
3627 msk_rxeof(sc_if, status, control, len);
3628 rxprog++;
3629 /*
3630 * Because there is no way to sync single Rx LE
3631 * put the DMA sync operation off until the end of
3632 * event processing.
3633 */
3634 rxput[port]++;
3635 /* Update prefetch unit if we've passed water mark. */
3636 if (rxput[port] >= sc_if->msk_cdata.msk_rx_putwm) {
3637 msk_rxput(sc_if);
3638 rxput[port] = 0;
3639 }
3640 break;
3641 case OP_TXINDEXLE:
3642 if (sc->msk_if[MSK_PORT_A] != NULL)
3643 msk_txeof(sc->msk_if[MSK_PORT_A],
3644 status & STLE_TXA1_MSKL);
3645 if (sc->msk_if[MSK_PORT_B] != NULL)
3646 msk_txeof(sc->msk_if[MSK_PORT_B],
3647 ((status & STLE_TXA2_MSKL) >>
3648 STLE_TXA2_SHIFTL) |
3649 ((len & STLE_TXA2_MSKH) <<
3650 STLE_TXA2_SHIFTH));
3651 break;
3652 default:
3653 device_printf(sc->msk_dev, "unhandled opcode 0x%08x\n",
3654 control & STLE_OP_MASK);
3655 break;
3656 }
3657 MSK_INC(cons, sc->msk_stat_count);
3658 if (rxprog > sc->msk_process_limit)
3659 break;
3660 }
3661
3662 sc->msk_stat_cons = cons;
3663 bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map,
3664 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3665
3666 if (rxput[MSK_PORT_A] > 0)
3667 msk_rxput(sc->msk_if[MSK_PORT_A]);
3668 if (rxput[MSK_PORT_B] > 0)
3669 msk_rxput(sc->msk_if[MSK_PORT_B]);
3670
3671 return (sc->msk_stat_cons != CSR_READ_2(sc, STAT_PUT_IDX));
3672 }
3673
3674 static void
msk_intr(void * xsc)3675 msk_intr(void *xsc)
3676 {
3677 struct msk_softc *sc;
3678 struct msk_if_softc *sc_if0, *sc_if1;
3679 if_t ifp0, ifp1;
3680 uint32_t status;
3681 int domore;
3682
3683 sc = xsc;
3684 MSK_LOCK(sc);
3685
3686 /* Reading B0_Y2_SP_ISRC2 masks further interrupts. */
3687 status = CSR_READ_4(sc, B0_Y2_SP_ISRC2);
3688 if (status == 0 || status == 0xffffffff ||
3689 (sc->msk_pflags & MSK_FLAG_SUSPEND) != 0 ||
3690 (status & sc->msk_intrmask) == 0) {
3691 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2);
3692 MSK_UNLOCK(sc);
3693 return;
3694 }
3695
3696 sc_if0 = sc->msk_if[MSK_PORT_A];
3697 sc_if1 = sc->msk_if[MSK_PORT_B];
3698 ifp0 = ifp1 = NULL;
3699 if (sc_if0 != NULL)
3700 ifp0 = sc_if0->msk_ifp;
3701 if (sc_if1 != NULL)
3702 ifp1 = sc_if1->msk_ifp;
3703
3704 if ((status & Y2_IS_IRQ_PHY1) != 0 && sc_if0 != NULL)
3705 msk_intr_phy(sc_if0);
3706 if ((status & Y2_IS_IRQ_PHY2) != 0 && sc_if1 != NULL)
3707 msk_intr_phy(sc_if1);
3708 if ((status & Y2_IS_IRQ_MAC1) != 0 && sc_if0 != NULL)
3709 msk_intr_gmac(sc_if0);
3710 if ((status & Y2_IS_IRQ_MAC2) != 0 && sc_if1 != NULL)
3711 msk_intr_gmac(sc_if1);
3712 if ((status & (Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2)) != 0) {
3713 device_printf(sc->msk_dev, "Rx descriptor error\n");
3714 sc->msk_intrmask &= ~(Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2);
3715 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask);
3716 CSR_READ_4(sc, B0_IMSK);
3717 }
3718 if ((status & (Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2)) != 0) {
3719 device_printf(sc->msk_dev, "Tx descriptor error\n");
3720 sc->msk_intrmask &= ~(Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2);
3721 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask);
3722 CSR_READ_4(sc, B0_IMSK);
3723 }
3724 if ((status & Y2_IS_HW_ERR) != 0)
3725 msk_intr_hwerr(sc);
3726
3727 domore = msk_handle_events(sc);
3728 if ((status & Y2_IS_STAT_BMU) != 0 && domore == 0)
3729 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_CLR_IRQ);
3730
3731 /* Reenable interrupts. */
3732 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2);
3733
3734 if (ifp0 != NULL && (if_getdrvflags(ifp0) & IFF_DRV_RUNNING) != 0 &&
3735 !if_sendq_empty(ifp0))
3736 msk_start_locked(ifp0);
3737 if (ifp1 != NULL && (if_getdrvflags(ifp1) & IFF_DRV_RUNNING) != 0 &&
3738 !if_sendq_empty(ifp1))
3739 msk_start_locked(ifp1);
3740
3741 MSK_UNLOCK(sc);
3742 }
3743
3744 static void
msk_set_tx_stfwd(struct msk_if_softc * sc_if)3745 msk_set_tx_stfwd(struct msk_if_softc *sc_if)
3746 {
3747 struct msk_softc *sc;
3748 if_t ifp;
3749
3750 ifp = sc_if->msk_ifp;
3751 sc = sc_if->msk_softc;
3752 if ((sc->msk_hw_id == CHIP_ID_YUKON_EX &&
3753 sc->msk_hw_rev != CHIP_REV_YU_EX_A0) ||
3754 sc->msk_hw_id >= CHIP_ID_YUKON_SUPR) {
3755 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
3756 TX_STFW_ENA);
3757 } else {
3758 if (if_getmtu(ifp) > ETHERMTU) {
3759 /* Set Tx GMAC FIFO Almost Empty Threshold. */
3760 CSR_WRITE_4(sc,
3761 MR_ADDR(sc_if->msk_port, TX_GMF_AE_THR),
3762 MSK_ECU_JUMBO_WM << 16 | MSK_ECU_AE_THR);
3763 /* Disable Store & Forward mode for Tx. */
3764 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
3765 TX_STFW_DIS);
3766 } else {
3767 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
3768 TX_STFW_ENA);
3769 }
3770 }
3771 }
3772
3773 static void
msk_init(void * xsc)3774 msk_init(void *xsc)
3775 {
3776 struct msk_if_softc *sc_if = xsc;
3777
3778 MSK_IF_LOCK(sc_if);
3779 msk_init_locked(sc_if);
3780 MSK_IF_UNLOCK(sc_if);
3781 }
3782
3783 static void
msk_init_locked(struct msk_if_softc * sc_if)3784 msk_init_locked(struct msk_if_softc *sc_if)
3785 {
3786 struct msk_softc *sc;
3787 if_t ifp;
3788 struct mii_data *mii;
3789 uint8_t *eaddr;
3790 uint16_t gmac;
3791 uint32_t reg;
3792 int error;
3793
3794 MSK_IF_LOCK_ASSERT(sc_if);
3795
3796 ifp = sc_if->msk_ifp;
3797 sc = sc_if->msk_softc;
3798 mii = device_get_softc(sc_if->msk_miibus);
3799
3800 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)
3801 return;
3802
3803 error = 0;
3804 /* Cancel pending I/O and free all Rx/Tx buffers. */
3805 msk_stop(sc_if);
3806
3807 if (if_getmtu(ifp) < ETHERMTU)
3808 sc_if->msk_framesize = ETHERMTU;
3809 else
3810 sc_if->msk_framesize = if_getmtu(ifp);
3811 sc_if->msk_framesize += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
3812 if (if_getmtu(ifp) > ETHERMTU &&
3813 (sc_if->msk_flags & MSK_FLAG_JUMBO_NOCSUM) != 0) {
3814 if_sethwassistbits(ifp, 0, (MSK_CSUM_FEATURES | CSUM_TSO));
3815 if_setcapenablebit(ifp, 0, (IFCAP_TSO4 | IFCAP_TXCSUM));
3816 }
3817
3818 /* GMAC Control reset. */
3819 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_RST_SET);
3820 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_RST_CLR);
3821 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_F_LOOPB_OFF);
3822 if (sc->msk_hw_id == CHIP_ID_YUKON_EX ||
3823 sc->msk_hw_id == CHIP_ID_YUKON_SUPR)
3824 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL),
3825 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON |
3826 GMC_BYP_RETR_ON);
3827
3828 /*
3829 * Initialize GMAC first such that speed/duplex/flow-control
3830 * parameters are renegotiated when interface is brought up.
3831 */
3832 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, 0);
3833
3834 /* Dummy read the Interrupt Source Register. */
3835 CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC));
3836
3837 /* Clear MIB stats. */
3838 msk_stats_clear(sc_if);
3839
3840 /* Disable FCS. */
3841 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, GM_RXCR_CRC_DIS);
3842
3843 /* Setup Transmit Control Register. */
3844 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
3845
3846 /* Setup Transmit Flow Control Register. */
3847 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_FLOW_CTRL, 0xffff);
3848
3849 /* Setup Transmit Parameter Register. */
3850 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_PARAM,
3851 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) | TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
3852 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) | TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
3853
3854 gmac = DATA_BLIND_VAL(DATA_BLIND_DEF) |
3855 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
3856
3857 if (if_getmtu(ifp) > ETHERMTU)
3858 gmac |= GM_SMOD_JUMBO_ENA;
3859 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SERIAL_MODE, gmac);
3860
3861 /* Set station address. */
3862 eaddr = if_getlladdr(ifp);
3863 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_1L,
3864 eaddr[0] | (eaddr[1] << 8));
3865 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_1M,
3866 eaddr[2] | (eaddr[3] << 8));
3867 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_1H,
3868 eaddr[4] | (eaddr[5] << 8));
3869 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_2L,
3870 eaddr[0] | (eaddr[1] << 8));
3871 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_2M,
3872 eaddr[2] | (eaddr[3] << 8));
3873 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_2H,
3874 eaddr[4] | (eaddr[5] << 8));
3875
3876 /* Disable interrupts for counter overflows. */
3877 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_IRQ_MSK, 0);
3878 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_IRQ_MSK, 0);
3879 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TR_IRQ_MSK, 0);
3880
3881 /* Configure Rx MAC FIFO. */
3882 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET);
3883 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_CLR);
3884 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
3885 if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P ||
3886 sc->msk_hw_id == CHIP_ID_YUKON_EX)
3887 reg |= GMF_RX_OVER_ON;
3888 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), reg);
3889
3890 /* Set receive filter. */
3891 msk_rxfilter(sc_if);
3892
3893 if (sc->msk_hw_id == CHIP_ID_YUKON_XL) {
3894 /* Clear flush mask - HW bug. */
3895 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_MSK), 0);
3896 } else {
3897 /* Flush Rx MAC FIFO on any flow control or error. */
3898 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_MSK),
3899 GMR_FS_ANY_ERR);
3900 }
3901
3902 /*
3903 * Set Rx FIFO flush threshold to 64 bytes + 1 FIFO word
3904 * due to hardware hang on receipt of pause frames.
3905 */
3906 reg = RX_GMF_FL_THR_DEF + 1;
3907 /* Another magic for Yukon FE+ - From Linux. */
3908 if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P &&
3909 sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0)
3910 reg = 0x178;
3911 CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_THR), reg);
3912
3913 /* Configure Tx MAC FIFO. */
3914 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_SET);
3915 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_CLR);
3916 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_OPER_ON);
3917
3918 /* Configure hardware VLAN tag insertion/stripping. */
3919 msk_setvlan(sc_if, ifp);
3920
3921 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) {
3922 /* Set Rx Pause threshold. */
3923 CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_LP_THR),
3924 MSK_ECU_LLPP);
3925 CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_UP_THR),
3926 MSK_ECU_ULPP);
3927 /* Configure store-and-forward for Tx. */
3928 msk_set_tx_stfwd(sc_if);
3929 }
3930
3931 if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P &&
3932 sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) {
3933 /* Disable dynamic watermark - from Linux. */
3934 reg = CSR_READ_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_EA));
3935 reg &= ~0x03;
3936 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_EA), reg);
3937 }
3938
3939 /*
3940 * Disable Force Sync bit and Alloc bit in Tx RAM interface
3941 * arbiter as we don't use Sync Tx queue.
3942 */
3943 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL),
3944 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
3945 /* Enable the RAM Interface Arbiter. */
3946 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), TXA_ENA_ARB);
3947
3948 /* Setup RAM buffer. */
3949 msk_set_rambuffer(sc_if);
3950
3951 /* Disable Tx sync Queue. */
3952 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txsq, RB_CTRL), RB_RST_SET);
3953
3954 /* Setup Tx Queue Bus Memory Interface. */
3955 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_RESET);
3956 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_OPER_INIT);
3957 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_FIFO_OP_ON);
3958 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_WM), MSK_BMU_TX_WM);
3959 switch (sc->msk_hw_id) {
3960 case CHIP_ID_YUKON_EC_U:
3961 if (sc->msk_hw_rev == CHIP_REV_YU_EC_U_A0) {
3962 /* Fix for Yukon-EC Ultra: set BMU FIFO level */
3963 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_AL),
3964 MSK_ECU_TXFF_LEV);
3965 }
3966 break;
3967 case CHIP_ID_YUKON_EX:
3968 /*
3969 * Yukon Extreme seems to have silicon bug for
3970 * automatic Tx checksum calculation capability.
3971 */
3972 if (sc->msk_hw_rev == CHIP_REV_YU_EX_B0)
3973 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_F),
3974 F_TX_CHK_AUTO_OFF);
3975 break;
3976 }
3977
3978 /* Setup Rx Queue Bus Memory Interface. */
3979 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_RESET);
3980 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_OPER_INIT);
3981 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_FIFO_OP_ON);
3982 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_rxq, Q_WM), MSK_BMU_RX_WM);
3983 if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U &&
3984 sc->msk_hw_rev >= CHIP_REV_YU_EC_U_A1) {
3985 /* MAC Rx RAM Read is controlled by hardware. */
3986 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_F), F_M_RX_RAM_DIS);
3987 }
3988
3989 msk_set_prefetch(sc, sc_if->msk_txq,
3990 sc_if->msk_rdata.msk_tx_ring_paddr, MSK_TX_RING_CNT - 1);
3991 msk_init_tx_ring(sc_if);
3992
3993 /* Disable Rx checksum offload and RSS hash. */
3994 reg = BMU_DIS_RX_RSS_HASH;
3995 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 &&
3996 (if_getcapenable(ifp) & IFCAP_RXCSUM) != 0)
3997 reg |= BMU_ENA_RX_CHKSUM;
3998 else
3999 reg |= BMU_DIS_RX_CHKSUM;
4000 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), reg);
4001 if (sc_if->msk_framesize > (MCLBYTES - MSK_RX_BUF_ALIGN)) {
4002 msk_set_prefetch(sc, sc_if->msk_rxq,
4003 sc_if->msk_rdata.msk_jumbo_rx_ring_paddr,
4004 MSK_JUMBO_RX_RING_CNT - 1);
4005 error = msk_init_jumbo_rx_ring(sc_if);
4006 } else {
4007 msk_set_prefetch(sc, sc_if->msk_rxq,
4008 sc_if->msk_rdata.msk_rx_ring_paddr,
4009 MSK_RX_RING_CNT - 1);
4010 error = msk_init_rx_ring(sc_if);
4011 }
4012 if (error != 0) {
4013 device_printf(sc_if->msk_if_dev,
4014 "initialization failed: no memory for Rx buffers\n");
4015 msk_stop(sc_if);
4016 return;
4017 }
4018 if (sc->msk_hw_id == CHIP_ID_YUKON_EX ||
4019 sc->msk_hw_id == CHIP_ID_YUKON_SUPR) {
4020 /* Disable flushing of non-ASF packets. */
4021 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T),
4022 GMF_RX_MACSEC_FLUSH_OFF);
4023 }
4024
4025 /* Configure interrupt handling. */
4026 if (sc_if->msk_port == MSK_PORT_A) {
4027 sc->msk_intrmask |= Y2_IS_PORT_A;
4028 sc->msk_intrhwemask |= Y2_HWE_L1_MASK;
4029 } else {
4030 sc->msk_intrmask |= Y2_IS_PORT_B;
4031 sc->msk_intrhwemask |= Y2_HWE_L2_MASK;
4032 }
4033 /* Configure IRQ moderation mask. */
4034 CSR_WRITE_4(sc, B2_IRQM_MSK, sc->msk_intrmask);
4035 if (sc->msk_int_holdoff > 0) {
4036 /* Configure initial IRQ moderation timer value. */
4037 CSR_WRITE_4(sc, B2_IRQM_INI,
4038 MSK_USECS(sc, sc->msk_int_holdoff));
4039 CSR_WRITE_4(sc, B2_IRQM_VAL,
4040 MSK_USECS(sc, sc->msk_int_holdoff));
4041 /* Start IRQ moderation. */
4042 CSR_WRITE_1(sc, B2_IRQM_CTRL, TIM_START);
4043 }
4044 CSR_WRITE_4(sc, B0_HWE_IMSK, sc->msk_intrhwemask);
4045 CSR_READ_4(sc, B0_HWE_IMSK);
4046 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask);
4047 CSR_READ_4(sc, B0_IMSK);
4048
4049 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0);
4050 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
4051
4052 sc_if->msk_flags &= ~MSK_FLAG_LINK;
4053 mii_mediachg(mii);
4054
4055 callout_reset(&sc_if->msk_tick_ch, hz, msk_tick, sc_if);
4056 }
4057
4058 static void
msk_set_rambuffer(struct msk_if_softc * sc_if)4059 msk_set_rambuffer(struct msk_if_softc *sc_if)
4060 {
4061 struct msk_softc *sc;
4062 int ltpp, utpp;
4063
4064 sc = sc_if->msk_softc;
4065 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0)
4066 return;
4067
4068 /* Setup Rx Queue. */
4069 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_RST_CLR);
4070 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_START),
4071 sc->msk_rxqstart[sc_if->msk_port] / 8);
4072 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_END),
4073 sc->msk_rxqend[sc_if->msk_port] / 8);
4074 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_WP),
4075 sc->msk_rxqstart[sc_if->msk_port] / 8);
4076 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RP),
4077 sc->msk_rxqstart[sc_if->msk_port] / 8);
4078
4079 utpp = (sc->msk_rxqend[sc_if->msk_port] + 1 -
4080 sc->msk_rxqstart[sc_if->msk_port] - MSK_RB_ULPP) / 8;
4081 ltpp = (sc->msk_rxqend[sc_if->msk_port] + 1 -
4082 sc->msk_rxqstart[sc_if->msk_port] - MSK_RB_LLPP_B) / 8;
4083 if (sc->msk_rxqsize < MSK_MIN_RXQ_SIZE)
4084 ltpp += (MSK_RB_LLPP_B - MSK_RB_LLPP_S) / 8;
4085 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RX_UTPP), utpp);
4086 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RX_LTPP), ltpp);
4087 /* Set Rx priority(RB_RX_UTHP/RB_RX_LTHP) thresholds? */
4088
4089 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_ENA_OP_MD);
4090 CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL));
4091
4092 /* Setup Tx Queue. */
4093 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_RST_CLR);
4094 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_START),
4095 sc->msk_txqstart[sc_if->msk_port] / 8);
4096 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_END),
4097 sc->msk_txqend[sc_if->msk_port] / 8);
4098 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_WP),
4099 sc->msk_txqstart[sc_if->msk_port] / 8);
4100 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_RP),
4101 sc->msk_txqstart[sc_if->msk_port] / 8);
4102 /* Enable Store & Forward for Tx side. */
4103 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_ENA_STFWD);
4104 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_ENA_OP_MD);
4105 CSR_READ_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL));
4106 }
4107
4108 static void
msk_set_prefetch(struct msk_softc * sc,int qaddr,bus_addr_t addr,uint32_t count)4109 msk_set_prefetch(struct msk_softc *sc, int qaddr, bus_addr_t addr,
4110 uint32_t count)
4111 {
4112
4113 /* Reset the prefetch unit. */
4114 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG),
4115 PREF_UNIT_RST_SET);
4116 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG),
4117 PREF_UNIT_RST_CLR);
4118 /* Set LE base address. */
4119 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_LOW_REG),
4120 MSK_ADDR_LO(addr));
4121 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_HI_REG),
4122 MSK_ADDR_HI(addr));
4123 /* Set the list last index. */
4124 CSR_WRITE_2(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_LAST_IDX_REG),
4125 count);
4126 /* Turn on prefetch unit. */
4127 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG),
4128 PREF_UNIT_OP_ON);
4129 /* Dummy read to ensure write. */
4130 CSR_READ_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG));
4131 }
4132
4133 static void
msk_stop(struct msk_if_softc * sc_if)4134 msk_stop(struct msk_if_softc *sc_if)
4135 {
4136 struct msk_softc *sc;
4137 struct msk_txdesc *txd;
4138 struct msk_rxdesc *rxd;
4139 struct msk_rxdesc *jrxd;
4140 if_t ifp;
4141 uint32_t val;
4142 int i;
4143
4144 MSK_IF_LOCK_ASSERT(sc_if);
4145 sc = sc_if->msk_softc;
4146 ifp = sc_if->msk_ifp;
4147
4148 callout_stop(&sc_if->msk_tick_ch);
4149 sc_if->msk_watchdog_timer = 0;
4150
4151 /* Disable interrupts. */
4152 if (sc_if->msk_port == MSK_PORT_A) {
4153 sc->msk_intrmask &= ~Y2_IS_PORT_A;
4154 sc->msk_intrhwemask &= ~Y2_HWE_L1_MASK;
4155 } else {
4156 sc->msk_intrmask &= ~Y2_IS_PORT_B;
4157 sc->msk_intrhwemask &= ~Y2_HWE_L2_MASK;
4158 }
4159 CSR_WRITE_4(sc, B0_HWE_IMSK, sc->msk_intrhwemask);
4160 CSR_READ_4(sc, B0_HWE_IMSK);
4161 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask);
4162 CSR_READ_4(sc, B0_IMSK);
4163
4164 /* Disable Tx/Rx MAC. */
4165 val = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL);
4166 val &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
4167 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, val);
4168 /* Read again to ensure writing. */
4169 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL);
4170 /* Update stats and clear counters. */
4171 msk_stats_update(sc_if);
4172
4173 /* Stop Tx BMU. */
4174 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_STOP);
4175 val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR));
4176 for (i = 0; i < MSK_TIMEOUT; i++) {
4177 if ((val & (BMU_STOP | BMU_IDLE)) == 0) {
4178 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR),
4179 BMU_STOP);
4180 val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR));
4181 } else
4182 break;
4183 DELAY(1);
4184 }
4185 if (i == MSK_TIMEOUT)
4186 device_printf(sc_if->msk_if_dev, "Tx BMU stop failed\n");
4187 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL),
4188 RB_RST_SET | RB_DIS_OP_MD);
4189
4190 /* Disable all GMAC interrupt. */
4191 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_MSK), 0);
4192 /* Disable PHY interrupt. */
4193 msk_phy_writereg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_MASK, 0);
4194
4195 /* Disable the RAM Interface Arbiter. */
4196 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), TXA_DIS_ARB);
4197
4198 /* Reset the PCI FIFO of the async Tx queue */
4199 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR),
4200 BMU_RST_SET | BMU_FIFO_RST);
4201
4202 /* Reset the Tx prefetch units. */
4203 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(sc_if->msk_txq, PREF_UNIT_CTRL_REG),
4204 PREF_UNIT_RST_SET);
4205
4206 /* Reset the RAM Buffer async Tx queue. */
4207 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_RST_SET);
4208
4209 /* Reset Tx MAC FIFO. */
4210 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_SET);
4211 /* Set Pause Off. */
4212 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_PAUSE_OFF);
4213
4214 /*
4215 * The Rx Stop command will not work for Yukon-2 if the BMU does not
4216 * reach the end of packet and since we can't make sure that we have
4217 * incoming data, we must reset the BMU while it is not during a DMA
4218 * transfer. Since it is possible that the Rx path is still active,
4219 * the Rx RAM buffer will be stopped first, so any possible incoming
4220 * data will not trigger a DMA. After the RAM buffer is stopped, the
4221 * BMU is polled until any DMA in progress is ended and only then it
4222 * will be reset.
4223 */
4224
4225 /* Disable the RAM Buffer receive queue. */
4226 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_DIS_OP_MD);
4227 for (i = 0; i < MSK_TIMEOUT; i++) {
4228 if (CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, Q_RSL)) ==
4229 CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, Q_RL)))
4230 break;
4231 DELAY(1);
4232 }
4233 if (i == MSK_TIMEOUT)
4234 device_printf(sc_if->msk_if_dev, "Rx BMU stop failed\n");
4235 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR),
4236 BMU_RST_SET | BMU_FIFO_RST);
4237 /* Reset the Rx prefetch unit. */
4238 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_CTRL_REG),
4239 PREF_UNIT_RST_SET);
4240 /* Reset the RAM Buffer receive queue. */
4241 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_RST_SET);
4242 /* Reset Rx MAC FIFO. */
4243 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET);
4244
4245 /* Free Rx and Tx mbufs still in the queues. */
4246 for (i = 0; i < MSK_RX_RING_CNT; i++) {
4247 rxd = &sc_if->msk_cdata.msk_rxdesc[i];
4248 if (rxd->rx_m != NULL) {
4249 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag,
4250 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
4251 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_tag,
4252 rxd->rx_dmamap);
4253 m_freem(rxd->rx_m);
4254 rxd->rx_m = NULL;
4255 }
4256 }
4257 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) {
4258 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i];
4259 if (jrxd->rx_m != NULL) {
4260 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag,
4261 jrxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
4262 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_tag,
4263 jrxd->rx_dmamap);
4264 m_freem(jrxd->rx_m);
4265 jrxd->rx_m = NULL;
4266 }
4267 }
4268 for (i = 0; i < MSK_TX_RING_CNT; i++) {
4269 txd = &sc_if->msk_cdata.msk_txdesc[i];
4270 if (txd->tx_m != NULL) {
4271 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag,
4272 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
4273 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag,
4274 txd->tx_dmamap);
4275 m_freem(txd->tx_m);
4276 txd->tx_m = NULL;
4277 }
4278 }
4279
4280 /*
4281 * Mark the interface down.
4282 */
4283 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE));
4284 sc_if->msk_flags &= ~MSK_FLAG_LINK;
4285 }
4286
4287 /*
4288 * When GM_PAR_MIB_CLR bit of GM_PHY_ADDR is set, reading lower
4289 * counter clears high 16 bits of the counter such that accessing
4290 * lower 16 bits should be the last operation.
4291 */
4292 #define MSK_READ_MIB32(x, y) \
4293 ((((uint32_t)GMAC_READ_2(sc, x, (y) + 4)) << 16) + \
4294 (uint32_t)GMAC_READ_2(sc, x, y))
4295 #define MSK_READ_MIB64(x, y) \
4296 ((((uint64_t)MSK_READ_MIB32(x, (y) + 8)) << 32) + \
4297 (uint64_t)MSK_READ_MIB32(x, y))
4298
4299 static void
msk_stats_clear(struct msk_if_softc * sc_if)4300 msk_stats_clear(struct msk_if_softc *sc_if)
4301 {
4302 struct msk_softc *sc;
4303 uint16_t gmac;
4304 int i;
4305
4306 MSK_IF_LOCK_ASSERT(sc_if);
4307
4308 sc = sc_if->msk_softc;
4309 /* Set MIB Clear Counter Mode. */
4310 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_PHY_ADDR);
4311 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR);
4312 /* Read all MIB Counters with Clear Mode set. */
4313 for (i = GM_RXF_UC_OK; i <= GM_TXE_FIFO_UR; i += sizeof(uint32_t))
4314 (void)MSK_READ_MIB32(sc_if->msk_port, i);
4315 /* Clear MIB Clear Counter Mode. */
4316 gmac &= ~GM_PAR_MIB_CLR;
4317 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac);
4318 }
4319
4320 static void
msk_stats_update(struct msk_if_softc * sc_if)4321 msk_stats_update(struct msk_if_softc *sc_if)
4322 {
4323 struct msk_softc *sc;
4324 if_t ifp;
4325 struct msk_hw_stats *stats;
4326 uint16_t gmac;
4327
4328 MSK_IF_LOCK_ASSERT(sc_if);
4329
4330 ifp = sc_if->msk_ifp;
4331 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0)
4332 return;
4333 sc = sc_if->msk_softc;
4334 stats = &sc_if->msk_stats;
4335 /* Set MIB Clear Counter Mode. */
4336 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_PHY_ADDR);
4337 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR);
4338
4339 /* Rx stats. */
4340 stats->rx_ucast_frames +=
4341 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_UC_OK);
4342 stats->rx_bcast_frames +=
4343 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_BC_OK);
4344 stats->rx_pause_frames +=
4345 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_MPAUSE);
4346 stats->rx_mcast_frames +=
4347 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_MC_OK);
4348 stats->rx_crc_errs +=
4349 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_FCS_ERR);
4350 stats->rx_good_octets +=
4351 MSK_READ_MIB64(sc_if->msk_port, GM_RXO_OK_LO);
4352 stats->rx_bad_octets +=
4353 MSK_READ_MIB64(sc_if->msk_port, GM_RXO_ERR_LO);
4354 stats->rx_runts +=
4355 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_SHT);
4356 stats->rx_runt_errs +=
4357 MSK_READ_MIB32(sc_if->msk_port, GM_RXE_FRAG);
4358 stats->rx_pkts_64 +=
4359 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_64B);
4360 stats->rx_pkts_65_127 +=
4361 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_127B);
4362 stats->rx_pkts_128_255 +=
4363 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_255B);
4364 stats->rx_pkts_256_511 +=
4365 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_511B);
4366 stats->rx_pkts_512_1023 +=
4367 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_1023B);
4368 stats->rx_pkts_1024_1518 +=
4369 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_1518B);
4370 stats->rx_pkts_1519_max +=
4371 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_MAX_SZ);
4372 stats->rx_pkts_too_long +=
4373 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_LNG_ERR);
4374 stats->rx_pkts_jabbers +=
4375 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_JAB_PKT);
4376 stats->rx_fifo_oflows +=
4377 MSK_READ_MIB32(sc_if->msk_port, GM_RXE_FIFO_OV);
4378
4379 /* Tx stats. */
4380 stats->tx_ucast_frames +=
4381 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_UC_OK);
4382 stats->tx_bcast_frames +=
4383 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_BC_OK);
4384 stats->tx_pause_frames +=
4385 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MPAUSE);
4386 stats->tx_mcast_frames +=
4387 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MC_OK);
4388 stats->tx_octets +=
4389 MSK_READ_MIB64(sc_if->msk_port, GM_TXO_OK_LO);
4390 stats->tx_pkts_64 +=
4391 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_64B);
4392 stats->tx_pkts_65_127 +=
4393 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_127B);
4394 stats->tx_pkts_128_255 +=
4395 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_255B);
4396 stats->tx_pkts_256_511 +=
4397 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_511B);
4398 stats->tx_pkts_512_1023 +=
4399 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_1023B);
4400 stats->tx_pkts_1024_1518 +=
4401 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_1518B);
4402 stats->tx_pkts_1519_max +=
4403 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MAX_SZ);
4404 stats->tx_colls +=
4405 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_COL);
4406 stats->tx_late_colls +=
4407 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_LAT_COL);
4408 stats->tx_excess_colls +=
4409 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_ABO_COL);
4410 stats->tx_multi_colls +=
4411 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MUL_COL);
4412 stats->tx_single_colls +=
4413 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_SNG_COL);
4414 stats->tx_underflows +=
4415 MSK_READ_MIB32(sc_if->msk_port, GM_TXE_FIFO_UR);
4416 /* Clear MIB Clear Counter Mode. */
4417 gmac &= ~GM_PAR_MIB_CLR;
4418 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac);
4419 }
4420
4421 static int
msk_sysctl_stat32(SYSCTL_HANDLER_ARGS)4422 msk_sysctl_stat32(SYSCTL_HANDLER_ARGS)
4423 {
4424 struct msk_softc *sc;
4425 struct msk_if_softc *sc_if;
4426 uint32_t result, *stat;
4427 int off;
4428
4429 sc_if = (struct msk_if_softc *)arg1;
4430 sc = sc_if->msk_softc;
4431 off = arg2;
4432 stat = (uint32_t *)((uint8_t *)&sc_if->msk_stats + off);
4433
4434 MSK_IF_LOCK(sc_if);
4435 result = MSK_READ_MIB32(sc_if->msk_port, GM_MIB_CNT_BASE + off * 2);
4436 result += *stat;
4437 MSK_IF_UNLOCK(sc_if);
4438
4439 return (sysctl_handle_int(oidp, &result, 0, req));
4440 }
4441
4442 static int
msk_sysctl_stat64(SYSCTL_HANDLER_ARGS)4443 msk_sysctl_stat64(SYSCTL_HANDLER_ARGS)
4444 {
4445 struct msk_softc *sc;
4446 struct msk_if_softc *sc_if;
4447 uint64_t result, *stat;
4448 int off;
4449
4450 sc_if = (struct msk_if_softc *)arg1;
4451 sc = sc_if->msk_softc;
4452 off = arg2;
4453 stat = (uint64_t *)((uint8_t *)&sc_if->msk_stats + off);
4454
4455 MSK_IF_LOCK(sc_if);
4456 result = MSK_READ_MIB64(sc_if->msk_port, GM_MIB_CNT_BASE + off * 2);
4457 result += *stat;
4458 MSK_IF_UNLOCK(sc_if);
4459
4460 return (sysctl_handle_64(oidp, &result, 0, req));
4461 }
4462
4463 #undef MSK_READ_MIB32
4464 #undef MSK_READ_MIB64
4465
4466 #define MSK_SYSCTL_STAT32(sc, c, o, p, n, d) \
4467 SYSCTL_ADD_PROC(c, p, OID_AUTO, o, \
4468 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, \
4469 sc, offsetof(struct msk_hw_stats, n), msk_sysctl_stat32, \
4470 "IU", d)
4471 #define MSK_SYSCTL_STAT64(sc, c, o, p, n, d) \
4472 SYSCTL_ADD_PROC(c, p, OID_AUTO, o, \
4473 CTLTYPE_U64 | CTLFLAG_RD | CTLFLAG_NEEDGIANT, \
4474 sc, offsetof(struct msk_hw_stats, n), msk_sysctl_stat64, \
4475 "QU", d)
4476
4477 static void
msk_sysctl_node(struct msk_if_softc * sc_if)4478 msk_sysctl_node(struct msk_if_softc *sc_if)
4479 {
4480 struct sysctl_ctx_list *ctx;
4481 struct sysctl_oid_list *child, *schild;
4482 struct sysctl_oid *tree;
4483
4484 ctx = device_get_sysctl_ctx(sc_if->msk_if_dev);
4485 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc_if->msk_if_dev));
4486
4487 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats",
4488 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "MSK Statistics");
4489 schild = SYSCTL_CHILDREN(tree);
4490 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "rx",
4491 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "MSK RX Statistics");
4492 child = SYSCTL_CHILDREN(tree);
4493 MSK_SYSCTL_STAT32(sc_if, ctx, "ucast_frames",
4494 child, rx_ucast_frames, "Good unicast frames");
4495 MSK_SYSCTL_STAT32(sc_if, ctx, "bcast_frames",
4496 child, rx_bcast_frames, "Good broadcast frames");
4497 MSK_SYSCTL_STAT32(sc_if, ctx, "pause_frames",
4498 child, rx_pause_frames, "Pause frames");
4499 MSK_SYSCTL_STAT32(sc_if, ctx, "mcast_frames",
4500 child, rx_mcast_frames, "Multicast frames");
4501 MSK_SYSCTL_STAT32(sc_if, ctx, "crc_errs",
4502 child, rx_crc_errs, "CRC errors");
4503 MSK_SYSCTL_STAT64(sc_if, ctx, "good_octets",
4504 child, rx_good_octets, "Good octets");
4505 MSK_SYSCTL_STAT64(sc_if, ctx, "bad_octets",
4506 child, rx_bad_octets, "Bad octets");
4507 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_64",
4508 child, rx_pkts_64, "64 bytes frames");
4509 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_65_127",
4510 child, rx_pkts_65_127, "65 to 127 bytes frames");
4511 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_128_255",
4512 child, rx_pkts_128_255, "128 to 255 bytes frames");
4513 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_256_511",
4514 child, rx_pkts_256_511, "256 to 511 bytes frames");
4515 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_512_1023",
4516 child, rx_pkts_512_1023, "512 to 1023 bytes frames");
4517 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1024_1518",
4518 child, rx_pkts_1024_1518, "1024 to 1518 bytes frames");
4519 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1519_max",
4520 child, rx_pkts_1519_max, "1519 to max frames");
4521 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_too_long",
4522 child, rx_pkts_too_long, "frames too long");
4523 MSK_SYSCTL_STAT32(sc_if, ctx, "jabbers",
4524 child, rx_pkts_jabbers, "Jabber errors");
4525 MSK_SYSCTL_STAT32(sc_if, ctx, "overflows",
4526 child, rx_fifo_oflows, "FIFO overflows");
4527
4528 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "tx",
4529 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "MSK TX Statistics");
4530 child = SYSCTL_CHILDREN(tree);
4531 MSK_SYSCTL_STAT32(sc_if, ctx, "ucast_frames",
4532 child, tx_ucast_frames, "Unicast frames");
4533 MSK_SYSCTL_STAT32(sc_if, ctx, "bcast_frames",
4534 child, tx_bcast_frames, "Broadcast frames");
4535 MSK_SYSCTL_STAT32(sc_if, ctx, "pause_frames",
4536 child, tx_pause_frames, "Pause frames");
4537 MSK_SYSCTL_STAT32(sc_if, ctx, "mcast_frames",
4538 child, tx_mcast_frames, "Multicast frames");
4539 MSK_SYSCTL_STAT64(sc_if, ctx, "octets",
4540 child, tx_octets, "Octets");
4541 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_64",
4542 child, tx_pkts_64, "64 bytes frames");
4543 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_65_127",
4544 child, tx_pkts_65_127, "65 to 127 bytes frames");
4545 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_128_255",
4546 child, tx_pkts_128_255, "128 to 255 bytes frames");
4547 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_256_511",
4548 child, tx_pkts_256_511, "256 to 511 bytes frames");
4549 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_512_1023",
4550 child, tx_pkts_512_1023, "512 to 1023 bytes frames");
4551 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1024_1518",
4552 child, tx_pkts_1024_1518, "1024 to 1518 bytes frames");
4553 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1519_max",
4554 child, tx_pkts_1519_max, "1519 to max frames");
4555 MSK_SYSCTL_STAT32(sc_if, ctx, "colls",
4556 child, tx_colls, "Collisions");
4557 MSK_SYSCTL_STAT32(sc_if, ctx, "late_colls",
4558 child, tx_late_colls, "Late collisions");
4559 MSK_SYSCTL_STAT32(sc_if, ctx, "excess_colls",
4560 child, tx_excess_colls, "Excessive collisions");
4561 MSK_SYSCTL_STAT32(sc_if, ctx, "multi_colls",
4562 child, tx_multi_colls, "Multiple collisions");
4563 MSK_SYSCTL_STAT32(sc_if, ctx, "single_colls",
4564 child, tx_single_colls, "Single collisions");
4565 MSK_SYSCTL_STAT32(sc_if, ctx, "underflows",
4566 child, tx_underflows, "FIFO underflows");
4567 }
4568
4569 #undef MSK_SYSCTL_STAT32
4570 #undef MSK_SYSCTL_STAT64
4571
4572 static int
sysctl_int_range(SYSCTL_HANDLER_ARGS,int low,int high)4573 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
4574 {
4575 int error, value;
4576
4577 if (!arg1)
4578 return (EINVAL);
4579 value = *(int *)arg1;
4580 error = sysctl_handle_int(oidp, &value, 0, req);
4581 if (error || !req->newptr)
4582 return (error);
4583 if (value < low || value > high)
4584 return (EINVAL);
4585 *(int *)arg1 = value;
4586
4587 return (0);
4588 }
4589
4590 static int
sysctl_hw_msk_proc_limit(SYSCTL_HANDLER_ARGS)4591 sysctl_hw_msk_proc_limit(SYSCTL_HANDLER_ARGS)
4592 {
4593
4594 return (sysctl_int_range(oidp, arg1, arg2, req, MSK_PROC_MIN,
4595 MSK_PROC_MAX));
4596 }
4597