1 /******************************************************************************
2 *
3 * Name : sky2.c
4 * Project: Gigabit Ethernet Driver for FreeBSD 5.x/6.x
5 * Version: $Revision: 1.23 $
6 * Date : $Date: 2005/12/22 09:04:11 $
7 * Purpose: Main driver source file
8 *
9 *****************************************************************************/
10
11 /******************************************************************************
12 *
13 * LICENSE:
14 * Copyright (C) Marvell International Ltd. and/or its affiliates
15 *
16 * The computer program files contained in this folder ("Files")
17 * are provided to you under the BSD-type license terms provided
18 * below, and any use of such Files and any derivative works
19 * thereof created by you shall be governed by the following terms
20 * and conditions:
21 *
22 * - Redistributions of source code must retain the above copyright
23 * notice, this list of conditions and the following disclaimer.
24 * - Redistributions in binary form must reproduce the above
25 * copyright notice, this list of conditions and the following
26 * disclaimer in the documentation and/or other materials provided
27 * with the distribution.
28 * - Neither the name of Marvell nor the names of its contributors
29 * may be used to endorse or promote products derived from this
30 * software without specific prior written permission.
31 *
32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
33 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
34 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
35 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
36 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
37 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
38 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
39 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
41 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
42 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
43 * OF THE POSSIBILITY OF SUCH DAMAGE.
44 * /LICENSE
45 *
46 *****************************************************************************/
47
48 /*-
49 * SPDX-License-Identifier: BSD-4-Clause AND BSD-3-Clause
50 *
51 * Copyright (c) 1997, 1998, 1999, 2000
52 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
53 *
54 * Redistribution and use in source and binary forms, with or without
55 * modification, are permitted provided that the following conditions
56 * are met:
57 * 1. Redistributions of source code must retain the above copyright
58 * notice, this list of conditions and the following disclaimer.
59 * 2. Redistributions in binary form must reproduce the above copyright
60 * notice, this list of conditions and the following disclaimer in the
61 * documentation and/or other materials provided with the distribution.
62 * 3. All advertising materials mentioning features or use of this software
63 * must display the following acknowledgement:
64 * This product includes software developed by Bill Paul.
65 * 4. Neither the name of the author nor the names of any co-contributors
66 * may be used to endorse or promote products derived from this software
67 * without specific prior written permission.
68 *
69 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
70 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
71 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
72 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
73 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
74 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
75 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
76 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
77 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
78 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
79 * THE POSSIBILITY OF SUCH DAMAGE.
80 */
81 /*-
82 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu>
83 *
84 * Permission to use, copy, modify, and distribute this software for any
85 * purpose with or without fee is hereby granted, provided that the above
86 * copyright notice and this permission notice appear in all copies.
87 *
88 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
89 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
90 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
91 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
92 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
93 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
94 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
95 */
96
97 /*
98 * Device driver for the Marvell Yukon II Ethernet controller.
99 * Due to lack of documentation, this driver is based on the code from
100 * sk(4) and Marvell's myk(4) driver for FreeBSD 5.x.
101 */
102
103 #include <sys/param.h>
104 #include <sys/systm.h>
105 #include <sys/bus.h>
106 #include <sys/endian.h>
107 #include <sys/mbuf.h>
108 #include <sys/malloc.h>
109 #include <sys/kernel.h>
110 #include <sys/module.h>
111 #include <sys/socket.h>
112 #include <sys/sockio.h>
113 #include <sys/queue.h>
114 #include <sys/sysctl.h>
115
116 #include <net/bpf.h>
117 #include <net/ethernet.h>
118 #include <net/if.h>
119 #include <net/if_var.h>
120 #include <net/if_arp.h>
121 #include <net/if_dl.h>
122 #include <net/if_media.h>
123 #include <net/if_types.h>
124 #include <net/if_vlan_var.h>
125
126 #include <netinet/in.h>
127 #include <netinet/in_systm.h>
128 #include <netinet/ip.h>
129 #include <netinet/tcp.h>
130 #include <netinet/udp.h>
131
132 #include <machine/bus.h>
133 #include <machine/in_cksum.h>
134 #include <machine/resource.h>
135 #include <sys/rman.h>
136
137 #include <dev/mii/mii.h>
138 #include <dev/mii/miivar.h>
139
140 #include <dev/pci/pcireg.h>
141 #include <dev/pci/pcivar.h>
142
143 #include <dev/msk/if_mskreg.h>
144
145 MODULE_DEPEND(msk, pci, 1, 1, 1);
146 MODULE_DEPEND(msk, ether, 1, 1, 1);
147 MODULE_DEPEND(msk, miibus, 1, 1, 1);
148
149 /* "device miibus" required. See GENERIC if you get errors here. */
150 #include "miibus_if.h"
151
152 /* Tunables. */
153 static int msi_disable = 0;
154 TUNABLE_INT("hw.msk.msi_disable", &msi_disable);
155 static int legacy_intr = 0;
156 TUNABLE_INT("hw.msk.legacy_intr", &legacy_intr);
157 static int jumbo_disable = 0;
158 TUNABLE_INT("hw.msk.jumbo_disable", &jumbo_disable);
159
160 #define MSK_CSUM_FEATURES (CSUM_TCP | CSUM_UDP)
161
162 /*
163 * Devices supported by this driver.
164 */
165 static const struct msk_product {
166 uint16_t msk_vendorid;
167 uint16_t msk_deviceid;
168 const char *msk_name;
169 } msk_products[] = {
170 { VENDORID_SK, DEVICEID_SK_YUKON2,
171 "SK-9Sxx Gigabit Ethernet" },
172 { VENDORID_SK, DEVICEID_SK_YUKON2_EXPR,
173 "SK-9Exx Gigabit Ethernet"},
174 { VENDORID_MARVELL, DEVICEID_MRVL_8021CU,
175 "Marvell Yukon 88E8021CU Gigabit Ethernet" },
176 { VENDORID_MARVELL, DEVICEID_MRVL_8021X,
177 "Marvell Yukon 88E8021 SX/LX Gigabit Ethernet" },
178 { VENDORID_MARVELL, DEVICEID_MRVL_8022CU,
179 "Marvell Yukon 88E8022CU Gigabit Ethernet" },
180 { VENDORID_MARVELL, DEVICEID_MRVL_8022X,
181 "Marvell Yukon 88E8022 SX/LX Gigabit Ethernet" },
182 { VENDORID_MARVELL, DEVICEID_MRVL_8061CU,
183 "Marvell Yukon 88E8061CU Gigabit Ethernet" },
184 { VENDORID_MARVELL, DEVICEID_MRVL_8061X,
185 "Marvell Yukon 88E8061 SX/LX Gigabit Ethernet" },
186 { VENDORID_MARVELL, DEVICEID_MRVL_8062CU,
187 "Marvell Yukon 88E8062CU Gigabit Ethernet" },
188 { VENDORID_MARVELL, DEVICEID_MRVL_8062X,
189 "Marvell Yukon 88E8062 SX/LX Gigabit Ethernet" },
190 { VENDORID_MARVELL, DEVICEID_MRVL_8035,
191 "Marvell Yukon 88E8035 Fast Ethernet" },
192 { VENDORID_MARVELL, DEVICEID_MRVL_8036,
193 "Marvell Yukon 88E8036 Fast Ethernet" },
194 { VENDORID_MARVELL, DEVICEID_MRVL_8038,
195 "Marvell Yukon 88E8038 Fast Ethernet" },
196 { VENDORID_MARVELL, DEVICEID_MRVL_8039,
197 "Marvell Yukon 88E8039 Fast Ethernet" },
198 { VENDORID_MARVELL, DEVICEID_MRVL_8040,
199 "Marvell Yukon 88E8040 Fast Ethernet" },
200 { VENDORID_MARVELL, DEVICEID_MRVL_8040T,
201 "Marvell Yukon 88E8040T Fast Ethernet" },
202 { VENDORID_MARVELL, DEVICEID_MRVL_8042,
203 "Marvell Yukon 88E8042 Fast Ethernet" },
204 { VENDORID_MARVELL, DEVICEID_MRVL_8048,
205 "Marvell Yukon 88E8048 Fast Ethernet" },
206 { VENDORID_MARVELL, DEVICEID_MRVL_4361,
207 "Marvell Yukon 88E8050 Gigabit Ethernet" },
208 { VENDORID_MARVELL, DEVICEID_MRVL_4360,
209 "Marvell Yukon 88E8052 Gigabit Ethernet" },
210 { VENDORID_MARVELL, DEVICEID_MRVL_4362,
211 "Marvell Yukon 88E8053 Gigabit Ethernet" },
212 { VENDORID_MARVELL, DEVICEID_MRVL_4363,
213 "Marvell Yukon 88E8055 Gigabit Ethernet" },
214 { VENDORID_MARVELL, DEVICEID_MRVL_4364,
215 "Marvell Yukon 88E8056 Gigabit Ethernet" },
216 { VENDORID_MARVELL, DEVICEID_MRVL_4365,
217 "Marvell Yukon 88E8070 Gigabit Ethernet" },
218 { VENDORID_MARVELL, DEVICEID_MRVL_436A,
219 "Marvell Yukon 88E8058 Gigabit Ethernet" },
220 { VENDORID_MARVELL, DEVICEID_MRVL_436B,
221 "Marvell Yukon 88E8071 Gigabit Ethernet" },
222 { VENDORID_MARVELL, DEVICEID_MRVL_436C,
223 "Marvell Yukon 88E8072 Gigabit Ethernet" },
224 { VENDORID_MARVELL, DEVICEID_MRVL_436D,
225 "Marvell Yukon 88E8055 Gigabit Ethernet" },
226 { VENDORID_MARVELL, DEVICEID_MRVL_4370,
227 "Marvell Yukon 88E8075 Gigabit Ethernet" },
228 { VENDORID_MARVELL, DEVICEID_MRVL_4380,
229 "Marvell Yukon 88E8057 Gigabit Ethernet" },
230 { VENDORID_MARVELL, DEVICEID_MRVL_4381,
231 "Marvell Yukon 88E8059 Gigabit Ethernet" },
232 { VENDORID_DLINK, DEVICEID_DLINK_DGE550SX,
233 "D-Link 550SX Gigabit Ethernet" },
234 { VENDORID_DLINK, DEVICEID_DLINK_DGE560SX,
235 "D-Link 560SX Gigabit Ethernet" },
236 { VENDORID_DLINK, DEVICEID_DLINK_DGE560T,
237 "D-Link 560T Gigabit Ethernet" }
238 };
239
240 static const char *model_name[] = {
241 "Yukon XL",
242 "Yukon EC Ultra",
243 "Yukon EX",
244 "Yukon EC",
245 "Yukon FE",
246 "Yukon FE+",
247 "Yukon Supreme",
248 "Yukon Ultra 2",
249 "Yukon Unknown",
250 "Yukon Optima",
251 };
252
253 static int mskc_probe(device_t);
254 static int mskc_attach(device_t);
255 static void mskc_child_deleted(device_t, device_t);
256 static int mskc_detach(device_t);
257 static int mskc_shutdown(device_t);
258 static int mskc_setup_rambuffer(struct msk_softc *);
259 static int mskc_suspend(device_t);
260 static int mskc_resume(device_t);
261 static bus_dma_tag_t mskc_get_dma_tag(device_t, device_t);
262 static void mskc_reset(struct msk_softc *);
263
264 static int msk_probe(device_t);
265 static int msk_attach(device_t);
266 static int msk_detach(device_t);
267
268 static void msk_tick(void *);
269 static void msk_intr(void *);
270 static void msk_intr_phy(struct msk_if_softc *);
271 static void msk_intr_gmac(struct msk_if_softc *);
272 static __inline void msk_rxput(struct msk_if_softc *);
273 static int msk_handle_events(struct msk_softc *);
274 static void msk_handle_hwerr(struct msk_if_softc *, uint32_t);
275 static void msk_intr_hwerr(struct msk_softc *);
276 #ifndef __NO_STRICT_ALIGNMENT
277 static __inline void msk_fixup_rx(struct mbuf *);
278 #endif
279 static __inline void msk_rxcsum(struct msk_if_softc *, uint32_t, struct mbuf *);
280 static void msk_rxeof(struct msk_if_softc *, uint32_t, uint32_t, int);
281 static void msk_jumbo_rxeof(struct msk_if_softc *, uint32_t, uint32_t, int);
282 static void msk_txeof(struct msk_if_softc *, int);
283 static int msk_encap(struct msk_if_softc *, struct mbuf **);
284 static void msk_start(if_t);
285 static void msk_start_locked(if_t);
286 static int msk_ioctl(if_t, u_long, caddr_t);
287 static void msk_set_prefetch(struct msk_softc *, int, bus_addr_t, uint32_t);
288 static void msk_set_rambuffer(struct msk_if_softc *);
289 static void msk_set_tx_stfwd(struct msk_if_softc *);
290 static void msk_init(void *);
291 static void msk_init_locked(struct msk_if_softc *);
292 static void msk_stop(struct msk_if_softc *);
293 static void msk_watchdog(struct msk_if_softc *);
294 static int msk_mediachange(if_t);
295 static void msk_mediastatus(if_t, struct ifmediareq *);
296 static void msk_phy_power(struct msk_softc *, int);
297 static void msk_dmamap_cb(void *, bus_dma_segment_t *, int, int);
298 static int msk_status_dma_alloc(struct msk_softc *);
299 static void msk_status_dma_free(struct msk_softc *);
300 static int msk_txrx_dma_alloc(struct msk_if_softc *);
301 static int msk_rx_dma_jalloc(struct msk_if_softc *);
302 static void msk_txrx_dma_free(struct msk_if_softc *);
303 static void msk_rx_dma_jfree(struct msk_if_softc *);
304 static int msk_rx_fill(struct msk_if_softc *, int);
305 static int msk_init_rx_ring(struct msk_if_softc *);
306 static int msk_init_jumbo_rx_ring(struct msk_if_softc *);
307 static void msk_init_tx_ring(struct msk_if_softc *);
308 static __inline void msk_discard_rxbuf(struct msk_if_softc *, int);
309 static __inline void msk_discard_jumbo_rxbuf(struct msk_if_softc *, int);
310 static int msk_newbuf(struct msk_if_softc *, int);
311 static int msk_jumbo_newbuf(struct msk_if_softc *, int);
312
313 static int msk_phy_readreg(struct msk_if_softc *, int, int);
314 static int msk_phy_writereg(struct msk_if_softc *, int, int, int);
315 static int msk_miibus_readreg(device_t, int, int);
316 static int msk_miibus_writereg(device_t, int, int, int);
317 static void msk_miibus_statchg(device_t);
318
319 static void msk_rxfilter(struct msk_if_softc *);
320 static void msk_setvlan(struct msk_if_softc *, if_t);
321
322 static void msk_stats_clear(struct msk_if_softc *);
323 static void msk_stats_update(struct msk_if_softc *);
324 static int msk_sysctl_stat32(SYSCTL_HANDLER_ARGS);
325 static int msk_sysctl_stat64(SYSCTL_HANDLER_ARGS);
326 static void msk_sysctl_node(struct msk_if_softc *);
327 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int);
328 static int sysctl_hw_msk_proc_limit(SYSCTL_HANDLER_ARGS);
329
330 static device_method_t mskc_methods[] = {
331 /* Device interface */
332 DEVMETHOD(device_probe, mskc_probe),
333 DEVMETHOD(device_attach, mskc_attach),
334 DEVMETHOD(device_detach, mskc_detach),
335 DEVMETHOD(device_suspend, mskc_suspend),
336 DEVMETHOD(device_resume, mskc_resume),
337 DEVMETHOD(device_shutdown, mskc_shutdown),
338
339 DEVMETHOD(bus_child_deleted, mskc_child_deleted),
340 DEVMETHOD(bus_get_dma_tag, mskc_get_dma_tag),
341
342 DEVMETHOD_END
343 };
344
345 static driver_t mskc_driver = {
346 "mskc",
347 mskc_methods,
348 sizeof(struct msk_softc)
349 };
350
351 static device_method_t msk_methods[] = {
352 /* Device interface */
353 DEVMETHOD(device_probe, msk_probe),
354 DEVMETHOD(device_attach, msk_attach),
355 DEVMETHOD(device_detach, msk_detach),
356 DEVMETHOD(device_shutdown, bus_generic_shutdown),
357
358 /* MII interface */
359 DEVMETHOD(miibus_readreg, msk_miibus_readreg),
360 DEVMETHOD(miibus_writereg, msk_miibus_writereg),
361 DEVMETHOD(miibus_statchg, msk_miibus_statchg),
362
363 DEVMETHOD_END
364 };
365
366 static driver_t msk_driver = {
367 "msk",
368 msk_methods,
369 sizeof(struct msk_if_softc)
370 };
371
372 DRIVER_MODULE(mskc, pci, mskc_driver, NULL, NULL);
373 DRIVER_MODULE(msk, mskc, msk_driver, NULL, NULL);
374 DRIVER_MODULE(miibus, msk, miibus_driver, NULL, NULL);
375
376 static struct resource_spec msk_res_spec_io[] = {
377 { SYS_RES_IOPORT, PCIR_BAR(1), RF_ACTIVE },
378 { -1, 0, 0 }
379 };
380
381 static struct resource_spec msk_res_spec_mem[] = {
382 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE },
383 { -1, 0, 0 }
384 };
385
386 static struct resource_spec msk_irq_spec_legacy[] = {
387 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
388 { -1, 0, 0 }
389 };
390
391 static struct resource_spec msk_irq_spec_msi[] = {
392 { SYS_RES_IRQ, 1, RF_ACTIVE },
393 { -1, 0, 0 }
394 };
395
396 static int
msk_miibus_readreg(device_t dev,int phy,int reg)397 msk_miibus_readreg(device_t dev, int phy, int reg)
398 {
399 struct msk_if_softc *sc_if;
400
401 sc_if = device_get_softc(dev);
402
403 return (msk_phy_readreg(sc_if, phy, reg));
404 }
405
406 static int
msk_phy_readreg(struct msk_if_softc * sc_if,int phy,int reg)407 msk_phy_readreg(struct msk_if_softc *sc_if, int phy, int reg)
408 {
409 struct msk_softc *sc;
410 int i, val;
411
412 sc = sc_if->msk_softc;
413
414 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_CTRL,
415 GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
416
417 for (i = 0; i < MSK_TIMEOUT; i++) {
418 DELAY(1);
419 val = GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_CTRL);
420 if ((val & GM_SMI_CT_RD_VAL) != 0) {
421 val = GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_DATA);
422 break;
423 }
424 }
425
426 if (i == MSK_TIMEOUT) {
427 if_printf(sc_if->msk_ifp, "phy failed to come ready\n");
428 val = 0;
429 }
430
431 return (val);
432 }
433
434 static int
msk_miibus_writereg(device_t dev,int phy,int reg,int val)435 msk_miibus_writereg(device_t dev, int phy, int reg, int val)
436 {
437 struct msk_if_softc *sc_if;
438
439 sc_if = device_get_softc(dev);
440
441 return (msk_phy_writereg(sc_if, phy, reg, val));
442 }
443
444 static int
msk_phy_writereg(struct msk_if_softc * sc_if,int phy,int reg,int val)445 msk_phy_writereg(struct msk_if_softc *sc_if, int phy, int reg, int val)
446 {
447 struct msk_softc *sc;
448 int i;
449
450 sc = sc_if->msk_softc;
451
452 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_DATA, val);
453 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_CTRL,
454 GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg));
455 for (i = 0; i < MSK_TIMEOUT; i++) {
456 DELAY(1);
457 if ((GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_CTRL) &
458 GM_SMI_CT_BUSY) == 0)
459 break;
460 }
461 if (i == MSK_TIMEOUT)
462 if_printf(sc_if->msk_ifp, "phy write timeout\n");
463
464 return (0);
465 }
466
467 static void
msk_miibus_statchg(device_t dev)468 msk_miibus_statchg(device_t dev)
469 {
470 struct msk_softc *sc;
471 struct msk_if_softc *sc_if;
472 struct mii_data *mii;
473 if_t ifp;
474 uint32_t gmac;
475
476 sc_if = device_get_softc(dev);
477 sc = sc_if->msk_softc;
478
479 MSK_IF_LOCK_ASSERT(sc_if);
480
481 mii = device_get_softc(sc_if->msk_miibus);
482 ifp = sc_if->msk_ifp;
483 if (mii == NULL || ifp == NULL ||
484 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0)
485 return;
486
487 sc_if->msk_flags &= ~MSK_FLAG_LINK;
488 if ((mii->mii_media_status & (IFM_AVALID | IFM_ACTIVE)) ==
489 (IFM_AVALID | IFM_ACTIVE)) {
490 switch (IFM_SUBTYPE(mii->mii_media_active)) {
491 case IFM_10_T:
492 case IFM_100_TX:
493 sc_if->msk_flags |= MSK_FLAG_LINK;
494 break;
495 case IFM_1000_T:
496 case IFM_1000_SX:
497 case IFM_1000_LX:
498 case IFM_1000_CX:
499 if ((sc_if->msk_flags & MSK_FLAG_FASTETHER) == 0)
500 sc_if->msk_flags |= MSK_FLAG_LINK;
501 break;
502 default:
503 break;
504 }
505 }
506
507 if ((sc_if->msk_flags & MSK_FLAG_LINK) != 0) {
508 /* Enable Tx FIFO Underrun. */
509 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_MSK),
510 GM_IS_TX_FF_UR | GM_IS_RX_FF_OR);
511 /*
512 * Because mii(4) notify msk(4) that it detected link status
513 * change, there is no need to enable automatic
514 * speed/flow-control/duplex updates.
515 */
516 gmac = GM_GPCR_AU_ALL_DIS;
517 switch (IFM_SUBTYPE(mii->mii_media_active)) {
518 case IFM_1000_SX:
519 case IFM_1000_T:
520 gmac |= GM_GPCR_SPEED_1000;
521 break;
522 case IFM_100_TX:
523 gmac |= GM_GPCR_SPEED_100;
524 break;
525 case IFM_10_T:
526 break;
527 }
528
529 if ((IFM_OPTIONS(mii->mii_media_active) &
530 IFM_ETH_RXPAUSE) == 0)
531 gmac |= GM_GPCR_FC_RX_DIS;
532 if ((IFM_OPTIONS(mii->mii_media_active) &
533 IFM_ETH_TXPAUSE) == 0)
534 gmac |= GM_GPCR_FC_TX_DIS;
535 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0)
536 gmac |= GM_GPCR_DUP_FULL;
537 else
538 gmac |= GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS;
539 gmac |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
540 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac);
541 /* Read again to ensure writing. */
542 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL);
543 gmac = GMC_PAUSE_OFF;
544 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
545 if ((IFM_OPTIONS(mii->mii_media_active) &
546 IFM_ETH_RXPAUSE) != 0)
547 gmac = GMC_PAUSE_ON;
548 }
549 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), gmac);
550
551 /* Enable PHY interrupt for FIFO underrun/overflow. */
552 msk_phy_writereg(sc_if, PHY_ADDR_MARV,
553 PHY_MARV_INT_MASK, PHY_M_IS_FIFO_ERROR);
554 } else {
555 /*
556 * Link state changed to down.
557 * Disable PHY interrupts.
558 */
559 msk_phy_writereg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_MASK, 0);
560 /* Disable Rx/Tx MAC. */
561 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL);
562 if ((gmac & (GM_GPCR_RX_ENA | GM_GPCR_TX_ENA)) != 0) {
563 gmac &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
564 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac);
565 /* Read again to ensure writing. */
566 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL);
567 }
568 }
569 }
570
571 static u_int
msk_hash_maddr(void * arg,struct sockaddr_dl * sdl,u_int cnt)572 msk_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
573 {
574 uint32_t *mchash = arg;
575 uint32_t crc;
576
577 crc = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN);
578 /* Just want the 6 least significant bits. */
579 crc &= 0x3f;
580 /* Set the corresponding bit in the hash table. */
581 mchash[crc >> 5] |= 1 << (crc & 0x1f);
582
583 return (1);
584 }
585
586 static void
msk_rxfilter(struct msk_if_softc * sc_if)587 msk_rxfilter(struct msk_if_softc *sc_if)
588 {
589 struct msk_softc *sc;
590 if_t ifp;
591 uint32_t mchash[2];
592 uint16_t mode;
593
594 sc = sc_if->msk_softc;
595
596 MSK_IF_LOCK_ASSERT(sc_if);
597
598 ifp = sc_if->msk_ifp;
599
600 bzero(mchash, sizeof(mchash));
601 mode = GMAC_READ_2(sc, sc_if->msk_port, GM_RX_CTRL);
602 if ((if_getflags(ifp) & IFF_PROMISC) != 0)
603 mode &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
604 else if ((if_getflags(ifp) & IFF_ALLMULTI) != 0) {
605 mode |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
606 mchash[0] = 0xffff;
607 mchash[1] = 0xffff;
608 } else {
609 mode |= GM_RXCR_UCF_ENA;
610 if_foreach_llmaddr(ifp, msk_hash_maddr, mchash);
611 if (mchash[0] != 0 || mchash[1] != 0)
612 mode |= GM_RXCR_MCF_ENA;
613 }
614
615 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H1,
616 mchash[0] & 0xffff);
617 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H2,
618 (mchash[0] >> 16) & 0xffff);
619 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H3,
620 mchash[1] & 0xffff);
621 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H4,
622 (mchash[1] >> 16) & 0xffff);
623 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, mode);
624 }
625
626 static void
msk_setvlan(struct msk_if_softc * sc_if,if_t ifp)627 msk_setvlan(struct msk_if_softc *sc_if, if_t ifp)
628 {
629 struct msk_softc *sc;
630
631 sc = sc_if->msk_softc;
632 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) {
633 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T),
634 RX_VLAN_STRIP_ON);
635 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
636 TX_VLAN_TAG_ON);
637 } else {
638 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T),
639 RX_VLAN_STRIP_OFF);
640 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
641 TX_VLAN_TAG_OFF);
642 }
643 }
644
645 static int
msk_rx_fill(struct msk_if_softc * sc_if,int jumbo)646 msk_rx_fill(struct msk_if_softc *sc_if, int jumbo)
647 {
648 uint16_t idx;
649 int i;
650
651 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 &&
652 (if_getcapenable(sc_if->msk_ifp) & IFCAP_RXCSUM) != 0) {
653 /* Wait until controller executes OP_TCPSTART command. */
654 for (i = 100; i > 0; i--) {
655 DELAY(100);
656 idx = CSR_READ_2(sc_if->msk_softc,
657 Y2_PREF_Q_ADDR(sc_if->msk_rxq,
658 PREF_UNIT_GET_IDX_REG));
659 if (idx != 0)
660 break;
661 }
662 if (i == 0) {
663 device_printf(sc_if->msk_if_dev,
664 "prefetch unit stuck?\n");
665 return (ETIMEDOUT);
666 }
667 /*
668 * Fill consumed LE with free buffer. This can be done
669 * in Rx handler but we don't want to add special code
670 * in fast handler.
671 */
672 if (jumbo > 0) {
673 if (msk_jumbo_newbuf(sc_if, 0) != 0)
674 return (ENOBUFS);
675 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_ring_tag,
676 sc_if->msk_cdata.msk_jumbo_rx_ring_map,
677 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
678 } else {
679 if (msk_newbuf(sc_if, 0) != 0)
680 return (ENOBUFS);
681 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_ring_tag,
682 sc_if->msk_cdata.msk_rx_ring_map,
683 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
684 }
685 sc_if->msk_cdata.msk_rx_prod = 0;
686 CSR_WRITE_2(sc_if->msk_softc,
687 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG),
688 sc_if->msk_cdata.msk_rx_prod);
689 }
690 return (0);
691 }
692
693 static int
msk_init_rx_ring(struct msk_if_softc * sc_if)694 msk_init_rx_ring(struct msk_if_softc *sc_if)
695 {
696 struct msk_ring_data *rd;
697 struct msk_rxdesc *rxd;
698 int i, nbuf, prod;
699
700 MSK_IF_LOCK_ASSERT(sc_if);
701
702 sc_if->msk_cdata.msk_rx_cons = 0;
703 sc_if->msk_cdata.msk_rx_prod = 0;
704 sc_if->msk_cdata.msk_rx_putwm = MSK_PUT_WM;
705
706 rd = &sc_if->msk_rdata;
707 bzero(rd->msk_rx_ring, sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT);
708 for (i = prod = 0; i < MSK_RX_RING_CNT; i++) {
709 rxd = &sc_if->msk_cdata.msk_rxdesc[prod];
710 rxd->rx_m = NULL;
711 rxd->rx_le = &rd->msk_rx_ring[prod];
712 MSK_INC(prod, MSK_RX_RING_CNT);
713 }
714 nbuf = MSK_RX_BUF_CNT;
715 prod = 0;
716 /* Have controller know how to compute Rx checksum. */
717 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 &&
718 (if_getcapenable(sc_if->msk_ifp) & IFCAP_RXCSUM) != 0) {
719 #ifdef MSK_64BIT_DMA
720 rxd = &sc_if->msk_cdata.msk_rxdesc[prod];
721 rxd->rx_m = NULL;
722 rxd->rx_le = &rd->msk_rx_ring[prod];
723 rxd->rx_le->msk_addr = htole32(ETHER_HDR_LEN << 16 |
724 ETHER_HDR_LEN);
725 rxd->rx_le->msk_control = htole32(OP_TCPSTART | HW_OWNER);
726 MSK_INC(prod, MSK_RX_RING_CNT);
727 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_RX_RING_CNT);
728 #endif
729 rxd = &sc_if->msk_cdata.msk_rxdesc[prod];
730 rxd->rx_m = NULL;
731 rxd->rx_le = &rd->msk_rx_ring[prod];
732 rxd->rx_le->msk_addr = htole32(ETHER_HDR_LEN << 16 |
733 ETHER_HDR_LEN);
734 rxd->rx_le->msk_control = htole32(OP_TCPSTART | HW_OWNER);
735 MSK_INC(prod, MSK_RX_RING_CNT);
736 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_RX_RING_CNT);
737 nbuf--;
738 }
739 for (i = 0; i < nbuf; i++) {
740 if (msk_newbuf(sc_if, prod) != 0)
741 return (ENOBUFS);
742 MSK_RX_INC(prod, MSK_RX_RING_CNT);
743 }
744
745 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_ring_tag,
746 sc_if->msk_cdata.msk_rx_ring_map,
747 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
748
749 /* Update prefetch unit. */
750 sc_if->msk_cdata.msk_rx_prod = prod;
751 CSR_WRITE_2(sc_if->msk_softc,
752 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG),
753 (sc_if->msk_cdata.msk_rx_prod + MSK_RX_RING_CNT - 1) %
754 MSK_RX_RING_CNT);
755 if (msk_rx_fill(sc_if, 0) != 0)
756 return (ENOBUFS);
757 return (0);
758 }
759
760 static int
msk_init_jumbo_rx_ring(struct msk_if_softc * sc_if)761 msk_init_jumbo_rx_ring(struct msk_if_softc *sc_if)
762 {
763 struct msk_ring_data *rd;
764 struct msk_rxdesc *rxd;
765 int i, nbuf, prod;
766
767 MSK_IF_LOCK_ASSERT(sc_if);
768
769 sc_if->msk_cdata.msk_rx_cons = 0;
770 sc_if->msk_cdata.msk_rx_prod = 0;
771 sc_if->msk_cdata.msk_rx_putwm = MSK_PUT_WM;
772
773 rd = &sc_if->msk_rdata;
774 bzero(rd->msk_jumbo_rx_ring,
775 sizeof(struct msk_rx_desc) * MSK_JUMBO_RX_RING_CNT);
776 for (i = prod = 0; i < MSK_JUMBO_RX_RING_CNT; i++) {
777 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[prod];
778 rxd->rx_m = NULL;
779 rxd->rx_le = &rd->msk_jumbo_rx_ring[prod];
780 MSK_INC(prod, MSK_JUMBO_RX_RING_CNT);
781 }
782 nbuf = MSK_RX_BUF_CNT;
783 prod = 0;
784 /* Have controller know how to compute Rx checksum. */
785 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 &&
786 (if_getcapenable(sc_if->msk_ifp) & IFCAP_RXCSUM) != 0) {
787 #ifdef MSK_64BIT_DMA
788 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[prod];
789 rxd->rx_m = NULL;
790 rxd->rx_le = &rd->msk_jumbo_rx_ring[prod];
791 rxd->rx_le->msk_addr = htole32(ETHER_HDR_LEN << 16 |
792 ETHER_HDR_LEN);
793 rxd->rx_le->msk_control = htole32(OP_TCPSTART | HW_OWNER);
794 MSK_INC(prod, MSK_JUMBO_RX_RING_CNT);
795 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_JUMBO_RX_RING_CNT);
796 #endif
797 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[prod];
798 rxd->rx_m = NULL;
799 rxd->rx_le = &rd->msk_jumbo_rx_ring[prod];
800 rxd->rx_le->msk_addr = htole32(ETHER_HDR_LEN << 16 |
801 ETHER_HDR_LEN);
802 rxd->rx_le->msk_control = htole32(OP_TCPSTART | HW_OWNER);
803 MSK_INC(prod, MSK_JUMBO_RX_RING_CNT);
804 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_JUMBO_RX_RING_CNT);
805 nbuf--;
806 }
807 for (i = 0; i < nbuf; i++) {
808 if (msk_jumbo_newbuf(sc_if, prod) != 0)
809 return (ENOBUFS);
810 MSK_RX_INC(prod, MSK_JUMBO_RX_RING_CNT);
811 }
812
813 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_ring_tag,
814 sc_if->msk_cdata.msk_jumbo_rx_ring_map,
815 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
816
817 /* Update prefetch unit. */
818 sc_if->msk_cdata.msk_rx_prod = prod;
819 CSR_WRITE_2(sc_if->msk_softc,
820 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG),
821 (sc_if->msk_cdata.msk_rx_prod + MSK_JUMBO_RX_RING_CNT - 1) %
822 MSK_JUMBO_RX_RING_CNT);
823 if (msk_rx_fill(sc_if, 1) != 0)
824 return (ENOBUFS);
825 return (0);
826 }
827
828 static void
msk_init_tx_ring(struct msk_if_softc * sc_if)829 msk_init_tx_ring(struct msk_if_softc *sc_if)
830 {
831 struct msk_ring_data *rd;
832 struct msk_txdesc *txd;
833 int i;
834
835 sc_if->msk_cdata.msk_tso_mtu = 0;
836 sc_if->msk_cdata.msk_last_csum = 0;
837 sc_if->msk_cdata.msk_tx_prod = 0;
838 sc_if->msk_cdata.msk_tx_cons = 0;
839 sc_if->msk_cdata.msk_tx_cnt = 0;
840 sc_if->msk_cdata.msk_tx_high_addr = 0;
841
842 rd = &sc_if->msk_rdata;
843 bzero(rd->msk_tx_ring, sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT);
844 for (i = 0; i < MSK_TX_RING_CNT; i++) {
845 txd = &sc_if->msk_cdata.msk_txdesc[i];
846 txd->tx_m = NULL;
847 txd->tx_le = &rd->msk_tx_ring[i];
848 }
849
850 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag,
851 sc_if->msk_cdata.msk_tx_ring_map,
852 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
853 }
854
855 static __inline void
msk_discard_rxbuf(struct msk_if_softc * sc_if,int idx)856 msk_discard_rxbuf(struct msk_if_softc *sc_if, int idx)
857 {
858 struct msk_rx_desc *rx_le;
859 struct msk_rxdesc *rxd;
860 struct mbuf *m;
861
862 #ifdef MSK_64BIT_DMA
863 rxd = &sc_if->msk_cdata.msk_rxdesc[idx];
864 rx_le = rxd->rx_le;
865 rx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER);
866 MSK_INC(idx, MSK_RX_RING_CNT);
867 #endif
868 rxd = &sc_if->msk_cdata.msk_rxdesc[idx];
869 m = rxd->rx_m;
870 rx_le = rxd->rx_le;
871 rx_le->msk_control = htole32(m->m_len | OP_PACKET | HW_OWNER);
872 }
873
874 static __inline void
msk_discard_jumbo_rxbuf(struct msk_if_softc * sc_if,int idx)875 msk_discard_jumbo_rxbuf(struct msk_if_softc *sc_if, int idx)
876 {
877 struct msk_rx_desc *rx_le;
878 struct msk_rxdesc *rxd;
879 struct mbuf *m;
880
881 #ifdef MSK_64BIT_DMA
882 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx];
883 rx_le = rxd->rx_le;
884 rx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER);
885 MSK_INC(idx, MSK_JUMBO_RX_RING_CNT);
886 #endif
887 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx];
888 m = rxd->rx_m;
889 rx_le = rxd->rx_le;
890 rx_le->msk_control = htole32(m->m_len | OP_PACKET | HW_OWNER);
891 }
892
893 static int
msk_newbuf(struct msk_if_softc * sc_if,int idx)894 msk_newbuf(struct msk_if_softc *sc_if, int idx)
895 {
896 struct msk_rx_desc *rx_le;
897 struct msk_rxdesc *rxd;
898 struct mbuf *m;
899 bus_dma_segment_t segs[1];
900 bus_dmamap_t map;
901 int nsegs;
902
903 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
904 if (m == NULL)
905 return (ENOBUFS);
906
907 m->m_len = m->m_pkthdr.len = MCLBYTES;
908 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0)
909 m_adj(m, ETHER_ALIGN);
910 #ifndef __NO_STRICT_ALIGNMENT
911 else
912 m_adj(m, MSK_RX_BUF_ALIGN);
913 #endif
914
915 if (bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_rx_tag,
916 sc_if->msk_cdata.msk_rx_sparemap, m, segs, &nsegs,
917 BUS_DMA_NOWAIT) != 0) {
918 m_freem(m);
919 return (ENOBUFS);
920 }
921 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
922
923 rxd = &sc_if->msk_cdata.msk_rxdesc[idx];
924 #ifdef MSK_64BIT_DMA
925 rx_le = rxd->rx_le;
926 rx_le->msk_addr = htole32(MSK_ADDR_HI(segs[0].ds_addr));
927 rx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER);
928 MSK_INC(idx, MSK_RX_RING_CNT);
929 rxd = &sc_if->msk_cdata.msk_rxdesc[idx];
930 #endif
931 if (rxd->rx_m != NULL) {
932 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap,
933 BUS_DMASYNC_POSTREAD);
934 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap);
935 rxd->rx_m = NULL;
936 }
937 map = rxd->rx_dmamap;
938 rxd->rx_dmamap = sc_if->msk_cdata.msk_rx_sparemap;
939 sc_if->msk_cdata.msk_rx_sparemap = map;
940 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap,
941 BUS_DMASYNC_PREREAD);
942 rxd->rx_m = m;
943 rx_le = rxd->rx_le;
944 rx_le->msk_addr = htole32(MSK_ADDR_LO(segs[0].ds_addr));
945 rx_le->msk_control =
946 htole32(segs[0].ds_len | OP_PACKET | HW_OWNER);
947
948 return (0);
949 }
950
951 static int
msk_jumbo_newbuf(struct msk_if_softc * sc_if,int idx)952 msk_jumbo_newbuf(struct msk_if_softc *sc_if, int idx)
953 {
954 struct msk_rx_desc *rx_le;
955 struct msk_rxdesc *rxd;
956 struct mbuf *m;
957 bus_dma_segment_t segs[1];
958 bus_dmamap_t map;
959 int nsegs;
960
961 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES);
962 if (m == NULL)
963 return (ENOBUFS);
964 m->m_len = m->m_pkthdr.len = MJUM9BYTES;
965 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0)
966 m_adj(m, ETHER_ALIGN);
967 #ifndef __NO_STRICT_ALIGNMENT
968 else
969 m_adj(m, MSK_RX_BUF_ALIGN);
970 #endif
971
972 if (bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_jumbo_rx_tag,
973 sc_if->msk_cdata.msk_jumbo_rx_sparemap, m, segs, &nsegs,
974 BUS_DMA_NOWAIT) != 0) {
975 m_freem(m);
976 return (ENOBUFS);
977 }
978 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
979
980 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx];
981 #ifdef MSK_64BIT_DMA
982 rx_le = rxd->rx_le;
983 rx_le->msk_addr = htole32(MSK_ADDR_HI(segs[0].ds_addr));
984 rx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER);
985 MSK_INC(idx, MSK_JUMBO_RX_RING_CNT);
986 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx];
987 #endif
988 if (rxd->rx_m != NULL) {
989 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag,
990 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
991 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_tag,
992 rxd->rx_dmamap);
993 rxd->rx_m = NULL;
994 }
995 map = rxd->rx_dmamap;
996 rxd->rx_dmamap = sc_if->msk_cdata.msk_jumbo_rx_sparemap;
997 sc_if->msk_cdata.msk_jumbo_rx_sparemap = map;
998 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, rxd->rx_dmamap,
999 BUS_DMASYNC_PREREAD);
1000 rxd->rx_m = m;
1001 rx_le = rxd->rx_le;
1002 rx_le->msk_addr = htole32(MSK_ADDR_LO(segs[0].ds_addr));
1003 rx_le->msk_control =
1004 htole32(segs[0].ds_len | OP_PACKET | HW_OWNER);
1005
1006 return (0);
1007 }
1008
1009 /*
1010 * Set media options.
1011 */
1012 static int
msk_mediachange(if_t ifp)1013 msk_mediachange(if_t ifp)
1014 {
1015 struct msk_if_softc *sc_if;
1016 struct mii_data *mii;
1017 int error;
1018
1019 sc_if = if_getsoftc(ifp);
1020
1021 MSK_IF_LOCK(sc_if);
1022 mii = device_get_softc(sc_if->msk_miibus);
1023 error = mii_mediachg(mii);
1024 MSK_IF_UNLOCK(sc_if);
1025
1026 return (error);
1027 }
1028
1029 /*
1030 * Report current media status.
1031 */
1032 static void
msk_mediastatus(if_t ifp,struct ifmediareq * ifmr)1033 msk_mediastatus(if_t ifp, struct ifmediareq *ifmr)
1034 {
1035 struct msk_if_softc *sc_if;
1036 struct mii_data *mii;
1037
1038 sc_if = if_getsoftc(ifp);
1039 MSK_IF_LOCK(sc_if);
1040 if ((if_getflags(ifp) & IFF_UP) == 0) {
1041 MSK_IF_UNLOCK(sc_if);
1042 return;
1043 }
1044 mii = device_get_softc(sc_if->msk_miibus);
1045
1046 mii_pollstat(mii);
1047 ifmr->ifm_active = mii->mii_media_active;
1048 ifmr->ifm_status = mii->mii_media_status;
1049 MSK_IF_UNLOCK(sc_if);
1050 }
1051
1052 static int
msk_ioctl(if_t ifp,u_long command,caddr_t data)1053 msk_ioctl(if_t ifp, u_long command, caddr_t data)
1054 {
1055 struct msk_if_softc *sc_if;
1056 struct ifreq *ifr;
1057 struct mii_data *mii;
1058 int error, mask, reinit;
1059
1060 sc_if = if_getsoftc(ifp);
1061 ifr = (struct ifreq *)data;
1062 error = 0;
1063
1064 switch(command) {
1065 case SIOCSIFMTU:
1066 MSK_IF_LOCK(sc_if);
1067 if (ifr->ifr_mtu > MSK_JUMBO_MTU || ifr->ifr_mtu < ETHERMIN)
1068 error = EINVAL;
1069 else if (if_getmtu(ifp) != ifr->ifr_mtu) {
1070 if (ifr->ifr_mtu > ETHERMTU) {
1071 if ((sc_if->msk_flags & MSK_FLAG_JUMBO) == 0) {
1072 error = EINVAL;
1073 MSK_IF_UNLOCK(sc_if);
1074 break;
1075 }
1076 if ((sc_if->msk_flags &
1077 MSK_FLAG_JUMBO_NOCSUM) != 0) {
1078 if_sethwassistbits(ifp, 0,
1079 MSK_CSUM_FEATURES | CSUM_TSO);
1080 if_setcapenablebit(ifp, 0,
1081 IFCAP_TSO4 | IFCAP_TXCSUM);
1082 VLAN_CAPABILITIES(ifp);
1083 }
1084 }
1085 if_setmtu(ifp, ifr->ifr_mtu);
1086 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) {
1087 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1088 msk_init_locked(sc_if);
1089 }
1090 }
1091 MSK_IF_UNLOCK(sc_if);
1092 break;
1093 case SIOCSIFFLAGS:
1094 MSK_IF_LOCK(sc_if);
1095 if ((if_getflags(ifp) & IFF_UP) != 0) {
1096 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0 &&
1097 ((if_getflags(ifp) ^ sc_if->msk_if_flags) &
1098 (IFF_PROMISC | IFF_ALLMULTI)) != 0)
1099 msk_rxfilter(sc_if);
1100 else if ((sc_if->msk_flags & MSK_FLAG_DETACH) == 0)
1101 msk_init_locked(sc_if);
1102 } else if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)
1103 msk_stop(sc_if);
1104 sc_if->msk_if_flags = if_getflags(ifp);
1105 MSK_IF_UNLOCK(sc_if);
1106 break;
1107 case SIOCADDMULTI:
1108 case SIOCDELMULTI:
1109 MSK_IF_LOCK(sc_if);
1110 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)
1111 msk_rxfilter(sc_if);
1112 MSK_IF_UNLOCK(sc_if);
1113 break;
1114 case SIOCGIFMEDIA:
1115 case SIOCSIFMEDIA:
1116 mii = device_get_softc(sc_if->msk_miibus);
1117 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1118 break;
1119 case SIOCSIFCAP:
1120 reinit = 0;
1121 MSK_IF_LOCK(sc_if);
1122 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp);
1123 if ((mask & IFCAP_TXCSUM) != 0 &&
1124 (IFCAP_TXCSUM & if_getcapabilities(ifp)) != 0) {
1125 if_togglecapenable(ifp, IFCAP_TXCSUM);
1126 if ((IFCAP_TXCSUM & if_getcapenable(ifp)) != 0)
1127 if_sethwassistbits(ifp, MSK_CSUM_FEATURES, 0);
1128 else
1129 if_sethwassistbits(ifp, 0, MSK_CSUM_FEATURES);
1130 }
1131 if ((mask & IFCAP_RXCSUM) != 0 &&
1132 (IFCAP_RXCSUM & if_getcapabilities(ifp)) != 0) {
1133 if_togglecapenable(ifp, IFCAP_RXCSUM);
1134 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0)
1135 reinit = 1;
1136 }
1137 if ((mask & IFCAP_VLAN_HWCSUM) != 0 &&
1138 (IFCAP_VLAN_HWCSUM & if_getcapabilities(ifp)) != 0)
1139 if_togglecapenable(ifp, IFCAP_VLAN_HWCSUM);
1140 if ((mask & IFCAP_TSO4) != 0 &&
1141 (IFCAP_TSO4 & if_getcapabilities(ifp)) != 0) {
1142 if_togglecapenable(ifp, IFCAP_TSO4);
1143 if ((IFCAP_TSO4 & if_getcapenable(ifp)) != 0)
1144 if_sethwassistbits(ifp, CSUM_TSO, 0);
1145 else
1146 if_sethwassistbits(ifp, 0, CSUM_TSO);
1147 }
1148 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
1149 (IFCAP_VLAN_HWTSO & if_getcapabilities(ifp)) != 0)
1150 if_togglecapenable(ifp, IFCAP_VLAN_HWTSO);
1151 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
1152 (IFCAP_VLAN_HWTAGGING & if_getcapabilities(ifp)) != 0) {
1153 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING);
1154 if ((IFCAP_VLAN_HWTAGGING & if_getcapenable(ifp)) == 0)
1155 if_setcapenablebit(ifp, 0,
1156 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM);
1157 msk_setvlan(sc_if, ifp);
1158 }
1159 if (if_getmtu(ifp) > ETHERMTU &&
1160 (sc_if->msk_flags & MSK_FLAG_JUMBO_NOCSUM) != 0) {
1161 if_sethwassistbits(ifp, 0, (MSK_CSUM_FEATURES | CSUM_TSO));
1162 if_setcapenablebit(ifp, 0, (IFCAP_TSO4 | IFCAP_TXCSUM));
1163 }
1164 VLAN_CAPABILITIES(ifp);
1165 if (reinit > 0 && (if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) {
1166 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1167 msk_init_locked(sc_if);
1168 }
1169 MSK_IF_UNLOCK(sc_if);
1170 break;
1171 default:
1172 error = ether_ioctl(ifp, command, data);
1173 break;
1174 }
1175
1176 return (error);
1177 }
1178
1179 static int
mskc_probe(device_t dev)1180 mskc_probe(device_t dev)
1181 {
1182 const struct msk_product *mp;
1183 uint16_t vendor, devid;
1184 int i;
1185
1186 vendor = pci_get_vendor(dev);
1187 devid = pci_get_device(dev);
1188 mp = msk_products;
1189 for (i = 0; i < nitems(msk_products); i++, mp++) {
1190 if (vendor == mp->msk_vendorid && devid == mp->msk_deviceid) {
1191 device_set_desc(dev, mp->msk_name);
1192 return (BUS_PROBE_DEFAULT);
1193 }
1194 }
1195
1196 return (ENXIO);
1197 }
1198
1199 static int
mskc_setup_rambuffer(struct msk_softc * sc)1200 mskc_setup_rambuffer(struct msk_softc *sc)
1201 {
1202 int next;
1203 int i;
1204
1205 /* Get adapter SRAM size. */
1206 sc->msk_ramsize = CSR_READ_1(sc, B2_E_0) * 4;
1207 if (bootverbose)
1208 device_printf(sc->msk_dev,
1209 "RAM buffer size : %dKB\n", sc->msk_ramsize);
1210 if (sc->msk_ramsize == 0)
1211 return (0);
1212
1213 sc->msk_pflags |= MSK_FLAG_RAMBUF;
1214 /*
1215 * Give receiver 2/3 of memory and round down to the multiple
1216 * of 1024. Tx/Rx RAM buffer size of Yukon II should be multiple
1217 * of 1024.
1218 */
1219 sc->msk_rxqsize = rounddown((sc->msk_ramsize * 1024 * 2) / 3, 1024);
1220 sc->msk_txqsize = (sc->msk_ramsize * 1024) - sc->msk_rxqsize;
1221 for (i = 0, next = 0; i < sc->msk_num_port; i++) {
1222 sc->msk_rxqstart[i] = next;
1223 sc->msk_rxqend[i] = next + sc->msk_rxqsize - 1;
1224 next = sc->msk_rxqend[i] + 1;
1225 sc->msk_txqstart[i] = next;
1226 sc->msk_txqend[i] = next + sc->msk_txqsize - 1;
1227 next = sc->msk_txqend[i] + 1;
1228 if (bootverbose) {
1229 device_printf(sc->msk_dev,
1230 "Port %d : Rx Queue %dKB(0x%08x:0x%08x)\n", i,
1231 sc->msk_rxqsize / 1024, sc->msk_rxqstart[i],
1232 sc->msk_rxqend[i]);
1233 device_printf(sc->msk_dev,
1234 "Port %d : Tx Queue %dKB(0x%08x:0x%08x)\n", i,
1235 sc->msk_txqsize / 1024, sc->msk_txqstart[i],
1236 sc->msk_txqend[i]);
1237 }
1238 }
1239
1240 return (0);
1241 }
1242
1243 static void
msk_phy_power(struct msk_softc * sc,int mode)1244 msk_phy_power(struct msk_softc *sc, int mode)
1245 {
1246 uint32_t our, val;
1247 int i;
1248
1249 switch (mode) {
1250 case MSK_PHY_POWERUP:
1251 /* Switch power to VCC (WA for VAUX problem). */
1252 CSR_WRITE_1(sc, B0_POWER_CTRL,
1253 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
1254 /* Disable Core Clock Division, set Clock Select to 0. */
1255 CSR_WRITE_4(sc, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
1256
1257 val = 0;
1258 if (sc->msk_hw_id == CHIP_ID_YUKON_XL &&
1259 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) {
1260 /* Enable bits are inverted. */
1261 val = Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
1262 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
1263 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS;
1264 }
1265 /*
1266 * Enable PCI & Core Clock, enable clock gating for both Links.
1267 */
1268 CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val);
1269
1270 our = CSR_PCI_READ_4(sc, PCI_OUR_REG_1);
1271 our &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
1272 if (sc->msk_hw_id == CHIP_ID_YUKON_XL) {
1273 if (sc->msk_hw_rev > CHIP_REV_YU_XL_A1) {
1274 /* Deassert Low Power for 1st PHY. */
1275 our |= PCI_Y2_PHY1_COMA;
1276 if (sc->msk_num_port > 1)
1277 our |= PCI_Y2_PHY2_COMA;
1278 }
1279 }
1280 if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U ||
1281 sc->msk_hw_id == CHIP_ID_YUKON_EX ||
1282 sc->msk_hw_id >= CHIP_ID_YUKON_FE_P) {
1283 val = CSR_PCI_READ_4(sc, PCI_OUR_REG_4);
1284 val &= (PCI_FORCE_ASPM_REQUEST |
1285 PCI_ASPM_GPHY_LINK_DOWN | PCI_ASPM_INT_FIFO_EMPTY |
1286 PCI_ASPM_CLKRUN_REQUEST);
1287 /* Set all bits to 0 except bits 15..12. */
1288 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_4, val);
1289 val = CSR_PCI_READ_4(sc, PCI_OUR_REG_5);
1290 val &= PCI_CTL_TIM_VMAIN_AV_MSK;
1291 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_5, val);
1292 CSR_PCI_WRITE_4(sc, PCI_CFG_REG_1, 0);
1293 CSR_WRITE_2(sc, B0_CTST, Y2_HW_WOL_ON);
1294 /*
1295 * Disable status race, workaround for
1296 * Yukon EC Ultra & Yukon EX.
1297 */
1298 val = CSR_READ_4(sc, B2_GP_IO);
1299 val |= GLB_GPIO_STAT_RACE_DIS;
1300 CSR_WRITE_4(sc, B2_GP_IO, val);
1301 CSR_READ_4(sc, B2_GP_IO);
1302 }
1303 /* Release PHY from PowerDown/COMA mode. */
1304 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_1, our);
1305
1306 for (i = 0; i < sc->msk_num_port; i++) {
1307 CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL),
1308 GMLC_RST_SET);
1309 CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL),
1310 GMLC_RST_CLR);
1311 }
1312 break;
1313 case MSK_PHY_POWERDOWN:
1314 val = CSR_PCI_READ_4(sc, PCI_OUR_REG_1);
1315 val |= PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD;
1316 if (sc->msk_hw_id == CHIP_ID_YUKON_XL &&
1317 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) {
1318 val &= ~PCI_Y2_PHY1_COMA;
1319 if (sc->msk_num_port > 1)
1320 val &= ~PCI_Y2_PHY2_COMA;
1321 }
1322 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_1, val);
1323
1324 val = Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
1325 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
1326 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS;
1327 if (sc->msk_hw_id == CHIP_ID_YUKON_XL &&
1328 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) {
1329 /* Enable bits are inverted. */
1330 val = 0;
1331 }
1332 /*
1333 * Disable PCI & Core Clock, disable clock gating for
1334 * both Links.
1335 */
1336 CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val);
1337 CSR_WRITE_1(sc, B0_POWER_CTRL,
1338 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF);
1339 break;
1340 default:
1341 break;
1342 }
1343 }
1344
1345 static void
mskc_reset(struct msk_softc * sc)1346 mskc_reset(struct msk_softc *sc)
1347 {
1348 bus_addr_t addr;
1349 uint16_t status;
1350 uint32_t val;
1351 int i, initram;
1352
1353 /* Disable ASF. */
1354 if (sc->msk_hw_id >= CHIP_ID_YUKON_XL &&
1355 sc->msk_hw_id <= CHIP_ID_YUKON_SUPR) {
1356 if (sc->msk_hw_id == CHIP_ID_YUKON_EX ||
1357 sc->msk_hw_id == CHIP_ID_YUKON_SUPR) {
1358 CSR_WRITE_4(sc, B28_Y2_CPU_WDOG, 0);
1359 status = CSR_READ_2(sc, B28_Y2_ASF_HCU_CCSR);
1360 /* Clear AHB bridge & microcontroller reset. */
1361 status &= ~(Y2_ASF_HCU_CCSR_AHB_RST |
1362 Y2_ASF_HCU_CCSR_CPU_RST_MODE);
1363 /* Clear ASF microcontroller state. */
1364 status &= ~Y2_ASF_HCU_CCSR_UC_STATE_MSK;
1365 status &= ~Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE_MSK;
1366 CSR_WRITE_2(sc, B28_Y2_ASF_HCU_CCSR, status);
1367 CSR_WRITE_4(sc, B28_Y2_CPU_WDOG, 0);
1368 } else
1369 CSR_WRITE_1(sc, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
1370 CSR_WRITE_2(sc, B0_CTST, Y2_ASF_DISABLE);
1371 /*
1372 * Since we disabled ASF, S/W reset is required for
1373 * Power Management.
1374 */
1375 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET);
1376 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR);
1377 }
1378
1379 /* Clear all error bits in the PCI status register. */
1380 status = pci_read_config(sc->msk_dev, PCIR_STATUS, 2);
1381 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON);
1382
1383 pci_write_config(sc->msk_dev, PCIR_STATUS, status |
1384 PCIM_STATUS_PERR | PCIM_STATUS_SERR | PCIM_STATUS_RMABORT |
1385 PCIM_STATUS_RTABORT | PCIM_STATUS_MDPERR, 2);
1386 CSR_WRITE_2(sc, B0_CTST, CS_MRST_CLR);
1387
1388 switch (sc->msk_bustype) {
1389 case MSK_PEX_BUS:
1390 /* Clear all PEX errors. */
1391 CSR_PCI_WRITE_4(sc, PEX_UNC_ERR_STAT, 0xffffffff);
1392 val = CSR_PCI_READ_4(sc, PEX_UNC_ERR_STAT);
1393 if ((val & PEX_RX_OV) != 0) {
1394 sc->msk_intrmask &= ~Y2_IS_HW_ERR;
1395 sc->msk_intrhwemask &= ~Y2_IS_PCI_EXP;
1396 }
1397 break;
1398 case MSK_PCI_BUS:
1399 case MSK_PCIX_BUS:
1400 /* Set Cache Line Size to 2(8bytes) if configured to 0. */
1401 val = pci_read_config(sc->msk_dev, PCIR_CACHELNSZ, 1);
1402 if (val == 0)
1403 pci_write_config(sc->msk_dev, PCIR_CACHELNSZ, 2, 1);
1404 if (sc->msk_bustype == MSK_PCIX_BUS) {
1405 /* Set Cache Line Size opt. */
1406 val = pci_read_config(sc->msk_dev, PCI_OUR_REG_1, 4);
1407 val |= PCI_CLS_OPT;
1408 pci_write_config(sc->msk_dev, PCI_OUR_REG_1, val, 4);
1409 }
1410 break;
1411 }
1412 /* Set PHY power state. */
1413 msk_phy_power(sc, MSK_PHY_POWERUP);
1414
1415 /* Reset GPHY/GMAC Control */
1416 for (i = 0; i < sc->msk_num_port; i++) {
1417 /* GPHY Control reset. */
1418 CSR_WRITE_1(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_SET);
1419 CSR_WRITE_1(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_CLR);
1420 /* GMAC Control reset. */
1421 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_SET);
1422 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_CLR);
1423 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_F_LOOPB_OFF);
1424 if (sc->msk_hw_id == CHIP_ID_YUKON_EX ||
1425 sc->msk_hw_id == CHIP_ID_YUKON_SUPR)
1426 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL),
1427 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON |
1428 GMC_BYP_RETR_ON);
1429 }
1430
1431 if (sc->msk_hw_id == CHIP_ID_YUKON_SUPR &&
1432 sc->msk_hw_rev > CHIP_REV_YU_SU_B0)
1433 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_3, PCI_CLK_MACSEC_DIS);
1434 if (sc->msk_hw_id == CHIP_ID_YUKON_OPT && sc->msk_hw_rev == 0) {
1435 /* Disable PCIe PHY powerdown(reg 0x80, bit7). */
1436 CSR_WRITE_4(sc, Y2_PEX_PHY_DATA, (0x0080 << 16) | 0x0080);
1437 }
1438 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
1439
1440 /* LED On. */
1441 CSR_WRITE_2(sc, B0_CTST, Y2_LED_STAT_ON);
1442
1443 /* Clear TWSI IRQ. */
1444 CSR_WRITE_4(sc, B2_I2C_IRQ, I2C_CLR_IRQ);
1445
1446 /* Turn off hardware timer. */
1447 CSR_WRITE_1(sc, B2_TI_CTRL, TIM_STOP);
1448 CSR_WRITE_1(sc, B2_TI_CTRL, TIM_CLR_IRQ);
1449
1450 /* Turn off descriptor polling. */
1451 CSR_WRITE_1(sc, B28_DPT_CTRL, DPT_STOP);
1452
1453 /* Turn off time stamps. */
1454 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_STOP);
1455 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
1456
1457 initram = 0;
1458 if (sc->msk_hw_id == CHIP_ID_YUKON_XL ||
1459 sc->msk_hw_id == CHIP_ID_YUKON_EC ||
1460 sc->msk_hw_id == CHIP_ID_YUKON_FE)
1461 initram++;
1462
1463 /* Configure timeout values. */
1464 for (i = 0; initram > 0 && i < sc->msk_num_port; i++) {
1465 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_SET);
1466 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
1467 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_R1),
1468 MSK_RI_TO_53);
1469 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA1),
1470 MSK_RI_TO_53);
1471 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS1),
1472 MSK_RI_TO_53);
1473 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_R1),
1474 MSK_RI_TO_53);
1475 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA1),
1476 MSK_RI_TO_53);
1477 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS1),
1478 MSK_RI_TO_53);
1479 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_R2),
1480 MSK_RI_TO_53);
1481 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA2),
1482 MSK_RI_TO_53);
1483 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS2),
1484 MSK_RI_TO_53);
1485 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_R2),
1486 MSK_RI_TO_53);
1487 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA2),
1488 MSK_RI_TO_53);
1489 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS2),
1490 MSK_RI_TO_53);
1491 }
1492
1493 /* Disable all interrupts. */
1494 CSR_WRITE_4(sc, B0_HWE_IMSK, 0);
1495 CSR_READ_4(sc, B0_HWE_IMSK);
1496 CSR_WRITE_4(sc, B0_IMSK, 0);
1497 CSR_READ_4(sc, B0_IMSK);
1498
1499 /*
1500 * On dual port PCI-X card, there is an problem where status
1501 * can be received out of order due to split transactions.
1502 */
1503 if (sc->msk_pcixcap != 0 && sc->msk_num_port > 1) {
1504 uint16_t pcix_cmd;
1505
1506 pcix_cmd = pci_read_config(sc->msk_dev,
1507 sc->msk_pcixcap + PCIXR_COMMAND, 2);
1508 /* Clear Max Outstanding Split Transactions. */
1509 pcix_cmd &= ~PCIXM_COMMAND_MAX_SPLITS;
1510 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON);
1511 pci_write_config(sc->msk_dev,
1512 sc->msk_pcixcap + PCIXR_COMMAND, pcix_cmd, 2);
1513 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
1514 }
1515 if (sc->msk_expcap != 0) {
1516 /* Change Max. Read Request Size to 2048 bytes. */
1517 if (pci_get_max_read_req(sc->msk_dev) == 512)
1518 pci_set_max_read_req(sc->msk_dev, 2048);
1519 }
1520
1521 /* Clear status list. */
1522 bzero(sc->msk_stat_ring,
1523 sizeof(struct msk_stat_desc) * sc->msk_stat_count);
1524 sc->msk_stat_cons = 0;
1525 bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map,
1526 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1527 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_RST_SET);
1528 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_RST_CLR);
1529 /* Set the status list base address. */
1530 addr = sc->msk_stat_ring_paddr;
1531 CSR_WRITE_4(sc, STAT_LIST_ADDR_LO, MSK_ADDR_LO(addr));
1532 CSR_WRITE_4(sc, STAT_LIST_ADDR_HI, MSK_ADDR_HI(addr));
1533 /* Set the status list last index. */
1534 CSR_WRITE_2(sc, STAT_LAST_IDX, sc->msk_stat_count - 1);
1535 if (sc->msk_hw_id == CHIP_ID_YUKON_EC &&
1536 sc->msk_hw_rev == CHIP_REV_YU_EC_A1) {
1537 /* WA for dev. #4.3 */
1538 CSR_WRITE_2(sc, STAT_TX_IDX_TH, ST_TXTH_IDX_MASK);
1539 /* WA for dev. #4.18 */
1540 CSR_WRITE_1(sc, STAT_FIFO_WM, 0x21);
1541 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x07);
1542 } else {
1543 CSR_WRITE_2(sc, STAT_TX_IDX_TH, 0x0a);
1544 CSR_WRITE_1(sc, STAT_FIFO_WM, 0x10);
1545 if (sc->msk_hw_id == CHIP_ID_YUKON_XL &&
1546 sc->msk_hw_rev == CHIP_REV_YU_XL_A0)
1547 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x04);
1548 else
1549 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x10);
1550 CSR_WRITE_4(sc, STAT_ISR_TIMER_INI, 0x0190);
1551 }
1552 /*
1553 * Use default value for STAT_ISR_TIMER_INI, STAT_LEV_TIMER_INI.
1554 */
1555 CSR_WRITE_4(sc, STAT_TX_TIMER_INI, MSK_USECS(sc, 1000));
1556
1557 /* Enable status unit. */
1558 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_OP_ON);
1559
1560 CSR_WRITE_1(sc, STAT_TX_TIMER_CTRL, TIM_START);
1561 CSR_WRITE_1(sc, STAT_LEV_TIMER_CTRL, TIM_START);
1562 CSR_WRITE_1(sc, STAT_ISR_TIMER_CTRL, TIM_START);
1563 }
1564
1565 static int
msk_probe(device_t dev)1566 msk_probe(device_t dev)
1567 {
1568 struct msk_softc *sc;
1569
1570 sc = device_get_softc(device_get_parent(dev));
1571 /*
1572 * Not much to do here. We always know there will be
1573 * at least one GMAC present, and if there are two,
1574 * mskc_attach() will create a second device instance
1575 * for us.
1576 */
1577 device_set_descf(dev,
1578 "Marvell Technology Group Ltd. %s Id 0x%02x Rev 0x%02x",
1579 model_name[sc->msk_hw_id - CHIP_ID_YUKON_XL], sc->msk_hw_id,
1580 sc->msk_hw_rev);
1581
1582 return (BUS_PROBE_DEFAULT);
1583 }
1584
1585 static int
msk_attach(device_t dev)1586 msk_attach(device_t dev)
1587 {
1588 struct msk_softc *sc;
1589 struct msk_if_softc *sc_if;
1590 if_t ifp;
1591 struct msk_mii_data *mmd;
1592 int i, port, error;
1593 uint8_t eaddr[6];
1594
1595 if (dev == NULL)
1596 return (EINVAL);
1597
1598 error = 0;
1599 sc_if = device_get_softc(dev);
1600 sc = device_get_softc(device_get_parent(dev));
1601 mmd = device_get_ivars(dev);
1602 port = mmd->port;
1603
1604 sc_if->msk_if_dev = dev;
1605 sc_if->msk_port = port;
1606 sc_if->msk_softc = sc;
1607 sc_if->msk_flags = sc->msk_pflags;
1608 sc->msk_if[port] = sc_if;
1609 /* Setup Tx/Rx queue register offsets. */
1610 if (port == MSK_PORT_A) {
1611 sc_if->msk_txq = Q_XA1;
1612 sc_if->msk_txsq = Q_XS1;
1613 sc_if->msk_rxq = Q_R1;
1614 } else {
1615 sc_if->msk_txq = Q_XA2;
1616 sc_if->msk_txsq = Q_XS2;
1617 sc_if->msk_rxq = Q_R2;
1618 }
1619
1620 callout_init_mtx(&sc_if->msk_tick_ch, &sc_if->msk_softc->msk_mtx, 0);
1621 msk_sysctl_node(sc_if);
1622
1623 if ((error = msk_txrx_dma_alloc(sc_if)) != 0)
1624 goto fail;
1625 msk_rx_dma_jalloc(sc_if);
1626
1627 ifp = sc_if->msk_ifp = if_alloc(IFT_ETHER);
1628 if_setsoftc(ifp, sc_if);
1629 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1630 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
1631 if_setcapabilities(ifp, IFCAP_TXCSUM | IFCAP_TSO4);
1632 /*
1633 * Enable Rx checksum offloading if controller supports
1634 * new descriptor formant and controller is not Yukon XL.
1635 */
1636 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 &&
1637 sc->msk_hw_id != CHIP_ID_YUKON_XL)
1638 if_setcapabilitiesbit(ifp, IFCAP_RXCSUM, 0);
1639 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0 &&
1640 (sc_if->msk_flags & MSK_FLAG_NORX_CSUM) == 0)
1641 if_setcapabilitiesbit(ifp, IFCAP_RXCSUM, 0);
1642 if_sethwassist(ifp, MSK_CSUM_FEATURES | CSUM_TSO);
1643 if_setcapenable(ifp, if_getcapabilities(ifp));
1644 if_setioctlfn(ifp, msk_ioctl);
1645 if_setstartfn(ifp, msk_start);
1646 if_setinitfn(ifp, msk_init);
1647 if_setsendqlen(ifp, MSK_TX_RING_CNT - 1);
1648 if_setsendqready(ifp);
1649 /*
1650 * Get station address for this interface. Note that
1651 * dual port cards actually come with three station
1652 * addresses: one for each port, plus an extra. The
1653 * extra one is used by the SysKonnect driver software
1654 * as a 'virtual' station address for when both ports
1655 * are operating in failover mode. Currently we don't
1656 * use this extra address.
1657 */
1658 MSK_IF_LOCK(sc_if);
1659 for (i = 0; i < ETHER_ADDR_LEN; i++)
1660 eaddr[i] = CSR_READ_1(sc, B2_MAC_1 + (port * 8) + i);
1661
1662 /*
1663 * Call MI attach routine. Can't hold locks when calling into ether_*.
1664 */
1665 MSK_IF_UNLOCK(sc_if);
1666 ether_ifattach(ifp, eaddr);
1667 MSK_IF_LOCK(sc_if);
1668
1669 /* VLAN capability setup */
1670 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU, 0);
1671 if ((sc_if->msk_flags & MSK_FLAG_NOHWVLAN) == 0) {
1672 /*
1673 * Due to Tx checksum offload hardware bugs, msk(4) manually
1674 * computes checksum for short frames. For VLAN tagged frames
1675 * this workaround does not work so disable checksum offload
1676 * for VLAN interface.
1677 */
1678 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWTSO, 0);
1679 /*
1680 * Enable Rx checksum offloading for VLAN tagged frames
1681 * if controller support new descriptor format.
1682 */
1683 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0 &&
1684 (sc_if->msk_flags & MSK_FLAG_NORX_CSUM) == 0)
1685 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWCSUM, 0);
1686 }
1687 if_setcapenable(ifp, if_getcapabilities(ifp));
1688 /*
1689 * Disable RX checksum offloading on controllers that don't use
1690 * new descriptor format but give chance to enable it.
1691 */
1692 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0)
1693 if_setcapenablebit(ifp, 0, IFCAP_RXCSUM);
1694
1695 /*
1696 * Tell the upper layer(s) we support long frames.
1697 * Must appear after the call to ether_ifattach() because
1698 * ether_ifattach() sets ifi_hdrlen to the default value.
1699 */
1700 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
1701
1702 /*
1703 * Do miibus setup.
1704 */
1705 MSK_IF_UNLOCK(sc_if);
1706 error = mii_attach(dev, &sc_if->msk_miibus, ifp, msk_mediachange,
1707 msk_mediastatus, BMSR_DEFCAPMASK, PHY_ADDR_MARV, MII_OFFSET_ANY,
1708 mmd->mii_flags);
1709 if (error != 0) {
1710 device_printf(sc_if->msk_if_dev, "attaching PHYs failed\n");
1711 ether_ifdetach(ifp);
1712 error = ENXIO;
1713 goto fail;
1714 }
1715
1716 fail:
1717 if (error != 0) {
1718 /* Access should be ok even though lock has been dropped */
1719 sc->msk_if[port] = NULL;
1720 msk_detach(dev);
1721 }
1722
1723 return (error);
1724 }
1725
1726 /*
1727 * Attach the interface. Allocate softc structures, do ifmedia
1728 * setup and ethernet/BPF attach.
1729 */
1730 static int
mskc_attach(device_t dev)1731 mskc_attach(device_t dev)
1732 {
1733 struct msk_softc *sc;
1734 struct msk_mii_data *mmd;
1735 int error, msic, msir, reg;
1736
1737 sc = device_get_softc(dev);
1738 sc->msk_dev = dev;
1739 mtx_init(&sc->msk_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1740 MTX_DEF);
1741
1742 /*
1743 * Map control/status registers.
1744 */
1745 pci_enable_busmaster(dev);
1746
1747 /* Allocate I/O resource */
1748 #ifdef MSK_USEIOSPACE
1749 sc->msk_res_spec = msk_res_spec_io;
1750 #else
1751 sc->msk_res_spec = msk_res_spec_mem;
1752 #endif
1753 sc->msk_irq_spec = msk_irq_spec_legacy;
1754 error = bus_alloc_resources(dev, sc->msk_res_spec, sc->msk_res);
1755 if (error) {
1756 if (sc->msk_res_spec == msk_res_spec_mem)
1757 sc->msk_res_spec = msk_res_spec_io;
1758 else
1759 sc->msk_res_spec = msk_res_spec_mem;
1760 error = bus_alloc_resources(dev, sc->msk_res_spec, sc->msk_res);
1761 if (error) {
1762 device_printf(dev, "couldn't allocate %s resources\n",
1763 sc->msk_res_spec == msk_res_spec_mem ? "memory" :
1764 "I/O");
1765 mtx_destroy(&sc->msk_mtx);
1766 return (ENXIO);
1767 }
1768 }
1769
1770 /* Enable all clocks before accessing any registers. */
1771 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_3, 0);
1772
1773 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR);
1774 sc->msk_hw_id = CSR_READ_1(sc, B2_CHIP_ID);
1775 sc->msk_hw_rev = (CSR_READ_1(sc, B2_MAC_CFG) >> 4) & 0x0f;
1776 /* Bail out if chip is not recognized. */
1777 if (sc->msk_hw_id < CHIP_ID_YUKON_XL ||
1778 sc->msk_hw_id > CHIP_ID_YUKON_OPT ||
1779 sc->msk_hw_id == CHIP_ID_YUKON_UNKNOWN) {
1780 device_printf(dev, "unknown device: id=0x%02x, rev=0x%02x\n",
1781 sc->msk_hw_id, sc->msk_hw_rev);
1782 mtx_destroy(&sc->msk_mtx);
1783 return (ENXIO);
1784 }
1785
1786 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
1787 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
1788 OID_AUTO, "process_limit",
1789 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
1790 &sc->msk_process_limit, 0, sysctl_hw_msk_proc_limit, "I",
1791 "max number of Rx events to process");
1792
1793 sc->msk_process_limit = MSK_PROC_DEFAULT;
1794 error = resource_int_value(device_get_name(dev), device_get_unit(dev),
1795 "process_limit", &sc->msk_process_limit);
1796 if (error == 0) {
1797 if (sc->msk_process_limit < MSK_PROC_MIN ||
1798 sc->msk_process_limit > MSK_PROC_MAX) {
1799 device_printf(dev, "process_limit value out of range; "
1800 "using default: %d\n", MSK_PROC_DEFAULT);
1801 sc->msk_process_limit = MSK_PROC_DEFAULT;
1802 }
1803 }
1804
1805 sc->msk_int_holdoff = MSK_INT_HOLDOFF_DEFAULT;
1806 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
1807 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
1808 "int_holdoff", CTLFLAG_RW, &sc->msk_int_holdoff, 0,
1809 "Maximum number of time to delay interrupts");
1810 resource_int_value(device_get_name(dev), device_get_unit(dev),
1811 "int_holdoff", &sc->msk_int_holdoff);
1812
1813 sc->msk_pmd = CSR_READ_1(sc, B2_PMD_TYP);
1814 /* Check number of MACs. */
1815 sc->msk_num_port = 1;
1816 if ((CSR_READ_1(sc, B2_Y2_HW_RES) & CFG_DUAL_MAC_MSK) ==
1817 CFG_DUAL_MAC_MSK) {
1818 if (!(CSR_READ_1(sc, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
1819 sc->msk_num_port++;
1820 }
1821
1822 /* Check bus type. */
1823 if (pci_find_cap(sc->msk_dev, PCIY_EXPRESS, ®) == 0) {
1824 sc->msk_bustype = MSK_PEX_BUS;
1825 sc->msk_expcap = reg;
1826 } else if (pci_find_cap(sc->msk_dev, PCIY_PCIX, ®) == 0) {
1827 sc->msk_bustype = MSK_PCIX_BUS;
1828 sc->msk_pcixcap = reg;
1829 } else
1830 sc->msk_bustype = MSK_PCI_BUS;
1831
1832 switch (sc->msk_hw_id) {
1833 case CHIP_ID_YUKON_EC:
1834 sc->msk_clock = 125; /* 125 MHz */
1835 sc->msk_pflags |= MSK_FLAG_JUMBO;
1836 break;
1837 case CHIP_ID_YUKON_EC_U:
1838 sc->msk_clock = 125; /* 125 MHz */
1839 sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_JUMBO_NOCSUM;
1840 break;
1841 case CHIP_ID_YUKON_EX:
1842 sc->msk_clock = 125; /* 125 MHz */
1843 sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_DESCV2 |
1844 MSK_FLAG_AUTOTX_CSUM;
1845 /*
1846 * Yukon Extreme seems to have silicon bug for
1847 * automatic Tx checksum calculation capability.
1848 */
1849 if (sc->msk_hw_rev == CHIP_REV_YU_EX_B0)
1850 sc->msk_pflags &= ~MSK_FLAG_AUTOTX_CSUM;
1851 /*
1852 * Yukon Extreme A0 could not use store-and-forward
1853 * for jumbo frames, so disable Tx checksum
1854 * offloading for jumbo frames.
1855 */
1856 if (sc->msk_hw_rev == CHIP_REV_YU_EX_A0)
1857 sc->msk_pflags |= MSK_FLAG_JUMBO_NOCSUM;
1858 break;
1859 case CHIP_ID_YUKON_FE:
1860 sc->msk_clock = 100; /* 100 MHz */
1861 sc->msk_pflags |= MSK_FLAG_FASTETHER;
1862 break;
1863 case CHIP_ID_YUKON_FE_P:
1864 sc->msk_clock = 50; /* 50 MHz */
1865 sc->msk_pflags |= MSK_FLAG_FASTETHER | MSK_FLAG_DESCV2 |
1866 MSK_FLAG_AUTOTX_CSUM;
1867 if (sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) {
1868 /*
1869 * XXX
1870 * FE+ A0 has status LE writeback bug so msk(4)
1871 * does not rely on status word of received frame
1872 * in msk_rxeof() which in turn disables all
1873 * hardware assistance bits reported by the status
1874 * word as well as validity of the received frame.
1875 * Just pass received frames to upper stack with
1876 * minimal test and let upper stack handle them.
1877 */
1878 sc->msk_pflags |= MSK_FLAG_NOHWVLAN |
1879 MSK_FLAG_NORXCHK | MSK_FLAG_NORX_CSUM;
1880 }
1881 break;
1882 case CHIP_ID_YUKON_XL:
1883 sc->msk_clock = 156; /* 156 MHz */
1884 sc->msk_pflags |= MSK_FLAG_JUMBO;
1885 break;
1886 case CHIP_ID_YUKON_SUPR:
1887 sc->msk_clock = 125; /* 125 MHz */
1888 sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_DESCV2 |
1889 MSK_FLAG_AUTOTX_CSUM;
1890 break;
1891 case CHIP_ID_YUKON_UL_2:
1892 sc->msk_clock = 125; /* 125 MHz */
1893 sc->msk_pflags |= MSK_FLAG_JUMBO;
1894 break;
1895 case CHIP_ID_YUKON_OPT:
1896 sc->msk_clock = 125; /* 125 MHz */
1897 sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_DESCV2;
1898 break;
1899 default:
1900 sc->msk_clock = 156; /* 156 MHz */
1901 break;
1902 }
1903
1904 /* Allocate IRQ resources. */
1905 msic = pci_msi_count(dev);
1906 if (bootverbose)
1907 device_printf(dev, "MSI count : %d\n", msic);
1908 if (legacy_intr != 0)
1909 msi_disable = 1;
1910 if (msi_disable == 0 && msic > 0) {
1911 msir = 1;
1912 if (pci_alloc_msi(dev, &msir) == 0) {
1913 if (msir == 1) {
1914 sc->msk_pflags |= MSK_FLAG_MSI;
1915 sc->msk_irq_spec = msk_irq_spec_msi;
1916 } else
1917 pci_release_msi(dev);
1918 }
1919 }
1920
1921 error = bus_alloc_resources(dev, sc->msk_irq_spec, sc->msk_irq);
1922 if (error) {
1923 device_printf(dev, "couldn't allocate IRQ resources\n");
1924 goto fail;
1925 }
1926
1927 if ((error = msk_status_dma_alloc(sc)) != 0)
1928 goto fail;
1929
1930 /* Set base interrupt mask. */
1931 sc->msk_intrmask = Y2_IS_HW_ERR | Y2_IS_STAT_BMU;
1932 sc->msk_intrhwemask = Y2_IS_TIST_OV | Y2_IS_MST_ERR |
1933 Y2_IS_IRQ_STAT | Y2_IS_PCI_EXP | Y2_IS_PCI_NEXP;
1934
1935 /* Reset the adapter. */
1936 mskc_reset(sc);
1937
1938 if ((error = mskc_setup_rambuffer(sc)) != 0)
1939 goto fail;
1940
1941 sc->msk_devs[MSK_PORT_A] = device_add_child(dev, "msk", DEVICE_UNIT_ANY);
1942 if (sc->msk_devs[MSK_PORT_A] == NULL) {
1943 device_printf(dev, "failed to add child for PORT_A\n");
1944 error = ENXIO;
1945 goto fail;
1946 }
1947 mmd = malloc(sizeof(struct msk_mii_data), M_DEVBUF, M_WAITOK | M_ZERO);
1948 mmd->port = MSK_PORT_A;
1949 mmd->pmd = sc->msk_pmd;
1950 mmd->mii_flags |= MIIF_DOPAUSE;
1951 if (sc->msk_pmd == 'L' || sc->msk_pmd == 'S')
1952 mmd->mii_flags |= MIIF_HAVEFIBER;
1953 if (sc->msk_pmd == 'P')
1954 mmd->mii_flags |= MIIF_HAVEFIBER | MIIF_MACPRIV0;
1955 device_set_ivars(sc->msk_devs[MSK_PORT_A], mmd);
1956
1957 if (sc->msk_num_port > 1) {
1958 sc->msk_devs[MSK_PORT_B] = device_add_child(dev, "msk", DEVICE_UNIT_ANY);
1959 if (sc->msk_devs[MSK_PORT_B] == NULL) {
1960 device_printf(dev, "failed to add child for PORT_B\n");
1961 error = ENXIO;
1962 goto fail;
1963 }
1964 mmd = malloc(sizeof(struct msk_mii_data), M_DEVBUF, M_WAITOK |
1965 M_ZERO);
1966 mmd->port = MSK_PORT_B;
1967 mmd->pmd = sc->msk_pmd;
1968 if (sc->msk_pmd == 'L' || sc->msk_pmd == 'S')
1969 mmd->mii_flags |= MIIF_HAVEFIBER;
1970 if (sc->msk_pmd == 'P')
1971 mmd->mii_flags |= MIIF_HAVEFIBER | MIIF_MACPRIV0;
1972 device_set_ivars(sc->msk_devs[MSK_PORT_B], mmd);
1973 }
1974
1975 bus_attach_children(dev);
1976
1977 /* Hook interrupt last to avoid having to lock softc. */
1978 error = bus_setup_intr(dev, sc->msk_irq[0], INTR_TYPE_NET |
1979 INTR_MPSAFE, NULL, msk_intr, sc, &sc->msk_intrhand);
1980 if (error != 0) {
1981 device_printf(dev, "couldn't set up interrupt handler\n");
1982 goto fail;
1983 }
1984 fail:
1985 if (error != 0)
1986 mskc_detach(dev);
1987
1988 return (error);
1989 }
1990
1991 /*
1992 * Shutdown hardware and free up resources. This can be called any
1993 * time after the mutex has been initialized. It is called in both
1994 * the error case in attach and the normal detach case so it needs
1995 * to be careful about only freeing resources that have actually been
1996 * allocated.
1997 */
1998 static int
msk_detach(device_t dev)1999 msk_detach(device_t dev)
2000 {
2001 struct msk_softc *sc;
2002 struct msk_if_softc *sc_if;
2003 if_t ifp;
2004
2005 sc_if = device_get_softc(dev);
2006 KASSERT(mtx_initialized(&sc_if->msk_softc->msk_mtx),
2007 ("msk mutex not initialized in msk_detach"));
2008 MSK_IF_LOCK(sc_if);
2009
2010 ifp = sc_if->msk_ifp;
2011 if (device_is_attached(dev)) {
2012 /* XXX */
2013 sc_if->msk_flags |= MSK_FLAG_DETACH;
2014 msk_stop(sc_if);
2015 /* Can't hold locks while calling detach. */
2016 MSK_IF_UNLOCK(sc_if);
2017 callout_drain(&sc_if->msk_tick_ch);
2018 if (ifp)
2019 ether_ifdetach(ifp);
2020 MSK_IF_LOCK(sc_if);
2021 }
2022
2023 /*
2024 * We're generally called from mskc_detach() which is using
2025 * device_delete_child() to get to here. It's already trashed
2026 * miibus for us, so don't do it here or we'll panic.
2027 *
2028 * if (sc_if->msk_miibus != NULL) {
2029 * device_delete_child(dev, sc_if->msk_miibus);
2030 * sc_if->msk_miibus = NULL;
2031 * }
2032 */
2033
2034 msk_rx_dma_jfree(sc_if);
2035 msk_txrx_dma_free(sc_if);
2036 bus_generic_detach(dev);
2037
2038 sc = sc_if->msk_softc;
2039 sc->msk_if[sc_if->msk_port] = NULL;
2040 MSK_IF_UNLOCK(sc_if);
2041 if (ifp)
2042 if_free(ifp);
2043
2044 return (0);
2045 }
2046
2047 static void
mskc_child_deleted(device_t dev,device_t child)2048 mskc_child_deleted(device_t dev, device_t child)
2049 {
2050 free(device_get_ivars(child), M_DEVBUF);
2051 }
2052
2053 static int
mskc_detach(device_t dev)2054 mskc_detach(device_t dev)
2055 {
2056 struct msk_softc *sc;
2057
2058 sc = device_get_softc(dev);
2059 KASSERT(mtx_initialized(&sc->msk_mtx), ("msk mutex not initialized"));
2060
2061 if (device_is_alive(dev)) {
2062 if (sc->msk_devs[MSK_PORT_A] != NULL) {
2063 device_delete_child(dev, sc->msk_devs[MSK_PORT_A]);
2064 }
2065 if (sc->msk_devs[MSK_PORT_B] != NULL) {
2066 device_delete_child(dev, sc->msk_devs[MSK_PORT_B]);
2067 }
2068 bus_generic_detach(dev);
2069 }
2070
2071 /* Disable all interrupts. */
2072 CSR_WRITE_4(sc, B0_IMSK, 0);
2073 CSR_READ_4(sc, B0_IMSK);
2074 CSR_WRITE_4(sc, B0_HWE_IMSK, 0);
2075 CSR_READ_4(sc, B0_HWE_IMSK);
2076
2077 /* LED Off. */
2078 CSR_WRITE_2(sc, B0_CTST, Y2_LED_STAT_OFF);
2079
2080 /* Put hardware reset. */
2081 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET);
2082
2083 msk_status_dma_free(sc);
2084
2085 if (sc->msk_intrhand) {
2086 bus_teardown_intr(dev, sc->msk_irq[0], sc->msk_intrhand);
2087 sc->msk_intrhand = NULL;
2088 }
2089 bus_release_resources(dev, sc->msk_irq_spec, sc->msk_irq);
2090 if ((sc->msk_pflags & MSK_FLAG_MSI) != 0)
2091 pci_release_msi(dev);
2092 bus_release_resources(dev, sc->msk_res_spec, sc->msk_res);
2093 mtx_destroy(&sc->msk_mtx);
2094
2095 return (0);
2096 }
2097
2098 static bus_dma_tag_t
mskc_get_dma_tag(device_t bus,device_t child __unused)2099 mskc_get_dma_tag(device_t bus, device_t child __unused)
2100 {
2101
2102 return (bus_get_dma_tag(bus));
2103 }
2104
2105 struct msk_dmamap_arg {
2106 bus_addr_t msk_busaddr;
2107 };
2108
2109 static void
msk_dmamap_cb(void * arg,bus_dma_segment_t * segs,int nseg,int error)2110 msk_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
2111 {
2112 struct msk_dmamap_arg *ctx;
2113
2114 if (error != 0)
2115 return;
2116 ctx = arg;
2117 ctx->msk_busaddr = segs[0].ds_addr;
2118 }
2119
2120 /* Create status DMA region. */
2121 static int
msk_status_dma_alloc(struct msk_softc * sc)2122 msk_status_dma_alloc(struct msk_softc *sc)
2123 {
2124 struct msk_dmamap_arg ctx;
2125 bus_size_t stat_sz;
2126 int count, error;
2127
2128 /*
2129 * It seems controller requires number of status LE entries
2130 * is power of 2 and the maximum number of status LE entries
2131 * is 4096. For dual-port controllers, the number of status
2132 * LE entries should be large enough to hold both port's
2133 * status updates.
2134 */
2135 count = 3 * MSK_RX_RING_CNT + MSK_TX_RING_CNT;
2136 count = imin(4096, roundup2(count, 1024));
2137 sc->msk_stat_count = count;
2138 stat_sz = count * sizeof(struct msk_stat_desc);
2139 error = bus_dma_tag_create(
2140 bus_get_dma_tag(sc->msk_dev), /* parent */
2141 MSK_STAT_ALIGN, 0, /* alignment, boundary */
2142 BUS_SPACE_MAXADDR, /* lowaddr */
2143 BUS_SPACE_MAXADDR, /* highaddr */
2144 NULL, NULL, /* filter, filterarg */
2145 stat_sz, /* maxsize */
2146 1, /* nsegments */
2147 stat_sz, /* maxsegsize */
2148 0, /* flags */
2149 NULL, NULL, /* lockfunc, lockarg */
2150 &sc->msk_stat_tag);
2151 if (error != 0) {
2152 device_printf(sc->msk_dev,
2153 "failed to create status DMA tag\n");
2154 return (error);
2155 }
2156
2157 /* Allocate DMA'able memory and load the DMA map for status ring. */
2158 error = bus_dmamem_alloc(sc->msk_stat_tag,
2159 (void **)&sc->msk_stat_ring, BUS_DMA_WAITOK | BUS_DMA_COHERENT |
2160 BUS_DMA_ZERO, &sc->msk_stat_map);
2161 if (error != 0) {
2162 device_printf(sc->msk_dev,
2163 "failed to allocate DMA'able memory for status ring\n");
2164 return (error);
2165 }
2166
2167 ctx.msk_busaddr = 0;
2168 error = bus_dmamap_load(sc->msk_stat_tag, sc->msk_stat_map,
2169 sc->msk_stat_ring, stat_sz, msk_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
2170 if (error != 0) {
2171 device_printf(sc->msk_dev,
2172 "failed to load DMA'able memory for status ring\n");
2173 return (error);
2174 }
2175 sc->msk_stat_ring_paddr = ctx.msk_busaddr;
2176
2177 return (0);
2178 }
2179
2180 static void
msk_status_dma_free(struct msk_softc * sc)2181 msk_status_dma_free(struct msk_softc *sc)
2182 {
2183
2184 /* Destroy status block. */
2185 if (sc->msk_stat_tag) {
2186 if (sc->msk_stat_ring_paddr) {
2187 bus_dmamap_unload(sc->msk_stat_tag, sc->msk_stat_map);
2188 sc->msk_stat_ring_paddr = 0;
2189 }
2190 if (sc->msk_stat_ring) {
2191 bus_dmamem_free(sc->msk_stat_tag,
2192 sc->msk_stat_ring, sc->msk_stat_map);
2193 sc->msk_stat_ring = NULL;
2194 }
2195 bus_dma_tag_destroy(sc->msk_stat_tag);
2196 sc->msk_stat_tag = NULL;
2197 }
2198 }
2199
2200 static int
msk_txrx_dma_alloc(struct msk_if_softc * sc_if)2201 msk_txrx_dma_alloc(struct msk_if_softc *sc_if)
2202 {
2203 struct msk_dmamap_arg ctx;
2204 struct msk_txdesc *txd;
2205 struct msk_rxdesc *rxd;
2206 bus_size_t rxalign;
2207 int error, i;
2208
2209 /* Create parent DMA tag. */
2210 error = bus_dma_tag_create(
2211 bus_get_dma_tag(sc_if->msk_if_dev), /* parent */
2212 1, 0, /* alignment, boundary */
2213 BUS_SPACE_MAXADDR, /* lowaddr */
2214 BUS_SPACE_MAXADDR, /* highaddr */
2215 NULL, NULL, /* filter, filterarg */
2216 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
2217 0, /* nsegments */
2218 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
2219 0, /* flags */
2220 NULL, NULL, /* lockfunc, lockarg */
2221 &sc_if->msk_cdata.msk_parent_tag);
2222 if (error != 0) {
2223 device_printf(sc_if->msk_if_dev,
2224 "failed to create parent DMA tag\n");
2225 goto fail;
2226 }
2227 /* Create tag for Tx ring. */
2228 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */
2229 MSK_RING_ALIGN, 0, /* alignment, boundary */
2230 BUS_SPACE_MAXADDR, /* lowaddr */
2231 BUS_SPACE_MAXADDR, /* highaddr */
2232 NULL, NULL, /* filter, filterarg */
2233 MSK_TX_RING_SZ, /* maxsize */
2234 1, /* nsegments */
2235 MSK_TX_RING_SZ, /* maxsegsize */
2236 0, /* flags */
2237 NULL, NULL, /* lockfunc, lockarg */
2238 &sc_if->msk_cdata.msk_tx_ring_tag);
2239 if (error != 0) {
2240 device_printf(sc_if->msk_if_dev,
2241 "failed to create Tx ring DMA tag\n");
2242 goto fail;
2243 }
2244
2245 /* Create tag for Rx ring. */
2246 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */
2247 MSK_RING_ALIGN, 0, /* alignment, boundary */
2248 BUS_SPACE_MAXADDR, /* lowaddr */
2249 BUS_SPACE_MAXADDR, /* highaddr */
2250 NULL, NULL, /* filter, filterarg */
2251 MSK_RX_RING_SZ, /* maxsize */
2252 1, /* nsegments */
2253 MSK_RX_RING_SZ, /* maxsegsize */
2254 0, /* flags */
2255 NULL, NULL, /* lockfunc, lockarg */
2256 &sc_if->msk_cdata.msk_rx_ring_tag);
2257 if (error != 0) {
2258 device_printf(sc_if->msk_if_dev,
2259 "failed to create Rx ring DMA tag\n");
2260 goto fail;
2261 }
2262
2263 /* Create tag for Tx buffers. */
2264 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */
2265 1, 0, /* alignment, boundary */
2266 BUS_SPACE_MAXADDR, /* lowaddr */
2267 BUS_SPACE_MAXADDR, /* highaddr */
2268 NULL, NULL, /* filter, filterarg */
2269 MSK_TSO_MAXSIZE, /* maxsize */
2270 MSK_MAXTXSEGS, /* nsegments */
2271 MSK_TSO_MAXSGSIZE, /* maxsegsize */
2272 0, /* flags */
2273 NULL, NULL, /* lockfunc, lockarg */
2274 &sc_if->msk_cdata.msk_tx_tag);
2275 if (error != 0) {
2276 device_printf(sc_if->msk_if_dev,
2277 "failed to create Tx DMA tag\n");
2278 goto fail;
2279 }
2280
2281 rxalign = 1;
2282 /*
2283 * Workaround hardware hang which seems to happen when Rx buffer
2284 * is not aligned on multiple of FIFO word(8 bytes).
2285 */
2286 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0)
2287 rxalign = MSK_RX_BUF_ALIGN;
2288 /* Create tag for Rx buffers. */
2289 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */
2290 rxalign, 0, /* alignment, boundary */
2291 BUS_SPACE_MAXADDR, /* lowaddr */
2292 BUS_SPACE_MAXADDR, /* highaddr */
2293 NULL, NULL, /* filter, filterarg */
2294 MCLBYTES, /* maxsize */
2295 1, /* nsegments */
2296 MCLBYTES, /* maxsegsize */
2297 0, /* flags */
2298 NULL, NULL, /* lockfunc, lockarg */
2299 &sc_if->msk_cdata.msk_rx_tag);
2300 if (error != 0) {
2301 device_printf(sc_if->msk_if_dev,
2302 "failed to create Rx DMA tag\n");
2303 goto fail;
2304 }
2305
2306 /* Allocate DMA'able memory and load the DMA map for Tx ring. */
2307 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_tx_ring_tag,
2308 (void **)&sc_if->msk_rdata.msk_tx_ring, BUS_DMA_WAITOK |
2309 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->msk_cdata.msk_tx_ring_map);
2310 if (error != 0) {
2311 device_printf(sc_if->msk_if_dev,
2312 "failed to allocate DMA'able memory for Tx ring\n");
2313 goto fail;
2314 }
2315
2316 ctx.msk_busaddr = 0;
2317 error = bus_dmamap_load(sc_if->msk_cdata.msk_tx_ring_tag,
2318 sc_if->msk_cdata.msk_tx_ring_map, sc_if->msk_rdata.msk_tx_ring,
2319 MSK_TX_RING_SZ, msk_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
2320 if (error != 0) {
2321 device_printf(sc_if->msk_if_dev,
2322 "failed to load DMA'able memory for Tx ring\n");
2323 goto fail;
2324 }
2325 sc_if->msk_rdata.msk_tx_ring_paddr = ctx.msk_busaddr;
2326
2327 /* Allocate DMA'able memory and load the DMA map for Rx ring. */
2328 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_rx_ring_tag,
2329 (void **)&sc_if->msk_rdata.msk_rx_ring, BUS_DMA_WAITOK |
2330 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->msk_cdata.msk_rx_ring_map);
2331 if (error != 0) {
2332 device_printf(sc_if->msk_if_dev,
2333 "failed to allocate DMA'able memory for Rx ring\n");
2334 goto fail;
2335 }
2336
2337 ctx.msk_busaddr = 0;
2338 error = bus_dmamap_load(sc_if->msk_cdata.msk_rx_ring_tag,
2339 sc_if->msk_cdata.msk_rx_ring_map, sc_if->msk_rdata.msk_rx_ring,
2340 MSK_RX_RING_SZ, msk_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
2341 if (error != 0) {
2342 device_printf(sc_if->msk_if_dev,
2343 "failed to load DMA'able memory for Rx ring\n");
2344 goto fail;
2345 }
2346 sc_if->msk_rdata.msk_rx_ring_paddr = ctx.msk_busaddr;
2347
2348 /* Create DMA maps for Tx buffers. */
2349 for (i = 0; i < MSK_TX_RING_CNT; i++) {
2350 txd = &sc_if->msk_cdata.msk_txdesc[i];
2351 txd->tx_m = NULL;
2352 txd->tx_dmamap = NULL;
2353 error = bus_dmamap_create(sc_if->msk_cdata.msk_tx_tag, 0,
2354 &txd->tx_dmamap);
2355 if (error != 0) {
2356 device_printf(sc_if->msk_if_dev,
2357 "failed to create Tx dmamap\n");
2358 goto fail;
2359 }
2360 }
2361 /* Create DMA maps for Rx buffers. */
2362 if ((error = bus_dmamap_create(sc_if->msk_cdata.msk_rx_tag, 0,
2363 &sc_if->msk_cdata.msk_rx_sparemap)) != 0) {
2364 device_printf(sc_if->msk_if_dev,
2365 "failed to create spare Rx dmamap\n");
2366 goto fail;
2367 }
2368 for (i = 0; i < MSK_RX_RING_CNT; i++) {
2369 rxd = &sc_if->msk_cdata.msk_rxdesc[i];
2370 rxd->rx_m = NULL;
2371 rxd->rx_dmamap = NULL;
2372 error = bus_dmamap_create(sc_if->msk_cdata.msk_rx_tag, 0,
2373 &rxd->rx_dmamap);
2374 if (error != 0) {
2375 device_printf(sc_if->msk_if_dev,
2376 "failed to create Rx dmamap\n");
2377 goto fail;
2378 }
2379 }
2380
2381 fail:
2382 return (error);
2383 }
2384
2385 static int
msk_rx_dma_jalloc(struct msk_if_softc * sc_if)2386 msk_rx_dma_jalloc(struct msk_if_softc *sc_if)
2387 {
2388 struct msk_dmamap_arg ctx;
2389 struct msk_rxdesc *jrxd;
2390 bus_size_t rxalign;
2391 int error, i;
2392
2393 if (jumbo_disable != 0 || (sc_if->msk_flags & MSK_FLAG_JUMBO) == 0) {
2394 sc_if->msk_flags &= ~MSK_FLAG_JUMBO;
2395 device_printf(sc_if->msk_if_dev,
2396 "disabling jumbo frame support\n");
2397 return (0);
2398 }
2399 /* Create tag for jumbo Rx ring. */
2400 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */
2401 MSK_RING_ALIGN, 0, /* alignment, boundary */
2402 BUS_SPACE_MAXADDR, /* lowaddr */
2403 BUS_SPACE_MAXADDR, /* highaddr */
2404 NULL, NULL, /* filter, filterarg */
2405 MSK_JUMBO_RX_RING_SZ, /* maxsize */
2406 1, /* nsegments */
2407 MSK_JUMBO_RX_RING_SZ, /* maxsegsize */
2408 0, /* flags */
2409 NULL, NULL, /* lockfunc, lockarg */
2410 &sc_if->msk_cdata.msk_jumbo_rx_ring_tag);
2411 if (error != 0) {
2412 device_printf(sc_if->msk_if_dev,
2413 "failed to create jumbo Rx ring DMA tag\n");
2414 goto jumbo_fail;
2415 }
2416
2417 rxalign = 1;
2418 /*
2419 * Workaround hardware hang which seems to happen when Rx buffer
2420 * is not aligned on multiple of FIFO word(8 bytes).
2421 */
2422 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0)
2423 rxalign = MSK_RX_BUF_ALIGN;
2424 /* Create tag for jumbo Rx buffers. */
2425 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */
2426 rxalign, 0, /* alignment, boundary */
2427 BUS_SPACE_MAXADDR, /* lowaddr */
2428 BUS_SPACE_MAXADDR, /* highaddr */
2429 NULL, NULL, /* filter, filterarg */
2430 MJUM9BYTES, /* maxsize */
2431 1, /* nsegments */
2432 MJUM9BYTES, /* maxsegsize */
2433 0, /* flags */
2434 NULL, NULL, /* lockfunc, lockarg */
2435 &sc_if->msk_cdata.msk_jumbo_rx_tag);
2436 if (error != 0) {
2437 device_printf(sc_if->msk_if_dev,
2438 "failed to create jumbo Rx DMA tag\n");
2439 goto jumbo_fail;
2440 }
2441
2442 /* Allocate DMA'able memory and load the DMA map for jumbo Rx ring. */
2443 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_jumbo_rx_ring_tag,
2444 (void **)&sc_if->msk_rdata.msk_jumbo_rx_ring,
2445 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO,
2446 &sc_if->msk_cdata.msk_jumbo_rx_ring_map);
2447 if (error != 0) {
2448 device_printf(sc_if->msk_if_dev,
2449 "failed to allocate DMA'able memory for jumbo Rx ring\n");
2450 goto jumbo_fail;
2451 }
2452
2453 ctx.msk_busaddr = 0;
2454 error = bus_dmamap_load(sc_if->msk_cdata.msk_jumbo_rx_ring_tag,
2455 sc_if->msk_cdata.msk_jumbo_rx_ring_map,
2456 sc_if->msk_rdata.msk_jumbo_rx_ring, MSK_JUMBO_RX_RING_SZ,
2457 msk_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
2458 if (error != 0) {
2459 device_printf(sc_if->msk_if_dev,
2460 "failed to load DMA'able memory for jumbo Rx ring\n");
2461 goto jumbo_fail;
2462 }
2463 sc_if->msk_rdata.msk_jumbo_rx_ring_paddr = ctx.msk_busaddr;
2464
2465 /* Create DMA maps for jumbo Rx buffers. */
2466 if ((error = bus_dmamap_create(sc_if->msk_cdata.msk_jumbo_rx_tag, 0,
2467 &sc_if->msk_cdata.msk_jumbo_rx_sparemap)) != 0) {
2468 device_printf(sc_if->msk_if_dev,
2469 "failed to create spare jumbo Rx dmamap\n");
2470 goto jumbo_fail;
2471 }
2472 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) {
2473 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i];
2474 jrxd->rx_m = NULL;
2475 jrxd->rx_dmamap = NULL;
2476 error = bus_dmamap_create(sc_if->msk_cdata.msk_jumbo_rx_tag, 0,
2477 &jrxd->rx_dmamap);
2478 if (error != 0) {
2479 device_printf(sc_if->msk_if_dev,
2480 "failed to create jumbo Rx dmamap\n");
2481 goto jumbo_fail;
2482 }
2483 }
2484
2485 return (0);
2486
2487 jumbo_fail:
2488 msk_rx_dma_jfree(sc_if);
2489 device_printf(sc_if->msk_if_dev, "disabling jumbo frame support "
2490 "due to resource shortage\n");
2491 sc_if->msk_flags &= ~MSK_FLAG_JUMBO;
2492 return (error);
2493 }
2494
2495 static void
msk_txrx_dma_free(struct msk_if_softc * sc_if)2496 msk_txrx_dma_free(struct msk_if_softc *sc_if)
2497 {
2498 struct msk_txdesc *txd;
2499 struct msk_rxdesc *rxd;
2500 int i;
2501
2502 /* Tx ring. */
2503 if (sc_if->msk_cdata.msk_tx_ring_tag) {
2504 if (sc_if->msk_rdata.msk_tx_ring_paddr)
2505 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_ring_tag,
2506 sc_if->msk_cdata.msk_tx_ring_map);
2507 if (sc_if->msk_rdata.msk_tx_ring)
2508 bus_dmamem_free(sc_if->msk_cdata.msk_tx_ring_tag,
2509 sc_if->msk_rdata.msk_tx_ring,
2510 sc_if->msk_cdata.msk_tx_ring_map);
2511 sc_if->msk_rdata.msk_tx_ring = NULL;
2512 sc_if->msk_rdata.msk_tx_ring_paddr = 0;
2513 bus_dma_tag_destroy(sc_if->msk_cdata.msk_tx_ring_tag);
2514 sc_if->msk_cdata.msk_tx_ring_tag = NULL;
2515 }
2516 /* Rx ring. */
2517 if (sc_if->msk_cdata.msk_rx_ring_tag) {
2518 if (sc_if->msk_rdata.msk_rx_ring_paddr)
2519 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_ring_tag,
2520 sc_if->msk_cdata.msk_rx_ring_map);
2521 if (sc_if->msk_rdata.msk_rx_ring)
2522 bus_dmamem_free(sc_if->msk_cdata.msk_rx_ring_tag,
2523 sc_if->msk_rdata.msk_rx_ring,
2524 sc_if->msk_cdata.msk_rx_ring_map);
2525 sc_if->msk_rdata.msk_rx_ring = NULL;
2526 sc_if->msk_rdata.msk_rx_ring_paddr = 0;
2527 bus_dma_tag_destroy(sc_if->msk_cdata.msk_rx_ring_tag);
2528 sc_if->msk_cdata.msk_rx_ring_tag = NULL;
2529 }
2530 /* Tx buffers. */
2531 if (sc_if->msk_cdata.msk_tx_tag) {
2532 for (i = 0; i < MSK_TX_RING_CNT; i++) {
2533 txd = &sc_if->msk_cdata.msk_txdesc[i];
2534 if (txd->tx_dmamap) {
2535 bus_dmamap_destroy(sc_if->msk_cdata.msk_tx_tag,
2536 txd->tx_dmamap);
2537 txd->tx_dmamap = NULL;
2538 }
2539 }
2540 bus_dma_tag_destroy(sc_if->msk_cdata.msk_tx_tag);
2541 sc_if->msk_cdata.msk_tx_tag = NULL;
2542 }
2543 /* Rx buffers. */
2544 if (sc_if->msk_cdata.msk_rx_tag) {
2545 for (i = 0; i < MSK_RX_RING_CNT; i++) {
2546 rxd = &sc_if->msk_cdata.msk_rxdesc[i];
2547 if (rxd->rx_dmamap) {
2548 bus_dmamap_destroy(sc_if->msk_cdata.msk_rx_tag,
2549 rxd->rx_dmamap);
2550 rxd->rx_dmamap = NULL;
2551 }
2552 }
2553 if (sc_if->msk_cdata.msk_rx_sparemap) {
2554 bus_dmamap_destroy(sc_if->msk_cdata.msk_rx_tag,
2555 sc_if->msk_cdata.msk_rx_sparemap);
2556 sc_if->msk_cdata.msk_rx_sparemap = 0;
2557 }
2558 bus_dma_tag_destroy(sc_if->msk_cdata.msk_rx_tag);
2559 sc_if->msk_cdata.msk_rx_tag = NULL;
2560 }
2561 if (sc_if->msk_cdata.msk_parent_tag) {
2562 bus_dma_tag_destroy(sc_if->msk_cdata.msk_parent_tag);
2563 sc_if->msk_cdata.msk_parent_tag = NULL;
2564 }
2565 }
2566
2567 static void
msk_rx_dma_jfree(struct msk_if_softc * sc_if)2568 msk_rx_dma_jfree(struct msk_if_softc *sc_if)
2569 {
2570 struct msk_rxdesc *jrxd;
2571 int i;
2572
2573 /* Jumbo Rx ring. */
2574 if (sc_if->msk_cdata.msk_jumbo_rx_ring_tag) {
2575 if (sc_if->msk_rdata.msk_jumbo_rx_ring_paddr)
2576 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_ring_tag,
2577 sc_if->msk_cdata.msk_jumbo_rx_ring_map);
2578 if (sc_if->msk_rdata.msk_jumbo_rx_ring)
2579 bus_dmamem_free(sc_if->msk_cdata.msk_jumbo_rx_ring_tag,
2580 sc_if->msk_rdata.msk_jumbo_rx_ring,
2581 sc_if->msk_cdata.msk_jumbo_rx_ring_map);
2582 sc_if->msk_rdata.msk_jumbo_rx_ring = NULL;
2583 sc_if->msk_rdata.msk_jumbo_rx_ring_paddr = 0;
2584 bus_dma_tag_destroy(sc_if->msk_cdata.msk_jumbo_rx_ring_tag);
2585 sc_if->msk_cdata.msk_jumbo_rx_ring_tag = NULL;
2586 }
2587 /* Jumbo Rx buffers. */
2588 if (sc_if->msk_cdata.msk_jumbo_rx_tag) {
2589 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) {
2590 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i];
2591 if (jrxd->rx_dmamap) {
2592 bus_dmamap_destroy(
2593 sc_if->msk_cdata.msk_jumbo_rx_tag,
2594 jrxd->rx_dmamap);
2595 jrxd->rx_dmamap = NULL;
2596 }
2597 }
2598 if (sc_if->msk_cdata.msk_jumbo_rx_sparemap) {
2599 bus_dmamap_destroy(sc_if->msk_cdata.msk_jumbo_rx_tag,
2600 sc_if->msk_cdata.msk_jumbo_rx_sparemap);
2601 sc_if->msk_cdata.msk_jumbo_rx_sparemap = 0;
2602 }
2603 bus_dma_tag_destroy(sc_if->msk_cdata.msk_jumbo_rx_tag);
2604 sc_if->msk_cdata.msk_jumbo_rx_tag = NULL;
2605 }
2606 }
2607
2608 static int
msk_encap(struct msk_if_softc * sc_if,struct mbuf ** m_head)2609 msk_encap(struct msk_if_softc *sc_if, struct mbuf **m_head)
2610 {
2611 struct msk_txdesc *txd, *txd_last;
2612 struct msk_tx_desc *tx_le;
2613 struct mbuf *m;
2614 bus_dmamap_t map;
2615 bus_dma_segment_t txsegs[MSK_MAXTXSEGS];
2616 uint32_t control, csum, prod, si;
2617 uint16_t offset, tcp_offset, tso_mtu;
2618 int error, i, nseg, tso;
2619
2620 MSK_IF_LOCK_ASSERT(sc_if);
2621
2622 tcp_offset = offset = 0;
2623 m = *m_head;
2624 if (((sc_if->msk_flags & MSK_FLAG_AUTOTX_CSUM) == 0 &&
2625 (m->m_pkthdr.csum_flags & MSK_CSUM_FEATURES) != 0) ||
2626 ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 &&
2627 (m->m_pkthdr.csum_flags & CSUM_TSO) != 0)) {
2628 /*
2629 * Since mbuf has no protocol specific structure information
2630 * in it we have to inspect protocol information here to
2631 * setup TSO and checksum offload. I don't know why Marvell
2632 * made a such decision in chip design because other GigE
2633 * hardwares normally takes care of all these chores in
2634 * hardware. However, TSO performance of Yukon II is very
2635 * good such that it's worth to implement it.
2636 */
2637 struct ether_header *eh;
2638 struct ip *ip;
2639 struct tcphdr *tcp;
2640
2641 if (M_WRITABLE(m) == 0) {
2642 /* Get a writable copy. */
2643 m = m_dup(*m_head, M_NOWAIT);
2644 m_freem(*m_head);
2645 if (m == NULL) {
2646 *m_head = NULL;
2647 return (ENOBUFS);
2648 }
2649 *m_head = m;
2650 }
2651
2652 offset = sizeof(struct ether_header);
2653 m = m_pullup(m, offset);
2654 if (m == NULL) {
2655 *m_head = NULL;
2656 return (ENOBUFS);
2657 }
2658 eh = mtod(m, struct ether_header *);
2659 /* Check if hardware VLAN insertion is off. */
2660 if (eh->ether_type == htons(ETHERTYPE_VLAN)) {
2661 offset = sizeof(struct ether_vlan_header);
2662 m = m_pullup(m, offset);
2663 if (m == NULL) {
2664 *m_head = NULL;
2665 return (ENOBUFS);
2666 }
2667 }
2668 m = m_pullup(m, offset + sizeof(struct ip));
2669 if (m == NULL) {
2670 *m_head = NULL;
2671 return (ENOBUFS);
2672 }
2673 ip = (struct ip *)(mtod(m, char *) + offset);
2674 offset += (ip->ip_hl << 2);
2675 tcp_offset = offset;
2676 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
2677 m = m_pullup(m, offset + sizeof(struct tcphdr));
2678 if (m == NULL) {
2679 *m_head = NULL;
2680 return (ENOBUFS);
2681 }
2682 tcp = (struct tcphdr *)(mtod(m, char *) + offset);
2683 offset += (tcp->th_off << 2);
2684 } else if ((sc_if->msk_flags & MSK_FLAG_AUTOTX_CSUM) == 0 &&
2685 (m->m_pkthdr.len < MSK_MIN_FRAMELEN) &&
2686 (m->m_pkthdr.csum_flags & CSUM_TCP) != 0) {
2687 /*
2688 * It seems that Yukon II has Tx checksum offload bug
2689 * for small TCP packets that's less than 60 bytes in
2690 * size (e.g. TCP window probe packet, pure ACK packet).
2691 * Common work around like padding with zeros to make
2692 * the frame minimum ethernet frame size didn't work at
2693 * all.
2694 * Instead of disabling checksum offload completely we
2695 * resort to S/W checksum routine when we encounter
2696 * short TCP frames.
2697 * Short UDP packets appear to be handled correctly by
2698 * Yukon II. Also I assume this bug does not happen on
2699 * controllers that use newer descriptor format or
2700 * automatic Tx checksum calculation.
2701 */
2702 m = m_pullup(m, offset + sizeof(struct tcphdr));
2703 if (m == NULL) {
2704 *m_head = NULL;
2705 return (ENOBUFS);
2706 }
2707 *(uint16_t *)(m->m_data + offset +
2708 m->m_pkthdr.csum_data) = in_cksum_skip(m,
2709 m->m_pkthdr.len, offset);
2710 m->m_pkthdr.csum_flags &= ~CSUM_TCP;
2711 }
2712 *m_head = m;
2713 }
2714
2715 prod = sc_if->msk_cdata.msk_tx_prod;
2716 txd = &sc_if->msk_cdata.msk_txdesc[prod];
2717 txd_last = txd;
2718 map = txd->tx_dmamap;
2719 error = bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_tx_tag, map,
2720 *m_head, txsegs, &nseg, BUS_DMA_NOWAIT);
2721 if (error == EFBIG) {
2722 m = m_collapse(*m_head, M_NOWAIT, MSK_MAXTXSEGS);
2723 if (m == NULL) {
2724 m_freem(*m_head);
2725 *m_head = NULL;
2726 return (ENOBUFS);
2727 }
2728 *m_head = m;
2729 error = bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_tx_tag,
2730 map, *m_head, txsegs, &nseg, BUS_DMA_NOWAIT);
2731 if (error != 0) {
2732 m_freem(*m_head);
2733 *m_head = NULL;
2734 return (error);
2735 }
2736 } else if (error != 0)
2737 return (error);
2738 if (nseg == 0) {
2739 m_freem(*m_head);
2740 *m_head = NULL;
2741 return (EIO);
2742 }
2743
2744 /* Check number of available descriptors. */
2745 if (sc_if->msk_cdata.msk_tx_cnt + nseg >=
2746 (MSK_TX_RING_CNT - MSK_RESERVED_TX_DESC_CNT)) {
2747 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, map);
2748 return (ENOBUFS);
2749 }
2750
2751 control = 0;
2752 tso = 0;
2753 tx_le = NULL;
2754
2755 /* Check TSO support. */
2756 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
2757 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0)
2758 tso_mtu = m->m_pkthdr.tso_segsz;
2759 else
2760 tso_mtu = offset + m->m_pkthdr.tso_segsz;
2761 if (tso_mtu != sc_if->msk_cdata.msk_tso_mtu) {
2762 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
2763 tx_le->msk_addr = htole32(tso_mtu);
2764 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0)
2765 tx_le->msk_control = htole32(OP_MSS | HW_OWNER);
2766 else
2767 tx_le->msk_control =
2768 htole32(OP_LRGLEN | HW_OWNER);
2769 sc_if->msk_cdata.msk_tx_cnt++;
2770 MSK_INC(prod, MSK_TX_RING_CNT);
2771 sc_if->msk_cdata.msk_tso_mtu = tso_mtu;
2772 }
2773 tso++;
2774 }
2775 /* Check if we have a VLAN tag to insert. */
2776 if ((m->m_flags & M_VLANTAG) != 0) {
2777 if (tx_le == NULL) {
2778 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
2779 tx_le->msk_addr = htole32(0);
2780 tx_le->msk_control = htole32(OP_VLAN | HW_OWNER |
2781 htons(m->m_pkthdr.ether_vtag));
2782 sc_if->msk_cdata.msk_tx_cnt++;
2783 MSK_INC(prod, MSK_TX_RING_CNT);
2784 } else {
2785 tx_le->msk_control |= htole32(OP_VLAN |
2786 htons(m->m_pkthdr.ether_vtag));
2787 }
2788 control |= INS_VLAN;
2789 }
2790 /* Check if we have to handle checksum offload. */
2791 if (tso == 0 && (m->m_pkthdr.csum_flags & MSK_CSUM_FEATURES) != 0) {
2792 if ((sc_if->msk_flags & MSK_FLAG_AUTOTX_CSUM) != 0)
2793 control |= CALSUM;
2794 else {
2795 control |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
2796 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0)
2797 control |= UDPTCP;
2798 /* Checksum write position. */
2799 csum = (tcp_offset + m->m_pkthdr.csum_data) & 0xffff;
2800 /* Checksum start position. */
2801 csum |= (uint32_t)tcp_offset << 16;
2802 if (csum != sc_if->msk_cdata.msk_last_csum) {
2803 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
2804 tx_le->msk_addr = htole32(csum);
2805 tx_le->msk_control = htole32(1 << 16 |
2806 (OP_TCPLISW | HW_OWNER));
2807 sc_if->msk_cdata.msk_tx_cnt++;
2808 MSK_INC(prod, MSK_TX_RING_CNT);
2809 sc_if->msk_cdata.msk_last_csum = csum;
2810 }
2811 }
2812 }
2813
2814 #ifdef MSK_64BIT_DMA
2815 if (MSK_ADDR_HI(txsegs[0].ds_addr) !=
2816 sc_if->msk_cdata.msk_tx_high_addr) {
2817 sc_if->msk_cdata.msk_tx_high_addr =
2818 MSK_ADDR_HI(txsegs[0].ds_addr);
2819 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
2820 tx_le->msk_addr = htole32(MSK_ADDR_HI(txsegs[0].ds_addr));
2821 tx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER);
2822 sc_if->msk_cdata.msk_tx_cnt++;
2823 MSK_INC(prod, MSK_TX_RING_CNT);
2824 }
2825 #endif
2826 si = prod;
2827 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
2828 tx_le->msk_addr = htole32(MSK_ADDR_LO(txsegs[0].ds_addr));
2829 if (tso == 0)
2830 tx_le->msk_control = htole32(txsegs[0].ds_len | control |
2831 OP_PACKET);
2832 else
2833 tx_le->msk_control = htole32(txsegs[0].ds_len | control |
2834 OP_LARGESEND);
2835 sc_if->msk_cdata.msk_tx_cnt++;
2836 MSK_INC(prod, MSK_TX_RING_CNT);
2837
2838 for (i = 1; i < nseg; i++) {
2839 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
2840 #ifdef MSK_64BIT_DMA
2841 if (MSK_ADDR_HI(txsegs[i].ds_addr) !=
2842 sc_if->msk_cdata.msk_tx_high_addr) {
2843 sc_if->msk_cdata.msk_tx_high_addr =
2844 MSK_ADDR_HI(txsegs[i].ds_addr);
2845 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
2846 tx_le->msk_addr =
2847 htole32(MSK_ADDR_HI(txsegs[i].ds_addr));
2848 tx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER);
2849 sc_if->msk_cdata.msk_tx_cnt++;
2850 MSK_INC(prod, MSK_TX_RING_CNT);
2851 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
2852 }
2853 #endif
2854 tx_le->msk_addr = htole32(MSK_ADDR_LO(txsegs[i].ds_addr));
2855 tx_le->msk_control = htole32(txsegs[i].ds_len | control |
2856 OP_BUFFER | HW_OWNER);
2857 sc_if->msk_cdata.msk_tx_cnt++;
2858 MSK_INC(prod, MSK_TX_RING_CNT);
2859 }
2860 /* Update producer index. */
2861 sc_if->msk_cdata.msk_tx_prod = prod;
2862
2863 /* Set EOP on the last descriptor. */
2864 prod = (prod + MSK_TX_RING_CNT - 1) % MSK_TX_RING_CNT;
2865 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
2866 tx_le->msk_control |= htole32(EOP);
2867
2868 /* Turn the first descriptor ownership to hardware. */
2869 tx_le = &sc_if->msk_rdata.msk_tx_ring[si];
2870 tx_le->msk_control |= htole32(HW_OWNER);
2871
2872 txd = &sc_if->msk_cdata.msk_txdesc[prod];
2873 map = txd_last->tx_dmamap;
2874 txd_last->tx_dmamap = txd->tx_dmamap;
2875 txd->tx_dmamap = map;
2876 txd->tx_m = m;
2877
2878 /* Sync descriptors. */
2879 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, map, BUS_DMASYNC_PREWRITE);
2880 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag,
2881 sc_if->msk_cdata.msk_tx_ring_map,
2882 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2883
2884 return (0);
2885 }
2886
2887 static void
msk_start(if_t ifp)2888 msk_start(if_t ifp)
2889 {
2890 struct msk_if_softc *sc_if;
2891
2892 sc_if = if_getsoftc(ifp);
2893 MSK_IF_LOCK(sc_if);
2894 msk_start_locked(ifp);
2895 MSK_IF_UNLOCK(sc_if);
2896 }
2897
2898 static void
msk_start_locked(if_t ifp)2899 msk_start_locked(if_t ifp)
2900 {
2901 struct msk_if_softc *sc_if;
2902 struct mbuf *m_head;
2903 int enq;
2904
2905 sc_if = if_getsoftc(ifp);
2906 MSK_IF_LOCK_ASSERT(sc_if);
2907
2908 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
2909 IFF_DRV_RUNNING || (sc_if->msk_flags & MSK_FLAG_LINK) == 0)
2910 return;
2911
2912 for (enq = 0; !if_sendq_empty(ifp) &&
2913 sc_if->msk_cdata.msk_tx_cnt <
2914 (MSK_TX_RING_CNT - MSK_RESERVED_TX_DESC_CNT); ) {
2915 m_head = if_dequeue(ifp);
2916 if (m_head == NULL)
2917 break;
2918 /*
2919 * Pack the data into the transmit ring. If we
2920 * don't have room, set the OACTIVE flag and wait
2921 * for the NIC to drain the ring.
2922 */
2923 if (msk_encap(sc_if, &m_head) != 0) {
2924 if (m_head == NULL)
2925 break;
2926 if_sendq_prepend(ifp, m_head);
2927 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
2928 break;
2929 }
2930
2931 enq++;
2932 /*
2933 * If there's a BPF listener, bounce a copy of this frame
2934 * to him.
2935 */
2936 ETHER_BPF_MTAP(ifp, m_head);
2937 }
2938
2939 if (enq > 0) {
2940 /* Transmit */
2941 CSR_WRITE_2(sc_if->msk_softc,
2942 Y2_PREF_Q_ADDR(sc_if->msk_txq, PREF_UNIT_PUT_IDX_REG),
2943 sc_if->msk_cdata.msk_tx_prod);
2944
2945 /* Set a timeout in case the chip goes out to lunch. */
2946 sc_if->msk_watchdog_timer = MSK_TX_TIMEOUT;
2947 }
2948 }
2949
2950 static void
msk_watchdog(struct msk_if_softc * sc_if)2951 msk_watchdog(struct msk_if_softc *sc_if)
2952 {
2953 if_t ifp;
2954
2955 MSK_IF_LOCK_ASSERT(sc_if);
2956
2957 if (sc_if->msk_watchdog_timer == 0 || --sc_if->msk_watchdog_timer)
2958 return;
2959 ifp = sc_if->msk_ifp;
2960 if ((sc_if->msk_flags & MSK_FLAG_LINK) == 0) {
2961 if (bootverbose)
2962 if_printf(sc_if->msk_ifp, "watchdog timeout "
2963 "(missed link)\n");
2964 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
2965 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
2966 msk_init_locked(sc_if);
2967 return;
2968 }
2969
2970 if_printf(ifp, "watchdog timeout\n");
2971 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
2972 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
2973 msk_init_locked(sc_if);
2974 if (!if_sendq_empty(ifp))
2975 msk_start_locked(ifp);
2976 }
2977
2978 static int
mskc_shutdown(device_t dev)2979 mskc_shutdown(device_t dev)
2980 {
2981 struct msk_softc *sc;
2982 int i;
2983
2984 sc = device_get_softc(dev);
2985 MSK_LOCK(sc);
2986 for (i = 0; i < sc->msk_num_port; i++) {
2987 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL &&
2988 ((if_getdrvflags(sc->msk_if[i]->msk_ifp) &
2989 IFF_DRV_RUNNING) != 0))
2990 msk_stop(sc->msk_if[i]);
2991 }
2992 MSK_UNLOCK(sc);
2993
2994 /* Put hardware reset. */
2995 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET);
2996 return (0);
2997 }
2998
2999 static int
mskc_suspend(device_t dev)3000 mskc_suspend(device_t dev)
3001 {
3002 struct msk_softc *sc;
3003 int i;
3004
3005 sc = device_get_softc(dev);
3006
3007 MSK_LOCK(sc);
3008
3009 for (i = 0; i < sc->msk_num_port; i++) {
3010 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL &&
3011 ((if_getdrvflags(sc->msk_if[i]->msk_ifp) &
3012 IFF_DRV_RUNNING) != 0))
3013 msk_stop(sc->msk_if[i]);
3014 }
3015
3016 /* Disable all interrupts. */
3017 CSR_WRITE_4(sc, B0_IMSK, 0);
3018 CSR_READ_4(sc, B0_IMSK);
3019 CSR_WRITE_4(sc, B0_HWE_IMSK, 0);
3020 CSR_READ_4(sc, B0_HWE_IMSK);
3021
3022 msk_phy_power(sc, MSK_PHY_POWERDOWN);
3023
3024 /* Put hardware reset. */
3025 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET);
3026 sc->msk_pflags |= MSK_FLAG_SUSPEND;
3027
3028 MSK_UNLOCK(sc);
3029
3030 return (0);
3031 }
3032
3033 static int
mskc_resume(device_t dev)3034 mskc_resume(device_t dev)
3035 {
3036 struct msk_softc *sc;
3037 int i;
3038
3039 sc = device_get_softc(dev);
3040
3041 MSK_LOCK(sc);
3042
3043 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_3, 0);
3044 mskc_reset(sc);
3045 for (i = 0; i < sc->msk_num_port; i++) {
3046 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL &&
3047 ((if_getflags(sc->msk_if[i]->msk_ifp) & IFF_UP) != 0)) {
3048 if_setdrvflagbits(sc->msk_if[i]->msk_ifp, 0,
3049 IFF_DRV_RUNNING);
3050 msk_init_locked(sc->msk_if[i]);
3051 }
3052 }
3053 sc->msk_pflags &= ~MSK_FLAG_SUSPEND;
3054
3055 MSK_UNLOCK(sc);
3056
3057 return (0);
3058 }
3059
3060 #ifndef __NO_STRICT_ALIGNMENT
3061 static __inline void
msk_fixup_rx(struct mbuf * m)3062 msk_fixup_rx(struct mbuf *m)
3063 {
3064 int i;
3065 uint16_t *src, *dst;
3066
3067 src = mtod(m, uint16_t *);
3068 dst = src - 3;
3069
3070 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++)
3071 *dst++ = *src++;
3072
3073 m->m_data -= (MSK_RX_BUF_ALIGN - ETHER_ALIGN);
3074 }
3075 #endif
3076
3077 static __inline void
msk_rxcsum(struct msk_if_softc * sc_if,uint32_t control,struct mbuf * m)3078 msk_rxcsum(struct msk_if_softc *sc_if, uint32_t control, struct mbuf *m)
3079 {
3080 struct ether_header *eh;
3081 struct ip *ip;
3082 struct udphdr *uh;
3083 int32_t hlen, len, pktlen, temp32;
3084 uint16_t csum, *opts;
3085
3086 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0) {
3087 if ((control & (CSS_IPV4 | CSS_IPFRAG)) == CSS_IPV4) {
3088 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
3089 if ((control & CSS_IPV4_CSUM_OK) != 0)
3090 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
3091 if ((control & (CSS_TCP | CSS_UDP)) != 0 &&
3092 (control & (CSS_TCPUDP_CSUM_OK)) != 0) {
3093 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
3094 CSUM_PSEUDO_HDR;
3095 m->m_pkthdr.csum_data = 0xffff;
3096 }
3097 }
3098 return;
3099 }
3100 /*
3101 * Marvell Yukon controllers that support OP_RXCHKS has known
3102 * to have various Rx checksum offloading bugs. These
3103 * controllers can be configured to compute simple checksum
3104 * at two different positions. So we can compute IP and TCP/UDP
3105 * checksum at the same time. We intentionally have controller
3106 * compute TCP/UDP checksum twice by specifying the same
3107 * checksum start position and compare the result. If the value
3108 * is different it would indicate the hardware logic was wrong.
3109 */
3110 if ((sc_if->msk_csum & 0xFFFF) != (sc_if->msk_csum >> 16)) {
3111 if (bootverbose)
3112 device_printf(sc_if->msk_if_dev,
3113 "Rx checksum value mismatch!\n");
3114 return;
3115 }
3116 pktlen = m->m_pkthdr.len;
3117 if (pktlen < sizeof(struct ether_header) + sizeof(struct ip))
3118 return;
3119 eh = mtod(m, struct ether_header *);
3120 if (eh->ether_type != htons(ETHERTYPE_IP))
3121 return;
3122 ip = (struct ip *)(eh + 1);
3123 if (ip->ip_v != IPVERSION)
3124 return;
3125
3126 hlen = ip->ip_hl << 2;
3127 pktlen -= sizeof(struct ether_header);
3128 if (hlen < sizeof(struct ip))
3129 return;
3130 if (ntohs(ip->ip_len) < hlen)
3131 return;
3132 if (ntohs(ip->ip_len) != pktlen)
3133 return;
3134 if (ip->ip_off & htons(IP_MF | IP_OFFMASK))
3135 return; /* can't handle fragmented packet. */
3136
3137 switch (ip->ip_p) {
3138 case IPPROTO_TCP:
3139 if (pktlen < (hlen + sizeof(struct tcphdr)))
3140 return;
3141 break;
3142 case IPPROTO_UDP:
3143 if (pktlen < (hlen + sizeof(struct udphdr)))
3144 return;
3145 uh = (struct udphdr *)((caddr_t)ip + hlen);
3146 if (uh->uh_sum == 0)
3147 return; /* no checksum */
3148 break;
3149 default:
3150 return;
3151 }
3152 csum = bswap16(sc_if->msk_csum & 0xFFFF);
3153 /* Checksum fixup for IP options. */
3154 len = hlen - sizeof(struct ip);
3155 if (len > 0) {
3156 opts = (uint16_t *)(ip + 1);
3157 for (; len > 0; len -= sizeof(uint16_t), opts++) {
3158 temp32 = csum - *opts;
3159 temp32 = (temp32 >> 16) + (temp32 & 65535);
3160 csum = temp32 & 65535;
3161 }
3162 }
3163 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID;
3164 m->m_pkthdr.csum_data = csum;
3165 }
3166
3167 static void
msk_rxeof(struct msk_if_softc * sc_if,uint32_t status,uint32_t control,int len)3168 msk_rxeof(struct msk_if_softc *sc_if, uint32_t status, uint32_t control,
3169 int len)
3170 {
3171 struct mbuf *m;
3172 if_t ifp;
3173 struct msk_rxdesc *rxd;
3174 int cons, rxlen;
3175
3176 ifp = sc_if->msk_ifp;
3177
3178 MSK_IF_LOCK_ASSERT(sc_if);
3179
3180 cons = sc_if->msk_cdata.msk_rx_cons;
3181 do {
3182 rxlen = status >> 16;
3183 if ((status & GMR_FS_VLAN) != 0 &&
3184 (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0)
3185 rxlen -= ETHER_VLAN_ENCAP_LEN;
3186 if ((sc_if->msk_flags & MSK_FLAG_NORXCHK) != 0) {
3187 /*
3188 * For controllers that returns bogus status code
3189 * just do minimal check and let upper stack
3190 * handle this frame.
3191 */
3192 if (len > MSK_MAX_FRAMELEN || len < ETHER_HDR_LEN) {
3193 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
3194 msk_discard_rxbuf(sc_if, cons);
3195 break;
3196 }
3197 } else if (len > sc_if->msk_framesize ||
3198 ((status & GMR_FS_ANY_ERR) != 0) ||
3199 ((status & GMR_FS_RX_OK) == 0) || (rxlen != len)) {
3200 /* Don't count flow-control packet as errors. */
3201 if ((status & GMR_FS_GOOD_FC) == 0)
3202 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
3203 msk_discard_rxbuf(sc_if, cons);
3204 break;
3205 }
3206 #ifdef MSK_64BIT_DMA
3207 rxd = &sc_if->msk_cdata.msk_rxdesc[(cons + 1) %
3208 MSK_RX_RING_CNT];
3209 #else
3210 rxd = &sc_if->msk_cdata.msk_rxdesc[cons];
3211 #endif
3212 m = rxd->rx_m;
3213 if (msk_newbuf(sc_if, cons) != 0) {
3214 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
3215 /* Reuse old buffer. */
3216 msk_discard_rxbuf(sc_if, cons);
3217 break;
3218 }
3219 m->m_pkthdr.rcvif = ifp;
3220 m->m_pkthdr.len = m->m_len = len;
3221 #ifndef __NO_STRICT_ALIGNMENT
3222 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0)
3223 msk_fixup_rx(m);
3224 #endif
3225 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
3226 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0)
3227 msk_rxcsum(sc_if, control, m);
3228 /* Check for VLAN tagged packets. */
3229 if ((status & GMR_FS_VLAN) != 0 &&
3230 (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) {
3231 m->m_pkthdr.ether_vtag = sc_if->msk_vtag;
3232 m->m_flags |= M_VLANTAG;
3233 }
3234 MSK_IF_UNLOCK(sc_if);
3235 if_input(ifp, m);
3236 MSK_IF_LOCK(sc_if);
3237 } while (0);
3238
3239 MSK_RX_INC(sc_if->msk_cdata.msk_rx_cons, MSK_RX_RING_CNT);
3240 MSK_RX_INC(sc_if->msk_cdata.msk_rx_prod, MSK_RX_RING_CNT);
3241 }
3242
3243 static void
msk_jumbo_rxeof(struct msk_if_softc * sc_if,uint32_t status,uint32_t control,int len)3244 msk_jumbo_rxeof(struct msk_if_softc *sc_if, uint32_t status, uint32_t control,
3245 int len)
3246 {
3247 struct mbuf *m;
3248 if_t ifp;
3249 struct msk_rxdesc *jrxd;
3250 int cons, rxlen;
3251
3252 ifp = sc_if->msk_ifp;
3253
3254 MSK_IF_LOCK_ASSERT(sc_if);
3255
3256 cons = sc_if->msk_cdata.msk_rx_cons;
3257 do {
3258 rxlen = status >> 16;
3259 if ((status & GMR_FS_VLAN) != 0 &&
3260 (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0)
3261 rxlen -= ETHER_VLAN_ENCAP_LEN;
3262 if (len > sc_if->msk_framesize ||
3263 ((status & GMR_FS_ANY_ERR) != 0) ||
3264 ((status & GMR_FS_RX_OK) == 0) || (rxlen != len)) {
3265 /* Don't count flow-control packet as errors. */
3266 if ((status & GMR_FS_GOOD_FC) == 0)
3267 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
3268 msk_discard_jumbo_rxbuf(sc_if, cons);
3269 break;
3270 }
3271 #ifdef MSK_64BIT_DMA
3272 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[(cons + 1) %
3273 MSK_JUMBO_RX_RING_CNT];
3274 #else
3275 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[cons];
3276 #endif
3277 m = jrxd->rx_m;
3278 if (msk_jumbo_newbuf(sc_if, cons) != 0) {
3279 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
3280 /* Reuse old buffer. */
3281 msk_discard_jumbo_rxbuf(sc_if, cons);
3282 break;
3283 }
3284 m->m_pkthdr.rcvif = ifp;
3285 m->m_pkthdr.len = m->m_len = len;
3286 #ifndef __NO_STRICT_ALIGNMENT
3287 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0)
3288 msk_fixup_rx(m);
3289 #endif
3290 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
3291 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0)
3292 msk_rxcsum(sc_if, control, m);
3293 /* Check for VLAN tagged packets. */
3294 if ((status & GMR_FS_VLAN) != 0 &&
3295 (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) {
3296 m->m_pkthdr.ether_vtag = sc_if->msk_vtag;
3297 m->m_flags |= M_VLANTAG;
3298 }
3299 MSK_IF_UNLOCK(sc_if);
3300 if_input(ifp, m);
3301 MSK_IF_LOCK(sc_if);
3302 } while (0);
3303
3304 MSK_RX_INC(sc_if->msk_cdata.msk_rx_cons, MSK_JUMBO_RX_RING_CNT);
3305 MSK_RX_INC(sc_if->msk_cdata.msk_rx_prod, MSK_JUMBO_RX_RING_CNT);
3306 }
3307
3308 static void
msk_txeof(struct msk_if_softc * sc_if,int idx)3309 msk_txeof(struct msk_if_softc *sc_if, int idx)
3310 {
3311 struct msk_txdesc *txd;
3312 struct msk_tx_desc *cur_tx;
3313 if_t ifp;
3314 uint32_t control;
3315 int cons, prog;
3316
3317 MSK_IF_LOCK_ASSERT(sc_if);
3318
3319 ifp = sc_if->msk_ifp;
3320
3321 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag,
3322 sc_if->msk_cdata.msk_tx_ring_map,
3323 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
3324 /*
3325 * Go through our tx ring and free mbufs for those
3326 * frames that have been sent.
3327 */
3328 cons = sc_if->msk_cdata.msk_tx_cons;
3329 prog = 0;
3330 for (; cons != idx; MSK_INC(cons, MSK_TX_RING_CNT)) {
3331 if (sc_if->msk_cdata.msk_tx_cnt <= 0)
3332 break;
3333 prog++;
3334 cur_tx = &sc_if->msk_rdata.msk_tx_ring[cons];
3335 control = le32toh(cur_tx->msk_control);
3336 sc_if->msk_cdata.msk_tx_cnt--;
3337 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
3338 if ((control & EOP) == 0)
3339 continue;
3340 txd = &sc_if->msk_cdata.msk_txdesc[cons];
3341 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, txd->tx_dmamap,
3342 BUS_DMASYNC_POSTWRITE);
3343 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, txd->tx_dmamap);
3344
3345 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
3346 KASSERT(txd->tx_m != NULL, ("%s: freeing NULL mbuf!",
3347 __func__));
3348 m_freem(txd->tx_m);
3349 txd->tx_m = NULL;
3350 }
3351
3352 if (prog > 0) {
3353 sc_if->msk_cdata.msk_tx_cons = cons;
3354 if (sc_if->msk_cdata.msk_tx_cnt == 0)
3355 sc_if->msk_watchdog_timer = 0;
3356 /* No need to sync LEs as we didn't update LEs. */
3357 }
3358 }
3359
3360 static void
msk_tick(void * xsc_if)3361 msk_tick(void *xsc_if)
3362 {
3363 struct epoch_tracker et;
3364 struct msk_if_softc *sc_if;
3365 struct mii_data *mii;
3366
3367 sc_if = xsc_if;
3368
3369 MSK_IF_LOCK_ASSERT(sc_if);
3370
3371 mii = device_get_softc(sc_if->msk_miibus);
3372
3373 mii_tick(mii);
3374 if ((sc_if->msk_flags & MSK_FLAG_LINK) == 0)
3375 msk_miibus_statchg(sc_if->msk_if_dev);
3376 NET_EPOCH_ENTER(et);
3377 msk_handle_events(sc_if->msk_softc);
3378 NET_EPOCH_EXIT(et);
3379 msk_watchdog(sc_if);
3380 callout_reset(&sc_if->msk_tick_ch, hz, msk_tick, sc_if);
3381 }
3382
3383 static void
msk_intr_phy(struct msk_if_softc * sc_if)3384 msk_intr_phy(struct msk_if_softc *sc_if)
3385 {
3386 uint16_t status;
3387
3388 msk_phy_readreg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_STAT);
3389 status = msk_phy_readreg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_STAT);
3390 /* Handle FIFO Underrun/Overflow? */
3391 if ((status & PHY_M_IS_FIFO_ERROR))
3392 device_printf(sc_if->msk_if_dev,
3393 "PHY FIFO underrun/overflow.\n");
3394 }
3395
3396 static void
msk_intr_gmac(struct msk_if_softc * sc_if)3397 msk_intr_gmac(struct msk_if_softc *sc_if)
3398 {
3399 struct msk_softc *sc;
3400 uint8_t status;
3401
3402 sc = sc_if->msk_softc;
3403 status = CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC));
3404
3405 /* GMAC Rx FIFO overrun. */
3406 if ((status & GM_IS_RX_FF_OR) != 0)
3407 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T),
3408 GMF_CLI_RX_FO);
3409 /* GMAC Tx FIFO underrun. */
3410 if ((status & GM_IS_TX_FF_UR) != 0) {
3411 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
3412 GMF_CLI_TX_FU);
3413 device_printf(sc_if->msk_if_dev, "Tx FIFO underrun!\n");
3414 /*
3415 * XXX
3416 * In case of Tx underrun, we may need to flush/reset
3417 * Tx MAC but that would also require resynchronization
3418 * with status LEs. Reinitializing status LEs would
3419 * affect other port in dual MAC configuration so it
3420 * should be avoided as possible as we can.
3421 * Due to lack of documentation it's all vague guess but
3422 * it needs more investigation.
3423 */
3424 }
3425 }
3426
3427 static void
msk_handle_hwerr(struct msk_if_softc * sc_if,uint32_t status)3428 msk_handle_hwerr(struct msk_if_softc *sc_if, uint32_t status)
3429 {
3430 struct msk_softc *sc;
3431
3432 sc = sc_if->msk_softc;
3433 if ((status & Y2_IS_PAR_RD1) != 0) {
3434 device_printf(sc_if->msk_if_dev,
3435 "RAM buffer read parity error\n");
3436 /* Clear IRQ. */
3437 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(sc_if->msk_port, B3_RI_CTRL),
3438 RI_CLR_RD_PERR);
3439 }
3440 if ((status & Y2_IS_PAR_WR1) != 0) {
3441 device_printf(sc_if->msk_if_dev,
3442 "RAM buffer write parity error\n");
3443 /* Clear IRQ. */
3444 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(sc_if->msk_port, B3_RI_CTRL),
3445 RI_CLR_WR_PERR);
3446 }
3447 if ((status & Y2_IS_PAR_MAC1) != 0) {
3448 device_printf(sc_if->msk_if_dev, "Tx MAC parity error\n");
3449 /* Clear IRQ. */
3450 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
3451 GMF_CLI_TX_PE);
3452 }
3453 if ((status & Y2_IS_PAR_RX1) != 0) {
3454 device_printf(sc_if->msk_if_dev, "Rx parity error\n");
3455 /* Clear IRQ. */
3456 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_IRQ_PAR);
3457 }
3458 if ((status & (Y2_IS_TCP_TXS1 | Y2_IS_TCP_TXA1)) != 0) {
3459 device_printf(sc_if->msk_if_dev, "TCP segmentation error\n");
3460 /* Clear IRQ. */
3461 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_IRQ_TCP);
3462 }
3463 }
3464
3465 static void
msk_intr_hwerr(struct msk_softc * sc)3466 msk_intr_hwerr(struct msk_softc *sc)
3467 {
3468 uint32_t status;
3469 uint32_t tlphead[4];
3470
3471 status = CSR_READ_4(sc, B0_HWE_ISRC);
3472 /* Time Stamp timer overflow. */
3473 if ((status & Y2_IS_TIST_OV) != 0)
3474 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
3475 if ((status & Y2_IS_PCI_NEXP) != 0) {
3476 /*
3477 * PCI Express Error occurred which is not described in PEX
3478 * spec.
3479 * This error is also mapped either to Master Abort(
3480 * Y2_IS_MST_ERR) or Target Abort (Y2_IS_IRQ_STAT) bit and
3481 * can only be cleared there.
3482 */
3483 device_printf(sc->msk_dev,
3484 "PCI Express protocol violation error\n");
3485 }
3486
3487 if ((status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) != 0) {
3488 uint16_t v16;
3489
3490 if ((status & Y2_IS_MST_ERR) != 0)
3491 device_printf(sc->msk_dev,
3492 "unexpected IRQ Status error\n");
3493 else
3494 device_printf(sc->msk_dev,
3495 "unexpected IRQ Master error\n");
3496 /* Reset all bits in the PCI status register. */
3497 v16 = pci_read_config(sc->msk_dev, PCIR_STATUS, 2);
3498 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3499 pci_write_config(sc->msk_dev, PCIR_STATUS, v16 |
3500 PCIM_STATUS_PERR | PCIM_STATUS_SERR | PCIM_STATUS_RMABORT |
3501 PCIM_STATUS_RTABORT | PCIM_STATUS_MDPERR, 2);
3502 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3503 }
3504
3505 /* Check for PCI Express Uncorrectable Error. */
3506 if ((status & Y2_IS_PCI_EXP) != 0) {
3507 uint32_t v32;
3508
3509 /*
3510 * On PCI Express bus bridges are called root complexes (RC).
3511 * PCI Express errors are recognized by the root complex too,
3512 * which requests the system to handle the problem. After
3513 * error occurrence it may be that no access to the adapter
3514 * may be performed any longer.
3515 */
3516
3517 v32 = CSR_PCI_READ_4(sc, PEX_UNC_ERR_STAT);
3518 if ((v32 & PEX_UNSUP_REQ) != 0) {
3519 /* Ignore unsupported request error. */
3520 device_printf(sc->msk_dev,
3521 "Uncorrectable PCI Express error\n");
3522 }
3523 if ((v32 & (PEX_FATAL_ERRORS | PEX_POIS_TLP)) != 0) {
3524 int i;
3525
3526 /* Get TLP header form Log Registers. */
3527 for (i = 0; i < 4; i++)
3528 tlphead[i] = CSR_PCI_READ_4(sc,
3529 PEX_HEADER_LOG + i * 4);
3530 /* Check for vendor defined broadcast message. */
3531 if (!(tlphead[0] == 0x73004001 && tlphead[1] == 0x7f)) {
3532 sc->msk_intrhwemask &= ~Y2_IS_PCI_EXP;
3533 CSR_WRITE_4(sc, B0_HWE_IMSK,
3534 sc->msk_intrhwemask);
3535 CSR_READ_4(sc, B0_HWE_IMSK);
3536 }
3537 }
3538 /* Clear the interrupt. */
3539 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3540 CSR_PCI_WRITE_4(sc, PEX_UNC_ERR_STAT, 0xffffffff);
3541 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3542 }
3543
3544 if ((status & Y2_HWE_L1_MASK) != 0 && sc->msk_if[MSK_PORT_A] != NULL)
3545 msk_handle_hwerr(sc->msk_if[MSK_PORT_A], status);
3546 if ((status & Y2_HWE_L2_MASK) != 0 && sc->msk_if[MSK_PORT_B] != NULL)
3547 msk_handle_hwerr(sc->msk_if[MSK_PORT_B], status >> 8);
3548 }
3549
3550 static __inline void
msk_rxput(struct msk_if_softc * sc_if)3551 msk_rxput(struct msk_if_softc *sc_if)
3552 {
3553 struct msk_softc *sc;
3554
3555 sc = sc_if->msk_softc;
3556 if (sc_if->msk_framesize > (MCLBYTES - MSK_RX_BUF_ALIGN))
3557 bus_dmamap_sync(
3558 sc_if->msk_cdata.msk_jumbo_rx_ring_tag,
3559 sc_if->msk_cdata.msk_jumbo_rx_ring_map,
3560 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3561 else
3562 bus_dmamap_sync(
3563 sc_if->msk_cdata.msk_rx_ring_tag,
3564 sc_if->msk_cdata.msk_rx_ring_map,
3565 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3566 CSR_WRITE_2(sc, Y2_PREF_Q_ADDR(sc_if->msk_rxq,
3567 PREF_UNIT_PUT_IDX_REG), sc_if->msk_cdata.msk_rx_prod);
3568 }
3569
3570 static int
msk_handle_events(struct msk_softc * sc)3571 msk_handle_events(struct msk_softc *sc)
3572 {
3573 struct msk_if_softc *sc_if;
3574 int rxput[2];
3575 struct msk_stat_desc *sd;
3576 uint32_t control, status;
3577 int cons, len, port, rxprog;
3578
3579 if (sc->msk_stat_cons == CSR_READ_2(sc, STAT_PUT_IDX))
3580 return (0);
3581
3582 /* Sync status LEs. */
3583 bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map,
3584 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
3585
3586 rxput[MSK_PORT_A] = rxput[MSK_PORT_B] = 0;
3587 rxprog = 0;
3588 cons = sc->msk_stat_cons;
3589 for (;;) {
3590 sd = &sc->msk_stat_ring[cons];
3591 control = le32toh(sd->msk_control);
3592 if ((control & HW_OWNER) == 0)
3593 break;
3594 control &= ~HW_OWNER;
3595 sd->msk_control = htole32(control);
3596 status = le32toh(sd->msk_status);
3597 len = control & STLE_LEN_MASK;
3598 port = (control >> 16) & 0x01;
3599 sc_if = sc->msk_if[port];
3600 if (sc_if == NULL) {
3601 device_printf(sc->msk_dev, "invalid port opcode "
3602 "0x%08x\n", control & STLE_OP_MASK);
3603 continue;
3604 }
3605
3606 switch (control & STLE_OP_MASK) {
3607 case OP_RXVLAN:
3608 sc_if->msk_vtag = ntohs(len);
3609 break;
3610 case OP_RXCHKSVLAN:
3611 sc_if->msk_vtag = ntohs(len);
3612 /* FALLTHROUGH */
3613 case OP_RXCHKS:
3614 sc_if->msk_csum = status;
3615 break;
3616 case OP_RXSTAT:
3617 if (!(if_getdrvflags(sc_if->msk_ifp) & IFF_DRV_RUNNING))
3618 break;
3619 if (sc_if->msk_framesize >
3620 (MCLBYTES - MSK_RX_BUF_ALIGN))
3621 msk_jumbo_rxeof(sc_if, status, control, len);
3622 else
3623 msk_rxeof(sc_if, status, control, len);
3624 rxprog++;
3625 /*
3626 * Because there is no way to sync single Rx LE
3627 * put the DMA sync operation off until the end of
3628 * event processing.
3629 */
3630 rxput[port]++;
3631 /* Update prefetch unit if we've passed water mark. */
3632 if (rxput[port] >= sc_if->msk_cdata.msk_rx_putwm) {
3633 msk_rxput(sc_if);
3634 rxput[port] = 0;
3635 }
3636 break;
3637 case OP_TXINDEXLE:
3638 if (sc->msk_if[MSK_PORT_A] != NULL)
3639 msk_txeof(sc->msk_if[MSK_PORT_A],
3640 status & STLE_TXA1_MSKL);
3641 if (sc->msk_if[MSK_PORT_B] != NULL)
3642 msk_txeof(sc->msk_if[MSK_PORT_B],
3643 ((status & STLE_TXA2_MSKL) >>
3644 STLE_TXA2_SHIFTL) |
3645 ((len & STLE_TXA2_MSKH) <<
3646 STLE_TXA2_SHIFTH));
3647 break;
3648 default:
3649 device_printf(sc->msk_dev, "unhandled opcode 0x%08x\n",
3650 control & STLE_OP_MASK);
3651 break;
3652 }
3653 MSK_INC(cons, sc->msk_stat_count);
3654 if (rxprog > sc->msk_process_limit)
3655 break;
3656 }
3657
3658 sc->msk_stat_cons = cons;
3659 bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map,
3660 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3661
3662 if (rxput[MSK_PORT_A] > 0)
3663 msk_rxput(sc->msk_if[MSK_PORT_A]);
3664 if (rxput[MSK_PORT_B] > 0)
3665 msk_rxput(sc->msk_if[MSK_PORT_B]);
3666
3667 return (sc->msk_stat_cons != CSR_READ_2(sc, STAT_PUT_IDX));
3668 }
3669
3670 static void
msk_intr(void * xsc)3671 msk_intr(void *xsc)
3672 {
3673 struct msk_softc *sc;
3674 struct msk_if_softc *sc_if0, *sc_if1;
3675 if_t ifp0, ifp1;
3676 uint32_t status;
3677 int domore;
3678
3679 sc = xsc;
3680 MSK_LOCK(sc);
3681
3682 /* Reading B0_Y2_SP_ISRC2 masks further interrupts. */
3683 status = CSR_READ_4(sc, B0_Y2_SP_ISRC2);
3684 if (status == 0 || status == 0xffffffff ||
3685 (sc->msk_pflags & MSK_FLAG_SUSPEND) != 0 ||
3686 (status & sc->msk_intrmask) == 0) {
3687 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2);
3688 MSK_UNLOCK(sc);
3689 return;
3690 }
3691
3692 sc_if0 = sc->msk_if[MSK_PORT_A];
3693 sc_if1 = sc->msk_if[MSK_PORT_B];
3694 ifp0 = ifp1 = NULL;
3695 if (sc_if0 != NULL)
3696 ifp0 = sc_if0->msk_ifp;
3697 if (sc_if1 != NULL)
3698 ifp1 = sc_if1->msk_ifp;
3699
3700 if ((status & Y2_IS_IRQ_PHY1) != 0 && sc_if0 != NULL)
3701 msk_intr_phy(sc_if0);
3702 if ((status & Y2_IS_IRQ_PHY2) != 0 && sc_if1 != NULL)
3703 msk_intr_phy(sc_if1);
3704 if ((status & Y2_IS_IRQ_MAC1) != 0 && sc_if0 != NULL)
3705 msk_intr_gmac(sc_if0);
3706 if ((status & Y2_IS_IRQ_MAC2) != 0 && sc_if1 != NULL)
3707 msk_intr_gmac(sc_if1);
3708 if ((status & (Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2)) != 0) {
3709 device_printf(sc->msk_dev, "Rx descriptor error\n");
3710 sc->msk_intrmask &= ~(Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2);
3711 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask);
3712 CSR_READ_4(sc, B0_IMSK);
3713 }
3714 if ((status & (Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2)) != 0) {
3715 device_printf(sc->msk_dev, "Tx descriptor error\n");
3716 sc->msk_intrmask &= ~(Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2);
3717 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask);
3718 CSR_READ_4(sc, B0_IMSK);
3719 }
3720 if ((status & Y2_IS_HW_ERR) != 0)
3721 msk_intr_hwerr(sc);
3722
3723 domore = msk_handle_events(sc);
3724 if ((status & Y2_IS_STAT_BMU) != 0 && domore == 0)
3725 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_CLR_IRQ);
3726
3727 /* Reenable interrupts. */
3728 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2);
3729
3730 if (ifp0 != NULL && (if_getdrvflags(ifp0) & IFF_DRV_RUNNING) != 0 &&
3731 !if_sendq_empty(ifp0))
3732 msk_start_locked(ifp0);
3733 if (ifp1 != NULL && (if_getdrvflags(ifp1) & IFF_DRV_RUNNING) != 0 &&
3734 !if_sendq_empty(ifp1))
3735 msk_start_locked(ifp1);
3736
3737 MSK_UNLOCK(sc);
3738 }
3739
3740 static void
msk_set_tx_stfwd(struct msk_if_softc * sc_if)3741 msk_set_tx_stfwd(struct msk_if_softc *sc_if)
3742 {
3743 struct msk_softc *sc;
3744 if_t ifp;
3745
3746 ifp = sc_if->msk_ifp;
3747 sc = sc_if->msk_softc;
3748 if ((sc->msk_hw_id == CHIP_ID_YUKON_EX &&
3749 sc->msk_hw_rev != CHIP_REV_YU_EX_A0) ||
3750 sc->msk_hw_id >= CHIP_ID_YUKON_SUPR) {
3751 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
3752 TX_STFW_ENA);
3753 } else {
3754 if (if_getmtu(ifp) > ETHERMTU) {
3755 /* Set Tx GMAC FIFO Almost Empty Threshold. */
3756 CSR_WRITE_4(sc,
3757 MR_ADDR(sc_if->msk_port, TX_GMF_AE_THR),
3758 MSK_ECU_JUMBO_WM << 16 | MSK_ECU_AE_THR);
3759 /* Disable Store & Forward mode for Tx. */
3760 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
3761 TX_STFW_DIS);
3762 } else {
3763 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
3764 TX_STFW_ENA);
3765 }
3766 }
3767 }
3768
3769 static void
msk_init(void * xsc)3770 msk_init(void *xsc)
3771 {
3772 struct msk_if_softc *sc_if = xsc;
3773
3774 MSK_IF_LOCK(sc_if);
3775 msk_init_locked(sc_if);
3776 MSK_IF_UNLOCK(sc_if);
3777 }
3778
3779 static void
msk_init_locked(struct msk_if_softc * sc_if)3780 msk_init_locked(struct msk_if_softc *sc_if)
3781 {
3782 struct msk_softc *sc;
3783 if_t ifp;
3784 struct mii_data *mii;
3785 uint8_t *eaddr;
3786 uint16_t gmac;
3787 uint32_t reg;
3788 int error;
3789
3790 MSK_IF_LOCK_ASSERT(sc_if);
3791
3792 ifp = sc_if->msk_ifp;
3793 sc = sc_if->msk_softc;
3794 mii = device_get_softc(sc_if->msk_miibus);
3795
3796 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)
3797 return;
3798
3799 error = 0;
3800 /* Cancel pending I/O and free all Rx/Tx buffers. */
3801 msk_stop(sc_if);
3802
3803 if (if_getmtu(ifp) < ETHERMTU)
3804 sc_if->msk_framesize = ETHERMTU;
3805 else
3806 sc_if->msk_framesize = if_getmtu(ifp);
3807 sc_if->msk_framesize += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
3808 if (if_getmtu(ifp) > ETHERMTU &&
3809 (sc_if->msk_flags & MSK_FLAG_JUMBO_NOCSUM) != 0) {
3810 if_sethwassistbits(ifp, 0, (MSK_CSUM_FEATURES | CSUM_TSO));
3811 if_setcapenablebit(ifp, 0, (IFCAP_TSO4 | IFCAP_TXCSUM));
3812 }
3813
3814 /* GMAC Control reset. */
3815 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_RST_SET);
3816 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_RST_CLR);
3817 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_F_LOOPB_OFF);
3818 if (sc->msk_hw_id == CHIP_ID_YUKON_EX ||
3819 sc->msk_hw_id == CHIP_ID_YUKON_SUPR)
3820 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL),
3821 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON |
3822 GMC_BYP_RETR_ON);
3823
3824 /*
3825 * Initialize GMAC first such that speed/duplex/flow-control
3826 * parameters are renegotiated when interface is brought up.
3827 */
3828 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, 0);
3829
3830 /* Dummy read the Interrupt Source Register. */
3831 CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC));
3832
3833 /* Clear MIB stats. */
3834 msk_stats_clear(sc_if);
3835
3836 /* Disable FCS. */
3837 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, GM_RXCR_CRC_DIS);
3838
3839 /* Setup Transmit Control Register. */
3840 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
3841
3842 /* Setup Transmit Flow Control Register. */
3843 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_FLOW_CTRL, 0xffff);
3844
3845 /* Setup Transmit Parameter Register. */
3846 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_PARAM,
3847 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) | TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
3848 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) | TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
3849
3850 gmac = DATA_BLIND_VAL(DATA_BLIND_DEF) |
3851 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
3852
3853 if (if_getmtu(ifp) > ETHERMTU)
3854 gmac |= GM_SMOD_JUMBO_ENA;
3855 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SERIAL_MODE, gmac);
3856
3857 /* Set station address. */
3858 eaddr = if_getlladdr(ifp);
3859 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_1L,
3860 eaddr[0] | (eaddr[1] << 8));
3861 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_1M,
3862 eaddr[2] | (eaddr[3] << 8));
3863 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_1H,
3864 eaddr[4] | (eaddr[5] << 8));
3865 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_2L,
3866 eaddr[0] | (eaddr[1] << 8));
3867 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_2M,
3868 eaddr[2] | (eaddr[3] << 8));
3869 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_2H,
3870 eaddr[4] | (eaddr[5] << 8));
3871
3872 /* Disable interrupts for counter overflows. */
3873 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_IRQ_MSK, 0);
3874 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_IRQ_MSK, 0);
3875 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TR_IRQ_MSK, 0);
3876
3877 /* Configure Rx MAC FIFO. */
3878 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET);
3879 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_CLR);
3880 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
3881 if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P ||
3882 sc->msk_hw_id == CHIP_ID_YUKON_EX)
3883 reg |= GMF_RX_OVER_ON;
3884 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), reg);
3885
3886 /* Set receive filter. */
3887 msk_rxfilter(sc_if);
3888
3889 if (sc->msk_hw_id == CHIP_ID_YUKON_XL) {
3890 /* Clear flush mask - HW bug. */
3891 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_MSK), 0);
3892 } else {
3893 /* Flush Rx MAC FIFO on any flow control or error. */
3894 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_MSK),
3895 GMR_FS_ANY_ERR);
3896 }
3897
3898 /*
3899 * Set Rx FIFO flush threshold to 64 bytes + 1 FIFO word
3900 * due to hardware hang on receipt of pause frames.
3901 */
3902 reg = RX_GMF_FL_THR_DEF + 1;
3903 /* Another magic for Yukon FE+ - From Linux. */
3904 if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P &&
3905 sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0)
3906 reg = 0x178;
3907 CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_THR), reg);
3908
3909 /* Configure Tx MAC FIFO. */
3910 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_SET);
3911 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_CLR);
3912 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_OPER_ON);
3913
3914 /* Configure hardware VLAN tag insertion/stripping. */
3915 msk_setvlan(sc_if, ifp);
3916
3917 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) {
3918 /* Set Rx Pause threshold. */
3919 CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_LP_THR),
3920 MSK_ECU_LLPP);
3921 CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_UP_THR),
3922 MSK_ECU_ULPP);
3923 /* Configure store-and-forward for Tx. */
3924 msk_set_tx_stfwd(sc_if);
3925 }
3926
3927 if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P &&
3928 sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) {
3929 /* Disable dynamic watermark - from Linux. */
3930 reg = CSR_READ_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_EA));
3931 reg &= ~0x03;
3932 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_EA), reg);
3933 }
3934
3935 /*
3936 * Disable Force Sync bit and Alloc bit in Tx RAM interface
3937 * arbiter as we don't use Sync Tx queue.
3938 */
3939 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL),
3940 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
3941 /* Enable the RAM Interface Arbiter. */
3942 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), TXA_ENA_ARB);
3943
3944 /* Setup RAM buffer. */
3945 msk_set_rambuffer(sc_if);
3946
3947 /* Disable Tx sync Queue. */
3948 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txsq, RB_CTRL), RB_RST_SET);
3949
3950 /* Setup Tx Queue Bus Memory Interface. */
3951 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_RESET);
3952 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_OPER_INIT);
3953 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_FIFO_OP_ON);
3954 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_WM), MSK_BMU_TX_WM);
3955 switch (sc->msk_hw_id) {
3956 case CHIP_ID_YUKON_EC_U:
3957 if (sc->msk_hw_rev == CHIP_REV_YU_EC_U_A0) {
3958 /* Fix for Yukon-EC Ultra: set BMU FIFO level */
3959 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_AL),
3960 MSK_ECU_TXFF_LEV);
3961 }
3962 break;
3963 case CHIP_ID_YUKON_EX:
3964 /*
3965 * Yukon Extreme seems to have silicon bug for
3966 * automatic Tx checksum calculation capability.
3967 */
3968 if (sc->msk_hw_rev == CHIP_REV_YU_EX_B0)
3969 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_F),
3970 F_TX_CHK_AUTO_OFF);
3971 break;
3972 }
3973
3974 /* Setup Rx Queue Bus Memory Interface. */
3975 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_RESET);
3976 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_OPER_INIT);
3977 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_FIFO_OP_ON);
3978 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_rxq, Q_WM), MSK_BMU_RX_WM);
3979 if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U &&
3980 sc->msk_hw_rev >= CHIP_REV_YU_EC_U_A1) {
3981 /* MAC Rx RAM Read is controlled by hardware. */
3982 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_F), F_M_RX_RAM_DIS);
3983 }
3984
3985 msk_set_prefetch(sc, sc_if->msk_txq,
3986 sc_if->msk_rdata.msk_tx_ring_paddr, MSK_TX_RING_CNT - 1);
3987 msk_init_tx_ring(sc_if);
3988
3989 /* Disable Rx checksum offload and RSS hash. */
3990 reg = BMU_DIS_RX_RSS_HASH;
3991 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 &&
3992 (if_getcapenable(ifp) & IFCAP_RXCSUM) != 0)
3993 reg |= BMU_ENA_RX_CHKSUM;
3994 else
3995 reg |= BMU_DIS_RX_CHKSUM;
3996 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), reg);
3997 if (sc_if->msk_framesize > (MCLBYTES - MSK_RX_BUF_ALIGN)) {
3998 msk_set_prefetch(sc, sc_if->msk_rxq,
3999 sc_if->msk_rdata.msk_jumbo_rx_ring_paddr,
4000 MSK_JUMBO_RX_RING_CNT - 1);
4001 error = msk_init_jumbo_rx_ring(sc_if);
4002 } else {
4003 msk_set_prefetch(sc, sc_if->msk_rxq,
4004 sc_if->msk_rdata.msk_rx_ring_paddr,
4005 MSK_RX_RING_CNT - 1);
4006 error = msk_init_rx_ring(sc_if);
4007 }
4008 if (error != 0) {
4009 device_printf(sc_if->msk_if_dev,
4010 "initialization failed: no memory for Rx buffers\n");
4011 msk_stop(sc_if);
4012 return;
4013 }
4014 if (sc->msk_hw_id == CHIP_ID_YUKON_EX ||
4015 sc->msk_hw_id == CHIP_ID_YUKON_SUPR) {
4016 /* Disable flushing of non-ASF packets. */
4017 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T),
4018 GMF_RX_MACSEC_FLUSH_OFF);
4019 }
4020
4021 /* Configure interrupt handling. */
4022 if (sc_if->msk_port == MSK_PORT_A) {
4023 sc->msk_intrmask |= Y2_IS_PORT_A;
4024 sc->msk_intrhwemask |= Y2_HWE_L1_MASK;
4025 } else {
4026 sc->msk_intrmask |= Y2_IS_PORT_B;
4027 sc->msk_intrhwemask |= Y2_HWE_L2_MASK;
4028 }
4029 /* Configure IRQ moderation mask. */
4030 CSR_WRITE_4(sc, B2_IRQM_MSK, sc->msk_intrmask);
4031 if (sc->msk_int_holdoff > 0) {
4032 /* Configure initial IRQ moderation timer value. */
4033 CSR_WRITE_4(sc, B2_IRQM_INI,
4034 MSK_USECS(sc, sc->msk_int_holdoff));
4035 CSR_WRITE_4(sc, B2_IRQM_VAL,
4036 MSK_USECS(sc, sc->msk_int_holdoff));
4037 /* Start IRQ moderation. */
4038 CSR_WRITE_1(sc, B2_IRQM_CTRL, TIM_START);
4039 }
4040 CSR_WRITE_4(sc, B0_HWE_IMSK, sc->msk_intrhwemask);
4041 CSR_READ_4(sc, B0_HWE_IMSK);
4042 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask);
4043 CSR_READ_4(sc, B0_IMSK);
4044
4045 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0);
4046 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
4047
4048 sc_if->msk_flags &= ~MSK_FLAG_LINK;
4049 mii_mediachg(mii);
4050
4051 callout_reset(&sc_if->msk_tick_ch, hz, msk_tick, sc_if);
4052 }
4053
4054 static void
msk_set_rambuffer(struct msk_if_softc * sc_if)4055 msk_set_rambuffer(struct msk_if_softc *sc_if)
4056 {
4057 struct msk_softc *sc;
4058 int ltpp, utpp;
4059
4060 sc = sc_if->msk_softc;
4061 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0)
4062 return;
4063
4064 /* Setup Rx Queue. */
4065 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_RST_CLR);
4066 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_START),
4067 sc->msk_rxqstart[sc_if->msk_port] / 8);
4068 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_END),
4069 sc->msk_rxqend[sc_if->msk_port] / 8);
4070 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_WP),
4071 sc->msk_rxqstart[sc_if->msk_port] / 8);
4072 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RP),
4073 sc->msk_rxqstart[sc_if->msk_port] / 8);
4074
4075 utpp = (sc->msk_rxqend[sc_if->msk_port] + 1 -
4076 sc->msk_rxqstart[sc_if->msk_port] - MSK_RB_ULPP) / 8;
4077 ltpp = (sc->msk_rxqend[sc_if->msk_port] + 1 -
4078 sc->msk_rxqstart[sc_if->msk_port] - MSK_RB_LLPP_B) / 8;
4079 if (sc->msk_rxqsize < MSK_MIN_RXQ_SIZE)
4080 ltpp += (MSK_RB_LLPP_B - MSK_RB_LLPP_S) / 8;
4081 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RX_UTPP), utpp);
4082 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RX_LTPP), ltpp);
4083 /* Set Rx priority(RB_RX_UTHP/RB_RX_LTHP) thresholds? */
4084
4085 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_ENA_OP_MD);
4086 CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL));
4087
4088 /* Setup Tx Queue. */
4089 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_RST_CLR);
4090 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_START),
4091 sc->msk_txqstart[sc_if->msk_port] / 8);
4092 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_END),
4093 sc->msk_txqend[sc_if->msk_port] / 8);
4094 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_WP),
4095 sc->msk_txqstart[sc_if->msk_port] / 8);
4096 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_RP),
4097 sc->msk_txqstart[sc_if->msk_port] / 8);
4098 /* Enable Store & Forward for Tx side. */
4099 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_ENA_STFWD);
4100 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_ENA_OP_MD);
4101 CSR_READ_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL));
4102 }
4103
4104 static void
msk_set_prefetch(struct msk_softc * sc,int qaddr,bus_addr_t addr,uint32_t count)4105 msk_set_prefetch(struct msk_softc *sc, int qaddr, bus_addr_t addr,
4106 uint32_t count)
4107 {
4108
4109 /* Reset the prefetch unit. */
4110 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG),
4111 PREF_UNIT_RST_SET);
4112 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG),
4113 PREF_UNIT_RST_CLR);
4114 /* Set LE base address. */
4115 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_LOW_REG),
4116 MSK_ADDR_LO(addr));
4117 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_HI_REG),
4118 MSK_ADDR_HI(addr));
4119 /* Set the list last index. */
4120 CSR_WRITE_2(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_LAST_IDX_REG),
4121 count);
4122 /* Turn on prefetch unit. */
4123 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG),
4124 PREF_UNIT_OP_ON);
4125 /* Dummy read to ensure write. */
4126 CSR_READ_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG));
4127 }
4128
4129 static void
msk_stop(struct msk_if_softc * sc_if)4130 msk_stop(struct msk_if_softc *sc_if)
4131 {
4132 struct msk_softc *sc;
4133 struct msk_txdesc *txd;
4134 struct msk_rxdesc *rxd;
4135 struct msk_rxdesc *jrxd;
4136 if_t ifp;
4137 uint32_t val;
4138 int i;
4139
4140 MSK_IF_LOCK_ASSERT(sc_if);
4141 sc = sc_if->msk_softc;
4142 ifp = sc_if->msk_ifp;
4143
4144 callout_stop(&sc_if->msk_tick_ch);
4145 sc_if->msk_watchdog_timer = 0;
4146
4147 /* Disable interrupts. */
4148 if (sc_if->msk_port == MSK_PORT_A) {
4149 sc->msk_intrmask &= ~Y2_IS_PORT_A;
4150 sc->msk_intrhwemask &= ~Y2_HWE_L1_MASK;
4151 } else {
4152 sc->msk_intrmask &= ~Y2_IS_PORT_B;
4153 sc->msk_intrhwemask &= ~Y2_HWE_L2_MASK;
4154 }
4155 CSR_WRITE_4(sc, B0_HWE_IMSK, sc->msk_intrhwemask);
4156 CSR_READ_4(sc, B0_HWE_IMSK);
4157 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask);
4158 CSR_READ_4(sc, B0_IMSK);
4159
4160 /* Disable Tx/Rx MAC. */
4161 val = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL);
4162 val &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
4163 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, val);
4164 /* Read again to ensure writing. */
4165 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL);
4166 /* Update stats and clear counters. */
4167 msk_stats_update(sc_if);
4168
4169 /* Stop Tx BMU. */
4170 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_STOP);
4171 val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR));
4172 for (i = 0; i < MSK_TIMEOUT; i++) {
4173 if ((val & (BMU_STOP | BMU_IDLE)) == 0) {
4174 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR),
4175 BMU_STOP);
4176 val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR));
4177 } else
4178 break;
4179 DELAY(1);
4180 }
4181 if (i == MSK_TIMEOUT)
4182 device_printf(sc_if->msk_if_dev, "Tx BMU stop failed\n");
4183 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL),
4184 RB_RST_SET | RB_DIS_OP_MD);
4185
4186 /* Disable all GMAC interrupt. */
4187 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_MSK), 0);
4188 /* Disable PHY interrupt. */
4189 msk_phy_writereg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_MASK, 0);
4190
4191 /* Disable the RAM Interface Arbiter. */
4192 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), TXA_DIS_ARB);
4193
4194 /* Reset the PCI FIFO of the async Tx queue */
4195 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR),
4196 BMU_RST_SET | BMU_FIFO_RST);
4197
4198 /* Reset the Tx prefetch units. */
4199 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(sc_if->msk_txq, PREF_UNIT_CTRL_REG),
4200 PREF_UNIT_RST_SET);
4201
4202 /* Reset the RAM Buffer async Tx queue. */
4203 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_RST_SET);
4204
4205 /* Reset Tx MAC FIFO. */
4206 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_SET);
4207 /* Set Pause Off. */
4208 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_PAUSE_OFF);
4209
4210 /*
4211 * The Rx Stop command will not work for Yukon-2 if the BMU does not
4212 * reach the end of packet and since we can't make sure that we have
4213 * incoming data, we must reset the BMU while it is not during a DMA
4214 * transfer. Since it is possible that the Rx path is still active,
4215 * the Rx RAM buffer will be stopped first, so any possible incoming
4216 * data will not trigger a DMA. After the RAM buffer is stopped, the
4217 * BMU is polled until any DMA in progress is ended and only then it
4218 * will be reset.
4219 */
4220
4221 /* Disable the RAM Buffer receive queue. */
4222 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_DIS_OP_MD);
4223 for (i = 0; i < MSK_TIMEOUT; i++) {
4224 if (CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, Q_RSL)) ==
4225 CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, Q_RL)))
4226 break;
4227 DELAY(1);
4228 }
4229 if (i == MSK_TIMEOUT)
4230 device_printf(sc_if->msk_if_dev, "Rx BMU stop failed\n");
4231 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR),
4232 BMU_RST_SET | BMU_FIFO_RST);
4233 /* Reset the Rx prefetch unit. */
4234 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_CTRL_REG),
4235 PREF_UNIT_RST_SET);
4236 /* Reset the RAM Buffer receive queue. */
4237 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_RST_SET);
4238 /* Reset Rx MAC FIFO. */
4239 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET);
4240
4241 /* Free Rx and Tx mbufs still in the queues. */
4242 for (i = 0; i < MSK_RX_RING_CNT; i++) {
4243 rxd = &sc_if->msk_cdata.msk_rxdesc[i];
4244 if (rxd->rx_m != NULL) {
4245 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag,
4246 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
4247 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_tag,
4248 rxd->rx_dmamap);
4249 m_freem(rxd->rx_m);
4250 rxd->rx_m = NULL;
4251 }
4252 }
4253 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) {
4254 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i];
4255 if (jrxd->rx_m != NULL) {
4256 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag,
4257 jrxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
4258 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_tag,
4259 jrxd->rx_dmamap);
4260 m_freem(jrxd->rx_m);
4261 jrxd->rx_m = NULL;
4262 }
4263 }
4264 for (i = 0; i < MSK_TX_RING_CNT; i++) {
4265 txd = &sc_if->msk_cdata.msk_txdesc[i];
4266 if (txd->tx_m != NULL) {
4267 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag,
4268 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
4269 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag,
4270 txd->tx_dmamap);
4271 m_freem(txd->tx_m);
4272 txd->tx_m = NULL;
4273 }
4274 }
4275
4276 /*
4277 * Mark the interface down.
4278 */
4279 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE));
4280 sc_if->msk_flags &= ~MSK_FLAG_LINK;
4281 }
4282
4283 /*
4284 * When GM_PAR_MIB_CLR bit of GM_PHY_ADDR is set, reading lower
4285 * counter clears high 16 bits of the counter such that accessing
4286 * lower 16 bits should be the last operation.
4287 */
4288 #define MSK_READ_MIB32(x, y) \
4289 ((((uint32_t)GMAC_READ_2(sc, x, (y) + 4)) << 16) + \
4290 (uint32_t)GMAC_READ_2(sc, x, y))
4291 #define MSK_READ_MIB64(x, y) \
4292 ((((uint64_t)MSK_READ_MIB32(x, (y) + 8)) << 32) + \
4293 (uint64_t)MSK_READ_MIB32(x, y))
4294
4295 static void
msk_stats_clear(struct msk_if_softc * sc_if)4296 msk_stats_clear(struct msk_if_softc *sc_if)
4297 {
4298 struct msk_softc *sc;
4299 uint16_t gmac;
4300 int i;
4301
4302 MSK_IF_LOCK_ASSERT(sc_if);
4303
4304 sc = sc_if->msk_softc;
4305 /* Set MIB Clear Counter Mode. */
4306 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_PHY_ADDR);
4307 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR);
4308 /* Read all MIB Counters with Clear Mode set. */
4309 for (i = GM_RXF_UC_OK; i <= GM_TXE_FIFO_UR; i += sizeof(uint32_t))
4310 (void)MSK_READ_MIB32(sc_if->msk_port, i);
4311 /* Clear MIB Clear Counter Mode. */
4312 gmac &= ~GM_PAR_MIB_CLR;
4313 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac);
4314 }
4315
4316 static void
msk_stats_update(struct msk_if_softc * sc_if)4317 msk_stats_update(struct msk_if_softc *sc_if)
4318 {
4319 struct msk_softc *sc;
4320 if_t ifp;
4321 struct msk_hw_stats *stats;
4322 uint16_t gmac;
4323
4324 MSK_IF_LOCK_ASSERT(sc_if);
4325
4326 ifp = sc_if->msk_ifp;
4327 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0)
4328 return;
4329 sc = sc_if->msk_softc;
4330 stats = &sc_if->msk_stats;
4331 /* Set MIB Clear Counter Mode. */
4332 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_PHY_ADDR);
4333 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR);
4334
4335 /* Rx stats. */
4336 stats->rx_ucast_frames +=
4337 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_UC_OK);
4338 stats->rx_bcast_frames +=
4339 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_BC_OK);
4340 stats->rx_pause_frames +=
4341 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_MPAUSE);
4342 stats->rx_mcast_frames +=
4343 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_MC_OK);
4344 stats->rx_crc_errs +=
4345 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_FCS_ERR);
4346 stats->rx_good_octets +=
4347 MSK_READ_MIB64(sc_if->msk_port, GM_RXO_OK_LO);
4348 stats->rx_bad_octets +=
4349 MSK_READ_MIB64(sc_if->msk_port, GM_RXO_ERR_LO);
4350 stats->rx_runts +=
4351 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_SHT);
4352 stats->rx_runt_errs +=
4353 MSK_READ_MIB32(sc_if->msk_port, GM_RXE_FRAG);
4354 stats->rx_pkts_64 +=
4355 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_64B);
4356 stats->rx_pkts_65_127 +=
4357 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_127B);
4358 stats->rx_pkts_128_255 +=
4359 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_255B);
4360 stats->rx_pkts_256_511 +=
4361 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_511B);
4362 stats->rx_pkts_512_1023 +=
4363 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_1023B);
4364 stats->rx_pkts_1024_1518 +=
4365 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_1518B);
4366 stats->rx_pkts_1519_max +=
4367 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_MAX_SZ);
4368 stats->rx_pkts_too_long +=
4369 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_LNG_ERR);
4370 stats->rx_pkts_jabbers +=
4371 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_JAB_PKT);
4372 stats->rx_fifo_oflows +=
4373 MSK_READ_MIB32(sc_if->msk_port, GM_RXE_FIFO_OV);
4374
4375 /* Tx stats. */
4376 stats->tx_ucast_frames +=
4377 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_UC_OK);
4378 stats->tx_bcast_frames +=
4379 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_BC_OK);
4380 stats->tx_pause_frames +=
4381 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MPAUSE);
4382 stats->tx_mcast_frames +=
4383 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MC_OK);
4384 stats->tx_octets +=
4385 MSK_READ_MIB64(sc_if->msk_port, GM_TXO_OK_LO);
4386 stats->tx_pkts_64 +=
4387 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_64B);
4388 stats->tx_pkts_65_127 +=
4389 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_127B);
4390 stats->tx_pkts_128_255 +=
4391 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_255B);
4392 stats->tx_pkts_256_511 +=
4393 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_511B);
4394 stats->tx_pkts_512_1023 +=
4395 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_1023B);
4396 stats->tx_pkts_1024_1518 +=
4397 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_1518B);
4398 stats->tx_pkts_1519_max +=
4399 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MAX_SZ);
4400 stats->tx_colls +=
4401 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_COL);
4402 stats->tx_late_colls +=
4403 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_LAT_COL);
4404 stats->tx_excess_colls +=
4405 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_ABO_COL);
4406 stats->tx_multi_colls +=
4407 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MUL_COL);
4408 stats->tx_single_colls +=
4409 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_SNG_COL);
4410 stats->tx_underflows +=
4411 MSK_READ_MIB32(sc_if->msk_port, GM_TXE_FIFO_UR);
4412 /* Clear MIB Clear Counter Mode. */
4413 gmac &= ~GM_PAR_MIB_CLR;
4414 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac);
4415 }
4416
4417 static int
msk_sysctl_stat32(SYSCTL_HANDLER_ARGS)4418 msk_sysctl_stat32(SYSCTL_HANDLER_ARGS)
4419 {
4420 struct msk_softc *sc;
4421 struct msk_if_softc *sc_if;
4422 uint32_t result, *stat;
4423 int off;
4424
4425 sc_if = (struct msk_if_softc *)arg1;
4426 sc = sc_if->msk_softc;
4427 off = arg2;
4428 stat = (uint32_t *)((uint8_t *)&sc_if->msk_stats + off);
4429
4430 MSK_IF_LOCK(sc_if);
4431 result = MSK_READ_MIB32(sc_if->msk_port, GM_MIB_CNT_BASE + off * 2);
4432 result += *stat;
4433 MSK_IF_UNLOCK(sc_if);
4434
4435 return (sysctl_handle_int(oidp, &result, 0, req));
4436 }
4437
4438 static int
msk_sysctl_stat64(SYSCTL_HANDLER_ARGS)4439 msk_sysctl_stat64(SYSCTL_HANDLER_ARGS)
4440 {
4441 struct msk_softc *sc;
4442 struct msk_if_softc *sc_if;
4443 uint64_t result, *stat;
4444 int off;
4445
4446 sc_if = (struct msk_if_softc *)arg1;
4447 sc = sc_if->msk_softc;
4448 off = arg2;
4449 stat = (uint64_t *)((uint8_t *)&sc_if->msk_stats + off);
4450
4451 MSK_IF_LOCK(sc_if);
4452 result = MSK_READ_MIB64(sc_if->msk_port, GM_MIB_CNT_BASE + off * 2);
4453 result += *stat;
4454 MSK_IF_UNLOCK(sc_if);
4455
4456 return (sysctl_handle_64(oidp, &result, 0, req));
4457 }
4458
4459 #undef MSK_READ_MIB32
4460 #undef MSK_READ_MIB64
4461
4462 #define MSK_SYSCTL_STAT32(sc, c, o, p, n, d) \
4463 SYSCTL_ADD_PROC(c, p, OID_AUTO, o, \
4464 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, \
4465 sc, offsetof(struct msk_hw_stats, n), msk_sysctl_stat32, \
4466 "IU", d)
4467 #define MSK_SYSCTL_STAT64(sc, c, o, p, n, d) \
4468 SYSCTL_ADD_PROC(c, p, OID_AUTO, o, \
4469 CTLTYPE_U64 | CTLFLAG_RD | CTLFLAG_NEEDGIANT, \
4470 sc, offsetof(struct msk_hw_stats, n), msk_sysctl_stat64, \
4471 "QU", d)
4472
4473 static void
msk_sysctl_node(struct msk_if_softc * sc_if)4474 msk_sysctl_node(struct msk_if_softc *sc_if)
4475 {
4476 struct sysctl_ctx_list *ctx;
4477 struct sysctl_oid_list *child, *schild;
4478 struct sysctl_oid *tree;
4479
4480 ctx = device_get_sysctl_ctx(sc_if->msk_if_dev);
4481 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc_if->msk_if_dev));
4482
4483 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats",
4484 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "MSK Statistics");
4485 schild = SYSCTL_CHILDREN(tree);
4486 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "rx",
4487 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "MSK RX Statistics");
4488 child = SYSCTL_CHILDREN(tree);
4489 MSK_SYSCTL_STAT32(sc_if, ctx, "ucast_frames",
4490 child, rx_ucast_frames, "Good unicast frames");
4491 MSK_SYSCTL_STAT32(sc_if, ctx, "bcast_frames",
4492 child, rx_bcast_frames, "Good broadcast frames");
4493 MSK_SYSCTL_STAT32(sc_if, ctx, "pause_frames",
4494 child, rx_pause_frames, "Pause frames");
4495 MSK_SYSCTL_STAT32(sc_if, ctx, "mcast_frames",
4496 child, rx_mcast_frames, "Multicast frames");
4497 MSK_SYSCTL_STAT32(sc_if, ctx, "crc_errs",
4498 child, rx_crc_errs, "CRC errors");
4499 MSK_SYSCTL_STAT64(sc_if, ctx, "good_octets",
4500 child, rx_good_octets, "Good octets");
4501 MSK_SYSCTL_STAT64(sc_if, ctx, "bad_octets",
4502 child, rx_bad_octets, "Bad octets");
4503 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_64",
4504 child, rx_pkts_64, "64 bytes frames");
4505 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_65_127",
4506 child, rx_pkts_65_127, "65 to 127 bytes frames");
4507 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_128_255",
4508 child, rx_pkts_128_255, "128 to 255 bytes frames");
4509 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_256_511",
4510 child, rx_pkts_256_511, "256 to 511 bytes frames");
4511 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_512_1023",
4512 child, rx_pkts_512_1023, "512 to 1023 bytes frames");
4513 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1024_1518",
4514 child, rx_pkts_1024_1518, "1024 to 1518 bytes frames");
4515 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1519_max",
4516 child, rx_pkts_1519_max, "1519 to max frames");
4517 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_too_long",
4518 child, rx_pkts_too_long, "frames too long");
4519 MSK_SYSCTL_STAT32(sc_if, ctx, "jabbers",
4520 child, rx_pkts_jabbers, "Jabber errors");
4521 MSK_SYSCTL_STAT32(sc_if, ctx, "overflows",
4522 child, rx_fifo_oflows, "FIFO overflows");
4523
4524 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "tx",
4525 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "MSK TX Statistics");
4526 child = SYSCTL_CHILDREN(tree);
4527 MSK_SYSCTL_STAT32(sc_if, ctx, "ucast_frames",
4528 child, tx_ucast_frames, "Unicast frames");
4529 MSK_SYSCTL_STAT32(sc_if, ctx, "bcast_frames",
4530 child, tx_bcast_frames, "Broadcast frames");
4531 MSK_SYSCTL_STAT32(sc_if, ctx, "pause_frames",
4532 child, tx_pause_frames, "Pause frames");
4533 MSK_SYSCTL_STAT32(sc_if, ctx, "mcast_frames",
4534 child, tx_mcast_frames, "Multicast frames");
4535 MSK_SYSCTL_STAT64(sc_if, ctx, "octets",
4536 child, tx_octets, "Octets");
4537 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_64",
4538 child, tx_pkts_64, "64 bytes frames");
4539 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_65_127",
4540 child, tx_pkts_65_127, "65 to 127 bytes frames");
4541 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_128_255",
4542 child, tx_pkts_128_255, "128 to 255 bytes frames");
4543 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_256_511",
4544 child, tx_pkts_256_511, "256 to 511 bytes frames");
4545 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_512_1023",
4546 child, tx_pkts_512_1023, "512 to 1023 bytes frames");
4547 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1024_1518",
4548 child, tx_pkts_1024_1518, "1024 to 1518 bytes frames");
4549 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1519_max",
4550 child, tx_pkts_1519_max, "1519 to max frames");
4551 MSK_SYSCTL_STAT32(sc_if, ctx, "colls",
4552 child, tx_colls, "Collisions");
4553 MSK_SYSCTL_STAT32(sc_if, ctx, "late_colls",
4554 child, tx_late_colls, "Late collisions");
4555 MSK_SYSCTL_STAT32(sc_if, ctx, "excess_colls",
4556 child, tx_excess_colls, "Excessive collisions");
4557 MSK_SYSCTL_STAT32(sc_if, ctx, "multi_colls",
4558 child, tx_multi_colls, "Multiple collisions");
4559 MSK_SYSCTL_STAT32(sc_if, ctx, "single_colls",
4560 child, tx_single_colls, "Single collisions");
4561 MSK_SYSCTL_STAT32(sc_if, ctx, "underflows",
4562 child, tx_underflows, "FIFO underflows");
4563 }
4564
4565 #undef MSK_SYSCTL_STAT32
4566 #undef MSK_SYSCTL_STAT64
4567
4568 static int
sysctl_int_range(SYSCTL_HANDLER_ARGS,int low,int high)4569 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
4570 {
4571 int error, value;
4572
4573 if (!arg1)
4574 return (EINVAL);
4575 value = *(int *)arg1;
4576 error = sysctl_handle_int(oidp, &value, 0, req);
4577 if (error || !req->newptr)
4578 return (error);
4579 if (value < low || value > high)
4580 return (EINVAL);
4581 *(int *)arg1 = value;
4582
4583 return (0);
4584 }
4585
4586 static int
sysctl_hw_msk_proc_limit(SYSCTL_HANDLER_ARGS)4587 sysctl_hw_msk_proc_limit(SYSCTL_HANDLER_ARGS)
4588 {
4589
4590 return (sysctl_int_range(oidp, arg1, arg2, req, MSK_PROC_MIN,
4591 MSK_PROC_MAX));
4592 }
4593