1 /*
2 * mr_sas.c: source for mr_sas driver
3 *
4 * Solaris MegaRAID device driver for SAS2.0 controllers
5 * Copyright (c) 2008-2012, LSI Logic Corporation.
6 * All rights reserved.
7 *
8 * Version:
9 * Author:
10 * Swaminathan K S
11 * Arun Chandrashekhar
12 * Manju R
13 * Rasheed
14 * Shakeel Bukhari
15 *
16 * Redistribution and use in source and binary forms, with or without
17 * modification, are permitted provided that the following conditions are met:
18 *
19 * 1. Redistributions of source code must retain the above copyright notice,
20 * this list of conditions and the following disclaimer.
21 *
22 * 2. Redistributions in binary form must reproduce the above copyright notice,
23 * this list of conditions and the following disclaimer in the documentation
24 * and/or other materials provided with the distribution.
25 *
26 * 3. Neither the name of the author nor the names of its contributors may be
27 * used to endorse or promote products derived from this software without
28 * specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
33 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
34 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
35 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
36 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
37 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
38 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
39 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
40 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
41 * DAMAGE.
42 */
43
44 /*
45 * Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved.
46 * Copyright (c) 2011 Bayard G. Bell. All rights reserved.
47 * Copyright 2013 Nexenta Systems, Inc. All rights reserved.
48 * Copyright 2015, 2017 Citrus IT Limited. All rights reserved.
49 * Copyright 2015 Garrett D'Amore <garrett@damore.org>
50 * Copyright 2023 Oxide Computer Company
51 */
52
53 #include <sys/types.h>
54 #include <sys/param.h>
55 #include <sys/file.h>
56 #include <sys/errno.h>
57 #include <sys/open.h>
58 #include <sys/cred.h>
59 #include <sys/modctl.h>
60 #include <sys/conf.h>
61 #include <sys/devops.h>
62 #include <sys/cmn_err.h>
63 #include <sys/kmem.h>
64 #include <sys/stat.h>
65 #include <sys/mkdev.h>
66 #include <sys/pci.h>
67 #include <sys/scsi/scsi.h>
68 #include <sys/ddi.h>
69 #include <sys/sunddi.h>
70 #include <sys/atomic.h>
71 #include <sys/signal.h>
72 #include <sys/byteorder.h>
73 #include <sys/sdt.h>
74 #include <sys/fs/dv_node.h> /* devfs_clean */
75
76 #include "mr_sas.h"
77
78 /*
79 * FMA header files
80 */
81 #include <sys/ddifm.h>
82 #include <sys/fm/protocol.h>
83 #include <sys/fm/util.h>
84 #include <sys/fm/io/ddi.h>
85
86 /* Macros to help Skinny and stock 2108/MFI live together. */
87 #define WR_IB_PICK_QPORT(addr, instance) \
88 if ((instance)->skinny) { \
89 WR_IB_LOW_QPORT((addr), (instance)); \
90 WR_IB_HIGH_QPORT(0, (instance)); \
91 } else { \
92 WR_IB_QPORT((addr), (instance)); \
93 }
94
95 /*
96 * Local static data
97 */
98 static void *mrsas_state = NULL;
99 static volatile boolean_t mrsas_relaxed_ordering = B_TRUE;
100 volatile int debug_level_g = CL_NONE;
101 static volatile int msi_enable = 1;
102 static volatile int ctio_enable = 1;
103
104 /* Default Timeout value to issue online controller reset */
105 volatile int debug_timeout_g = 0xF0; /* 0xB4; */
106 /* Simulate consecutive firmware fault */
107 static volatile int debug_fw_faults_after_ocr_g = 0;
108 #ifdef OCRDEBUG
109 /* Simulate three consecutive timeout for an IO */
110 static volatile int debug_consecutive_timeout_after_ocr_g = 0;
111 #endif
112
113 #pragma weak scsi_hba_open
114 #pragma weak scsi_hba_close
115 #pragma weak scsi_hba_ioctl
116
117 /* Local static prototypes. */
118 static int mrsas_getinfo(dev_info_t *, ddi_info_cmd_t, void *, void **);
119 static int mrsas_attach(dev_info_t *, ddi_attach_cmd_t);
120 #ifdef __sparc
121 static int mrsas_reset(dev_info_t *, ddi_reset_cmd_t);
122 #else
123 static int mrsas_quiesce(dev_info_t *);
124 #endif
125 static int mrsas_detach(dev_info_t *, ddi_detach_cmd_t);
126 static int mrsas_open(dev_t *, int, int, cred_t *);
127 static int mrsas_close(dev_t, int, int, cred_t *);
128 static int mrsas_ioctl(dev_t, int, intptr_t, int, cred_t *, int *);
129
130 static int mrsas_tran_tgt_init(dev_info_t *, dev_info_t *,
131 scsi_hba_tran_t *, struct scsi_device *);
132 static struct scsi_pkt *mrsas_tran_init_pkt(struct scsi_address *, register
133 struct scsi_pkt *, struct buf *, int, int, int, int,
134 int (*)(), caddr_t);
135 static int mrsas_tran_start(struct scsi_address *,
136 register struct scsi_pkt *);
137 static int mrsas_tran_abort(struct scsi_address *, struct scsi_pkt *);
138 static int mrsas_tran_reset(struct scsi_address *, int);
139 static int mrsas_tran_getcap(struct scsi_address *, char *, int);
140 static int mrsas_tran_setcap(struct scsi_address *, char *, int, int);
141 static void mrsas_tran_destroy_pkt(struct scsi_address *,
142 struct scsi_pkt *);
143 static void mrsas_tran_dmafree(struct scsi_address *, struct scsi_pkt *);
144 static void mrsas_tran_sync_pkt(struct scsi_address *, struct scsi_pkt *);
145 static int mrsas_tran_quiesce(dev_info_t *dip);
146 static int mrsas_tran_unquiesce(dev_info_t *dip);
147 static uint_t mrsas_isr(caddr_t, caddr_t);
148 static uint_t mrsas_softintr();
149 static void mrsas_undo_resources(dev_info_t *, struct mrsas_instance *);
150
151 static void free_space_for_mfi(struct mrsas_instance *);
152 static uint32_t read_fw_status_reg_ppc(struct mrsas_instance *);
153 static void issue_cmd_ppc(struct mrsas_cmd *, struct mrsas_instance *);
154 static int issue_cmd_in_poll_mode_ppc(struct mrsas_instance *,
155 struct mrsas_cmd *);
156 static int issue_cmd_in_sync_mode_ppc(struct mrsas_instance *,
157 struct mrsas_cmd *);
158 static void enable_intr_ppc(struct mrsas_instance *);
159 static void disable_intr_ppc(struct mrsas_instance *);
160 static int intr_ack_ppc(struct mrsas_instance *);
161 static void flush_cache(struct mrsas_instance *instance);
162 void display_scsi_inquiry(caddr_t);
163 static int start_mfi_aen(struct mrsas_instance *instance);
164 static int handle_drv_ioctl(struct mrsas_instance *instance,
165 struct mrsas_ioctl *ioctl, int mode);
166 static int handle_mfi_ioctl(struct mrsas_instance *instance,
167 struct mrsas_ioctl *ioctl, int mode);
168 static int handle_mfi_aen(struct mrsas_instance *instance,
169 struct mrsas_aen *aen);
170 static struct mrsas_cmd *build_cmd(struct mrsas_instance *,
171 struct scsi_address *, struct scsi_pkt *, uchar_t *);
172 static int alloc_additional_dma_buffer(struct mrsas_instance *);
173 static void complete_cmd_in_sync_mode(struct mrsas_instance *,
174 struct mrsas_cmd *);
175 static int mrsas_kill_adapter(struct mrsas_instance *);
176 static int mrsas_issue_init_mfi(struct mrsas_instance *);
177 static int mrsas_reset_ppc(struct mrsas_instance *);
178 static uint32_t mrsas_initiate_ocr_if_fw_is_faulty(struct mrsas_instance *);
179 static int wait_for_outstanding(struct mrsas_instance *instance);
180 static int register_mfi_aen(struct mrsas_instance *instance,
181 uint32_t seq_num, uint32_t class_locale_word);
182 static int issue_mfi_pthru(struct mrsas_instance *instance, struct
183 mrsas_ioctl *ioctl, struct mrsas_cmd *cmd, int mode);
184 static int issue_mfi_dcmd(struct mrsas_instance *instance, struct
185 mrsas_ioctl *ioctl, struct mrsas_cmd *cmd, int mode);
186 static int issue_mfi_smp(struct mrsas_instance *instance, struct
187 mrsas_ioctl *ioctl, struct mrsas_cmd *cmd, int mode);
188 static int issue_mfi_stp(struct mrsas_instance *instance, struct
189 mrsas_ioctl *ioctl, struct mrsas_cmd *cmd, int mode);
190 static int abort_aen_cmd(struct mrsas_instance *instance,
191 struct mrsas_cmd *cmd_to_abort);
192
193 static void mrsas_rem_intrs(struct mrsas_instance *instance);
194 static int mrsas_add_intrs(struct mrsas_instance *instance, int intr_type);
195
196 static void mrsas_tran_tgt_free(dev_info_t *, dev_info_t *,
197 scsi_hba_tran_t *, struct scsi_device *);
198 static int mrsas_tran_bus_config(dev_info_t *, uint_t,
199 ddi_bus_config_op_t, void *, dev_info_t **);
200 static int mrsas_parse_devname(char *, int *, int *);
201 static int mrsas_config_all_devices(struct mrsas_instance *);
202 static int mrsas_config_ld(struct mrsas_instance *, uint16_t,
203 uint8_t, dev_info_t **);
204 static int mrsas_name_node(dev_info_t *, char *, int);
205 static void mrsas_issue_evt_taskq(struct mrsas_eventinfo *);
206 static void free_additional_dma_buffer(struct mrsas_instance *);
207 static void io_timeout_checker(void *);
208 static void mrsas_fm_init(struct mrsas_instance *);
209 static void mrsas_fm_fini(struct mrsas_instance *);
210
211 static struct mrsas_function_template mrsas_function_template_ppc = {
212 .read_fw_status_reg = read_fw_status_reg_ppc,
213 .issue_cmd = issue_cmd_ppc,
214 .issue_cmd_in_sync_mode = issue_cmd_in_sync_mode_ppc,
215 .issue_cmd_in_poll_mode = issue_cmd_in_poll_mode_ppc,
216 .enable_intr = enable_intr_ppc,
217 .disable_intr = disable_intr_ppc,
218 .intr_ack = intr_ack_ppc,
219 .init_adapter = mrsas_init_adapter_ppc
220 };
221
222
223 static struct mrsas_function_template mrsas_function_template_fusion = {
224 .read_fw_status_reg = tbolt_read_fw_status_reg,
225 .issue_cmd = tbolt_issue_cmd,
226 .issue_cmd_in_sync_mode = tbolt_issue_cmd_in_sync_mode,
227 .issue_cmd_in_poll_mode = tbolt_issue_cmd_in_poll_mode,
228 .enable_intr = tbolt_enable_intr,
229 .disable_intr = tbolt_disable_intr,
230 .intr_ack = tbolt_intr_ack,
231 .init_adapter = mrsas_init_adapter_tbolt
232 };
233
234
235 ddi_dma_attr_t mrsas_generic_dma_attr = {
236 DMA_ATTR_V0, /* dma_attr_version */
237 0, /* low DMA address range */
238 0xFFFFFFFFU, /* high DMA address range */
239 0xFFFFFFFFU, /* DMA counter register */
240 8, /* DMA address alignment */
241 0x07, /* DMA burstsizes */
242 1, /* min DMA size */
243 0xFFFFFFFFU, /* max DMA size */
244 0xFFFFFFFFU, /* segment boundary */
245 MRSAS_MAX_SGE_CNT, /* dma_attr_sglen */
246 512, /* granularity of device */
247 0 /* bus specific DMA flags */
248 };
249
250 int32_t mrsas_max_cap_maxxfer = 0x1000000;
251
252 /*
253 * Fix for: Thunderbolt controller IO timeout when IO write size is 1MEG,
254 * Limit size to 256K
255 */
256 uint32_t mrsas_tbolt_max_cap_maxxfer = (512 * 512);
257
258 /*
259 * cb_ops contains base level routines
260 */
261 static struct cb_ops mrsas_cb_ops = {
262 mrsas_open, /* open */
263 mrsas_close, /* close */
264 nodev, /* strategy */
265 nodev, /* print */
266 nodev, /* dump */
267 nodev, /* read */
268 nodev, /* write */
269 mrsas_ioctl, /* ioctl */
270 nodev, /* devmap */
271 nodev, /* mmap */
272 nodev, /* segmap */
273 nochpoll, /* poll */
274 nodev, /* cb_prop_op */
275 0, /* streamtab */
276 D_NEW | D_HOTPLUG, /* cb_flag */
277 CB_REV, /* cb_rev */
278 nodev, /* cb_aread */
279 nodev /* cb_awrite */
280 };
281
282 /*
283 * dev_ops contains configuration routines
284 */
285 static struct dev_ops mrsas_ops = {
286 DEVO_REV, /* rev, */
287 0, /* refcnt */
288 mrsas_getinfo, /* getinfo */
289 nulldev, /* identify */
290 nulldev, /* probe */
291 mrsas_attach, /* attach */
292 mrsas_detach, /* detach */
293 #ifdef __sparc
294 mrsas_reset, /* reset */
295 #else /* __sparc */
296 nodev,
297 #endif /* __sparc */
298 &mrsas_cb_ops, /* char/block ops */
299 NULL, /* bus ops */
300 NULL, /* power */
301 #ifdef __sparc
302 ddi_quiesce_not_needed
303 #else /* __sparc */
304 mrsas_quiesce /* quiesce */
305 #endif /* __sparc */
306 };
307
308 static struct modldrv modldrv = {
309 &mod_driverops, /* module type - driver */
310 MRSAS_VERSION,
311 &mrsas_ops, /* driver ops */
312 };
313
314 static struct modlinkage modlinkage = {
315 MODREV_1, /* ml_rev - must be MODREV_1 */
316 &modldrv, /* ml_linkage */
317 NULL /* end of driver linkage */
318 };
319
320 static struct ddi_device_acc_attr endian_attr = {
321 DDI_DEVICE_ATTR_V1,
322 DDI_STRUCTURE_LE_ACC,
323 DDI_STRICTORDER_ACC,
324 DDI_DEFAULT_ACC
325 };
326
327 /* Use the LSI Fast Path for the 2208 (tbolt) commands. */
328 unsigned int enable_fp = 1;
329
330
331 /*
332 * ************************************************************************** *
333 * *
334 * common entry points - for loadable kernel modules *
335 * *
336 * ************************************************************************** *
337 */
338
339 /*
340 * _init - initialize a loadable module
341 * @void
342 *
343 * The driver should perform any one-time resource allocation or data
344 * initialization during driver loading in _init(). For example, the driver
345 * should initialize any mutexes global to the driver in this routine.
346 * The driver should not, however, use _init() to allocate or initialize
347 * anything that has to do with a particular instance of the device.
348 * Per-instance initialization must be done in attach().
349 */
350 int
_init(void)351 _init(void)
352 {
353 int ret;
354
355 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
356
357 ret = ddi_soft_state_init(&mrsas_state,
358 sizeof (struct mrsas_instance), 0);
359
360 if (ret != DDI_SUCCESS) {
361 cmn_err(CE_WARN, "mr_sas: could not init state");
362 return (ret);
363 }
364
365 if ((ret = scsi_hba_init(&modlinkage)) != DDI_SUCCESS) {
366 cmn_err(CE_WARN, "mr_sas: could not init scsi hba");
367 ddi_soft_state_fini(&mrsas_state);
368 return (ret);
369 }
370
371 ret = mod_install(&modlinkage);
372
373 if (ret != DDI_SUCCESS) {
374 cmn_err(CE_WARN, "mr_sas: mod_install failed");
375 scsi_hba_fini(&modlinkage);
376 ddi_soft_state_fini(&mrsas_state);
377 }
378
379 return (ret);
380 }
381
382 /*
383 * _info - returns information about a loadable module.
384 * @void
385 *
386 * _info() is called to return module information. This is a typical entry
387 * point that does predefined role. It simply calls mod_info().
388 */
389 int
_info(struct modinfo * modinfop)390 _info(struct modinfo *modinfop)
391 {
392 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
393
394 return (mod_info(&modlinkage, modinfop));
395 }
396
397 /*
398 * _fini - prepare a loadable module for unloading
399 * @void
400 *
401 * In _fini(), the driver should release any resources that were allocated in
402 * _init(). The driver must remove itself from the system module list.
403 */
404 int
_fini(void)405 _fini(void)
406 {
407 int ret;
408
409 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
410
411 if ((ret = mod_remove(&modlinkage)) != DDI_SUCCESS) {
412 con_log(CL_ANN1,
413 (CE_WARN, "_fini: mod_remove() failed, error 0x%X", ret));
414 return (ret);
415 }
416
417 scsi_hba_fini(&modlinkage);
418 con_log(CL_DLEVEL1, (CE_NOTE, "_fini: scsi_hba_fini() done."));
419
420 ddi_soft_state_fini(&mrsas_state);
421 con_log(CL_DLEVEL1, (CE_NOTE, "_fini: ddi_soft_state_fini() done."));
422
423 return (ret);
424 }
425
426
427 /*
428 * ************************************************************************** *
429 * *
430 * common entry points - for autoconfiguration *
431 * *
432 * ************************************************************************** *
433 */
434 /*
435 * attach - adds a device to the system as part of initialization
436 * @dip:
437 * @cmd:
438 *
439 * The kernel calls a driver's attach() entry point to attach an instance of
440 * a device (for MegaRAID, it is instance of a controller) or to resume
441 * operation for an instance of a device that has been suspended or has been
442 * shut down by the power management framework
443 * The attach() entry point typically includes the following types of
444 * processing:
445 * - allocate a soft-state structure for the device instance (for MegaRAID,
446 * controller instance)
447 * - initialize per-instance mutexes
448 * - initialize condition variables
449 * - register the device's interrupts (for MegaRAID, controller's interrupts)
450 * - map the registers and memory of the device instance (for MegaRAID,
451 * controller instance)
452 * - create minor device nodes for the device instance (for MegaRAID,
453 * controller instance)
454 * - report that the device instance (for MegaRAID, controller instance) has
455 * attached
456 */
457 static int
mrsas_attach(dev_info_t * dip,ddi_attach_cmd_t cmd)458 mrsas_attach(dev_info_t *dip, ddi_attach_cmd_t cmd)
459 {
460 int instance_no;
461 int nregs;
462 int i = 0;
463 uint8_t irq;
464 uint16_t vendor_id;
465 uint16_t device_id;
466 uint16_t subsysvid;
467 uint16_t subsysid;
468 uint16_t command;
469 off_t reglength = 0;
470 int intr_types = 0;
471 char *data;
472
473 scsi_hba_tran_t *tran;
474 ddi_dma_attr_t tran_dma_attr;
475 struct mrsas_instance *instance;
476
477 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
478
479 /* CONSTCOND */
480 ASSERT(NO_COMPETING_THREADS);
481
482 instance_no = ddi_get_instance(dip);
483
484 /*
485 * check to see whether this device is in a DMA-capable slot.
486 */
487 if (ddi_slaveonly(dip) == DDI_SUCCESS) {
488 dev_err(dip, CE_WARN, "Device in slave-only slot, unused");
489 return (DDI_FAILURE);
490 }
491
492 switch (cmd) {
493 case DDI_ATTACH:
494 /* allocate the soft state for the instance */
495 if (ddi_soft_state_zalloc(mrsas_state, instance_no)
496 != DDI_SUCCESS) {
497 dev_err(dip, CE_WARN, "Failed to allocate soft state");
498 return (DDI_FAILURE);
499 }
500
501 instance = (struct mrsas_instance *)ddi_get_soft_state
502 (mrsas_state, instance_no);
503
504 if (instance == NULL) {
505 dev_err(dip, CE_WARN, "Bad soft state");
506 ddi_soft_state_free(mrsas_state, instance_no);
507 return (DDI_FAILURE);
508 }
509
510 instance->unroll.softs = 1;
511
512 /* Setup the PCI configuration space handles */
513 if (pci_config_setup(dip, &instance->pci_handle) !=
514 DDI_SUCCESS) {
515 dev_err(dip, CE_WARN, "pci config setup failed");
516
517 ddi_soft_state_free(mrsas_state, instance_no);
518 return (DDI_FAILURE);
519 }
520
521 if (ddi_dev_nregs(dip, &nregs) != DDI_SUCCESS) {
522 dev_err(dip, CE_WARN, "Failed to get registers");
523
524 pci_config_teardown(&instance->pci_handle);
525 ddi_soft_state_free(mrsas_state, instance_no);
526 return (DDI_FAILURE);
527 }
528
529 vendor_id = pci_config_get16(instance->pci_handle,
530 PCI_CONF_VENID);
531 device_id = pci_config_get16(instance->pci_handle,
532 PCI_CONF_DEVID);
533
534 subsysvid = pci_config_get16(instance->pci_handle,
535 PCI_CONF_SUBVENID);
536 subsysid = pci_config_get16(instance->pci_handle,
537 PCI_CONF_SUBSYSID);
538
539 pci_config_put16(instance->pci_handle, PCI_CONF_COMM,
540 (pci_config_get16(instance->pci_handle,
541 PCI_CONF_COMM) | PCI_COMM_ME));
542 irq = pci_config_get8(instance->pci_handle,
543 PCI_CONF_ILINE);
544
545 dev_err(dip, CE_CONT,
546 "?0x%x:0x%x 0x%x:0x%x, irq:%d drv-ver:%s\n",
547 vendor_id, device_id, subsysvid,
548 subsysid, irq, MRSAS_VERSION);
549
550 /* enable bus-mastering */
551 command = pci_config_get16(instance->pci_handle,
552 PCI_CONF_COMM);
553
554 if (!(command & PCI_COMM_ME)) {
555 command |= PCI_COMM_ME;
556
557 pci_config_put16(instance->pci_handle,
558 PCI_CONF_COMM, command);
559
560 con_log(CL_ANN, (CE_CONT, "mr_sas%d: "
561 "enable bus-mastering", instance_no));
562 } else {
563 con_log(CL_DLEVEL1, (CE_CONT, "mr_sas%d: "
564 "bus-mastering already set", instance_no));
565 }
566
567 /* initialize function pointers */
568 switch (device_id) {
569 case PCI_DEVICE_ID_LSI_INVADER:
570 case PCI_DEVICE_ID_LSI_FURY:
571 case PCI_DEVICE_ID_LSI_INTRUDER:
572 case PCI_DEVICE_ID_LSI_INTRUDER_24:
573 case PCI_DEVICE_ID_LSI_CUTLASS_52:
574 case PCI_DEVICE_ID_LSI_CUTLASS_53:
575 dev_err(dip, CE_CONT, "?Gen3 device detected\n");
576 instance->gen3 = 1;
577 /* FALLTHROUGH */
578 case PCI_DEVICE_ID_LSI_TBOLT:
579 dev_err(dip, CE_CONT, "?TBOLT device detected\n");
580
581 instance->func_ptr =
582 &mrsas_function_template_fusion;
583 instance->tbolt = 1;
584 break;
585
586 case PCI_DEVICE_ID_LSI_SKINNY:
587 case PCI_DEVICE_ID_LSI_SKINNY_NEW:
588 /*
589 * FALLTHRU to PPC-style functions, but mark this
590 * instance as Skinny, because the register set is
591 * slightly different (See WR_IB_PICK_QPORT), and
592 * certain other features are available to a Skinny
593 * HBA.
594 */
595 dev_err(dip, CE_CONT, "?Skinny device detected\n");
596 instance->skinny = 1;
597 /* FALLTHRU */
598
599 case PCI_DEVICE_ID_LSI_2108VDE:
600 case PCI_DEVICE_ID_LSI_2108V:
601 dev_err(dip, CE_CONT,
602 "?2108 Liberator device detected\n");
603
604 instance->func_ptr =
605 &mrsas_function_template_ppc;
606 break;
607
608 default:
609 dev_err(dip, CE_WARN, "Invalid device detected");
610
611 pci_config_teardown(&instance->pci_handle);
612 ddi_soft_state_free(mrsas_state, instance_no);
613 return (DDI_FAILURE);
614 }
615
616 instance->baseaddress = pci_config_get32(
617 instance->pci_handle, PCI_CONF_BASE0);
618 instance->baseaddress &= 0x0fffc;
619
620 instance->dip = dip;
621 instance->vendor_id = vendor_id;
622 instance->device_id = device_id;
623 instance->subsysvid = subsysvid;
624 instance->subsysid = subsysid;
625 instance->instance = instance_no;
626
627 /* Initialize FMA */
628 instance->fm_capabilities = ddi_prop_get_int(
629 DDI_DEV_T_ANY, instance->dip, DDI_PROP_DONTPASS,
630 "fm-capable", DDI_FM_EREPORT_CAPABLE |
631 DDI_FM_ACCCHK_CAPABLE | DDI_FM_DMACHK_CAPABLE
632 | DDI_FM_ERRCB_CAPABLE);
633
634 mrsas_fm_init(instance);
635
636 /* Setup register map */
637 if ((ddi_dev_regsize(instance->dip,
638 REGISTER_SET_IO_2108, ®length) != DDI_SUCCESS) ||
639 reglength < MINIMUM_MFI_MEM_SZ) {
640 goto fail_attach;
641 }
642 if (reglength > DEFAULT_MFI_MEM_SZ) {
643 reglength = DEFAULT_MFI_MEM_SZ;
644 con_log(CL_DLEVEL1, (CE_NOTE,
645 "mr_sas: register length to map is 0x%lx bytes",
646 reglength));
647 }
648 if (ddi_regs_map_setup(instance->dip,
649 REGISTER_SET_IO_2108, &instance->regmap, 0,
650 reglength, &endian_attr, &instance->regmap_handle)
651 != DDI_SUCCESS) {
652 dev_err(dip, CE_WARN, "couldn't map control registers");
653 goto fail_attach;
654 }
655
656 instance->unroll.regs = 1;
657
658 /*
659 * Disable Interrupt Now.
660 * Setup Software interrupt
661 */
662 instance->func_ptr->disable_intr(instance);
663
664 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, dip, 0,
665 "mrsas-enable-msi", &data) == DDI_SUCCESS) {
666 if (strncmp(data, "no", 3) == 0) {
667 msi_enable = 0;
668 con_log(CL_ANN1, (CE_WARN,
669 "msi_enable = %d disabled", msi_enable));
670 }
671 ddi_prop_free(data);
672 }
673
674 dev_err(dip, CE_CONT, "?msi_enable = %d\n", msi_enable);
675
676 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, dip, 0,
677 "mrsas-enable-fp", &data) == DDI_SUCCESS) {
678 if (strncmp(data, "no", 3) == 0) {
679 enable_fp = 0;
680 dev_err(dip, CE_NOTE,
681 "enable_fp = %d, Fast-Path disabled.\n",
682 enable_fp);
683 }
684
685 ddi_prop_free(data);
686 }
687
688 dev_err(dip, CE_CONT, "?enable_fp = %d\n", enable_fp);
689
690 /* Check for all supported interrupt types */
691 if (ddi_intr_get_supported_types(
692 dip, &intr_types) != DDI_SUCCESS) {
693 dev_err(dip, CE_WARN,
694 "ddi_intr_get_supported_types() failed");
695 goto fail_attach;
696 }
697
698 con_log(CL_DLEVEL1, (CE_NOTE,
699 "ddi_intr_get_supported_types() ret: 0x%x", intr_types));
700
701 /* Initialize and Setup Interrupt handler */
702 if (msi_enable && (intr_types & DDI_INTR_TYPE_MSIX)) {
703 if (mrsas_add_intrs(instance, DDI_INTR_TYPE_MSIX) !=
704 DDI_SUCCESS) {
705 dev_err(dip, CE_WARN,
706 "MSIX interrupt query failed");
707 goto fail_attach;
708 }
709 instance->intr_type = DDI_INTR_TYPE_MSIX;
710 } else if (msi_enable && (intr_types & DDI_INTR_TYPE_MSI)) {
711 if (mrsas_add_intrs(instance, DDI_INTR_TYPE_MSI) !=
712 DDI_SUCCESS) {
713 dev_err(dip, CE_WARN,
714 "MSI interrupt query failed");
715 goto fail_attach;
716 }
717 instance->intr_type = DDI_INTR_TYPE_MSI;
718 } else if (intr_types & DDI_INTR_TYPE_FIXED) {
719 msi_enable = 0;
720 if (mrsas_add_intrs(instance, DDI_INTR_TYPE_FIXED) !=
721 DDI_SUCCESS) {
722 dev_err(dip, CE_WARN,
723 "FIXED interrupt query failed");
724 goto fail_attach;
725 }
726 instance->intr_type = DDI_INTR_TYPE_FIXED;
727 } else {
728 dev_err(dip, CE_WARN, "Device cannot "
729 "suppport either FIXED or MSI/X "
730 "interrupts");
731 goto fail_attach;
732 }
733
734 instance->unroll.intr = 1;
735
736 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, dip, 0,
737 "mrsas-enable-ctio", &data) == DDI_SUCCESS) {
738 if (strncmp(data, "no", 3) == 0) {
739 ctio_enable = 0;
740 con_log(CL_ANN1, (CE_WARN,
741 "ctio_enable = %d disabled", ctio_enable));
742 }
743 ddi_prop_free(data);
744 }
745
746 dev_err(dip, CE_CONT, "?ctio_enable = %d\n", ctio_enable);
747
748 /* setup the mfi based low level driver */
749 if (mrsas_init_adapter(instance) != DDI_SUCCESS) {
750 dev_err(dip, CE_WARN,
751 "could not initialize the low level driver");
752
753 goto fail_attach;
754 }
755
756 /* Initialize all Mutex */
757 INIT_LIST_HEAD(&instance->completed_pool_list);
758 mutex_init(&instance->completed_pool_mtx, NULL,
759 MUTEX_DRIVER, DDI_INTR_PRI(instance->intr_pri));
760
761 mutex_init(&instance->sync_map_mtx, NULL,
762 MUTEX_DRIVER, DDI_INTR_PRI(instance->intr_pri));
763
764 mutex_init(&instance->app_cmd_pool_mtx, NULL,
765 MUTEX_DRIVER, DDI_INTR_PRI(instance->intr_pri));
766
767 mutex_init(&instance->config_dev_mtx, NULL,
768 MUTEX_DRIVER, DDI_INTR_PRI(instance->intr_pri));
769
770 mutex_init(&instance->cmd_pend_mtx, NULL,
771 MUTEX_DRIVER, DDI_INTR_PRI(instance->intr_pri));
772
773 mutex_init(&instance->ocr_flags_mtx, NULL,
774 MUTEX_DRIVER, DDI_INTR_PRI(instance->intr_pri));
775
776 mutex_init(&instance->int_cmd_mtx, NULL,
777 MUTEX_DRIVER, DDI_INTR_PRI(instance->intr_pri));
778 cv_init(&instance->int_cmd_cv, NULL, CV_DRIVER, NULL);
779
780 mutex_init(&instance->cmd_pool_mtx, NULL,
781 MUTEX_DRIVER, DDI_INTR_PRI(instance->intr_pri));
782
783 mutex_init(&instance->reg_write_mtx, NULL,
784 MUTEX_DRIVER, DDI_INTR_PRI(instance->intr_pri));
785
786 if (instance->tbolt) {
787 mutex_init(&instance->cmd_app_pool_mtx, NULL,
788 MUTEX_DRIVER, DDI_INTR_PRI(instance->intr_pri));
789
790 mutex_init(&instance->chip_mtx, NULL,
791 MUTEX_DRIVER, DDI_INTR_PRI(instance->intr_pri));
792
793 }
794
795 instance->unroll.mutexs = 1;
796
797 instance->timeout_id = (timeout_id_t)-1;
798
799 /* Register our soft-isr for highlevel interrupts. */
800 instance->isr_level = instance->intr_pri;
801 if (!(instance->tbolt)) {
802 if (instance->isr_level == HIGH_LEVEL_INTR) {
803 if (ddi_add_softintr(dip,
804 DDI_SOFTINT_HIGH,
805 &instance->soft_intr_id, NULL, NULL,
806 mrsas_softintr, (caddr_t)instance) !=
807 DDI_SUCCESS) {
808 dev_err(dip, CE_WARN,
809 "Software ISR did not register");
810
811 goto fail_attach;
812 }
813
814 instance->unroll.soft_isr = 1;
815
816 }
817 }
818
819 instance->softint_running = 0;
820
821 /* Allocate a transport structure */
822 tran = scsi_hba_tran_alloc(dip, SCSI_HBA_CANSLEEP);
823
824 if (tran == NULL) {
825 dev_err(dip, CE_WARN,
826 "scsi_hba_tran_alloc failed");
827 goto fail_attach;
828 }
829
830 instance->tran = tran;
831 instance->unroll.tran = 1;
832
833 tran->tran_hba_private = instance;
834 tran->tran_tgt_init = mrsas_tran_tgt_init;
835 tran->tran_tgt_probe = scsi_hba_probe;
836 tran->tran_tgt_free = mrsas_tran_tgt_free;
837 tran->tran_init_pkt = mrsas_tran_init_pkt;
838 if (instance->tbolt)
839 tran->tran_start = mrsas_tbolt_tran_start;
840 else
841 tran->tran_start = mrsas_tran_start;
842 tran->tran_abort = mrsas_tran_abort;
843 tran->tran_reset = mrsas_tran_reset;
844 tran->tran_getcap = mrsas_tran_getcap;
845 tran->tran_setcap = mrsas_tran_setcap;
846 tran->tran_destroy_pkt = mrsas_tran_destroy_pkt;
847 tran->tran_dmafree = mrsas_tran_dmafree;
848 tran->tran_sync_pkt = mrsas_tran_sync_pkt;
849 tran->tran_quiesce = mrsas_tran_quiesce;
850 tran->tran_unquiesce = mrsas_tran_unquiesce;
851 tran->tran_bus_config = mrsas_tran_bus_config;
852
853 if (mrsas_relaxed_ordering)
854 mrsas_generic_dma_attr.dma_attr_flags |=
855 DDI_DMA_RELAXED_ORDERING;
856
857
858 tran_dma_attr = mrsas_generic_dma_attr;
859 tran_dma_attr.dma_attr_sgllen = instance->max_num_sge;
860
861 /* Attach this instance of the hba */
862 if (scsi_hba_attach_setup(dip, &tran_dma_attr, tran, 0)
863 != DDI_SUCCESS) {
864 dev_err(dip, CE_WARN,
865 "scsi_hba_attach failed");
866
867 goto fail_attach;
868 }
869 instance->unroll.tranSetup = 1;
870 con_log(CL_ANN1,
871 (CE_CONT, "scsi_hba_attach_setup() done."));
872
873 /* create devctl node for cfgadm command */
874 if (ddi_create_minor_node(dip, "devctl",
875 S_IFCHR, INST2DEVCTL(instance_no),
876 DDI_NT_SCSI_NEXUS, 0) == DDI_FAILURE) {
877 dev_err(dip, CE_WARN, "failed to create devctl node.");
878
879 goto fail_attach;
880 }
881
882 instance->unroll.devctl = 1;
883
884 /* create scsi node for cfgadm command */
885 if (ddi_create_minor_node(dip, "scsi", S_IFCHR,
886 INST2SCSI(instance_no), DDI_NT_SCSI_ATTACHMENT_POINT, 0) ==
887 DDI_FAILURE) {
888 dev_err(dip, CE_WARN, "failed to create scsi node.");
889
890 goto fail_attach;
891 }
892
893 instance->unroll.scsictl = 1;
894
895 (void) snprintf(instance->iocnode, sizeof (instance->iocnode),
896 "%d:lsirdctl", instance_no);
897
898 /*
899 * Create a node for applications
900 * for issuing ioctl to the driver.
901 */
902 if (ddi_create_minor_node(dip, instance->iocnode,
903 S_IFCHR, INST2LSIRDCTL(instance_no), DDI_PSEUDO, 0) ==
904 DDI_FAILURE) {
905 dev_err(dip, CE_WARN, "failed to create ioctl node.");
906
907 goto fail_attach;
908 }
909
910 instance->unroll.ioctl = 1;
911
912 /* Create a taskq to handle dr events */
913 if ((instance->taskq = ddi_taskq_create(dip,
914 "mrsas_dr_taskq", 1, TASKQ_DEFAULTPRI, 0)) == NULL) {
915 dev_err(dip, CE_WARN, "failed to create taskq.");
916 instance->taskq = NULL;
917 goto fail_attach;
918 }
919 instance->unroll.taskq = 1;
920 con_log(CL_ANN1, (CE_CONT, "ddi_taskq_create() done."));
921
922 /* enable interrupt */
923 instance->func_ptr->enable_intr(instance);
924
925 /* initiate AEN */
926 if (start_mfi_aen(instance)) {
927 dev_err(dip, CE_WARN, "failed to initiate AEN.");
928 goto fail_attach;
929 }
930 instance->unroll.aenPend = 1;
931 con_log(CL_ANN1,
932 (CE_CONT, "AEN started for instance %d.", instance_no));
933
934 /* Finally! We are on the air. */
935 ddi_report_dev(dip);
936
937 /* FMA handle checking. */
938 if (mrsas_check_acc_handle(instance->regmap_handle) !=
939 DDI_SUCCESS) {
940 goto fail_attach;
941 }
942 if (mrsas_check_acc_handle(instance->pci_handle) !=
943 DDI_SUCCESS) {
944 goto fail_attach;
945 }
946
947 instance->mr_ld_list =
948 kmem_zalloc(MRDRV_MAX_LD * sizeof (struct mrsas_ld),
949 KM_SLEEP);
950 instance->unroll.ldlist_buff = 1;
951
952 if (instance->tbolt || instance->skinny) {
953 instance->mr_tbolt_pd_max = MRSAS_TBOLT_PD_TGT_MAX;
954 instance->mr_tbolt_pd_list =
955 kmem_zalloc(MRSAS_TBOLT_GET_PD_MAX(instance) *
956 sizeof (struct mrsas_tbolt_pd), KM_SLEEP);
957 ASSERT(instance->mr_tbolt_pd_list);
958 for (i = 0; i < instance->mr_tbolt_pd_max; i++) {
959 instance->mr_tbolt_pd_list[i].lun_type =
960 MRSAS_TBOLT_PD_LUN;
961 instance->mr_tbolt_pd_list[i].dev_id =
962 (uint8_t)i;
963 }
964
965 instance->unroll.pdlist_buff = 1;
966 }
967 break;
968 case DDI_PM_RESUME:
969 con_log(CL_ANN, (CE_NOTE, "mr_sas: DDI_PM_RESUME"));
970 break;
971 case DDI_RESUME:
972 con_log(CL_ANN, (CE_NOTE, "mr_sas: DDI_RESUME"));
973 break;
974 default:
975 con_log(CL_ANN,
976 (CE_WARN, "mr_sas: invalid attach cmd=%x", cmd));
977 return (DDI_FAILURE);
978 }
979
980
981 con_log(CL_DLEVEL1,
982 (CE_NOTE, "mrsas_attach() return SUCCESS instance_num %d",
983 instance_no));
984 return (DDI_SUCCESS);
985
986 fail_attach:
987
988 mrsas_undo_resources(dip, instance);
989
990 mrsas_fm_ereport(instance, DDI_FM_DEVICE_NO_RESPONSE);
991 ddi_fm_service_impact(instance->dip, DDI_SERVICE_LOST);
992
993 mrsas_fm_fini(instance);
994
995 pci_config_teardown(&instance->pci_handle);
996 ddi_soft_state_free(mrsas_state, instance_no);
997
998 return (DDI_FAILURE);
999 }
1000
1001 /*
1002 * getinfo - gets device information
1003 * @dip:
1004 * @cmd:
1005 * @arg:
1006 * @resultp:
1007 *
1008 * The system calls getinfo() to obtain configuration information that only
1009 * the driver knows. The mapping of minor numbers to device instance is
1010 * entirely under the control of the driver. The system sometimes needs to ask
1011 * the driver which device a particular dev_t represents.
1012 * Given the device number return the devinfo pointer from the scsi_device
1013 * structure.
1014 */
1015 /*ARGSUSED*/
1016 static int
mrsas_getinfo(dev_info_t * dip,ddi_info_cmd_t cmd,void * arg,void ** resultp)1017 mrsas_getinfo(dev_info_t *dip, ddi_info_cmd_t cmd, void *arg, void **resultp)
1018 {
1019 int rval;
1020 int mrsas_minor = getminor((dev_t)arg);
1021
1022 struct mrsas_instance *instance;
1023
1024 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
1025
1026 switch (cmd) {
1027 case DDI_INFO_DEVT2DEVINFO:
1028 instance = (struct mrsas_instance *)
1029 ddi_get_soft_state(mrsas_state,
1030 MINOR2INST(mrsas_minor));
1031
1032 if (instance == NULL) {
1033 *resultp = NULL;
1034 rval = DDI_FAILURE;
1035 } else {
1036 *resultp = instance->dip;
1037 rval = DDI_SUCCESS;
1038 }
1039 break;
1040 case DDI_INFO_DEVT2INSTANCE:
1041 *resultp = (void *)(intptr_t)
1042 (MINOR2INST(getminor((dev_t)arg)));
1043 rval = DDI_SUCCESS;
1044 break;
1045 default:
1046 *resultp = NULL;
1047 rval = DDI_FAILURE;
1048 }
1049
1050 return (rval);
1051 }
1052
1053 /*
1054 * detach - detaches a device from the system
1055 * @dip: pointer to the device's dev_info structure
1056 * @cmd: type of detach
1057 *
1058 * A driver's detach() entry point is called to detach an instance of a device
1059 * that is bound to the driver. The entry point is called with the instance of
1060 * the device node to be detached and with DDI_DETACH, which is specified as
1061 * the cmd argument to the entry point.
1062 * This routine is called during driver unload. We free all the allocated
1063 * resources and call the corresponding LLD so that it can also release all
1064 * its resources.
1065 */
1066 static int
mrsas_detach(dev_info_t * dip,ddi_detach_cmd_t cmd)1067 mrsas_detach(dev_info_t *dip, ddi_detach_cmd_t cmd)
1068 {
1069 int instance_no;
1070
1071 struct mrsas_instance *instance;
1072
1073 con_log(CL_ANN, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
1074
1075
1076 /* CONSTCOND */
1077 ASSERT(NO_COMPETING_THREADS);
1078
1079 instance_no = ddi_get_instance(dip);
1080
1081 instance = (struct mrsas_instance *)ddi_get_soft_state(mrsas_state,
1082 instance_no);
1083
1084 if (!instance) {
1085 dev_err(dip, CE_WARN, "could not get instance in detach");
1086
1087 return (DDI_FAILURE);
1088 }
1089
1090 switch (cmd) {
1091 case DDI_DETACH:
1092 con_log(CL_ANN, (CE_NOTE,
1093 "mrsas_detach: DDI_DETACH"));
1094
1095 mutex_enter(&instance->config_dev_mtx);
1096 if (instance->timeout_id != (timeout_id_t)-1) {
1097 mutex_exit(&instance->config_dev_mtx);
1098 (void) untimeout(instance->timeout_id);
1099 instance->timeout_id = (timeout_id_t)-1;
1100 mutex_enter(&instance->config_dev_mtx);
1101 instance->unroll.timer = 0;
1102 }
1103 mutex_exit(&instance->config_dev_mtx);
1104
1105 if (instance->unroll.tranSetup == 1) {
1106 if (scsi_hba_detach(dip) != DDI_SUCCESS) {
1107 dev_err(dip, CE_WARN,
1108 "failed to detach");
1109 return (DDI_FAILURE);
1110 }
1111 instance->unroll.tranSetup = 0;
1112 con_log(CL_ANN1,
1113 (CE_CONT, "scsi_hba_dettach() done."));
1114 }
1115
1116 flush_cache(instance);
1117
1118 mrsas_undo_resources(dip, instance);
1119
1120 mrsas_fm_fini(instance);
1121
1122 pci_config_teardown(&instance->pci_handle);
1123 ddi_soft_state_free(mrsas_state, instance_no);
1124 break;
1125
1126 case DDI_PM_SUSPEND:
1127 con_log(CL_ANN, (CE_NOTE,
1128 "mrsas_detach: DDI_PM_SUSPEND"));
1129
1130 break;
1131 case DDI_SUSPEND:
1132 con_log(CL_ANN, (CE_NOTE,
1133 "mrsas_detach: DDI_SUSPEND"));
1134
1135 break;
1136 default:
1137 con_log(CL_ANN, (CE_WARN,
1138 "invalid detach command:0x%x", cmd));
1139 return (DDI_FAILURE);
1140 }
1141
1142 return (DDI_SUCCESS);
1143 }
1144
1145
1146 static void
mrsas_undo_resources(dev_info_t * dip,struct mrsas_instance * instance)1147 mrsas_undo_resources(dev_info_t *dip, struct mrsas_instance *instance)
1148 {
1149 con_log(CL_ANN, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
1150
1151 if (instance->unroll.ioctl == 1) {
1152 ddi_remove_minor_node(dip, instance->iocnode);
1153 instance->unroll.ioctl = 0;
1154 }
1155
1156 if (instance->unroll.scsictl == 1) {
1157 ddi_remove_minor_node(dip, "scsi");
1158 instance->unroll.scsictl = 0;
1159 }
1160
1161 if (instance->unroll.devctl == 1) {
1162 ddi_remove_minor_node(dip, "devctl");
1163 instance->unroll.devctl = 0;
1164 }
1165
1166 if (instance->unroll.tranSetup == 1) {
1167 if (scsi_hba_detach(dip) != DDI_SUCCESS) {
1168 dev_err(dip, CE_WARN, "failed to detach");
1169 return; /* DDI_FAILURE */
1170 }
1171 instance->unroll.tranSetup = 0;
1172 con_log(CL_ANN1, (CE_CONT, "scsi_hba_dettach() done."));
1173 }
1174
1175 if (instance->unroll.tran == 1) {
1176 scsi_hba_tran_free(instance->tran);
1177 instance->unroll.tran = 0;
1178 con_log(CL_ANN1, (CE_CONT, "scsi_hba_tran_free() done."));
1179 }
1180
1181 if (instance->unroll.syncCmd == 1) {
1182 if (instance->tbolt) {
1183 if (abort_syncmap_cmd(instance,
1184 instance->map_update_cmd)) {
1185 dev_err(dip, CE_WARN, "mrsas_detach: "
1186 "failed to abort previous syncmap command");
1187 }
1188
1189 instance->unroll.syncCmd = 0;
1190 con_log(CL_ANN1, (CE_CONT, "sync cmd aborted, done."));
1191 }
1192 }
1193
1194 if (instance->unroll.aenPend == 1) {
1195 if (abort_aen_cmd(instance, instance->aen_cmd))
1196 dev_err(dip, CE_WARN, "mrsas_detach: "
1197 "failed to abort prevous AEN command");
1198
1199 instance->unroll.aenPend = 0;
1200 con_log(CL_ANN1, (CE_CONT, "aen cmd aborted, done."));
1201 /* This means the controller is fully initialized and running */
1202 /* Shutdown should be a last command to controller. */
1203 /* shutdown_controller(); */
1204 }
1205
1206
1207 if (instance->unroll.timer == 1) {
1208 if (instance->timeout_id != (timeout_id_t)-1) {
1209 (void) untimeout(instance->timeout_id);
1210 instance->timeout_id = (timeout_id_t)-1;
1211
1212 instance->unroll.timer = 0;
1213 }
1214 }
1215
1216 instance->func_ptr->disable_intr(instance);
1217
1218
1219 if (instance->unroll.mutexs == 1) {
1220 mutex_destroy(&instance->cmd_pool_mtx);
1221 mutex_destroy(&instance->app_cmd_pool_mtx);
1222 mutex_destroy(&instance->cmd_pend_mtx);
1223 mutex_destroy(&instance->completed_pool_mtx);
1224 mutex_destroy(&instance->sync_map_mtx);
1225 mutex_destroy(&instance->int_cmd_mtx);
1226 cv_destroy(&instance->int_cmd_cv);
1227 mutex_destroy(&instance->config_dev_mtx);
1228 mutex_destroy(&instance->ocr_flags_mtx);
1229 mutex_destroy(&instance->reg_write_mtx);
1230
1231 if (instance->tbolt) {
1232 mutex_destroy(&instance->cmd_app_pool_mtx);
1233 mutex_destroy(&instance->chip_mtx);
1234 }
1235
1236 instance->unroll.mutexs = 0;
1237 con_log(CL_ANN1, (CE_CONT, "Destroy mutex & cv, done."));
1238 }
1239
1240
1241 if (instance->unroll.soft_isr == 1) {
1242 ddi_remove_softintr(instance->soft_intr_id);
1243 instance->unroll.soft_isr = 0;
1244 }
1245
1246 if (instance->unroll.intr == 1) {
1247 mrsas_rem_intrs(instance);
1248 instance->unroll.intr = 0;
1249 }
1250
1251
1252 if (instance->unroll.taskq == 1) {
1253 if (instance->taskq) {
1254 ddi_taskq_destroy(instance->taskq);
1255 instance->unroll.taskq = 0;
1256 }
1257
1258 }
1259
1260 /*
1261 * free dma memory allocated for
1262 * cmds/frames/queues/driver version etc
1263 */
1264 if (instance->unroll.verBuff == 1) {
1265 (void) mrsas_free_dma_obj(instance, instance->drv_ver_dma_obj);
1266 instance->unroll.verBuff = 0;
1267 }
1268
1269 if (instance->unroll.pdlist_buff == 1) {
1270 if (instance->mr_tbolt_pd_list != NULL) {
1271 kmem_free(instance->mr_tbolt_pd_list,
1272 MRSAS_TBOLT_GET_PD_MAX(instance) *
1273 sizeof (struct mrsas_tbolt_pd));
1274 }
1275
1276 instance->mr_tbolt_pd_list = NULL;
1277 instance->unroll.pdlist_buff = 0;
1278 }
1279
1280 if (instance->unroll.ldlist_buff == 1) {
1281 if (instance->mr_ld_list != NULL) {
1282 kmem_free(instance->mr_ld_list, MRDRV_MAX_LD
1283 * sizeof (struct mrsas_ld));
1284 }
1285
1286 instance->mr_ld_list = NULL;
1287 instance->unroll.ldlist_buff = 0;
1288 }
1289
1290 if (instance->tbolt) {
1291 if (instance->unroll.alloc_space_mpi2 == 1) {
1292 free_space_for_mpi2(instance);
1293 instance->unroll.alloc_space_mpi2 = 0;
1294 }
1295 } else {
1296 if (instance->unroll.alloc_space_mfi == 1) {
1297 free_space_for_mfi(instance);
1298 instance->unroll.alloc_space_mfi = 0;
1299 }
1300 }
1301
1302 if (instance->unroll.regs == 1) {
1303 ddi_regs_map_free(&instance->regmap_handle);
1304 instance->unroll.regs = 0;
1305 con_log(CL_ANN1, (CE_CONT, "ddi_regs_map_free() done."));
1306 }
1307 }
1308
1309
1310
1311 /*
1312 * ************************************************************************** *
1313 * *
1314 * common entry points - for character driver types *
1315 * *
1316 * ************************************************************************** *
1317 */
1318 /*
1319 * open - gets access to a device
1320 * @dev:
1321 * @openflags:
1322 * @otyp:
1323 * @credp:
1324 *
1325 * Access to a device by one or more application programs is controlled
1326 * through the open() and close() entry points. The primary function of
1327 * open() is to verify that the open request is allowed.
1328 */
1329 static int
mrsas_open(dev_t * dev,int openflags,int otyp,cred_t * credp)1330 mrsas_open(dev_t *dev, int openflags, int otyp, cred_t *credp)
1331 {
1332 int rval = 0;
1333
1334 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
1335
1336 /* Check root permissions */
1337 if (drv_priv(credp) != 0) {
1338 con_log(CL_ANN, (CE_WARN,
1339 "mr_sas: Non-root ioctl access denied!"));
1340 return (EPERM);
1341 }
1342
1343 /* Verify we are being opened as a character device */
1344 if (otyp != OTYP_CHR) {
1345 con_log(CL_ANN, (CE_WARN,
1346 "mr_sas: ioctl node must be a char node"));
1347 return (EINVAL);
1348 }
1349
1350 if (ddi_get_soft_state(mrsas_state, MINOR2INST(getminor(*dev)))
1351 == NULL) {
1352 return (ENXIO);
1353 }
1354
1355 if (scsi_hba_open) {
1356 rval = scsi_hba_open(dev, openflags, otyp, credp);
1357 }
1358
1359 return (rval);
1360 }
1361
1362 /*
1363 * close - gives up access to a device
1364 * @dev:
1365 * @openflags:
1366 * @otyp:
1367 * @credp:
1368 *
1369 * close() should perform any cleanup necessary to finish using the minor
1370 * device, and prepare the device (and driver) to be opened again.
1371 */
1372 static int
mrsas_close(dev_t dev,int openflags,int otyp,cred_t * credp)1373 mrsas_close(dev_t dev, int openflags, int otyp, cred_t *credp)
1374 {
1375 int rval = 0;
1376
1377 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
1378
1379 /* no need for locks! */
1380
1381 if (scsi_hba_close) {
1382 rval = scsi_hba_close(dev, openflags, otyp, credp);
1383 }
1384
1385 return (rval);
1386 }
1387
1388 /*
1389 * ioctl - performs a range of I/O commands for character drivers
1390 * @dev:
1391 * @cmd:
1392 * @arg:
1393 * @mode:
1394 * @credp:
1395 * @rvalp:
1396 *
1397 * ioctl() routine must make sure that user data is copied into or out of the
1398 * kernel address space explicitly using copyin(), copyout(), ddi_copyin(),
1399 * and ddi_copyout(), as appropriate.
1400 * This is a wrapper routine to serialize access to the actual ioctl routine.
1401 * ioctl() should return 0 on success, or the appropriate error number. The
1402 * driver may also set the value returned to the calling process through rvalp.
1403 */
1404
1405 static int
mrsas_ioctl(dev_t dev,int cmd,intptr_t arg,int mode,cred_t * credp,int * rvalp)1406 mrsas_ioctl(dev_t dev, int cmd, intptr_t arg, int mode, cred_t *credp,
1407 int *rvalp)
1408 {
1409 int rval = 0;
1410
1411 struct mrsas_instance *instance;
1412 struct mrsas_ioctl *ioctl;
1413 struct mrsas_aen aen;
1414 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
1415
1416 instance = ddi_get_soft_state(mrsas_state, MINOR2INST(getminor(dev)));
1417
1418 if (instance == NULL) {
1419 /* invalid minor number */
1420 con_log(CL_ANN, (CE_WARN, "mr_sas: adapter not found."));
1421 return (ENXIO);
1422 }
1423
1424 ioctl = (struct mrsas_ioctl *)kmem_zalloc(sizeof (struct mrsas_ioctl),
1425 KM_SLEEP);
1426 ASSERT(ioctl);
1427
1428 switch ((uint_t)cmd) {
1429 case MRSAS_IOCTL_FIRMWARE:
1430 if (ddi_copyin((void *)arg, ioctl,
1431 sizeof (struct mrsas_ioctl), mode)) {
1432 con_log(CL_ANN, (CE_WARN, "mrsas_ioctl: "
1433 "ERROR IOCTL copyin"));
1434 kmem_free(ioctl, sizeof (struct mrsas_ioctl));
1435 return (EFAULT);
1436 }
1437
1438 if (ioctl->control_code == MRSAS_DRIVER_IOCTL_COMMON) {
1439 rval = handle_drv_ioctl(instance, ioctl, mode);
1440 } else {
1441 rval = handle_mfi_ioctl(instance, ioctl, mode);
1442 }
1443
1444 if (ddi_copyout((void *)ioctl, (void *)arg,
1445 (sizeof (struct mrsas_ioctl) - 1), mode)) {
1446 con_log(CL_ANN, (CE_WARN,
1447 "mrsas_ioctl: copy_to_user failed"));
1448 rval = 1;
1449 }
1450
1451 break;
1452 case MRSAS_IOCTL_AEN:
1453 if (ddi_copyin((void *) arg, &aen,
1454 sizeof (struct mrsas_aen), mode)) {
1455 con_log(CL_ANN, (CE_WARN,
1456 "mrsas_ioctl: ERROR AEN copyin"));
1457 kmem_free(ioctl, sizeof (struct mrsas_ioctl));
1458 return (EFAULT);
1459 }
1460
1461 rval = handle_mfi_aen(instance, &aen);
1462
1463 if (ddi_copyout((void *) &aen, (void *)arg,
1464 sizeof (struct mrsas_aen), mode)) {
1465 con_log(CL_ANN, (CE_WARN,
1466 "mrsas_ioctl: copy_to_user failed"));
1467 rval = 1;
1468 }
1469
1470 break;
1471 default:
1472 rval = scsi_hba_ioctl(dev, cmd, arg,
1473 mode, credp, rvalp);
1474
1475 con_log(CL_DLEVEL1, (CE_NOTE, "mrsas_ioctl: "
1476 "scsi_hba_ioctl called, ret = %x.", rval));
1477 }
1478
1479 kmem_free(ioctl, sizeof (struct mrsas_ioctl));
1480 return (rval);
1481 }
1482
1483 /*
1484 * ************************************************************************** *
1485 * *
1486 * common entry points - for block driver types *
1487 * *
1488 * ************************************************************************** *
1489 */
1490 #ifdef __sparc
1491 /*
1492 * reset - TBD
1493 * @dip:
1494 * @cmd:
1495 *
1496 * TBD
1497 */
1498 /*ARGSUSED*/
1499 static int
mrsas_reset(dev_info_t * dip,ddi_reset_cmd_t cmd)1500 mrsas_reset(dev_info_t *dip, ddi_reset_cmd_t cmd)
1501 {
1502 int instance_no;
1503
1504 struct mrsas_instance *instance;
1505
1506 instance_no = ddi_get_instance(dip);
1507 instance = (struct mrsas_instance *)ddi_get_soft_state
1508 (mrsas_state, instance_no);
1509
1510 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
1511
1512 if (!instance) {
1513 con_log(CL_ANN, (CE_WARN, "mr_sas:%d could not get adapter "
1514 "in reset", instance_no));
1515 return (DDI_FAILURE);
1516 }
1517
1518 instance->func_ptr->disable_intr(instance);
1519
1520 con_log(CL_ANN1, (CE_CONT, "flushing cache for instance %d",
1521 instance_no));
1522
1523 flush_cache(instance);
1524
1525 return (DDI_SUCCESS);
1526 }
1527 #else /* __sparc */
1528 /*ARGSUSED*/
1529 static int
mrsas_quiesce(dev_info_t * dip)1530 mrsas_quiesce(dev_info_t *dip)
1531 {
1532 int instance_no;
1533
1534 struct mrsas_instance *instance;
1535
1536 instance_no = ddi_get_instance(dip);
1537 instance = (struct mrsas_instance *)ddi_get_soft_state
1538 (mrsas_state, instance_no);
1539
1540 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
1541
1542 if (!instance) {
1543 con_log(CL_ANN1, (CE_WARN, "mr_sas:%d could not get adapter "
1544 "in quiesce", instance_no));
1545 return (DDI_FAILURE);
1546 }
1547 if (instance->deadadapter || instance->adapterresetinprogress) {
1548 con_log(CL_ANN1, (CE_WARN, "mr_sas:%d adapter is not in "
1549 "healthy state", instance_no));
1550 return (DDI_FAILURE);
1551 }
1552
1553 if (abort_aen_cmd(instance, instance->aen_cmd)) {
1554 con_log(CL_ANN1, (CE_WARN, "mrsas_quiesce: "
1555 "failed to abort prevous AEN command QUIESCE"));
1556 }
1557
1558 if (instance->tbolt) {
1559 if (abort_syncmap_cmd(instance,
1560 instance->map_update_cmd)) {
1561 dev_err(dip, CE_WARN,
1562 "mrsas_detach: failed to abort "
1563 "previous syncmap command");
1564 return (DDI_FAILURE);
1565 }
1566 }
1567
1568 instance->func_ptr->disable_intr(instance);
1569
1570 con_log(CL_ANN1, (CE_CONT, "flushing cache for instance %d",
1571 instance_no));
1572
1573 flush_cache(instance);
1574
1575 if (wait_for_outstanding(instance)) {
1576 con_log(CL_ANN1,
1577 (CE_CONT, "wait_for_outstanding: return FAIL.\n"));
1578 return (DDI_FAILURE);
1579 }
1580 return (DDI_SUCCESS);
1581 }
1582 #endif /* __sparc */
1583
1584 /*
1585 * ************************************************************************** *
1586 * *
1587 * entry points (SCSI HBA) *
1588 * *
1589 * ************************************************************************** *
1590 */
1591 /*
1592 * tran_tgt_init - initialize a target device instance
1593 * @hba_dip:
1594 * @tgt_dip:
1595 * @tran:
1596 * @sd:
1597 *
1598 * The tran_tgt_init() entry point enables the HBA to allocate and initialize
1599 * any per-target resources. tran_tgt_init() also enables the HBA to qualify
1600 * the device's address as valid and supportable for that particular HBA.
1601 * By returning DDI_FAILURE, the instance of the target driver for that device
1602 * is not probed or attached.
1603 */
1604 /*ARGSUSED*/
1605 static int
mrsas_tran_tgt_init(dev_info_t * hba_dip,dev_info_t * tgt_dip,scsi_hba_tran_t * tran,struct scsi_device * sd)1606 mrsas_tran_tgt_init(dev_info_t *hba_dip, dev_info_t *tgt_dip,
1607 scsi_hba_tran_t *tran, struct scsi_device *sd)
1608 {
1609 struct mrsas_instance *instance;
1610 uint16_t tgt = sd->sd_address.a_target;
1611 uint8_t lun = sd->sd_address.a_lun;
1612 dev_info_t *child = NULL;
1613
1614 con_log(CL_DLEVEL2, (CE_NOTE, "mrsas_tgt_init target %d lun %d",
1615 tgt, lun));
1616
1617 instance = ADDR2MR(&sd->sd_address);
1618
1619 if (ndi_dev_is_persistent_node(tgt_dip) == 0) {
1620 /*
1621 * If no persistent node exists, we don't allow .conf node
1622 * to be created.
1623 */
1624 if ((child = mrsas_find_child(instance, tgt, lun)) != NULL) {
1625 con_log(CL_DLEVEL2,
1626 (CE_NOTE, "mrsas_tgt_init find child ="
1627 " %p t = %d l = %d", (void *)child, tgt, lun));
1628 if (ndi_merge_node(tgt_dip, mrsas_name_node) !=
1629 DDI_SUCCESS)
1630 /* Create this .conf node */
1631 return (DDI_SUCCESS);
1632 }
1633 con_log(CL_DLEVEL2, (CE_NOTE, "mrsas_tgt_init in ndi_per "
1634 "DDI_FAILURE t = %d l = %d", tgt, lun));
1635 return (DDI_FAILURE);
1636
1637 }
1638
1639 con_log(CL_DLEVEL2, (CE_NOTE, "mrsas_tgt_init dev_dip %p tgt_dip %p",
1640 (void *)instance->mr_ld_list[tgt].dip, (void *)tgt_dip));
1641
1642 if (tgt < MRDRV_MAX_LD && lun == 0) {
1643 if (instance->mr_ld_list[tgt].dip == NULL &&
1644 strcmp(ddi_driver_name(sd->sd_dev), "sd") == 0) {
1645 mutex_enter(&instance->config_dev_mtx);
1646 instance->mr_ld_list[tgt].dip = tgt_dip;
1647 instance->mr_ld_list[tgt].lun_type = MRSAS_LD_LUN;
1648 instance->mr_ld_list[tgt].flag = MRDRV_TGT_VALID;
1649 mutex_exit(&instance->config_dev_mtx);
1650 }
1651 } else if (instance->tbolt || instance->skinny) {
1652 if (instance->mr_tbolt_pd_list[tgt].dip == NULL) {
1653 mutex_enter(&instance->config_dev_mtx);
1654 instance->mr_tbolt_pd_list[tgt].dip = tgt_dip;
1655 instance->mr_tbolt_pd_list[tgt].flag =
1656 MRDRV_TGT_VALID;
1657 mutex_exit(&instance->config_dev_mtx);
1658 con_log(CL_ANN1, (CE_NOTE, "mrsas_tran_tgt_init:"
1659 "t%xl%x", tgt, lun));
1660 }
1661 }
1662
1663 return (DDI_SUCCESS);
1664 }
1665
1666 /*ARGSUSED*/
1667 static void
mrsas_tran_tgt_free(dev_info_t * hba_dip,dev_info_t * tgt_dip,scsi_hba_tran_t * hba_tran,struct scsi_device * sd)1668 mrsas_tran_tgt_free(dev_info_t *hba_dip, dev_info_t *tgt_dip,
1669 scsi_hba_tran_t *hba_tran, struct scsi_device *sd)
1670 {
1671 struct mrsas_instance *instance;
1672 int tgt = sd->sd_address.a_target;
1673 int lun = sd->sd_address.a_lun;
1674
1675 instance = ADDR2MR(&sd->sd_address);
1676
1677 con_log(CL_DLEVEL2, (CE_NOTE, "tgt_free t = %d l = %d", tgt, lun));
1678
1679 if (tgt < MRDRV_MAX_LD && lun == 0) {
1680 if (instance->mr_ld_list[tgt].dip == tgt_dip) {
1681 mutex_enter(&instance->config_dev_mtx);
1682 instance->mr_ld_list[tgt].dip = NULL;
1683 mutex_exit(&instance->config_dev_mtx);
1684 }
1685 } else if (instance->tbolt || instance->skinny) {
1686 mutex_enter(&instance->config_dev_mtx);
1687 instance->mr_tbolt_pd_list[tgt].dip = NULL;
1688 mutex_exit(&instance->config_dev_mtx);
1689 con_log(CL_ANN1, (CE_NOTE, "tgt_free: Setting dip = NULL"
1690 "for tgt:%x", tgt));
1691 }
1692 }
1693
1694 dev_info_t *
mrsas_find_child(struct mrsas_instance * instance,uint16_t tgt,uint8_t lun)1695 mrsas_find_child(struct mrsas_instance *instance, uint16_t tgt, uint8_t lun)
1696 {
1697 dev_info_t *child = NULL;
1698 char addr[SCSI_MAXNAMELEN];
1699 char tmp[MAXNAMELEN];
1700
1701 (void) snprintf(addr, sizeof (addr), "%x,%x", tgt, lun);
1702 for (child = ddi_get_child(instance->dip); child;
1703 child = ddi_get_next_sibling(child)) {
1704
1705 if (ndi_dev_is_persistent_node(child) == 0) {
1706 continue;
1707 }
1708
1709 if (mrsas_name_node(child, tmp, MAXNAMELEN) !=
1710 DDI_SUCCESS) {
1711 continue;
1712 }
1713
1714 if (strcmp(addr, tmp) == 0) {
1715 break;
1716 }
1717 }
1718 con_log(CL_DLEVEL2, (CE_NOTE, "mrsas_find_child: return child = %p",
1719 (void *)child));
1720 return (child);
1721 }
1722
1723 /*
1724 * mrsas_name_node -
1725 * @dip:
1726 * @name:
1727 * @len:
1728 */
1729 static int
mrsas_name_node(dev_info_t * dip,char * name,int len)1730 mrsas_name_node(dev_info_t *dip, char *name, int len)
1731 {
1732 int tgt, lun;
1733
1734 tgt = ddi_prop_get_int(DDI_DEV_T_ANY, dip,
1735 DDI_PROP_DONTPASS, "target", -1);
1736 con_log(CL_DLEVEL2, (CE_NOTE,
1737 "mrsas_name_node: dip %p tgt %d", (void *)dip, tgt));
1738 if (tgt == -1) {
1739 return (DDI_FAILURE);
1740 }
1741 lun = ddi_prop_get_int(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS,
1742 "lun", -1);
1743 con_log(CL_DLEVEL2,
1744 (CE_NOTE, "mrsas_name_node: tgt %d lun %d", tgt, lun));
1745 if (lun == -1) {
1746 return (DDI_FAILURE);
1747 }
1748 (void) snprintf(name, len, "%x,%x", tgt, lun);
1749 return (DDI_SUCCESS);
1750 }
1751
1752 /*
1753 * tran_init_pkt - allocate & initialize a scsi_pkt structure
1754 * @ap:
1755 * @pkt:
1756 * @bp:
1757 * @cmdlen:
1758 * @statuslen:
1759 * @tgtlen:
1760 * @flags:
1761 * @callback:
1762 *
1763 * The tran_init_pkt() entry point allocates and initializes a scsi_pkt
1764 * structure and DMA resources for a target driver request. The
1765 * tran_init_pkt() entry point is called when the target driver calls the
1766 * SCSA function scsi_init_pkt(). Each call of the tran_init_pkt() entry point
1767 * is a request to perform one or more of three possible services:
1768 * - allocation and initialization of a scsi_pkt structure
1769 * - allocation of DMA resources for data transfer
1770 * - reallocation of DMA resources for the next portion of the data transfer
1771 */
1772 static struct scsi_pkt *
mrsas_tran_init_pkt(struct scsi_address * ap,register struct scsi_pkt * pkt,struct buf * bp,int cmdlen,int statuslen,int tgtlen,int flags,int (* callback)(),caddr_t arg)1773 mrsas_tran_init_pkt(struct scsi_address *ap, register struct scsi_pkt *pkt,
1774 struct buf *bp, int cmdlen, int statuslen, int tgtlen,
1775 int flags, int (*callback)(), caddr_t arg)
1776 {
1777 struct scsa_cmd *acmd;
1778 struct mrsas_instance *instance;
1779 struct scsi_pkt *new_pkt;
1780
1781 con_log(CL_DLEVEL1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
1782
1783 instance = ADDR2MR(ap);
1784
1785 /* step #1 : pkt allocation */
1786 if (pkt == NULL) {
1787 pkt = scsi_hba_pkt_alloc(instance->dip, ap, cmdlen, statuslen,
1788 tgtlen, sizeof (struct scsa_cmd), callback, arg);
1789 if (pkt == NULL) {
1790 return (NULL);
1791 }
1792
1793 acmd = PKT2CMD(pkt);
1794
1795 /*
1796 * Initialize the new pkt - we redundantly initialize
1797 * all the fields for illustrative purposes.
1798 */
1799 acmd->cmd_pkt = pkt;
1800 acmd->cmd_flags = 0;
1801 acmd->cmd_scblen = statuslen;
1802 acmd->cmd_cdblen = cmdlen;
1803 acmd->cmd_dmahandle = NULL;
1804 acmd->cmd_ncookies = 0;
1805 acmd->cmd_cookie = 0;
1806 acmd->cmd_cookiecnt = 0;
1807 acmd->cmd_nwin = 0;
1808
1809 pkt->pkt_address = *ap;
1810 pkt->pkt_comp = (void (*)())NULL;
1811 pkt->pkt_flags = 0;
1812 pkt->pkt_time = 0;
1813 pkt->pkt_resid = 0;
1814 pkt->pkt_state = 0;
1815 pkt->pkt_statistics = 0;
1816 pkt->pkt_reason = 0;
1817 new_pkt = pkt;
1818 } else {
1819 acmd = PKT2CMD(pkt);
1820 new_pkt = NULL;
1821 }
1822
1823 /* step #2 : dma allocation/move */
1824 if (bp && bp->b_bcount != 0) {
1825 if (acmd->cmd_dmahandle == NULL) {
1826 if (mrsas_dma_alloc(instance, pkt, bp, flags,
1827 callback) == DDI_FAILURE) {
1828 if (new_pkt) {
1829 scsi_hba_pkt_free(ap, new_pkt);
1830 }
1831 return ((struct scsi_pkt *)NULL);
1832 }
1833 } else {
1834 if (mrsas_dma_move(instance, pkt, bp) == DDI_FAILURE) {
1835 return ((struct scsi_pkt *)NULL);
1836 }
1837 }
1838 }
1839
1840 return (pkt);
1841 }
1842
1843 /*
1844 * tran_start - transport a SCSI command to the addressed target
1845 * @ap:
1846 * @pkt:
1847 *
1848 * The tran_start() entry point for a SCSI HBA driver is called to transport a
1849 * SCSI command to the addressed target. The SCSI command is described
1850 * entirely within the scsi_pkt structure, which the target driver allocated
1851 * through the HBA driver's tran_init_pkt() entry point. If the command
1852 * involves a data transfer, DMA resources must also have been allocated for
1853 * the scsi_pkt structure.
1854 *
1855 * Return Values :
1856 * TRAN_BUSY - request queue is full, no more free scbs
1857 * TRAN_ACCEPT - pkt has been submitted to the instance
1858 */
1859 static int
mrsas_tran_start(struct scsi_address * ap,register struct scsi_pkt * pkt)1860 mrsas_tran_start(struct scsi_address *ap, register struct scsi_pkt *pkt)
1861 {
1862 uchar_t cmd_done = 0;
1863
1864 struct mrsas_instance *instance = ADDR2MR(ap);
1865 struct mrsas_cmd *cmd;
1866
1867 con_log(CL_DLEVEL1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
1868 if (instance->deadadapter == 1) {
1869 con_log(CL_ANN1, (CE_WARN,
1870 "mrsas_tran_start: return TRAN_FATAL_ERROR "
1871 "for IO, as the HBA doesnt take any more IOs"));
1872 if (pkt) {
1873 pkt->pkt_reason = CMD_DEV_GONE;
1874 pkt->pkt_statistics = STAT_DISCON;
1875 }
1876 return (TRAN_FATAL_ERROR);
1877 }
1878
1879 if (instance->adapterresetinprogress) {
1880 con_log(CL_ANN1, (CE_NOTE, "mrsas_tran_start: Reset flag set, "
1881 "returning mfi_pkt and setting TRAN_BUSY\n"));
1882 return (TRAN_BUSY);
1883 }
1884
1885 con_log(CL_ANN1, (CE_CONT, "chkpnt:%s:%d:SCSI CDB[0]=0x%x time:%x",
1886 __func__, __LINE__, pkt->pkt_cdbp[0], pkt->pkt_time));
1887
1888 pkt->pkt_reason = CMD_CMPLT;
1889 *pkt->pkt_scbp = STATUS_GOOD; /* clear arq scsi_status */
1890
1891 cmd = build_cmd(instance, ap, pkt, &cmd_done);
1892
1893 /*
1894 * Check if the command is already completed by the mrsas_build_cmd()
1895 * routine. In which case the busy_flag would be clear and scb will be
1896 * NULL and appropriate reason provided in pkt_reason field
1897 */
1898 if (cmd_done) {
1899 pkt->pkt_reason = CMD_CMPLT;
1900 pkt->pkt_scbp[0] = STATUS_GOOD;
1901 pkt->pkt_state |= STATE_GOT_BUS | STATE_GOT_TARGET
1902 | STATE_SENT_CMD;
1903 if (((pkt->pkt_flags & FLAG_NOINTR) == 0) && pkt->pkt_comp) {
1904 (*pkt->pkt_comp)(pkt);
1905 }
1906
1907 return (TRAN_ACCEPT);
1908 }
1909
1910 if (cmd == NULL) {
1911 return (TRAN_BUSY);
1912 }
1913
1914 if ((pkt->pkt_flags & FLAG_NOINTR) == 0) {
1915 if (instance->fw_outstanding > instance->max_fw_cmds) {
1916 con_log(CL_ANN, (CE_CONT, "mr_sas:Firmware busy"));
1917 DTRACE_PROBE2(start_tran_err,
1918 uint16_t, instance->fw_outstanding,
1919 uint16_t, instance->max_fw_cmds);
1920 mrsas_return_mfi_pkt(instance, cmd);
1921 return (TRAN_BUSY);
1922 }
1923
1924 /* Synchronize the Cmd frame for the controller */
1925 (void) ddi_dma_sync(cmd->frame_dma_obj.dma_handle, 0, 0,
1926 DDI_DMA_SYNC_FORDEV);
1927 con_log(CL_ANN, (CE_CONT, "issue_cmd_ppc: SCSI CDB[0]=0x%x"
1928 "cmd->index:%x\n", pkt->pkt_cdbp[0], cmd->index));
1929 instance->func_ptr->issue_cmd(cmd, instance);
1930
1931 } else {
1932 struct mrsas_header *hdr = &cmd->frame->hdr;
1933
1934 instance->func_ptr->issue_cmd_in_poll_mode(instance, cmd);
1935
1936 pkt->pkt_reason = CMD_CMPLT;
1937 pkt->pkt_statistics = 0;
1938 pkt->pkt_state |= STATE_XFERRED_DATA | STATE_GOT_STATUS;
1939
1940 switch (ddi_get8(cmd->frame_dma_obj.acc_handle,
1941 &hdr->cmd_status)) {
1942 case MFI_STAT_OK:
1943 pkt->pkt_scbp[0] = STATUS_GOOD;
1944 break;
1945
1946 case MFI_STAT_SCSI_DONE_WITH_ERROR:
1947 con_log(CL_ANN, (CE_CONT,
1948 "mrsas_tran_start: scsi done with error"));
1949 pkt->pkt_reason = CMD_CMPLT;
1950 pkt->pkt_statistics = 0;
1951
1952 ((struct scsi_status *)pkt->pkt_scbp)->sts_chk = 1;
1953 break;
1954
1955 case MFI_STAT_DEVICE_NOT_FOUND:
1956 con_log(CL_ANN, (CE_CONT,
1957 "mrsas_tran_start: device not found error"));
1958 pkt->pkt_reason = CMD_DEV_GONE;
1959 pkt->pkt_statistics = STAT_DISCON;
1960 break;
1961
1962 default:
1963 ((struct scsi_status *)pkt->pkt_scbp)->sts_busy = 1;
1964 }
1965
1966 (void) mrsas_common_check(instance, cmd);
1967 DTRACE_PROBE2(start_nointr_done, uint8_t, hdr->cmd,
1968 uint8_t, hdr->cmd_status);
1969 mrsas_return_mfi_pkt(instance, cmd);
1970
1971 if (pkt->pkt_comp) {
1972 (*pkt->pkt_comp)(pkt);
1973 }
1974
1975 }
1976
1977 return (TRAN_ACCEPT);
1978 }
1979
1980 /*
1981 * tran_abort - Abort any commands that are currently in transport
1982 * @ap:
1983 * @pkt:
1984 *
1985 * The tran_abort() entry point for a SCSI HBA driver is called to abort any
1986 * commands that are currently in transport for a particular target. This entry
1987 * point is called when a target driver calls scsi_abort(). The tran_abort()
1988 * entry point should attempt to abort the command denoted by the pkt
1989 * parameter. If the pkt parameter is NULL, tran_abort() should attempt to
1990 * abort all outstanding commands in the transport layer for the particular
1991 * target or logical unit.
1992 */
1993 /*ARGSUSED*/
1994 static int
mrsas_tran_abort(struct scsi_address * ap,struct scsi_pkt * pkt)1995 mrsas_tran_abort(struct scsi_address *ap, struct scsi_pkt *pkt)
1996 {
1997 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
1998
1999 /* abort command not supported by H/W */
2000
2001 return (DDI_FAILURE);
2002 }
2003
2004 /*
2005 * tran_reset - reset either the SCSI bus or target
2006 * @ap:
2007 * @level:
2008 *
2009 * The tran_reset() entry point for a SCSI HBA driver is called to reset either
2010 * the SCSI bus or a particular SCSI target device. This entry point is called
2011 * when a target driver calls scsi_reset(). The tran_reset() entry point must
2012 * reset the SCSI bus if level is RESET_ALL. If level is RESET_TARGET, just the
2013 * particular target or logical unit must be reset.
2014 */
2015 /*ARGSUSED*/
2016 static int
mrsas_tran_reset(struct scsi_address * ap,int level)2017 mrsas_tran_reset(struct scsi_address *ap, int level)
2018 {
2019 struct mrsas_instance *instance = ADDR2MR(ap);
2020
2021 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
2022
2023 if (wait_for_outstanding(instance)) {
2024 con_log(CL_ANN1,
2025 (CE_CONT, "wait_for_outstanding: return FAIL.\n"));
2026 return (DDI_FAILURE);
2027 } else {
2028 return (DDI_SUCCESS);
2029 }
2030 }
2031
2032 /*
2033 * tran_getcap - get one of a set of SCSA-defined capabilities
2034 * @ap:
2035 * @cap:
2036 * @whom:
2037 *
2038 * The target driver can request the current setting of the capability for a
2039 * particular target by setting the whom parameter to nonzero. A whom value of
2040 * zero indicates a request for the current setting of the general capability
2041 * for the SCSI bus or for adapter hardware. The tran_getcap() should return -1
2042 * for undefined capabilities or the current value of the requested capability.
2043 */
2044 /*ARGSUSED*/
2045 static int
mrsas_tran_getcap(struct scsi_address * ap,char * cap,int whom)2046 mrsas_tran_getcap(struct scsi_address *ap, char *cap, int whom)
2047 {
2048 int rval = 0;
2049
2050 struct mrsas_instance *instance = ADDR2MR(ap);
2051
2052 con_log(CL_DLEVEL2, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
2053
2054 /* we do allow inquiring about capabilities for other targets */
2055 if (cap == NULL) {
2056 return (-1);
2057 }
2058
2059 switch (scsi_hba_lookup_capstr(cap)) {
2060 case SCSI_CAP_DMA_MAX:
2061 if (instance->tbolt) {
2062 /* Limit to 256k max transfer */
2063 rval = mrsas_tbolt_max_cap_maxxfer;
2064 } else {
2065 /* Limit to 16MB max transfer */
2066 rval = mrsas_max_cap_maxxfer;
2067 }
2068 break;
2069 case SCSI_CAP_MSG_OUT:
2070 rval = 1;
2071 break;
2072 case SCSI_CAP_DISCONNECT:
2073 rval = 0;
2074 break;
2075 case SCSI_CAP_SYNCHRONOUS:
2076 rval = 0;
2077 break;
2078 case SCSI_CAP_WIDE_XFER:
2079 rval = 1;
2080 break;
2081 case SCSI_CAP_TAGGED_QING:
2082 rval = 1;
2083 break;
2084 case SCSI_CAP_UNTAGGED_QING:
2085 rval = 1;
2086 break;
2087 case SCSI_CAP_PARITY:
2088 rval = 1;
2089 break;
2090 case SCSI_CAP_INITIATOR_ID:
2091 rval = instance->init_id;
2092 break;
2093 case SCSI_CAP_ARQ:
2094 rval = 1;
2095 break;
2096 case SCSI_CAP_LINKED_CMDS:
2097 rval = 0;
2098 break;
2099 case SCSI_CAP_RESET_NOTIFICATION:
2100 rval = 1;
2101 break;
2102 case SCSI_CAP_GEOMETRY:
2103 rval = -1;
2104
2105 break;
2106 default:
2107 con_log(CL_DLEVEL2, (CE_NOTE, "Default cap coming 0x%x",
2108 scsi_hba_lookup_capstr(cap)));
2109 rval = -1;
2110 break;
2111 }
2112
2113 return (rval);
2114 }
2115
2116 /*
2117 * tran_setcap - set one of a set of SCSA-defined capabilities
2118 * @ap:
2119 * @cap:
2120 * @value:
2121 * @whom:
2122 *
2123 * The target driver might request that the new value be set for a particular
2124 * target by setting the whom parameter to nonzero. A whom value of zero
2125 * means that request is to set the new value for the SCSI bus or for adapter
2126 * hardware in general.
2127 * The tran_setcap() should return the following values as appropriate:
2128 * - -1 for undefined capabilities
2129 * - 0 if the HBA driver cannot set the capability to the requested value
2130 * - 1 if the HBA driver is able to set the capability to the requested value
2131 */
2132 /*ARGSUSED*/
2133 static int
mrsas_tran_setcap(struct scsi_address * ap,char * cap,int value,int whom)2134 mrsas_tran_setcap(struct scsi_address *ap, char *cap, int value, int whom)
2135 {
2136 int rval = 1;
2137
2138 con_log(CL_DLEVEL2, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
2139
2140 /* We don't allow setting capabilities for other targets */
2141 if (cap == NULL || whom == 0) {
2142 return (-1);
2143 }
2144
2145 switch (scsi_hba_lookup_capstr(cap)) {
2146 case SCSI_CAP_DMA_MAX:
2147 case SCSI_CAP_MSG_OUT:
2148 case SCSI_CAP_PARITY:
2149 case SCSI_CAP_LINKED_CMDS:
2150 case SCSI_CAP_RESET_NOTIFICATION:
2151 case SCSI_CAP_DISCONNECT:
2152 case SCSI_CAP_SYNCHRONOUS:
2153 case SCSI_CAP_UNTAGGED_QING:
2154 case SCSI_CAP_WIDE_XFER:
2155 case SCSI_CAP_INITIATOR_ID:
2156 case SCSI_CAP_ARQ:
2157 /*
2158 * None of these are settable via
2159 * the capability interface.
2160 */
2161 break;
2162 case SCSI_CAP_TAGGED_QING:
2163 rval = 1;
2164 break;
2165 case SCSI_CAP_SECTOR_SIZE:
2166 rval = 1;
2167 break;
2168
2169 case SCSI_CAP_TOTAL_SECTORS:
2170 rval = 1;
2171 break;
2172 default:
2173 rval = -1;
2174 break;
2175 }
2176
2177 return (rval);
2178 }
2179
2180 /*
2181 * tran_destroy_pkt - deallocate scsi_pkt structure
2182 * @ap:
2183 * @pkt:
2184 *
2185 * The tran_destroy_pkt() entry point is the HBA driver function that
2186 * deallocates scsi_pkt structures. The tran_destroy_pkt() entry point is
2187 * called when the target driver calls scsi_destroy_pkt(). The
2188 * tran_destroy_pkt() entry point must free any DMA resources that have been
2189 * allocated for the packet. An implicit DMA synchronization occurs if the
2190 * DMA resources are freed and any cached data remains after the completion
2191 * of the transfer.
2192 */
2193 static void
mrsas_tran_destroy_pkt(struct scsi_address * ap,struct scsi_pkt * pkt)2194 mrsas_tran_destroy_pkt(struct scsi_address *ap, struct scsi_pkt *pkt)
2195 {
2196 struct scsa_cmd *acmd = PKT2CMD(pkt);
2197
2198 con_log(CL_DLEVEL2, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
2199
2200 if (acmd->cmd_flags & CFLAG_DMAVALID) {
2201 acmd->cmd_flags &= ~CFLAG_DMAVALID;
2202
2203 (void) ddi_dma_unbind_handle(acmd->cmd_dmahandle);
2204
2205 ddi_dma_free_handle(&acmd->cmd_dmahandle);
2206
2207 acmd->cmd_dmahandle = NULL;
2208 }
2209
2210 /* free the pkt */
2211 scsi_hba_pkt_free(ap, pkt);
2212 }
2213
2214 /*
2215 * tran_dmafree - deallocates DMA resources
2216 * @ap:
2217 * @pkt:
2218 *
2219 * The tran_dmafree() entry point deallocates DMAQ resources that have been
2220 * allocated for a scsi_pkt structure. The tran_dmafree() entry point is
2221 * called when the target driver calls scsi_dmafree(). The tran_dmafree() must
2222 * free only DMA resources allocated for a scsi_pkt structure, not the
2223 * scsi_pkt itself. When DMA resources are freed, a DMA synchronization is
2224 * implicitly performed.
2225 */
2226 /*ARGSUSED*/
2227 static void
mrsas_tran_dmafree(struct scsi_address * ap,struct scsi_pkt * pkt)2228 mrsas_tran_dmafree(struct scsi_address *ap, struct scsi_pkt *pkt)
2229 {
2230 register struct scsa_cmd *acmd = PKT2CMD(pkt);
2231
2232 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
2233
2234 if (acmd->cmd_flags & CFLAG_DMAVALID) {
2235 acmd->cmd_flags &= ~CFLAG_DMAVALID;
2236
2237 (void) ddi_dma_unbind_handle(acmd->cmd_dmahandle);
2238
2239 ddi_dma_free_handle(&acmd->cmd_dmahandle);
2240
2241 acmd->cmd_dmahandle = NULL;
2242 }
2243 }
2244
2245 /*
2246 * tran_sync_pkt - synchronize the DMA object allocated
2247 * @ap:
2248 * @pkt:
2249 *
2250 * The tran_sync_pkt() entry point synchronizes the DMA object allocated for
2251 * the scsi_pkt structure before or after a DMA transfer. The tran_sync_pkt()
2252 * entry point is called when the target driver calls scsi_sync_pkt(). If the
2253 * data transfer direction is a DMA read from device to memory, tran_sync_pkt()
2254 * must synchronize the CPU's view of the data. If the data transfer direction
2255 * is a DMA write from memory to device, tran_sync_pkt() must synchronize the
2256 * device's view of the data.
2257 */
2258 /*ARGSUSED*/
2259 static void
mrsas_tran_sync_pkt(struct scsi_address * ap,struct scsi_pkt * pkt)2260 mrsas_tran_sync_pkt(struct scsi_address *ap, struct scsi_pkt *pkt)
2261 {
2262 register struct scsa_cmd *acmd = PKT2CMD(pkt);
2263
2264 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
2265
2266 if (acmd->cmd_flags & CFLAG_DMAVALID) {
2267 (void) ddi_dma_sync(acmd->cmd_dmahandle, acmd->cmd_dma_offset,
2268 acmd->cmd_dma_len, (acmd->cmd_flags & CFLAG_DMASEND) ?
2269 DDI_DMA_SYNC_FORDEV : DDI_DMA_SYNC_FORCPU);
2270 }
2271 }
2272
2273 /*ARGSUSED*/
2274 static int
mrsas_tran_quiesce(dev_info_t * dip)2275 mrsas_tran_quiesce(dev_info_t *dip)
2276 {
2277 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
2278
2279 return (1);
2280 }
2281
2282 /*ARGSUSED*/
2283 static int
mrsas_tran_unquiesce(dev_info_t * dip)2284 mrsas_tran_unquiesce(dev_info_t *dip)
2285 {
2286 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
2287
2288 return (1);
2289 }
2290
2291
2292 /*
2293 * mrsas_isr(caddr_t, caddr_t)
2294 *
2295 * The Interrupt Service Routine
2296 *
2297 * Collect status for all completed commands and do callback
2298 *
2299 */
2300 static uint_t
mrsas_isr(caddr_t arg1,caddr_t arg2 __unused)2301 mrsas_isr(caddr_t arg1, caddr_t arg2 __unused)
2302 {
2303 struct mrsas_instance *instance = (struct mrsas_instance *)arg1;
2304 int need_softintr;
2305 uint32_t producer;
2306 uint32_t consumer;
2307 uint32_t context;
2308 int retval;
2309
2310 struct mrsas_cmd *cmd;
2311 struct mrsas_header *hdr;
2312 struct scsi_pkt *pkt;
2313
2314 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
2315 ASSERT(instance);
2316 if (instance->tbolt) {
2317 mutex_enter(&instance->chip_mtx);
2318 if ((instance->intr_type == DDI_INTR_TYPE_FIXED) &&
2319 !(instance->func_ptr->intr_ack(instance))) {
2320 mutex_exit(&instance->chip_mtx);
2321 return (DDI_INTR_UNCLAIMED);
2322 }
2323 retval = mr_sas_tbolt_process_outstanding_cmd(instance);
2324 mutex_exit(&instance->chip_mtx);
2325 return (retval);
2326 } else {
2327 if ((instance->intr_type == DDI_INTR_TYPE_FIXED) &&
2328 !instance->func_ptr->intr_ack(instance)) {
2329 return (DDI_INTR_UNCLAIMED);
2330 }
2331 }
2332
2333 (void) ddi_dma_sync(instance->mfi_internal_dma_obj.dma_handle,
2334 0, 0, DDI_DMA_SYNC_FORCPU);
2335
2336 if (mrsas_check_dma_handle(instance->mfi_internal_dma_obj.dma_handle)
2337 != DDI_SUCCESS) {
2338 mrsas_fm_ereport(instance, DDI_FM_DEVICE_NO_RESPONSE);
2339 ddi_fm_service_impact(instance->dip, DDI_SERVICE_LOST);
2340 con_log(CL_ANN1, (CE_WARN,
2341 "mr_sas_isr(): FMA check, returning DDI_INTR_UNCLAIMED"));
2342 return (DDI_INTR_CLAIMED);
2343 }
2344 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
2345
2346 #ifdef OCRDEBUG
2347 if (debug_consecutive_timeout_after_ocr_g == 1) {
2348 con_log(CL_ANN1, (CE_NOTE,
2349 "simulating consecutive timeout after ocr"));
2350 return (DDI_INTR_CLAIMED);
2351 }
2352 #endif
2353
2354 mutex_enter(&instance->completed_pool_mtx);
2355 mutex_enter(&instance->cmd_pend_mtx);
2356
2357 producer = ddi_get32(instance->mfi_internal_dma_obj.acc_handle,
2358 instance->producer);
2359 consumer = ddi_get32(instance->mfi_internal_dma_obj.acc_handle,
2360 instance->consumer);
2361
2362 con_log(CL_ANN, (CE_CONT, " producer %x consumer %x ",
2363 producer, consumer));
2364 if (producer == consumer) {
2365 con_log(CL_ANN, (CE_WARN, "producer == consumer case"));
2366 DTRACE_PROBE2(isr_pc_err, uint32_t, producer,
2367 uint32_t, consumer);
2368 mutex_exit(&instance->cmd_pend_mtx);
2369 mutex_exit(&instance->completed_pool_mtx);
2370 return (DDI_INTR_CLAIMED);
2371 }
2372
2373 while (consumer != producer) {
2374 context = ddi_get32(instance->mfi_internal_dma_obj.acc_handle,
2375 &instance->reply_queue[consumer]);
2376 cmd = instance->cmd_list[context];
2377
2378 if (cmd->sync_cmd == MRSAS_TRUE) {
2379 hdr = (struct mrsas_header *)&cmd->frame->hdr;
2380 if (hdr) {
2381 mlist_del_init(&cmd->list);
2382 }
2383 } else {
2384 pkt = cmd->pkt;
2385 if (pkt) {
2386 mlist_del_init(&cmd->list);
2387 }
2388 }
2389
2390 mlist_add_tail(&cmd->list, &instance->completed_pool_list);
2391
2392 consumer++;
2393 if (consumer == (instance->max_fw_cmds + 1)) {
2394 consumer = 0;
2395 }
2396 }
2397 ddi_put32(instance->mfi_internal_dma_obj.acc_handle,
2398 instance->consumer, consumer);
2399 mutex_exit(&instance->cmd_pend_mtx);
2400 mutex_exit(&instance->completed_pool_mtx);
2401
2402 (void) ddi_dma_sync(instance->mfi_internal_dma_obj.dma_handle,
2403 0, 0, DDI_DMA_SYNC_FORDEV);
2404
2405 if (instance->softint_running) {
2406 need_softintr = 0;
2407 } else {
2408 need_softintr = 1;
2409 }
2410
2411 if (instance->isr_level == HIGH_LEVEL_INTR) {
2412 if (need_softintr) {
2413 ddi_trigger_softintr(instance->soft_intr_id);
2414 }
2415 } else {
2416 /*
2417 * Not a high-level interrupt, therefore call the soft level
2418 * interrupt explicitly
2419 */
2420 (void) mrsas_softintr(instance);
2421 }
2422
2423 return (DDI_INTR_CLAIMED);
2424 }
2425
2426
2427 /*
2428 * ************************************************************************** *
2429 * *
2430 * libraries *
2431 * *
2432 * ************************************************************************** *
2433 */
2434 /*
2435 * get_mfi_pkt : Get a command from the free pool
2436 * After successful allocation, the caller of this routine
2437 * must clear the frame buffer (memset to zero) before
2438 * using the packet further.
2439 *
2440 * ***** Note *****
2441 * After clearing the frame buffer the context id of the
2442 * frame buffer SHOULD be restored back.
2443 */
2444 struct mrsas_cmd *
mrsas_get_mfi_pkt(struct mrsas_instance * instance)2445 mrsas_get_mfi_pkt(struct mrsas_instance *instance)
2446 {
2447 mlist_t *head = &instance->cmd_pool_list;
2448 struct mrsas_cmd *cmd = NULL;
2449
2450 mutex_enter(&instance->cmd_pool_mtx);
2451
2452 if (!mlist_empty(head)) {
2453 cmd = mlist_entry(head->next, struct mrsas_cmd, list);
2454 mlist_del_init(head->next);
2455 }
2456 if (cmd != NULL) {
2457 cmd->pkt = NULL;
2458 cmd->retry_count_for_ocr = 0;
2459 cmd->drv_pkt_time = 0;
2460
2461 }
2462 mutex_exit(&instance->cmd_pool_mtx);
2463
2464 return (cmd);
2465 }
2466
2467 static struct mrsas_cmd *
get_mfi_app_pkt(struct mrsas_instance * instance)2468 get_mfi_app_pkt(struct mrsas_instance *instance)
2469 {
2470 mlist_t *head = &instance->app_cmd_pool_list;
2471 struct mrsas_cmd *cmd = NULL;
2472
2473 mutex_enter(&instance->app_cmd_pool_mtx);
2474
2475 if (!mlist_empty(head)) {
2476 cmd = mlist_entry(head->next, struct mrsas_cmd, list);
2477 mlist_del_init(head->next);
2478 }
2479 if (cmd != NULL) {
2480 cmd->pkt = NULL;
2481 cmd->retry_count_for_ocr = 0;
2482 cmd->drv_pkt_time = 0;
2483 }
2484
2485 mutex_exit(&instance->app_cmd_pool_mtx);
2486
2487 return (cmd);
2488 }
2489 /*
2490 * return_mfi_pkt : Return a cmd to free command pool
2491 */
2492 void
mrsas_return_mfi_pkt(struct mrsas_instance * instance,struct mrsas_cmd * cmd)2493 mrsas_return_mfi_pkt(struct mrsas_instance *instance, struct mrsas_cmd *cmd)
2494 {
2495 mutex_enter(&instance->cmd_pool_mtx);
2496 /* use mlist_add_tail for debug assistance */
2497 mlist_add_tail(&cmd->list, &instance->cmd_pool_list);
2498
2499 mutex_exit(&instance->cmd_pool_mtx);
2500 }
2501
2502 static void
return_mfi_app_pkt(struct mrsas_instance * instance,struct mrsas_cmd * cmd)2503 return_mfi_app_pkt(struct mrsas_instance *instance, struct mrsas_cmd *cmd)
2504 {
2505 mutex_enter(&instance->app_cmd_pool_mtx);
2506
2507 mlist_add(&cmd->list, &instance->app_cmd_pool_list);
2508
2509 mutex_exit(&instance->app_cmd_pool_mtx);
2510 }
2511 void
push_pending_mfi_pkt(struct mrsas_instance * instance,struct mrsas_cmd * cmd)2512 push_pending_mfi_pkt(struct mrsas_instance *instance, struct mrsas_cmd *cmd)
2513 {
2514 struct scsi_pkt *pkt;
2515 struct mrsas_header *hdr;
2516 con_log(CL_DLEVEL2, (CE_NOTE, "push_pending_pkt(): Called\n"));
2517 mutex_enter(&instance->cmd_pend_mtx);
2518 mlist_del_init(&cmd->list);
2519 mlist_add_tail(&cmd->list, &instance->cmd_pend_list);
2520 if (cmd->sync_cmd == MRSAS_TRUE) {
2521 hdr = (struct mrsas_header *)&cmd->frame->hdr;
2522 if (hdr) {
2523 con_log(CL_ANN1, (CE_CONT,
2524 "push_pending_mfi_pkt: "
2525 "cmd %p index %x "
2526 "time %llx",
2527 (void *)cmd, cmd->index,
2528 gethrtime()));
2529 /* Wait for specified interval */
2530 cmd->drv_pkt_time = ddi_get16(
2531 cmd->frame_dma_obj.acc_handle, &hdr->timeout);
2532 if (cmd->drv_pkt_time < debug_timeout_g)
2533 cmd->drv_pkt_time = (uint16_t)debug_timeout_g;
2534 con_log(CL_ANN1, (CE_CONT,
2535 "push_pending_pkt(): Called IO Timeout Value %x\n",
2536 cmd->drv_pkt_time));
2537 }
2538 if (hdr && instance->timeout_id == (timeout_id_t)-1) {
2539 instance->timeout_id = timeout(io_timeout_checker,
2540 (void *) instance, drv_usectohz(MRSAS_1_SECOND));
2541 }
2542 } else {
2543 pkt = cmd->pkt;
2544 if (pkt) {
2545 con_log(CL_ANN1, (CE_CONT,
2546 "push_pending_mfi_pkt: "
2547 "cmd %p index %x pkt %p, "
2548 "time %llx",
2549 (void *)cmd, cmd->index, (void *)pkt,
2550 gethrtime()));
2551 cmd->drv_pkt_time = (uint16_t)debug_timeout_g;
2552 }
2553 if (pkt && instance->timeout_id == (timeout_id_t)-1) {
2554 instance->timeout_id = timeout(io_timeout_checker,
2555 (void *) instance, drv_usectohz(MRSAS_1_SECOND));
2556 }
2557 }
2558
2559 mutex_exit(&instance->cmd_pend_mtx);
2560
2561 }
2562
2563 int
mrsas_print_pending_cmds(struct mrsas_instance * instance)2564 mrsas_print_pending_cmds(struct mrsas_instance *instance)
2565 {
2566 mlist_t *head = &instance->cmd_pend_list;
2567 mlist_t *tmp = head;
2568 struct mrsas_cmd *cmd = NULL;
2569 struct mrsas_header *hdr;
2570 unsigned int flag = 1;
2571 struct scsi_pkt *pkt;
2572 int saved_level;
2573 int cmd_count = 0;
2574
2575 saved_level = debug_level_g;
2576 debug_level_g = CL_ANN1;
2577
2578 dev_err(instance->dip, CE_NOTE,
2579 "mrsas_print_pending_cmds(): Called");
2580
2581 while (flag) {
2582 mutex_enter(&instance->cmd_pend_mtx);
2583 tmp = tmp->next;
2584 if (tmp == head) {
2585 mutex_exit(&instance->cmd_pend_mtx);
2586 flag = 0;
2587 con_log(CL_ANN1, (CE_CONT, "mrsas_print_pending_cmds():"
2588 " NO MORE CMDS PENDING....\n"));
2589 break;
2590 } else {
2591 cmd = mlist_entry(tmp, struct mrsas_cmd, list);
2592 mutex_exit(&instance->cmd_pend_mtx);
2593 if (cmd) {
2594 if (cmd->sync_cmd == MRSAS_TRUE) {
2595 hdr = (struct mrsas_header *)
2596 &cmd->frame->hdr;
2597 if (hdr) {
2598 con_log(CL_ANN1, (CE_CONT,
2599 "print: cmd %p index 0x%x "
2600 "drv_pkt_time 0x%x (NO-PKT)"
2601 " hdr %p\n", (void *)cmd,
2602 cmd->index,
2603 cmd->drv_pkt_time,
2604 (void *)hdr));
2605 }
2606 } else {
2607 pkt = cmd->pkt;
2608 if (pkt) {
2609 con_log(CL_ANN1, (CE_CONT,
2610 "print: cmd %p index 0x%x "
2611 "drv_pkt_time 0x%x pkt %p \n",
2612 (void *)cmd, cmd->index,
2613 cmd->drv_pkt_time, (void *)pkt));
2614 }
2615 }
2616
2617 if (++cmd_count == 1) {
2618 mrsas_print_cmd_details(instance, cmd,
2619 0xDD);
2620 } else {
2621 mrsas_print_cmd_details(instance, cmd,
2622 1);
2623 }
2624
2625 }
2626 }
2627 }
2628 con_log(CL_ANN1, (CE_CONT, "mrsas_print_pending_cmds(): Done\n"));
2629
2630
2631 debug_level_g = saved_level;
2632
2633 return (DDI_SUCCESS);
2634 }
2635
2636
2637 int
mrsas_complete_pending_cmds(struct mrsas_instance * instance)2638 mrsas_complete_pending_cmds(struct mrsas_instance *instance)
2639 {
2640
2641 struct mrsas_cmd *cmd = NULL;
2642 struct scsi_pkt *pkt;
2643 struct mrsas_header *hdr;
2644
2645 struct mlist_head *pos, *next;
2646
2647 con_log(CL_ANN1, (CE_NOTE,
2648 "mrsas_complete_pending_cmds(): Called"));
2649
2650 mutex_enter(&instance->cmd_pend_mtx);
2651 mlist_for_each_safe(pos, next, &instance->cmd_pend_list) {
2652 cmd = mlist_entry(pos, struct mrsas_cmd, list);
2653 if (cmd) {
2654 pkt = cmd->pkt;
2655 if (pkt) { /* for IO */
2656 if (((pkt->pkt_flags & FLAG_NOINTR)
2657 == 0) && pkt->pkt_comp) {
2658 pkt->pkt_reason
2659 = CMD_DEV_GONE;
2660 pkt->pkt_statistics
2661 = STAT_DISCON;
2662 con_log(CL_ANN1, (CE_CONT,
2663 "fail and posting to scsa "
2664 "cmd %p index %x"
2665 " pkt %p "
2666 "time : %llx",
2667 (void *)cmd, cmd->index,
2668 (void *)pkt, gethrtime()));
2669 (*pkt->pkt_comp)(pkt);
2670 }
2671 } else { /* for DCMDS */
2672 if (cmd->sync_cmd == MRSAS_TRUE) {
2673 hdr = (struct mrsas_header *)&cmd->frame->hdr;
2674 con_log(CL_ANN1, (CE_CONT,
2675 "posting invalid status to application "
2676 "cmd %p index %x"
2677 " hdr %p "
2678 "time : %llx",
2679 (void *)cmd, cmd->index,
2680 (void *)hdr, gethrtime()));
2681 hdr->cmd_status = MFI_STAT_INVALID_STATUS;
2682 complete_cmd_in_sync_mode(instance, cmd);
2683 }
2684 }
2685 mlist_del_init(&cmd->list);
2686 } else {
2687 con_log(CL_ANN1, (CE_CONT,
2688 "mrsas_complete_pending_cmds:"
2689 "NULL command\n"));
2690 }
2691 con_log(CL_ANN1, (CE_CONT,
2692 "mrsas_complete_pending_cmds:"
2693 "looping for more commands\n"));
2694 }
2695 mutex_exit(&instance->cmd_pend_mtx);
2696
2697 con_log(CL_ANN1, (CE_CONT, "mrsas_complete_pending_cmds(): DONE\n"));
2698 return (DDI_SUCCESS);
2699 }
2700
2701 void
mrsas_print_cmd_details(struct mrsas_instance * instance,struct mrsas_cmd * cmd,int detail)2702 mrsas_print_cmd_details(struct mrsas_instance *instance, struct mrsas_cmd *cmd,
2703 int detail)
2704 {
2705 struct scsi_pkt *pkt = cmd->pkt;
2706 Mpi2RaidSCSIIORequest_t *scsi_io = cmd->scsi_io_request;
2707 int i;
2708 int saved_level;
2709 ddi_acc_handle_t acc_handle =
2710 instance->mpi2_frame_pool_dma_obj.acc_handle;
2711
2712 if (detail == 0xDD) {
2713 saved_level = debug_level_g;
2714 debug_level_g = CL_ANN1;
2715 }
2716
2717
2718 if (instance->tbolt) {
2719 con_log(CL_ANN1, (CE_CONT, "print_cmd_details: cmd %p "
2720 "cmd->index 0x%x SMID 0x%x timer 0x%x sec\n",
2721 (void *)cmd, cmd->index, cmd->SMID, cmd->drv_pkt_time));
2722 } else {
2723 con_log(CL_ANN1, (CE_CONT, "print_cmd_details: cmd %p "
2724 "cmd->index 0x%x timer 0x%x sec\n",
2725 (void *)cmd, cmd->index, cmd->drv_pkt_time));
2726 }
2727
2728 if (pkt) {
2729 con_log(CL_ANN1, (CE_CONT, "scsi_pkt CDB[0]=0x%x",
2730 pkt->pkt_cdbp[0]));
2731 } else {
2732 con_log(CL_ANN1, (CE_CONT, "NO-PKT"));
2733 }
2734
2735 if ((detail == 0xDD) && instance->tbolt) {
2736 con_log(CL_ANN1, (CE_CONT, "RAID_SCSI_IO_REQUEST\n"));
2737 con_log(CL_ANN1, (CE_CONT, "DevHandle=0x%X Function=0x%X "
2738 "IoFlags=0x%X SGLFlags=0x%X DataLength=0x%X\n",
2739 ddi_get16(acc_handle, &scsi_io->DevHandle),
2740 ddi_get8(acc_handle, &scsi_io->Function),
2741 ddi_get16(acc_handle, &scsi_io->IoFlags),
2742 ddi_get16(acc_handle, &scsi_io->SGLFlags),
2743 ddi_get32(acc_handle, &scsi_io->DataLength)));
2744
2745 for (i = 0; i < 32; i++) {
2746 con_log(CL_ANN1, (CE_CONT, "CDB[%d]=0x%x ", i,
2747 ddi_get8(acc_handle, &scsi_io->CDB.CDB32[i])));
2748 }
2749
2750 con_log(CL_ANN1, (CE_CONT, "RAID-CONTEXT\n"));
2751 con_log(CL_ANN1, (CE_CONT, "status=0x%X extStatus=0x%X "
2752 "ldTargetId=0x%X timeoutValue=0x%X regLockFlags=0x%X "
2753 "RAIDFlags=0x%X regLockRowLBA=0x%" PRIu64
2754 " regLockLength=0x%X spanArm=0x%X\n",
2755 ddi_get8(acc_handle, &scsi_io->RaidContext.status),
2756 ddi_get8(acc_handle, &scsi_io->RaidContext.extStatus),
2757 ddi_get16(acc_handle, &scsi_io->RaidContext.ldTargetId),
2758 ddi_get16(acc_handle, &scsi_io->RaidContext.timeoutValue),
2759 ddi_get8(acc_handle, &scsi_io->RaidContext.regLockFlags),
2760 ddi_get8(acc_handle, &scsi_io->RaidContext.RAIDFlags),
2761 ddi_get64(acc_handle, &scsi_io->RaidContext.regLockRowLBA),
2762 ddi_get32(acc_handle, &scsi_io->RaidContext.regLockLength),
2763 ddi_get8(acc_handle, &scsi_io->RaidContext.spanArm)));
2764 }
2765
2766 if (detail == 0xDD) {
2767 debug_level_g = saved_level;
2768 }
2769 }
2770
2771
2772 int
mrsas_issue_pending_cmds(struct mrsas_instance * instance)2773 mrsas_issue_pending_cmds(struct mrsas_instance *instance)
2774 {
2775 mlist_t *head = &instance->cmd_pend_list;
2776 mlist_t *tmp = head->next;
2777 struct mrsas_cmd *cmd = NULL;
2778 struct scsi_pkt *pkt;
2779
2780 con_log(CL_ANN1, (CE_NOTE, "mrsas_issue_pending_cmds(): Called"));
2781 while (tmp != head) {
2782 mutex_enter(&instance->cmd_pend_mtx);
2783 cmd = mlist_entry(tmp, struct mrsas_cmd, list);
2784 tmp = tmp->next;
2785 mutex_exit(&instance->cmd_pend_mtx);
2786 if (cmd) {
2787 con_log(CL_ANN1, (CE_CONT,
2788 "mrsas_issue_pending_cmds(): "
2789 "Got a cmd: cmd %p index 0x%x drv_pkt_time 0x%x ",
2790 (void *)cmd, cmd->index, cmd->drv_pkt_time));
2791
2792 /* Reset command timeout value */
2793 if (cmd->drv_pkt_time < debug_timeout_g)
2794 cmd->drv_pkt_time = (uint16_t)debug_timeout_g;
2795
2796 cmd->retry_count_for_ocr++;
2797
2798 dev_err(instance->dip, CE_CONT,
2799 "cmd retry count = %d\n",
2800 cmd->retry_count_for_ocr);
2801
2802 if (cmd->retry_count_for_ocr > IO_RETRY_COUNT) {
2803 dev_err(instance->dip,
2804 CE_WARN, "mrsas_issue_pending_cmds(): "
2805 "cmd->retry_count exceeded limit >%d\n",
2806 IO_RETRY_COUNT);
2807 mrsas_print_cmd_details(instance, cmd, 0xDD);
2808
2809 dev_err(instance->dip, CE_WARN,
2810 "mrsas_issue_pending_cmds():"
2811 "Calling KILL Adapter");
2812 if (instance->tbolt)
2813 mrsas_tbolt_kill_adapter(instance);
2814 else
2815 (void) mrsas_kill_adapter(instance);
2816 return (DDI_FAILURE);
2817 }
2818
2819 pkt = cmd->pkt;
2820 if (pkt) {
2821 con_log(CL_ANN1, (CE_CONT,
2822 "PENDING PKT-CMD ISSUE: cmd %p index %x "
2823 "pkt %p time %llx",
2824 (void *)cmd, cmd->index,
2825 (void *)pkt,
2826 gethrtime()));
2827
2828 } else {
2829 dev_err(instance->dip, CE_CONT,
2830 "mrsas_issue_pending_cmds(): NO-PKT, "
2831 "cmd %p index 0x%x drv_pkt_time 0x%x",
2832 (void *)cmd, cmd->index, cmd->drv_pkt_time);
2833 }
2834
2835
2836 if (cmd->sync_cmd == MRSAS_TRUE) {
2837 dev_err(instance->dip, CE_CONT,
2838 "mrsas_issue_pending_cmds(): "
2839 "SYNC_CMD == TRUE \n");
2840 instance->func_ptr->issue_cmd_in_sync_mode(
2841 instance, cmd);
2842 } else {
2843 instance->func_ptr->issue_cmd(cmd, instance);
2844 }
2845 } else {
2846 con_log(CL_ANN1, (CE_CONT,
2847 "mrsas_issue_pending_cmds: NULL command\n"));
2848 }
2849 con_log(CL_ANN1, (CE_CONT,
2850 "mrsas_issue_pending_cmds:"
2851 "looping for more commands"));
2852 }
2853 con_log(CL_ANN1, (CE_CONT, "mrsas_issue_pending_cmds(): DONE\n"));
2854 return (DDI_SUCCESS);
2855 }
2856
2857
2858
2859 /*
2860 * destroy_mfi_frame_pool
2861 */
2862 void
destroy_mfi_frame_pool(struct mrsas_instance * instance)2863 destroy_mfi_frame_pool(struct mrsas_instance *instance)
2864 {
2865 int i;
2866 uint32_t max_cmd = instance->max_fw_cmds;
2867
2868 struct mrsas_cmd *cmd;
2869
2870 /* return all frames to pool */
2871
2872 for (i = 0; i < max_cmd; i++) {
2873
2874 cmd = instance->cmd_list[i];
2875
2876 if (cmd->frame_dma_obj_status == DMA_OBJ_ALLOCATED)
2877 (void) mrsas_free_dma_obj(instance, cmd->frame_dma_obj);
2878
2879 cmd->frame_dma_obj_status = DMA_OBJ_FREED;
2880 }
2881
2882 }
2883
2884 /*
2885 * create_mfi_frame_pool
2886 */
2887 int
create_mfi_frame_pool(struct mrsas_instance * instance)2888 create_mfi_frame_pool(struct mrsas_instance *instance)
2889 {
2890 int i = 0;
2891 int cookie_cnt;
2892 uint16_t max_cmd;
2893 uint16_t sge_sz;
2894 uint32_t sgl_sz;
2895 uint32_t tot_frame_size;
2896 struct mrsas_cmd *cmd;
2897 int retval = DDI_SUCCESS;
2898
2899 max_cmd = instance->max_fw_cmds;
2900 sge_sz = sizeof (struct mrsas_sge_ieee);
2901 /* calculated the number of 64byte frames required for SGL */
2902 sgl_sz = sge_sz * instance->max_num_sge;
2903 tot_frame_size = sgl_sz + MRMFI_FRAME_SIZE + SENSE_LENGTH;
2904
2905 con_log(CL_DLEVEL3, (CE_NOTE, "create_mfi_frame_pool: "
2906 "sgl_sz %x tot_frame_size %x", sgl_sz, tot_frame_size));
2907
2908 while (i < max_cmd) {
2909 cmd = instance->cmd_list[i];
2910
2911 cmd->frame_dma_obj.size = tot_frame_size;
2912 cmd->frame_dma_obj.dma_attr = mrsas_generic_dma_attr;
2913 cmd->frame_dma_obj.dma_attr.dma_attr_addr_hi = 0xFFFFFFFFU;
2914 cmd->frame_dma_obj.dma_attr.dma_attr_count_max = 0xFFFFFFFFU;
2915 cmd->frame_dma_obj.dma_attr.dma_attr_sgllen = 1;
2916 cmd->frame_dma_obj.dma_attr.dma_attr_align = 64;
2917
2918 cookie_cnt = mrsas_alloc_dma_obj(instance, &cmd->frame_dma_obj,
2919 (uchar_t)DDI_STRUCTURE_LE_ACC);
2920
2921 if (cookie_cnt == -1 || cookie_cnt > 1) {
2922 dev_err(instance->dip, CE_WARN,
2923 "create_mfi_frame_pool: could not alloc.");
2924 retval = DDI_FAILURE;
2925 goto mrsas_undo_frame_pool;
2926 }
2927
2928 bzero(cmd->frame_dma_obj.buffer, tot_frame_size);
2929
2930 cmd->frame_dma_obj_status = DMA_OBJ_ALLOCATED;
2931 cmd->frame = (union mrsas_frame *)cmd->frame_dma_obj.buffer;
2932 cmd->frame_phys_addr =
2933 cmd->frame_dma_obj.dma_cookie[0].dmac_address;
2934
2935 cmd->sense = (uint8_t *)(((unsigned long)
2936 cmd->frame_dma_obj.buffer) +
2937 tot_frame_size - SENSE_LENGTH);
2938 cmd->sense_phys_addr =
2939 cmd->frame_dma_obj.dma_cookie[0].dmac_address +
2940 tot_frame_size - SENSE_LENGTH;
2941
2942 if (!cmd->frame || !cmd->sense) {
2943 dev_err(instance->dip, CE_WARN,
2944 "pci_pool_alloc failed");
2945 retval = ENOMEM;
2946 goto mrsas_undo_frame_pool;
2947 }
2948
2949 ddi_put32(cmd->frame_dma_obj.acc_handle,
2950 &cmd->frame->io.context, cmd->index);
2951 i++;
2952
2953 con_log(CL_DLEVEL3, (CE_NOTE, "[%x]-%x",
2954 cmd->index, cmd->frame_phys_addr));
2955 }
2956
2957 return (DDI_SUCCESS);
2958
2959 mrsas_undo_frame_pool:
2960 if (i > 0)
2961 destroy_mfi_frame_pool(instance);
2962
2963 return (retval);
2964 }
2965
2966 /*
2967 * free_additional_dma_buffer
2968 */
2969 static void
free_additional_dma_buffer(struct mrsas_instance * instance)2970 free_additional_dma_buffer(struct mrsas_instance *instance)
2971 {
2972 if (instance->mfi_internal_dma_obj.status == DMA_OBJ_ALLOCATED) {
2973 (void) mrsas_free_dma_obj(instance,
2974 instance->mfi_internal_dma_obj);
2975 instance->mfi_internal_dma_obj.status = DMA_OBJ_FREED;
2976 }
2977
2978 if (instance->mfi_evt_detail_obj.status == DMA_OBJ_ALLOCATED) {
2979 (void) mrsas_free_dma_obj(instance,
2980 instance->mfi_evt_detail_obj);
2981 instance->mfi_evt_detail_obj.status = DMA_OBJ_FREED;
2982 }
2983 }
2984
2985 /*
2986 * alloc_additional_dma_buffer
2987 */
2988 static int
alloc_additional_dma_buffer(struct mrsas_instance * instance)2989 alloc_additional_dma_buffer(struct mrsas_instance *instance)
2990 {
2991 uint32_t reply_q_sz;
2992 uint32_t internal_buf_size = PAGESIZE*2;
2993
2994 /* max cmds plus 1 + producer & consumer */
2995 reply_q_sz = sizeof (uint32_t) * (instance->max_fw_cmds + 1 + 2);
2996
2997 instance->mfi_internal_dma_obj.size = internal_buf_size;
2998 instance->mfi_internal_dma_obj.dma_attr = mrsas_generic_dma_attr;
2999 instance->mfi_internal_dma_obj.dma_attr.dma_attr_addr_hi = 0xFFFFFFFFU;
3000 instance->mfi_internal_dma_obj.dma_attr.dma_attr_count_max =
3001 0xFFFFFFFFU;
3002 instance->mfi_internal_dma_obj.dma_attr.dma_attr_sgllen = 1;
3003
3004 if (mrsas_alloc_dma_obj(instance, &instance->mfi_internal_dma_obj,
3005 (uchar_t)DDI_STRUCTURE_LE_ACC) != 1) {
3006 dev_err(instance->dip, CE_WARN,
3007 "could not alloc reply queue");
3008 return (DDI_FAILURE);
3009 }
3010
3011 bzero(instance->mfi_internal_dma_obj.buffer, internal_buf_size);
3012
3013 instance->mfi_internal_dma_obj.status |= DMA_OBJ_ALLOCATED;
3014
3015 instance->producer = (uint32_t *)((unsigned long)
3016 instance->mfi_internal_dma_obj.buffer);
3017 instance->consumer = (uint32_t *)((unsigned long)
3018 instance->mfi_internal_dma_obj.buffer + 4);
3019 instance->reply_queue = (uint32_t *)((unsigned long)
3020 instance->mfi_internal_dma_obj.buffer + 8);
3021 instance->internal_buf = (caddr_t)(((unsigned long)
3022 instance->mfi_internal_dma_obj.buffer) + reply_q_sz + 8);
3023 instance->internal_buf_dmac_add =
3024 instance->mfi_internal_dma_obj.dma_cookie[0].dmac_address +
3025 (reply_q_sz + 8);
3026 instance->internal_buf_size = internal_buf_size -
3027 (reply_q_sz + 8);
3028
3029 /* allocate evt_detail */
3030 instance->mfi_evt_detail_obj.size = sizeof (struct mrsas_evt_detail);
3031 instance->mfi_evt_detail_obj.dma_attr = mrsas_generic_dma_attr;
3032 instance->mfi_evt_detail_obj.dma_attr.dma_attr_addr_hi = 0xFFFFFFFFU;
3033 instance->mfi_evt_detail_obj.dma_attr.dma_attr_count_max = 0xFFFFFFFFU;
3034 instance->mfi_evt_detail_obj.dma_attr.dma_attr_sgllen = 1;
3035 instance->mfi_evt_detail_obj.dma_attr.dma_attr_align = 1;
3036
3037 if (mrsas_alloc_dma_obj(instance, &instance->mfi_evt_detail_obj,
3038 (uchar_t)DDI_STRUCTURE_LE_ACC) != 1) {
3039 dev_err(instance->dip, CE_WARN, "alloc_additional_dma_buffer: "
3040 "could not allocate data transfer buffer.");
3041 goto mrsas_undo_internal_buff;
3042 }
3043
3044 bzero(instance->mfi_evt_detail_obj.buffer,
3045 sizeof (struct mrsas_evt_detail));
3046
3047 instance->mfi_evt_detail_obj.status |= DMA_OBJ_ALLOCATED;
3048
3049 return (DDI_SUCCESS);
3050
3051 mrsas_undo_internal_buff:
3052 if (instance->mfi_internal_dma_obj.status == DMA_OBJ_ALLOCATED) {
3053 (void) mrsas_free_dma_obj(instance,
3054 instance->mfi_internal_dma_obj);
3055 instance->mfi_internal_dma_obj.status = DMA_OBJ_FREED;
3056 }
3057
3058 return (DDI_FAILURE);
3059 }
3060
3061
3062 void
mrsas_free_cmd_pool(struct mrsas_instance * instance)3063 mrsas_free_cmd_pool(struct mrsas_instance *instance)
3064 {
3065 int i;
3066 uint32_t max_cmd;
3067 size_t sz;
3068
3069 /* already freed */
3070 if (instance->cmd_list == NULL) {
3071 return;
3072 }
3073
3074 max_cmd = instance->max_fw_cmds;
3075
3076 /* size of cmd_list array */
3077 sz = sizeof (struct mrsas_cmd *) * max_cmd;
3078
3079 /* First free each cmd */
3080 for (i = 0; i < max_cmd; i++) {
3081 if (instance->cmd_list[i] != NULL) {
3082 kmem_free(instance->cmd_list[i],
3083 sizeof (struct mrsas_cmd));
3084 }
3085
3086 instance->cmd_list[i] = NULL;
3087 }
3088
3089 /* Now, free cmd_list array */
3090 if (instance->cmd_list != NULL)
3091 kmem_free(instance->cmd_list, sz);
3092
3093 instance->cmd_list = NULL;
3094
3095 INIT_LIST_HEAD(&instance->cmd_pool_list);
3096 INIT_LIST_HEAD(&instance->cmd_pend_list);
3097 if (instance->tbolt) {
3098 INIT_LIST_HEAD(&instance->cmd_app_pool_list);
3099 } else {
3100 INIT_LIST_HEAD(&instance->app_cmd_pool_list);
3101 }
3102
3103 }
3104
3105
3106 /*
3107 * mrsas_alloc_cmd_pool
3108 */
3109 int
mrsas_alloc_cmd_pool(struct mrsas_instance * instance)3110 mrsas_alloc_cmd_pool(struct mrsas_instance *instance)
3111 {
3112 int i;
3113 int count;
3114 uint32_t max_cmd;
3115 uint32_t reserve_cmd;
3116 size_t sz;
3117
3118 struct mrsas_cmd *cmd;
3119
3120 max_cmd = instance->max_fw_cmds;
3121 con_log(CL_ANN1, (CE_NOTE, "mrsas_alloc_cmd_pool: "
3122 "max_cmd %x", max_cmd));
3123
3124
3125 sz = sizeof (struct mrsas_cmd *) * max_cmd;
3126
3127 /*
3128 * instance->cmd_list is an array of struct mrsas_cmd pointers.
3129 * Allocate the dynamic array first and then allocate individual
3130 * commands.
3131 */
3132 instance->cmd_list = kmem_zalloc(sz, KM_SLEEP);
3133 ASSERT(instance->cmd_list);
3134
3135 /* create a frame pool and assign one frame to each cmd */
3136 for (count = 0; count < max_cmd; count++) {
3137 instance->cmd_list[count] =
3138 kmem_zalloc(sizeof (struct mrsas_cmd), KM_SLEEP);
3139 ASSERT(instance->cmd_list[count]);
3140 }
3141
3142 /* add all the commands to command pool */
3143
3144 INIT_LIST_HEAD(&instance->cmd_pool_list);
3145 INIT_LIST_HEAD(&instance->cmd_pend_list);
3146 INIT_LIST_HEAD(&instance->app_cmd_pool_list);
3147
3148 /*
3149 * When max_cmd is lower than MRSAS_APP_RESERVED_CMDS, how do I split
3150 * into app_cmd and regular cmd? For now, just take
3151 * max(1/8th of max, 4);
3152 */
3153 reserve_cmd = min(MRSAS_APP_RESERVED_CMDS,
3154 max(max_cmd >> 3, MRSAS_APP_MIN_RESERVED_CMDS));
3155
3156 for (i = 0; i < reserve_cmd; i++) {
3157 cmd = instance->cmd_list[i];
3158 cmd->index = i;
3159 mlist_add_tail(&cmd->list, &instance->app_cmd_pool_list);
3160 }
3161
3162
3163 for (i = reserve_cmd; i < max_cmd; i++) {
3164 cmd = instance->cmd_list[i];
3165 cmd->index = i;
3166 mlist_add_tail(&cmd->list, &instance->cmd_pool_list);
3167 }
3168
3169 return (DDI_SUCCESS);
3170 }
3171
3172
3173 /*
3174 * free_space_for_mfi
3175 */
3176 static void
free_space_for_mfi(struct mrsas_instance * instance)3177 free_space_for_mfi(struct mrsas_instance *instance)
3178 {
3179
3180 /* already freed */
3181 if (instance->cmd_list == NULL) {
3182 return;
3183 }
3184
3185 /* Free additional dma buffer */
3186 free_additional_dma_buffer(instance);
3187
3188 /* Free the MFI frame pool */
3189 destroy_mfi_frame_pool(instance);
3190
3191 /* Free all the commands in the cmd_list */
3192 /* Free the cmd_list buffer itself */
3193 mrsas_free_cmd_pool(instance);
3194 }
3195
3196 /*
3197 * alloc_space_for_mfi
3198 */
3199 static int
alloc_space_for_mfi(struct mrsas_instance * instance)3200 alloc_space_for_mfi(struct mrsas_instance *instance)
3201 {
3202 /* Allocate command pool (memory for cmd_list & individual commands) */
3203 if (mrsas_alloc_cmd_pool(instance)) {
3204 dev_err(instance->dip, CE_WARN, "error creating cmd pool");
3205 return (DDI_FAILURE);
3206 }
3207
3208 /* Allocate MFI Frame pool */
3209 if (create_mfi_frame_pool(instance)) {
3210 dev_err(instance->dip, CE_WARN,
3211 "error creating frame DMA pool");
3212 goto mfi_undo_cmd_pool;
3213 }
3214
3215 /* Allocate additional DMA buffer */
3216 if (alloc_additional_dma_buffer(instance)) {
3217 dev_err(instance->dip, CE_WARN,
3218 "error creating frame DMA pool");
3219 goto mfi_undo_frame_pool;
3220 }
3221
3222 return (DDI_SUCCESS);
3223
3224 mfi_undo_frame_pool:
3225 destroy_mfi_frame_pool(instance);
3226
3227 mfi_undo_cmd_pool:
3228 mrsas_free_cmd_pool(instance);
3229
3230 return (DDI_FAILURE);
3231 }
3232
3233
3234
3235 /*
3236 * get_ctrl_info
3237 */
3238 static int
get_ctrl_info(struct mrsas_instance * instance,struct mrsas_ctrl_info * ctrl_info)3239 get_ctrl_info(struct mrsas_instance *instance,
3240 struct mrsas_ctrl_info *ctrl_info)
3241 {
3242 int ret = 0;
3243
3244 struct mrsas_cmd *cmd;
3245 struct mrsas_dcmd_frame *dcmd;
3246 struct mrsas_ctrl_info *ci;
3247
3248 if (instance->tbolt) {
3249 cmd = get_raid_msg_mfi_pkt(instance);
3250 } else {
3251 cmd = mrsas_get_mfi_pkt(instance);
3252 }
3253
3254 if (!cmd) {
3255 con_log(CL_ANN, (CE_WARN,
3256 "Failed to get a cmd for ctrl info"));
3257 DTRACE_PROBE2(info_mfi_err, uint16_t, instance->fw_outstanding,
3258 uint16_t, instance->max_fw_cmds);
3259 return (DDI_FAILURE);
3260 }
3261
3262 /* Clear the frame buffer and assign back the context id */
3263 (void) memset((char *)&cmd->frame[0], 0, sizeof (union mrsas_frame));
3264 ddi_put32(cmd->frame_dma_obj.acc_handle, &cmd->frame->hdr.context,
3265 cmd->index);
3266
3267 dcmd = &cmd->frame->dcmd;
3268
3269 ci = (struct mrsas_ctrl_info *)instance->internal_buf;
3270
3271 if (!ci) {
3272 dev_err(instance->dip, CE_WARN,
3273 "Failed to alloc mem for ctrl info");
3274 mrsas_return_mfi_pkt(instance, cmd);
3275 return (DDI_FAILURE);
3276 }
3277
3278 (void) memset(ci, 0, sizeof (struct mrsas_ctrl_info));
3279
3280 /* for( i = 0; i < DCMD_MBOX_SZ; i++ ) dcmd->mbox.b[i] = 0; */
3281 (void) memset(dcmd->mbox.b, 0, DCMD_MBOX_SZ);
3282
3283 ddi_put8(cmd->frame_dma_obj.acc_handle, &dcmd->cmd, MFI_CMD_OP_DCMD);
3284 ddi_put8(cmd->frame_dma_obj.acc_handle, &dcmd->cmd_status,
3285 MFI_CMD_STATUS_POLL_MODE);
3286 ddi_put8(cmd->frame_dma_obj.acc_handle, &dcmd->sge_count, 1);
3287 ddi_put16(cmd->frame_dma_obj.acc_handle, &dcmd->flags,
3288 MFI_FRAME_DIR_READ);
3289 ddi_put16(cmd->frame_dma_obj.acc_handle, &dcmd->timeout, 0);
3290 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->data_xfer_len,
3291 sizeof (struct mrsas_ctrl_info));
3292 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->opcode,
3293 MR_DCMD_CTRL_GET_INFO);
3294 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->sgl.sge32[0].phys_addr,
3295 instance->internal_buf_dmac_add);
3296 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->sgl.sge32[0].length,
3297 sizeof (struct mrsas_ctrl_info));
3298
3299 cmd->frame_count = 1;
3300
3301 if (instance->tbolt) {
3302 mr_sas_tbolt_build_mfi_cmd(instance, cmd);
3303 }
3304
3305 if (!instance->func_ptr->issue_cmd_in_poll_mode(instance, cmd)) {
3306 ret = 0;
3307
3308 ctrl_info->max_request_size = ddi_get32(
3309 cmd->frame_dma_obj.acc_handle, &ci->max_request_size);
3310
3311 ctrl_info->ld_present_count = ddi_get16(
3312 cmd->frame_dma_obj.acc_handle, &ci->ld_present_count);
3313
3314 ctrl_info->properties.on_off_properties = ddi_get32(
3315 cmd->frame_dma_obj.acc_handle,
3316 &ci->properties.on_off_properties);
3317 ddi_rep_get8(cmd->frame_dma_obj.acc_handle,
3318 (uint8_t *)(ctrl_info->product_name),
3319 (uint8_t *)(ci->product_name), 80 * sizeof (char),
3320 DDI_DEV_AUTOINCR);
3321 /* should get more members of ci with ddi_get when needed */
3322 } else {
3323 dev_err(instance->dip, CE_WARN,
3324 "get_ctrl_info: Ctrl info failed");
3325 ret = -1;
3326 }
3327
3328 if (mrsas_common_check(instance, cmd) != DDI_SUCCESS) {
3329 ret = -1;
3330 }
3331 if (instance->tbolt) {
3332 return_raid_msg_mfi_pkt(instance, cmd);
3333 } else {
3334 mrsas_return_mfi_pkt(instance, cmd);
3335 }
3336
3337 return (ret);
3338 }
3339
3340 /*
3341 * abort_aen_cmd
3342 */
3343 static int
abort_aen_cmd(struct mrsas_instance * instance,struct mrsas_cmd * cmd_to_abort)3344 abort_aen_cmd(struct mrsas_instance *instance,
3345 struct mrsas_cmd *cmd_to_abort)
3346 {
3347 int ret = 0;
3348
3349 struct mrsas_cmd *cmd;
3350 struct mrsas_abort_frame *abort_fr;
3351
3352 con_log(CL_ANN1, (CE_NOTE, "chkpnt: abort_aen:%d", __LINE__));
3353
3354 if (instance->tbolt) {
3355 cmd = get_raid_msg_mfi_pkt(instance);
3356 } else {
3357 cmd = mrsas_get_mfi_pkt(instance);
3358 }
3359
3360 if (!cmd) {
3361 con_log(CL_ANN1, (CE_WARN,
3362 "abort_aen_cmd():Failed to get a cmd for abort_aen_cmd"));
3363 DTRACE_PROBE2(abort_mfi_err, uint16_t, instance->fw_outstanding,
3364 uint16_t, instance->max_fw_cmds);
3365 return (DDI_FAILURE);
3366 }
3367
3368 /* Clear the frame buffer and assign back the context id */
3369 (void) memset((char *)&cmd->frame[0], 0, sizeof (union mrsas_frame));
3370 ddi_put32(cmd->frame_dma_obj.acc_handle, &cmd->frame->hdr.context,
3371 cmd->index);
3372
3373 abort_fr = &cmd->frame->abort;
3374
3375 /* prepare and issue the abort frame */
3376 ddi_put8(cmd->frame_dma_obj.acc_handle,
3377 &abort_fr->cmd, MFI_CMD_OP_ABORT);
3378 ddi_put8(cmd->frame_dma_obj.acc_handle, &abort_fr->cmd_status,
3379 MFI_CMD_STATUS_SYNC_MODE);
3380 ddi_put16(cmd->frame_dma_obj.acc_handle, &abort_fr->flags, 0);
3381 ddi_put32(cmd->frame_dma_obj.acc_handle, &abort_fr->abort_context,
3382 cmd_to_abort->index);
3383 ddi_put32(cmd->frame_dma_obj.acc_handle,
3384 &abort_fr->abort_mfi_phys_addr_lo, cmd_to_abort->frame_phys_addr);
3385 ddi_put32(cmd->frame_dma_obj.acc_handle,
3386 &abort_fr->abort_mfi_phys_addr_hi, 0);
3387
3388 instance->aen_cmd->abort_aen = 1;
3389
3390 cmd->frame_count = 1;
3391
3392 if (instance->tbolt) {
3393 mr_sas_tbolt_build_mfi_cmd(instance, cmd);
3394 }
3395
3396 if (instance->func_ptr->issue_cmd_in_poll_mode(instance, cmd)) {
3397 con_log(CL_ANN1, (CE_WARN,
3398 "abort_aen_cmd: issue_cmd_in_poll_mode failed"));
3399 ret = -1;
3400 } else {
3401 ret = 0;
3402 }
3403
3404 instance->aen_cmd->abort_aen = 1;
3405 instance->aen_cmd = 0;
3406
3407 if (instance->tbolt) {
3408 return_raid_msg_mfi_pkt(instance, cmd);
3409 } else {
3410 mrsas_return_mfi_pkt(instance, cmd);
3411 }
3412
3413 atomic_add_16(&instance->fw_outstanding, (-1));
3414
3415 return (ret);
3416 }
3417
3418
3419 static int
mrsas_build_init_cmd(struct mrsas_instance * instance,struct mrsas_cmd ** cmd_ptr)3420 mrsas_build_init_cmd(struct mrsas_instance *instance,
3421 struct mrsas_cmd **cmd_ptr)
3422 {
3423 struct mrsas_cmd *cmd;
3424 struct mrsas_init_frame *init_frame;
3425 struct mrsas_init_queue_info *initq_info;
3426 struct mrsas_drv_ver drv_ver_info;
3427
3428
3429 /*
3430 * Prepare a init frame. Note the init frame points to queue info
3431 * structure. Each frame has SGL allocated after first 64 bytes. For
3432 * this frame - since we don't need any SGL - we use SGL's space as
3433 * queue info structure
3434 */
3435 cmd = *cmd_ptr;
3436
3437
3438 /* Clear the frame buffer and assign back the context id */
3439 (void) memset((char *)&cmd->frame[0], 0, sizeof (union mrsas_frame));
3440 ddi_put32(cmd->frame_dma_obj.acc_handle, &cmd->frame->hdr.context,
3441 cmd->index);
3442
3443 init_frame = (struct mrsas_init_frame *)cmd->frame;
3444 initq_info = (struct mrsas_init_queue_info *)
3445 ((unsigned long)init_frame + 64);
3446
3447 (void) memset(init_frame, 0, MRMFI_FRAME_SIZE);
3448 (void) memset(initq_info, 0, sizeof (struct mrsas_init_queue_info));
3449
3450 ddi_put32(cmd->frame_dma_obj.acc_handle, &initq_info->init_flags, 0);
3451
3452 ddi_put32(cmd->frame_dma_obj.acc_handle,
3453 &initq_info->reply_queue_entries, instance->max_fw_cmds + 1);
3454
3455 ddi_put32(cmd->frame_dma_obj.acc_handle,
3456 &initq_info->producer_index_phys_addr_hi, 0);
3457 ddi_put32(cmd->frame_dma_obj.acc_handle,
3458 &initq_info->producer_index_phys_addr_lo,
3459 instance->mfi_internal_dma_obj.dma_cookie[0].dmac_address);
3460
3461 ddi_put32(cmd->frame_dma_obj.acc_handle,
3462 &initq_info->consumer_index_phys_addr_hi, 0);
3463 ddi_put32(cmd->frame_dma_obj.acc_handle,
3464 &initq_info->consumer_index_phys_addr_lo,
3465 instance->mfi_internal_dma_obj.dma_cookie[0].dmac_address + 4);
3466
3467 ddi_put32(cmd->frame_dma_obj.acc_handle,
3468 &initq_info->reply_queue_start_phys_addr_hi, 0);
3469 ddi_put32(cmd->frame_dma_obj.acc_handle,
3470 &initq_info->reply_queue_start_phys_addr_lo,
3471 instance->mfi_internal_dma_obj.dma_cookie[0].dmac_address + 8);
3472
3473 ddi_put8(cmd->frame_dma_obj.acc_handle,
3474 &init_frame->cmd, MFI_CMD_OP_INIT);
3475 ddi_put8(cmd->frame_dma_obj.acc_handle, &init_frame->cmd_status,
3476 MFI_CMD_STATUS_POLL_MODE);
3477 ddi_put16(cmd->frame_dma_obj.acc_handle, &init_frame->flags, 0);
3478 ddi_put32(cmd->frame_dma_obj.acc_handle,
3479 &init_frame->queue_info_new_phys_addr_lo,
3480 cmd->frame_phys_addr + 64);
3481 ddi_put32(cmd->frame_dma_obj.acc_handle,
3482 &init_frame->queue_info_new_phys_addr_hi, 0);
3483
3484
3485 /* fill driver version information */
3486 fill_up_drv_ver(&drv_ver_info);
3487
3488 /* allocate the driver version data transfer buffer */
3489 instance->drv_ver_dma_obj.size = sizeof (drv_ver_info.drv_ver);
3490 instance->drv_ver_dma_obj.dma_attr = mrsas_generic_dma_attr;
3491 instance->drv_ver_dma_obj.dma_attr.dma_attr_addr_hi = 0xFFFFFFFFU;
3492 instance->drv_ver_dma_obj.dma_attr.dma_attr_count_max = 0xFFFFFFFFU;
3493 instance->drv_ver_dma_obj.dma_attr.dma_attr_sgllen = 1;
3494 instance->drv_ver_dma_obj.dma_attr.dma_attr_align = 1;
3495
3496 if (mrsas_alloc_dma_obj(instance, &instance->drv_ver_dma_obj,
3497 (uchar_t)DDI_STRUCTURE_LE_ACC) != 1) {
3498 con_log(CL_ANN, (CE_WARN,
3499 "init_mfi : Could not allocate driver version buffer."));
3500 return (DDI_FAILURE);
3501 }
3502 /* copy driver version to dma buffer */
3503 (void) memset(instance->drv_ver_dma_obj.buffer, 0,
3504 sizeof (drv_ver_info.drv_ver));
3505 ddi_rep_put8(cmd->frame_dma_obj.acc_handle,
3506 (uint8_t *)drv_ver_info.drv_ver,
3507 (uint8_t *)instance->drv_ver_dma_obj.buffer,
3508 sizeof (drv_ver_info.drv_ver), DDI_DEV_AUTOINCR);
3509
3510
3511 /* copy driver version physical address to init frame */
3512 ddi_put64(cmd->frame_dma_obj.acc_handle, &init_frame->driverversion,
3513 instance->drv_ver_dma_obj.dma_cookie[0].dmac_address);
3514
3515 ddi_put32(cmd->frame_dma_obj.acc_handle, &init_frame->data_xfer_len,
3516 sizeof (struct mrsas_init_queue_info));
3517
3518 cmd->frame_count = 1;
3519
3520 *cmd_ptr = cmd;
3521
3522 return (DDI_SUCCESS);
3523 }
3524
3525
3526 /*
3527 * mrsas_init_adapter_ppc - Initialize MFI interface adapter.
3528 */
3529 int
mrsas_init_adapter_ppc(struct mrsas_instance * instance)3530 mrsas_init_adapter_ppc(struct mrsas_instance *instance)
3531 {
3532 struct mrsas_cmd *cmd;
3533
3534 /*
3535 * allocate memory for mfi adapter(cmd pool, individual commands, mfi
3536 * frames etc
3537 */
3538 if (alloc_space_for_mfi(instance) != DDI_SUCCESS) {
3539 con_log(CL_ANN, (CE_NOTE,
3540 "Error, failed to allocate memory for MFI adapter"));
3541 return (DDI_FAILURE);
3542 }
3543
3544 /* Build INIT command */
3545 cmd = mrsas_get_mfi_pkt(instance);
3546 if (cmd == NULL) {
3547 DTRACE_PROBE2(init_adapter_mfi_err, uint16_t,
3548 instance->fw_outstanding, uint16_t, instance->max_fw_cmds);
3549 return (DDI_FAILURE);
3550 }
3551
3552 if (mrsas_build_init_cmd(instance, &cmd) != DDI_SUCCESS) {
3553 con_log(CL_ANN,
3554 (CE_NOTE, "Error, failed to build INIT command"));
3555
3556 goto fail_undo_alloc_mfi_space;
3557 }
3558
3559 /*
3560 * Disable interrupt before sending init frame ( see linux driver code)
3561 * send INIT MFI frame in polled mode
3562 */
3563 if (instance->func_ptr->issue_cmd_in_poll_mode(instance, cmd)) {
3564 con_log(CL_ANN, (CE_WARN, "failed to init firmware"));
3565 goto fail_fw_init;
3566 }
3567
3568 if (mrsas_common_check(instance, cmd) != DDI_SUCCESS)
3569 goto fail_fw_init;
3570 mrsas_return_mfi_pkt(instance, cmd);
3571
3572 if (ctio_enable &&
3573 (instance->func_ptr->read_fw_status_reg(instance) & 0x04000000)) {
3574 con_log(CL_ANN, (CE_NOTE, "mr_sas: IEEE SGL's supported"));
3575 instance->flag_ieee = 1;
3576 } else {
3577 instance->flag_ieee = 0;
3578 }
3579
3580 ASSERT(!instance->skinny || instance->flag_ieee);
3581
3582 instance->unroll.alloc_space_mfi = 1;
3583 instance->unroll.verBuff = 1;
3584
3585 return (DDI_SUCCESS);
3586
3587
3588 fail_fw_init:
3589 (void) mrsas_free_dma_obj(instance, instance->drv_ver_dma_obj);
3590
3591 fail_undo_alloc_mfi_space:
3592 mrsas_return_mfi_pkt(instance, cmd);
3593 free_space_for_mfi(instance);
3594
3595 return (DDI_FAILURE);
3596
3597 }
3598
3599 /*
3600 * mrsas_init_adapter - Initialize adapter.
3601 */
3602 int
mrsas_init_adapter(struct mrsas_instance * instance)3603 mrsas_init_adapter(struct mrsas_instance *instance)
3604 {
3605 struct mrsas_ctrl_info ctrl_info;
3606
3607
3608 /* we expect the FW state to be READY */
3609 if (mfi_state_transition_to_ready(instance)) {
3610 con_log(CL_ANN, (CE_WARN, "mr_sas: F/W is not ready"));
3611 return (DDI_FAILURE);
3612 }
3613
3614 /* get various operational parameters from status register */
3615 instance->max_num_sge =
3616 (instance->func_ptr->read_fw_status_reg(instance) &
3617 0xFF0000) >> 0x10;
3618 instance->max_num_sge =
3619 (instance->max_num_sge > MRSAS_MAX_SGE_CNT) ?
3620 MRSAS_MAX_SGE_CNT : instance->max_num_sge;
3621
3622 /*
3623 * Reduce the max supported cmds by 1. This is to ensure that the
3624 * reply_q_sz (1 more than the max cmd that driver may send)
3625 * does not exceed max cmds that the FW can support
3626 */
3627 instance->max_fw_cmds =
3628 instance->func_ptr->read_fw_status_reg(instance) & 0xFFFF;
3629 instance->max_fw_cmds = instance->max_fw_cmds - 1;
3630
3631
3632
3633 /* Initialize adapter */
3634 if (instance->func_ptr->init_adapter(instance) != DDI_SUCCESS) {
3635 con_log(CL_ANN,
3636 (CE_WARN, "mr_sas: could not initialize adapter"));
3637 return (DDI_FAILURE);
3638 }
3639
3640 /* gather misc FW related information */
3641 instance->disable_online_ctrl_reset = 0;
3642
3643 if (!get_ctrl_info(instance, &ctrl_info)) {
3644 instance->max_sectors_per_req = ctrl_info.max_request_size;
3645 con_log(CL_ANN1, (CE_NOTE,
3646 "product name %s ld present %d",
3647 ctrl_info.product_name, ctrl_info.ld_present_count));
3648 } else {
3649 instance->max_sectors_per_req = instance->max_num_sge *
3650 PAGESIZE / 512;
3651 }
3652
3653 if (ctrl_info.properties.on_off_properties & DISABLE_OCR_PROP_FLAG)
3654 instance->disable_online_ctrl_reset = 1;
3655
3656 return (DDI_SUCCESS);
3657
3658 }
3659
3660
3661
3662 static int
mrsas_issue_init_mfi(struct mrsas_instance * instance)3663 mrsas_issue_init_mfi(struct mrsas_instance *instance)
3664 {
3665 struct mrsas_cmd *cmd;
3666 struct mrsas_init_frame *init_frame;
3667 struct mrsas_init_queue_info *initq_info;
3668
3669 /*
3670 * Prepare a init frame. Note the init frame points to queue info
3671 * structure. Each frame has SGL allocated after first 64 bytes. For
3672 * this frame - since we don't need any SGL - we use SGL's space as
3673 * queue info structure
3674 */
3675 con_log(CL_ANN1, (CE_NOTE,
3676 "mrsas_issue_init_mfi: entry\n"));
3677 cmd = get_mfi_app_pkt(instance);
3678
3679 if (!cmd) {
3680 con_log(CL_ANN1, (CE_WARN,
3681 "mrsas_issue_init_mfi: get_pkt failed\n"));
3682 return (DDI_FAILURE);
3683 }
3684
3685 /* Clear the frame buffer and assign back the context id */
3686 (void) memset((char *)&cmd->frame[0], 0, sizeof (union mrsas_frame));
3687 ddi_put32(cmd->frame_dma_obj.acc_handle, &cmd->frame->hdr.context,
3688 cmd->index);
3689
3690 init_frame = (struct mrsas_init_frame *)cmd->frame;
3691 initq_info = (struct mrsas_init_queue_info *)
3692 ((unsigned long)init_frame + 64);
3693
3694 (void) memset(init_frame, 0, MRMFI_FRAME_SIZE);
3695 (void) memset(initq_info, 0, sizeof (struct mrsas_init_queue_info));
3696
3697 ddi_put32(cmd->frame_dma_obj.acc_handle, &initq_info->init_flags, 0);
3698
3699 ddi_put32(cmd->frame_dma_obj.acc_handle,
3700 &initq_info->reply_queue_entries, instance->max_fw_cmds + 1);
3701 ddi_put32(cmd->frame_dma_obj.acc_handle,
3702 &initq_info->producer_index_phys_addr_hi, 0);
3703 ddi_put32(cmd->frame_dma_obj.acc_handle,
3704 &initq_info->producer_index_phys_addr_lo,
3705 instance->mfi_internal_dma_obj.dma_cookie[0].dmac_address);
3706 ddi_put32(cmd->frame_dma_obj.acc_handle,
3707 &initq_info->consumer_index_phys_addr_hi, 0);
3708 ddi_put32(cmd->frame_dma_obj.acc_handle,
3709 &initq_info->consumer_index_phys_addr_lo,
3710 instance->mfi_internal_dma_obj.dma_cookie[0].dmac_address + 4);
3711
3712 ddi_put32(cmd->frame_dma_obj.acc_handle,
3713 &initq_info->reply_queue_start_phys_addr_hi, 0);
3714 ddi_put32(cmd->frame_dma_obj.acc_handle,
3715 &initq_info->reply_queue_start_phys_addr_lo,
3716 instance->mfi_internal_dma_obj.dma_cookie[0].dmac_address + 8);
3717
3718 ddi_put8(cmd->frame_dma_obj.acc_handle,
3719 &init_frame->cmd, MFI_CMD_OP_INIT);
3720 ddi_put8(cmd->frame_dma_obj.acc_handle, &init_frame->cmd_status,
3721 MFI_CMD_STATUS_POLL_MODE);
3722 ddi_put16(cmd->frame_dma_obj.acc_handle, &init_frame->flags, 0);
3723 ddi_put32(cmd->frame_dma_obj.acc_handle,
3724 &init_frame->queue_info_new_phys_addr_lo,
3725 cmd->frame_phys_addr + 64);
3726 ddi_put32(cmd->frame_dma_obj.acc_handle,
3727 &init_frame->queue_info_new_phys_addr_hi, 0);
3728
3729 ddi_put32(cmd->frame_dma_obj.acc_handle, &init_frame->data_xfer_len,
3730 sizeof (struct mrsas_init_queue_info));
3731
3732 cmd->frame_count = 1;
3733
3734 /* issue the init frame in polled mode */
3735 if (instance->func_ptr->issue_cmd_in_poll_mode(instance, cmd)) {
3736 con_log(CL_ANN1, (CE_WARN,
3737 "mrsas_issue_init_mfi():failed to "
3738 "init firmware"));
3739 return_mfi_app_pkt(instance, cmd);
3740 return (DDI_FAILURE);
3741 }
3742
3743 if (mrsas_common_check(instance, cmd) != DDI_SUCCESS) {
3744 return_mfi_app_pkt(instance, cmd);
3745 return (DDI_FAILURE);
3746 }
3747
3748 return_mfi_app_pkt(instance, cmd);
3749 con_log(CL_ANN1, (CE_CONT, "mrsas_issue_init_mfi: Done"));
3750
3751 return (DDI_SUCCESS);
3752 }
3753 /*
3754 * mfi_state_transition_to_ready : Move the FW to READY state
3755 *
3756 * @reg_set : MFI register set
3757 */
3758 int
mfi_state_transition_to_ready(struct mrsas_instance * instance)3759 mfi_state_transition_to_ready(struct mrsas_instance *instance)
3760 {
3761 int i;
3762 uint8_t max_wait;
3763 uint32_t fw_ctrl = 0;
3764 uint32_t fw_state;
3765 uint32_t cur_state;
3766 uint32_t cur_abs_reg_val;
3767 uint32_t prev_abs_reg_val;
3768 uint32_t status;
3769
3770 cur_abs_reg_val =
3771 instance->func_ptr->read_fw_status_reg(instance);
3772 fw_state =
3773 cur_abs_reg_val & MFI_STATE_MASK;
3774 con_log(CL_ANN1, (CE_CONT,
3775 "mfi_state_transition_to_ready:FW state = 0x%x", fw_state));
3776
3777 while (fw_state != MFI_STATE_READY) {
3778 con_log(CL_ANN, (CE_CONT,
3779 "mfi_state_transition_to_ready:FW state%x", fw_state));
3780
3781 switch (fw_state) {
3782 case MFI_STATE_FAULT:
3783 con_log(CL_ANN, (CE_NOTE,
3784 "mr_sas: FW in FAULT state!!"));
3785
3786 return (ENODEV);
3787 case MFI_STATE_WAIT_HANDSHAKE:
3788 /* set the CLR bit in IMR0 */
3789 con_log(CL_ANN1, (CE_NOTE,
3790 "mr_sas: FW waiting for HANDSHAKE"));
3791 /*
3792 * PCI_Hot Plug: MFI F/W requires
3793 * (MFI_INIT_CLEAR_HANDSHAKE|MFI_INIT_HOTPLUG)
3794 * to be set
3795 */
3796 /* WR_IB_MSG_0(MFI_INIT_CLEAR_HANDSHAKE, instance); */
3797 if (!instance->tbolt && !instance->skinny) {
3798 WR_IB_DOORBELL(MFI_INIT_CLEAR_HANDSHAKE |
3799 MFI_INIT_HOTPLUG, instance);
3800 } else {
3801 WR_RESERVED0_REGISTER(MFI_INIT_CLEAR_HANDSHAKE |
3802 MFI_INIT_HOTPLUG, instance);
3803 }
3804 max_wait = (instance->tbolt == 1) ? 180 : 2;
3805 cur_state = MFI_STATE_WAIT_HANDSHAKE;
3806 break;
3807 case MFI_STATE_BOOT_MESSAGE_PENDING:
3808 /* set the CLR bit in IMR0 */
3809 con_log(CL_ANN1, (CE_NOTE,
3810 "mr_sas: FW state boot message pending"));
3811 /*
3812 * PCI_Hot Plug: MFI F/W requires
3813 * (MFI_INIT_CLEAR_HANDSHAKE|MFI_INIT_HOTPLUG)
3814 * to be set
3815 */
3816 if (!instance->tbolt && !instance->skinny) {
3817 WR_IB_DOORBELL(MFI_INIT_HOTPLUG, instance);
3818 } else {
3819 WR_RESERVED0_REGISTER(MFI_INIT_HOTPLUG,
3820 instance);
3821 }
3822 max_wait = (instance->tbolt == 1) ? 180 : 10;
3823 cur_state = MFI_STATE_BOOT_MESSAGE_PENDING;
3824 break;
3825 case MFI_STATE_OPERATIONAL:
3826 /* bring it to READY state; assuming max wait 2 secs */
3827 instance->func_ptr->disable_intr(instance);
3828 con_log(CL_ANN1, (CE_NOTE,
3829 "mr_sas: FW in OPERATIONAL state"));
3830 /*
3831 * PCI_Hot Plug: MFI F/W requires
3832 * (MFI_INIT_READY | MFI_INIT_MFIMODE | MFI_INIT_ABORT)
3833 * to be set
3834 */
3835 /* WR_IB_DOORBELL(MFI_INIT_READY, instance); */
3836 if (!instance->tbolt && !instance->skinny) {
3837 WR_IB_DOORBELL(MFI_RESET_FLAGS, instance);
3838 } else {
3839 WR_RESERVED0_REGISTER(MFI_RESET_FLAGS,
3840 instance);
3841
3842 for (i = 0; i < (10 * 1000); i++) {
3843 status =
3844 RD_RESERVED0_REGISTER(instance);
3845 if (status & 1) {
3846 delay(1 *
3847 drv_usectohz(MILLISEC));
3848 } else {
3849 break;
3850 }
3851 }
3852
3853 }
3854 max_wait = (instance->tbolt == 1) ? 180 : 10;
3855 cur_state = MFI_STATE_OPERATIONAL;
3856 break;
3857 case MFI_STATE_UNDEFINED:
3858 /* this state should not last for more than 2 seconds */
3859 con_log(CL_ANN1, (CE_NOTE, "FW state undefined"));
3860
3861 max_wait = (instance->tbolt == 1) ? 180 : 2;
3862 cur_state = MFI_STATE_UNDEFINED;
3863 break;
3864 case MFI_STATE_BB_INIT:
3865 max_wait = (instance->tbolt == 1) ? 180 : 2;
3866 cur_state = MFI_STATE_BB_INIT;
3867 break;
3868 case MFI_STATE_FW_INIT:
3869 max_wait = (instance->tbolt == 1) ? 180 : 2;
3870 cur_state = MFI_STATE_FW_INIT;
3871 break;
3872 case MFI_STATE_FW_INIT_2:
3873 max_wait = 180;
3874 cur_state = MFI_STATE_FW_INIT_2;
3875 break;
3876 case MFI_STATE_DEVICE_SCAN:
3877 max_wait = 180;
3878 cur_state = MFI_STATE_DEVICE_SCAN;
3879 prev_abs_reg_val = cur_abs_reg_val;
3880 con_log(CL_NONE, (CE_NOTE,
3881 "Device scan in progress ...\n"));
3882 break;
3883 case MFI_STATE_FLUSH_CACHE:
3884 max_wait = 180;
3885 cur_state = MFI_STATE_FLUSH_CACHE;
3886 break;
3887 default:
3888 con_log(CL_ANN1, (CE_NOTE,
3889 "mr_sas: Unknown state 0x%x", fw_state));
3890 return (ENODEV);
3891 }
3892
3893 /* the cur_state should not last for more than max_wait secs */
3894 for (i = 0; i < (max_wait * MILLISEC); i++) {
3895 /* fw_state = RD_OB_MSG_0(instance) & MFI_STATE_MASK; */
3896 cur_abs_reg_val =
3897 instance->func_ptr->read_fw_status_reg(instance);
3898 fw_state = cur_abs_reg_val & MFI_STATE_MASK;
3899
3900 if (fw_state == cur_state) {
3901 delay(1 * drv_usectohz(MILLISEC));
3902 } else {
3903 break;
3904 }
3905 }
3906 if (fw_state == MFI_STATE_DEVICE_SCAN) {
3907 if (prev_abs_reg_val != cur_abs_reg_val) {
3908 continue;
3909 }
3910 }
3911
3912 /* return error if fw_state hasn't changed after max_wait */
3913 if (fw_state == cur_state) {
3914 con_log(CL_ANN1, (CE_WARN,
3915 "FW state hasn't changed in %d secs", max_wait));
3916 return (ENODEV);
3917 }
3918 };
3919
3920 /* This may also need to apply to Skinny, but for now, don't worry. */
3921 if (!instance->tbolt && !instance->skinny) {
3922 fw_ctrl = RD_IB_DOORBELL(instance);
3923 con_log(CL_ANN1, (CE_CONT,
3924 "mfi_state_transition_to_ready:FW ctrl = 0x%x", fw_ctrl));
3925
3926 /*
3927 * Write 0xF to the doorbell register to do the following.
3928 * - Abort all outstanding commands (bit 0).
3929 * - Transition from OPERATIONAL to READY state (bit 1).
3930 * - Discard (possible) low MFA posted in 64-bit mode (bit-2).
3931 * - Set to release FW to continue running (i.e. BIOS handshake
3932 * (bit 3).
3933 */
3934 WR_IB_DOORBELL(0xF, instance);
3935 }
3936
3937 if (mrsas_check_acc_handle(instance->regmap_handle) != DDI_SUCCESS) {
3938 return (EIO);
3939 }
3940
3941 return (DDI_SUCCESS);
3942 }
3943
3944 /*
3945 * get_seq_num
3946 */
3947 static int
get_seq_num(struct mrsas_instance * instance,struct mrsas_evt_log_info * eli)3948 get_seq_num(struct mrsas_instance *instance,
3949 struct mrsas_evt_log_info *eli)
3950 {
3951 int ret = DDI_SUCCESS;
3952
3953 dma_obj_t dcmd_dma_obj;
3954 struct mrsas_cmd *cmd;
3955 struct mrsas_dcmd_frame *dcmd;
3956 struct mrsas_evt_log_info *eli_tmp;
3957 if (instance->tbolt) {
3958 cmd = get_raid_msg_mfi_pkt(instance);
3959 } else {
3960 cmd = mrsas_get_mfi_pkt(instance);
3961 }
3962
3963 if (!cmd) {
3964 dev_err(instance->dip, CE_WARN, "failed to get a cmd");
3965 DTRACE_PROBE2(seq_num_mfi_err, uint16_t,
3966 instance->fw_outstanding, uint16_t, instance->max_fw_cmds);
3967 return (ENOMEM);
3968 }
3969
3970 /* Clear the frame buffer and assign back the context id */
3971 (void) memset((char *)&cmd->frame[0], 0, sizeof (union mrsas_frame));
3972 ddi_put32(cmd->frame_dma_obj.acc_handle, &cmd->frame->hdr.context,
3973 cmd->index);
3974
3975 dcmd = &cmd->frame->dcmd;
3976
3977 /* allocate the data transfer buffer */
3978 dcmd_dma_obj.size = sizeof (struct mrsas_evt_log_info);
3979 dcmd_dma_obj.dma_attr = mrsas_generic_dma_attr;
3980 dcmd_dma_obj.dma_attr.dma_attr_addr_hi = 0xFFFFFFFFU;
3981 dcmd_dma_obj.dma_attr.dma_attr_count_max = 0xFFFFFFFFU;
3982 dcmd_dma_obj.dma_attr.dma_attr_sgllen = 1;
3983 dcmd_dma_obj.dma_attr.dma_attr_align = 1;
3984
3985 if (mrsas_alloc_dma_obj(instance, &dcmd_dma_obj,
3986 (uchar_t)DDI_STRUCTURE_LE_ACC) != 1) {
3987 dev_err(instance->dip, CE_WARN,
3988 "get_seq_num: could not allocate data transfer buffer.");
3989 return (DDI_FAILURE);
3990 }
3991
3992 (void) memset(dcmd_dma_obj.buffer, 0,
3993 sizeof (struct mrsas_evt_log_info));
3994
3995 (void) memset(dcmd->mbox.b, 0, DCMD_MBOX_SZ);
3996
3997 ddi_put8(cmd->frame_dma_obj.acc_handle, &dcmd->cmd, MFI_CMD_OP_DCMD);
3998 ddi_put8(cmd->frame_dma_obj.acc_handle, &dcmd->cmd_status, 0);
3999 ddi_put8(cmd->frame_dma_obj.acc_handle, &dcmd->sge_count, 1);
4000 ddi_put16(cmd->frame_dma_obj.acc_handle, &dcmd->flags,
4001 MFI_FRAME_DIR_READ);
4002 ddi_put16(cmd->frame_dma_obj.acc_handle, &dcmd->timeout, 0);
4003 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->data_xfer_len,
4004 sizeof (struct mrsas_evt_log_info));
4005 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->opcode,
4006 MR_DCMD_CTRL_EVENT_GET_INFO);
4007 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->sgl.sge32[0].length,
4008 sizeof (struct mrsas_evt_log_info));
4009 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->sgl.sge32[0].phys_addr,
4010 dcmd_dma_obj.dma_cookie[0].dmac_address);
4011
4012 cmd->sync_cmd = MRSAS_TRUE;
4013 cmd->frame_count = 1;
4014
4015 if (instance->tbolt) {
4016 mr_sas_tbolt_build_mfi_cmd(instance, cmd);
4017 }
4018
4019 if (instance->func_ptr->issue_cmd_in_sync_mode(instance, cmd)) {
4020 dev_err(instance->dip, CE_WARN, "get_seq_num: "
4021 "failed to issue MRSAS_DCMD_CTRL_EVENT_GET_INFO");
4022 ret = DDI_FAILURE;
4023 } else {
4024 eli_tmp = (struct mrsas_evt_log_info *)dcmd_dma_obj.buffer;
4025 eli->newest_seq_num = ddi_get32(cmd->frame_dma_obj.acc_handle,
4026 &eli_tmp->newest_seq_num);
4027 ret = DDI_SUCCESS;
4028 }
4029
4030 if (mrsas_free_dma_obj(instance, dcmd_dma_obj) != DDI_SUCCESS)
4031 ret = DDI_FAILURE;
4032
4033 if (instance->tbolt) {
4034 return_raid_msg_mfi_pkt(instance, cmd);
4035 } else {
4036 mrsas_return_mfi_pkt(instance, cmd);
4037 }
4038
4039 return (ret);
4040 }
4041
4042 /*
4043 * start_mfi_aen
4044 */
4045 static int
start_mfi_aen(struct mrsas_instance * instance)4046 start_mfi_aen(struct mrsas_instance *instance)
4047 {
4048 int ret = 0;
4049
4050 struct mrsas_evt_log_info eli;
4051 union mrsas_evt_class_locale class_locale;
4052
4053 /* get the latest sequence number from FW */
4054 (void) memset(&eli, 0, sizeof (struct mrsas_evt_log_info));
4055
4056 if (get_seq_num(instance, &eli)) {
4057 dev_err(instance->dip, CE_WARN,
4058 "start_mfi_aen: failed to get seq num");
4059 return (-1);
4060 }
4061
4062 /* register AEN with FW for latest sequence number plus 1 */
4063 class_locale.members.reserved = 0;
4064 class_locale.members.locale = LE_16(MR_EVT_LOCALE_ALL);
4065 class_locale.members.class = MR_EVT_CLASS_INFO;
4066 class_locale.word = LE_32(class_locale.word);
4067 ret = register_mfi_aen(instance, eli.newest_seq_num + 1,
4068 class_locale.word);
4069
4070 if (ret) {
4071 dev_err(instance->dip, CE_WARN,
4072 "start_mfi_aen: aen registration failed");
4073 return (-1);
4074 }
4075
4076
4077 return (ret);
4078 }
4079
4080 /*
4081 * flush_cache
4082 */
4083 static void
flush_cache(struct mrsas_instance * instance)4084 flush_cache(struct mrsas_instance *instance)
4085 {
4086 struct mrsas_cmd *cmd = NULL;
4087 struct mrsas_dcmd_frame *dcmd;
4088 if (instance->tbolt) {
4089 cmd = get_raid_msg_mfi_pkt(instance);
4090 } else {
4091 cmd = mrsas_get_mfi_pkt(instance);
4092 }
4093
4094 if (!cmd) {
4095 con_log(CL_ANN1, (CE_WARN,
4096 "flush_cache():Failed to get a cmd for flush_cache"));
4097 DTRACE_PROBE2(flush_cache_err, uint16_t,
4098 instance->fw_outstanding, uint16_t, instance->max_fw_cmds);
4099 return;
4100 }
4101
4102 /* Clear the frame buffer and assign back the context id */
4103 (void) memset((char *)&cmd->frame[0], 0, sizeof (union mrsas_frame));
4104 ddi_put32(cmd->frame_dma_obj.acc_handle, &cmd->frame->hdr.context,
4105 cmd->index);
4106
4107 dcmd = &cmd->frame->dcmd;
4108
4109 (void) memset(dcmd->mbox.b, 0, DCMD_MBOX_SZ);
4110
4111 ddi_put8(cmd->frame_dma_obj.acc_handle, &dcmd->cmd, MFI_CMD_OP_DCMD);
4112 ddi_put8(cmd->frame_dma_obj.acc_handle, &dcmd->cmd_status, 0x0);
4113 ddi_put8(cmd->frame_dma_obj.acc_handle, &dcmd->sge_count, 0);
4114 ddi_put16(cmd->frame_dma_obj.acc_handle, &dcmd->flags,
4115 MFI_FRAME_DIR_NONE);
4116 ddi_put16(cmd->frame_dma_obj.acc_handle, &dcmd->timeout, 0);
4117 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->data_xfer_len, 0);
4118 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->opcode,
4119 MR_DCMD_CTRL_CACHE_FLUSH);
4120 ddi_put8(cmd->frame_dma_obj.acc_handle, &dcmd->mbox.b[0],
4121 MR_FLUSH_CTRL_CACHE | MR_FLUSH_DISK_CACHE);
4122
4123 cmd->frame_count = 1;
4124
4125 if (instance->tbolt) {
4126 mr_sas_tbolt_build_mfi_cmd(instance, cmd);
4127 }
4128
4129 if (instance->func_ptr->issue_cmd_in_poll_mode(instance, cmd)) {
4130 con_log(CL_ANN1, (CE_WARN,
4131 "flush_cache: failed to issue MFI_DCMD_CTRL_CACHE_FLUSH"));
4132 }
4133 con_log(CL_ANN1, (CE_CONT, "flush_cache done"));
4134 if (instance->tbolt) {
4135 return_raid_msg_mfi_pkt(instance, cmd);
4136 } else {
4137 mrsas_return_mfi_pkt(instance, cmd);
4138 }
4139
4140 }
4141
4142 /*
4143 * service_mfi_aen- Completes an AEN command
4144 * @instance: Adapter soft state
4145 * @cmd: Command to be completed
4146 *
4147 */
4148 void
service_mfi_aen(struct mrsas_instance * instance,struct mrsas_cmd * cmd)4149 service_mfi_aen(struct mrsas_instance *instance, struct mrsas_cmd *cmd)
4150 {
4151 uint32_t seq_num;
4152 struct mrsas_evt_detail *evt_detail =
4153 (struct mrsas_evt_detail *)instance->mfi_evt_detail_obj.buffer;
4154 int rval = 0;
4155 int tgt = 0;
4156 uint8_t dtype;
4157 mrsas_pd_address_t *pd_addr;
4158 ddi_acc_handle_t acc_handle;
4159
4160 con_log(CL_ANN, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
4161
4162 acc_handle = cmd->frame_dma_obj.acc_handle;
4163 cmd->cmd_status = ddi_get8(acc_handle, &cmd->frame->io.cmd_status);
4164 if (cmd->cmd_status == ENODATA) {
4165 cmd->cmd_status = 0;
4166 }
4167
4168 /*
4169 * log the MFI AEN event to the sysevent queue so that
4170 * application will get noticed
4171 */
4172 if (ddi_log_sysevent(instance->dip, DDI_VENDOR_LSI, "LSIMEGA", "SAS",
4173 NULL, NULL, DDI_NOSLEEP) != DDI_SUCCESS) {
4174 int instance_no = ddi_get_instance(instance->dip);
4175 con_log(CL_ANN, (CE_WARN,
4176 "mr_sas%d: Failed to log AEN event", instance_no));
4177 }
4178 /*
4179 * Check for any ld devices that has changed state. i.e. online
4180 * or offline.
4181 */
4182 con_log(CL_ANN1, (CE_CONT,
4183 "AEN: code = %x class = %x locale = %x args = %x",
4184 ddi_get32(acc_handle, &evt_detail->code),
4185 evt_detail->cl.members.class,
4186 ddi_get16(acc_handle, &evt_detail->cl.members.locale),
4187 ddi_get8(acc_handle, &evt_detail->arg_type)));
4188
4189 switch (ddi_get32(acc_handle, &evt_detail->code)) {
4190 case MR_EVT_CFG_CLEARED: {
4191 for (tgt = 0; tgt < MRDRV_MAX_LD; tgt++) {
4192 if (instance->mr_ld_list[tgt].dip != NULL) {
4193 mutex_enter(&instance->config_dev_mtx);
4194 instance->mr_ld_list[tgt].flag =
4195 (uint8_t)~MRDRV_TGT_VALID;
4196 mutex_exit(&instance->config_dev_mtx);
4197 rval = mrsas_service_evt(instance, tgt, 0,
4198 MRSAS_EVT_UNCONFIG_TGT, 0);
4199 con_log(CL_ANN1, (CE_WARN,
4200 "mr_sas: CFG CLEARED AEN rval = %d "
4201 "tgt id = %d", rval, tgt));
4202 }
4203 }
4204 break;
4205 }
4206
4207 case MR_EVT_LD_DELETED: {
4208 tgt = ddi_get16(acc_handle, &evt_detail->args.ld.target_id);
4209 mutex_enter(&instance->config_dev_mtx);
4210 instance->mr_ld_list[tgt].flag = (uint8_t)~MRDRV_TGT_VALID;
4211 mutex_exit(&instance->config_dev_mtx);
4212 rval = mrsas_service_evt(instance,
4213 ddi_get16(acc_handle, &evt_detail->args.ld.target_id), 0,
4214 MRSAS_EVT_UNCONFIG_TGT, 0);
4215 con_log(CL_ANN1, (CE_WARN, "mr_sas: LD DELETED AEN rval = %d "
4216 "tgt id = %d index = %d", rval,
4217 ddi_get16(acc_handle, &evt_detail->args.ld.target_id),
4218 ddi_get8(acc_handle, &evt_detail->args.ld.ld_index)));
4219 break;
4220 } /* End of MR_EVT_LD_DELETED */
4221
4222 case MR_EVT_LD_CREATED: {
4223 rval = mrsas_service_evt(instance,
4224 ddi_get16(acc_handle, &evt_detail->args.ld.target_id), 0,
4225 MRSAS_EVT_CONFIG_TGT, 0);
4226 con_log(CL_ANN1, (CE_WARN, "mr_sas: LD CREATED AEN rval = %d "
4227 "tgt id = %d index = %d", rval,
4228 ddi_get16(acc_handle, &evt_detail->args.ld.target_id),
4229 ddi_get8(acc_handle, &evt_detail->args.ld.ld_index)));
4230 break;
4231 } /* End of MR_EVT_LD_CREATED */
4232
4233 case MR_EVT_PD_REMOVED_EXT: {
4234 if (instance->tbolt || instance->skinny) {
4235 pd_addr = &evt_detail->args.pd_addr;
4236 dtype = pd_addr->scsi_dev_type;
4237 con_log(CL_DLEVEL1, (CE_NOTE,
4238 " MR_EVT_PD_REMOVED_EXT: dtype = %x,"
4239 " arg_type = %d ", dtype, evt_detail->arg_type));
4240 tgt = ddi_get16(acc_handle,
4241 &evt_detail->args.pd.device_id);
4242 mutex_enter(&instance->config_dev_mtx);
4243 instance->mr_tbolt_pd_list[tgt].flag =
4244 (uint8_t)~MRDRV_TGT_VALID;
4245 mutex_exit(&instance->config_dev_mtx);
4246 rval = mrsas_service_evt(instance, ddi_get16(
4247 acc_handle, &evt_detail->args.pd.device_id),
4248 1, MRSAS_EVT_UNCONFIG_TGT, 0);
4249 con_log(CL_ANN1, (CE_WARN, "mr_sas: PD_REMOVED:"
4250 "rval = %d tgt id = %d ", rval,
4251 ddi_get16(acc_handle,
4252 &evt_detail->args.pd.device_id)));
4253 }
4254 break;
4255 } /* End of MR_EVT_PD_REMOVED_EXT */
4256
4257 case MR_EVT_PD_INSERTED_EXT: {
4258 if (instance->tbolt || instance->skinny) {
4259 rval = mrsas_service_evt(instance,
4260 ddi_get16(acc_handle,
4261 &evt_detail->args.pd.device_id),
4262 1, MRSAS_EVT_CONFIG_TGT, 0);
4263 con_log(CL_ANN1, (CE_WARN, "mr_sas: PD_INSERTEDi_EXT:"
4264 "rval = %d tgt id = %d ", rval,
4265 ddi_get16(acc_handle,
4266 &evt_detail->args.pd.device_id)));
4267 }
4268 break;
4269 } /* End of MR_EVT_PD_INSERTED_EXT */
4270
4271 case MR_EVT_PD_STATE_CHANGE: {
4272 if (instance->tbolt || instance->skinny) {
4273 tgt = ddi_get16(acc_handle,
4274 &evt_detail->args.pd.device_id);
4275 if ((evt_detail->args.pd_state.prevState ==
4276 PD_SYSTEM) &&
4277 (evt_detail->args.pd_state.newState != PD_SYSTEM)) {
4278 mutex_enter(&instance->config_dev_mtx);
4279 instance->mr_tbolt_pd_list[tgt].flag =
4280 (uint8_t)~MRDRV_TGT_VALID;
4281 mutex_exit(&instance->config_dev_mtx);
4282 rval = mrsas_service_evt(instance,
4283 ddi_get16(acc_handle,
4284 &evt_detail->args.pd.device_id),
4285 1, MRSAS_EVT_UNCONFIG_TGT, 0);
4286 con_log(CL_ANN1, (CE_WARN, "mr_sas: PD_REMOVED:"
4287 "rval = %d tgt id = %d ", rval,
4288 ddi_get16(acc_handle,
4289 &evt_detail->args.pd.device_id)));
4290 break;
4291 }
4292 if ((evt_detail->args.pd_state.prevState
4293 == UNCONFIGURED_GOOD) &&
4294 (evt_detail->args.pd_state.newState == PD_SYSTEM)) {
4295 rval = mrsas_service_evt(instance,
4296 ddi_get16(acc_handle,
4297 &evt_detail->args.pd.device_id),
4298 1, MRSAS_EVT_CONFIG_TGT, 0);
4299 con_log(CL_ANN1, (CE_WARN,
4300 "mr_sas: PD_INSERTED: rval = %d "
4301 " tgt id = %d ", rval,
4302 ddi_get16(acc_handle,
4303 &evt_detail->args.pd.device_id)));
4304 break;
4305 }
4306 }
4307 break;
4308 }
4309
4310 } /* End of Main Switch */
4311
4312 /* get copy of seq_num and class/locale for re-registration */
4313 seq_num = ddi_get32(acc_handle, &evt_detail->seq_num);
4314 seq_num++;
4315 (void) memset(instance->mfi_evt_detail_obj.buffer, 0,
4316 sizeof (struct mrsas_evt_detail));
4317
4318 ddi_put8(acc_handle, &cmd->frame->dcmd.cmd_status, 0x0);
4319 ddi_put32(acc_handle, &cmd->frame->dcmd.mbox.w[0], seq_num);
4320
4321 instance->aen_seq_num = seq_num;
4322
4323 cmd->frame_count = 1;
4324
4325 cmd->retry_count_for_ocr = 0;
4326 cmd->drv_pkt_time = 0;
4327
4328 /* Issue the aen registration frame */
4329 instance->func_ptr->issue_cmd(cmd, instance);
4330 }
4331
4332 /*
4333 * complete_cmd_in_sync_mode - Completes an internal command
4334 * @instance: Adapter soft state
4335 * @cmd: Command to be completed
4336 *
4337 * The issue_cmd_in_sync_mode() function waits for a command to complete
4338 * after it issues a command. This function wakes up that waiting routine by
4339 * calling wake_up() on the wait queue.
4340 */
4341 static void
complete_cmd_in_sync_mode(struct mrsas_instance * instance,struct mrsas_cmd * cmd)4342 complete_cmd_in_sync_mode(struct mrsas_instance *instance,
4343 struct mrsas_cmd *cmd)
4344 {
4345 cmd->cmd_status = ddi_get8(cmd->frame_dma_obj.acc_handle,
4346 &cmd->frame->io.cmd_status);
4347
4348 cmd->sync_cmd = MRSAS_FALSE;
4349
4350 con_log(CL_ANN1, (CE_NOTE, "complete_cmd_in_sync_mode called %p \n",
4351 (void *)cmd));
4352
4353 mutex_enter(&instance->int_cmd_mtx);
4354 if (cmd->cmd_status == ENODATA) {
4355 cmd->cmd_status = 0;
4356 }
4357 cv_broadcast(&instance->int_cmd_cv);
4358 mutex_exit(&instance->int_cmd_mtx);
4359
4360 }
4361
4362 /*
4363 * Call this function inside mrsas_softintr.
4364 * mrsas_initiate_ocr_if_fw_is_faulty - Initiates OCR if FW status is faulty
4365 * @instance: Adapter soft state
4366 */
4367
4368 static uint32_t
mrsas_initiate_ocr_if_fw_is_faulty(struct mrsas_instance * instance)4369 mrsas_initiate_ocr_if_fw_is_faulty(struct mrsas_instance *instance)
4370 {
4371 uint32_t cur_abs_reg_val;
4372 uint32_t fw_state;
4373
4374 cur_abs_reg_val = instance->func_ptr->read_fw_status_reg(instance);
4375 fw_state = cur_abs_reg_val & MFI_STATE_MASK;
4376 if (fw_state == MFI_STATE_FAULT) {
4377 if (instance->disable_online_ctrl_reset == 1) {
4378 dev_err(instance->dip, CE_WARN,
4379 "mrsas_initiate_ocr_if_fw_is_faulty: "
4380 "FW in Fault state, detected in ISR: "
4381 "FW doesn't support ocr ");
4382
4383 return (ADAPTER_RESET_NOT_REQUIRED);
4384 } else {
4385 con_log(CL_ANN, (CE_NOTE,
4386 "mrsas_initiate_ocr_if_fw_is_faulty: FW in Fault "
4387 "state, detected in ISR: FW supports ocr "));
4388
4389 return (ADAPTER_RESET_REQUIRED);
4390 }
4391 }
4392
4393 return (ADAPTER_RESET_NOT_REQUIRED);
4394 }
4395
4396 /*
4397 * mrsas_softintr - The Software ISR
4398 * @param arg : HBA soft state
4399 *
4400 * called from high-level interrupt if hi-level interrupt are not there,
4401 * otherwise triggered as a soft interrupt
4402 */
4403 static uint_t
mrsas_softintr(struct mrsas_instance * instance)4404 mrsas_softintr(struct mrsas_instance *instance)
4405 {
4406 struct scsi_pkt *pkt;
4407 struct scsa_cmd *acmd;
4408 struct mrsas_cmd *cmd;
4409 struct mlist_head *pos, *next;
4410 mlist_t process_list;
4411 struct mrsas_header *hdr;
4412 struct scsi_arq_status *arqstat;
4413
4414 con_log(CL_ANN1, (CE_NOTE, "mrsas_softintr() called."));
4415
4416 ASSERT(instance);
4417
4418 mutex_enter(&instance->completed_pool_mtx);
4419
4420 if (mlist_empty(&instance->completed_pool_list)) {
4421 mutex_exit(&instance->completed_pool_mtx);
4422 return (DDI_INTR_CLAIMED);
4423 }
4424
4425 instance->softint_running = 1;
4426
4427 INIT_LIST_HEAD(&process_list);
4428 mlist_splice(&instance->completed_pool_list, &process_list);
4429 INIT_LIST_HEAD(&instance->completed_pool_list);
4430
4431 mutex_exit(&instance->completed_pool_mtx);
4432
4433 /* perform all callbacks first, before releasing the SCBs */
4434 mlist_for_each_safe(pos, next, &process_list) {
4435 cmd = mlist_entry(pos, struct mrsas_cmd, list);
4436
4437 /* syncronize the Cmd frame for the controller */
4438 (void) ddi_dma_sync(cmd->frame_dma_obj.dma_handle,
4439 0, 0, DDI_DMA_SYNC_FORCPU);
4440
4441 if (mrsas_check_dma_handle(cmd->frame_dma_obj.dma_handle) !=
4442 DDI_SUCCESS) {
4443 mrsas_fm_ereport(instance, DDI_FM_DEVICE_NO_RESPONSE);
4444 ddi_fm_service_impact(instance->dip, DDI_SERVICE_LOST);
4445 con_log(CL_ANN1, (CE_WARN,
4446 "mrsas_softintr: "
4447 "FMA check reports DMA handle failure"));
4448 return (DDI_INTR_CLAIMED);
4449 }
4450
4451 hdr = &cmd->frame->hdr;
4452
4453 /* remove the internal command from the process list */
4454 mlist_del_init(&cmd->list);
4455
4456 switch (ddi_get8(cmd->frame_dma_obj.acc_handle, &hdr->cmd)) {
4457 case MFI_CMD_OP_PD_SCSI:
4458 case MFI_CMD_OP_LD_SCSI:
4459 case MFI_CMD_OP_LD_READ:
4460 case MFI_CMD_OP_LD_WRITE:
4461 /*
4462 * MFI_CMD_OP_PD_SCSI and MFI_CMD_OP_LD_SCSI
4463 * could have been issued either through an
4464 * IO path or an IOCTL path. If it was via IOCTL,
4465 * we will send it to internal completion.
4466 */
4467 if (cmd->sync_cmd == MRSAS_TRUE) {
4468 complete_cmd_in_sync_mode(instance, cmd);
4469 break;
4470 }
4471
4472 /* regular commands */
4473 acmd = cmd->cmd;
4474 pkt = CMD2PKT(acmd);
4475
4476 if (acmd->cmd_flags & CFLAG_DMAVALID) {
4477 if (acmd->cmd_flags & CFLAG_CONSISTENT) {
4478 (void) ddi_dma_sync(acmd->cmd_dmahandle,
4479 acmd->cmd_dma_offset,
4480 acmd->cmd_dma_len,
4481 DDI_DMA_SYNC_FORCPU);
4482 }
4483 }
4484
4485 pkt->pkt_reason = CMD_CMPLT;
4486 pkt->pkt_statistics = 0;
4487 pkt->pkt_state = STATE_GOT_BUS
4488 | STATE_GOT_TARGET | STATE_SENT_CMD
4489 | STATE_XFERRED_DATA | STATE_GOT_STATUS;
4490
4491 con_log(CL_ANN, (CE_CONT,
4492 "CDB[0] = %x completed for %s: size %lx context %x",
4493 pkt->pkt_cdbp[0], ((acmd->islogical) ? "LD" : "PD"),
4494 acmd->cmd_dmacount, hdr->context));
4495 DTRACE_PROBE3(softintr_cdb, uint8_t, pkt->pkt_cdbp[0],
4496 uint_t, acmd->cmd_cdblen, ulong_t,
4497 acmd->cmd_dmacount);
4498
4499 if (pkt->pkt_cdbp[0] == SCMD_INQUIRY) {
4500 struct scsi_inquiry *inq;
4501
4502 if (acmd->cmd_dmacount != 0) {
4503 bp_mapin(acmd->cmd_buf);
4504 inq = (struct scsi_inquiry *)
4505 acmd->cmd_buf->b_un.b_addr;
4506
4507 if (hdr->cmd_status == MFI_STAT_OK) {
4508 display_scsi_inquiry(
4509 (caddr_t)inq);
4510 }
4511 }
4512 }
4513
4514 DTRACE_PROBE2(softintr_done, uint8_t, hdr->cmd,
4515 uint8_t, hdr->cmd_status);
4516
4517 switch (hdr->cmd_status) {
4518 case MFI_STAT_OK:
4519 pkt->pkt_scbp[0] = STATUS_GOOD;
4520 break;
4521 case MFI_STAT_LD_CC_IN_PROGRESS:
4522 case MFI_STAT_LD_RECON_IN_PROGRESS:
4523 pkt->pkt_scbp[0] = STATUS_GOOD;
4524 break;
4525 case MFI_STAT_LD_INIT_IN_PROGRESS:
4526 con_log(CL_ANN,
4527 (CE_WARN, "Initialization in Progress"));
4528 pkt->pkt_reason = CMD_TRAN_ERR;
4529
4530 break;
4531 case MFI_STAT_SCSI_DONE_WITH_ERROR:
4532 con_log(CL_ANN, (CE_CONT, "scsi_done error"));
4533
4534 pkt->pkt_reason = CMD_CMPLT;
4535 ((struct scsi_status *)
4536 pkt->pkt_scbp)->sts_chk = 1;
4537
4538 if (pkt->pkt_cdbp[0] == SCMD_TEST_UNIT_READY) {
4539 con_log(CL_ANN,
4540 (CE_WARN, "TEST_UNIT_READY fail"));
4541 } else {
4542 pkt->pkt_state |= STATE_ARQ_DONE;
4543 arqstat = (void *)(pkt->pkt_scbp);
4544 arqstat->sts_rqpkt_reason = CMD_CMPLT;
4545 arqstat->sts_rqpkt_resid = 0;
4546 arqstat->sts_rqpkt_state |=
4547 STATE_GOT_BUS | STATE_GOT_TARGET
4548 | STATE_SENT_CMD
4549 | STATE_XFERRED_DATA;
4550 *(uint8_t *)&arqstat->sts_rqpkt_status =
4551 STATUS_GOOD;
4552 ddi_rep_get8(
4553 cmd->frame_dma_obj.acc_handle,
4554 (uint8_t *)
4555 &(arqstat->sts_sensedata),
4556 cmd->sense,
4557 sizeof (struct scsi_extended_sense),
4558 DDI_DEV_AUTOINCR);
4559 }
4560 break;
4561 case MFI_STAT_LD_OFFLINE:
4562 case MFI_STAT_DEVICE_NOT_FOUND:
4563 con_log(CL_ANN, (CE_CONT,
4564 "mrsas_softintr:device not found error"));
4565 pkt->pkt_reason = CMD_DEV_GONE;
4566 pkt->pkt_statistics = STAT_DISCON;
4567 break;
4568 case MFI_STAT_LD_LBA_OUT_OF_RANGE:
4569 pkt->pkt_state |= STATE_ARQ_DONE;
4570 pkt->pkt_reason = CMD_CMPLT;
4571 ((struct scsi_status *)
4572 pkt->pkt_scbp)->sts_chk = 1;
4573
4574 arqstat = (void *)(pkt->pkt_scbp);
4575 arqstat->sts_rqpkt_reason = CMD_CMPLT;
4576 arqstat->sts_rqpkt_resid = 0;
4577 arqstat->sts_rqpkt_state |= STATE_GOT_BUS
4578 | STATE_GOT_TARGET | STATE_SENT_CMD
4579 | STATE_XFERRED_DATA;
4580 *(uint8_t *)&arqstat->sts_rqpkt_status =
4581 STATUS_GOOD;
4582
4583 arqstat->sts_sensedata.es_valid = 1;
4584 arqstat->sts_sensedata.es_key =
4585 KEY_ILLEGAL_REQUEST;
4586 arqstat->sts_sensedata.es_class =
4587 CLASS_EXTENDED_SENSE;
4588
4589 /*
4590 * LOGICAL BLOCK ADDRESS OUT OF RANGE:
4591 * ASC: 0x21h; ASCQ: 0x00h;
4592 */
4593 arqstat->sts_sensedata.es_add_code = 0x21;
4594 arqstat->sts_sensedata.es_qual_code = 0x00;
4595
4596 break;
4597
4598 default:
4599 con_log(CL_ANN, (CE_CONT, "Unknown status!"));
4600 pkt->pkt_reason = CMD_TRAN_ERR;
4601
4602 break;
4603 }
4604
4605 atomic_add_16(&instance->fw_outstanding, (-1));
4606
4607 (void) mrsas_common_check(instance, cmd);
4608
4609 if (acmd->cmd_dmahandle) {
4610 if (mrsas_check_dma_handle(
4611 acmd->cmd_dmahandle) != DDI_SUCCESS) {
4612 ddi_fm_service_impact(instance->dip,
4613 DDI_SERVICE_UNAFFECTED);
4614 pkt->pkt_reason = CMD_TRAN_ERR;
4615 pkt->pkt_statistics = 0;
4616 }
4617 }
4618
4619 mrsas_return_mfi_pkt(instance, cmd);
4620
4621 /* Call the callback routine */
4622 if (((pkt->pkt_flags & FLAG_NOINTR) == 0) &&
4623 pkt->pkt_comp) {
4624 (*pkt->pkt_comp)(pkt);
4625 }
4626
4627 break;
4628
4629 case MFI_CMD_OP_SMP:
4630 case MFI_CMD_OP_STP:
4631 complete_cmd_in_sync_mode(instance, cmd);
4632 break;
4633
4634 case MFI_CMD_OP_DCMD:
4635 /* see if got an event notification */
4636 if (ddi_get32(cmd->frame_dma_obj.acc_handle,
4637 &cmd->frame->dcmd.opcode) ==
4638 MR_DCMD_CTRL_EVENT_WAIT) {
4639 if ((instance->aen_cmd == cmd) &&
4640 (instance->aen_cmd->abort_aen)) {
4641 con_log(CL_ANN, (CE_WARN,
4642 "mrsas_softintr: "
4643 "aborted_aen returned"));
4644 } else {
4645 atomic_add_16(&instance->fw_outstanding,
4646 (-1));
4647 service_mfi_aen(instance, cmd);
4648 }
4649 } else {
4650 complete_cmd_in_sync_mode(instance, cmd);
4651 }
4652
4653 break;
4654
4655 case MFI_CMD_OP_ABORT:
4656 con_log(CL_ANN, (CE_NOTE, "MFI_CMD_OP_ABORT complete"));
4657 /*
4658 * MFI_CMD_OP_ABORT successfully completed
4659 * in the synchronous mode
4660 */
4661 complete_cmd_in_sync_mode(instance, cmd);
4662 break;
4663
4664 default:
4665 mrsas_fm_ereport(instance, DDI_FM_DEVICE_NO_RESPONSE);
4666 ddi_fm_service_impact(instance->dip, DDI_SERVICE_LOST);
4667
4668 if (cmd->pkt != NULL) {
4669 pkt = cmd->pkt;
4670 if (((pkt->pkt_flags & FLAG_NOINTR) == 0) &&
4671 pkt->pkt_comp) {
4672
4673 con_log(CL_ANN1, (CE_CONT, "posting to "
4674 "scsa cmd %p index %x pkt %p"
4675 "time %llx, default ", (void *)cmd,
4676 cmd->index, (void *)pkt,
4677 gethrtime()));
4678
4679 (*pkt->pkt_comp)(pkt);
4680
4681 }
4682 }
4683 con_log(CL_ANN, (CE_WARN, "Cmd type unknown !"));
4684 break;
4685 }
4686 }
4687
4688 instance->softint_running = 0;
4689
4690 return (DDI_INTR_CLAIMED);
4691 }
4692
4693 /*
4694 * mrsas_alloc_dma_obj
4695 *
4696 * Allocate the memory and other resources for an dma object.
4697 */
4698 int
mrsas_alloc_dma_obj(struct mrsas_instance * instance,dma_obj_t * obj,uchar_t endian_flags)4699 mrsas_alloc_dma_obj(struct mrsas_instance *instance, dma_obj_t *obj,
4700 uchar_t endian_flags)
4701 {
4702 int i;
4703 size_t alen = 0;
4704 uint_t cookie_cnt;
4705 struct ddi_device_acc_attr tmp_endian_attr;
4706
4707 tmp_endian_attr = endian_attr;
4708 tmp_endian_attr.devacc_attr_endian_flags = endian_flags;
4709 tmp_endian_attr.devacc_attr_access = DDI_DEFAULT_ACC;
4710
4711 i = ddi_dma_alloc_handle(instance->dip, &obj->dma_attr,
4712 DDI_DMA_SLEEP, NULL, &obj->dma_handle);
4713 if (i != DDI_SUCCESS) {
4714
4715 switch (i) {
4716 case DDI_DMA_BADATTR :
4717 con_log(CL_ANN, (CE_WARN,
4718 "Failed ddi_dma_alloc_handle- Bad attribute"));
4719 break;
4720 case DDI_DMA_NORESOURCES :
4721 con_log(CL_ANN, (CE_WARN,
4722 "Failed ddi_dma_alloc_handle- No Resources"));
4723 break;
4724 default :
4725 con_log(CL_ANN, (CE_WARN,
4726 "Failed ddi_dma_alloc_handle: "
4727 "unknown status %d", i));
4728 break;
4729 }
4730
4731 return (-1);
4732 }
4733
4734 if ((ddi_dma_mem_alloc(obj->dma_handle, obj->size, &tmp_endian_attr,
4735 DDI_DMA_RDWR | DDI_DMA_STREAMING, DDI_DMA_SLEEP, NULL,
4736 &obj->buffer, &alen, &obj->acc_handle) != DDI_SUCCESS) ||
4737 alen < obj->size) {
4738
4739 ddi_dma_free_handle(&obj->dma_handle);
4740
4741 con_log(CL_ANN, (CE_WARN, "Failed : ddi_dma_mem_alloc"));
4742
4743 return (-1);
4744 }
4745
4746 if (ddi_dma_addr_bind_handle(obj->dma_handle, NULL, obj->buffer,
4747 obj->size, DDI_DMA_RDWR | DDI_DMA_STREAMING, DDI_DMA_SLEEP,
4748 NULL, &obj->dma_cookie[0], &cookie_cnt) != DDI_SUCCESS) {
4749
4750 ddi_dma_mem_free(&obj->acc_handle);
4751 ddi_dma_free_handle(&obj->dma_handle);
4752
4753 con_log(CL_ANN, (CE_WARN, "Failed : ddi_dma_addr_bind_handle"));
4754
4755 return (-1);
4756 }
4757
4758 if (mrsas_check_dma_handle(obj->dma_handle) != DDI_SUCCESS) {
4759 ddi_fm_service_impact(instance->dip, DDI_SERVICE_LOST);
4760 return (-1);
4761 }
4762
4763 if (mrsas_check_acc_handle(obj->acc_handle) != DDI_SUCCESS) {
4764 ddi_fm_service_impact(instance->dip, DDI_SERVICE_LOST);
4765 return (-1);
4766 }
4767
4768 return (cookie_cnt);
4769 }
4770
4771 /*
4772 * mrsas_free_dma_obj(struct mrsas_instance *, dma_obj_t)
4773 *
4774 * De-allocate the memory and other resources for an dma object, which must
4775 * have been alloated by a previous call to mrsas_alloc_dma_obj()
4776 */
4777 int
mrsas_free_dma_obj(struct mrsas_instance * instance,dma_obj_t obj)4778 mrsas_free_dma_obj(struct mrsas_instance *instance, dma_obj_t obj)
4779 {
4780
4781 if ((obj.dma_handle == NULL) || (obj.acc_handle == NULL)) {
4782 return (DDI_SUCCESS);
4783 }
4784
4785 /*
4786 * NOTE: These check-handle functions fail if *_handle == NULL, but
4787 * this function succeeds because of the previous check.
4788 */
4789 if (mrsas_check_dma_handle(obj.dma_handle) != DDI_SUCCESS) {
4790 ddi_fm_service_impact(instance->dip, DDI_SERVICE_UNAFFECTED);
4791 return (DDI_FAILURE);
4792 }
4793
4794 if (mrsas_check_acc_handle(obj.acc_handle) != DDI_SUCCESS) {
4795 ddi_fm_service_impact(instance->dip, DDI_SERVICE_UNAFFECTED);
4796 return (DDI_FAILURE);
4797 }
4798
4799 (void) ddi_dma_unbind_handle(obj.dma_handle);
4800 ddi_dma_mem_free(&obj.acc_handle);
4801 ddi_dma_free_handle(&obj.dma_handle);
4802 obj.acc_handle = NULL;
4803 return (DDI_SUCCESS);
4804 }
4805
4806 /*
4807 * mrsas_dma_alloc(instance_t *, struct scsi_pkt *, struct buf *,
4808 * int, int (*)())
4809 *
4810 * Allocate dma resources for a new scsi command
4811 */
4812 int
mrsas_dma_alloc(struct mrsas_instance * instance,struct scsi_pkt * pkt,struct buf * bp,int flags,int (* callback)())4813 mrsas_dma_alloc(struct mrsas_instance *instance, struct scsi_pkt *pkt,
4814 struct buf *bp, int flags, int (*callback)())
4815 {
4816 int dma_flags;
4817 int (*cb)(caddr_t);
4818 int i;
4819
4820 ddi_dma_attr_t tmp_dma_attr = mrsas_generic_dma_attr;
4821 struct scsa_cmd *acmd = PKT2CMD(pkt);
4822
4823 acmd->cmd_buf = bp;
4824
4825 if (bp->b_flags & B_READ) {
4826 acmd->cmd_flags &= ~CFLAG_DMASEND;
4827 dma_flags = DDI_DMA_READ;
4828 } else {
4829 acmd->cmd_flags |= CFLAG_DMASEND;
4830 dma_flags = DDI_DMA_WRITE;
4831 }
4832
4833 if (flags & PKT_CONSISTENT) {
4834 acmd->cmd_flags |= CFLAG_CONSISTENT;
4835 dma_flags |= DDI_DMA_CONSISTENT;
4836 }
4837
4838 if (flags & PKT_DMA_PARTIAL) {
4839 dma_flags |= DDI_DMA_PARTIAL;
4840 }
4841
4842 dma_flags |= DDI_DMA_REDZONE;
4843
4844 cb = (callback == NULL_FUNC) ? DDI_DMA_DONTWAIT : DDI_DMA_SLEEP;
4845
4846 tmp_dma_attr.dma_attr_sgllen = instance->max_num_sge;
4847 tmp_dma_attr.dma_attr_addr_hi = 0xffffffffffffffffull;
4848 if (instance->tbolt) {
4849 /* OCR-RESET FIX */
4850 tmp_dma_attr.dma_attr_count_max =
4851 (U64)mrsas_tbolt_max_cap_maxxfer; /* limit to 256K */
4852 tmp_dma_attr.dma_attr_maxxfer =
4853 (U64)mrsas_tbolt_max_cap_maxxfer; /* limit to 256K */
4854 }
4855
4856 if ((i = ddi_dma_alloc_handle(instance->dip, &tmp_dma_attr,
4857 cb, 0, &acmd->cmd_dmahandle)) != DDI_SUCCESS) {
4858 switch (i) {
4859 case DDI_DMA_BADATTR:
4860 bioerror(bp, EFAULT);
4861 return (DDI_FAILURE);
4862
4863 case DDI_DMA_NORESOURCES:
4864 bioerror(bp, 0);
4865 return (DDI_FAILURE);
4866
4867 default:
4868 con_log(CL_ANN, (CE_PANIC, "ddi_dma_alloc_handle: "
4869 "impossible result (0x%x)", i));
4870 bioerror(bp, EFAULT);
4871 return (DDI_FAILURE);
4872 }
4873 }
4874
4875 i = ddi_dma_buf_bind_handle(acmd->cmd_dmahandle, bp, dma_flags,
4876 cb, 0, &acmd->cmd_dmacookies[0], &acmd->cmd_ncookies);
4877
4878 switch (i) {
4879 case DDI_DMA_PARTIAL_MAP:
4880 if ((dma_flags & DDI_DMA_PARTIAL) == 0) {
4881 con_log(CL_ANN, (CE_PANIC, "ddi_dma_buf_bind_handle: "
4882 "DDI_DMA_PARTIAL_MAP impossible"));
4883 goto no_dma_cookies;
4884 }
4885
4886 if (ddi_dma_numwin(acmd->cmd_dmahandle, &acmd->cmd_nwin) ==
4887 DDI_FAILURE) {
4888 con_log(CL_ANN, (CE_PANIC, "ddi_dma_numwin failed"));
4889 goto no_dma_cookies;
4890 }
4891
4892 if (ddi_dma_getwin(acmd->cmd_dmahandle, acmd->cmd_curwin,
4893 &acmd->cmd_dma_offset, &acmd->cmd_dma_len,
4894 &acmd->cmd_dmacookies[0], &acmd->cmd_ncookies) ==
4895 DDI_FAILURE) {
4896
4897 con_log(CL_ANN, (CE_PANIC, "ddi_dma_getwin failed"));
4898 goto no_dma_cookies;
4899 }
4900
4901 goto get_dma_cookies;
4902 case DDI_DMA_MAPPED:
4903 acmd->cmd_nwin = 1;
4904 acmd->cmd_dma_len = 0;
4905 acmd->cmd_dma_offset = 0;
4906
4907 get_dma_cookies:
4908 i = 0;
4909 acmd->cmd_dmacount = 0;
4910 for (;;) {
4911 acmd->cmd_dmacount +=
4912 acmd->cmd_dmacookies[i++].dmac_size;
4913
4914 if (i == instance->max_num_sge ||
4915 i == acmd->cmd_ncookies)
4916 break;
4917
4918 ddi_dma_nextcookie(acmd->cmd_dmahandle,
4919 &acmd->cmd_dmacookies[i]);
4920 }
4921
4922 acmd->cmd_cookie = i;
4923 acmd->cmd_cookiecnt = i;
4924
4925 acmd->cmd_flags |= CFLAG_DMAVALID;
4926
4927 if (bp->b_bcount >= acmd->cmd_dmacount) {
4928 pkt->pkt_resid = bp->b_bcount - acmd->cmd_dmacount;
4929 } else {
4930 pkt->pkt_resid = 0;
4931 }
4932
4933 return (DDI_SUCCESS);
4934 case DDI_DMA_NORESOURCES:
4935 bioerror(bp, 0);
4936 break;
4937 case DDI_DMA_NOMAPPING:
4938 bioerror(bp, EFAULT);
4939 break;
4940 case DDI_DMA_TOOBIG:
4941 bioerror(bp, EINVAL);
4942 break;
4943 case DDI_DMA_INUSE:
4944 con_log(CL_ANN, (CE_PANIC, "ddi_dma_buf_bind_handle:"
4945 " DDI_DMA_INUSE impossible"));
4946 break;
4947 default:
4948 con_log(CL_ANN, (CE_PANIC, "ddi_dma_buf_bind_handle: "
4949 "impossible result (0x%x)", i));
4950 break;
4951 }
4952
4953 no_dma_cookies:
4954 ddi_dma_free_handle(&acmd->cmd_dmahandle);
4955 acmd->cmd_dmahandle = NULL;
4956 acmd->cmd_flags &= ~CFLAG_DMAVALID;
4957 return (DDI_FAILURE);
4958 }
4959
4960 /*
4961 * mrsas_dma_move(struct mrsas_instance *, struct scsi_pkt *, struct buf *)
4962 *
4963 * move dma resources to next dma window
4964 *
4965 */
4966 int
mrsas_dma_move(struct mrsas_instance * instance,struct scsi_pkt * pkt,struct buf * bp)4967 mrsas_dma_move(struct mrsas_instance *instance, struct scsi_pkt *pkt,
4968 struct buf *bp)
4969 {
4970 int i = 0;
4971
4972 struct scsa_cmd *acmd = PKT2CMD(pkt);
4973
4974 /*
4975 * If there are no more cookies remaining in this window,
4976 * must move to the next window first.
4977 */
4978 if (acmd->cmd_cookie == acmd->cmd_ncookies) {
4979 if (acmd->cmd_curwin == acmd->cmd_nwin && acmd->cmd_nwin == 1) {
4980 return (DDI_SUCCESS);
4981 }
4982
4983 /* at last window, cannot move */
4984 if (++acmd->cmd_curwin >= acmd->cmd_nwin) {
4985 return (DDI_FAILURE);
4986 }
4987
4988 if (ddi_dma_getwin(acmd->cmd_dmahandle, acmd->cmd_curwin,
4989 &acmd->cmd_dma_offset, &acmd->cmd_dma_len,
4990 &acmd->cmd_dmacookies[0], &acmd->cmd_ncookies) ==
4991 DDI_FAILURE) {
4992 return (DDI_FAILURE);
4993 }
4994
4995 acmd->cmd_cookie = 0;
4996 } else {
4997 /* still more cookies in this window - get the next one */
4998 ddi_dma_nextcookie(acmd->cmd_dmahandle,
4999 &acmd->cmd_dmacookies[0]);
5000 }
5001
5002 /* get remaining cookies in this window, up to our maximum */
5003 for (;;) {
5004 acmd->cmd_dmacount += acmd->cmd_dmacookies[i++].dmac_size;
5005 acmd->cmd_cookie++;
5006
5007 if (i == instance->max_num_sge ||
5008 acmd->cmd_cookie == acmd->cmd_ncookies) {
5009 break;
5010 }
5011
5012 ddi_dma_nextcookie(acmd->cmd_dmahandle,
5013 &acmd->cmd_dmacookies[i]);
5014 }
5015
5016 acmd->cmd_cookiecnt = i;
5017
5018 if (bp->b_bcount >= acmd->cmd_dmacount) {
5019 pkt->pkt_resid = bp->b_bcount - acmd->cmd_dmacount;
5020 } else {
5021 pkt->pkt_resid = 0;
5022 }
5023
5024 return (DDI_SUCCESS);
5025 }
5026
5027 /*
5028 * build_cmd
5029 */
5030 static struct mrsas_cmd *
build_cmd(struct mrsas_instance * instance,struct scsi_address * ap,struct scsi_pkt * pkt,uchar_t * cmd_done)5031 build_cmd(struct mrsas_instance *instance, struct scsi_address *ap,
5032 struct scsi_pkt *pkt, uchar_t *cmd_done)
5033 {
5034 uint16_t flags = 0;
5035 uint32_t i;
5036 uint32_t sge_bytes;
5037 uint32_t tmp_data_xfer_len;
5038 ddi_acc_handle_t acc_handle;
5039 struct mrsas_cmd *cmd;
5040 struct mrsas_sge64 *mfi_sgl;
5041 struct mrsas_sge_ieee *mfi_sgl_ieee;
5042 struct scsa_cmd *acmd = PKT2CMD(pkt);
5043 struct mrsas_pthru_frame *pthru;
5044 struct mrsas_io_frame *ldio;
5045
5046 /* find out if this is logical or physical drive command. */
5047 acmd->islogical = MRDRV_IS_LOGICAL(ap);
5048 acmd->device_id = MAP_DEVICE_ID(instance, ap);
5049 *cmd_done = 0;
5050
5051 /* get the command packet */
5052 if (!(cmd = mrsas_get_mfi_pkt(instance))) {
5053 DTRACE_PROBE2(build_cmd_mfi_err, uint16_t,
5054 instance->fw_outstanding, uint16_t, instance->max_fw_cmds);
5055 return (NULL);
5056 }
5057
5058 acc_handle = cmd->frame_dma_obj.acc_handle;
5059
5060 /* Clear the frame buffer and assign back the context id */
5061 (void) memset((char *)&cmd->frame[0], 0, sizeof (union mrsas_frame));
5062 ddi_put32(acc_handle, &cmd->frame->hdr.context, cmd->index);
5063
5064 cmd->pkt = pkt;
5065 cmd->cmd = acmd;
5066 DTRACE_PROBE3(build_cmds, uint8_t, pkt->pkt_cdbp[0],
5067 ulong_t, acmd->cmd_dmacount, ulong_t, acmd->cmd_dma_len);
5068
5069 /* lets get the command directions */
5070 if (acmd->cmd_flags & CFLAG_DMASEND) {
5071 flags = MFI_FRAME_DIR_WRITE;
5072
5073 if (acmd->cmd_flags & CFLAG_CONSISTENT) {
5074 (void) ddi_dma_sync(acmd->cmd_dmahandle,
5075 acmd->cmd_dma_offset, acmd->cmd_dma_len,
5076 DDI_DMA_SYNC_FORDEV);
5077 }
5078 } else if (acmd->cmd_flags & ~CFLAG_DMASEND) {
5079 flags = MFI_FRAME_DIR_READ;
5080
5081 if (acmd->cmd_flags & CFLAG_CONSISTENT) {
5082 (void) ddi_dma_sync(acmd->cmd_dmahandle,
5083 acmd->cmd_dma_offset, acmd->cmd_dma_len,
5084 DDI_DMA_SYNC_FORCPU);
5085 }
5086 } else {
5087 flags = MFI_FRAME_DIR_NONE;
5088 }
5089
5090 if (instance->flag_ieee) {
5091 flags |= MFI_FRAME_IEEE;
5092 }
5093 flags |= MFI_FRAME_SGL64;
5094
5095 switch (pkt->pkt_cdbp[0]) {
5096
5097 /*
5098 * case SCMD_SYNCHRONIZE_CACHE:
5099 * flush_cache(instance);
5100 * mrsas_return_mfi_pkt(instance, cmd);
5101 * *cmd_done = 1;
5102 *
5103 * return (NULL);
5104 */
5105
5106 case SCMD_READ:
5107 case SCMD_WRITE:
5108 case SCMD_READ_G1:
5109 case SCMD_WRITE_G1:
5110 case SCMD_READ_G4:
5111 case SCMD_WRITE_G4:
5112 case SCMD_READ_G5:
5113 case SCMD_WRITE_G5:
5114 if (acmd->islogical) {
5115 ldio = (struct mrsas_io_frame *)cmd->frame;
5116
5117 /*
5118 * preare the Logical IO frame:
5119 * 2nd bit is zero for all read cmds
5120 */
5121 ddi_put8(acc_handle, &ldio->cmd,
5122 (pkt->pkt_cdbp[0] & 0x02) ? MFI_CMD_OP_LD_WRITE
5123 : MFI_CMD_OP_LD_READ);
5124 ddi_put8(acc_handle, &ldio->cmd_status, 0x0);
5125 ddi_put8(acc_handle, &ldio->scsi_status, 0x0);
5126 ddi_put8(acc_handle, &ldio->target_id, acmd->device_id);
5127 ddi_put16(acc_handle, &ldio->timeout, 0);
5128 ddi_put8(acc_handle, &ldio->reserved_0, 0);
5129 ddi_put16(acc_handle, &ldio->pad_0, 0);
5130 ddi_put16(acc_handle, &ldio->flags, flags);
5131
5132 /* Initialize sense Information */
5133 bzero(cmd->sense, SENSE_LENGTH);
5134 ddi_put8(acc_handle, &ldio->sense_len, SENSE_LENGTH);
5135 ddi_put32(acc_handle, &ldio->sense_buf_phys_addr_hi, 0);
5136 ddi_put32(acc_handle, &ldio->sense_buf_phys_addr_lo,
5137 cmd->sense_phys_addr);
5138 ddi_put32(acc_handle, &ldio->start_lba_hi, 0);
5139 ddi_put8(acc_handle, &ldio->access_byte,
5140 (acmd->cmd_cdblen != 6) ? pkt->pkt_cdbp[1] : 0);
5141 ddi_put8(acc_handle, &ldio->sge_count,
5142 acmd->cmd_cookiecnt);
5143 if (instance->flag_ieee) {
5144 mfi_sgl_ieee =
5145 (struct mrsas_sge_ieee *)&ldio->sgl;
5146 } else {
5147 mfi_sgl = (struct mrsas_sge64 *)&ldio->sgl;
5148 }
5149
5150 (void) ddi_get32(acc_handle, &ldio->context);
5151
5152 if (acmd->cmd_cdblen == CDB_GROUP0) {
5153 /* 6-byte cdb */
5154 ddi_put32(acc_handle, &ldio->lba_count, (
5155 (uint16_t)(pkt->pkt_cdbp[4])));
5156
5157 ddi_put32(acc_handle, &ldio->start_lba_lo, (
5158 ((uint32_t)(pkt->pkt_cdbp[3])) |
5159 ((uint32_t)(pkt->pkt_cdbp[2]) << 8) |
5160 ((uint32_t)((pkt->pkt_cdbp[1]) & 0x1F)
5161 << 16)));
5162 } else if (acmd->cmd_cdblen == CDB_GROUP1) {
5163 /* 10-byte cdb */
5164 ddi_put32(acc_handle, &ldio->lba_count, (
5165 ((uint16_t)(pkt->pkt_cdbp[8])) |
5166 ((uint16_t)(pkt->pkt_cdbp[7]) << 8)));
5167
5168 ddi_put32(acc_handle, &ldio->start_lba_lo, (
5169 ((uint32_t)(pkt->pkt_cdbp[5])) |
5170 ((uint32_t)(pkt->pkt_cdbp[4]) << 8) |
5171 ((uint32_t)(pkt->pkt_cdbp[3]) << 16) |
5172 ((uint32_t)(pkt->pkt_cdbp[2]) << 24)));
5173 } else if (acmd->cmd_cdblen == CDB_GROUP5) {
5174 /* 12-byte cdb */
5175 ddi_put32(acc_handle, &ldio->lba_count, (
5176 ((uint32_t)(pkt->pkt_cdbp[9])) |
5177 ((uint32_t)(pkt->pkt_cdbp[8]) << 8) |
5178 ((uint32_t)(pkt->pkt_cdbp[7]) << 16) |
5179 ((uint32_t)(pkt->pkt_cdbp[6]) << 24)));
5180
5181 ddi_put32(acc_handle, &ldio->start_lba_lo, (
5182 ((uint32_t)(pkt->pkt_cdbp[5])) |
5183 ((uint32_t)(pkt->pkt_cdbp[4]) << 8) |
5184 ((uint32_t)(pkt->pkt_cdbp[3]) << 16) |
5185 ((uint32_t)(pkt->pkt_cdbp[2]) << 24)));
5186 } else if (acmd->cmd_cdblen == CDB_GROUP4) {
5187 /* 16-byte cdb */
5188 ddi_put32(acc_handle, &ldio->lba_count, (
5189 ((uint32_t)(pkt->pkt_cdbp[13])) |
5190 ((uint32_t)(pkt->pkt_cdbp[12]) << 8) |
5191 ((uint32_t)(pkt->pkt_cdbp[11]) << 16) |
5192 ((uint32_t)(pkt->pkt_cdbp[10]) << 24)));
5193
5194 ddi_put32(acc_handle, &ldio->start_lba_lo, (
5195 ((uint32_t)(pkt->pkt_cdbp[9])) |
5196 ((uint32_t)(pkt->pkt_cdbp[8]) << 8) |
5197 ((uint32_t)(pkt->pkt_cdbp[7]) << 16) |
5198 ((uint32_t)(pkt->pkt_cdbp[6]) << 24)));
5199
5200 ddi_put32(acc_handle, &ldio->start_lba_hi, (
5201 ((uint32_t)(pkt->pkt_cdbp[5])) |
5202 ((uint32_t)(pkt->pkt_cdbp[4]) << 8) |
5203 ((uint32_t)(pkt->pkt_cdbp[3]) << 16) |
5204 ((uint32_t)(pkt->pkt_cdbp[2]) << 24)));
5205 }
5206
5207 break;
5208 }
5209 /* For all non-rd/wr and physical disk cmds */
5210 /* FALLTHROUGH */
5211 default:
5212
5213 switch (pkt->pkt_cdbp[0]) {
5214 case SCMD_MODE_SENSE:
5215 case SCMD_MODE_SENSE_G1: {
5216 union scsi_cdb *cdbp;
5217 uint16_t page_code;
5218
5219 cdbp = (void *)pkt->pkt_cdbp;
5220 page_code = (uint16_t)cdbp->cdb_un.sg.scsi[0];
5221 switch (page_code) {
5222 case 0x3:
5223 case 0x4:
5224 (void) mrsas_mode_sense_build(pkt);
5225 mrsas_return_mfi_pkt(instance, cmd);
5226 *cmd_done = 1;
5227 return (NULL);
5228 }
5229 break;
5230 }
5231 default:
5232 break;
5233 }
5234
5235 pthru = (struct mrsas_pthru_frame *)cmd->frame;
5236
5237 /* prepare the DCDB frame */
5238 ddi_put8(acc_handle, &pthru->cmd, (acmd->islogical) ?
5239 MFI_CMD_OP_LD_SCSI : MFI_CMD_OP_PD_SCSI);
5240 ddi_put8(acc_handle, &pthru->cmd_status, 0x0);
5241 ddi_put8(acc_handle, &pthru->scsi_status, 0x0);
5242 ddi_put8(acc_handle, &pthru->target_id, acmd->device_id);
5243 ddi_put8(acc_handle, &pthru->lun, 0);
5244 ddi_put8(acc_handle, &pthru->cdb_len, acmd->cmd_cdblen);
5245 ddi_put16(acc_handle, &pthru->timeout, 0);
5246 ddi_put16(acc_handle, &pthru->flags, flags);
5247 tmp_data_xfer_len = 0;
5248 for (i = 0; i < acmd->cmd_cookiecnt; i++) {
5249 tmp_data_xfer_len += acmd->cmd_dmacookies[i].dmac_size;
5250 }
5251 ddi_put32(acc_handle, &pthru->data_xfer_len,
5252 tmp_data_xfer_len);
5253 ddi_put8(acc_handle, &pthru->sge_count, acmd->cmd_cookiecnt);
5254 if (instance->flag_ieee) {
5255 mfi_sgl_ieee = (struct mrsas_sge_ieee *)&pthru->sgl;
5256 } else {
5257 mfi_sgl = (struct mrsas_sge64 *)&pthru->sgl;
5258 }
5259
5260 bzero(cmd->sense, SENSE_LENGTH);
5261 ddi_put8(acc_handle, &pthru->sense_len, SENSE_LENGTH);
5262 ddi_put32(acc_handle, &pthru->sense_buf_phys_addr_hi, 0);
5263 ddi_put32(acc_handle, &pthru->sense_buf_phys_addr_lo,
5264 cmd->sense_phys_addr);
5265
5266 (void) ddi_get32(acc_handle, &pthru->context);
5267 ddi_rep_put8(acc_handle, (uint8_t *)pkt->pkt_cdbp,
5268 (uint8_t *)pthru->cdb, acmd->cmd_cdblen, DDI_DEV_AUTOINCR);
5269
5270 break;
5271 }
5272
5273 /* prepare the scatter-gather list for the firmware */
5274 if (instance->flag_ieee) {
5275 for (i = 0; i < acmd->cmd_cookiecnt; i++, mfi_sgl_ieee++) {
5276 ddi_put64(acc_handle, &mfi_sgl_ieee->phys_addr,
5277 acmd->cmd_dmacookies[i].dmac_laddress);
5278 ddi_put32(acc_handle, &mfi_sgl_ieee->length,
5279 acmd->cmd_dmacookies[i].dmac_size);
5280 }
5281 sge_bytes = sizeof (struct mrsas_sge_ieee)*acmd->cmd_cookiecnt;
5282 } else {
5283 for (i = 0; i < acmd->cmd_cookiecnt; i++, mfi_sgl++) {
5284 ddi_put64(acc_handle, &mfi_sgl->phys_addr,
5285 acmd->cmd_dmacookies[i].dmac_laddress);
5286 ddi_put32(acc_handle, &mfi_sgl->length,
5287 acmd->cmd_dmacookies[i].dmac_size);
5288 }
5289 sge_bytes = sizeof (struct mrsas_sge64)*acmd->cmd_cookiecnt;
5290 }
5291
5292 cmd->frame_count = (sge_bytes / MRMFI_FRAME_SIZE) +
5293 ((sge_bytes % MRMFI_FRAME_SIZE) ? 1 : 0) + 1;
5294
5295 if (cmd->frame_count >= 8) {
5296 cmd->frame_count = 8;
5297 }
5298
5299 return (cmd);
5300 }
5301
5302 /*
5303 * wait_for_outstanding - Wait for all outstanding cmds
5304 * @instance: Adapter soft state
5305 *
5306 * This function waits for upto MRDRV_RESET_WAIT_TIME seconds for FW to
5307 * complete all its outstanding commands. Returns error if one or more IOs
5308 * are pending after this time period.
5309 */
5310 static int
wait_for_outstanding(struct mrsas_instance * instance)5311 wait_for_outstanding(struct mrsas_instance *instance)
5312 {
5313 int i;
5314 uint32_t wait_time = 90;
5315
5316 for (i = 0; i < wait_time; i++) {
5317 if (!instance->fw_outstanding) {
5318 break;
5319 }
5320
5321 drv_usecwait(MILLISEC); /* wait for 1000 usecs */;
5322 }
5323
5324 if (instance->fw_outstanding) {
5325 return (1);
5326 }
5327
5328 return (0);
5329 }
5330
5331 /*
5332 * issue_mfi_pthru
5333 */
5334 static int
issue_mfi_pthru(struct mrsas_instance * instance,struct mrsas_ioctl * ioctl,struct mrsas_cmd * cmd,int mode)5335 issue_mfi_pthru(struct mrsas_instance *instance, struct mrsas_ioctl *ioctl,
5336 struct mrsas_cmd *cmd, int mode)
5337 {
5338 void *ubuf;
5339 uint32_t kphys_addr = 0;
5340 uint32_t xferlen = 0;
5341 uint32_t new_xfer_length = 0;
5342 uint_t model;
5343 ddi_acc_handle_t acc_handle = cmd->frame_dma_obj.acc_handle;
5344 dma_obj_t pthru_dma_obj;
5345 struct mrsas_pthru_frame *kpthru;
5346 struct mrsas_pthru_frame *pthru;
5347 int i;
5348 pthru = &cmd->frame->pthru;
5349 kpthru = (struct mrsas_pthru_frame *)&ioctl->frame[0];
5350
5351 if (instance->adapterresetinprogress) {
5352 con_log(CL_ANN1, (CE_WARN, "issue_mfi_pthru: Reset flag set, "
5353 "returning mfi_pkt and setting TRAN_BUSY\n"));
5354 return (DDI_FAILURE);
5355 }
5356 model = ddi_model_convert_from(mode & FMODELS);
5357 if (model == DDI_MODEL_ILP32) {
5358 con_log(CL_ANN1, (CE_CONT, "issue_mfi_pthru: DDI_MODEL_LP32"));
5359
5360 xferlen = kpthru->sgl.sge32[0].length;
5361
5362 ubuf = (void *)(ulong_t)kpthru->sgl.sge32[0].phys_addr;
5363 } else {
5364 #ifdef _ILP32
5365 con_log(CL_ANN1, (CE_CONT, "issue_mfi_pthru: DDI_MODEL_LP32"));
5366 xferlen = kpthru->sgl.sge32[0].length;
5367 ubuf = (void *)(ulong_t)kpthru->sgl.sge32[0].phys_addr;
5368 #else
5369 con_log(CL_ANN1, (CE_CONT, "issue_mfi_pthru: DDI_MODEL_LP64"));
5370 xferlen = kpthru->sgl.sge64[0].length;
5371 ubuf = (void *)(ulong_t)kpthru->sgl.sge64[0].phys_addr;
5372 #endif
5373 }
5374
5375 if (xferlen) {
5376 /* means IOCTL requires DMA */
5377 /* allocate the data transfer buffer */
5378 /* pthru_dma_obj.size = xferlen; */
5379 MRSAS_GET_BOUNDARY_ALIGNED_LEN(xferlen, new_xfer_length,
5380 PAGESIZE);
5381 pthru_dma_obj.size = new_xfer_length;
5382 pthru_dma_obj.dma_attr = mrsas_generic_dma_attr;
5383 pthru_dma_obj.dma_attr.dma_attr_addr_hi = 0xFFFFFFFFU;
5384 pthru_dma_obj.dma_attr.dma_attr_count_max = 0xFFFFFFFFU;
5385 pthru_dma_obj.dma_attr.dma_attr_sgllen = 1;
5386 pthru_dma_obj.dma_attr.dma_attr_align = 1;
5387
5388 /* allocate kernel buffer for DMA */
5389 if (mrsas_alloc_dma_obj(instance, &pthru_dma_obj,
5390 (uchar_t)DDI_STRUCTURE_LE_ACC) != 1) {
5391 con_log(CL_ANN, (CE_WARN, "issue_mfi_pthru: "
5392 "could not allocate data transfer buffer."));
5393 return (DDI_FAILURE);
5394 }
5395 (void) memset(pthru_dma_obj.buffer, 0, xferlen);
5396
5397 /* If IOCTL requires DMA WRITE, do ddi_copyin IOCTL data copy */
5398 if (kpthru->flags & MFI_FRAME_DIR_WRITE) {
5399 for (i = 0; i < xferlen; i++) {
5400 if (ddi_copyin((uint8_t *)ubuf+i,
5401 (uint8_t *)pthru_dma_obj.buffer+i,
5402 1, mode)) {
5403 con_log(CL_ANN, (CE_WARN,
5404 "issue_mfi_pthru : "
5405 "copy from user space failed"));
5406 return (DDI_FAILURE);
5407 }
5408 }
5409 }
5410
5411 kphys_addr = pthru_dma_obj.dma_cookie[0].dmac_address;
5412 }
5413
5414 ddi_put8(acc_handle, &pthru->cmd, kpthru->cmd);
5415 ddi_put8(acc_handle, &pthru->sense_len, SENSE_LENGTH);
5416 ddi_put8(acc_handle, &pthru->cmd_status, 0);
5417 ddi_put8(acc_handle, &pthru->scsi_status, 0);
5418 ddi_put8(acc_handle, &pthru->target_id, kpthru->target_id);
5419 ddi_put8(acc_handle, &pthru->lun, kpthru->lun);
5420 ddi_put8(acc_handle, &pthru->cdb_len, kpthru->cdb_len);
5421 ddi_put8(acc_handle, &pthru->sge_count, kpthru->sge_count);
5422 ddi_put16(acc_handle, &pthru->timeout, kpthru->timeout);
5423 ddi_put32(acc_handle, &pthru->data_xfer_len, kpthru->data_xfer_len);
5424
5425 ddi_put32(acc_handle, &pthru->sense_buf_phys_addr_hi, 0);
5426 pthru->sense_buf_phys_addr_lo = cmd->sense_phys_addr;
5427 /* ddi_put32(acc_handle, &pthru->sense_buf_phys_addr_lo, 0); */
5428
5429 ddi_rep_put8(acc_handle, (uint8_t *)kpthru->cdb, (uint8_t *)pthru->cdb,
5430 pthru->cdb_len, DDI_DEV_AUTOINCR);
5431
5432 ddi_put16(acc_handle, &pthru->flags, kpthru->flags & ~MFI_FRAME_SGL64);
5433 ddi_put32(acc_handle, &pthru->sgl.sge32[0].length, xferlen);
5434 ddi_put32(acc_handle, &pthru->sgl.sge32[0].phys_addr, kphys_addr);
5435
5436 cmd->sync_cmd = MRSAS_TRUE;
5437 cmd->frame_count = 1;
5438
5439 if (instance->tbolt) {
5440 mr_sas_tbolt_build_mfi_cmd(instance, cmd);
5441 }
5442
5443 if (instance->func_ptr->issue_cmd_in_sync_mode(instance, cmd)) {
5444 con_log(CL_ANN, (CE_WARN,
5445 "issue_mfi_pthru: fw_ioctl failed"));
5446 } else {
5447 if (xferlen && kpthru->flags & MFI_FRAME_DIR_READ) {
5448 for (i = 0; i < xferlen; i++) {
5449 if (ddi_copyout(
5450 (uint8_t *)pthru_dma_obj.buffer+i,
5451 (uint8_t *)ubuf+i, 1, mode)) {
5452 con_log(CL_ANN, (CE_WARN,
5453 "issue_mfi_pthru : "
5454 "copy to user space failed"));
5455 return (DDI_FAILURE);
5456 }
5457 }
5458 }
5459 }
5460
5461 kpthru->cmd_status = ddi_get8(acc_handle, &pthru->cmd_status);
5462 kpthru->scsi_status = ddi_get8(acc_handle, &pthru->scsi_status);
5463
5464 con_log(CL_ANN, (CE_CONT, "issue_mfi_pthru: cmd_status %x, "
5465 "scsi_status %x", kpthru->cmd_status, kpthru->scsi_status));
5466 DTRACE_PROBE3(issue_pthru, uint8_t, kpthru->cmd, uint8_t,
5467 kpthru->cmd_status, uint8_t, kpthru->scsi_status);
5468
5469 if (kpthru->sense_len) {
5470 uint_t sense_len = SENSE_LENGTH;
5471 void *sense_ubuf =
5472 (void *)(ulong_t)kpthru->sense_buf_phys_addr_lo;
5473 if (kpthru->sense_len <= SENSE_LENGTH) {
5474 sense_len = kpthru->sense_len;
5475 }
5476
5477 for (i = 0; i < sense_len; i++) {
5478 if (ddi_copyout(
5479 (uint8_t *)cmd->sense+i,
5480 (uint8_t *)sense_ubuf+i, 1, mode)) {
5481 con_log(CL_ANN, (CE_WARN,
5482 "issue_mfi_pthru : "
5483 "copy to user space failed"));
5484 }
5485 con_log(CL_DLEVEL1, (CE_WARN,
5486 "Copying Sense info sense_buff[%d] = 0x%X",
5487 i, *((uint8_t *)cmd->sense + i)));
5488 }
5489 }
5490 (void) ddi_dma_sync(cmd->frame_dma_obj.dma_handle, 0, 0,
5491 DDI_DMA_SYNC_FORDEV);
5492
5493 if (xferlen) {
5494 /* free kernel buffer */
5495 if (mrsas_free_dma_obj(instance, pthru_dma_obj) != DDI_SUCCESS)
5496 return (DDI_FAILURE);
5497 }
5498
5499 return (DDI_SUCCESS);
5500 }
5501
5502 /*
5503 * issue_mfi_dcmd
5504 */
5505 static int
issue_mfi_dcmd(struct mrsas_instance * instance,struct mrsas_ioctl * ioctl,struct mrsas_cmd * cmd,int mode)5506 issue_mfi_dcmd(struct mrsas_instance *instance, struct mrsas_ioctl *ioctl,
5507 struct mrsas_cmd *cmd, int mode)
5508 {
5509 void *ubuf;
5510 uint32_t kphys_addr = 0;
5511 uint32_t xferlen = 0;
5512 uint32_t new_xfer_length = 0;
5513 uint32_t model;
5514 dma_obj_t dcmd_dma_obj;
5515 struct mrsas_dcmd_frame *kdcmd;
5516 struct mrsas_dcmd_frame *dcmd;
5517 ddi_acc_handle_t acc_handle = cmd->frame_dma_obj.acc_handle;
5518 int i;
5519 dcmd = &cmd->frame->dcmd;
5520 kdcmd = (struct mrsas_dcmd_frame *)&ioctl->frame[0];
5521
5522 if (instance->adapterresetinprogress) {
5523 con_log(CL_ANN1, (CE_NOTE, "Reset flag set, "
5524 "returning mfi_pkt and setting TRAN_BUSY"));
5525 return (DDI_FAILURE);
5526 }
5527 model = ddi_model_convert_from(mode & FMODELS);
5528 if (model == DDI_MODEL_ILP32) {
5529 con_log(CL_ANN1, (CE_CONT, "issue_mfi_dcmd: DDI_MODEL_ILP32"));
5530
5531 xferlen = kdcmd->sgl.sge32[0].length;
5532
5533 ubuf = (void *)(ulong_t)kdcmd->sgl.sge32[0].phys_addr;
5534 } else {
5535 #ifdef _ILP32
5536 con_log(CL_ANN1, (CE_CONT, "issue_mfi_dcmd: DDI_MODEL_ILP32"));
5537 xferlen = kdcmd->sgl.sge32[0].length;
5538 ubuf = (void *)(ulong_t)kdcmd->sgl.sge32[0].phys_addr;
5539 #else
5540 con_log(CL_ANN1, (CE_CONT, "issue_mfi_dcmd: DDI_MODEL_LP64"));
5541 xferlen = kdcmd->sgl.sge64[0].length;
5542 ubuf = (void *)(ulong_t)kdcmd->sgl.sge64[0].phys_addr;
5543 #endif
5544 }
5545 if (xferlen) {
5546 /* means IOCTL requires DMA */
5547 /* allocate the data transfer buffer */
5548 /* dcmd_dma_obj.size = xferlen; */
5549 MRSAS_GET_BOUNDARY_ALIGNED_LEN(xferlen, new_xfer_length,
5550 PAGESIZE);
5551 dcmd_dma_obj.size = new_xfer_length;
5552 dcmd_dma_obj.dma_attr = mrsas_generic_dma_attr;
5553 dcmd_dma_obj.dma_attr.dma_attr_addr_hi = 0xFFFFFFFFU;
5554 dcmd_dma_obj.dma_attr.dma_attr_count_max = 0xFFFFFFFFU;
5555 dcmd_dma_obj.dma_attr.dma_attr_sgllen = 1;
5556 dcmd_dma_obj.dma_attr.dma_attr_align = 1;
5557
5558 /* allocate kernel buffer for DMA */
5559 if (mrsas_alloc_dma_obj(instance, &dcmd_dma_obj,
5560 (uchar_t)DDI_STRUCTURE_LE_ACC) != 1) {
5561 con_log(CL_ANN,
5562 (CE_WARN, "issue_mfi_dcmd: could not "
5563 "allocate data transfer buffer."));
5564 return (DDI_FAILURE);
5565 }
5566 (void) memset(dcmd_dma_obj.buffer, 0, xferlen);
5567
5568 /* If IOCTL requires DMA WRITE, do ddi_copyin IOCTL data copy */
5569 if (kdcmd->flags & MFI_FRAME_DIR_WRITE) {
5570 for (i = 0; i < xferlen; i++) {
5571 if (ddi_copyin((uint8_t *)ubuf + i,
5572 (uint8_t *)dcmd_dma_obj.buffer + i,
5573 1, mode)) {
5574 con_log(CL_ANN, (CE_WARN,
5575 "issue_mfi_dcmd : "
5576 "copy from user space failed"));
5577 return (DDI_FAILURE);
5578 }
5579 }
5580 }
5581
5582 kphys_addr = dcmd_dma_obj.dma_cookie[0].dmac_address;
5583 }
5584
5585 ddi_put8(acc_handle, &dcmd->cmd, kdcmd->cmd);
5586 ddi_put8(acc_handle, &dcmd->cmd_status, 0);
5587 ddi_put8(acc_handle, &dcmd->sge_count, kdcmd->sge_count);
5588 ddi_put16(acc_handle, &dcmd->timeout, kdcmd->timeout);
5589 ddi_put32(acc_handle, &dcmd->data_xfer_len, kdcmd->data_xfer_len);
5590 ddi_put32(acc_handle, &dcmd->opcode, kdcmd->opcode);
5591
5592 ddi_rep_put8(acc_handle, (uint8_t *)kdcmd->mbox.b,
5593 (uint8_t *)dcmd->mbox.b, DCMD_MBOX_SZ, DDI_DEV_AUTOINCR);
5594
5595 ddi_put16(acc_handle, &dcmd->flags, kdcmd->flags & ~MFI_FRAME_SGL64);
5596 ddi_put32(acc_handle, &dcmd->sgl.sge32[0].length, xferlen);
5597 ddi_put32(acc_handle, &dcmd->sgl.sge32[0].phys_addr, kphys_addr);
5598
5599 cmd->sync_cmd = MRSAS_TRUE;
5600 cmd->frame_count = 1;
5601
5602 if (instance->tbolt) {
5603 mr_sas_tbolt_build_mfi_cmd(instance, cmd);
5604 }
5605
5606 if (instance->func_ptr->issue_cmd_in_sync_mode(instance, cmd)) {
5607 con_log(CL_ANN, (CE_WARN, "issue_mfi_dcmd: fw_ioctl failed"));
5608 } else {
5609 if (xferlen && (kdcmd->flags & MFI_FRAME_DIR_READ)) {
5610 for (i = 0; i < xferlen; i++) {
5611 if (ddi_copyout(
5612 (uint8_t *)dcmd_dma_obj.buffer + i,
5613 (uint8_t *)ubuf + i,
5614 1, mode)) {
5615 con_log(CL_ANN, (CE_WARN,
5616 "issue_mfi_dcmd : "
5617 "copy to user space failed"));
5618 return (DDI_FAILURE);
5619 }
5620 }
5621 }
5622 }
5623
5624 kdcmd->cmd_status = ddi_get8(acc_handle, &dcmd->cmd_status);
5625 con_log(CL_ANN,
5626 (CE_CONT, "issue_mfi_dcmd: cmd_status %x", kdcmd->cmd_status));
5627 DTRACE_PROBE3(issue_dcmd, uint32_t, kdcmd->opcode, uint8_t,
5628 kdcmd->cmd, uint8_t, kdcmd->cmd_status);
5629
5630 if (xferlen) {
5631 /* free kernel buffer */
5632 if (mrsas_free_dma_obj(instance, dcmd_dma_obj) != DDI_SUCCESS)
5633 return (DDI_FAILURE);
5634 }
5635
5636 return (DDI_SUCCESS);
5637 }
5638
5639 /*
5640 * issue_mfi_smp
5641 */
5642 static int
issue_mfi_smp(struct mrsas_instance * instance,struct mrsas_ioctl * ioctl,struct mrsas_cmd * cmd,int mode)5643 issue_mfi_smp(struct mrsas_instance *instance, struct mrsas_ioctl *ioctl,
5644 struct mrsas_cmd *cmd, int mode)
5645 {
5646 void *request_ubuf;
5647 void *response_ubuf;
5648 uint32_t request_xferlen = 0;
5649 uint32_t response_xferlen = 0;
5650 uint32_t new_xfer_length1 = 0;
5651 uint32_t new_xfer_length2 = 0;
5652 uint_t model;
5653 dma_obj_t request_dma_obj;
5654 dma_obj_t response_dma_obj;
5655 ddi_acc_handle_t acc_handle = cmd->frame_dma_obj.acc_handle;
5656 struct mrsas_smp_frame *ksmp;
5657 struct mrsas_smp_frame *smp;
5658 struct mrsas_sge32 *sge32;
5659 #ifndef _ILP32
5660 struct mrsas_sge64 *sge64;
5661 #endif
5662 int i;
5663 uint64_t tmp_sas_addr;
5664
5665 smp = &cmd->frame->smp;
5666 ksmp = (struct mrsas_smp_frame *)&ioctl->frame[0];
5667
5668 if (instance->adapterresetinprogress) {
5669 con_log(CL_ANN1, (CE_WARN, "Reset flag set, "
5670 "returning mfi_pkt and setting TRAN_BUSY\n"));
5671 return (DDI_FAILURE);
5672 }
5673 model = ddi_model_convert_from(mode & FMODELS);
5674 if (model == DDI_MODEL_ILP32) {
5675 con_log(CL_ANN1, (CE_CONT, "issue_mfi_smp: DDI_MODEL_ILP32"));
5676
5677 sge32 = &ksmp->sgl[0].sge32[0];
5678 response_xferlen = sge32[0].length;
5679 request_xferlen = sge32[1].length;
5680 con_log(CL_ANN, (CE_CONT, "issue_mfi_smp: "
5681 "response_xferlen = %x, request_xferlen = %x",
5682 response_xferlen, request_xferlen));
5683
5684 response_ubuf = (void *)(ulong_t)sge32[0].phys_addr;
5685 request_ubuf = (void *)(ulong_t)sge32[1].phys_addr;
5686 con_log(CL_ANN1, (CE_CONT, "issue_mfi_smp: "
5687 "response_ubuf = %p, request_ubuf = %p",
5688 response_ubuf, request_ubuf));
5689 } else {
5690 #ifdef _ILP32
5691 con_log(CL_ANN1, (CE_CONT, "issue_mfi_smp: DDI_MODEL_ILP32"));
5692
5693 sge32 = &ksmp->sgl[0].sge32[0];
5694 response_xferlen = sge32[0].length;
5695 request_xferlen = sge32[1].length;
5696 con_log(CL_ANN, (CE_CONT, "issue_mfi_smp: "
5697 "response_xferlen = %x, request_xferlen = %x",
5698 response_xferlen, request_xferlen));
5699
5700 response_ubuf = (void *)(ulong_t)sge32[0].phys_addr;
5701 request_ubuf = (void *)(ulong_t)sge32[1].phys_addr;
5702 con_log(CL_ANN1, (CE_CONT, "issue_mfi_smp: "
5703 "response_ubuf = %p, request_ubuf = %p",
5704 response_ubuf, request_ubuf));
5705 #else
5706 con_log(CL_ANN1, (CE_CONT, "issue_mfi_smp: DDI_MODEL_LP64"));
5707
5708 sge64 = &ksmp->sgl[0].sge64[0];
5709 response_xferlen = sge64[0].length;
5710 request_xferlen = sge64[1].length;
5711
5712 response_ubuf = (void *)(ulong_t)sge64[0].phys_addr;
5713 request_ubuf = (void *)(ulong_t)sge64[1].phys_addr;
5714 #endif
5715 }
5716 if (request_xferlen) {
5717 /* means IOCTL requires DMA */
5718 /* allocate the data transfer buffer */
5719 /* request_dma_obj.size = request_xferlen; */
5720 MRSAS_GET_BOUNDARY_ALIGNED_LEN(request_xferlen,
5721 new_xfer_length1, PAGESIZE);
5722 request_dma_obj.size = new_xfer_length1;
5723 request_dma_obj.dma_attr = mrsas_generic_dma_attr;
5724 request_dma_obj.dma_attr.dma_attr_addr_hi = 0xFFFFFFFFU;
5725 request_dma_obj.dma_attr.dma_attr_count_max = 0xFFFFFFFFU;
5726 request_dma_obj.dma_attr.dma_attr_sgllen = 1;
5727 request_dma_obj.dma_attr.dma_attr_align = 1;
5728
5729 /* allocate kernel buffer for DMA */
5730 if (mrsas_alloc_dma_obj(instance, &request_dma_obj,
5731 (uchar_t)DDI_STRUCTURE_LE_ACC) != 1) {
5732 con_log(CL_ANN, (CE_WARN, "issue_mfi_smp: "
5733 "could not allocate data transfer buffer."));
5734 return (DDI_FAILURE);
5735 }
5736 (void) memset(request_dma_obj.buffer, 0, request_xferlen);
5737
5738 /* If IOCTL requires DMA WRITE, do ddi_copyin IOCTL data copy */
5739 for (i = 0; i < request_xferlen; i++) {
5740 if (ddi_copyin((uint8_t *)request_ubuf + i,
5741 (uint8_t *)request_dma_obj.buffer + i,
5742 1, mode)) {
5743 con_log(CL_ANN, (CE_WARN, "issue_mfi_smp: "
5744 "copy from user space failed"));
5745 return (DDI_FAILURE);
5746 }
5747 }
5748 }
5749
5750 if (response_xferlen) {
5751 /* means IOCTL requires DMA */
5752 /* allocate the data transfer buffer */
5753 /* response_dma_obj.size = response_xferlen; */
5754 MRSAS_GET_BOUNDARY_ALIGNED_LEN(response_xferlen,
5755 new_xfer_length2, PAGESIZE);
5756 response_dma_obj.size = new_xfer_length2;
5757 response_dma_obj.dma_attr = mrsas_generic_dma_attr;
5758 response_dma_obj.dma_attr.dma_attr_addr_hi = 0xFFFFFFFFU;
5759 response_dma_obj.dma_attr.dma_attr_count_max = 0xFFFFFFFFU;
5760 response_dma_obj.dma_attr.dma_attr_sgllen = 1;
5761 response_dma_obj.dma_attr.dma_attr_align = 1;
5762
5763 /* allocate kernel buffer for DMA */
5764 if (mrsas_alloc_dma_obj(instance, &response_dma_obj,
5765 (uchar_t)DDI_STRUCTURE_LE_ACC) != 1) {
5766 con_log(CL_ANN, (CE_WARN, "issue_mfi_smp: "
5767 "could not allocate data transfer buffer."));
5768 return (DDI_FAILURE);
5769 }
5770 (void) memset(response_dma_obj.buffer, 0, response_xferlen);
5771
5772 /* If IOCTL requires DMA WRITE, do ddi_copyin IOCTL data copy */
5773 for (i = 0; i < response_xferlen; i++) {
5774 if (ddi_copyin((uint8_t *)response_ubuf + i,
5775 (uint8_t *)response_dma_obj.buffer + i,
5776 1, mode)) {
5777 con_log(CL_ANN, (CE_WARN, "issue_mfi_smp: "
5778 "copy from user space failed"));
5779 return (DDI_FAILURE);
5780 }
5781 }
5782 }
5783
5784 ddi_put8(acc_handle, &smp->cmd, ksmp->cmd);
5785 ddi_put8(acc_handle, &smp->cmd_status, 0);
5786 ddi_put8(acc_handle, &smp->connection_status, 0);
5787 ddi_put8(acc_handle, &smp->sge_count, ksmp->sge_count);
5788 /* smp->context = ksmp->context; */
5789 ddi_put16(acc_handle, &smp->timeout, ksmp->timeout);
5790 ddi_put32(acc_handle, &smp->data_xfer_len, ksmp->data_xfer_len);
5791
5792 bcopy((void *)&ksmp->sas_addr, (void *)&tmp_sas_addr,
5793 sizeof (uint64_t));
5794 ddi_put64(acc_handle, &smp->sas_addr, tmp_sas_addr);
5795
5796 ddi_put16(acc_handle, &smp->flags, ksmp->flags & ~MFI_FRAME_SGL64);
5797
5798 model = ddi_model_convert_from(mode & FMODELS);
5799 if (model == DDI_MODEL_ILP32) {
5800 con_log(CL_ANN1, (CE_CONT,
5801 "issue_mfi_smp: DDI_MODEL_ILP32"));
5802
5803 sge32 = &smp->sgl[0].sge32[0];
5804 ddi_put32(acc_handle, &sge32[0].length, response_xferlen);
5805 ddi_put32(acc_handle, &sge32[0].phys_addr,
5806 response_dma_obj.dma_cookie[0].dmac_address);
5807 ddi_put32(acc_handle, &sge32[1].length, request_xferlen);
5808 ddi_put32(acc_handle, &sge32[1].phys_addr,
5809 request_dma_obj.dma_cookie[0].dmac_address);
5810 } else {
5811 #ifdef _ILP32
5812 con_log(CL_ANN1, (CE_CONT,
5813 "issue_mfi_smp: DDI_MODEL_ILP32"));
5814 sge32 = &smp->sgl[0].sge32[0];
5815 ddi_put32(acc_handle, &sge32[0].length, response_xferlen);
5816 ddi_put32(acc_handle, &sge32[0].phys_addr,
5817 response_dma_obj.dma_cookie[0].dmac_address);
5818 ddi_put32(acc_handle, &sge32[1].length, request_xferlen);
5819 ddi_put32(acc_handle, &sge32[1].phys_addr,
5820 request_dma_obj.dma_cookie[0].dmac_address);
5821 #else
5822 con_log(CL_ANN1, (CE_CONT,
5823 "issue_mfi_smp: DDI_MODEL_LP64"));
5824 sge64 = &smp->sgl[0].sge64[0];
5825 ddi_put32(acc_handle, &sge64[0].length, response_xferlen);
5826 ddi_put64(acc_handle, &sge64[0].phys_addr,
5827 response_dma_obj.dma_cookie[0].dmac_address);
5828 ddi_put32(acc_handle, &sge64[1].length, request_xferlen);
5829 ddi_put64(acc_handle, &sge64[1].phys_addr,
5830 request_dma_obj.dma_cookie[0].dmac_address);
5831 #endif
5832 }
5833 con_log(CL_ANN1, (CE_CONT, "issue_mfi_smp : "
5834 "smp->response_xferlen = %d, smp->request_xferlen = %d "
5835 "smp->data_xfer_len = %d", ddi_get32(acc_handle, &sge32[0].length),
5836 ddi_get32(acc_handle, &sge32[1].length),
5837 ddi_get32(acc_handle, &smp->data_xfer_len)));
5838
5839 cmd->sync_cmd = MRSAS_TRUE;
5840 cmd->frame_count = 1;
5841
5842 if (instance->tbolt) {
5843 mr_sas_tbolt_build_mfi_cmd(instance, cmd);
5844 }
5845
5846 if (instance->func_ptr->issue_cmd_in_sync_mode(instance, cmd)) {
5847 con_log(CL_ANN, (CE_WARN,
5848 "issue_mfi_smp: fw_ioctl failed"));
5849 } else {
5850 con_log(CL_ANN1, (CE_CONT,
5851 "issue_mfi_smp: copy to user space"));
5852
5853 if (request_xferlen) {
5854 for (i = 0; i < request_xferlen; i++) {
5855 if (ddi_copyout(
5856 (uint8_t *)request_dma_obj.buffer +
5857 i, (uint8_t *)request_ubuf + i,
5858 1, mode)) {
5859 con_log(CL_ANN, (CE_WARN,
5860 "issue_mfi_smp : copy to user space"
5861 " failed"));
5862 return (DDI_FAILURE);
5863 }
5864 }
5865 }
5866
5867 if (response_xferlen) {
5868 for (i = 0; i < response_xferlen; i++) {
5869 if (ddi_copyout(
5870 (uint8_t *)response_dma_obj.buffer
5871 + i, (uint8_t *)response_ubuf
5872 + i, 1, mode)) {
5873 con_log(CL_ANN, (CE_WARN,
5874 "issue_mfi_smp : copy to "
5875 "user space failed"));
5876 return (DDI_FAILURE);
5877 }
5878 }
5879 }
5880 }
5881
5882 ksmp->cmd_status = ddi_get8(acc_handle, &smp->cmd_status);
5883 con_log(CL_ANN1, (CE_NOTE, "issue_mfi_smp: smp->cmd_status = %d",
5884 ksmp->cmd_status));
5885 DTRACE_PROBE2(issue_smp, uint8_t, ksmp->cmd, uint8_t, ksmp->cmd_status);
5886
5887 if (request_xferlen) {
5888 /* free kernel buffer */
5889 if (mrsas_free_dma_obj(instance, request_dma_obj) !=
5890 DDI_SUCCESS)
5891 return (DDI_FAILURE);
5892 }
5893
5894 if (response_xferlen) {
5895 /* free kernel buffer */
5896 if (mrsas_free_dma_obj(instance, response_dma_obj) !=
5897 DDI_SUCCESS)
5898 return (DDI_FAILURE);
5899 }
5900
5901 return (DDI_SUCCESS);
5902 }
5903
5904 /*
5905 * issue_mfi_stp
5906 */
5907 static int
issue_mfi_stp(struct mrsas_instance * instance,struct mrsas_ioctl * ioctl,struct mrsas_cmd * cmd,int mode)5908 issue_mfi_stp(struct mrsas_instance *instance, struct mrsas_ioctl *ioctl,
5909 struct mrsas_cmd *cmd, int mode)
5910 {
5911 void *fis_ubuf;
5912 void *data_ubuf;
5913 uint32_t fis_xferlen = 0;
5914 uint32_t new_xfer_length1 = 0;
5915 uint32_t new_xfer_length2 = 0;
5916 uint32_t data_xferlen = 0;
5917 uint_t model;
5918 dma_obj_t fis_dma_obj;
5919 dma_obj_t data_dma_obj;
5920 struct mrsas_stp_frame *kstp;
5921 struct mrsas_stp_frame *stp;
5922 ddi_acc_handle_t acc_handle = cmd->frame_dma_obj.acc_handle;
5923 int i;
5924
5925 stp = &cmd->frame->stp;
5926 kstp = (struct mrsas_stp_frame *)&ioctl->frame[0];
5927
5928 if (instance->adapterresetinprogress) {
5929 con_log(CL_ANN1, (CE_WARN, "Reset flag set, "
5930 "returning mfi_pkt and setting TRAN_BUSY\n"));
5931 return (DDI_FAILURE);
5932 }
5933 model = ddi_model_convert_from(mode & FMODELS);
5934 if (model == DDI_MODEL_ILP32) {
5935 con_log(CL_ANN1, (CE_CONT, "issue_mfi_stp: DDI_MODEL_ILP32"));
5936
5937 fis_xferlen = kstp->sgl.sge32[0].length;
5938 data_xferlen = kstp->sgl.sge32[1].length;
5939
5940 fis_ubuf = (void *)(ulong_t)kstp->sgl.sge32[0].phys_addr;
5941 data_ubuf = (void *)(ulong_t)kstp->sgl.sge32[1].phys_addr;
5942 } else {
5943 #ifdef _ILP32
5944 con_log(CL_ANN1, (CE_CONT, "issue_mfi_stp: DDI_MODEL_ILP32"));
5945
5946 fis_xferlen = kstp->sgl.sge32[0].length;
5947 data_xferlen = kstp->sgl.sge32[1].length;
5948
5949 fis_ubuf = (void *)(ulong_t)kstp->sgl.sge32[0].phys_addr;
5950 data_ubuf = (void *)(ulong_t)kstp->sgl.sge32[1].phys_addr;
5951 #else
5952 con_log(CL_ANN1, (CE_CONT, "issue_mfi_stp: DDI_MODEL_LP64"));
5953
5954 fis_xferlen = kstp->sgl.sge64[0].length;
5955 data_xferlen = kstp->sgl.sge64[1].length;
5956
5957 fis_ubuf = (void *)(ulong_t)kstp->sgl.sge64[0].phys_addr;
5958 data_ubuf = (void *)(ulong_t)kstp->sgl.sge64[1].phys_addr;
5959 #endif
5960 }
5961
5962
5963 if (fis_xferlen) {
5964 con_log(CL_ANN, (CE_CONT, "issue_mfi_stp: "
5965 "fis_ubuf = %p fis_xferlen = %x", fis_ubuf, fis_xferlen));
5966
5967 /* means IOCTL requires DMA */
5968 /* allocate the data transfer buffer */
5969 /* fis_dma_obj.size = fis_xferlen; */
5970 MRSAS_GET_BOUNDARY_ALIGNED_LEN(fis_xferlen,
5971 new_xfer_length1, PAGESIZE);
5972 fis_dma_obj.size = new_xfer_length1;
5973 fis_dma_obj.dma_attr = mrsas_generic_dma_attr;
5974 fis_dma_obj.dma_attr.dma_attr_addr_hi = 0xFFFFFFFFU;
5975 fis_dma_obj.dma_attr.dma_attr_count_max = 0xFFFFFFFFU;
5976 fis_dma_obj.dma_attr.dma_attr_sgllen = 1;
5977 fis_dma_obj.dma_attr.dma_attr_align = 1;
5978
5979 /* allocate kernel buffer for DMA */
5980 if (mrsas_alloc_dma_obj(instance, &fis_dma_obj,
5981 (uchar_t)DDI_STRUCTURE_LE_ACC) != 1) {
5982 con_log(CL_ANN, (CE_WARN, "issue_mfi_stp : "
5983 "could not allocate data transfer buffer."));
5984 return (DDI_FAILURE);
5985 }
5986 (void) memset(fis_dma_obj.buffer, 0, fis_xferlen);
5987
5988 /* If IOCTL requires DMA WRITE, do ddi_copyin IOCTL data copy */
5989 for (i = 0; i < fis_xferlen; i++) {
5990 if (ddi_copyin((uint8_t *)fis_ubuf + i,
5991 (uint8_t *)fis_dma_obj.buffer + i, 1, mode)) {
5992 con_log(CL_ANN, (CE_WARN, "issue_mfi_stp: "
5993 "copy from user space failed"));
5994 return (DDI_FAILURE);
5995 }
5996 }
5997 }
5998
5999 if (data_xferlen) {
6000 con_log(CL_ANN, (CE_CONT, "issue_mfi_stp: data_ubuf = %p "
6001 "data_xferlen = %x", data_ubuf, data_xferlen));
6002
6003 /* means IOCTL requires DMA */
6004 /* allocate the data transfer buffer */
6005 /* data_dma_obj.size = data_xferlen; */
6006 MRSAS_GET_BOUNDARY_ALIGNED_LEN(data_xferlen, new_xfer_length2,
6007 PAGESIZE);
6008 data_dma_obj.size = new_xfer_length2;
6009 data_dma_obj.dma_attr = mrsas_generic_dma_attr;
6010 data_dma_obj.dma_attr.dma_attr_addr_hi = 0xFFFFFFFFU;
6011 data_dma_obj.dma_attr.dma_attr_count_max = 0xFFFFFFFFU;
6012 data_dma_obj.dma_attr.dma_attr_sgllen = 1;
6013 data_dma_obj.dma_attr.dma_attr_align = 1;
6014
6015 /* allocate kernel buffer for DMA */
6016 if (mrsas_alloc_dma_obj(instance, &data_dma_obj,
6017 (uchar_t)DDI_STRUCTURE_LE_ACC) != 1) {
6018 con_log(CL_ANN, (CE_WARN, "issue_mfi_stp: "
6019 "could not allocate data transfer buffer."));
6020 return (DDI_FAILURE);
6021 }
6022 (void) memset(data_dma_obj.buffer, 0, data_xferlen);
6023
6024 /* If IOCTL requires DMA WRITE, do ddi_copyin IOCTL data copy */
6025 for (i = 0; i < data_xferlen; i++) {
6026 if (ddi_copyin((uint8_t *)data_ubuf + i,
6027 (uint8_t *)data_dma_obj.buffer + i, 1, mode)) {
6028 con_log(CL_ANN, (CE_WARN, "issue_mfi_stp: "
6029 "copy from user space failed"));
6030 return (DDI_FAILURE);
6031 }
6032 }
6033 }
6034
6035 ddi_put8(acc_handle, &stp->cmd, kstp->cmd);
6036 ddi_put8(acc_handle, &stp->cmd_status, 0);
6037 ddi_put8(acc_handle, &stp->connection_status, 0);
6038 ddi_put8(acc_handle, &stp->target_id, kstp->target_id);
6039 ddi_put8(acc_handle, &stp->sge_count, kstp->sge_count);
6040
6041 ddi_put16(acc_handle, &stp->timeout, kstp->timeout);
6042 ddi_put32(acc_handle, &stp->data_xfer_len, kstp->data_xfer_len);
6043
6044 ddi_rep_put8(acc_handle, (uint8_t *)kstp->fis, (uint8_t *)stp->fis, 10,
6045 DDI_DEV_AUTOINCR);
6046
6047 ddi_put16(acc_handle, &stp->flags, kstp->flags & ~MFI_FRAME_SGL64);
6048 ddi_put32(acc_handle, &stp->stp_flags, kstp->stp_flags);
6049 ddi_put32(acc_handle, &stp->sgl.sge32[0].length, fis_xferlen);
6050 ddi_put32(acc_handle, &stp->sgl.sge32[0].phys_addr,
6051 fis_dma_obj.dma_cookie[0].dmac_address);
6052 ddi_put32(acc_handle, &stp->sgl.sge32[1].length, data_xferlen);
6053 ddi_put32(acc_handle, &stp->sgl.sge32[1].phys_addr,
6054 data_dma_obj.dma_cookie[0].dmac_address);
6055
6056 cmd->sync_cmd = MRSAS_TRUE;
6057 cmd->frame_count = 1;
6058
6059 if (instance->tbolt) {
6060 mr_sas_tbolt_build_mfi_cmd(instance, cmd);
6061 }
6062
6063 if (instance->func_ptr->issue_cmd_in_sync_mode(instance, cmd)) {
6064 con_log(CL_ANN, (CE_WARN, "issue_mfi_stp: fw_ioctl failed"));
6065 } else {
6066
6067 if (fis_xferlen) {
6068 for (i = 0; i < fis_xferlen; i++) {
6069 if (ddi_copyout(
6070 (uint8_t *)fis_dma_obj.buffer + i,
6071 (uint8_t *)fis_ubuf + i, 1, mode)) {
6072 con_log(CL_ANN, (CE_WARN,
6073 "issue_mfi_stp : copy to "
6074 "user space failed"));
6075 return (DDI_FAILURE);
6076 }
6077 }
6078 }
6079 }
6080 if (data_xferlen) {
6081 for (i = 0; i < data_xferlen; i++) {
6082 if (ddi_copyout(
6083 (uint8_t *)data_dma_obj.buffer + i,
6084 (uint8_t *)data_ubuf + i, 1, mode)) {
6085 con_log(CL_ANN, (CE_WARN,
6086 "issue_mfi_stp : copy to"
6087 " user space failed"));
6088 return (DDI_FAILURE);
6089 }
6090 }
6091 }
6092
6093 kstp->cmd_status = ddi_get8(acc_handle, &stp->cmd_status);
6094 con_log(CL_ANN1, (CE_NOTE, "issue_mfi_stp: stp->cmd_status = %d",
6095 kstp->cmd_status));
6096 DTRACE_PROBE2(issue_stp, uint8_t, kstp->cmd, uint8_t, kstp->cmd_status);
6097
6098 if (fis_xferlen) {
6099 /* free kernel buffer */
6100 if (mrsas_free_dma_obj(instance, fis_dma_obj) != DDI_SUCCESS)
6101 return (DDI_FAILURE);
6102 }
6103
6104 if (data_xferlen) {
6105 /* free kernel buffer */
6106 if (mrsas_free_dma_obj(instance, data_dma_obj) != DDI_SUCCESS)
6107 return (DDI_FAILURE);
6108 }
6109
6110 return (DDI_SUCCESS);
6111 }
6112
6113 /*
6114 * fill_up_drv_ver
6115 */
6116 void
fill_up_drv_ver(struct mrsas_drv_ver * dv)6117 fill_up_drv_ver(struct mrsas_drv_ver *dv)
6118 {
6119 (void) memset(dv, 0, sizeof (struct mrsas_drv_ver));
6120
6121 (void) memcpy(dv->signature, "$LSI LOGIC$", strlen("$LSI LOGIC$"));
6122 (void) memcpy(dv->os_name, "Solaris", strlen("Solaris"));
6123 (void) memcpy(dv->drv_name, "mr_sas", strlen("mr_sas"));
6124 (void) memcpy(dv->drv_ver, MRSAS_VERSION, strlen(MRSAS_VERSION));
6125 (void) memcpy(dv->drv_rel_date, MRSAS_RELDATE,
6126 strlen(MRSAS_RELDATE));
6127
6128 }
6129
6130 /*
6131 * handle_drv_ioctl
6132 */
6133 static int
handle_drv_ioctl(struct mrsas_instance * instance,struct mrsas_ioctl * ioctl,int mode)6134 handle_drv_ioctl(struct mrsas_instance *instance, struct mrsas_ioctl *ioctl,
6135 int mode)
6136 {
6137 int i;
6138 int rval = DDI_SUCCESS;
6139 int *props = NULL;
6140 void *ubuf;
6141
6142 uint8_t *pci_conf_buf;
6143 uint32_t xferlen;
6144 uint32_t num_props;
6145 uint_t model;
6146 struct mrsas_dcmd_frame *kdcmd;
6147 struct mrsas_drv_ver dv;
6148 struct mrsas_pci_information pi;
6149
6150 kdcmd = (struct mrsas_dcmd_frame *)&ioctl->frame[0];
6151
6152 model = ddi_model_convert_from(mode & FMODELS);
6153 if (model == DDI_MODEL_ILP32) {
6154 con_log(CL_ANN1, (CE_CONT,
6155 "handle_drv_ioctl: DDI_MODEL_ILP32"));
6156
6157 xferlen = kdcmd->sgl.sge32[0].length;
6158
6159 ubuf = (void *)(ulong_t)kdcmd->sgl.sge32[0].phys_addr;
6160 } else {
6161 #ifdef _ILP32
6162 con_log(CL_ANN1, (CE_CONT,
6163 "handle_drv_ioctl: DDI_MODEL_ILP32"));
6164 xferlen = kdcmd->sgl.sge32[0].length;
6165 ubuf = (void *)(ulong_t)kdcmd->sgl.sge32[0].phys_addr;
6166 #else
6167 con_log(CL_ANN1, (CE_CONT,
6168 "handle_drv_ioctl: DDI_MODEL_LP64"));
6169 xferlen = kdcmd->sgl.sge64[0].length;
6170 ubuf = (void *)(ulong_t)kdcmd->sgl.sge64[0].phys_addr;
6171 #endif
6172 }
6173 con_log(CL_ANN1, (CE_CONT, "handle_drv_ioctl: "
6174 "dataBuf=%p size=%d bytes", ubuf, xferlen));
6175
6176 switch (kdcmd->opcode) {
6177 case MRSAS_DRIVER_IOCTL_DRIVER_VERSION:
6178 con_log(CL_ANN1, (CE_CONT, "handle_drv_ioctl: "
6179 "MRSAS_DRIVER_IOCTL_DRIVER_VERSION"));
6180
6181 fill_up_drv_ver(&dv);
6182
6183 if (ddi_copyout(&dv, ubuf, xferlen, mode)) {
6184 con_log(CL_ANN, (CE_WARN, "handle_drv_ioctl: "
6185 "MRSAS_DRIVER_IOCTL_DRIVER_VERSION : "
6186 "copy to user space failed"));
6187 kdcmd->cmd_status = 1;
6188 rval = 1;
6189 } else {
6190 kdcmd->cmd_status = 0;
6191 }
6192 break;
6193 case MRSAS_DRIVER_IOCTL_PCI_INFORMATION:
6194 con_log(CL_ANN1, (CE_NOTE, "handle_drv_ioctl: "
6195 "MRSAS_DRIVER_IOCTL_PCI_INFORMAITON"));
6196
6197 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, instance->dip,
6198 0, "reg", &props, &num_props)) {
6199 con_log(CL_ANN, (CE_WARN, "handle_drv_ioctl: "
6200 "MRSAS_DRIVER_IOCTL_PCI_INFORMATION : "
6201 "ddi_prop_look_int_array failed"));
6202 rval = DDI_FAILURE;
6203 } else {
6204
6205 pi.busNumber = (props[0] >> 16) & 0xFF;
6206 pi.deviceNumber = (props[0] >> 11) & 0x1f;
6207 pi.functionNumber = (props[0] >> 8) & 0x7;
6208 ddi_prop_free((void *)props);
6209 }
6210
6211 pci_conf_buf = (uint8_t *)&pi.pciHeaderInfo;
6212
6213 for (i = 0; i < (sizeof (struct mrsas_pci_information) -
6214 offsetof(struct mrsas_pci_information, pciHeaderInfo));
6215 i++) {
6216 pci_conf_buf[i] =
6217 pci_config_get8(instance->pci_handle, i);
6218 }
6219
6220 if (ddi_copyout(&pi, ubuf, xferlen, mode)) {
6221 con_log(CL_ANN, (CE_WARN, "handle_drv_ioctl: "
6222 "MRSAS_DRIVER_IOCTL_PCI_INFORMATION : "
6223 "copy to user space failed"));
6224 kdcmd->cmd_status = 1;
6225 rval = 1;
6226 } else {
6227 kdcmd->cmd_status = 0;
6228 }
6229 break;
6230 default:
6231 con_log(CL_ANN, (CE_WARN, "handle_drv_ioctl: "
6232 "invalid driver specific IOCTL opcode = 0x%x",
6233 kdcmd->opcode));
6234 kdcmd->cmd_status = 1;
6235 rval = DDI_FAILURE;
6236 break;
6237 }
6238
6239 return (rval);
6240 }
6241
6242 /*
6243 * handle_mfi_ioctl
6244 */
6245 static int
handle_mfi_ioctl(struct mrsas_instance * instance,struct mrsas_ioctl * ioctl,int mode)6246 handle_mfi_ioctl(struct mrsas_instance *instance, struct mrsas_ioctl *ioctl,
6247 int mode)
6248 {
6249 int rval = DDI_SUCCESS;
6250
6251 struct mrsas_header *hdr;
6252 struct mrsas_cmd *cmd;
6253
6254 if (instance->tbolt) {
6255 cmd = get_raid_msg_mfi_pkt(instance);
6256 } else {
6257 cmd = mrsas_get_mfi_pkt(instance);
6258 }
6259 if (!cmd) {
6260 con_log(CL_ANN, (CE_WARN, "mr_sas: "
6261 "failed to get a cmd packet"));
6262 DTRACE_PROBE2(mfi_ioctl_err, uint16_t,
6263 instance->fw_outstanding, uint16_t, instance->max_fw_cmds);
6264 return (DDI_FAILURE);
6265 }
6266
6267 /* Clear the frame buffer and assign back the context id */
6268 (void) memset((char *)&cmd->frame[0], 0, sizeof (union mrsas_frame));
6269 ddi_put32(cmd->frame_dma_obj.acc_handle, &cmd->frame->hdr.context,
6270 cmd->index);
6271
6272 hdr = (struct mrsas_header *)&ioctl->frame[0];
6273
6274 switch (ddi_get8(cmd->frame_dma_obj.acc_handle, &hdr->cmd)) {
6275 case MFI_CMD_OP_DCMD:
6276 rval = issue_mfi_dcmd(instance, ioctl, cmd, mode);
6277 break;
6278 case MFI_CMD_OP_SMP:
6279 rval = issue_mfi_smp(instance, ioctl, cmd, mode);
6280 break;
6281 case MFI_CMD_OP_STP:
6282 rval = issue_mfi_stp(instance, ioctl, cmd, mode);
6283 break;
6284 case MFI_CMD_OP_LD_SCSI:
6285 case MFI_CMD_OP_PD_SCSI:
6286 rval = issue_mfi_pthru(instance, ioctl, cmd, mode);
6287 break;
6288 default:
6289 con_log(CL_ANN, (CE_WARN, "handle_mfi_ioctl: "
6290 "invalid mfi ioctl hdr->cmd = %d", hdr->cmd));
6291 rval = DDI_FAILURE;
6292 break;
6293 }
6294
6295 if (mrsas_common_check(instance, cmd) != DDI_SUCCESS)
6296 rval = DDI_FAILURE;
6297
6298 if (instance->tbolt) {
6299 return_raid_msg_mfi_pkt(instance, cmd);
6300 } else {
6301 mrsas_return_mfi_pkt(instance, cmd);
6302 }
6303
6304 return (rval);
6305 }
6306
6307 /*
6308 * AEN
6309 */
6310 static int
handle_mfi_aen(struct mrsas_instance * instance,struct mrsas_aen * aen)6311 handle_mfi_aen(struct mrsas_instance *instance, struct mrsas_aen *aen)
6312 {
6313 int rval = 0;
6314
6315 rval = register_mfi_aen(instance, instance->aen_seq_num,
6316 aen->class_locale_word);
6317
6318 aen->cmd_status = (uint8_t)rval;
6319
6320 return (rval);
6321 }
6322
6323 static int
register_mfi_aen(struct mrsas_instance * instance,uint32_t seq_num,uint32_t class_locale_word)6324 register_mfi_aen(struct mrsas_instance *instance, uint32_t seq_num,
6325 uint32_t class_locale_word)
6326 {
6327 int ret_val;
6328
6329 struct mrsas_cmd *cmd, *aen_cmd;
6330 struct mrsas_dcmd_frame *dcmd;
6331 union mrsas_evt_class_locale curr_aen;
6332 union mrsas_evt_class_locale prev_aen;
6333
6334 con_log(CL_ANN, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
6335 /*
6336 * If there an AEN pending already (aen_cmd), check if the
6337 * class_locale of that pending AEN is inclusive of the new
6338 * AEN request we currently have. If it is, then we don't have
6339 * to do anything. In other words, whichever events the current
6340 * AEN request is subscribing to, have already been subscribed
6341 * to.
6342 *
6343 * If the old_cmd is _not_ inclusive, then we have to abort
6344 * that command, form a class_locale that is superset of both
6345 * old and current and re-issue to the FW
6346 */
6347
6348 curr_aen.word = LE_32(class_locale_word);
6349 curr_aen.members.locale = LE_16(curr_aen.members.locale);
6350 aen_cmd = instance->aen_cmd;
6351 if (aen_cmd) {
6352 prev_aen.word = ddi_get32(aen_cmd->frame_dma_obj.acc_handle,
6353 &aen_cmd->frame->dcmd.mbox.w[1]);
6354 prev_aen.word = LE_32(prev_aen.word);
6355 prev_aen.members.locale = LE_16(prev_aen.members.locale);
6356 /*
6357 * A class whose enum value is smaller is inclusive of all
6358 * higher values. If a PROGRESS (= -1) was previously
6359 * registered, then a new registration requests for higher
6360 * classes need not be sent to FW. They are automatically
6361 * included.
6362 *
6363 * Locale numbers don't have such hierarchy. They are bitmap
6364 * values
6365 */
6366 if ((prev_aen.members.class <= curr_aen.members.class) &&
6367 !((prev_aen.members.locale & curr_aen.members.locale) ^
6368 curr_aen.members.locale)) {
6369 /*
6370 * Previously issued event registration includes
6371 * current request. Nothing to do.
6372 */
6373
6374 return (0);
6375 } else {
6376 curr_aen.members.locale |= prev_aen.members.locale;
6377
6378 if (prev_aen.members.class < curr_aen.members.class)
6379 curr_aen.members.class = prev_aen.members.class;
6380
6381 ret_val = abort_aen_cmd(instance, aen_cmd);
6382
6383 if (ret_val) {
6384 con_log(CL_ANN, (CE_WARN, "register_mfi_aen: "
6385 "failed to abort prevous AEN command"));
6386
6387 return (ret_val);
6388 }
6389 }
6390 } else {
6391 curr_aen.word = LE_32(class_locale_word);
6392 curr_aen.members.locale = LE_16(curr_aen.members.locale);
6393 }
6394
6395 if (instance->tbolt) {
6396 cmd = get_raid_msg_mfi_pkt(instance);
6397 } else {
6398 cmd = mrsas_get_mfi_pkt(instance);
6399 }
6400
6401 if (!cmd) {
6402 DTRACE_PROBE2(mfi_aen_err, uint16_t, instance->fw_outstanding,
6403 uint16_t, instance->max_fw_cmds);
6404 return (ENOMEM);
6405 }
6406
6407 /* Clear the frame buffer and assign back the context id */
6408 (void) memset((char *)&cmd->frame[0], 0, sizeof (union mrsas_frame));
6409 ddi_put32(cmd->frame_dma_obj.acc_handle, &cmd->frame->hdr.context,
6410 cmd->index);
6411
6412 dcmd = &cmd->frame->dcmd;
6413
6414 /* for(i = 0; i < DCMD_MBOX_SZ; i++) dcmd->mbox.b[i] = 0; */
6415 (void) memset(dcmd->mbox.b, 0, DCMD_MBOX_SZ);
6416
6417 (void) memset(instance->mfi_evt_detail_obj.buffer, 0,
6418 sizeof (struct mrsas_evt_detail));
6419
6420 /* Prepare DCMD for aen registration */
6421 ddi_put8(cmd->frame_dma_obj.acc_handle, &dcmd->cmd, MFI_CMD_OP_DCMD);
6422 ddi_put8(cmd->frame_dma_obj.acc_handle, &dcmd->cmd_status, 0x0);
6423 ddi_put8(cmd->frame_dma_obj.acc_handle, &dcmd->sge_count, 1);
6424 ddi_put16(cmd->frame_dma_obj.acc_handle, &dcmd->flags,
6425 MFI_FRAME_DIR_READ);
6426 ddi_put16(cmd->frame_dma_obj.acc_handle, &dcmd->timeout, 0);
6427 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->data_xfer_len,
6428 sizeof (struct mrsas_evt_detail));
6429 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->opcode,
6430 MR_DCMD_CTRL_EVENT_WAIT);
6431 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->mbox.w[0], seq_num);
6432 curr_aen.members.locale = LE_16(curr_aen.members.locale);
6433 curr_aen.word = LE_32(curr_aen.word);
6434 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->mbox.w[1],
6435 curr_aen.word);
6436 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->sgl.sge32[0].phys_addr,
6437 instance->mfi_evt_detail_obj.dma_cookie[0].dmac_address);
6438 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->sgl.sge32[0].length,
6439 sizeof (struct mrsas_evt_detail));
6440
6441 instance->aen_seq_num = seq_num;
6442
6443
6444 /*
6445 * Store reference to the cmd used to register for AEN. When an
6446 * application wants us to register for AEN, we have to abort this
6447 * cmd and re-register with a new EVENT LOCALE supplied by that app
6448 */
6449 instance->aen_cmd = cmd;
6450
6451 cmd->frame_count = 1;
6452
6453 /* Issue the aen registration frame */
6454 /* atomic_add_16 (&instance->fw_outstanding, 1); */
6455 if (instance->tbolt) {
6456 mr_sas_tbolt_build_mfi_cmd(instance, cmd);
6457 }
6458 instance->func_ptr->issue_cmd(cmd, instance);
6459
6460 return (0);
6461 }
6462
6463 void
display_scsi_inquiry(caddr_t scsi_inq)6464 display_scsi_inquiry(caddr_t scsi_inq)
6465 {
6466 #define MAX_SCSI_DEVICE_CODE 14
6467 int i;
6468 char inquiry_buf[256] = {0};
6469 int len;
6470 const char *const scsi_device_types[] = {
6471 "Direct-Access ",
6472 "Sequential-Access",
6473 "Printer ",
6474 "Processor ",
6475 "WORM ",
6476 "CD-ROM ",
6477 "Scanner ",
6478 "Optical Device ",
6479 "Medium Changer ",
6480 "Communications ",
6481 "Unknown ",
6482 "Unknown ",
6483 "Unknown ",
6484 "Enclosure ",
6485 };
6486
6487 len = 0;
6488
6489 len += snprintf(inquiry_buf + len, 265 - len, " Vendor: ");
6490 for (i = 8; i < 16; i++) {
6491 len += snprintf(inquiry_buf + len, 265 - len, "%c",
6492 scsi_inq[i]);
6493 }
6494
6495 len += snprintf(inquiry_buf + len, 265 - len, " Model: ");
6496
6497 for (i = 16; i < 32; i++) {
6498 len += snprintf(inquiry_buf + len, 265 - len, "%c",
6499 scsi_inq[i]);
6500 }
6501
6502 len += snprintf(inquiry_buf + len, 265 - len, " Rev: ");
6503
6504 for (i = 32; i < 36; i++) {
6505 len += snprintf(inquiry_buf + len, 265 - len, "%c",
6506 scsi_inq[i]);
6507 }
6508
6509 len += snprintf(inquiry_buf + len, 265 - len, "\n");
6510
6511
6512 i = scsi_inq[0] & 0x1f;
6513
6514
6515 len += snprintf(inquiry_buf + len, 265 - len, " Type: %s ",
6516 i < MAX_SCSI_DEVICE_CODE ? scsi_device_types[i] :
6517 "Unknown ");
6518
6519
6520 len += snprintf(inquiry_buf + len, 265 - len,
6521 " ANSI SCSI revision: %02x", scsi_inq[2] & 0x07);
6522
6523 if ((scsi_inq[2] & 0x07) == 1 && (scsi_inq[3] & 0x0f) == 1) {
6524 len += snprintf(inquiry_buf + len, 265 - len, " CCS\n");
6525 } else {
6526 len += snprintf(inquiry_buf + len, 265 - len, "\n");
6527 }
6528
6529 con_log(CL_DLEVEL2, (CE_CONT, inquiry_buf));
6530 }
6531
6532 static void
io_timeout_checker(void * arg)6533 io_timeout_checker(void *arg)
6534 {
6535 struct scsi_pkt *pkt;
6536 struct mrsas_instance *instance = arg;
6537 struct mrsas_cmd *cmd = NULL;
6538 struct mrsas_header *hdr;
6539 int time = 0;
6540 int counter = 0;
6541 struct mlist_head *pos, *next;
6542 mlist_t process_list;
6543
6544 if (instance->adapterresetinprogress == 1) {
6545 con_log(CL_ANN, (CE_NOTE, "io_timeout_checker:"
6546 " reset in progress"));
6547
6548 instance->timeout_id = timeout(io_timeout_checker,
6549 (void *) instance, drv_usectohz(MRSAS_1_SECOND));
6550 return;
6551 }
6552
6553 /* See if this check needs to be in the beginning or last in ISR */
6554 if (mrsas_initiate_ocr_if_fw_is_faulty(instance) == 1) {
6555 dev_err(instance->dip, CE_WARN, "io_timeout_checker: "
6556 "FW Fault, calling reset adapter");
6557 dev_err(instance->dip, CE_CONT, "io_timeout_checker: "
6558 "fw_outstanding 0x%X max_fw_cmds 0x%X",
6559 instance->fw_outstanding, instance->max_fw_cmds);
6560 if (instance->adapterresetinprogress == 0) {
6561 instance->adapterresetinprogress = 1;
6562 if (instance->tbolt)
6563 (void) mrsas_tbolt_reset_ppc(instance);
6564 else
6565 (void) mrsas_reset_ppc(instance);
6566 instance->adapterresetinprogress = 0;
6567 }
6568 instance->timeout_id = timeout(io_timeout_checker,
6569 (void *) instance, drv_usectohz(MRSAS_1_SECOND));
6570 return;
6571 }
6572
6573 INIT_LIST_HEAD(&process_list);
6574
6575 mutex_enter(&instance->cmd_pend_mtx);
6576 mlist_for_each_safe(pos, next, &instance->cmd_pend_list) {
6577 cmd = mlist_entry(pos, struct mrsas_cmd, list);
6578
6579 if (cmd == NULL) {
6580 continue;
6581 }
6582
6583 if (cmd->sync_cmd == MRSAS_TRUE) {
6584 hdr = (struct mrsas_header *)&cmd->frame->hdr;
6585 if (hdr == NULL) {
6586 continue;
6587 }
6588 time = --cmd->drv_pkt_time;
6589 } else {
6590 pkt = cmd->pkt;
6591 if (pkt == NULL) {
6592 continue;
6593 }
6594 time = --cmd->drv_pkt_time;
6595 }
6596 if (time <= 0) {
6597 dev_err(instance->dip, CE_WARN, "%llx: "
6598 "io_timeout_checker: TIMING OUT: pkt: %p, "
6599 "cmd %p fw_outstanding 0x%X max_fw_cmds 0x%X",
6600 gethrtime(), (void *)pkt, (void *)cmd,
6601 instance->fw_outstanding, instance->max_fw_cmds);
6602
6603 counter++;
6604 break;
6605 }
6606 }
6607 mutex_exit(&instance->cmd_pend_mtx);
6608
6609 if (counter) {
6610 if (instance->disable_online_ctrl_reset == 1) {
6611 dev_err(instance->dip, CE_WARN, "%s(): OCR is NOT "
6612 "supported by Firmware, KILL adapter!!!",
6613 __func__);
6614
6615 if (instance->tbolt)
6616 mrsas_tbolt_kill_adapter(instance);
6617 else
6618 (void) mrsas_kill_adapter(instance);
6619
6620 return;
6621 } else {
6622 if (cmd->retry_count_for_ocr <= IO_RETRY_COUNT) {
6623 if (instance->adapterresetinprogress == 0) {
6624 if (instance->tbolt) {
6625 (void) mrsas_tbolt_reset_ppc(
6626 instance);
6627 } else {
6628 (void) mrsas_reset_ppc(
6629 instance);
6630 }
6631 }
6632 } else {
6633 dev_err(instance->dip, CE_WARN,
6634 "io_timeout_checker: "
6635 "cmd %p cmd->index %d "
6636 "timed out even after 3 resets: "
6637 "so KILL adapter", (void *)cmd, cmd->index);
6638
6639 mrsas_print_cmd_details(instance, cmd, 0xDD);
6640
6641 if (instance->tbolt)
6642 mrsas_tbolt_kill_adapter(instance);
6643 else
6644 (void) mrsas_kill_adapter(instance);
6645 return;
6646 }
6647 }
6648 }
6649 con_log(CL_ANN, (CE_NOTE, "mrsas: "
6650 "schedule next timeout check: "
6651 "do timeout \n"));
6652 instance->timeout_id =
6653 timeout(io_timeout_checker, (void *)instance,
6654 drv_usectohz(MRSAS_1_SECOND));
6655 }
6656
6657 static uint32_t
read_fw_status_reg_ppc(struct mrsas_instance * instance)6658 read_fw_status_reg_ppc(struct mrsas_instance *instance)
6659 {
6660 return ((uint32_t)RD_OB_SCRATCH_PAD_0(instance));
6661 }
6662
6663 static void
issue_cmd_ppc(struct mrsas_cmd * cmd,struct mrsas_instance * instance)6664 issue_cmd_ppc(struct mrsas_cmd *cmd, struct mrsas_instance *instance)
6665 {
6666 struct scsi_pkt *pkt;
6667 atomic_inc_16(&instance->fw_outstanding);
6668
6669 pkt = cmd->pkt;
6670 if (pkt) {
6671 con_log(CL_DLEVEL1, (CE_NOTE, "%llx : issue_cmd_ppc:"
6672 "ISSUED CMD TO FW : called : cmd:"
6673 ": %p instance : %p pkt : %p pkt_time : %x\n",
6674 gethrtime(), (void *)cmd, (void *)instance,
6675 (void *)pkt, cmd->drv_pkt_time));
6676 if (instance->adapterresetinprogress) {
6677 cmd->drv_pkt_time = (uint16_t)debug_timeout_g;
6678 con_log(CL_ANN1, (CE_NOTE, "Reset the scsi_pkt timer"));
6679 } else {
6680 push_pending_mfi_pkt(instance, cmd);
6681 }
6682
6683 } else {
6684 con_log(CL_DLEVEL1, (CE_NOTE, "%llx : issue_cmd_ppc:"
6685 "ISSUED CMD TO FW : called : cmd : %p, instance: %p"
6686 "(NO PKT)\n", gethrtime(), (void *)cmd, (void *)instance));
6687 }
6688
6689 mutex_enter(&instance->reg_write_mtx);
6690 /* Issue the command to the FW */
6691 WR_IB_PICK_QPORT((cmd->frame_phys_addr) |
6692 (((cmd->frame_count - 1) << 1) | 1), instance);
6693 mutex_exit(&instance->reg_write_mtx);
6694
6695 }
6696
6697 /*
6698 * issue_cmd_in_sync_mode
6699 */
6700 static int
issue_cmd_in_sync_mode_ppc(struct mrsas_instance * instance,struct mrsas_cmd * cmd)6701 issue_cmd_in_sync_mode_ppc(struct mrsas_instance *instance,
6702 struct mrsas_cmd *cmd)
6703 {
6704 int i;
6705 uint32_t msecs = MFI_POLL_TIMEOUT_SECS * MILLISEC;
6706 struct mrsas_header *hdr = &cmd->frame->hdr;
6707
6708 con_log(CL_ANN1, (CE_NOTE, "issue_cmd_in_sync_mode_ppc: called"));
6709
6710 if (instance->adapterresetinprogress) {
6711 cmd->drv_pkt_time = ddi_get16(
6712 cmd->frame_dma_obj.acc_handle, &hdr->timeout);
6713 if (cmd->drv_pkt_time < debug_timeout_g)
6714 cmd->drv_pkt_time = (uint16_t)debug_timeout_g;
6715
6716 con_log(CL_ANN1, (CE_NOTE, "sync_mode_ppc: "
6717 "issue and return in reset case\n"));
6718 WR_IB_PICK_QPORT((cmd->frame_phys_addr) |
6719 (((cmd->frame_count - 1) << 1) | 1), instance);
6720
6721 return (DDI_SUCCESS);
6722 } else {
6723 con_log(CL_ANN1, (CE_NOTE, "sync_mode_ppc: pushing the pkt\n"));
6724 push_pending_mfi_pkt(instance, cmd);
6725 }
6726
6727 cmd->cmd_status = ENODATA;
6728
6729 mutex_enter(&instance->reg_write_mtx);
6730 /* Issue the command to the FW */
6731 WR_IB_PICK_QPORT((cmd->frame_phys_addr) |
6732 (((cmd->frame_count - 1) << 1) | 1), instance);
6733 mutex_exit(&instance->reg_write_mtx);
6734
6735 mutex_enter(&instance->int_cmd_mtx);
6736 for (i = 0; i < msecs && (cmd->cmd_status == ENODATA); i++) {
6737 cv_wait(&instance->int_cmd_cv, &instance->int_cmd_mtx);
6738 }
6739 mutex_exit(&instance->int_cmd_mtx);
6740
6741 con_log(CL_ANN1, (CE_NOTE, "issue_cmd_in_sync_mode_ppc: done"));
6742
6743 if (i < (msecs -1)) {
6744 return (DDI_SUCCESS);
6745 } else {
6746 return (DDI_FAILURE);
6747 }
6748 }
6749
6750 /*
6751 * issue_cmd_in_poll_mode
6752 */
6753 static int
issue_cmd_in_poll_mode_ppc(struct mrsas_instance * instance,struct mrsas_cmd * cmd)6754 issue_cmd_in_poll_mode_ppc(struct mrsas_instance *instance,
6755 struct mrsas_cmd *cmd)
6756 {
6757 int i;
6758 uint16_t flags;
6759 uint32_t msecs = MFI_POLL_TIMEOUT_SECS * MILLISEC;
6760 struct mrsas_header *frame_hdr;
6761
6762 con_log(CL_ANN1, (CE_NOTE, "issue_cmd_in_poll_mode_ppc: called"));
6763
6764 frame_hdr = (struct mrsas_header *)cmd->frame;
6765 ddi_put8(cmd->frame_dma_obj.acc_handle, &frame_hdr->cmd_status,
6766 MFI_CMD_STATUS_POLL_MODE);
6767 flags = ddi_get16(cmd->frame_dma_obj.acc_handle, &frame_hdr->flags);
6768 flags |= MFI_FRAME_DONT_POST_IN_REPLY_QUEUE;
6769
6770 ddi_put16(cmd->frame_dma_obj.acc_handle, &frame_hdr->flags, flags);
6771
6772 /* issue the frame using inbound queue port */
6773 WR_IB_PICK_QPORT((cmd->frame_phys_addr) |
6774 (((cmd->frame_count - 1) << 1) | 1), instance);
6775
6776 /* wait for cmd_status to change from 0xFF */
6777 for (i = 0; i < msecs && (
6778 ddi_get8(cmd->frame_dma_obj.acc_handle, &frame_hdr->cmd_status)
6779 == MFI_CMD_STATUS_POLL_MODE); i++) {
6780 drv_usecwait(MILLISEC); /* wait for 1000 usecs */
6781 }
6782
6783 if (ddi_get8(cmd->frame_dma_obj.acc_handle, &frame_hdr->cmd_status)
6784 == MFI_CMD_STATUS_POLL_MODE) {
6785 con_log(CL_ANN, (CE_NOTE, "issue_cmd_in_poll_mode: "
6786 "cmd polling timed out"));
6787 return (DDI_FAILURE);
6788 }
6789
6790 return (DDI_SUCCESS);
6791 }
6792
6793 static void
enable_intr_ppc(struct mrsas_instance * instance)6794 enable_intr_ppc(struct mrsas_instance *instance)
6795 {
6796 uint32_t mask;
6797
6798 con_log(CL_ANN1, (CE_NOTE, "enable_intr_ppc: called"));
6799
6800 if (instance->skinny) {
6801 /* For SKINNY, write ~0x1, from BSD's mfi driver. */
6802 WR_OB_INTR_MASK(0xfffffffe, instance);
6803 } else {
6804 /* WR_OB_DOORBELL_CLEAR(0xFFFFFFFF, instance); */
6805 WR_OB_DOORBELL_CLEAR(OB_DOORBELL_CLEAR_MASK, instance);
6806
6807 /* WR_OB_INTR_MASK(~0x80000000, instance); */
6808 WR_OB_INTR_MASK(~(MFI_REPLY_2108_MESSAGE_INTR_MASK), instance);
6809 }
6810
6811 /* dummy read to force PCI flush */
6812 mask = RD_OB_INTR_MASK(instance);
6813
6814 con_log(CL_ANN1, (CE_NOTE, "enable_intr_ppc: "
6815 "outbound_intr_mask = 0x%x", mask));
6816 }
6817
6818 static void
disable_intr_ppc(struct mrsas_instance * instance)6819 disable_intr_ppc(struct mrsas_instance *instance)
6820 {
6821 con_log(CL_ANN1, (CE_NOTE, "disable_intr_ppc: called"));
6822
6823 con_log(CL_ANN1, (CE_NOTE, "disable_intr_ppc: before : "
6824 "outbound_intr_mask = 0x%x", RD_OB_INTR_MASK(instance)));
6825
6826 /* For now, assume there are no extras needed for Skinny support. */
6827
6828 WR_OB_INTR_MASK(OB_INTR_MASK, instance);
6829
6830 con_log(CL_ANN1, (CE_NOTE, "disable_intr_ppc: after : "
6831 "outbound_intr_mask = 0x%x", RD_OB_INTR_MASK(instance)));
6832
6833 /* dummy read to force PCI flush */
6834 (void) RD_OB_INTR_MASK(instance);
6835 }
6836
6837 static int
intr_ack_ppc(struct mrsas_instance * instance)6838 intr_ack_ppc(struct mrsas_instance *instance)
6839 {
6840 uint32_t status;
6841 int ret = DDI_INTR_CLAIMED;
6842
6843 con_log(CL_ANN1, (CE_NOTE, "intr_ack_ppc: called"));
6844
6845 /* check if it is our interrupt */
6846 status = RD_OB_INTR_STATUS(instance);
6847
6848 con_log(CL_ANN1, (CE_NOTE, "intr_ack_ppc: status = 0x%x", status));
6849
6850 /*
6851 * NOTE: Some drivers call out SKINNY here, but the return is the same
6852 * for SKINNY and 2108.
6853 */
6854 if (!(status & MFI_REPLY_2108_MESSAGE_INTR)) {
6855 ret = DDI_INTR_UNCLAIMED;
6856 }
6857
6858 if (mrsas_check_acc_handle(instance->regmap_handle) != DDI_SUCCESS) {
6859 ddi_fm_service_impact(instance->dip, DDI_SERVICE_LOST);
6860 ret = DDI_INTR_UNCLAIMED;
6861 }
6862
6863 if (ret == DDI_INTR_UNCLAIMED) {
6864 return (ret);
6865 }
6866
6867 /*
6868 * Clear the interrupt by writing back the same value.
6869 * Another case where SKINNY is slightly different.
6870 */
6871 if (instance->skinny) {
6872 WR_OB_INTR_STATUS(status, instance);
6873 } else {
6874 WR_OB_DOORBELL_CLEAR(status, instance);
6875 }
6876
6877 /* dummy READ */
6878 status = RD_OB_INTR_STATUS(instance);
6879
6880 con_log(CL_ANN1, (CE_NOTE, "intr_ack_ppc: interrupt cleared"));
6881
6882 return (ret);
6883 }
6884
6885 /*
6886 * Marks HBA as bad. This will be called either when an
6887 * IO packet times out even after 3 FW resets
6888 * or FW is found to be fault even after 3 continuous resets.
6889 */
6890
6891 static int
mrsas_kill_adapter(struct mrsas_instance * instance)6892 mrsas_kill_adapter(struct mrsas_instance *instance)
6893 {
6894 if (instance->deadadapter == 1)
6895 return (DDI_FAILURE);
6896
6897 con_log(CL_ANN1, (CE_NOTE, "mrsas_kill_adapter: "
6898 "Writing to doorbell with MFI_STOP_ADP "));
6899 mutex_enter(&instance->ocr_flags_mtx);
6900 instance->deadadapter = 1;
6901 mutex_exit(&instance->ocr_flags_mtx);
6902 instance->func_ptr->disable_intr(instance);
6903 WR_IB_DOORBELL(MFI_STOP_ADP, instance);
6904 (void) mrsas_complete_pending_cmds(instance);
6905 return (DDI_SUCCESS);
6906 }
6907
6908
6909 static int
mrsas_reset_ppc(struct mrsas_instance * instance)6910 mrsas_reset_ppc(struct mrsas_instance *instance)
6911 {
6912 uint32_t status;
6913 uint32_t retry = 0;
6914 uint32_t cur_abs_reg_val;
6915 uint32_t fw_state;
6916
6917 con_log(CL_ANN, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
6918
6919 if (instance->deadadapter == 1) {
6920 dev_err(instance->dip, CE_WARN, "mrsas_reset_ppc: "
6921 "no more resets as HBA has been marked dead ");
6922 return (DDI_FAILURE);
6923 }
6924 mutex_enter(&instance->ocr_flags_mtx);
6925 instance->adapterresetinprogress = 1;
6926 mutex_exit(&instance->ocr_flags_mtx);
6927 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc: adpterresetinprogress "
6928 "flag set, time %llx", gethrtime()));
6929
6930 instance->func_ptr->disable_intr(instance);
6931 retry_reset:
6932 WR_IB_WRITE_SEQ(0, instance);
6933 WR_IB_WRITE_SEQ(4, instance);
6934 WR_IB_WRITE_SEQ(0xb, instance);
6935 WR_IB_WRITE_SEQ(2, instance);
6936 WR_IB_WRITE_SEQ(7, instance);
6937 WR_IB_WRITE_SEQ(0xd, instance);
6938 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc: magic number written "
6939 "to write sequence register\n"));
6940 delay(100 * drv_usectohz(MILLISEC));
6941 status = RD_OB_DRWE(instance);
6942
6943 while (!(status & DIAG_WRITE_ENABLE)) {
6944 delay(100 * drv_usectohz(MILLISEC));
6945 status = RD_OB_DRWE(instance);
6946 if (retry++ == 100) {
6947 dev_err(instance->dip, CE_WARN,
6948 "mrsas_reset_ppc: DRWE bit "
6949 "check retry count %d", retry);
6950 return (DDI_FAILURE);
6951 }
6952 }
6953 WR_IB_DRWE(status | DIAG_RESET_ADAPTER, instance);
6954 delay(100 * drv_usectohz(MILLISEC));
6955 status = RD_OB_DRWE(instance);
6956 while (status & DIAG_RESET_ADAPTER) {
6957 delay(100 * drv_usectohz(MILLISEC));
6958 status = RD_OB_DRWE(instance);
6959 if (retry++ == 100) {
6960 dev_err(instance->dip, CE_WARN, "mrsas_reset_ppc: "
6961 "RESET FAILED. KILL adapter called.");
6962
6963 (void) mrsas_kill_adapter(instance);
6964 return (DDI_FAILURE);
6965 }
6966 }
6967 con_log(CL_ANN, (CE_NOTE, "mrsas_reset_ppc: Adapter reset complete"));
6968 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc: "
6969 "Calling mfi_state_transition_to_ready"));
6970
6971 /* Mark HBA as bad, if FW is fault after 3 continuous resets */
6972 if (mfi_state_transition_to_ready(instance) ||
6973 debug_fw_faults_after_ocr_g == 1) {
6974 cur_abs_reg_val =
6975 instance->func_ptr->read_fw_status_reg(instance);
6976 fw_state = cur_abs_reg_val & MFI_STATE_MASK;
6977
6978 #ifdef OCRDEBUG
6979 con_log(CL_ANN1, (CE_NOTE,
6980 "mrsas_reset_ppc :before fake: FW is not ready "
6981 "FW state = 0x%x", fw_state));
6982 if (debug_fw_faults_after_ocr_g == 1)
6983 fw_state = MFI_STATE_FAULT;
6984 #endif
6985
6986 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc : FW is not ready "
6987 "FW state = 0x%x", fw_state));
6988
6989 if (fw_state == MFI_STATE_FAULT) {
6990 /* increment the count */
6991 instance->fw_fault_count_after_ocr++;
6992 if (instance->fw_fault_count_after_ocr
6993 < MAX_FW_RESET_COUNT) {
6994 dev_err(instance->dip, CE_WARN,
6995 "mrsas_reset_ppc: "
6996 "FW is in fault after OCR count %d "
6997 "Retry Reset",
6998 instance->fw_fault_count_after_ocr);
6999 goto retry_reset;
7000
7001 } else {
7002 dev_err(instance->dip, CE_WARN,
7003 "mrsas_reset_ppc: "
7004 "Max Reset Count exceeded >%d"
7005 "Mark HBA as bad, KILL adapter",
7006 MAX_FW_RESET_COUNT);
7007
7008 (void) mrsas_kill_adapter(instance);
7009 return (DDI_FAILURE);
7010 }
7011 }
7012 }
7013 /* reset the counter as FW is up after OCR */
7014 instance->fw_fault_count_after_ocr = 0;
7015
7016
7017 ddi_put32(instance->mfi_internal_dma_obj.acc_handle,
7018 instance->producer, 0);
7019
7020 ddi_put32(instance->mfi_internal_dma_obj.acc_handle,
7021 instance->consumer, 0);
7022
7023 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc: "
7024 " after resetting produconsumer chck indexs:"
7025 "producer %x consumer %x", *instance->producer,
7026 *instance->consumer));
7027
7028 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc: "
7029 "Calling mrsas_issue_init_mfi"));
7030 (void) mrsas_issue_init_mfi(instance);
7031 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc: "
7032 "mrsas_issue_init_mfi Done"));
7033
7034 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc: "
7035 "Calling mrsas_print_pending_cmd\n"));
7036 (void) mrsas_print_pending_cmds(instance);
7037 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc: "
7038 "mrsas_print_pending_cmd done\n"));
7039
7040 instance->func_ptr->enable_intr(instance);
7041 instance->fw_outstanding = 0;
7042
7043 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc: "
7044 "Calling mrsas_issue_pending_cmds"));
7045 (void) mrsas_issue_pending_cmds(instance);
7046 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc: "
7047 "issue_pending_cmds done.\n"));
7048
7049 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc: "
7050 "Calling aen registration"));
7051
7052
7053 instance->aen_cmd->retry_count_for_ocr = 0;
7054 instance->aen_cmd->drv_pkt_time = 0;
7055
7056 instance->func_ptr->issue_cmd(instance->aen_cmd, instance);
7057 con_log(CL_ANN1, (CE_NOTE, "Unsetting adpresetinprogress flag.\n"));
7058
7059 mutex_enter(&instance->ocr_flags_mtx);
7060 instance->adapterresetinprogress = 0;
7061 mutex_exit(&instance->ocr_flags_mtx);
7062 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc: "
7063 "adpterresetinprogress flag unset"));
7064
7065 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc done\n"));
7066 return (DDI_SUCCESS);
7067 }
7068
7069 /*
7070 * FMA functions.
7071 */
7072 int
mrsas_common_check(struct mrsas_instance * instance,struct mrsas_cmd * cmd)7073 mrsas_common_check(struct mrsas_instance *instance, struct mrsas_cmd *cmd)
7074 {
7075 int ret = DDI_SUCCESS;
7076
7077 if (cmd != NULL &&
7078 mrsas_check_dma_handle(cmd->frame_dma_obj.dma_handle) !=
7079 DDI_SUCCESS) {
7080 ddi_fm_service_impact(instance->dip, DDI_SERVICE_UNAFFECTED);
7081 if (cmd->pkt != NULL) {
7082 cmd->pkt->pkt_reason = CMD_TRAN_ERR;
7083 cmd->pkt->pkt_statistics = 0;
7084 }
7085 ret = DDI_FAILURE;
7086 }
7087 if (mrsas_check_dma_handle(instance->mfi_internal_dma_obj.dma_handle)
7088 != DDI_SUCCESS) {
7089 ddi_fm_service_impact(instance->dip, DDI_SERVICE_UNAFFECTED);
7090 if (cmd != NULL && cmd->pkt != NULL) {
7091 cmd->pkt->pkt_reason = CMD_TRAN_ERR;
7092 cmd->pkt->pkt_statistics = 0;
7093 }
7094 ret = DDI_FAILURE;
7095 }
7096 if (mrsas_check_dma_handle(instance->mfi_evt_detail_obj.dma_handle) !=
7097 DDI_SUCCESS) {
7098 ddi_fm_service_impact(instance->dip, DDI_SERVICE_UNAFFECTED);
7099 if (cmd != NULL && cmd->pkt != NULL) {
7100 cmd->pkt->pkt_reason = CMD_TRAN_ERR;
7101 cmd->pkt->pkt_statistics = 0;
7102 }
7103 ret = DDI_FAILURE;
7104 }
7105 if (mrsas_check_acc_handle(instance->regmap_handle) != DDI_SUCCESS) {
7106 ddi_fm_service_impact(instance->dip, DDI_SERVICE_UNAFFECTED);
7107
7108 ddi_fm_acc_err_clear(instance->regmap_handle, DDI_FME_VER0);
7109
7110 if (cmd != NULL && cmd->pkt != NULL) {
7111 cmd->pkt->pkt_reason = CMD_TRAN_ERR;
7112 cmd->pkt->pkt_statistics = 0;
7113 }
7114 ret = DDI_FAILURE;
7115 }
7116
7117 return (ret);
7118 }
7119
7120 /*ARGSUSED*/
7121 static int
mrsas_fm_error_cb(dev_info_t * dip,ddi_fm_error_t * err,const void * impl_data)7122 mrsas_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data)
7123 {
7124 /*
7125 * as the driver can always deal with an error in any dma or
7126 * access handle, we can just return the fme_status value.
7127 */
7128 pci_ereport_post(dip, err, NULL);
7129 return (err->fme_status);
7130 }
7131
7132 static void
mrsas_fm_init(struct mrsas_instance * instance)7133 mrsas_fm_init(struct mrsas_instance *instance)
7134 {
7135 /* Need to change iblock to priority for new MSI intr */
7136 ddi_iblock_cookie_t fm_ibc;
7137
7138 /* Only register with IO Fault Services if we have some capability */
7139 if (instance->fm_capabilities) {
7140 /* Adjust access and dma attributes for FMA */
7141 endian_attr.devacc_attr_access = DDI_FLAGERR_ACC;
7142 mrsas_generic_dma_attr.dma_attr_flags = DDI_DMA_FLAGERR;
7143
7144 /*
7145 * Register capabilities with IO Fault Services.
7146 * fm_capabilities will be updated to indicate
7147 * capabilities actually supported (not requested.)
7148 */
7149
7150 ddi_fm_init(instance->dip, &instance->fm_capabilities, &fm_ibc);
7151
7152 /*
7153 * Initialize pci ereport capabilities if ereport
7154 * capable (should always be.)
7155 */
7156
7157 if (DDI_FM_EREPORT_CAP(instance->fm_capabilities) ||
7158 DDI_FM_ERRCB_CAP(instance->fm_capabilities)) {
7159 pci_ereport_setup(instance->dip);
7160 }
7161
7162 /*
7163 * Register error callback if error callback capable.
7164 */
7165 if (DDI_FM_ERRCB_CAP(instance->fm_capabilities)) {
7166 ddi_fm_handler_register(instance->dip,
7167 mrsas_fm_error_cb, (void*) instance);
7168 }
7169 } else {
7170 endian_attr.devacc_attr_access = DDI_DEFAULT_ACC;
7171 mrsas_generic_dma_attr.dma_attr_flags = 0;
7172 }
7173 }
7174
7175 static void
mrsas_fm_fini(struct mrsas_instance * instance)7176 mrsas_fm_fini(struct mrsas_instance *instance)
7177 {
7178 /* Only unregister FMA capabilities if registered */
7179 if (instance->fm_capabilities) {
7180 /*
7181 * Un-register error callback if error callback capable.
7182 */
7183 if (DDI_FM_ERRCB_CAP(instance->fm_capabilities)) {
7184 ddi_fm_handler_unregister(instance->dip);
7185 }
7186
7187 /*
7188 * Release any resources allocated by pci_ereport_setup()
7189 */
7190 if (DDI_FM_EREPORT_CAP(instance->fm_capabilities) ||
7191 DDI_FM_ERRCB_CAP(instance->fm_capabilities)) {
7192 pci_ereport_teardown(instance->dip);
7193 }
7194
7195 /* Unregister from IO Fault Services */
7196 ddi_fm_fini(instance->dip);
7197
7198 /* Adjust access and dma attributes for FMA */
7199 endian_attr.devacc_attr_access = DDI_DEFAULT_ACC;
7200 mrsas_generic_dma_attr.dma_attr_flags = 0;
7201 }
7202 }
7203
7204 int
mrsas_check_acc_handle(ddi_acc_handle_t handle)7205 mrsas_check_acc_handle(ddi_acc_handle_t handle)
7206 {
7207 ddi_fm_error_t de;
7208
7209 if (handle == NULL) {
7210 return (DDI_FAILURE);
7211 }
7212
7213 ddi_fm_acc_err_get(handle, &de, DDI_FME_VERSION);
7214
7215 return (de.fme_status);
7216 }
7217
7218 int
mrsas_check_dma_handle(ddi_dma_handle_t handle)7219 mrsas_check_dma_handle(ddi_dma_handle_t handle)
7220 {
7221 ddi_fm_error_t de;
7222
7223 if (handle == NULL) {
7224 return (DDI_FAILURE);
7225 }
7226
7227 ddi_fm_dma_err_get(handle, &de, DDI_FME_VERSION);
7228
7229 return (de.fme_status);
7230 }
7231
7232 void
mrsas_fm_ereport(struct mrsas_instance * instance,char * detail)7233 mrsas_fm_ereport(struct mrsas_instance *instance, char *detail)
7234 {
7235 uint64_t ena;
7236 char buf[FM_MAX_CLASS];
7237
7238 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", DDI_FM_DEVICE, detail);
7239 ena = fm_ena_generate(0, FM_ENA_FMT1);
7240 if (DDI_FM_EREPORT_CAP(instance->fm_capabilities)) {
7241 ddi_fm_ereport_post(instance->dip, buf, ena, DDI_NOSLEEP,
7242 FM_VERSION, DATA_TYPE_UINT8, FM_EREPORT_VERSION, NULL);
7243 }
7244 }
7245
7246 static int
mrsas_add_intrs(struct mrsas_instance * instance,int intr_type)7247 mrsas_add_intrs(struct mrsas_instance *instance, int intr_type)
7248 {
7249
7250 dev_info_t *dip = instance->dip;
7251 int avail, actual, count;
7252 int i, flag, ret;
7253
7254 con_log(CL_DLEVEL1, (CE_NOTE, "mrsas_add_intrs: intr_type = %x",
7255 intr_type));
7256
7257 /* Get number of interrupts */
7258 ret = ddi_intr_get_nintrs(dip, intr_type, &count);
7259 if ((ret != DDI_SUCCESS) || (count == 0)) {
7260 con_log(CL_ANN, (CE_WARN, "ddi_intr_get_nintrs() failed:"
7261 "ret %d count %d", ret, count));
7262
7263 return (DDI_FAILURE);
7264 }
7265
7266 con_log(CL_DLEVEL1, (CE_NOTE, "mrsas_add_intrs: count = %d ", count));
7267
7268 /* Get number of available interrupts */
7269 ret = ddi_intr_get_navail(dip, intr_type, &avail);
7270 if ((ret != DDI_SUCCESS) || (avail == 0)) {
7271 con_log(CL_ANN, (CE_WARN, "ddi_intr_get_navail() failed:"
7272 "ret %d avail %d", ret, avail));
7273
7274 return (DDI_FAILURE);
7275 }
7276 con_log(CL_DLEVEL1, (CE_NOTE, "mrsas_add_intrs: avail = %d ", avail));
7277
7278 /* Only one interrupt routine. So limit the count to 1 */
7279 if (count > 1) {
7280 count = 1;
7281 }
7282
7283 /*
7284 * Allocate an array of interrupt handlers. Currently we support
7285 * only one interrupt. The framework can be extended later.
7286 */
7287 instance->intr_htable_size = count * sizeof (ddi_intr_handle_t);
7288 instance->intr_htable = kmem_zalloc(instance->intr_htable_size,
7289 KM_SLEEP);
7290 ASSERT(instance->intr_htable);
7291
7292 flag = ((intr_type == DDI_INTR_TYPE_MSI) ||
7293 (intr_type == DDI_INTR_TYPE_MSIX)) ?
7294 DDI_INTR_ALLOC_STRICT : DDI_INTR_ALLOC_NORMAL;
7295
7296 /* Allocate interrupt */
7297 ret = ddi_intr_alloc(dip, instance->intr_htable, intr_type, 0,
7298 count, &actual, flag);
7299
7300 if ((ret != DDI_SUCCESS) || (actual == 0)) {
7301 con_log(CL_ANN, (CE_WARN, "mrsas_add_intrs: "
7302 "avail = %d", avail));
7303 goto mrsas_free_htable;
7304 }
7305
7306 if (actual < count) {
7307 con_log(CL_ANN, (CE_WARN, "mrsas_add_intrs: "
7308 "Requested = %d Received = %d", count, actual));
7309 }
7310 instance->intr_cnt = actual;
7311
7312 /*
7313 * Get the priority of the interrupt allocated.
7314 */
7315 if ((ret = ddi_intr_get_pri(instance->intr_htable[0],
7316 &instance->intr_pri)) != DDI_SUCCESS) {
7317 con_log(CL_ANN, (CE_WARN, "mrsas_add_intrs: "
7318 "get priority call failed"));
7319 goto mrsas_free_handles;
7320 }
7321
7322 /*
7323 * Test for high level mutex. we don't support them.
7324 */
7325 if (instance->intr_pri >= ddi_intr_get_hilevel_pri()) {
7326 con_log(CL_ANN, (CE_WARN, "mrsas_add_intrs: "
7327 "High level interrupts not supported."));
7328 goto mrsas_free_handles;
7329 }
7330
7331 con_log(CL_DLEVEL1, (CE_NOTE, "mrsas_add_intrs: intr_pri = 0x%x ",
7332 instance->intr_pri));
7333
7334 /* Call ddi_intr_add_handler() */
7335 for (i = 0; i < actual; i++) {
7336 ret = ddi_intr_add_handler(instance->intr_htable[i],
7337 mrsas_isr, (caddr_t)instance, (caddr_t)(uintptr_t)i);
7338
7339 if (ret != DDI_SUCCESS) {
7340 con_log(CL_ANN, (CE_WARN, "mrsas_add_intrs:"
7341 "failed %d", ret));
7342 goto mrsas_free_handles;
7343 }
7344
7345 }
7346
7347 con_log(CL_DLEVEL1, (CE_NOTE, " ddi_intr_add_handler done"));
7348
7349 if ((ret = ddi_intr_get_cap(instance->intr_htable[0],
7350 &instance->intr_cap)) != DDI_SUCCESS) {
7351 con_log(CL_ANN, (CE_WARN, "ddi_intr_get_cap() failed %d",
7352 ret));
7353 goto mrsas_free_handlers;
7354 }
7355
7356 if (instance->intr_cap & DDI_INTR_FLAG_BLOCK) {
7357 con_log(CL_ANN, (CE_WARN, "Calling ddi_intr_block _enable"));
7358
7359 (void) ddi_intr_block_enable(instance->intr_htable,
7360 instance->intr_cnt);
7361 } else {
7362 con_log(CL_ANN, (CE_NOTE, " calling ddi_intr_enable"));
7363
7364 for (i = 0; i < instance->intr_cnt; i++) {
7365 (void) ddi_intr_enable(instance->intr_htable[i]);
7366 con_log(CL_ANN, (CE_NOTE, "ddi intr enable returns "
7367 "%d", i));
7368 }
7369 }
7370
7371 return (DDI_SUCCESS);
7372
7373 mrsas_free_handlers:
7374 for (i = 0; i < actual; i++)
7375 (void) ddi_intr_remove_handler(instance->intr_htable[i]);
7376
7377 mrsas_free_handles:
7378 for (i = 0; i < actual; i++)
7379 (void) ddi_intr_free(instance->intr_htable[i]);
7380
7381 mrsas_free_htable:
7382 if (instance->intr_htable != NULL)
7383 kmem_free(instance->intr_htable, instance->intr_htable_size);
7384
7385 instance->intr_htable = NULL;
7386 instance->intr_htable_size = 0;
7387
7388 return (DDI_FAILURE);
7389
7390 }
7391
7392
7393 static void
mrsas_rem_intrs(struct mrsas_instance * instance)7394 mrsas_rem_intrs(struct mrsas_instance *instance)
7395 {
7396 int i;
7397
7398 con_log(CL_ANN, (CE_NOTE, "mrsas_rem_intrs called"));
7399
7400 /* Disable all interrupts first */
7401 if (instance->intr_cap & DDI_INTR_FLAG_BLOCK) {
7402 (void) ddi_intr_block_disable(instance->intr_htable,
7403 instance->intr_cnt);
7404 } else {
7405 for (i = 0; i < instance->intr_cnt; i++) {
7406 (void) ddi_intr_disable(instance->intr_htable[i]);
7407 }
7408 }
7409
7410 /* Remove all the handlers */
7411
7412 for (i = 0; i < instance->intr_cnt; i++) {
7413 (void) ddi_intr_remove_handler(instance->intr_htable[i]);
7414 (void) ddi_intr_free(instance->intr_htable[i]);
7415 }
7416
7417 if (instance->intr_htable != NULL)
7418 kmem_free(instance->intr_htable, instance->intr_htable_size);
7419
7420 instance->intr_htable = NULL;
7421 instance->intr_htable_size = 0;
7422
7423 }
7424
7425 static int
mrsas_tran_bus_config(dev_info_t * parent,uint_t flags,ddi_bus_config_op_t op,void * arg,dev_info_t ** childp)7426 mrsas_tran_bus_config(dev_info_t *parent, uint_t flags,
7427 ddi_bus_config_op_t op, void *arg, dev_info_t **childp)
7428 {
7429 struct mrsas_instance *instance;
7430 int rval = NDI_SUCCESS;
7431
7432 char *ptr = NULL;
7433 int tgt, lun;
7434
7435 con_log(CL_ANN1, (CE_NOTE, "Bus config called for op = %x", op));
7436
7437 if ((instance = ddi_get_soft_state(mrsas_state,
7438 ddi_get_instance(parent))) == NULL) {
7439 return (NDI_FAILURE);
7440 }
7441
7442 /* Hold nexus during bus_config */
7443 ndi_devi_enter(parent);
7444 switch (op) {
7445 case BUS_CONFIG_ONE: {
7446
7447 /* parse wwid/target name out of name given */
7448 if ((ptr = strchr((char *)arg, '@')) == NULL) {
7449 rval = NDI_FAILURE;
7450 break;
7451 }
7452 ptr++;
7453
7454 if (mrsas_parse_devname(arg, &tgt, &lun) != 0) {
7455 rval = NDI_FAILURE;
7456 break;
7457 }
7458
7459 if (lun == 0) {
7460 rval = mrsas_config_ld(instance, tgt, lun, childp);
7461 } else if ((instance->tbolt || instance->skinny) && lun != 0) {
7462 rval = mrsas_tbolt_config_pd(instance,
7463 tgt, lun, childp);
7464 } else {
7465 rval = NDI_FAILURE;
7466 }
7467
7468 break;
7469 }
7470 case BUS_CONFIG_DRIVER:
7471 case BUS_CONFIG_ALL: {
7472
7473 rval = mrsas_config_all_devices(instance);
7474
7475 rval = NDI_SUCCESS;
7476 break;
7477 }
7478 }
7479
7480 if (rval == NDI_SUCCESS) {
7481 rval = ndi_busop_bus_config(parent, flags, op, arg, childp, 0);
7482
7483 }
7484 ndi_devi_exit(parent);
7485
7486 con_log(CL_ANN1, (CE_NOTE, "mrsas_tran_bus_config: rval = %x",
7487 rval));
7488 return (rval);
7489 }
7490
7491 static int
mrsas_config_all_devices(struct mrsas_instance * instance)7492 mrsas_config_all_devices(struct mrsas_instance *instance)
7493 {
7494 int rval, tgt;
7495
7496 for (tgt = 0; tgt < MRDRV_MAX_LD; tgt++) {
7497 (void) mrsas_config_ld(instance, tgt, 0, NULL);
7498
7499 }
7500
7501 /* Config PD devices connected to the card */
7502 if (instance->tbolt || instance->skinny) {
7503 for (tgt = 0; tgt < instance->mr_tbolt_pd_max; tgt++) {
7504 (void) mrsas_tbolt_config_pd(instance, tgt, 1, NULL);
7505 }
7506 }
7507
7508 rval = NDI_SUCCESS;
7509 return (rval);
7510 }
7511
7512 static int
mrsas_parse_devname(char * devnm,int * tgt,int * lun)7513 mrsas_parse_devname(char *devnm, int *tgt, int *lun)
7514 {
7515 char devbuf[SCSI_MAXNAMELEN];
7516 char *addr;
7517 char *p, *tp, *lp;
7518 long num;
7519
7520 /* Parse dev name and address */
7521 (void) strcpy(devbuf, devnm);
7522 addr = "";
7523 for (p = devbuf; *p != '\0'; p++) {
7524 if (*p == '@') {
7525 addr = p + 1;
7526 *p = '\0';
7527 } else if (*p == ':') {
7528 *p = '\0';
7529 break;
7530 }
7531 }
7532
7533 /* Parse target and lun */
7534 for (p = tp = addr, lp = NULL; *p != '\0'; p++) {
7535 if (*p == ',') {
7536 lp = p + 1;
7537 *p = '\0';
7538 break;
7539 }
7540 }
7541 if (tgt && tp) {
7542 if (ddi_strtol(tp, NULL, 0x10, &num)) {
7543 return (DDI_FAILURE); /* Can declare this as constant */
7544 }
7545 *tgt = (int)num;
7546 }
7547 if (lun && lp) {
7548 if (ddi_strtol(lp, NULL, 0x10, &num)) {
7549 return (DDI_FAILURE);
7550 }
7551 *lun = (int)num;
7552 }
7553 return (DDI_SUCCESS); /* Success case */
7554 }
7555
7556 static int
mrsas_config_ld(struct mrsas_instance * instance,uint16_t tgt,uint8_t lun,dev_info_t ** ldip)7557 mrsas_config_ld(struct mrsas_instance *instance, uint16_t tgt,
7558 uint8_t lun, dev_info_t **ldip)
7559 {
7560 struct scsi_device *sd;
7561 dev_info_t *child;
7562 int rval;
7563
7564 con_log(CL_DLEVEL1, (CE_NOTE, "mrsas_config_ld: t = %d l = %d",
7565 tgt, lun));
7566
7567 if ((child = mrsas_find_child(instance, tgt, lun)) != NULL) {
7568 if (ldip) {
7569 *ldip = child;
7570 }
7571 if (instance->mr_ld_list[tgt].flag != MRDRV_TGT_VALID) {
7572 rval = mrsas_service_evt(instance, tgt, 0,
7573 MRSAS_EVT_UNCONFIG_TGT, 0);
7574 con_log(CL_ANN1, (CE_WARN,
7575 "mr_sas: DELETING STALE ENTRY rval = %d "
7576 "tgt id = %d ", rval, tgt));
7577 return (NDI_FAILURE);
7578 }
7579 return (NDI_SUCCESS);
7580 }
7581
7582 sd = kmem_zalloc(sizeof (struct scsi_device), KM_SLEEP);
7583 sd->sd_address.a_hba_tran = instance->tran;
7584 sd->sd_address.a_target = (uint16_t)tgt;
7585 sd->sd_address.a_lun = (uint8_t)lun;
7586
7587 if (scsi_hba_probe(sd, NULL) == SCSIPROBE_EXISTS)
7588 rval = mrsas_config_scsi_device(instance, sd, ldip);
7589 else
7590 rval = NDI_FAILURE;
7591
7592 /* sd_unprobe is blank now. Free buffer manually */
7593 if (sd->sd_inq) {
7594 kmem_free(sd->sd_inq, SUN_INQSIZE);
7595 sd->sd_inq = (struct scsi_inquiry *)NULL;
7596 }
7597
7598 kmem_free(sd, sizeof (struct scsi_device));
7599 con_log(CL_DLEVEL1, (CE_NOTE, "mrsas_config_ld: return rval = %d",
7600 rval));
7601 return (rval);
7602 }
7603
7604 int
mrsas_config_scsi_device(struct mrsas_instance * instance,struct scsi_device * sd,dev_info_t ** dipp)7605 mrsas_config_scsi_device(struct mrsas_instance *instance,
7606 struct scsi_device *sd, dev_info_t **dipp)
7607 {
7608 char *nodename = NULL;
7609 char **compatible = NULL;
7610 int ncompatible = 0;
7611 char *childname;
7612 dev_info_t *ldip = NULL;
7613 int tgt = sd->sd_address.a_target;
7614 int lun = sd->sd_address.a_lun;
7615 int dtype = sd->sd_inq->inq_dtype & DTYPE_MASK;
7616 int rval;
7617
7618 con_log(CL_DLEVEL1, (CE_NOTE, "mr_sas: scsi_device t%dL%d", tgt, lun));
7619 scsi_hba_nodename_compatible_get(sd->sd_inq, NULL, dtype,
7620 NULL, &nodename, &compatible, &ncompatible);
7621
7622 if (nodename == NULL) {
7623 con_log(CL_ANN1, (CE_WARN, "mr_sas: Found no compatible driver "
7624 "for t%dL%d", tgt, lun));
7625 rval = NDI_FAILURE;
7626 goto finish;
7627 }
7628
7629 childname = (dtype == DTYPE_DIRECT) ? "sd" : nodename;
7630 con_log(CL_DLEVEL1, (CE_NOTE,
7631 "mr_sas: Childname = %2s nodename = %s", childname, nodename));
7632
7633 /* Create a dev node */
7634 rval = ndi_devi_alloc(instance->dip, childname, DEVI_SID_NODEID, &ldip);
7635 con_log(CL_DLEVEL1, (CE_NOTE,
7636 "mr_sas_config_scsi_device: ndi_devi_alloc rval = %x", rval));
7637 if (rval == NDI_SUCCESS) {
7638 if (ndi_prop_update_int(DDI_DEV_T_NONE, ldip, "target", tgt) !=
7639 DDI_PROP_SUCCESS) {
7640 con_log(CL_ANN1, (CE_WARN, "mr_sas: unable to create "
7641 "property for t%dl%d target", tgt, lun));
7642 rval = NDI_FAILURE;
7643 goto finish;
7644 }
7645 if (ndi_prop_update_int(DDI_DEV_T_NONE, ldip, "lun", lun) !=
7646 DDI_PROP_SUCCESS) {
7647 con_log(CL_ANN1, (CE_WARN, "mr_sas: unable to create "
7648 "property for t%dl%d lun", tgt, lun));
7649 rval = NDI_FAILURE;
7650 goto finish;
7651 }
7652
7653 if (ndi_prop_update_string_array(DDI_DEV_T_NONE, ldip,
7654 "compatible", compatible, ncompatible) !=
7655 DDI_PROP_SUCCESS) {
7656 con_log(CL_ANN1, (CE_WARN, "mr_sas: unable to create "
7657 "property for t%dl%d compatible", tgt, lun));
7658 rval = NDI_FAILURE;
7659 goto finish;
7660 }
7661
7662 rval = ndi_devi_online(ldip, NDI_ONLINE_ATTACH);
7663 if (rval != NDI_SUCCESS) {
7664 con_log(CL_ANN1, (CE_WARN, "mr_sas: unable to online "
7665 "t%dl%d", tgt, lun));
7666 ndi_prop_remove_all(ldip);
7667 (void) ndi_devi_free(ldip);
7668 } else {
7669 con_log(CL_ANN1, (CE_CONT, "mr_sas: online Done :"
7670 "0 t%dl%d", tgt, lun));
7671 }
7672
7673 }
7674 finish:
7675 if (dipp) {
7676 *dipp = ldip;
7677 }
7678
7679 con_log(CL_DLEVEL1, (CE_NOTE,
7680 "mr_sas: config_scsi_device rval = %d t%dL%d",
7681 rval, tgt, lun));
7682 scsi_hba_nodename_compatible_free(nodename, compatible);
7683 return (rval);
7684 }
7685
7686 /*ARGSUSED*/
7687 int
mrsas_service_evt(struct mrsas_instance * instance,int tgt,int lun,int event,uint64_t wwn)7688 mrsas_service_evt(struct mrsas_instance *instance, int tgt, int lun, int event,
7689 uint64_t wwn)
7690 {
7691 struct mrsas_eventinfo *mrevt = NULL;
7692
7693 con_log(CL_ANN1, (CE_NOTE,
7694 "mrsas_service_evt called for t%dl%d event = %d",
7695 tgt, lun, event));
7696
7697 if ((instance->taskq == NULL) || (mrevt =
7698 kmem_zalloc(sizeof (struct mrsas_eventinfo), KM_NOSLEEP)) == NULL) {
7699 return (ENOMEM);
7700 }
7701
7702 mrevt->instance = instance;
7703 mrevt->tgt = tgt;
7704 mrevt->lun = lun;
7705 mrevt->event = event;
7706 mrevt->wwn = wwn;
7707
7708 if ((ddi_taskq_dispatch(instance->taskq,
7709 (void (*)(void *))mrsas_issue_evt_taskq, mrevt, DDI_NOSLEEP)) !=
7710 DDI_SUCCESS) {
7711 con_log(CL_ANN1, (CE_NOTE,
7712 "mr_sas: Event task failed for t%dl%d event = %d",
7713 tgt, lun, event));
7714 kmem_free(mrevt, sizeof (struct mrsas_eventinfo));
7715 return (DDI_FAILURE);
7716 }
7717 DTRACE_PROBE3(service_evt, int, tgt, int, lun, int, event);
7718 return (DDI_SUCCESS);
7719 }
7720
7721 static void
mrsas_issue_evt_taskq(struct mrsas_eventinfo * mrevt)7722 mrsas_issue_evt_taskq(struct mrsas_eventinfo *mrevt)
7723 {
7724 struct mrsas_instance *instance = mrevt->instance;
7725 dev_info_t *dip, *pdip;
7726 char *devname;
7727
7728 con_log(CL_ANN1, (CE_NOTE, "mrsas_issue_evt_taskq: called for"
7729 " tgt %d lun %d event %d",
7730 mrevt->tgt, mrevt->lun, mrevt->event));
7731
7732 if (mrevt->tgt < MRDRV_MAX_LD && mrevt->lun == 0) {
7733 mutex_enter(&instance->config_dev_mtx);
7734 dip = instance->mr_ld_list[mrevt->tgt].dip;
7735 mutex_exit(&instance->config_dev_mtx);
7736 } else {
7737 mutex_enter(&instance->config_dev_mtx);
7738 dip = instance->mr_tbolt_pd_list[mrevt->tgt].dip;
7739 mutex_exit(&instance->config_dev_mtx);
7740 }
7741
7742
7743 ndi_devi_enter(instance->dip);
7744 switch (mrevt->event) {
7745 case MRSAS_EVT_CONFIG_TGT:
7746 if (dip == NULL) {
7747
7748 if (mrevt->lun == 0) {
7749 (void) mrsas_config_ld(instance, mrevt->tgt,
7750 0, NULL);
7751 } else if (instance->tbolt || instance->skinny) {
7752 (void) mrsas_tbolt_config_pd(instance,
7753 mrevt->tgt,
7754 1, NULL);
7755 }
7756 con_log(CL_ANN1, (CE_NOTE,
7757 "mr_sas: EVT_CONFIG_TGT called:"
7758 " for tgt %d lun %d event %d",
7759 mrevt->tgt, mrevt->lun, mrevt->event));
7760
7761 } else {
7762 con_log(CL_ANN1, (CE_NOTE,
7763 "mr_sas: EVT_CONFIG_TGT dip != NULL:"
7764 " for tgt %d lun %d event %d",
7765 mrevt->tgt, mrevt->lun, mrevt->event));
7766 }
7767 break;
7768 case MRSAS_EVT_UNCONFIG_TGT:
7769 if (dip) {
7770 if (i_ddi_devi_attached(dip)) {
7771
7772 pdip = ddi_get_parent(dip);
7773
7774 devname = kmem_zalloc(MAXNAMELEN + 1, KM_SLEEP);
7775 (void) ddi_deviname(dip, devname);
7776
7777 (void) devfs_clean(pdip, devname + 1,
7778 DV_CLEAN_FORCE);
7779 kmem_free(devname, MAXNAMELEN + 1);
7780 }
7781 (void) ndi_devi_offline(dip, NDI_DEVI_REMOVE);
7782 con_log(CL_ANN1, (CE_NOTE,
7783 "mr_sas: EVT_UNCONFIG_TGT called:"
7784 " for tgt %d lun %d event %d",
7785 mrevt->tgt, mrevt->lun, mrevt->event));
7786 } else {
7787 con_log(CL_ANN1, (CE_NOTE,
7788 "mr_sas: EVT_UNCONFIG_TGT dip == NULL:"
7789 " for tgt %d lun %d event %d",
7790 mrevt->tgt, mrevt->lun, mrevt->event));
7791 }
7792 break;
7793 }
7794 kmem_free(mrevt, sizeof (struct mrsas_eventinfo));
7795 ndi_devi_exit(instance->dip);
7796 }
7797
7798
7799 int
mrsas_mode_sense_build(struct scsi_pkt * pkt)7800 mrsas_mode_sense_build(struct scsi_pkt *pkt)
7801 {
7802 union scsi_cdb *cdbp;
7803 uint16_t page_code;
7804 struct scsa_cmd *acmd;
7805 struct buf *bp;
7806 struct mode_header *modehdrp;
7807
7808 cdbp = (void *)pkt->pkt_cdbp;
7809 page_code = cdbp->cdb_un.sg.scsi[0];
7810 acmd = PKT2CMD(pkt);
7811 bp = acmd->cmd_buf;
7812 if ((!bp) && bp->b_un.b_addr && bp->b_bcount && acmd->cmd_dmacount) {
7813 con_log(CL_ANN1, (CE_WARN, "Failing MODESENSE Command"));
7814 /* ADD pkt statistics as Command failed. */
7815 return (0);
7816 }
7817
7818 bp_mapin(bp);
7819 bzero(bp->b_un.b_addr, bp->b_bcount);
7820
7821 switch (page_code) {
7822 case 0x3: {
7823 struct mode_format *page3p = NULL;
7824 modehdrp = (struct mode_header *)(bp->b_un.b_addr);
7825 modehdrp->bdesc_length = MODE_BLK_DESC_LENGTH;
7826
7827 page3p = (void *)((caddr_t)modehdrp +
7828 MODE_HEADER_LENGTH + MODE_BLK_DESC_LENGTH);
7829 page3p->mode_page.code = 0x3;
7830 page3p->mode_page.length =
7831 (uchar_t)(sizeof (struct mode_format));
7832 page3p->data_bytes_sect = 512;
7833 page3p->sect_track = 63;
7834 break;
7835 }
7836 case 0x4: {
7837 struct mode_geometry *page4p = NULL;
7838 modehdrp = (struct mode_header *)(bp->b_un.b_addr);
7839 modehdrp->bdesc_length = MODE_BLK_DESC_LENGTH;
7840
7841 page4p = (void *)((caddr_t)modehdrp +
7842 MODE_HEADER_LENGTH + MODE_BLK_DESC_LENGTH);
7843 page4p->mode_page.code = 0x4;
7844 page4p->mode_page.length =
7845 (uchar_t)(sizeof (struct mode_geometry));
7846 page4p->heads = 255;
7847 page4p->rpm = 10000;
7848 break;
7849 }
7850 default:
7851 break;
7852 }
7853 return (0);
7854 }
7855