1 // SPDX-License-Identifier: GPL-2.0 OR MIT
2 /*
3 * Copyright 2014-2022 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 */
24
25 #include <linux/printk.h>
26 #include <linux/slab.h>
27 #include <linux/mm_types.h>
28
29 #include "kfd_priv.h"
30 #include "kfd_mqd_manager.h"
31 #include "vi_structs.h"
32 #include "gca/gfx_8_0_sh_mask.h"
33 #include "gca/gfx_8_0_enum.h"
34 #include "oss/oss_3_0_sh_mask.h"
35
36 #define CP_MQD_CONTROL__PRIV_STATE__SHIFT 0x8
37
get_mqd(void * mqd)38 static inline struct vi_mqd *get_mqd(void *mqd)
39 {
40 return (struct vi_mqd *)mqd;
41 }
42
get_sdma_mqd(void * mqd)43 static inline struct vi_sdma_mqd *get_sdma_mqd(void *mqd)
44 {
45 return (struct vi_sdma_mqd *)mqd;
46 }
47
update_cu_mask(struct mqd_manager * mm,void * mqd,struct mqd_update_info * minfo)48 static void update_cu_mask(struct mqd_manager *mm, void *mqd,
49 struct mqd_update_info *minfo)
50 {
51 struct vi_mqd *m;
52 uint32_t se_mask[4] = {0}; /* 4 is the max # of SEs */
53
54 if (!minfo || !minfo->cu_mask.ptr)
55 return;
56
57 mqd_symmetrically_map_cu_mask(mm,
58 minfo->cu_mask.ptr, minfo->cu_mask.count, se_mask, 0);
59
60 m = get_mqd(mqd);
61 m->compute_static_thread_mgmt_se0 = se_mask[0];
62 m->compute_static_thread_mgmt_se1 = se_mask[1];
63 m->compute_static_thread_mgmt_se2 = se_mask[2];
64 m->compute_static_thread_mgmt_se3 = se_mask[3];
65
66 pr_debug("Update cu mask to %#x %#x %#x %#x\n",
67 m->compute_static_thread_mgmt_se0,
68 m->compute_static_thread_mgmt_se1,
69 m->compute_static_thread_mgmt_se2,
70 m->compute_static_thread_mgmt_se3);
71 }
72
set_priority(struct vi_mqd * m,struct queue_properties * q)73 static void set_priority(struct vi_mqd *m, struct queue_properties *q)
74 {
75 m->cp_hqd_pipe_priority = pipe_priority_map[q->priority];
76 /* m->cp_hqd_queue_priority = q->priority; */
77 }
78
allocate_mqd(struct mqd_manager * mm,struct queue_properties * q)79 static struct kfd_mem_obj *allocate_mqd(struct mqd_manager *mm,
80 struct queue_properties *q)
81 {
82 struct kfd_node *kfd = mm->dev;
83 struct kfd_mem_obj *mqd_mem_obj;
84
85 if (kfd_gtt_sa_allocate(kfd, sizeof(struct vi_mqd),
86 &mqd_mem_obj))
87 return NULL;
88
89 return mqd_mem_obj;
90 }
91
init_mqd(struct mqd_manager * mm,void ** mqd,struct kfd_mem_obj * mqd_mem_obj,uint64_t * gart_addr,struct queue_properties * q)92 static void init_mqd(struct mqd_manager *mm, void **mqd,
93 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr,
94 struct queue_properties *q)
95 {
96 uint64_t addr;
97 struct vi_mqd *m;
98
99 m = (struct vi_mqd *) mqd_mem_obj->cpu_ptr;
100 addr = mqd_mem_obj->gpu_addr;
101
102 memset(m, 0, sizeof(struct vi_mqd));
103
104 m->header = 0xC0310800;
105 m->compute_pipelinestat_enable = 1;
106 m->compute_static_thread_mgmt_se0 = 0xFFFFFFFF;
107 m->compute_static_thread_mgmt_se1 = 0xFFFFFFFF;
108 m->compute_static_thread_mgmt_se2 = 0xFFFFFFFF;
109 m->compute_static_thread_mgmt_se3 = 0xFFFFFFFF;
110
111 m->cp_hqd_persistent_state = CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK |
112 0x53 << CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT;
113
114 m->cp_mqd_control = 1 << CP_MQD_CONTROL__PRIV_STATE__SHIFT |
115 MTYPE_UC << CP_MQD_CONTROL__MTYPE__SHIFT;
116
117 m->cp_mqd_base_addr_lo = lower_32_bits(addr);
118 m->cp_mqd_base_addr_hi = upper_32_bits(addr);
119
120 m->cp_hqd_quantum = 1 << CP_HQD_QUANTUM__QUANTUM_EN__SHIFT |
121 1 << CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT |
122 1 << CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT;
123
124 set_priority(m, q);
125 m->cp_hqd_eop_rptr = 1 << CP_HQD_EOP_RPTR__INIT_FETCHER__SHIFT;
126
127 if (q->format == KFD_QUEUE_FORMAT_AQL)
128 m->cp_hqd_iq_rptr = 1;
129
130 if (q->tba_addr) {
131 m->compute_tba_lo = lower_32_bits(q->tba_addr >> 8);
132 m->compute_tba_hi = upper_32_bits(q->tba_addr >> 8);
133 m->compute_tma_lo = lower_32_bits(q->tma_addr >> 8);
134 m->compute_tma_hi = upper_32_bits(q->tma_addr >> 8);
135 m->compute_pgm_rsrc2 |=
136 (1 << COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT);
137 }
138
139 if (mm->dev->kfd->cwsr_enabled && q->ctx_save_restore_area_address) {
140 m->cp_hqd_persistent_state |=
141 (1 << CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT);
142 m->cp_hqd_ctx_save_base_addr_lo =
143 lower_32_bits(q->ctx_save_restore_area_address);
144 m->cp_hqd_ctx_save_base_addr_hi =
145 upper_32_bits(q->ctx_save_restore_area_address);
146 m->cp_hqd_ctx_save_size = q->ctx_save_restore_area_size;
147 m->cp_hqd_cntl_stack_size = q->ctl_stack_size;
148 m->cp_hqd_cntl_stack_offset = q->ctl_stack_size;
149 m->cp_hqd_wg_state_offset = q->ctl_stack_size;
150 }
151
152 *mqd = m;
153 if (gart_addr)
154 *gart_addr = addr;
155 mm->update_mqd(mm, m, q, NULL);
156 }
157
load_mqd(struct mqd_manager * mm,void * mqd,uint32_t pipe_id,uint32_t queue_id,struct queue_properties * p,struct mm_struct * mms)158 static int load_mqd(struct mqd_manager *mm, void *mqd,
159 uint32_t pipe_id, uint32_t queue_id,
160 struct queue_properties *p, struct mm_struct *mms)
161 {
162 /* AQL write pointer counts in 64B packets, PM4/CP counts in dwords. */
163 uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0);
164 uint32_t wptr_mask = (uint32_t)((p->queue_size / 4) - 1);
165
166 return mm->dev->kfd2kgd->hqd_load(mm->dev->adev, mqd, pipe_id, queue_id,
167 (uint32_t __user *)p->write_ptr,
168 wptr_shift, wptr_mask, mms, 0);
169 }
170
__update_mqd(struct mqd_manager * mm,void * mqd,struct queue_properties * q,struct mqd_update_info * minfo,unsigned int mtype,unsigned int atc_bit)171 static void __update_mqd(struct mqd_manager *mm, void *mqd,
172 struct queue_properties *q, struct mqd_update_info *minfo,
173 unsigned int mtype, unsigned int atc_bit)
174 {
175 struct vi_mqd *m;
176
177 m = get_mqd(mqd);
178
179 m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT |
180 atc_bit << CP_HQD_PQ_CONTROL__PQ_ATC__SHIFT |
181 mtype << CP_HQD_PQ_CONTROL__MTYPE__SHIFT;
182 m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1;
183 pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control);
184
185 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8);
186 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8);
187
188 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr);
189 m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr);
190 m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr);
191 m->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr);
192
193 m->cp_hqd_pq_doorbell_control =
194 q->doorbell_off <<
195 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT;
196 pr_debug("cp_hqd_pq_doorbell_control 0x%x\n",
197 m->cp_hqd_pq_doorbell_control);
198
199 m->cp_hqd_eop_control = atc_bit << CP_HQD_EOP_CONTROL__EOP_ATC__SHIFT |
200 mtype << CP_HQD_EOP_CONTROL__MTYPE__SHIFT;
201
202 m->cp_hqd_ib_control = atc_bit << CP_HQD_IB_CONTROL__IB_ATC__SHIFT |
203 3 << CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT |
204 mtype << CP_HQD_IB_CONTROL__MTYPE__SHIFT;
205
206 /*
207 * HW does not clamp this field correctly. Maximum EOP queue size
208 * is constrained by per-SE EOP done signal count, which is 8-bit.
209 * Limit is 0xFF EOP entries (= 0x7F8 dwords). CP will not submit
210 * more than (EOP entry count - 1) so a queue size of 0x800 dwords
211 * is safe, giving a maximum field value of 0xA.
212 */
213 m->cp_hqd_eop_control |= min(0xA,
214 order_base_2(q->eop_ring_buffer_size / 4) - 1);
215 m->cp_hqd_eop_base_addr_lo =
216 lower_32_bits(q->eop_ring_buffer_address >> 8);
217 m->cp_hqd_eop_base_addr_hi =
218 upper_32_bits(q->eop_ring_buffer_address >> 8);
219
220 m->cp_hqd_iq_timer = atc_bit << CP_HQD_IQ_TIMER__IQ_ATC__SHIFT |
221 mtype << CP_HQD_IQ_TIMER__MTYPE__SHIFT;
222
223 m->cp_hqd_vmid = q->vmid;
224
225 if (q->format == KFD_QUEUE_FORMAT_AQL) {
226 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK |
227 2 << CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT;
228 }
229
230 if (mm->dev->kfd->cwsr_enabled && q->ctx_save_restore_area_address)
231 m->cp_hqd_ctx_save_control =
232 atc_bit << CP_HQD_CTX_SAVE_CONTROL__ATC__SHIFT |
233 mtype << CP_HQD_CTX_SAVE_CONTROL__MTYPE__SHIFT;
234
235 update_cu_mask(mm, mqd, minfo);
236 set_priority(m, q);
237
238 q->is_active = QUEUE_IS_ACTIVE(*q);
239 }
240
check_preemption_failed(struct mqd_manager * mm,void * mqd)241 static bool check_preemption_failed(struct mqd_manager *mm, void *mqd)
242 {
243 struct vi_mqd *m = (struct vi_mqd *)mqd;
244
245 return kfd_check_hiq_mqd_doorbell_id(mm->dev, m->queue_doorbell_id0, 0);
246 }
247
update_mqd(struct mqd_manager * mm,void * mqd,struct queue_properties * q,struct mqd_update_info * minfo)248 static void update_mqd(struct mqd_manager *mm, void *mqd,
249 struct queue_properties *q,
250 struct mqd_update_info *minfo)
251 {
252 __update_mqd(mm, mqd, q, minfo, MTYPE_UC, 0);
253 }
254
get_wave_state(struct mqd_manager * mm,void * mqd,struct queue_properties * q,void __user * ctl_stack,u32 * ctl_stack_used_size,u32 * save_area_used_size)255 static int get_wave_state(struct mqd_manager *mm, void *mqd,
256 struct queue_properties *q,
257 void __user *ctl_stack,
258 u32 *ctl_stack_used_size,
259 u32 *save_area_used_size)
260 {
261 struct vi_mqd *m;
262
263 m = get_mqd(mqd);
264
265 *ctl_stack_used_size = m->cp_hqd_cntl_stack_size -
266 m->cp_hqd_cntl_stack_offset;
267 *save_area_used_size = m->cp_hqd_wg_state_offset -
268 m->cp_hqd_cntl_stack_size;
269
270 /* Control stack is not copied to user mode for GFXv8 because
271 * it's part of the context save area that is already
272 * accessible to user mode
273 */
274
275 return 0;
276 }
277
get_checkpoint_info(struct mqd_manager * mm,void * mqd,u32 * ctl_stack_size)278 static void get_checkpoint_info(struct mqd_manager *mm, void *mqd, u32 *ctl_stack_size)
279 {
280 /* Control stack is stored in user mode */
281 *ctl_stack_size = 0;
282 }
283
checkpoint_mqd(struct mqd_manager * mm,void * mqd,void * mqd_dst,void * ctl_stack_dst)284 static void checkpoint_mqd(struct mqd_manager *mm, void *mqd, void *mqd_dst, void *ctl_stack_dst)
285 {
286 struct vi_mqd *m;
287
288 m = get_mqd(mqd);
289
290 memcpy(mqd_dst, m, sizeof(struct vi_mqd));
291 }
292
restore_mqd(struct mqd_manager * mm,void ** mqd,struct kfd_mem_obj * mqd_mem_obj,uint64_t * gart_addr,struct queue_properties * qp,const void * mqd_src,const void * ctl_stack_src,const u32 ctl_stack_size)293 static void restore_mqd(struct mqd_manager *mm, void **mqd,
294 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr,
295 struct queue_properties *qp,
296 const void *mqd_src,
297 const void *ctl_stack_src, const u32 ctl_stack_size)
298 {
299 uint64_t addr;
300 struct vi_mqd *m;
301
302 m = (struct vi_mqd *) mqd_mem_obj->cpu_ptr;
303 addr = mqd_mem_obj->gpu_addr;
304
305 memcpy(m, mqd_src, sizeof(*m));
306
307 *mqd = m;
308 if (gart_addr)
309 *gart_addr = addr;
310
311 m->cp_hqd_pq_doorbell_control =
312 qp->doorbell_off <<
313 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT;
314 pr_debug("cp_hqd_pq_doorbell_control 0x%x\n",
315 m->cp_hqd_pq_doorbell_control);
316
317 qp->is_active = 0;
318 }
319
init_mqd_hiq(struct mqd_manager * mm,void ** mqd,struct kfd_mem_obj * mqd_mem_obj,uint64_t * gart_addr,struct queue_properties * q)320 static void init_mqd_hiq(struct mqd_manager *mm, void **mqd,
321 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr,
322 struct queue_properties *q)
323 {
324 struct vi_mqd *m;
325
326 init_mqd(mm, mqd, mqd_mem_obj, gart_addr, q);
327
328 m = get_mqd(*mqd);
329
330 m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT |
331 1 << CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT;
332 }
333
update_mqd_hiq(struct mqd_manager * mm,void * mqd,struct queue_properties * q,struct mqd_update_info * minfo)334 static void update_mqd_hiq(struct mqd_manager *mm, void *mqd,
335 struct queue_properties *q,
336 struct mqd_update_info *minfo)
337 {
338 __update_mqd(mm, mqd, q, minfo, MTYPE_UC, 0);
339 }
340
init_mqd_sdma(struct mqd_manager * mm,void ** mqd,struct kfd_mem_obj * mqd_mem_obj,uint64_t * gart_addr,struct queue_properties * q)341 static void init_mqd_sdma(struct mqd_manager *mm, void **mqd,
342 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr,
343 struct queue_properties *q)
344 {
345 struct vi_sdma_mqd *m;
346
347 m = (struct vi_sdma_mqd *) mqd_mem_obj->cpu_ptr;
348
349 memset(m, 0, sizeof(struct vi_sdma_mqd));
350
351 *mqd = m;
352 if (gart_addr)
353 *gart_addr = mqd_mem_obj->gpu_addr;
354
355 mm->update_mqd(mm, m, q, NULL);
356 }
357
update_mqd_sdma(struct mqd_manager * mm,void * mqd,struct queue_properties * q,struct mqd_update_info * minfo)358 static void update_mqd_sdma(struct mqd_manager *mm, void *mqd,
359 struct queue_properties *q,
360 struct mqd_update_info *minfo)
361 {
362 struct vi_sdma_mqd *m;
363
364 m = get_sdma_mqd(mqd);
365 m->sdmax_rlcx_rb_cntl = order_base_2(q->queue_size / 4)
366 << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT |
367 q->vmid << SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT |
368 1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT |
369 6 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT;
370
371 m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8);
372 m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8);
373 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr);
374 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr);
375 m->sdmax_rlcx_doorbell =
376 q->doorbell_off << SDMA0_RLC0_DOORBELL__OFFSET__SHIFT;
377
378 m->sdmax_rlcx_virtual_addr = q->sdma_vm_addr;
379
380 m->sdma_engine_id = q->sdma_engine_id;
381 m->sdma_queue_id = q->sdma_queue_id;
382
383 q->is_active = QUEUE_IS_ACTIVE(*q);
384 }
385
checkpoint_mqd_sdma(struct mqd_manager * mm,void * mqd,void * mqd_dst,void * ctl_stack_dst)386 static void checkpoint_mqd_sdma(struct mqd_manager *mm,
387 void *mqd,
388 void *mqd_dst,
389 void *ctl_stack_dst)
390 {
391 struct vi_sdma_mqd *m;
392
393 m = get_sdma_mqd(mqd);
394
395 memcpy(mqd_dst, m, sizeof(struct vi_sdma_mqd));
396 }
397
restore_mqd_sdma(struct mqd_manager * mm,void ** mqd,struct kfd_mem_obj * mqd_mem_obj,uint64_t * gart_addr,struct queue_properties * qp,const void * mqd_src,const void * ctl_stack_src,const u32 ctl_stack_size)398 static void restore_mqd_sdma(struct mqd_manager *mm, void **mqd,
399 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr,
400 struct queue_properties *qp,
401 const void *mqd_src,
402 const void *ctl_stack_src, const u32 ctl_stack_size)
403 {
404 uint64_t addr;
405 struct vi_sdma_mqd *m;
406
407 m = (struct vi_sdma_mqd *) mqd_mem_obj->cpu_ptr;
408 addr = mqd_mem_obj->gpu_addr;
409
410 memcpy(m, mqd_src, sizeof(*m));
411
412 m->sdmax_rlcx_doorbell =
413 qp->doorbell_off << SDMA0_RLC0_DOORBELL__OFFSET__SHIFT;
414
415 *mqd = m;
416 if (gart_addr)
417 *gart_addr = addr;
418
419 qp->is_active = 0;
420 }
421
422 #if defined(CONFIG_DEBUG_FS)
423
424
debugfs_show_mqd(struct seq_file * m,void * data)425 static int debugfs_show_mqd(struct seq_file *m, void *data)
426 {
427 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4,
428 data, sizeof(struct vi_mqd), false);
429 return 0;
430 }
431
debugfs_show_mqd_sdma(struct seq_file * m,void * data)432 static int debugfs_show_mqd_sdma(struct seq_file *m, void *data)
433 {
434 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4,
435 data, sizeof(struct vi_sdma_mqd), false);
436 return 0;
437 }
438
439 #endif
440
mqd_manager_init_vi(enum KFD_MQD_TYPE type,struct kfd_node * dev)441 struct mqd_manager *mqd_manager_init_vi(enum KFD_MQD_TYPE type,
442 struct kfd_node *dev)
443 {
444 struct mqd_manager *mqd;
445
446 if (WARN_ON(type >= KFD_MQD_TYPE_MAX))
447 return NULL;
448
449 mqd = kzalloc_obj(*mqd);
450 if (!mqd)
451 return NULL;
452
453 mqd->dev = dev;
454
455 switch (type) {
456 case KFD_MQD_TYPE_CP:
457 mqd->allocate_mqd = allocate_mqd;
458 mqd->init_mqd = init_mqd;
459 mqd->free_mqd = kfd_free_mqd_cp;
460 mqd->load_mqd = load_mqd;
461 mqd->update_mqd = update_mqd;
462 mqd->destroy_mqd = kfd_destroy_mqd_cp;
463 mqd->is_occupied = kfd_is_occupied_cp;
464 mqd->get_wave_state = get_wave_state;
465 mqd->get_checkpoint_info = get_checkpoint_info;
466 mqd->checkpoint_mqd = checkpoint_mqd;
467 mqd->restore_mqd = restore_mqd;
468 mqd->mqd_size = sizeof(struct vi_mqd);
469 #if defined(CONFIG_DEBUG_FS)
470 mqd->debugfs_show_mqd = debugfs_show_mqd;
471 #endif
472 break;
473 case KFD_MQD_TYPE_HIQ:
474 mqd->allocate_mqd = allocate_hiq_mqd;
475 mqd->init_mqd = init_mqd_hiq;
476 mqd->free_mqd = free_mqd_hiq_sdma;
477 mqd->load_mqd = load_mqd;
478 mqd->update_mqd = update_mqd_hiq;
479 mqd->destroy_mqd = kfd_destroy_mqd_cp;
480 mqd->is_occupied = kfd_is_occupied_cp;
481 mqd->mqd_size = sizeof(struct vi_mqd);
482 mqd->mqd_stride = kfd_mqd_stride;
483 #if defined(CONFIG_DEBUG_FS)
484 mqd->debugfs_show_mqd = debugfs_show_mqd;
485 #endif
486 mqd->check_preemption_failed = check_preemption_failed;
487 break;
488 case KFD_MQD_TYPE_DIQ:
489 mqd->allocate_mqd = allocate_mqd;
490 mqd->init_mqd = init_mqd_hiq;
491 mqd->free_mqd = kfd_free_mqd_cp;
492 mqd->load_mqd = load_mqd;
493 mqd->update_mqd = update_mqd_hiq;
494 mqd->destroy_mqd = kfd_destroy_mqd_cp;
495 mqd->is_occupied = kfd_is_occupied_cp;
496 mqd->mqd_size = sizeof(struct vi_mqd);
497 mqd->mqd_stride = kfd_mqd_stride;
498 #if defined(CONFIG_DEBUG_FS)
499 mqd->debugfs_show_mqd = debugfs_show_mqd;
500 #endif
501 break;
502 case KFD_MQD_TYPE_SDMA:
503 mqd->allocate_mqd = allocate_sdma_mqd;
504 mqd->init_mqd = init_mqd_sdma;
505 mqd->free_mqd = free_mqd_hiq_sdma;
506 mqd->load_mqd = kfd_load_mqd_sdma;
507 mqd->update_mqd = update_mqd_sdma;
508 mqd->destroy_mqd = kfd_destroy_mqd_sdma;
509 mqd->is_occupied = kfd_is_occupied_sdma;
510 mqd->checkpoint_mqd = checkpoint_mqd_sdma;
511 mqd->restore_mqd = restore_mqd_sdma;
512 mqd->mqd_size = sizeof(struct vi_sdma_mqd);
513 mqd->mqd_stride = kfd_mqd_stride;
514 #if defined(CONFIG_DEBUG_FS)
515 mqd->debugfs_show_mqd = debugfs_show_mqd_sdma;
516 #endif
517 break;
518 default:
519 kfree(mqd);
520 return NULL;
521 }
522
523 return mqd;
524 }
525