1 /******************************************************************************* 2 *Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. 3 * 4 *Redistribution and use in source and binary forms, with or without modification, are permitted provided 5 *that the following conditions are met: 6 *1. Redistributions of source code must retain the above copyright notice, this list of conditions and the 7 *following disclaimer. 8 *2. Redistributions in binary form must reproduce the above copyright notice, 9 *this list of conditions and the following disclaimer in the documentation and/or other materials provided 10 *with the distribution. 11 * 12 *THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 13 *WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 14 *FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 15 *FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 16 *NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 17 *BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 18 *LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 19 *SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE 20 * 21 * 22 ********************************************************************************/ 23 24 /*******************************************************************************/ 25 /*! \file mpi.h 26 * \brief The file defines the MPI constants and structures 27 * 28 * The file defines the MPI constants and structures 29 * 30 */ 31 /*******************************************************************************/ 32 33 #ifndef __MPI_H__ 34 #define __MPI_H__ 35 36 /*******************************************************************************/ 37 38 /*******************************************************************************/ 39 /* CONSTANTS */ 40 /*******************************************************************************/ 41 /*******************************************************************************/ 42 #define MPI_QUEUE_PRIORITY_HIGHEST 0xFF /**< Highest queue priority */ 43 #define MPI_QUEUE_PRIORITY_LOWEST 0x00 /**< Lowest queue priority */ 44 45 #define MPI_MAX_INBOUND_QUEUES 64 /**< Maximum number of inbound queues */ 46 #define MPI_MAX_OUTBOUND_QUEUES 64 /**< Maximum number of outbound queues */ 47 48 /**< Max # of memory chunks supported */ 49 #define MPI_MAX_MEM_REGIONS (MPI_MAX_INBOUND_QUEUES + MPI_MAX_OUTBOUND_QUEUES) + 4 50 #define MPI_LOGSIZE 4096 /**< default size */ 51 52 #define MPI_IB_NUM_MASK 0x0000FFFF /**< Mask of Inbound Queue Number */ 53 #define MPI_OB_NUM_MASK 0xFFFF0000 /**< Mask of Outbound Queue Number */ 54 #define MPI_OB_SHIFT 16 /**< bits shift for outbound queue number */ 55 56 57 #define BAR0 0x10 58 #define BAR1 0x14 59 #define BAR2 0x18 60 #define BAR3 0x1C 61 #define BAR4 0x20 62 #define BAR5 0x24 63 64 /*******************************************************************************/ 65 /*******************************************************************************/ 66 /* ENUMERATIONS */ 67 /*******************************************************************************/ 68 69 /*******************************************************************************/ 70 /*******************************************************************************/ 71 /** \enum mpiMsgCategory_e, 72 * \brief MPI message categories 73 */ 74 /*******************************************************************************/ 75 enum mpiMsgCategory_e 76 { 77 MPI_CATEGORY_ETHERNET = 0, 78 MPI_CATEGORY_FC, 79 MPI_CATEGORY_SAS_SATA, 80 MPI_CATEGORY_SCSI 81 }; 82 83 typedef enum mpiMsgCategory_e mpiMsgCategory_t; 84 85 /*******************************************************************************/ 86 /*******************************************************************************/ 87 /* TYPES */ 88 /*******************************************************************************/ 89 /*******************************************************************************/ 90 91 92 /*******************************************************************************/ 93 /*******************************************************************************/ 94 /* DATA STRUCTURES */ 95 /*******************************************************************************/ 96 /*******************************************************************************/ 97 98 /*******************************************************************************/ 99 /** \struct mpiMem_s 100 * \brief Structure that descibes memory regions 101 * 102 * The mpiMemoryDescriptor_t is used to describe the attributes for a memory 103 * region. Each element in the memory chunk has to be physically contiguous. 104 * Different elements in the memory chunk do not necessarily have to be 105 * contiguous to each other. 106 */ 107 /*******************************************************************************/ 108 struct mpiMem_s 109 { 110 void* virtPtr; /**< Virtual pointer to the memory region */ 111 void* appHandle; /**< Handle used for the application to free memory */ 112 bit32 physAddrUpper; /**< Upper 32 bits of physical address */ 113 bit32 physAddrLower; /**< Lower 32 bits of physical address */ 114 bit32 totalLength; /**< Total length in bytes allocated */ 115 bit32 numElements; /**< Number of elements */ 116 bit32 elementSize; /**< Size in bytes of an element */ 117 bit32 alignment; /**< Alignment in bytes needed. A value of one indicates */ 118 /**< no specific alignment requirement */ 119 bit32 type; /**< Memory type */ 120 bit32 reserved; /**< Reserved */ 121 }; 122 123 typedef struct mpiMem_s mpiMem_t; 124 125 /*******************************************************************************/ 126 /** \struct mpiMemReq_s 127 * \brief Describes MPI memory requirements 128 * 129 * The mpiMemRequirements_t is used to specify the memory allocation requirement 130 * for the MPI. This is the data structure used in the mpiGetRequirements() 131 * and the mpiInitialize() function calls 132 */ 133 /*******************************************************************************/ 134 struct mpiMemReq_s 135 { 136 bit32 count; /**< The number of element in the mpiMemory array */ 137 mpiMem_t region[MPI_MAX_MEM_REGIONS]; /**< Pointer to the array of structures that define memroy regions */ 138 }; 139 140 typedef struct mpiMemReq_s mpiMemReq_t; 141 142 /*******************************************************************************/ 143 /** \struct mpiQCQueue_s 144 * \brief Circular Queue descriptor 145 * 146 * This structure holds outbound circular queue attributes. 147 */ 148 /*******************************************************************************/ 149 struct mpiOCQueue_s 150 { 151 bit32 qNumber; /**< this queue number */ 152 bit32 numElements; /**< The total number of queue elements. A value 0 disables the queue */ 153 bit32 elementSize; /**< The size of each queue element, in bytes */ 154 bit32 priority; /**< The queue priority. Possible values for this field are */ 155 /**< MPI_QUEUE_PRIORITY_HIGHEST and MPI_QUEUE_PRIORITY_LOWEST */ 156 bit32 CIPCIBar; /**< PCI Bar */ 157 bit32 CIPCIOffset; /**< PCI Offset */ 158 bit32 DIntTOffset; /**< Dynamic Interrupt Coalescing Timeout offset */ 159 void* piPointer; /**< pointer of PI (virtual address)*/ 160 mpiMem_t memoryRegion; /**< Queue's memory region descriptor */ 161 bit32 producerIdx; /**< Copy of the producer index */ 162 bit32 consumerIdx; /**< Copy of the consumer index */ 163 bit32 pcibar; /**< CPI Logical Bar Number */ 164 agsaRoot_t *agRoot; /**< Pointer of LL Layer structure */ 165 }; 166 167 typedef struct mpiOCQueue_s mpiOCQueue_t; 168 169 /*******************************************************************************/ 170 /** \struct mpiICQueue_s 171 * \brief Circular Queue descriptor 172 * 173 * This structure holds inbound circular queue attributes. 174 */ 175 /*******************************************************************************/ 176 struct mpiICQueue_s 177 { 178 bit32 qNumber; /**< this queue number */ 179 bit32 numElements; /**< The total number of queue elements. A value 0 disables the queue */ 180 bit32 elementSize; /**< The size of each queue element, in bytes */ 181 bit32 priority; /**< The queue priority. Possible values for this field are */ 182 /**< MPI_QUEUE_PRIORITY_HIGHEST and MPI_QUEUE_PRIORITY_LOWEST */ 183 bit32 PIPCIBar; /**< PCI Bar */ 184 bit32 PIPCIOffset; /**< PCI Offset */ 185 void* ciPointer; /**< Pointer of CI (virtual Address) */ 186 mpiMem_t memoryRegion; /**< Queue's memory region descriptor */ 187 bit32 producerIdx; /**< Copy of the producer index */ 188 bit32 consumerIdx; /**< Copy of the consumer index */ 189 #ifdef SA_FW_TEST_BUNCH_STARTS 190 bit32 BunchStarts_QPending; // un-started bunched IOs on queue 191 bit32 BunchStarts_QPendingTick; // tick value when 1st IO is bunched 192 #endif /* SA_FW_TEST_BUNCH_STARTS */ 193 agsaRoot_t *agRoot; /**< Pointer of LL Layer structure */ 194 }; 195 196 typedef struct mpiICQueue_s mpiICQueue_t; 197 198 struct mpiHostLLConfigDescriptor_s 199 { 200 bit32 regDumpPCIBAR; 201 bit32 iQNPPD_HPPD_GEvent; /**< inbound Queue Process depth */ 202 /* bit0-7 inbound normal priority process depth */ 203 /* bit8-15 inbound high priority process depth */ 204 /* bit16-23 OQ number to receive GENERAL_EVENT Notification */ 205 /* bit24-31 reserved */ 206 bit32 outboundHWEventPID0_3; /**< outbound HW event for PortId 0 to 3 */ 207 /* bit0-7 outbound queue number of SAS_HW event for PortId 0 */ 208 /* bit8-15 outbound queue number of SAS_HW event for PortId 1 */ 209 /* bit16-23 outbound queue number of SAS_HW event for PortId 2 */ 210 /* bit24-31 outbound queue number of SAS_HW event for PortId 3 */ 211 bit32 outboundHWEventPID4_7; /**< outbound HW event for PortId 4 to 7 */ 212 /* bit0-7 outbound queue number of SAS_HW event for PortId 4 */ 213 /* bit8-15 outbound queue number of SAS_HW event for PortId 5 */ 214 /* bit16-23 outbound queue number of SAS_HW event for PortId 6 */ 215 /* bit24-31 outbound queue number of SAS_HW event for PortId 7 */ 216 bit32 outboundNCQEventPID0_3; /**< outbound NCQ event for PortId 0 to 3 */ 217 /* bit0-7 outbound queue number of SATA_NCQ event for PortId 0 */ 218 /* bit8-15 outbound queue number of SATA_NCQ event for PortId 1 */ 219 /* bit16-23 outbound queue number of SATA_NCQ event for PortId 2 */ 220 /* bit24-31 outbound queue number of SATA_NCQ event for PortId 3 */ 221 bit32 outboundNCQEventPID4_7; /**< outbound NCQ event for PortId 4 to 7 */ 222 /* bit0-7 outbound queue number of SATA_NCQ event for PortId 4 */ 223 /* bit8-15 outbound queue number of SATA_NCQ event for PortId 5 */ 224 /* bit16-23 outbound queue number of SATA_NCQ event for PortId 6 */ 225 /* bit24-31 outbound queue number of SATA_NCQ event for PortId 7 */ 226 bit32 outboundTargetITNexusEventPID0_3; /**< outbound target ITNexus Event for PortId 0 to 3 */ 227 /* bit0-7 outbound queue number of ITNexus event for PortId 0 */ 228 /* bit8-15 outbound queue number of ITNexus event for PortId 1 */ 229 /* bit16-23 outbound queue number of ITNexus event for PortId 2 */ 230 /* bit24-31 outbound queue number of ITNexus event for PortId 3 */ 231 bit32 outboundTargetITNexusEventPID4_7; /**< outbound target ITNexus Event for PortId 4 to 7 */ 232 /* bit0-7 outbound queue number of ITNexus event for PortId 4 */ 233 /* bit8-15 outbound queue number of ITNexus event for PortId 5 */ 234 /* bit16-23 outbound queue number of ITNexus event for PortId 6 */ 235 /* bit24-31 outbound queue number of ITNexus event for PortId 7 */ 236 bit32 outboundTargetSSPEventPID0_3; /**< outbound target SSP event for PordId 0 to 3 */ 237 /* bit0-7 outbound queue number of SSP event for PortId 0 */ 238 /* bit8-15 outbound queue number of SSP event for PortId 1 */ 239 /* bit16-23 outbound queue number of SSP event for PortId 2 */ 240 /* bit24-31 outbound queue number of SSP event for PortId 3 */ 241 bit32 outboundTargetSSPEventPID4_7; /**< outbound target SSP event for PordId 4 to 7 */ 242 /* bit0-7 outbound queue number of SSP event for PortId 4 */ 243 /* bit8-15 outbound queue number of SSP event for PortId 5 */ 244 /* bit16-23 outbound queue number of SSP event for PortId 6 */ 245 /* bit24-31 outbound queue number of SSP event for PortId 7 */ 246 bit32 ioAbortDelay; /* was reserved */ /**< io Abort delay MPI_TABLE_CHANGE */ 247 bit32 custset; /**< custset */ 248 bit32 upperEventLogAddress; /**< Upper physical MSGU Event log address */ 249 bit32 lowerEventLogAddress; /**< Lower physical MSGU Event log address */ 250 bit32 eventLogSize; /**< Size of MSGU Event log, 0 means log disable */ 251 bit32 eventLogOption; /**< Option of MSGU Event log */ 252 /* bit3-0 log severity, 0x0 Disable Logging */ 253 /* 0x1 Critical Error */ 254 /* 0x2 Minor Error */ 255 /* 0x3 Warning */ 256 /* 0x4 Information */ 257 /* 0x5 Debugging */ 258 /* 0x6 - 0xF Reserved */ 259 bit32 upperIOPeventLogAddress; /**< Upper physical IOP Event log address */ 260 bit32 lowerIOPeventLogAddress; /**< Lower physical IOP Event log address */ 261 bit32 IOPeventLogSize; /**< Size of IOP Event log, 0 means log disable */ 262 bit32 IOPeventLogOption; /**< Option of IOP Event log */ 263 /* bit3-0 log severity, 0x0 Disable Logging */ 264 /* 0x1 Critical Error */ 265 /* 0x2 Minor Error */ 266 /* 0x3 Warning */ 267 /* 0x4 Information */ 268 /* 0x5 Debugging */ 269 /* 0x6 - 0xF Reserved */ 270 bit32 FatalErrorInterrupt; /**< Fatal Error Interrupt enable and vector */ 271 /* bit0 Fatal Error Interrupt Enable */ 272 /* bit1 PI/CI Address */ 273 /* bit5 enable or disable outbound coalesce */ 274 /* bit7-6 reserved */ 275 /* bit15-8 Fatal Error Interrupt Vector */ 276 /* bit31-16 Reserved */ 277 bit32 FatalErrorDumpOffset0; /**< Fatal Error Register Dump Offset for MSGU */ 278 bit32 FatalErrorDumpLength0; /**< Fatal Error Register Dump Length for MSGU */ 279 bit32 FatalErrorDumpOffset1; /**< Fatal Error Register Dump Offset for IOP */ 280 bit32 FatalErrorDumpLength1; /**< Fatal Error Register Dump Length for IOP */ 281 bit32 HDAModeFlags; /**< HDA Mode Flags */ 282 /* bit1-0 Bootstrap pins */ 283 /* bit2 Force HDA Mode bit */ 284 /* bit3 HDA Firmware load method */ 285 bit32 analogSetupTblOffset; /**< Phy Calibration Table offset */ 286 /* bit23-0 phy calib table offset */ 287 /* bit31-24 entry size */ 288 bit32 InterruptVecTblOffset; /**< DW23 Interrupt Vector Table */ 289 /* bit23-0 interrupt vector table offset */ 290 /* bit31-24 entry size */ 291 bit32 phyAttributeTblOffset; /**< DW24 SAS Phy Attribute Table Offset */ 292 /* bit23-0 phy attribute table offset */ 293 /* bit31-24 entry size */ 294 bit32 PortRecoveryTimerPortResetTimer; /**< DW25 Port Recovery Timer and Port Reset Timer */ 295 bit32 InterruptReassertionDelay; /**< DW26 Interrupt Reassertion Delay 0:23 Reserved 24:31 */ 296 }; 297 298 typedef struct mpiHostLLConfigDescriptor_s mpiHostLLConfigDescriptor_t; 299 300 /*******************************************************************************/ 301 /** \struct mpiInboundQueueDescriptor_s 302 * \brief MPI inbound queue attributes 303 * 304 * The mpiInboundQueueDescriptor_t structure is used to describe an inbound queue 305 * attributes 306 */ 307 /*******************************************************************************/ 308 struct mpiInboundQueueDescriptor_s 309 { 310 bit32 numElements; /**< The total number of queue elements. A value 0 disables the queue */ 311 bit32 elementSize; /**< The size of each queue element, in bytes */ 312 bit32 priority; /**< The queue priority. Possible values for this field are */ 313 /**< MPI_QUEUE_PRIORITY_HIGHEST and MPI_QUEUE_PRIORITY_LOWEST */ 314 bit32 PIPCIBar; /**< PI PCIe Bar */ 315 bit32 PIOffset; /**< PI PCI Bar Offset */ 316 void* ciPointer; /**< Pointer of CI (virtual Address) */ 317 }; 318 319 typedef struct mpiInboundQueueDescriptor_s mpiInboundQueueDescriptor_t; 320 321 /*******************************************************************************/ 322 /** \struct mpiOutboundQueueDescriptor_s 323 * \brief MPI outbound queue attributes 324 * 325 * The mpiOutboundQueueDescriptor_t structure is used to describe an outbound queue 326 * attributes 327 */ 328 /*******************************************************************************/ 329 struct mpiOutboundQueueDescriptor_s 330 { 331 bit32 numElements; /**< The total number of queue elements. A value 0 disables the queue */ 332 bit32 elementSize; /**< The size of each queue element, in bytes */ 333 bit32 interruptDelay; /**< Delay in microseconds before the interrupt is asserted */ 334 /**< if the interrupt threshold has not been reached */ 335 bit32 interruptThreshold; /**< Number of interrupt events before the interrupt is asserted */ 336 /**< If set to 0, interrupts for this queue are disablec */ 337 bit32 interruptVector; /**< Interrupt vector assigned to this queue */ 338 bit32 CIPCIBar; /**< offset 0x14:PCI BAR for CI Offset */ 339 bit32 CIOffset; /**< offset 0x18:Offset address for outbound queue CI */ 340 bit32 DIntTOffset; /**< Dynamic Interrupt Coalescing Timeout offset */ 341 bit32 interruptEnable; /**< Interrupt enable flag */ 342 void* piPointer; /**< pointer of PI (virtual address)*/ 343 }; 344 345 typedef struct mpiOutboundQueueDescriptor_s mpiOutboundQueueDescriptor_t; 346 347 /*******************************************************************************/ 348 /** \struct mpiPhyCalibration_s 349 * \brief MPI Phy Calibration Table 350 * 351 * The mpiPhyCalibration_s structure is used to set Phy Calibration 352 * attributes 353 */ 354 /*******************************************************************************/ 355 struct mpiPhyCalibration_s 356 { 357 bit32 spaReg0; /* transmitter per port configuration 1 SAS_SATA G1 */ 358 bit32 spaReg1; /* transmitter per port configuration 2 SAS_SATA G1*/ 359 bit32 spaReg2; /* transmitter per port configuration 3 SAS_SATA G1*/ 360 bit32 spaReg3; /* transmitter configuration 1 */ 361 bit32 spaReg4; /* reveiver per port configuration 1 SAS_SATA G1G2 */ 362 bit32 spaReg5; /* reveiver per port configuration 2 SAS_SATA G3 */ 363 bit32 spaReg6; /* reveiver per configuration 1 */ 364 bit32 spaReg7; /* reveiver per configuration 2 */ 365 bit32 reserved[2]; /* reserved */ 366 }; 367 368 typedef struct mpiPhyCalibration_s mpiPhyCalibration_t; 369 370 #define ANALOG_SETUP_ENTRY_NO 10 371 #define ANALOG_SETUP_ENTRY_SIZE 10 372 373 374 /*******************************************************************************/ 375 /** \struct mpiConfig_s 376 * \brief MPI layer configuration parameters 377 * 378 * The mpiConfig_s structure is used as a parameter passed in 379 * mpiGetRequirements() and mpiInitialize() to describe the MPI software 380 * configuration 381 */ 382 /*******************************************************************************/ 383 struct mpiVConfig_s 384 { 385 mpiHostLLConfigDescriptor_t mainConfig; /**< main part of configuration table */ 386 mpiInboundQueueDescriptor_t inboundQueues[MPI_MAX_INBOUND_QUEUES]; /**< mpiQueueDescriptor structures that provide initialization */ 387 /**< attributes for the inbound queues. The maximum number of */ 388 /**< inbound queues is MPI_MAX_INBOUND_QUEUES */ 389 mpiOutboundQueueDescriptor_t outboundQueues[MPI_MAX_OUTBOUND_QUEUES]; /**< mpiQueueDescriptor structures that provide initialization */ 390 /**< attributes for the outbound queues. The maximum number of */ 391 /**< inbound queues is MPI_MAX_OUTBOUND_QUEUES */ 392 agsaPhyAnalogSetupTable_t phyAnalogConfig; 393 mpiInterruptVT_t interruptVTable; 394 sasPhyAttribute_t phyAttributeTable; 395 bit16 numInboundQueues; 396 bit16 numOutboundQueues; 397 bit16 maxNumInboundQueues; 398 bit16 maxNumOutboundQueues; 399 bit32 queueOption; 400 }; 401 402 /*******************************************************************************/ 403 /** \struct mpiConfig_s 404 * \brief MPI layer configuration parameters 405 * 406 * The mpiConfig_s structure is used as a parameter passed in 407 * mpiGetRequirements() and mpiInitialize() to describe the MPI software 408 * configuration 409 */ 410 /*******************************************************************************/ 411 struct mpiConfig_s 412 { 413 mpiHostLLConfigDescriptor_t mainConfig; /**< main part of configuration table */ 414 mpiInboundQueueDescriptor_t inboundQueues[MPI_MAX_INBOUND_QUEUES]; /**< mpiQueueDescriptor structures that provide initialization */ 415 /**< attributes for the inbound queues. The maximum number of */ 416 /**< inbound queues is MPI_MAX_INBOUND_QUEUES */ 417 mpiOutboundQueueDescriptor_t outboundQueues[MPI_MAX_OUTBOUND_QUEUES]; /**< mpiQueueDescriptor structures that provide initialization */ 418 /**< attributes for the outbound queues. The maximum number of */ 419 /**< inbound queues is MPI_MAX_OUTBOUND_QUEUES */ 420 agsaPhyAnalogSetupTable_t phyAnalogConfig; 421 bit16 numInboundQueues; 422 bit16 numOutboundQueues; 423 bit16 maxNumInboundQueues; 424 bit16 maxNumOutboundQueues; 425 bit32 queueOption; 426 }; 427 428 typedef struct mpiConfig_s mpiConfig_t; 429 430 #define TX_PORT_CFG1_OFFSET 0x00 431 #define TX_PORT_CFG2_OFFSET 0x04 432 #define TX_PORT_CFG3_OFFSET 0x08 433 #define TX_CFG_OFFSET 0x0c 434 #define RV_PORT_CFG1_OFFSET 0x10 435 #define RV_PORT_CFG2_OFFSET 0x14 436 #define RV_CFG1_OFFSET 0x18 437 #define RV_CFG2_OFFSET 0x1c 438 439 /*******************************************************************************/ 440 /*******************************************************************************/ 441 /* FUNCTIONS */ 442 /*******************************************************************************/ 443 /*******************************************************************************/ 444 /*******************************************************************************/ 445 void mpiRequirementsGet(mpiConfig_t *config, mpiMemReq_t *memoryRequirement); 446 FORCEINLINE bit32 mpiMsgFreeGet(mpiICQueue_t *circularQ, bit16 messageSize, void** messagePtr); 447 FORCEINLINE bit32 mpiMsgProduce(mpiICQueue_t *circularQ, void* messagePtr, 448 mpiMsgCategory_t category, bit16 opCode, 449 bit8 responseQueue, bit8 hiPriority); 450 #ifdef LOOPBACK_MPI 451 GLOBAL bit32 mpiMsgProduceOQ(mpiOCQueue_t *circularQ, void *messagePtr, 452 mpiMsgCategory_t category, bit16 opCode, 453 bit8 responseQueue, bit8 hiPriority); 454 GLOBAL bit32 mpiMsgFreeGetOQ(mpiOCQueue_t *circularQ, bit16 messageSize, 455 void** messagePtr); 456 #endif 457 458 #ifdef FAST_IO_TEST 459 bit32 mpiMsgPrepare(mpiICQueue_t *circularQ, void* messagePtr, 460 mpiMsgCategory_t category, bit16 opCode, 461 bit8 responseQueue, bit8 hiPriority); 462 463 bit32 mpiMsgProduceSend(mpiICQueue_t *circularQ, void* messagePtr, 464 mpiMsgCategory_t category, bit16 opCode, 465 bit8 responseQueue, bit8 hiPriority, int sendFl); 466 GLOBAL void mpiIBQMsgSend(mpiICQueue_t *circularQ); 467 #define INQ(queueNum) (bit8)(queueNum & MPI_IB_NUM_MASK) 468 #define OUQ(queueNum) (bit8)((queueNum & MPI_OB_NUM_MASK) >> MPI_OB_SHIFT) 469 #endif 470 471 FORCEINLINE bit32 mpiMsgConsume(mpiOCQueue_t *circularQ, void** messagePtr1, mpiMsgCategory_t *pCategory, bit16* pOpCode, bit8 *pBC); 472 FORCEINLINE bit32 mpiMsgFreeSet(mpiOCQueue_t *circularQ, void* messagePtr1, bit8 bc); 473 474 #endif /* __MPI_H__ */ 475 476