1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2018 Justin Hibbits
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include <sys/param.h>
30 #include <sys/bus.h>
31 #include <sys/kernel.h>
32 #include <sys/module.h>
33
34 #include <machine/bus.h>
35
36 #include <dev/ofw/ofw_bus.h>
37 #include <dev/ofw/ofw_bus_subr.h>
38
39 /*
40 * From the P1022 manual, sequence for writing to L2CTL is:
41 * - mbar
42 * - isync
43 * - write
44 * - read
45 * - mbar
46 */
47 #define L2_CTL 0x0
48 #define L2CTL_L2E 0x80000000
49 #define L2CTL_L2I 0x40000000
50 struct mpc85xx_cache_softc {
51 struct resource *sc_mem;
52 };
53
54 static struct ofw_compat_data compats[] = {
55 {"fsl,8540-l2-cache-controller", 1},
56 {"fsl,8541-l2-cache-controller", 1},
57 {"fsl,8544-l2-cache-controller", 1},
58 {"fsl,8548-l2-cache-controller", 1},
59 {"fsl,8555-l2-cache-controller", 1},
60 {"fsl,8568-l2-cache-controller", 1},
61 {"fsl,b4420-l2-cache-controller", 1},
62 {"fsl,b4860-l2-cache-controller", 1},
63 {"fsl,bsc9131-l2-cache-controller", 1},
64 {"fsl,bsc9132-l2-cache-controller", 1},
65 {"fsl,c293-l2-cache-controller", 1},
66 {"fsl,mpc8536-l2-cache-controller", 1},
67 {"fsl,mpc8540-l2-cache-controller", 1},
68 {"fsl,mpc8541-l2-cache-controller", 1},
69 {"fsl,mpc8544-l2-cache-controller", 1},
70 {"fsl,mpc8548-l2-cache-controller", 1},
71 {"fsl,mpc8555-l2-cache-controller", 1},
72 {"fsl,mpc8560-l2-cache-controller", 1},
73 {"fsl,mpc8568-l2-cache-controller", 1},
74 {"fsl,mpc8569-l2-cache-controller", 1},
75 {"fsl,mpc8572-l2-cache-controller", 1},
76 {"fsl,p1010-l2-cache-controller", 1},
77 {"fsl,p1011-l2-cache-controller", 1},
78 {"fsl,p1012-l2-cache-controller", 1},
79 {"fsl,p1013-l2-cache-controller", 1},
80 {"fsl,p1014-l2-cache-controller", 1},
81 {"fsl,p1015-l2-cache-controller", 1},
82 {"fsl,p1016-l2-cache-controller", 1},
83 {"fsl,p1020-l2-cache-controller", 1},
84 {"fsl,p1021-l2-cache-controller", 1},
85 {"fsl,p1022-l2-cache-controller", 1},
86 {"fsl,p1023-l2-cache-controller", 1},
87 {"fsl,p1024-l2-cache-controller", 1},
88 {"fsl,p1025-l2-cache-controller", 1},
89 {"fsl,p2010-l2-cache-controller", 1},
90 {"fsl,p2020-l2-cache-controller", 1},
91 {"fsl,t2080-l2-cache-controller", 1},
92 {"fsl,t4240-l2-cache-controller", 1},
93 {0, 0}
94 };
95
96 static int
mpc85xx_cache_probe(device_t dev)97 mpc85xx_cache_probe(device_t dev)
98 {
99
100 if (ofw_bus_search_compatible(dev, compats)->ocd_str == NULL)
101 return (ENXIO);
102
103 device_set_desc(dev, "MPC85xx L2 cache");
104 return (0);
105 }
106
107 static int
mpc85xx_cache_attach(device_t dev)108 mpc85xx_cache_attach(device_t dev)
109 {
110 struct mpc85xx_cache_softc *sc = device_get_softc(dev);
111 int rid;
112 int cache_line_size, cache_size;
113
114 /* Map registers. */
115 rid = 0;
116 sc->sc_mem = bus_alloc_resource_any(dev,
117 SYS_RES_MEMORY, &rid, RF_ACTIVE);
118 if (sc->sc_mem == NULL)
119 return (ENOMEM);
120
121 /* Enable cache and flash invalidate. */
122 __asm __volatile ("mbar; isync" ::: "memory");
123 bus_write_4(sc->sc_mem, L2_CTL, L2CTL_L2E | L2CTL_L2I);
124 bus_read_4(sc->sc_mem, L2_CTL);
125 __asm __volatile ("mbar" ::: "memory");
126
127 cache_line_size = 0;
128 cache_size = 0;
129 OF_getencprop(ofw_bus_get_node(dev), "cache-size", &cache_size,
130 sizeof(cache_size));
131 OF_getencprop(ofw_bus_get_node(dev), "cache-line-size",
132 &cache_line_size, sizeof(cache_line_size));
133
134 if (cache_line_size != 0 && cache_size != 0)
135 device_printf(dev,
136 "L2 cache size: %dKB, cache line size: %d bytes\n",
137 cache_size / 1024, cache_line_size);
138
139 return (0);
140 }
141
142 static device_method_t mpc85xx_cache_methods[] = {
143 /* device methods */
144 DEVMETHOD(device_probe, mpc85xx_cache_probe),
145 DEVMETHOD(device_attach, mpc85xx_cache_attach),
146
147 DEVMETHOD_END
148 };
149
150 static driver_t mpc85xx_cache_driver = {
151 "cache",
152 mpc85xx_cache_methods,
153 sizeof(struct mpc85xx_cache_softc),
154 };
155
156 EARLY_DRIVER_MODULE(mpc85xx_cache, simplebus, mpc85xx_cache_driver, NULL, NULL,
157 BUS_PASS_RESOURCE + BUS_PASS_ORDER_MIDDLE);
158