1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * GPIOs on MPC512x/8349/8572/8610/QorIQ and compatible
4 *
5 * Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk>
6 * Copyright (C) 2016 Freescale Semiconductor Inc.
7 */
8
9 #include <linux/acpi.h>
10 #include <linux/bitops.h>
11 #include <linux/gpio/driver.h>
12 #include <linux/init.h>
13 #include <linux/interrupt.h>
14 #include <linux/io.h>
15 #include <linux/irq.h>
16 #include <linux/kernel.h>
17 #include <linux/mod_devicetable.h>
18 #include <linux/of.h>
19 #include <linux/platform_device.h>
20 #include <linux/pm.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/property.h>
23 #include <linux/slab.h>
24 #include <linux/spinlock.h>
25
26 #define MPC8XXX_GPIO_PINS 32
27
28 #define GPIO_DIR 0x00
29 #define GPIO_ODR 0x04
30 #define GPIO_DAT 0x08
31 #define GPIO_IER 0x0c
32 #define GPIO_IMR 0x10
33 #define GPIO_ICR 0x14
34 #define GPIO_ICR2 0x18
35 #define GPIO_IBE 0x18
36
37 struct mpc8xxx_gpio_chip {
38 struct gpio_chip gc;
39 void __iomem *regs;
40 raw_spinlock_t lock;
41
42 int (*direction_output)(struct gpio_chip *chip,
43 unsigned offset, int value);
44
45 struct irq_domain *irq;
46 int irqn;
47 };
48
49 /*
50 * This hardware has a big endian bit assignment such that GPIO line 0 is
51 * connected to bit 31, line 1 to bit 30 ... line 31 to bit 0.
52 * This inline helper give the right bitmask for a certain line.
53 */
mpc_pin2mask(unsigned int offset)54 static inline u32 mpc_pin2mask(unsigned int offset)
55 {
56 return BIT(31 - offset);
57 }
58
59 /* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs
60 * defined as output cannot be determined by reading GPDAT register,
61 * so we use shadow data register instead. The status of input pins
62 * is determined by reading GPDAT register.
63 */
mpc8572_gpio_get(struct gpio_chip * gc,unsigned int gpio)64 static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio)
65 {
66 u32 val;
67 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
68 u32 out_mask, out_shadow;
69
70 out_mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_DIR);
71 val = gc->read_reg(mpc8xxx_gc->regs + GPIO_DAT) & ~out_mask;
72 out_shadow = gc->bgpio_data & out_mask;
73
74 return !!((val | out_shadow) & mpc_pin2mask(gpio));
75 }
76
mpc5121_gpio_dir_out(struct gpio_chip * gc,unsigned int gpio,int val)77 static int mpc5121_gpio_dir_out(struct gpio_chip *gc,
78 unsigned int gpio, int val)
79 {
80 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
81 /* GPIO 28..31 are input only on MPC5121 */
82 if (gpio >= 28)
83 return -EINVAL;
84
85 return mpc8xxx_gc->direction_output(gc, gpio, val);
86 }
87
mpc5125_gpio_dir_out(struct gpio_chip * gc,unsigned int gpio,int val)88 static int mpc5125_gpio_dir_out(struct gpio_chip *gc,
89 unsigned int gpio, int val)
90 {
91 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
92 /* GPIO 0..3 are input only on MPC5125 */
93 if (gpio <= 3)
94 return -EINVAL;
95
96 return mpc8xxx_gc->direction_output(gc, gpio, val);
97 }
98
mpc8xxx_gpio_to_irq(struct gpio_chip * gc,unsigned offset)99 static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
100 {
101 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
102
103 if (mpc8xxx_gc->irq && offset < MPC8XXX_GPIO_PINS)
104 return irq_create_mapping(mpc8xxx_gc->irq, offset);
105 else
106 return -ENXIO;
107 }
108
mpc8xxx_gpio_irq_cascade(int irq,void * data)109 static irqreturn_t mpc8xxx_gpio_irq_cascade(int irq, void *data)
110 {
111 struct mpc8xxx_gpio_chip *mpc8xxx_gc = data;
112 struct gpio_chip *gc = &mpc8xxx_gc->gc;
113 unsigned long mask;
114 int i;
115
116 mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_IER)
117 & gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR);
118 for_each_set_bit(i, &mask, 32)
119 generic_handle_domain_irq(mpc8xxx_gc->irq, 31 - i);
120
121 return IRQ_HANDLED;
122 }
123
mpc8xxx_irq_unmask(struct irq_data * d)124 static void mpc8xxx_irq_unmask(struct irq_data *d)
125 {
126 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
127 struct gpio_chip *gc = &mpc8xxx_gc->gc;
128 unsigned long flags;
129
130 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
131
132 gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR,
133 gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR)
134 | mpc_pin2mask(irqd_to_hwirq(d)));
135
136 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
137 }
138
mpc8xxx_irq_mask(struct irq_data * d)139 static void mpc8xxx_irq_mask(struct irq_data *d)
140 {
141 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
142 struct gpio_chip *gc = &mpc8xxx_gc->gc;
143 unsigned long flags;
144
145 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
146
147 gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR,
148 gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR)
149 & ~mpc_pin2mask(irqd_to_hwirq(d)));
150
151 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
152 }
153
mpc8xxx_irq_ack(struct irq_data * d)154 static void mpc8xxx_irq_ack(struct irq_data *d)
155 {
156 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
157 struct gpio_chip *gc = &mpc8xxx_gc->gc;
158
159 gc->write_reg(mpc8xxx_gc->regs + GPIO_IER,
160 mpc_pin2mask(irqd_to_hwirq(d)));
161 }
162
mpc8xxx_irq_set_type(struct irq_data * d,unsigned int flow_type)163 static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
164 {
165 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
166 struct gpio_chip *gc = &mpc8xxx_gc->gc;
167 unsigned long flags;
168
169 switch (flow_type) {
170 case IRQ_TYPE_EDGE_FALLING:
171 case IRQ_TYPE_LEVEL_LOW:
172 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
173 gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR,
174 gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR)
175 | mpc_pin2mask(irqd_to_hwirq(d)));
176 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
177 break;
178
179 case IRQ_TYPE_EDGE_BOTH:
180 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
181 gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR,
182 gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR)
183 & ~mpc_pin2mask(irqd_to_hwirq(d)));
184 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
185 break;
186
187 default:
188 return -EINVAL;
189 }
190
191 return 0;
192 }
193
mpc512x_irq_set_type(struct irq_data * d,unsigned int flow_type)194 static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type)
195 {
196 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
197 struct gpio_chip *gc = &mpc8xxx_gc->gc;
198 unsigned long gpio = irqd_to_hwirq(d);
199 void __iomem *reg;
200 unsigned int shift;
201 unsigned long flags;
202
203 if (gpio < 16) {
204 reg = mpc8xxx_gc->regs + GPIO_ICR;
205 shift = (15 - gpio) * 2;
206 } else {
207 reg = mpc8xxx_gc->regs + GPIO_ICR2;
208 shift = (15 - (gpio % 16)) * 2;
209 }
210
211 switch (flow_type) {
212 case IRQ_TYPE_EDGE_FALLING:
213 case IRQ_TYPE_LEVEL_LOW:
214 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
215 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift))
216 | (2 << shift));
217 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
218 break;
219
220 case IRQ_TYPE_EDGE_RISING:
221 case IRQ_TYPE_LEVEL_HIGH:
222 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
223 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift))
224 | (1 << shift));
225 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
226 break;
227
228 case IRQ_TYPE_EDGE_BOTH:
229 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
230 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift)));
231 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
232 break;
233
234 default:
235 return -EINVAL;
236 }
237
238 return 0;
239 }
240
241 static struct irq_chip mpc8xxx_irq_chip = {
242 .name = "mpc8xxx-gpio",
243 .irq_unmask = mpc8xxx_irq_unmask,
244 .irq_mask = mpc8xxx_irq_mask,
245 .irq_ack = mpc8xxx_irq_ack,
246 /* this might get overwritten in mpc8xxx_probe() */
247 .irq_set_type = mpc8xxx_irq_set_type,
248 };
249
mpc8xxx_gpio_irq_map(struct irq_domain * h,unsigned int irq,irq_hw_number_t hwirq)250 static int mpc8xxx_gpio_irq_map(struct irq_domain *h, unsigned int irq,
251 irq_hw_number_t hwirq)
252 {
253 irq_set_chip_data(irq, h->host_data);
254 irq_set_chip_and_handler(irq, &mpc8xxx_irq_chip, handle_edge_irq);
255
256 return 0;
257 }
258
259 static const struct irq_domain_ops mpc8xxx_gpio_irq_ops = {
260 .map = mpc8xxx_gpio_irq_map,
261 .xlate = irq_domain_xlate_twocell,
262 };
263
264 struct mpc8xxx_gpio_devtype {
265 int (*gpio_dir_out)(struct gpio_chip *, unsigned int, int);
266 int (*gpio_get)(struct gpio_chip *, unsigned int);
267 int (*irq_set_type)(struct irq_data *, unsigned int);
268 };
269
270 static const struct mpc8xxx_gpio_devtype mpc512x_gpio_devtype = {
271 .gpio_dir_out = mpc5121_gpio_dir_out,
272 .irq_set_type = mpc512x_irq_set_type,
273 };
274
275 static const struct mpc8xxx_gpio_devtype mpc5125_gpio_devtype = {
276 .gpio_dir_out = mpc5125_gpio_dir_out,
277 .irq_set_type = mpc512x_irq_set_type,
278 };
279
280 static const struct mpc8xxx_gpio_devtype mpc8572_gpio_devtype = {
281 .gpio_get = mpc8572_gpio_get,
282 };
283
284 static const struct mpc8xxx_gpio_devtype mpc8xxx_gpio_devtype_default = {
285 .irq_set_type = mpc8xxx_irq_set_type,
286 };
287
288 static const struct of_device_id mpc8xxx_gpio_ids[] = {
289 { .compatible = "fsl,mpc8349-gpio", },
290 { .compatible = "fsl,mpc8572-gpio", .data = &mpc8572_gpio_devtype, },
291 { .compatible = "fsl,mpc8610-gpio", },
292 { .compatible = "fsl,mpc5121-gpio", .data = &mpc512x_gpio_devtype, },
293 { .compatible = "fsl,mpc5125-gpio", .data = &mpc5125_gpio_devtype, },
294 { .compatible = "fsl,pq3-gpio", },
295 { .compatible = "fsl,ls1028a-gpio", },
296 { .compatible = "fsl,ls1088a-gpio", },
297 { .compatible = "fsl,qoriq-gpio", },
298 {}
299 };
300
mpc8xxx_probe(struct platform_device * pdev)301 static int mpc8xxx_probe(struct platform_device *pdev)
302 {
303 struct device_node *np = pdev->dev.of_node;
304 struct mpc8xxx_gpio_chip *mpc8xxx_gc;
305 struct gpio_chip *gc;
306 const struct mpc8xxx_gpio_devtype *devtype = NULL;
307 struct fwnode_handle *fwnode;
308 int ret;
309
310 mpc8xxx_gc = devm_kzalloc(&pdev->dev, sizeof(*mpc8xxx_gc), GFP_KERNEL);
311 if (!mpc8xxx_gc)
312 return -ENOMEM;
313
314 platform_set_drvdata(pdev, mpc8xxx_gc);
315
316 raw_spin_lock_init(&mpc8xxx_gc->lock);
317
318 mpc8xxx_gc->regs = devm_platform_ioremap_resource(pdev, 0);
319 if (IS_ERR(mpc8xxx_gc->regs))
320 return PTR_ERR(mpc8xxx_gc->regs);
321
322 gc = &mpc8xxx_gc->gc;
323 gc->parent = &pdev->dev;
324
325 if (device_property_read_bool(&pdev->dev, "little-endian")) {
326 ret = bgpio_init(gc, &pdev->dev, 4,
327 mpc8xxx_gc->regs + GPIO_DAT,
328 NULL, NULL,
329 mpc8xxx_gc->regs + GPIO_DIR, NULL,
330 BGPIOF_BIG_ENDIAN);
331 if (ret)
332 return ret;
333 dev_dbg(&pdev->dev, "GPIO registers are LITTLE endian\n");
334 } else {
335 ret = bgpio_init(gc, &pdev->dev, 4,
336 mpc8xxx_gc->regs + GPIO_DAT,
337 NULL, NULL,
338 mpc8xxx_gc->regs + GPIO_DIR, NULL,
339 BGPIOF_BIG_ENDIAN
340 | BGPIOF_BIG_ENDIAN_BYTE_ORDER);
341 if (ret)
342 return ret;
343 dev_dbg(&pdev->dev, "GPIO registers are BIG endian\n");
344 }
345
346 mpc8xxx_gc->direction_output = gc->direction_output;
347
348 devtype = device_get_match_data(&pdev->dev);
349 if (!devtype)
350 devtype = &mpc8xxx_gpio_devtype_default;
351
352 /*
353 * It's assumed that only a single type of gpio controller is available
354 * on the current machine, so overwriting global data is fine.
355 */
356 if (devtype->irq_set_type)
357 mpc8xxx_irq_chip.irq_set_type = devtype->irq_set_type;
358
359 if (devtype->gpio_dir_out)
360 gc->direction_output = devtype->gpio_dir_out;
361 if (devtype->gpio_get)
362 gc->get = devtype->gpio_get;
363
364 gc->to_irq = mpc8xxx_gpio_to_irq;
365
366 /*
367 * The GPIO Input Buffer Enable register(GPIO_IBE) is used to control
368 * the input enable of each individual GPIO port. When an individual
369 * GPIO port’s direction is set to input (GPIO_GPDIR[DRn=0]), the
370 * associated input enable must be set (GPIOxGPIE[IEn]=1) to propagate
371 * the port value to the GPIO Data Register.
372 */
373 fwnode = dev_fwnode(&pdev->dev);
374 if (of_device_is_compatible(np, "fsl,qoriq-gpio") ||
375 of_device_is_compatible(np, "fsl,ls1028a-gpio") ||
376 of_device_is_compatible(np, "fsl,ls1088a-gpio") ||
377 is_acpi_node(fwnode)) {
378 gc->write_reg(mpc8xxx_gc->regs + GPIO_IBE, 0xffffffff);
379 /* Also, latch state of GPIOs configured as output by bootloader. */
380 gc->bgpio_data = gc->read_reg(mpc8xxx_gc->regs + GPIO_DAT) &
381 gc->read_reg(mpc8xxx_gc->regs + GPIO_DIR);
382 }
383
384 ret = devm_gpiochip_add_data(&pdev->dev, gc, mpc8xxx_gc);
385 if (ret) {
386 dev_err(&pdev->dev,
387 "GPIO chip registration failed with status %d\n", ret);
388 return ret;
389 }
390
391 mpc8xxx_gc->irqn = platform_get_irq(pdev, 0);
392 if (mpc8xxx_gc->irqn < 0)
393 return mpc8xxx_gc->irqn;
394
395 mpc8xxx_gc->irq = irq_domain_create_linear(fwnode,
396 MPC8XXX_GPIO_PINS,
397 &mpc8xxx_gpio_irq_ops,
398 mpc8xxx_gc);
399
400 if (!mpc8xxx_gc->irq)
401 return 0;
402
403 /* ack and mask all irqs */
404 gc->write_reg(mpc8xxx_gc->regs + GPIO_IER, 0xffffffff);
405 gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, 0);
406
407 ret = devm_request_irq(&pdev->dev, mpc8xxx_gc->irqn,
408 mpc8xxx_gpio_irq_cascade,
409 IRQF_NO_THREAD | IRQF_SHARED, "gpio-cascade",
410 mpc8xxx_gc);
411 if (ret) {
412 dev_err(&pdev->dev,
413 "failed to devm_request_irq(%d), ret = %d\n",
414 mpc8xxx_gc->irqn, ret);
415 goto err;
416 }
417
418 device_init_wakeup(&pdev->dev, true);
419
420 return 0;
421 err:
422 irq_domain_remove(mpc8xxx_gc->irq);
423 return ret;
424 }
425
mpc8xxx_remove(struct platform_device * pdev)426 static void mpc8xxx_remove(struct platform_device *pdev)
427 {
428 struct mpc8xxx_gpio_chip *mpc8xxx_gc = platform_get_drvdata(pdev);
429
430 if (mpc8xxx_gc->irq) {
431 irq_set_chained_handler_and_data(mpc8xxx_gc->irqn, NULL, NULL);
432 irq_domain_remove(mpc8xxx_gc->irq);
433 }
434 }
435
mpc8xxx_suspend(struct device * dev)436 static int mpc8xxx_suspend(struct device *dev)
437 {
438 struct mpc8xxx_gpio_chip *mpc8xxx_gc = dev_get_drvdata(dev);
439
440 if (mpc8xxx_gc->irqn && device_may_wakeup(dev))
441 enable_irq_wake(mpc8xxx_gc->irqn);
442
443 return 0;
444 }
445
mpc8xxx_resume(struct device * dev)446 static int mpc8xxx_resume(struct device *dev)
447 {
448 struct mpc8xxx_gpio_chip *mpc8xxx_gc = dev_get_drvdata(dev);
449
450 if (mpc8xxx_gc->irqn && device_may_wakeup(dev))
451 disable_irq_wake(mpc8xxx_gc->irqn);
452
453 return 0;
454 }
455
456 static DEFINE_RUNTIME_DEV_PM_OPS(mpc8xx_pm_ops,
457 mpc8xxx_suspend, mpc8xxx_resume, NULL);
458
459 #ifdef CONFIG_ACPI
460 static const struct acpi_device_id gpio_acpi_ids[] = {
461 {"NXP0031",},
462 { }
463 };
464 MODULE_DEVICE_TABLE(acpi, gpio_acpi_ids);
465 #endif
466
467 static struct platform_driver mpc8xxx_plat_driver = {
468 .probe = mpc8xxx_probe,
469 .remove_new = mpc8xxx_remove,
470 .driver = {
471 .name = "gpio-mpc8xxx",
472 .of_match_table = mpc8xxx_gpio_ids,
473 .acpi_match_table = ACPI_PTR(gpio_acpi_ids),
474 .pm = pm_ptr(&mpc8xx_pm_ops),
475 },
476 };
477
mpc8xxx_init(void)478 static int __init mpc8xxx_init(void)
479 {
480 return platform_driver_register(&mpc8xxx_plat_driver);
481 }
482
483 arch_initcall(mpc8xxx_init);
484