1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2008-2015 Nathan Whitehorn
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 /*
31 * Manages physical address maps.
32 *
33 * Since the information managed by this module is also stored by the
34 * logical address mapping module, this module may throw away valid virtual
35 * to physical mappings at almost any time. However, invalidations of
36 * mappings must be done as requested.
37 *
38 * In order to cope with hardware architectures which make virtual to
39 * physical map invalidates expensive, this module may delay invalidate
40 * reduced protection operations until such time as they are actually
41 * necessary. This module is given full information as to which processors
42 * are currently using which maps, and to when physical maps must be made
43 * correct.
44 */
45
46 #include "opt_kstack_pages.h"
47
48 #include <sys/param.h>
49 #include <sys/kernel.h>
50 #include <sys/conf.h>
51 #include <sys/queue.h>
52 #include <sys/cpuset.h>
53 #include <sys/kerneldump.h>
54 #include <sys/ktr.h>
55 #include <sys/lock.h>
56 #include <sys/msgbuf.h>
57 #include <sys/malloc.h>
58 #include <sys/mman.h>
59 #include <sys/mutex.h>
60 #include <sys/proc.h>
61 #include <sys/rwlock.h>
62 #include <sys/sched.h>
63 #include <sys/sysctl.h>
64 #include <sys/systm.h>
65 #include <sys/vmmeter.h>
66 #include <sys/smp.h>
67 #include <sys/reboot.h>
68
69 #include <sys/kdb.h>
70
71 #include <dev/ofw/openfirm.h>
72
73 #include <vm/vm.h>
74 #include <vm/pmap.h>
75 #include <vm/vm_param.h>
76 #include <vm/vm_kern.h>
77 #include <vm/vm_page.h>
78 #include <vm/vm_phys.h>
79 #include <vm/vm_map.h>
80 #include <vm/vm_object.h>
81 #include <vm/vm_extern.h>
82 #include <vm/vm_pageout.h>
83 #include <vm/vm_dumpset.h>
84 #include <vm/vm_radix.h>
85 #include <vm/vm_reserv.h>
86 #include <vm/uma.h>
87
88 #include <machine/_inttypes.h>
89 #include <machine/cpu.h>
90 #include <machine/ifunc.h>
91 #include <machine/platform.h>
92 #include <machine/frame.h>
93 #include <machine/md_var.h>
94 #include <machine/psl.h>
95 #include <machine/bat.h>
96 #include <machine/hid.h>
97 #include <machine/pte.h>
98 #include <machine/sr.h>
99 #include <machine/trap.h>
100 #include <machine/mmuvar.h>
101
102 #include "mmu_oea64.h"
103
104 void moea64_release_vsid(uint64_t vsid);
105 uintptr_t moea64_get_unique_vsid(void);
106
107 #define DISABLE_TRANS(msr) msr = mfmsr(); mtmsr(msr & ~PSL_DR)
108 #define ENABLE_TRANS(msr) mtmsr(msr)
109
110 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4))
111 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff)
112 #define VSID_HASH_MASK 0x0000007fffffffffULL
113
114 /*
115 * Locking semantics:
116 *
117 * There are two locks of interest: the page locks and the pmap locks, which
118 * protect their individual PVO lists and are locked in that order. The contents
119 * of all PVO entries are protected by the locks of their respective pmaps.
120 * The pmap of any PVO is guaranteed not to change so long as the PVO is linked
121 * into any list.
122 *
123 */
124
125 #define PV_LOCK_COUNT MAXCPU
126 static struct mtx_padalign pv_lock[PV_LOCK_COUNT];
127
128 #define PV_LOCK_SHIFT 21
129 #define pa_index(pa) ((pa) >> PV_LOCK_SHIFT)
130
131 /*
132 * Cheap NUMA-izing of the pv locks, to reduce contention across domains.
133 * NUMA domains on POWER9 appear to be indexed as sparse memory spaces, with the
134 * index at (N << 45).
135 */
136 #ifdef __powerpc64__
137 #define PV_LOCK_IDX(pa) ((pa_index(pa) * (((pa) >> 45) + 1)) % PV_LOCK_COUNT)
138 #else
139 #define PV_LOCK_IDX(pa) (pa_index(pa) % PV_LOCK_COUNT)
140 #endif
141 #define PV_LOCKPTR(pa) ((struct mtx *)(&pv_lock[PV_LOCK_IDX(pa)]))
142 #define PV_LOCK(pa) mtx_lock(PV_LOCKPTR(pa))
143 #define PV_UNLOCK(pa) mtx_unlock(PV_LOCKPTR(pa))
144 #define PV_LOCKASSERT(pa) mtx_assert(PV_LOCKPTR(pa), MA_OWNED)
145 #define PV_PAGE_LOCK(m) PV_LOCK(VM_PAGE_TO_PHYS(m))
146 #define PV_PAGE_UNLOCK(m) PV_UNLOCK(VM_PAGE_TO_PHYS(m))
147 #define PV_PAGE_LOCKASSERT(m) PV_LOCKASSERT(VM_PAGE_TO_PHYS(m))
148
149 /* Superpage PV lock */
150
151 #define PV_LOCK_SIZE (1 << PV_LOCK_SHIFT)
152
153 static __always_inline void
moea64_sp_pv_lock(vm_paddr_t pa)154 moea64_sp_pv_lock(vm_paddr_t pa)
155 {
156 vm_paddr_t pa_end;
157
158 /* Note: breaking when pa_end is reached to avoid overflows */
159 pa_end = pa + (HPT_SP_SIZE - PV_LOCK_SIZE);
160 for (;;) {
161 mtx_lock_flags(PV_LOCKPTR(pa), MTX_DUPOK);
162 if (pa == pa_end)
163 break;
164 pa += PV_LOCK_SIZE;
165 }
166 }
167
168 static __always_inline void
moea64_sp_pv_unlock(vm_paddr_t pa)169 moea64_sp_pv_unlock(vm_paddr_t pa)
170 {
171 vm_paddr_t pa_end;
172
173 /* Note: breaking when pa_end is reached to avoid overflows */
174 pa_end = pa;
175 pa += HPT_SP_SIZE - PV_LOCK_SIZE;
176 for (;;) {
177 mtx_unlock_flags(PV_LOCKPTR(pa), MTX_DUPOK);
178 if (pa == pa_end)
179 break;
180 pa -= PV_LOCK_SIZE;
181 }
182 }
183
184 #define SP_PV_LOCK_ALIGNED(pa) moea64_sp_pv_lock(pa)
185 #define SP_PV_UNLOCK_ALIGNED(pa) moea64_sp_pv_unlock(pa)
186 #define SP_PV_LOCK(pa) moea64_sp_pv_lock((pa) & ~HPT_SP_MASK)
187 #define SP_PV_UNLOCK(pa) moea64_sp_pv_unlock((pa) & ~HPT_SP_MASK)
188 #define SP_PV_PAGE_LOCK(m) SP_PV_LOCK(VM_PAGE_TO_PHYS(m))
189 #define SP_PV_PAGE_UNLOCK(m) SP_PV_UNLOCK(VM_PAGE_TO_PHYS(m))
190
191 struct ofw_map {
192 cell_t om_va;
193 cell_t om_len;
194 uint64_t om_pa;
195 cell_t om_mode;
196 };
197
198 extern unsigned char _etext[];
199 extern unsigned char _end[];
200
201 extern void *slbtrap, *slbtrapend;
202
203 /*
204 * Map of physical memory regions.
205 */
206 static struct mem_region *regions;
207 static struct mem_region *pregions;
208 static struct numa_mem_region *numa_pregions;
209 static u_int phys_avail_count;
210 static int regions_sz, pregions_sz, numapregions_sz;
211
212 extern void bs_remap_earlyboot(void);
213
214 /*
215 * Lock for the SLB tables.
216 */
217 struct mtx moea64_slb_mutex;
218
219 /*
220 * PTEG data.
221 */
222 u_long moea64_pteg_count;
223 u_long moea64_pteg_mask;
224
225 /*
226 * PVO data.
227 */
228
229 uma_zone_t moea64_pvo_zone; /* zone for pvo entries */
230
231 static struct pvo_entry *moea64_bpvo_pool;
232 static int moea64_bpvo_pool_index = 0;
233 static int moea64_bpvo_pool_size = 0;
234 SYSCTL_INT(_machdep, OID_AUTO, moea64_allocated_bpvo_entries, CTLFLAG_RD,
235 &moea64_bpvo_pool_index, 0, "");
236
237 #define BPVO_POOL_SIZE 327680 /* Sensible historical default value */
238 #define BPVO_POOL_EXPANSION_FACTOR 3
239 #define VSID_NBPW (sizeof(u_int32_t) * 8)
240 #ifdef __powerpc64__
241 #define NVSIDS (NPMAPS * 16)
242 #define VSID_HASHMASK 0xffffffffUL
243 #else
244 #define NVSIDS NPMAPS
245 #define VSID_HASHMASK 0xfffffUL
246 #endif
247 static u_int moea64_vsid_bitmap[NVSIDS / VSID_NBPW];
248
249 static bool moea64_initialized = false;
250
251 #ifdef MOEA64_STATS
252 /*
253 * Statistics.
254 */
255 u_int moea64_pte_valid = 0;
256 u_int moea64_pte_overflow = 0;
257 u_int moea64_pvo_entries = 0;
258 u_int moea64_pvo_enter_calls = 0;
259 u_int moea64_pvo_remove_calls = 0;
260 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_valid, CTLFLAG_RD,
261 &moea64_pte_valid, 0, "");
262 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_overflow, CTLFLAG_RD,
263 &moea64_pte_overflow, 0, "");
264 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_entries, CTLFLAG_RD,
265 &moea64_pvo_entries, 0, "");
266 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_enter_calls, CTLFLAG_RD,
267 &moea64_pvo_enter_calls, 0, "");
268 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_remove_calls, CTLFLAG_RD,
269 &moea64_pvo_remove_calls, 0, "");
270 #endif
271
272 vm_offset_t moea64_scratchpage_va[2];
273 struct pvo_entry *moea64_scratchpage_pvo[2];
274 struct mtx moea64_scratchpage_mtx;
275
276 uint64_t moea64_large_page_mask = 0;
277 uint64_t moea64_large_page_size = 0;
278 int moea64_large_page_shift = 0;
279 bool moea64_has_lp_4k_16m = false;
280
281 /*
282 * PVO calls.
283 */
284 static int moea64_pvo_enter(struct pvo_entry *pvo,
285 struct pvo_head *pvo_head, struct pvo_entry **oldpvo);
286 static void moea64_pvo_remove_from_pmap(struct pvo_entry *pvo);
287 static void moea64_pvo_remove_from_page(struct pvo_entry *pvo);
288 static void moea64_pvo_remove_from_page_locked(
289 struct pvo_entry *pvo, vm_page_t m);
290 static struct pvo_entry *moea64_pvo_find_va(pmap_t, vm_offset_t);
291
292 /*
293 * Utility routines.
294 */
295 static bool moea64_query_bit(vm_page_t, uint64_t);
296 static u_int moea64_clear_bit(vm_page_t, uint64_t);
297 static void moea64_kremove(vm_offset_t);
298 static void moea64_syncicache(pmap_t pmap, vm_offset_t va,
299 vm_paddr_t pa, vm_size_t sz);
300 static void moea64_pmap_init_qpages(void);
301 static void moea64_remove_locked(pmap_t, vm_offset_t,
302 vm_offset_t, struct pvo_dlist *);
303
304 /*
305 * Superpages data and routines.
306 */
307
308 /*
309 * PVO flags (in vaddr) that must match for promotion to succeed.
310 * Note that protection bits are checked separately, as they reside in
311 * another field.
312 */
313 #define PVO_FLAGS_PROMOTE (PVO_WIRED | PVO_MANAGED | PVO_PTEGIDX_VALID)
314
315 #define PVO_IS_SP(pvo) (((pvo)->pvo_vaddr & PVO_LARGE) && \
316 (pvo)->pvo_pmap != kernel_pmap)
317
318 /* Get physical address from PVO. */
319 #define PVO_PADDR(pvo) moea64_pvo_paddr(pvo)
320
321 /* MD page flag indicating that the page is a superpage. */
322 #define MDPG_ATTR_SP 0x40000000
323
324 SYSCTL_DECL(_vm_pmap);
325
326 static SYSCTL_NODE(_vm_pmap, OID_AUTO, sp, CTLFLAG_RD, 0,
327 "SP page mapping counters");
328
329 static u_long sp_demotions;
330 SYSCTL_ULONG(_vm_pmap_sp, OID_AUTO, demotions, CTLFLAG_RD,
331 &sp_demotions, 0, "SP page demotions");
332
333 static u_long sp_mappings;
334 SYSCTL_ULONG(_vm_pmap_sp, OID_AUTO, mappings, CTLFLAG_RD,
335 &sp_mappings, 0, "SP page mappings");
336
337 static u_long sp_p_failures;
338 SYSCTL_ULONG(_vm_pmap_sp, OID_AUTO, p_failures, CTLFLAG_RD,
339 &sp_p_failures, 0, "SP page promotion failures");
340
341 static u_long sp_p_fail_pa;
342 SYSCTL_ULONG(_vm_pmap_sp, OID_AUTO, p_fail_pa, CTLFLAG_RD,
343 &sp_p_fail_pa, 0, "SP page promotion failure: PAs don't match");
344
345 static u_long sp_p_fail_flags;
346 SYSCTL_ULONG(_vm_pmap_sp, OID_AUTO, p_fail_flags, CTLFLAG_RD,
347 &sp_p_fail_flags, 0, "SP page promotion failure: page flags don't match");
348
349 static u_long sp_p_fail_prot;
350 SYSCTL_ULONG(_vm_pmap_sp, OID_AUTO, p_fail_prot, CTLFLAG_RD,
351 &sp_p_fail_prot, 0,
352 "SP page promotion failure: page protections don't match");
353
354 static u_long sp_p_fail_wimg;
355 SYSCTL_ULONG(_vm_pmap_sp, OID_AUTO, p_fail_wimg, CTLFLAG_RD,
356 &sp_p_fail_wimg, 0, "SP page promotion failure: WIMG bits don't match");
357
358 static u_long sp_promotions;
359 SYSCTL_ULONG(_vm_pmap_sp, OID_AUTO, promotions, CTLFLAG_RD,
360 &sp_promotions, 0, "SP page promotions");
361
362 static bool moea64_ps_enabled(pmap_t);
363 static void moea64_align_superpage(vm_object_t, vm_ooffset_t,
364 vm_offset_t *, vm_size_t);
365
366 static int moea64_sp_enter(pmap_t pmap, vm_offset_t va,
367 vm_page_t m, vm_prot_t prot, u_int flags, int8_t psind);
368 static struct pvo_entry *moea64_sp_remove(struct pvo_entry *sp,
369 struct pvo_dlist *tofree);
370
371 #if VM_NRESERVLEVEL > 0
372 static void moea64_sp_promote(pmap_t pmap, vm_offset_t va, vm_page_t m);
373 #endif
374 static void moea64_sp_demote_aligned(struct pvo_entry *sp);
375 static void moea64_sp_demote(struct pvo_entry *pvo);
376
377 static struct pvo_entry *moea64_sp_unwire(struct pvo_entry *sp);
378 static struct pvo_entry *moea64_sp_protect(struct pvo_entry *sp,
379 vm_prot_t prot);
380
381 static int64_t moea64_sp_query(struct pvo_entry *pvo, uint64_t ptebit);
382 static int64_t moea64_sp_clear(struct pvo_entry *pvo, vm_page_t m,
383 uint64_t ptebit);
384
385 static __inline bool moea64_sp_pvo_in_range(struct pvo_entry *pvo,
386 vm_offset_t sva, vm_offset_t eva);
387
388 /*
389 * Kernel MMU interface
390 */
391 void moea64_clear_modify(vm_page_t);
392 void moea64_copy_page(vm_page_t, vm_page_t);
393 void moea64_copy_page_dmap(vm_page_t, vm_page_t);
394 void moea64_copy_pages(vm_page_t *ma, vm_offset_t a_offset,
395 vm_page_t *mb, vm_offset_t b_offset, int xfersize);
396 void moea64_copy_pages_dmap(vm_page_t *ma, vm_offset_t a_offset,
397 vm_page_t *mb, vm_offset_t b_offset, int xfersize);
398 int moea64_enter(pmap_t, vm_offset_t, vm_page_t, vm_prot_t,
399 u_int flags, int8_t psind);
400 void moea64_enter_object(pmap_t, vm_offset_t, vm_offset_t, vm_page_t,
401 vm_prot_t);
402 void moea64_enter_quick(pmap_t, vm_offset_t, vm_page_t, vm_prot_t);
403 vm_paddr_t moea64_extract(pmap_t, vm_offset_t);
404 vm_page_t moea64_extract_and_hold(pmap_t, vm_offset_t, vm_prot_t);
405 void moea64_init(void);
406 bool moea64_is_modified(vm_page_t);
407 bool moea64_is_prefaultable(pmap_t, vm_offset_t);
408 bool moea64_is_referenced(vm_page_t);
409 int moea64_ts_referenced(vm_page_t);
410 vm_offset_t moea64_map(vm_offset_t *, vm_paddr_t, vm_paddr_t, int);
411 bool moea64_page_exists_quick(pmap_t, vm_page_t);
412 void moea64_page_init(vm_page_t);
413 int moea64_page_wired_mappings(vm_page_t);
414 int moea64_pinit(pmap_t);
415 void moea64_pinit0(pmap_t);
416 void moea64_protect(pmap_t, vm_offset_t, vm_offset_t, vm_prot_t);
417 void moea64_qenter(vm_offset_t, vm_page_t *, int);
418 void moea64_qremove(vm_offset_t, int);
419 void moea64_release(pmap_t);
420 void moea64_remove(pmap_t, vm_offset_t, vm_offset_t);
421 void moea64_remove_pages(pmap_t);
422 void moea64_remove_all(vm_page_t);
423 void moea64_remove_write(vm_page_t);
424 void moea64_unwire(pmap_t, vm_offset_t, vm_offset_t);
425 void moea64_zero_page(vm_page_t);
426 void moea64_zero_page_dmap(vm_page_t);
427 void moea64_zero_page_area(vm_page_t, int, int);
428 void moea64_activate(struct thread *);
429 void moea64_deactivate(struct thread *);
430 void *moea64_mapdev(vm_paddr_t, vm_size_t);
431 void *moea64_mapdev_attr(vm_paddr_t, vm_size_t, vm_memattr_t);
432 void moea64_unmapdev(void *, vm_size_t);
433 vm_paddr_t moea64_kextract(vm_offset_t);
434 void moea64_page_set_memattr(vm_page_t m, vm_memattr_t ma);
435 void moea64_kenter_attr(vm_offset_t, vm_paddr_t, vm_memattr_t ma);
436 void moea64_kenter(vm_offset_t, vm_paddr_t);
437 int moea64_dev_direct_mapped(vm_paddr_t, vm_size_t);
438 static void moea64_sync_icache(pmap_t, vm_offset_t, vm_size_t);
439 void moea64_dumpsys_map(vm_paddr_t pa, size_t sz,
440 void **va);
441 void moea64_scan_init(void);
442 vm_offset_t moea64_quick_enter_page(vm_page_t m);
443 vm_offset_t moea64_quick_enter_page_dmap(vm_page_t m);
444 void moea64_quick_remove_page(vm_offset_t addr);
445 bool moea64_page_is_mapped(vm_page_t m);
446 static int moea64_map_user_ptr(pmap_t pm,
447 volatile const void *uaddr, void **kaddr, size_t ulen, size_t *klen);
448 static int moea64_decode_kernel_ptr(vm_offset_t addr,
449 int *is_user, vm_offset_t *decoded_addr);
450 static size_t moea64_scan_pmap(struct bitset *dump_bitset);
451 static void *moea64_dump_pmap_init(unsigned blkpgs);
452 #ifdef __powerpc64__
453 static void moea64_page_array_startup(long);
454 #endif
455 static int moea64_mincore(pmap_t, vm_offset_t, vm_paddr_t *);
456
457 static struct pmap_funcs moea64_methods = {
458 .clear_modify = moea64_clear_modify,
459 .copy_page = moea64_copy_page,
460 .copy_pages = moea64_copy_pages,
461 .enter = moea64_enter,
462 .enter_object = moea64_enter_object,
463 .enter_quick = moea64_enter_quick,
464 .extract = moea64_extract,
465 .extract_and_hold = moea64_extract_and_hold,
466 .init = moea64_init,
467 .is_modified = moea64_is_modified,
468 .is_prefaultable = moea64_is_prefaultable,
469 .is_referenced = moea64_is_referenced,
470 .ts_referenced = moea64_ts_referenced,
471 .map = moea64_map,
472 .mincore = moea64_mincore,
473 .page_exists_quick = moea64_page_exists_quick,
474 .page_init = moea64_page_init,
475 .page_wired_mappings = moea64_page_wired_mappings,
476 .pinit = moea64_pinit,
477 .pinit0 = moea64_pinit0,
478 .protect = moea64_protect,
479 .qenter = moea64_qenter,
480 .qremove = moea64_qremove,
481 .release = moea64_release,
482 .remove = moea64_remove,
483 .remove_pages = moea64_remove_pages,
484 .remove_all = moea64_remove_all,
485 .remove_write = moea64_remove_write,
486 .sync_icache = moea64_sync_icache,
487 .unwire = moea64_unwire,
488 .zero_page = moea64_zero_page,
489 .zero_page_area = moea64_zero_page_area,
490 .activate = moea64_activate,
491 .deactivate = moea64_deactivate,
492 .page_set_memattr = moea64_page_set_memattr,
493 .quick_enter_page = moea64_quick_enter_page,
494 .quick_remove_page = moea64_quick_remove_page,
495 .page_is_mapped = moea64_page_is_mapped,
496 #ifdef __powerpc64__
497 .page_array_startup = moea64_page_array_startup,
498 #endif
499 .ps_enabled = moea64_ps_enabled,
500 .align_superpage = moea64_align_superpage,
501
502 /* Internal interfaces */
503 .mapdev = moea64_mapdev,
504 .mapdev_attr = moea64_mapdev_attr,
505 .unmapdev = moea64_unmapdev,
506 .kextract = moea64_kextract,
507 .kenter = moea64_kenter,
508 .kenter_attr = moea64_kenter_attr,
509 .dev_direct_mapped = moea64_dev_direct_mapped,
510 .dumpsys_pa_init = moea64_scan_init,
511 .dumpsys_scan_pmap = moea64_scan_pmap,
512 .dumpsys_dump_pmap_init = moea64_dump_pmap_init,
513 .dumpsys_map_chunk = moea64_dumpsys_map,
514 .map_user_ptr = moea64_map_user_ptr,
515 .decode_kernel_ptr = moea64_decode_kernel_ptr,
516 };
517
518 MMU_DEF(oea64_mmu, "mmu_oea64_base", moea64_methods);
519
520 /*
521 * Get physical address from PVO.
522 *
523 * For superpages, the lower bits are not stored on pvo_pte.pa and must be
524 * obtained from VA.
525 */
526 static __always_inline vm_paddr_t
moea64_pvo_paddr(struct pvo_entry * pvo)527 moea64_pvo_paddr(struct pvo_entry *pvo)
528 {
529 vm_paddr_t pa;
530
531 pa = (pvo)->pvo_pte.pa & LPTE_RPGN;
532
533 if (PVO_IS_SP(pvo)) {
534 pa &= ~HPT_SP_MASK; /* This is needed to clear LPTE_LP bits. */
535 pa |= PVO_VADDR(pvo) & HPT_SP_MASK;
536 }
537 return (pa);
538 }
539
540 static struct pvo_head *
vm_page_to_pvoh(vm_page_t m)541 vm_page_to_pvoh(vm_page_t m)
542 {
543
544 mtx_assert(PV_LOCKPTR(VM_PAGE_TO_PHYS(m)), MA_OWNED);
545 return (&m->md.mdpg_pvoh);
546 }
547
548 static struct pvo_entry *
alloc_pvo_entry(int bootstrap)549 alloc_pvo_entry(int bootstrap)
550 {
551 struct pvo_entry *pvo;
552
553 if (!moea64_initialized || bootstrap) {
554 if (moea64_bpvo_pool_index >= moea64_bpvo_pool_size) {
555 panic("%s: bpvo pool exhausted, index=%d, size=%d, bytes=%zd."
556 "Try setting machdep.moea64_bpvo_pool_size tunable",
557 __func__, moea64_bpvo_pool_index,
558 moea64_bpvo_pool_size,
559 moea64_bpvo_pool_size * sizeof(struct pvo_entry));
560 }
561 pvo = &moea64_bpvo_pool[
562 atomic_fetchadd_int(&moea64_bpvo_pool_index, 1)];
563 bzero(pvo, sizeof(*pvo));
564 pvo->pvo_vaddr = PVO_BOOTSTRAP;
565 } else
566 pvo = uma_zalloc(moea64_pvo_zone, M_NOWAIT | M_ZERO);
567
568 return (pvo);
569 }
570
571 static void
init_pvo_entry(struct pvo_entry * pvo,pmap_t pmap,vm_offset_t va)572 init_pvo_entry(struct pvo_entry *pvo, pmap_t pmap, vm_offset_t va)
573 {
574 uint64_t vsid;
575 uint64_t hash;
576 int shift;
577
578 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
579
580 pvo->pvo_pmap = pmap;
581 va &= ~ADDR_POFF;
582 pvo->pvo_vaddr |= va;
583 vsid = va_to_vsid(pmap, va);
584 pvo->pvo_vpn = (uint64_t)((va & ADDR_PIDX) >> ADDR_PIDX_SHFT)
585 | (vsid << 16);
586
587 if (pmap == kernel_pmap && (pvo->pvo_vaddr & PVO_LARGE) != 0)
588 shift = moea64_large_page_shift;
589 else
590 shift = ADDR_PIDX_SHFT;
591 hash = (vsid & VSID_HASH_MASK) ^ (((uint64_t)va & ADDR_PIDX) >> shift);
592 pvo->pvo_pte.slot = (hash & moea64_pteg_mask) << 3;
593 }
594
595 static void
free_pvo_entry(struct pvo_entry * pvo)596 free_pvo_entry(struct pvo_entry *pvo)
597 {
598
599 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP))
600 uma_zfree(moea64_pvo_zone, pvo);
601 }
602
603 void
moea64_pte_from_pvo(const struct pvo_entry * pvo,struct lpte * lpte)604 moea64_pte_from_pvo(const struct pvo_entry *pvo, struct lpte *lpte)
605 {
606
607 lpte->pte_hi = moea64_pte_vpn_from_pvo_vpn(pvo);
608 lpte->pte_hi |= LPTE_VALID;
609
610 if (pvo->pvo_vaddr & PVO_LARGE)
611 lpte->pte_hi |= LPTE_BIG;
612 if (pvo->pvo_vaddr & PVO_WIRED)
613 lpte->pte_hi |= LPTE_WIRED;
614 if (pvo->pvo_vaddr & PVO_HID)
615 lpte->pte_hi |= LPTE_HID;
616
617 lpte->pte_lo = pvo->pvo_pte.pa; /* Includes WIMG bits */
618 if (pvo->pvo_pte.prot & VM_PROT_WRITE)
619 lpte->pte_lo |= LPTE_BW;
620 else
621 lpte->pte_lo |= LPTE_BR;
622
623 if (!(pvo->pvo_pte.prot & VM_PROT_EXECUTE))
624 lpte->pte_lo |= LPTE_NOEXEC;
625 }
626
627 static __inline uint64_t
moea64_calc_wimg(vm_paddr_t pa,vm_memattr_t ma)628 moea64_calc_wimg(vm_paddr_t pa, vm_memattr_t ma)
629 {
630 uint64_t pte_lo;
631 int i;
632
633 if (ma != VM_MEMATTR_DEFAULT) {
634 switch (ma) {
635 case VM_MEMATTR_UNCACHEABLE:
636 return (LPTE_I | LPTE_G);
637 case VM_MEMATTR_CACHEABLE:
638 return (LPTE_M);
639 case VM_MEMATTR_WRITE_COMBINING:
640 case VM_MEMATTR_WRITE_BACK:
641 case VM_MEMATTR_PREFETCHABLE:
642 return (LPTE_I);
643 case VM_MEMATTR_WRITE_THROUGH:
644 return (LPTE_W | LPTE_M);
645 }
646 }
647
648 /*
649 * Assume the page is cache inhibited and access is guarded unless
650 * it's in our available memory array.
651 */
652 pte_lo = LPTE_I | LPTE_G;
653 for (i = 0; i < pregions_sz; i++) {
654 if ((pa >= pregions[i].mr_start) &&
655 (pa < (pregions[i].mr_start + pregions[i].mr_size))) {
656 pte_lo &= ~(LPTE_I | LPTE_G);
657 pte_lo |= LPTE_M;
658 break;
659 }
660 }
661
662 return pte_lo;
663 }
664
665 /*
666 * Quick sort callout for comparing memory regions.
667 */
668 static int om_cmp(const void *a, const void *b);
669
670 static int
om_cmp(const void * a,const void * b)671 om_cmp(const void *a, const void *b)
672 {
673 const struct ofw_map *mapa;
674 const struct ofw_map *mapb;
675
676 mapa = a;
677 mapb = b;
678 if (mapa->om_pa < mapb->om_pa)
679 return (-1);
680 else if (mapa->om_pa > mapb->om_pa)
681 return (1);
682 else
683 return (0);
684 }
685
686 static void
moea64_add_ofw_mappings(phandle_t mmu,size_t sz)687 moea64_add_ofw_mappings(phandle_t mmu, size_t sz)
688 {
689 struct ofw_map translations[sz/(4*sizeof(cell_t))]; /*>= 4 cells per */
690 pcell_t acells, trans_cells[sz/sizeof(cell_t)];
691 struct pvo_entry *pvo;
692 register_t msr;
693 vm_offset_t off;
694 vm_paddr_t pa_base;
695 int i, j;
696
697 bzero(translations, sz);
698 OF_getencprop(OF_finddevice("/"), "#address-cells", &acells,
699 sizeof(acells));
700 if (OF_getencprop(mmu, "translations", trans_cells, sz) == -1)
701 panic("moea64_bootstrap: can't get ofw translations");
702
703 CTR0(KTR_PMAP, "moea64_add_ofw_mappings: translations");
704 sz /= sizeof(cell_t);
705 for (i = 0, j = 0; i < sz; j++) {
706 translations[j].om_va = trans_cells[i++];
707 translations[j].om_len = trans_cells[i++];
708 translations[j].om_pa = trans_cells[i++];
709 if (acells == 2) {
710 translations[j].om_pa <<= 32;
711 translations[j].om_pa |= trans_cells[i++];
712 }
713 translations[j].om_mode = trans_cells[i++];
714 }
715 KASSERT(i == sz, ("Translations map has incorrect cell count (%d/%zd)",
716 i, sz));
717
718 sz = j;
719 qsort(translations, sz, sizeof (*translations), om_cmp);
720
721 for (i = 0; i < sz; i++) {
722 pa_base = translations[i].om_pa;
723 #ifndef __powerpc64__
724 if ((translations[i].om_pa >> 32) != 0)
725 panic("OFW translations above 32-bit boundary!");
726 #endif
727
728 if (pa_base % PAGE_SIZE)
729 panic("OFW translation not page-aligned (phys)!");
730 if (translations[i].om_va % PAGE_SIZE)
731 panic("OFW translation not page-aligned (virt)!");
732
733 CTR3(KTR_PMAP, "translation: pa=%#zx va=%#x len=%#x",
734 pa_base, translations[i].om_va, translations[i].om_len);
735
736 /* Now enter the pages for this mapping */
737
738 DISABLE_TRANS(msr);
739 for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) {
740 /* If this address is direct-mapped, skip remapping */
741 if (hw_direct_map &&
742 translations[i].om_va == PHYS_TO_DMAP(pa_base) &&
743 moea64_calc_wimg(pa_base + off, VM_MEMATTR_DEFAULT)
744 == LPTE_M)
745 continue;
746
747 PMAP_LOCK(kernel_pmap);
748 pvo = moea64_pvo_find_va(kernel_pmap,
749 translations[i].om_va + off);
750 PMAP_UNLOCK(kernel_pmap);
751 if (pvo != NULL)
752 continue;
753
754 moea64_kenter(translations[i].om_va + off,
755 pa_base + off);
756 }
757 ENABLE_TRANS(msr);
758 }
759 }
760
761 #ifdef __powerpc64__
762 static void
moea64_probe_large_page(void)763 moea64_probe_large_page(void)
764 {
765 uint16_t pvr = mfpvr() >> 16;
766
767 switch (pvr) {
768 case IBM970:
769 case IBM970FX:
770 case IBM970MP:
771 powerpc_sync(); isync();
772 mtspr(SPR_HID4, mfspr(SPR_HID4) & ~HID4_970_DISABLE_LG_PG);
773 powerpc_sync(); isync();
774
775 /* FALLTHROUGH */
776 default:
777 if (moea64_large_page_size == 0) {
778 moea64_large_page_size = 0x1000000; /* 16 MB */
779 moea64_large_page_shift = 24;
780 }
781 }
782
783 moea64_large_page_mask = moea64_large_page_size - 1;
784 }
785
786 static void
moea64_bootstrap_slb_prefault(vm_offset_t va,int large)787 moea64_bootstrap_slb_prefault(vm_offset_t va, int large)
788 {
789 struct slb *cache;
790 struct slb entry;
791 uint64_t esid, slbe;
792 uint64_t i;
793
794 cache = PCPU_GET(aim.slb);
795 esid = va >> ADDR_SR_SHFT;
796 slbe = (esid << SLBE_ESID_SHIFT) | SLBE_VALID;
797
798 for (i = 0; i < 64; i++) {
799 if (cache[i].slbe == (slbe | i))
800 return;
801 }
802
803 entry.slbe = slbe;
804 entry.slbv = KERNEL_VSID(esid) << SLBV_VSID_SHIFT;
805 if (large)
806 entry.slbv |= SLBV_L;
807
808 slb_insert_kernel(entry.slbe, entry.slbv);
809 }
810 #endif
811
812 static int
moea64_kenter_large(vm_offset_t va,vm_paddr_t pa,uint64_t attr,int bootstrap)813 moea64_kenter_large(vm_offset_t va, vm_paddr_t pa, uint64_t attr, int bootstrap)
814 {
815 struct pvo_entry *pvo;
816 uint64_t pte_lo;
817 int error;
818
819 pte_lo = LPTE_M;
820 pte_lo |= attr;
821
822 pvo = alloc_pvo_entry(bootstrap);
823 pvo->pvo_vaddr |= PVO_WIRED | PVO_LARGE;
824 init_pvo_entry(pvo, kernel_pmap, va);
825
826 pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE |
827 VM_PROT_EXECUTE;
828 pvo->pvo_pte.pa = pa | pte_lo;
829 error = moea64_pvo_enter(pvo, NULL, NULL);
830 if (error != 0)
831 panic("Error %d inserting large page\n", error);
832 return (0);
833 }
834
835 static void
moea64_setup_direct_map(vm_offset_t kernelstart,vm_offset_t kernelend)836 moea64_setup_direct_map(vm_offset_t kernelstart,
837 vm_offset_t kernelend)
838 {
839 register_t msr;
840 vm_paddr_t pa, pkernelstart, pkernelend;
841 vm_offset_t size, off;
842 uint64_t pte_lo;
843 int i;
844
845 if (moea64_large_page_size == 0)
846 hw_direct_map = 0;
847
848 DISABLE_TRANS(msr);
849 if (hw_direct_map) {
850 PMAP_LOCK(kernel_pmap);
851 for (i = 0; i < pregions_sz; i++) {
852 for (pa = pregions[i].mr_start; pa < pregions[i].mr_start +
853 pregions[i].mr_size; pa += moea64_large_page_size) {
854 pte_lo = LPTE_M;
855 if (pa & moea64_large_page_mask) {
856 pa &= moea64_large_page_mask;
857 pte_lo |= LPTE_G;
858 }
859 if (pa + moea64_large_page_size >
860 pregions[i].mr_start + pregions[i].mr_size)
861 pte_lo |= LPTE_G;
862
863 moea64_kenter_large(PHYS_TO_DMAP(pa), pa, pte_lo, 1);
864 }
865 }
866 PMAP_UNLOCK(kernel_pmap);
867 }
868
869 /*
870 * Make sure the kernel and BPVO pool stay mapped on systems either
871 * without a direct map or on which the kernel is not already executing
872 * out of the direct-mapped region.
873 */
874 if (kernelstart < DMAP_BASE_ADDRESS) {
875 /*
876 * For pre-dmap execution, we need to use identity mapping
877 * because we will be operating with the mmu on but in the
878 * wrong address configuration until we __restartkernel().
879 */
880 for (pa = kernelstart & ~PAGE_MASK; pa < kernelend;
881 pa += PAGE_SIZE)
882 moea64_kenter(pa, pa);
883 } else if (!hw_direct_map) {
884 pkernelstart = kernelstart & ~DMAP_BASE_ADDRESS;
885 pkernelend = kernelend & ~DMAP_BASE_ADDRESS;
886 for (pa = pkernelstart & ~PAGE_MASK; pa < pkernelend;
887 pa += PAGE_SIZE)
888 moea64_kenter(pa | DMAP_BASE_ADDRESS, pa);
889 }
890
891 if (!hw_direct_map) {
892 size = moea64_bpvo_pool_size*sizeof(struct pvo_entry);
893 off = (vm_offset_t)(moea64_bpvo_pool);
894 for (pa = off; pa < off + size; pa += PAGE_SIZE)
895 moea64_kenter(pa, pa);
896
897 /* Map exception vectors */
898 for (pa = EXC_RSVD; pa < EXC_LAST; pa += PAGE_SIZE)
899 moea64_kenter(pa | DMAP_BASE_ADDRESS, pa);
900 }
901 ENABLE_TRANS(msr);
902
903 /*
904 * Allow user to override unmapped_buf_allowed for testing.
905 * XXXKIB Only direct map implementation was tested.
906 */
907 if (!TUNABLE_INT_FETCH("vfs.unmapped_buf_allowed",
908 &unmapped_buf_allowed))
909 unmapped_buf_allowed = hw_direct_map;
910 }
911
912 /* Quick sort callout for comparing physical addresses. */
913 static int
pa_cmp(const void * a,const void * b)914 pa_cmp(const void *a, const void *b)
915 {
916 const vm_paddr_t *pa = a, *pb = b;
917
918 if (*pa < *pb)
919 return (-1);
920 else if (*pa > *pb)
921 return (1);
922 else
923 return (0);
924 }
925
926 void
moea64_early_bootstrap(vm_offset_t kernelstart,vm_offset_t kernelend)927 moea64_early_bootstrap(vm_offset_t kernelstart, vm_offset_t kernelend)
928 {
929 int i, j;
930 vm_size_t physsz, hwphyssz;
931 vm_paddr_t kernelphysstart, kernelphysend;
932 int rm_pavail;
933
934 /* Level 0 reservations consist of 4096 pages (16MB superpage). */
935 vm_level_0_order = 12;
936
937 #ifndef __powerpc64__
938 /* We don't have a direct map since there is no BAT */
939 hw_direct_map = 0;
940
941 /* Make sure battable is zero, since we have no BAT */
942 for (i = 0; i < 16; i++) {
943 battable[i].batu = 0;
944 battable[i].batl = 0;
945 }
946 #else
947 /* Install trap handlers for SLBs */
948 bcopy(&slbtrap, (void *)EXC_DSE,(size_t)&slbtrapend - (size_t)&slbtrap);
949 bcopy(&slbtrap, (void *)EXC_ISE,(size_t)&slbtrapend - (size_t)&slbtrap);
950 __syncicache((void *)EXC_DSE, 0x80);
951 __syncicache((void *)EXC_ISE, 0x80);
952 #endif
953
954 kernelphysstart = kernelstart & ~DMAP_BASE_ADDRESS;
955 kernelphysend = kernelend & ~DMAP_BASE_ADDRESS;
956
957 /* Get physical memory regions from firmware */
958 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz);
959 CTR0(KTR_PMAP, "moea64_bootstrap: physical memory");
960
961 if (PHYS_AVAIL_ENTRIES < regions_sz)
962 panic("moea64_bootstrap: phys_avail too small");
963
964 phys_avail_count = 0;
965 physsz = 0;
966 hwphyssz = 0;
967 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz);
968 for (i = 0, j = 0; i < regions_sz; i++, j += 2) {
969 CTR3(KTR_PMAP, "region: %#zx - %#zx (%#zx)",
970 regions[i].mr_start, regions[i].mr_start +
971 regions[i].mr_size, regions[i].mr_size);
972 if (hwphyssz != 0 &&
973 (physsz + regions[i].mr_size) >= hwphyssz) {
974 if (physsz < hwphyssz) {
975 phys_avail[j] = regions[i].mr_start;
976 phys_avail[j + 1] = regions[i].mr_start +
977 hwphyssz - physsz;
978 physsz = hwphyssz;
979 phys_avail_count++;
980 dump_avail[j] = phys_avail[j];
981 dump_avail[j + 1] = phys_avail[j + 1];
982 }
983 break;
984 }
985 phys_avail[j] = regions[i].mr_start;
986 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size;
987 phys_avail_count++;
988 physsz += regions[i].mr_size;
989 dump_avail[j] = phys_avail[j];
990 dump_avail[j + 1] = phys_avail[j + 1];
991 }
992
993 /* Check for overlap with the kernel and exception vectors */
994 rm_pavail = 0;
995 for (j = 0; j < 2*phys_avail_count; j+=2) {
996 if (phys_avail[j] < EXC_LAST)
997 phys_avail[j] += EXC_LAST;
998
999 if (phys_avail[j] >= kernelphysstart &&
1000 phys_avail[j+1] <= kernelphysend) {
1001 phys_avail[j] = phys_avail[j+1] = ~0;
1002 rm_pavail++;
1003 continue;
1004 }
1005
1006 if (kernelphysstart >= phys_avail[j] &&
1007 kernelphysstart < phys_avail[j+1]) {
1008 if (kernelphysend < phys_avail[j+1]) {
1009 phys_avail[2*phys_avail_count] =
1010 (kernelphysend & ~PAGE_MASK) + PAGE_SIZE;
1011 phys_avail[2*phys_avail_count + 1] =
1012 phys_avail[j+1];
1013 phys_avail_count++;
1014 }
1015
1016 phys_avail[j+1] = kernelphysstart & ~PAGE_MASK;
1017 }
1018
1019 if (kernelphysend >= phys_avail[j] &&
1020 kernelphysend < phys_avail[j+1]) {
1021 if (kernelphysstart > phys_avail[j]) {
1022 phys_avail[2*phys_avail_count] = phys_avail[j];
1023 phys_avail[2*phys_avail_count + 1] =
1024 kernelphysstart & ~PAGE_MASK;
1025 phys_avail_count++;
1026 }
1027
1028 phys_avail[j] = (kernelphysend & ~PAGE_MASK) +
1029 PAGE_SIZE;
1030 }
1031 }
1032
1033 /* Remove physical available regions marked for removal (~0) */
1034 if (rm_pavail) {
1035 qsort(phys_avail, 2*phys_avail_count, sizeof(phys_avail[0]),
1036 pa_cmp);
1037 phys_avail_count -= rm_pavail;
1038 for (i = 2*phys_avail_count;
1039 i < 2*(phys_avail_count + rm_pavail); i+=2)
1040 phys_avail[i] = phys_avail[i+1] = 0;
1041 }
1042
1043 physmem = btoc(physsz);
1044
1045 #ifdef PTEGCOUNT
1046 moea64_pteg_count = PTEGCOUNT;
1047 #else
1048 moea64_pteg_count = 0x1000;
1049
1050 while (moea64_pteg_count < physmem)
1051 moea64_pteg_count <<= 1;
1052
1053 moea64_pteg_count >>= 1;
1054 #endif /* PTEGCOUNT */
1055 }
1056
1057 void
moea64_mid_bootstrap(vm_offset_t kernelstart,vm_offset_t kernelend)1058 moea64_mid_bootstrap(vm_offset_t kernelstart, vm_offset_t kernelend)
1059 {
1060 int i;
1061
1062 /*
1063 * Set PTEG mask
1064 */
1065 moea64_pteg_mask = moea64_pteg_count - 1;
1066
1067 /*
1068 * Initialize SLB table lock and page locks
1069 */
1070 mtx_init(&moea64_slb_mutex, "SLB table", NULL, MTX_DEF);
1071 for (i = 0; i < PV_LOCK_COUNT; i++)
1072 mtx_init(&pv_lock[i], "page pv", NULL, MTX_DEF);
1073
1074 /*
1075 * Initialise the bootstrap pvo pool.
1076 */
1077 TUNABLE_INT_FETCH("machdep.moea64_bpvo_pool_size", &moea64_bpvo_pool_size);
1078 if (moea64_bpvo_pool_size == 0) {
1079 if (!hw_direct_map)
1080 moea64_bpvo_pool_size = ((ptoa((uintmax_t)physmem) * sizeof(struct vm_page)) /
1081 (PAGE_SIZE * PAGE_SIZE)) * BPVO_POOL_EXPANSION_FACTOR;
1082 else
1083 moea64_bpvo_pool_size = BPVO_POOL_SIZE;
1084 }
1085
1086 if (boothowto & RB_VERBOSE) {
1087 printf("mmu_oea64: bpvo pool entries = %d, bpvo pool size = %zu MB\n",
1088 moea64_bpvo_pool_size,
1089 moea64_bpvo_pool_size*sizeof(struct pvo_entry) / 1048576);
1090 }
1091
1092 moea64_bpvo_pool = (struct pvo_entry *)moea64_bootstrap_alloc(
1093 moea64_bpvo_pool_size*sizeof(struct pvo_entry), PAGE_SIZE);
1094 moea64_bpvo_pool_index = 0;
1095
1096 /* Place at address usable through the direct map */
1097 if (hw_direct_map)
1098 moea64_bpvo_pool = (struct pvo_entry *)
1099 PHYS_TO_DMAP((uintptr_t)moea64_bpvo_pool);
1100
1101 /*
1102 * Make sure kernel vsid is allocated as well as VSID 0.
1103 */
1104 #ifndef __powerpc64__
1105 moea64_vsid_bitmap[(KERNEL_VSIDBITS & (NVSIDS - 1)) / VSID_NBPW]
1106 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW);
1107 moea64_vsid_bitmap[0] |= 1;
1108 #endif
1109
1110 /*
1111 * Initialize the kernel pmap (which is statically allocated).
1112 */
1113 #ifdef __powerpc64__
1114 for (i = 0; i < 64; i++) {
1115 pcpup->pc_aim.slb[i].slbv = 0;
1116 pcpup->pc_aim.slb[i].slbe = 0;
1117 }
1118 #else
1119 for (i = 0; i < 16; i++)
1120 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i;
1121 #endif
1122
1123 kernel_pmap->pmap_phys = kernel_pmap;
1124 CPU_FILL(&kernel_pmap->pm_active);
1125 RB_INIT(&kernel_pmap->pmap_pvo);
1126
1127 PMAP_LOCK_INIT(kernel_pmap);
1128
1129 /*
1130 * Now map in all the other buffers we allocated earlier
1131 */
1132
1133 moea64_setup_direct_map(kernelstart, kernelend);
1134 }
1135
1136 void
moea64_late_bootstrap(vm_offset_t kernelstart,vm_offset_t kernelend)1137 moea64_late_bootstrap(vm_offset_t kernelstart, vm_offset_t kernelend)
1138 {
1139 ihandle_t mmui;
1140 phandle_t chosen;
1141 phandle_t mmu;
1142 ssize_t sz;
1143 int i;
1144 vm_offset_t pa, va;
1145 void *dpcpu;
1146
1147 /*
1148 * Set up the Open Firmware pmap and add its mappings if not in real
1149 * mode.
1150 */
1151
1152 chosen = OF_finddevice("/chosen");
1153 if (chosen != -1 && OF_getencprop(chosen, "mmu", &mmui, 4) != -1) {
1154 mmu = OF_instance_to_package(mmui);
1155 if (mmu == -1 ||
1156 (sz = OF_getproplen(mmu, "translations")) == -1)
1157 sz = 0;
1158 if (sz > 6144 /* tmpstksz - 2 KB headroom */)
1159 panic("moea64_bootstrap: too many ofw translations");
1160
1161 if (sz > 0)
1162 moea64_add_ofw_mappings(mmu, sz);
1163 }
1164
1165 /*
1166 * Calculate the last available physical address.
1167 */
1168 Maxmem = 0;
1169 for (i = 0; phys_avail[i + 1] != 0; i += 2)
1170 Maxmem = MAX(Maxmem, powerpc_btop(phys_avail[i + 1]));
1171
1172 /*
1173 * Initialize MMU.
1174 */
1175 pmap_cpu_bootstrap(0);
1176 mtmsr(mfmsr() | PSL_DR | PSL_IR);
1177 pmap_bootstrapped++;
1178
1179 /*
1180 * Set the start and end of kva.
1181 */
1182 virtual_avail = VM_MIN_KERNEL_ADDRESS;
1183 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS;
1184
1185 /*
1186 * Map the entire KVA range into the SLB. We must not fault there.
1187 */
1188 #ifdef __powerpc64__
1189 for (va = virtual_avail; va < virtual_end; va += SEGMENT_LENGTH)
1190 moea64_bootstrap_slb_prefault(va, 0);
1191 #endif
1192
1193 /*
1194 * Remap any early IO mappings (console framebuffer, etc.)
1195 */
1196 bs_remap_earlyboot();
1197
1198 /*
1199 * Figure out how far we can extend virtual_end into segment 16
1200 * without running into existing mappings. Segment 16 is guaranteed
1201 * to contain neither RAM nor devices (at least on Apple hardware),
1202 * but will generally contain some OFW mappings we should not
1203 * step on.
1204 */
1205
1206 #ifndef __powerpc64__ /* KVA is in high memory on PPC64 */
1207 PMAP_LOCK(kernel_pmap);
1208 while (virtual_end < VM_MAX_KERNEL_ADDRESS &&
1209 moea64_pvo_find_va(kernel_pmap, virtual_end+1) == NULL)
1210 virtual_end += PAGE_SIZE;
1211 PMAP_UNLOCK(kernel_pmap);
1212 #endif
1213
1214 /*
1215 * Allocate a kernel stack with a guard page for thread0 and map it
1216 * into the kernel page map.
1217 */
1218 pa = moea64_bootstrap_alloc(kstack_pages * PAGE_SIZE, PAGE_SIZE);
1219 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE;
1220 virtual_avail = va + kstack_pages * PAGE_SIZE;
1221 CTR2(KTR_PMAP, "moea64_bootstrap: kstack0 at %#x (%#x)", pa, va);
1222 thread0.td_kstack = va;
1223 thread0.td_kstack_pages = kstack_pages;
1224 for (i = 0; i < kstack_pages; i++) {
1225 moea64_kenter(va, pa);
1226 pa += PAGE_SIZE;
1227 va += PAGE_SIZE;
1228 }
1229
1230 /*
1231 * Allocate virtual address space for the message buffer.
1232 */
1233 pa = msgbuf_phys = moea64_bootstrap_alloc(msgbufsize, PAGE_SIZE);
1234 msgbufp = (struct msgbuf *)virtual_avail;
1235 va = virtual_avail;
1236 virtual_avail += round_page(msgbufsize);
1237 while (va < virtual_avail) {
1238 moea64_kenter(va, pa);
1239 pa += PAGE_SIZE;
1240 va += PAGE_SIZE;
1241 }
1242
1243 /*
1244 * Allocate virtual address space for the dynamic percpu area.
1245 */
1246 pa = moea64_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE);
1247 dpcpu = (void *)virtual_avail;
1248 va = virtual_avail;
1249 virtual_avail += DPCPU_SIZE;
1250 while (va < virtual_avail) {
1251 moea64_kenter(va, pa);
1252 pa += PAGE_SIZE;
1253 va += PAGE_SIZE;
1254 }
1255 dpcpu_init(dpcpu, curcpu);
1256
1257 crashdumpmap = (caddr_t)virtual_avail;
1258 virtual_avail += MAXDUMPPGS * PAGE_SIZE;
1259
1260 /*
1261 * Allocate some things for page zeroing. We put this directly
1262 * in the page table and use MOEA64_PTE_REPLACE to avoid any
1263 * of the PVO book-keeping or other parts of the VM system
1264 * from even knowing that this hack exists.
1265 */
1266
1267 if (!hw_direct_map) {
1268 mtx_init(&moea64_scratchpage_mtx, "pvo zero page", NULL,
1269 MTX_DEF);
1270 for (i = 0; i < 2; i++) {
1271 moea64_scratchpage_va[i] = (virtual_end+1) - PAGE_SIZE;
1272 virtual_end -= PAGE_SIZE;
1273
1274 moea64_kenter(moea64_scratchpage_va[i], 0);
1275
1276 PMAP_LOCK(kernel_pmap);
1277 moea64_scratchpage_pvo[i] = moea64_pvo_find_va(
1278 kernel_pmap, (vm_offset_t)moea64_scratchpage_va[i]);
1279 PMAP_UNLOCK(kernel_pmap);
1280 }
1281 }
1282
1283 numa_mem_regions(&numa_pregions, &numapregions_sz);
1284 }
1285
1286 static void
moea64_pmap_init_qpages(void)1287 moea64_pmap_init_qpages(void)
1288 {
1289 struct pcpu *pc;
1290 int i;
1291
1292 if (hw_direct_map)
1293 return;
1294
1295 CPU_FOREACH(i) {
1296 pc = pcpu_find(i);
1297 pc->pc_qmap_addr = kva_alloc(PAGE_SIZE);
1298 if (pc->pc_qmap_addr == 0)
1299 panic("pmap_init_qpages: unable to allocate KVA");
1300 PMAP_LOCK(kernel_pmap);
1301 pc->pc_aim.qmap_pvo =
1302 moea64_pvo_find_va(kernel_pmap, pc->pc_qmap_addr);
1303 PMAP_UNLOCK(kernel_pmap);
1304 mtx_init(&pc->pc_aim.qmap_lock, "qmap lock", NULL, MTX_DEF);
1305 }
1306 }
1307
1308 SYSINIT(qpages_init, SI_SUB_CPU, SI_ORDER_ANY, moea64_pmap_init_qpages, NULL);
1309
1310 /*
1311 * Activate a user pmap. This mostly involves setting some non-CPU
1312 * state.
1313 */
1314 void
moea64_activate(struct thread * td)1315 moea64_activate(struct thread *td)
1316 {
1317 pmap_t pm;
1318
1319 pm = &td->td_proc->p_vmspace->vm_pmap;
1320 CPU_SET(PCPU_GET(cpuid), &pm->pm_active);
1321
1322 #ifdef __powerpc64__
1323 PCPU_SET(aim.userslb, pm->pm_slb);
1324 __asm __volatile("slbmte %0, %1; isync" ::
1325 "r"(td->td_pcb->pcb_cpu.aim.usr_vsid), "r"(USER_SLB_SLBE));
1326 #else
1327 PCPU_SET(curpmap, pm->pmap_phys);
1328 mtsrin(USER_SR << ADDR_SR_SHFT, td->td_pcb->pcb_cpu.aim.usr_vsid);
1329 #endif
1330 }
1331
1332 void
moea64_deactivate(struct thread * td)1333 moea64_deactivate(struct thread *td)
1334 {
1335 pmap_t pm;
1336
1337 __asm __volatile("isync; slbie %0" :: "r"(USER_ADDR));
1338
1339 pm = &td->td_proc->p_vmspace->vm_pmap;
1340 CPU_CLR(PCPU_GET(cpuid), &pm->pm_active);
1341 #ifdef __powerpc64__
1342 PCPU_SET(aim.userslb, NULL);
1343 #else
1344 PCPU_SET(curpmap, NULL);
1345 #endif
1346 }
1347
1348 void
moea64_unwire(pmap_t pm,vm_offset_t sva,vm_offset_t eva)1349 moea64_unwire(pmap_t pm, vm_offset_t sva, vm_offset_t eva)
1350 {
1351 struct pvo_entry key, *pvo;
1352 vm_page_t m;
1353 int64_t refchg;
1354
1355 key.pvo_vaddr = sva;
1356 PMAP_LOCK(pm);
1357 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key);
1358 pvo != NULL && PVO_VADDR(pvo) < eva;
1359 pvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo)) {
1360 if (PVO_IS_SP(pvo)) {
1361 if (moea64_sp_pvo_in_range(pvo, sva, eva)) {
1362 pvo = moea64_sp_unwire(pvo);
1363 continue;
1364 } else {
1365 CTR1(KTR_PMAP, "%s: demote before unwire",
1366 __func__);
1367 moea64_sp_demote(pvo);
1368 }
1369 }
1370
1371 if ((pvo->pvo_vaddr & PVO_WIRED) == 0)
1372 panic("moea64_unwire: pvo %p is missing PVO_WIRED",
1373 pvo);
1374 pvo->pvo_vaddr &= ~PVO_WIRED;
1375 refchg = moea64_pte_replace(pvo, 0 /* No invalidation */);
1376 if ((pvo->pvo_vaddr & PVO_MANAGED) &&
1377 (pvo->pvo_pte.prot & VM_PROT_WRITE)) {
1378 if (refchg < 0)
1379 refchg = LPTE_CHG;
1380 m = PHYS_TO_VM_PAGE(PVO_PADDR(pvo));
1381
1382 refchg |= atomic_readandclear_32(&m->md.mdpg_attrs);
1383 if (refchg & LPTE_CHG)
1384 vm_page_dirty(m);
1385 if (refchg & LPTE_REF)
1386 vm_page_aflag_set(m, PGA_REFERENCED);
1387 }
1388 pm->pm_stats.wired_count--;
1389 }
1390 PMAP_UNLOCK(pm);
1391 }
1392
1393 static int
moea64_mincore(pmap_t pmap,vm_offset_t addr,vm_paddr_t * pap)1394 moea64_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *pap)
1395 {
1396 struct pvo_entry *pvo;
1397 vm_paddr_t pa;
1398 vm_page_t m;
1399 int val;
1400 bool managed;
1401
1402 PMAP_LOCK(pmap);
1403
1404 pvo = moea64_pvo_find_va(pmap, addr);
1405 if (pvo != NULL) {
1406 pa = PVO_PADDR(pvo);
1407 m = PHYS_TO_VM_PAGE(pa);
1408 managed = (pvo->pvo_vaddr & PVO_MANAGED) == PVO_MANAGED;
1409 if (PVO_IS_SP(pvo))
1410 val = MINCORE_INCORE | MINCORE_PSIND(1);
1411 else
1412 val = MINCORE_INCORE;
1413 } else {
1414 PMAP_UNLOCK(pmap);
1415 return (0);
1416 }
1417
1418 PMAP_UNLOCK(pmap);
1419
1420 if (m == NULL)
1421 return (0);
1422
1423 if (managed) {
1424 if (moea64_is_modified(m))
1425 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
1426
1427 if (moea64_is_referenced(m))
1428 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
1429 }
1430
1431 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
1432 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
1433 managed) {
1434 *pap = pa;
1435 }
1436
1437 return (val);
1438 }
1439
1440 /*
1441 * This goes through and sets the physical address of our
1442 * special scratch PTE to the PA we want to zero or copy. Because
1443 * of locking issues (this can get called in pvo_enter() by
1444 * the UMA allocator), we can't use most other utility functions here
1445 */
1446
1447 static __inline
moea64_set_scratchpage_pa(int which,vm_paddr_t pa)1448 void moea64_set_scratchpage_pa(int which, vm_paddr_t pa)
1449 {
1450 struct pvo_entry *pvo;
1451
1452 KASSERT(!hw_direct_map, ("Using OEA64 scratchpage with a direct map!"));
1453 mtx_assert(&moea64_scratchpage_mtx, MA_OWNED);
1454
1455 pvo = moea64_scratchpage_pvo[which];
1456 PMAP_LOCK(pvo->pvo_pmap);
1457 pvo->pvo_pte.pa =
1458 moea64_calc_wimg(pa, VM_MEMATTR_DEFAULT) | (uint64_t)pa;
1459 moea64_pte_replace(pvo, MOEA64_PTE_INVALIDATE);
1460 PMAP_UNLOCK(pvo->pvo_pmap);
1461 isync();
1462 }
1463
1464 void
moea64_copy_page(vm_page_t msrc,vm_page_t mdst)1465 moea64_copy_page(vm_page_t msrc, vm_page_t mdst)
1466 {
1467 mtx_lock(&moea64_scratchpage_mtx);
1468
1469 moea64_set_scratchpage_pa(0, VM_PAGE_TO_PHYS(msrc));
1470 moea64_set_scratchpage_pa(1, VM_PAGE_TO_PHYS(mdst));
1471
1472 bcopy((void *)moea64_scratchpage_va[0],
1473 (void *)moea64_scratchpage_va[1], PAGE_SIZE);
1474
1475 mtx_unlock(&moea64_scratchpage_mtx);
1476 }
1477
1478 void
moea64_copy_page_dmap(vm_page_t msrc,vm_page_t mdst)1479 moea64_copy_page_dmap(vm_page_t msrc, vm_page_t mdst)
1480 {
1481 vm_offset_t dst;
1482 vm_offset_t src;
1483
1484 dst = VM_PAGE_TO_PHYS(mdst);
1485 src = VM_PAGE_TO_PHYS(msrc);
1486
1487 bcopy((void *)PHYS_TO_DMAP(src), (void *)PHYS_TO_DMAP(dst),
1488 PAGE_SIZE);
1489 }
1490
1491 inline void
moea64_copy_pages_dmap(vm_page_t * ma,vm_offset_t a_offset,vm_page_t * mb,vm_offset_t b_offset,int xfersize)1492 moea64_copy_pages_dmap(vm_page_t *ma, vm_offset_t a_offset,
1493 vm_page_t *mb, vm_offset_t b_offset, int xfersize)
1494 {
1495 void *a_cp, *b_cp;
1496 vm_offset_t a_pg_offset, b_pg_offset;
1497 int cnt;
1498
1499 while (xfersize > 0) {
1500 a_pg_offset = a_offset & PAGE_MASK;
1501 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
1502 a_cp = (char *)(uintptr_t)PHYS_TO_DMAP(
1503 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT])) +
1504 a_pg_offset;
1505 b_pg_offset = b_offset & PAGE_MASK;
1506 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
1507 b_cp = (char *)(uintptr_t)PHYS_TO_DMAP(
1508 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT])) +
1509 b_pg_offset;
1510 bcopy(a_cp, b_cp, cnt);
1511 a_offset += cnt;
1512 b_offset += cnt;
1513 xfersize -= cnt;
1514 }
1515 }
1516
1517 void
moea64_copy_pages(vm_page_t * ma,vm_offset_t a_offset,vm_page_t * mb,vm_offset_t b_offset,int xfersize)1518 moea64_copy_pages(vm_page_t *ma, vm_offset_t a_offset,
1519 vm_page_t *mb, vm_offset_t b_offset, int xfersize)
1520 {
1521 void *a_cp, *b_cp;
1522 vm_offset_t a_pg_offset, b_pg_offset;
1523 int cnt;
1524
1525 mtx_lock(&moea64_scratchpage_mtx);
1526 while (xfersize > 0) {
1527 a_pg_offset = a_offset & PAGE_MASK;
1528 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
1529 moea64_set_scratchpage_pa(0,
1530 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT]));
1531 a_cp = (char *)moea64_scratchpage_va[0] + a_pg_offset;
1532 b_pg_offset = b_offset & PAGE_MASK;
1533 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
1534 moea64_set_scratchpage_pa(1,
1535 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT]));
1536 b_cp = (char *)moea64_scratchpage_va[1] + b_pg_offset;
1537 bcopy(a_cp, b_cp, cnt);
1538 a_offset += cnt;
1539 b_offset += cnt;
1540 xfersize -= cnt;
1541 }
1542 mtx_unlock(&moea64_scratchpage_mtx);
1543 }
1544
1545 void
moea64_zero_page_area(vm_page_t m,int off,int size)1546 moea64_zero_page_area(vm_page_t m, int off, int size)
1547 {
1548 vm_paddr_t pa = VM_PAGE_TO_PHYS(m);
1549
1550 if (size + off > PAGE_SIZE)
1551 panic("moea64_zero_page: size + off > PAGE_SIZE");
1552
1553 if (hw_direct_map) {
1554 bzero((caddr_t)(uintptr_t)PHYS_TO_DMAP(pa) + off, size);
1555 } else {
1556 mtx_lock(&moea64_scratchpage_mtx);
1557 moea64_set_scratchpage_pa(0, pa);
1558 bzero((caddr_t)moea64_scratchpage_va[0] + off, size);
1559 mtx_unlock(&moea64_scratchpage_mtx);
1560 }
1561 }
1562
1563 /*
1564 * Zero a page of physical memory by temporarily mapping it
1565 */
1566 void
moea64_zero_page(vm_page_t m)1567 moea64_zero_page(vm_page_t m)
1568 {
1569 vm_paddr_t pa = VM_PAGE_TO_PHYS(m);
1570 vm_offset_t va, off;
1571
1572 mtx_lock(&moea64_scratchpage_mtx);
1573
1574 moea64_set_scratchpage_pa(0, pa);
1575 va = moea64_scratchpage_va[0];
1576
1577 for (off = 0; off < PAGE_SIZE; off += cacheline_size)
1578 __asm __volatile("dcbz 0,%0" :: "r"(va + off));
1579
1580 mtx_unlock(&moea64_scratchpage_mtx);
1581 }
1582
1583 void
moea64_zero_page_dmap(vm_page_t m)1584 moea64_zero_page_dmap(vm_page_t m)
1585 {
1586 vm_paddr_t pa = VM_PAGE_TO_PHYS(m);
1587 vm_offset_t va, off;
1588
1589 va = PHYS_TO_DMAP(pa);
1590 for (off = 0; off < PAGE_SIZE; off += cacheline_size)
1591 __asm __volatile("dcbz 0,%0" :: "r"(va + off));
1592 }
1593
1594 vm_offset_t
moea64_quick_enter_page(vm_page_t m)1595 moea64_quick_enter_page(vm_page_t m)
1596 {
1597 struct pvo_entry *pvo;
1598 vm_paddr_t pa = VM_PAGE_TO_PHYS(m);
1599
1600 /*
1601 * MOEA64_PTE_REPLACE does some locking, so we can't just grab
1602 * a critical section and access the PCPU data like on i386.
1603 * Instead, pin the thread and grab the PCPU lock to prevent
1604 * a preempting thread from using the same PCPU data.
1605 */
1606 sched_pin();
1607
1608 mtx_assert(PCPU_PTR(aim.qmap_lock), MA_NOTOWNED);
1609 pvo = PCPU_GET(aim.qmap_pvo);
1610
1611 mtx_lock(PCPU_PTR(aim.qmap_lock));
1612 pvo->pvo_pte.pa = moea64_calc_wimg(pa, pmap_page_get_memattr(m)) |
1613 (uint64_t)pa;
1614 moea64_pte_replace(pvo, MOEA64_PTE_INVALIDATE);
1615 isync();
1616
1617 return (PCPU_GET(qmap_addr));
1618 }
1619
1620 vm_offset_t
moea64_quick_enter_page_dmap(vm_page_t m)1621 moea64_quick_enter_page_dmap(vm_page_t m)
1622 {
1623
1624 return (PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)));
1625 }
1626
1627 void
moea64_quick_remove_page(vm_offset_t addr)1628 moea64_quick_remove_page(vm_offset_t addr)
1629 {
1630
1631 mtx_assert(PCPU_PTR(aim.qmap_lock), MA_OWNED);
1632 KASSERT(PCPU_GET(qmap_addr) == addr,
1633 ("moea64_quick_remove_page: invalid address"));
1634 mtx_unlock(PCPU_PTR(aim.qmap_lock));
1635 sched_unpin();
1636 }
1637
1638 bool
moea64_page_is_mapped(vm_page_t m)1639 moea64_page_is_mapped(vm_page_t m)
1640 {
1641 return (!LIST_EMPTY(&(m)->md.mdpg_pvoh));
1642 }
1643
1644 /*
1645 * Map the given physical page at the specified virtual address in the
1646 * target pmap with the protection requested. If specified the page
1647 * will be wired down.
1648 */
1649
1650 int
moea64_enter(pmap_t pmap,vm_offset_t va,vm_page_t m,vm_prot_t prot,u_int flags,int8_t psind)1651 moea64_enter(pmap_t pmap, vm_offset_t va, vm_page_t m,
1652 vm_prot_t prot, u_int flags, int8_t psind)
1653 {
1654 struct pvo_entry *pvo, *oldpvo, *tpvo;
1655 struct pvo_head *pvo_head;
1656 uint64_t pte_lo;
1657 int error;
1658 vm_paddr_t pa;
1659
1660 if ((m->oflags & VPO_UNMANAGED) == 0) {
1661 if ((flags & PMAP_ENTER_QUICK_LOCKED) == 0)
1662 VM_PAGE_OBJECT_BUSY_ASSERT(m);
1663 else
1664 VM_OBJECT_ASSERT_LOCKED(m->object);
1665 }
1666
1667 if (psind > 0)
1668 return (moea64_sp_enter(pmap, va, m, prot, flags, psind));
1669
1670 pvo = alloc_pvo_entry(0);
1671 if (pvo == NULL)
1672 return (KERN_RESOURCE_SHORTAGE);
1673 pvo->pvo_pmap = NULL; /* to be filled in later */
1674 pvo->pvo_pte.prot = prot;
1675
1676 pa = VM_PAGE_TO_PHYS(m);
1677 pte_lo = moea64_calc_wimg(pa, pmap_page_get_memattr(m));
1678 pvo->pvo_pte.pa = pa | pte_lo;
1679
1680 if ((flags & PMAP_ENTER_WIRED) != 0)
1681 pvo->pvo_vaddr |= PVO_WIRED;
1682
1683 if ((m->oflags & VPO_UNMANAGED) != 0 || !moea64_initialized) {
1684 pvo_head = NULL;
1685 } else {
1686 pvo_head = &m->md.mdpg_pvoh;
1687 pvo->pvo_vaddr |= PVO_MANAGED;
1688 }
1689
1690 PV_LOCK(pa);
1691 PMAP_LOCK(pmap);
1692 if (pvo->pvo_pmap == NULL)
1693 init_pvo_entry(pvo, pmap, va);
1694
1695 if (moea64_ps_enabled(pmap) &&
1696 (tpvo = moea64_pvo_find_va(pmap, va & ~HPT_SP_MASK)) != NULL &&
1697 PVO_IS_SP(tpvo)) {
1698 /* Demote SP before entering a regular page */
1699 CTR2(KTR_PMAP, "%s: demote before enter: va=%#jx",
1700 __func__, (uintmax_t)va);
1701 moea64_sp_demote_aligned(tpvo);
1702 }
1703
1704 if (prot & VM_PROT_WRITE)
1705 if (pmap_bootstrapped &&
1706 (m->oflags & VPO_UNMANAGED) == 0)
1707 vm_page_aflag_set(m, PGA_WRITEABLE);
1708
1709 error = moea64_pvo_enter(pvo, pvo_head, &oldpvo);
1710 if (error == EEXIST) {
1711 if (oldpvo->pvo_vaddr == pvo->pvo_vaddr &&
1712 oldpvo->pvo_pte.pa == pvo->pvo_pte.pa &&
1713 oldpvo->pvo_pte.prot == prot) {
1714 /* Identical mapping already exists */
1715 error = 0;
1716
1717 /* If not in page table, reinsert it */
1718 if (moea64_pte_synch(oldpvo) < 0) {
1719 STAT_MOEA64(moea64_pte_overflow--);
1720 moea64_pte_insert(oldpvo);
1721 }
1722
1723 /* Then just clean up and go home */
1724 PMAP_UNLOCK(pmap);
1725 PV_UNLOCK(pa);
1726 free_pvo_entry(pvo);
1727 pvo = NULL;
1728 goto out;
1729 } else {
1730 /* Otherwise, need to kill it first */
1731 KASSERT(oldpvo->pvo_pmap == pmap, ("pmap of old "
1732 "mapping does not match new mapping"));
1733 moea64_pvo_remove_from_pmap(oldpvo);
1734 moea64_pvo_enter(pvo, pvo_head, NULL);
1735 }
1736 }
1737 PMAP_UNLOCK(pmap);
1738 PV_UNLOCK(pa);
1739
1740 /* Free any dead pages */
1741 if (error == EEXIST) {
1742 moea64_pvo_remove_from_page(oldpvo);
1743 free_pvo_entry(oldpvo);
1744 }
1745
1746 out:
1747 /*
1748 * Flush the page from the instruction cache if this page is
1749 * mapped executable and cacheable.
1750 */
1751 if (pmap != kernel_pmap && (m->a.flags & PGA_EXECUTABLE) == 0 &&
1752 (pte_lo & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) {
1753 vm_page_aflag_set(m, PGA_EXECUTABLE);
1754 moea64_syncicache(pmap, va, pa, PAGE_SIZE);
1755 }
1756
1757 #if VM_NRESERVLEVEL > 0
1758 /*
1759 * Try to promote pages.
1760 *
1761 * If the VA of the entered page is not aligned with its PA,
1762 * don't try page promotion as it is not possible.
1763 * This reduces the number of promotion failures dramatically.
1764 *
1765 * Ignore VM_PROT_NO_PROMOTE unless PMAP_ENTER_QUICK_LOCKED.
1766 */
1767 if (moea64_ps_enabled(pmap) && pmap != kernel_pmap && pvo != NULL &&
1768 (pvo->pvo_vaddr & PVO_MANAGED) != 0 &&
1769 (va & HPT_SP_MASK) == (pa & HPT_SP_MASK) &&
1770 ((prot & VM_PROT_NO_PROMOTE) == 0 ||
1771 (flags & PMAP_ENTER_QUICK_LOCKED) == 0) &&
1772 (m->flags & PG_FICTITIOUS) == 0 &&
1773 vm_reserv_level_iffullpop(m) == 0)
1774 moea64_sp_promote(pmap, va, m);
1775 #endif
1776
1777 return (KERN_SUCCESS);
1778 }
1779
1780 static void
moea64_syncicache(pmap_t pmap,vm_offset_t va,vm_paddr_t pa,vm_size_t sz)1781 moea64_syncicache(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
1782 vm_size_t sz)
1783 {
1784
1785 /*
1786 * This is much trickier than on older systems because
1787 * we can't sync the icache on physical addresses directly
1788 * without a direct map. Instead we check a couple of cases
1789 * where the memory is already mapped in and, failing that,
1790 * use the same trick we use for page zeroing to create
1791 * a temporary mapping for this physical address.
1792 */
1793
1794 if (!pmap_bootstrapped) {
1795 /*
1796 * If PMAP is not bootstrapped, we are likely to be
1797 * in real mode.
1798 */
1799 __syncicache((void *)(uintptr_t)pa, sz);
1800 } else if (pmap == kernel_pmap) {
1801 __syncicache((void *)va, sz);
1802 } else if (hw_direct_map) {
1803 __syncicache((void *)(uintptr_t)PHYS_TO_DMAP(pa), sz);
1804 } else {
1805 /* Use the scratch page to set up a temp mapping */
1806
1807 mtx_lock(&moea64_scratchpage_mtx);
1808
1809 moea64_set_scratchpage_pa(1, pa & ~ADDR_POFF);
1810 __syncicache((void *)(moea64_scratchpage_va[1] +
1811 (va & ADDR_POFF)), sz);
1812
1813 mtx_unlock(&moea64_scratchpage_mtx);
1814 }
1815 }
1816
1817 /*
1818 * Maps a sequence of resident pages belonging to the same object.
1819 * The sequence begins with the given page m_start. This page is
1820 * mapped at the given virtual address start. Each subsequent page is
1821 * mapped at a virtual address that is offset from start by the same
1822 * amount as the page is offset from m_start within the object. The
1823 * last page in the sequence is the page with the largest offset from
1824 * m_start that can be mapped at a virtual address less than the given
1825 * virtual address end. Not every virtual page between start and end
1826 * is mapped; only those for which a resident page exists with the
1827 * corresponding offset from m_start are mapped.
1828 */
1829 void
moea64_enter_object(pmap_t pm,vm_offset_t start,vm_offset_t end,vm_page_t m_start,vm_prot_t prot)1830 moea64_enter_object(pmap_t pm, vm_offset_t start, vm_offset_t end,
1831 vm_page_t m_start, vm_prot_t prot)
1832 {
1833 struct pctrie_iter pages;
1834 vm_page_t m;
1835 vm_offset_t va;
1836 int8_t psind;
1837
1838 VM_OBJECT_ASSERT_LOCKED(m_start->object);
1839
1840 vm_page_iter_limit_init(&pages, m_start->object,
1841 m_start->pindex + atop(end - start));
1842 m = vm_radix_iter_lookup(&pages, m_start->pindex);
1843 while (m != NULL) {
1844 va = start + ptoa(m->pindex - m_start->pindex);
1845 if ((va & HPT_SP_MASK) == 0 && va + HPT_SP_SIZE <= end &&
1846 m->psind == 1 && moea64_ps_enabled(pm))
1847 psind = 1;
1848 else
1849 psind = 0;
1850 moea64_enter(pm, va, m, prot &
1851 (VM_PROT_READ | VM_PROT_EXECUTE),
1852 PMAP_ENTER_NOSLEEP | PMAP_ENTER_QUICK_LOCKED, psind);
1853 if (psind == 1)
1854 m = vm_radix_iter_jump(&pages, HPT_SP_SIZE / PAGE_SIZE);
1855 else
1856 m = vm_radix_iter_step(&pages);
1857 }
1858 }
1859
1860 void
moea64_enter_quick(pmap_t pm,vm_offset_t va,vm_page_t m,vm_prot_t prot)1861 moea64_enter_quick(pmap_t pm, vm_offset_t va, vm_page_t m,
1862 vm_prot_t prot)
1863 {
1864
1865 moea64_enter(pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE |
1866 VM_PROT_NO_PROMOTE), PMAP_ENTER_NOSLEEP | PMAP_ENTER_QUICK_LOCKED,
1867 0);
1868 }
1869
1870 vm_paddr_t
moea64_extract(pmap_t pm,vm_offset_t va)1871 moea64_extract(pmap_t pm, vm_offset_t va)
1872 {
1873 struct pvo_entry *pvo;
1874 vm_paddr_t pa;
1875
1876 PMAP_LOCK(pm);
1877 pvo = moea64_pvo_find_va(pm, va);
1878 if (pvo == NULL)
1879 pa = 0;
1880 else
1881 pa = PVO_PADDR(pvo) | (va - PVO_VADDR(pvo));
1882 PMAP_UNLOCK(pm);
1883
1884 return (pa);
1885 }
1886
1887 /*
1888 * Atomically extract and hold the physical page with the given
1889 * pmap and virtual address pair if that mapping permits the given
1890 * protection.
1891 */
1892 vm_page_t
moea64_extract_and_hold(pmap_t pmap,vm_offset_t va,vm_prot_t prot)1893 moea64_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1894 {
1895 struct pvo_entry *pvo;
1896 vm_page_t m;
1897
1898 m = NULL;
1899 PMAP_LOCK(pmap);
1900 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF);
1901 if (pvo != NULL && (pvo->pvo_pte.prot & prot) == prot) {
1902 m = PHYS_TO_VM_PAGE(PVO_PADDR(pvo));
1903 if (!vm_page_wire_mapped(m))
1904 m = NULL;
1905 }
1906 PMAP_UNLOCK(pmap);
1907 return (m);
1908 }
1909
1910 static void *
moea64_uma_page_alloc(uma_zone_t zone,vm_size_t bytes,int domain,uint8_t * flags,int wait)1911 moea64_uma_page_alloc(uma_zone_t zone, vm_size_t bytes, int domain,
1912 uint8_t *flags, int wait)
1913 {
1914 struct pvo_entry *pvo;
1915 vm_offset_t va;
1916 vm_page_t m;
1917 int needed_lock;
1918
1919 /*
1920 * This entire routine is a horrible hack to avoid bothering kmem
1921 * for new KVA addresses. Because this can get called from inside
1922 * kmem allocation routines, calling kmem for a new address here
1923 * can lead to multiply locking non-recursive mutexes.
1924 */
1925
1926 *flags = UMA_SLAB_PRIV;
1927 needed_lock = !PMAP_LOCKED(kernel_pmap);
1928
1929 m = vm_page_alloc_noobj_domain(domain, malloc2vm_flags(wait) |
1930 VM_ALLOC_WIRED);
1931 if (m == NULL)
1932 return (NULL);
1933
1934 va = VM_PAGE_TO_PHYS(m);
1935
1936 pvo = alloc_pvo_entry(1 /* bootstrap */);
1937
1938 pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE;
1939 pvo->pvo_pte.pa = VM_PAGE_TO_PHYS(m) | LPTE_M;
1940
1941 if (needed_lock)
1942 PMAP_LOCK(kernel_pmap);
1943
1944 init_pvo_entry(pvo, kernel_pmap, va);
1945 pvo->pvo_vaddr |= PVO_WIRED;
1946
1947 moea64_pvo_enter(pvo, NULL, NULL);
1948
1949 if (needed_lock)
1950 PMAP_UNLOCK(kernel_pmap);
1951
1952 return (void *)va;
1953 }
1954
1955 extern int elf32_nxstack;
1956
1957 void
moea64_init(void)1958 moea64_init(void)
1959 {
1960
1961 CTR0(KTR_PMAP, "moea64_init");
1962
1963 moea64_pvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry),
1964 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR,
1965 UMA_ZONE_VM | UMA_ZONE_NOFREE);
1966
1967 /*
1968 * Are large page mappings enabled?
1969 *
1970 * While HPT superpages are not better tested, leave it disabled by
1971 * default.
1972 */
1973 superpages_enabled = 0;
1974 TUNABLE_INT_FETCH("vm.pmap.superpages_enabled", &superpages_enabled);
1975 if (superpages_enabled) {
1976 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
1977 ("moea64_init: can't assign to pagesizes[1]"));
1978
1979 if (moea64_large_page_size == 0) {
1980 printf("mmu_oea64: HW does not support large pages. "
1981 "Disabling superpages...\n");
1982 superpages_enabled = 0;
1983 } else if (!moea64_has_lp_4k_16m) {
1984 printf("mmu_oea64: "
1985 "HW does not support mixed 4KB/16MB page sizes. "
1986 "Disabling superpages...\n");
1987 superpages_enabled = 0;
1988 } else
1989 pagesizes[1] = HPT_SP_SIZE;
1990 }
1991
1992 if (!hw_direct_map) {
1993 uma_zone_set_allocf(moea64_pvo_zone, moea64_uma_page_alloc);
1994 }
1995
1996 #ifdef COMPAT_FREEBSD32
1997 elf32_nxstack = 1;
1998 #endif
1999
2000 moea64_initialized = true;
2001 }
2002
2003 bool
moea64_is_referenced(vm_page_t m)2004 moea64_is_referenced(vm_page_t m)
2005 {
2006
2007 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2008 ("moea64_is_referenced: page %p is not managed", m));
2009
2010 return (moea64_query_bit(m, LPTE_REF));
2011 }
2012
2013 bool
moea64_is_modified(vm_page_t m)2014 moea64_is_modified(vm_page_t m)
2015 {
2016
2017 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2018 ("moea64_is_modified: page %p is not managed", m));
2019
2020 /*
2021 * If the page is not busied then this check is racy.
2022 */
2023 if (!pmap_page_is_write_mapped(m))
2024 return (false);
2025
2026 return (moea64_query_bit(m, LPTE_CHG));
2027 }
2028
2029 bool
moea64_is_prefaultable(pmap_t pmap,vm_offset_t va)2030 moea64_is_prefaultable(pmap_t pmap, vm_offset_t va)
2031 {
2032 struct pvo_entry *pvo;
2033 bool rv = true;
2034
2035 PMAP_LOCK(pmap);
2036 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF);
2037 if (pvo != NULL)
2038 rv = false;
2039 PMAP_UNLOCK(pmap);
2040 return (rv);
2041 }
2042
2043 void
moea64_clear_modify(vm_page_t m)2044 moea64_clear_modify(vm_page_t m)
2045 {
2046
2047 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2048 ("moea64_clear_modify: page %p is not managed", m));
2049 vm_page_assert_busied(m);
2050
2051 if (!pmap_page_is_write_mapped(m))
2052 return;
2053 moea64_clear_bit(m, LPTE_CHG);
2054 }
2055
2056 /*
2057 * Clear the write and modified bits in each of the given page's mappings.
2058 */
2059 void
moea64_remove_write(vm_page_t m)2060 moea64_remove_write(vm_page_t m)
2061 {
2062 struct pvo_entry *pvo;
2063 int64_t refchg, ret;
2064 pmap_t pmap;
2065
2066 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2067 ("moea64_remove_write: page %p is not managed", m));
2068 vm_page_assert_busied(m);
2069
2070 if (!pmap_page_is_write_mapped(m))
2071 return;
2072
2073 powerpc_sync();
2074 PV_PAGE_LOCK(m);
2075 refchg = 0;
2076 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2077 pmap = pvo->pvo_pmap;
2078 PMAP_LOCK(pmap);
2079 if (!(pvo->pvo_vaddr & PVO_DEAD) &&
2080 (pvo->pvo_pte.prot & VM_PROT_WRITE)) {
2081 if (PVO_IS_SP(pvo)) {
2082 CTR1(KTR_PMAP, "%s: demote before remwr",
2083 __func__);
2084 moea64_sp_demote(pvo);
2085 }
2086 pvo->pvo_pte.prot &= ~VM_PROT_WRITE;
2087 ret = moea64_pte_replace(pvo, MOEA64_PTE_PROT_UPDATE);
2088 if (ret < 0)
2089 ret = LPTE_CHG;
2090 refchg |= ret;
2091 if (pvo->pvo_pmap == kernel_pmap)
2092 isync();
2093 }
2094 PMAP_UNLOCK(pmap);
2095 }
2096 if ((refchg | atomic_readandclear_32(&m->md.mdpg_attrs)) & LPTE_CHG)
2097 vm_page_dirty(m);
2098 vm_page_aflag_clear(m, PGA_WRITEABLE);
2099 PV_PAGE_UNLOCK(m);
2100 }
2101
2102 /*
2103 * moea64_ts_referenced:
2104 *
2105 * Return a count of reference bits for a page, clearing those bits.
2106 * It is not necessary for every reference bit to be cleared, but it
2107 * is necessary that 0 only be returned when there are truly no
2108 * reference bits set.
2109 *
2110 * XXX: The exact number of bits to check and clear is a matter that
2111 * should be tested and standardized at some point in the future for
2112 * optimal aging of shared pages.
2113 */
2114 int
moea64_ts_referenced(vm_page_t m)2115 moea64_ts_referenced(vm_page_t m)
2116 {
2117
2118 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2119 ("moea64_ts_referenced: page %p is not managed", m));
2120 return (moea64_clear_bit(m, LPTE_REF));
2121 }
2122
2123 /*
2124 * Modify the WIMG settings of all mappings for a page.
2125 */
2126 void
moea64_page_set_memattr(vm_page_t m,vm_memattr_t ma)2127 moea64_page_set_memattr(vm_page_t m, vm_memattr_t ma)
2128 {
2129 struct pvo_entry *pvo;
2130 int64_t refchg;
2131 pmap_t pmap;
2132 uint64_t lo;
2133
2134 CTR3(KTR_PMAP, "%s: pa=%#jx, ma=%#x",
2135 __func__, (uintmax_t)VM_PAGE_TO_PHYS(m), ma);
2136
2137 if ((m->oflags & VPO_UNMANAGED) != 0) {
2138 m->md.mdpg_cache_attrs = ma;
2139 return;
2140 }
2141
2142 lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), ma);
2143
2144 PV_PAGE_LOCK(m);
2145 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2146 pmap = pvo->pvo_pmap;
2147 PMAP_LOCK(pmap);
2148 if (!(pvo->pvo_vaddr & PVO_DEAD)) {
2149 if (PVO_IS_SP(pvo)) {
2150 CTR1(KTR_PMAP,
2151 "%s: demote before set_memattr", __func__);
2152 moea64_sp_demote(pvo);
2153 }
2154 pvo->pvo_pte.pa &= ~LPTE_WIMG;
2155 pvo->pvo_pte.pa |= lo;
2156 refchg = moea64_pte_replace(pvo, MOEA64_PTE_INVALIDATE);
2157 if (refchg < 0)
2158 refchg = (pvo->pvo_pte.prot & VM_PROT_WRITE) ?
2159 LPTE_CHG : 0;
2160 if ((pvo->pvo_vaddr & PVO_MANAGED) &&
2161 (pvo->pvo_pte.prot & VM_PROT_WRITE)) {
2162 refchg |=
2163 atomic_readandclear_32(&m->md.mdpg_attrs);
2164 if (refchg & LPTE_CHG)
2165 vm_page_dirty(m);
2166 if (refchg & LPTE_REF)
2167 vm_page_aflag_set(m, PGA_REFERENCED);
2168 }
2169 if (pvo->pvo_pmap == kernel_pmap)
2170 isync();
2171 }
2172 PMAP_UNLOCK(pmap);
2173 }
2174 m->md.mdpg_cache_attrs = ma;
2175 PV_PAGE_UNLOCK(m);
2176 }
2177
2178 /*
2179 * Map a wired page into kernel virtual address space.
2180 */
2181 void
moea64_kenter_attr(vm_offset_t va,vm_paddr_t pa,vm_memattr_t ma)2182 moea64_kenter_attr(vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma)
2183 {
2184 int error;
2185 struct pvo_entry *pvo, *oldpvo;
2186
2187 do {
2188 pvo = alloc_pvo_entry(0);
2189 if (pvo == NULL)
2190 vm_wait(NULL);
2191 } while (pvo == NULL);
2192 pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE | VM_PROT_EXECUTE;
2193 pvo->pvo_pte.pa = (pa & ~ADDR_POFF) | moea64_calc_wimg(pa, ma);
2194 pvo->pvo_vaddr |= PVO_WIRED;
2195
2196 PMAP_LOCK(kernel_pmap);
2197 oldpvo = moea64_pvo_find_va(kernel_pmap, va);
2198 if (oldpvo != NULL)
2199 moea64_pvo_remove_from_pmap(oldpvo);
2200 init_pvo_entry(pvo, kernel_pmap, va);
2201 error = moea64_pvo_enter(pvo, NULL, NULL);
2202 PMAP_UNLOCK(kernel_pmap);
2203
2204 /* Free any dead pages */
2205 if (oldpvo != NULL) {
2206 moea64_pvo_remove_from_page(oldpvo);
2207 free_pvo_entry(oldpvo);
2208 }
2209
2210 if (error != 0)
2211 panic("moea64_kenter: failed to enter va %#zx pa %#jx: %d", va,
2212 (uintmax_t)pa, error);
2213 }
2214
2215 void
moea64_kenter(vm_offset_t va,vm_paddr_t pa)2216 moea64_kenter(vm_offset_t va, vm_paddr_t pa)
2217 {
2218
2219 moea64_kenter_attr(va, pa, VM_MEMATTR_DEFAULT);
2220 }
2221
2222 /*
2223 * Extract the physical page address associated with the given kernel virtual
2224 * address.
2225 */
2226 vm_paddr_t
moea64_kextract(vm_offset_t va)2227 moea64_kextract(vm_offset_t va)
2228 {
2229 struct pvo_entry *pvo;
2230 vm_paddr_t pa;
2231
2232 /*
2233 * Shortcut the direct-mapped case when applicable. We never put
2234 * anything but 1:1 (or 62-bit aliased) mappings below
2235 * VM_MIN_KERNEL_ADDRESS.
2236 */
2237 if (va < VM_MIN_KERNEL_ADDRESS)
2238 return (va & ~DMAP_BASE_ADDRESS);
2239
2240 PMAP_LOCK(kernel_pmap);
2241 pvo = moea64_pvo_find_va(kernel_pmap, va);
2242 KASSERT(pvo != NULL, ("moea64_kextract: no addr found for %#" PRIxPTR,
2243 va));
2244 pa = PVO_PADDR(pvo) | (va - PVO_VADDR(pvo));
2245 PMAP_UNLOCK(kernel_pmap);
2246 return (pa);
2247 }
2248
2249 /*
2250 * Remove a wired page from kernel virtual address space.
2251 */
2252 void
moea64_kremove(vm_offset_t va)2253 moea64_kremove(vm_offset_t va)
2254 {
2255 moea64_remove(kernel_pmap, va, va + PAGE_SIZE);
2256 }
2257
2258 /*
2259 * Provide a kernel pointer corresponding to a given userland pointer.
2260 * The returned pointer is valid until the next time this function is
2261 * called in this thread. This is used internally in copyin/copyout.
2262 */
2263 static int
moea64_map_user_ptr(pmap_t pm,volatile const void * uaddr,void ** kaddr,size_t ulen,size_t * klen)2264 moea64_map_user_ptr(pmap_t pm, volatile const void *uaddr,
2265 void **kaddr, size_t ulen, size_t *klen)
2266 {
2267 size_t l;
2268 #ifdef __powerpc64__
2269 struct slb *slb;
2270 #endif
2271 register_t slbv;
2272
2273 *kaddr = (char *)USER_ADDR + ((uintptr_t)uaddr & ~SEGMENT_MASK);
2274 l = ((char *)USER_ADDR + SEGMENT_LENGTH) - (char *)(*kaddr);
2275 if (l > ulen)
2276 l = ulen;
2277 if (klen)
2278 *klen = l;
2279 else if (l != ulen)
2280 return (EFAULT);
2281
2282 #ifdef __powerpc64__
2283 /* Try lockless look-up first */
2284 slb = user_va_to_slb_entry(pm, (vm_offset_t)uaddr);
2285
2286 if (slb == NULL) {
2287 /* If it isn't there, we need to pre-fault the VSID */
2288 PMAP_LOCK(pm);
2289 slbv = va_to_vsid(pm, (vm_offset_t)uaddr) << SLBV_VSID_SHIFT;
2290 PMAP_UNLOCK(pm);
2291 } else {
2292 slbv = slb->slbv;
2293 }
2294
2295 /* Mark segment no-execute */
2296 slbv |= SLBV_N;
2297 #else
2298 slbv = va_to_vsid(pm, (vm_offset_t)uaddr);
2299
2300 /* Mark segment no-execute */
2301 slbv |= SR_N;
2302 #endif
2303
2304 /* If we have already set this VSID, we can just return */
2305 if (curthread->td_pcb->pcb_cpu.aim.usr_vsid == slbv)
2306 return (0);
2307
2308 __asm __volatile("isync");
2309 curthread->td_pcb->pcb_cpu.aim.usr_segm =
2310 (uintptr_t)uaddr >> ADDR_SR_SHFT;
2311 curthread->td_pcb->pcb_cpu.aim.usr_vsid = slbv;
2312 #ifdef __powerpc64__
2313 __asm __volatile ("slbie %0; slbmte %1, %2; isync" ::
2314 "r"(USER_ADDR), "r"(slbv), "r"(USER_SLB_SLBE));
2315 #else
2316 __asm __volatile("mtsr %0,%1; isync" :: "n"(USER_SR), "r"(slbv));
2317 #endif
2318
2319 return (0);
2320 }
2321
2322 /*
2323 * Figure out where a given kernel pointer (usually in a fault) points
2324 * to from the VM's perspective, potentially remapping into userland's
2325 * address space.
2326 */
2327 static int
moea64_decode_kernel_ptr(vm_offset_t addr,int * is_user,vm_offset_t * decoded_addr)2328 moea64_decode_kernel_ptr(vm_offset_t addr, int *is_user,
2329 vm_offset_t *decoded_addr)
2330 {
2331 vm_offset_t user_sr;
2332
2333 if ((addr >> ADDR_SR_SHFT) == (USER_ADDR >> ADDR_SR_SHFT)) {
2334 user_sr = curthread->td_pcb->pcb_cpu.aim.usr_segm;
2335 addr &= ADDR_PIDX | ADDR_POFF;
2336 addr |= user_sr << ADDR_SR_SHFT;
2337 *decoded_addr = addr;
2338 *is_user = 1;
2339 } else {
2340 *decoded_addr = addr;
2341 *is_user = 0;
2342 }
2343
2344 return (0);
2345 }
2346
2347 /*
2348 * Map a range of physical addresses into kernel virtual address space.
2349 *
2350 * The value passed in *virt is a suggested virtual address for the mapping.
2351 * Architectures which can support a direct-mapped physical to virtual region
2352 * can return the appropriate address within that region, leaving '*virt'
2353 * unchanged. Other architectures should map the pages starting at '*virt' and
2354 * update '*virt' with the first usable address after the mapped region.
2355 */
2356 vm_offset_t
moea64_map(vm_offset_t * virt,vm_paddr_t pa_start,vm_paddr_t pa_end,int prot)2357 moea64_map(vm_offset_t *virt, vm_paddr_t pa_start,
2358 vm_paddr_t pa_end, int prot)
2359 {
2360 vm_offset_t sva, va;
2361
2362 if (hw_direct_map) {
2363 /*
2364 * Check if every page in the region is covered by the direct
2365 * map. The direct map covers all of physical memory. Use
2366 * moea64_calc_wimg() as a shortcut to see if the page is in
2367 * physical memory as a way to see if the direct map covers it.
2368 */
2369 for (va = pa_start; va < pa_end; va += PAGE_SIZE)
2370 if (moea64_calc_wimg(va, VM_MEMATTR_DEFAULT) != LPTE_M)
2371 break;
2372 if (va == pa_end)
2373 return (PHYS_TO_DMAP(pa_start));
2374 }
2375 sva = *virt;
2376 va = sva;
2377 /* XXX respect prot argument */
2378 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE)
2379 moea64_kenter(va, pa_start);
2380 *virt = va;
2381
2382 return (sva);
2383 }
2384
2385 /*
2386 * Returns true if the pmap's pv is one of the first
2387 * 16 pvs linked to from this page. This count may
2388 * be changed upwards or downwards in the future; it
2389 * is only necessary that true be returned for a small
2390 * subset of pmaps for proper page aging.
2391 */
2392 bool
moea64_page_exists_quick(pmap_t pmap,vm_page_t m)2393 moea64_page_exists_quick(pmap_t pmap, vm_page_t m)
2394 {
2395 int loops;
2396 struct pvo_entry *pvo;
2397 bool rv;
2398
2399 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2400 ("moea64_page_exists_quick: page %p is not managed", m));
2401 loops = 0;
2402 rv = false;
2403 PV_PAGE_LOCK(m);
2404 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2405 if (!(pvo->pvo_vaddr & PVO_DEAD) && pvo->pvo_pmap == pmap) {
2406 rv = true;
2407 break;
2408 }
2409 if (++loops >= 16)
2410 break;
2411 }
2412 PV_PAGE_UNLOCK(m);
2413 return (rv);
2414 }
2415
2416 void
moea64_page_init(vm_page_t m)2417 moea64_page_init(vm_page_t m)
2418 {
2419
2420 m->md.mdpg_attrs = 0;
2421 m->md.mdpg_cache_attrs = VM_MEMATTR_DEFAULT;
2422 LIST_INIT(&m->md.mdpg_pvoh);
2423 }
2424
2425 /*
2426 * Return the number of managed mappings to the given physical page
2427 * that are wired.
2428 */
2429 int
moea64_page_wired_mappings(vm_page_t m)2430 moea64_page_wired_mappings(vm_page_t m)
2431 {
2432 struct pvo_entry *pvo;
2433 int count;
2434
2435 count = 0;
2436 if ((m->oflags & VPO_UNMANAGED) != 0)
2437 return (count);
2438 PV_PAGE_LOCK(m);
2439 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink)
2440 if ((pvo->pvo_vaddr & (PVO_DEAD | PVO_WIRED)) == PVO_WIRED)
2441 count++;
2442 PV_PAGE_UNLOCK(m);
2443 return (count);
2444 }
2445
2446 static uintptr_t moea64_vsidcontext;
2447
2448 uintptr_t
moea64_get_unique_vsid(void)2449 moea64_get_unique_vsid(void) {
2450 u_int entropy;
2451 register_t hash;
2452 uint32_t mask;
2453 int i;
2454
2455 entropy = 0;
2456 __asm __volatile("mftb %0" : "=r"(entropy));
2457
2458 mtx_lock(&moea64_slb_mutex);
2459 for (i = 0; i < NVSIDS; i += VSID_NBPW) {
2460 u_int n;
2461
2462 /*
2463 * Create a new value by multiplying by a prime and adding in
2464 * entropy from the timebase register. This is to make the
2465 * VSID more random so that the PT hash function collides
2466 * less often. (Note that the prime casues gcc to do shifts
2467 * instead of a multiply.)
2468 */
2469 moea64_vsidcontext = (moea64_vsidcontext * 0x1105) + entropy;
2470 hash = moea64_vsidcontext & (NVSIDS - 1);
2471 if (hash == 0) /* 0 is special, avoid it */
2472 continue;
2473 n = hash >> 5;
2474 mask = 1 << (hash & (VSID_NBPW - 1));
2475 hash = (moea64_vsidcontext & VSID_HASHMASK);
2476 if (moea64_vsid_bitmap[n] & mask) { /* collision? */
2477 /* anything free in this bucket? */
2478 if (moea64_vsid_bitmap[n] == 0xffffffff) {
2479 entropy = (moea64_vsidcontext >> 20);
2480 continue;
2481 }
2482 i = ffs(~moea64_vsid_bitmap[n]) - 1;
2483 mask = 1 << i;
2484 hash &= rounddown2(VSID_HASHMASK, VSID_NBPW);
2485 hash |= i;
2486 }
2487 if (hash == VSID_VRMA) /* also special, avoid this too */
2488 continue;
2489 KASSERT(!(moea64_vsid_bitmap[n] & mask),
2490 ("Allocating in-use VSID %#zx\n", hash));
2491 moea64_vsid_bitmap[n] |= mask;
2492 mtx_unlock(&moea64_slb_mutex);
2493 return (hash);
2494 }
2495
2496 mtx_unlock(&moea64_slb_mutex);
2497 panic("%s: out of segments",__func__);
2498 }
2499
2500 #ifdef __powerpc64__
2501 int
moea64_pinit(pmap_t pmap)2502 moea64_pinit(pmap_t pmap)
2503 {
2504
2505 RB_INIT(&pmap->pmap_pvo);
2506
2507 pmap->pm_slb_tree_root = slb_alloc_tree();
2508 pmap->pm_slb = slb_alloc_user_cache();
2509 pmap->pm_slb_len = 0;
2510
2511 return (1);
2512 }
2513 #else
2514 int
moea64_pinit(pmap_t pmap)2515 moea64_pinit(pmap_t pmap)
2516 {
2517 int i;
2518 uint32_t hash;
2519
2520 RB_INIT(&pmap->pmap_pvo);
2521
2522 if (pmap_bootstrapped)
2523 pmap->pmap_phys = (pmap_t)moea64_kextract((vm_offset_t)pmap);
2524 else
2525 pmap->pmap_phys = pmap;
2526
2527 /*
2528 * Allocate some segment registers for this pmap.
2529 */
2530 hash = moea64_get_unique_vsid();
2531
2532 for (i = 0; i < 16; i++)
2533 pmap->pm_sr[i] = VSID_MAKE(i, hash);
2534
2535 KASSERT(pmap->pm_sr[0] != 0, ("moea64_pinit: pm_sr[0] = 0"));
2536
2537 return (1);
2538 }
2539 #endif
2540
2541 /*
2542 * Initialize the pmap associated with process 0.
2543 */
2544 void
moea64_pinit0(pmap_t pm)2545 moea64_pinit0(pmap_t pm)
2546 {
2547
2548 PMAP_LOCK_INIT(pm);
2549 moea64_pinit(pm);
2550 bzero(&pm->pm_stats, sizeof(pm->pm_stats));
2551 }
2552
2553 /*
2554 * Set the physical protection on the specified range of this map as requested.
2555 */
2556 static void
moea64_pvo_protect(pmap_t pm,struct pvo_entry * pvo,vm_prot_t prot)2557 moea64_pvo_protect( pmap_t pm, struct pvo_entry *pvo, vm_prot_t prot)
2558 {
2559 struct vm_page *pg;
2560 vm_prot_t oldprot;
2561 int32_t refchg;
2562
2563 PMAP_LOCK_ASSERT(pm, MA_OWNED);
2564
2565 /*
2566 * Change the protection of the page.
2567 */
2568 oldprot = pvo->pvo_pte.prot;
2569 pvo->pvo_pte.prot = prot;
2570 pg = PHYS_TO_VM_PAGE(PVO_PADDR(pvo));
2571
2572 /*
2573 * If the PVO is in the page table, update mapping
2574 */
2575 refchg = moea64_pte_replace(pvo, MOEA64_PTE_PROT_UPDATE);
2576 if (refchg < 0)
2577 refchg = (oldprot & VM_PROT_WRITE) ? LPTE_CHG : 0;
2578
2579 if (pm != kernel_pmap && pg != NULL &&
2580 (pg->a.flags & PGA_EXECUTABLE) == 0 &&
2581 (pvo->pvo_pte.pa & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) {
2582 if ((pg->oflags & VPO_UNMANAGED) == 0)
2583 vm_page_aflag_set(pg, PGA_EXECUTABLE);
2584 moea64_syncicache(pm, PVO_VADDR(pvo),
2585 PVO_PADDR(pvo), PAGE_SIZE);
2586 }
2587
2588 /*
2589 * Update vm about the REF/CHG bits if the page is managed and we have
2590 * removed write access.
2591 */
2592 if (pg != NULL && (pvo->pvo_vaddr & PVO_MANAGED) &&
2593 (oldprot & VM_PROT_WRITE)) {
2594 refchg |= atomic_readandclear_32(&pg->md.mdpg_attrs);
2595 if (refchg & LPTE_CHG)
2596 vm_page_dirty(pg);
2597 if (refchg & LPTE_REF)
2598 vm_page_aflag_set(pg, PGA_REFERENCED);
2599 }
2600 }
2601
2602 void
moea64_protect(pmap_t pm,vm_offset_t sva,vm_offset_t eva,vm_prot_t prot)2603 moea64_protect(pmap_t pm, vm_offset_t sva, vm_offset_t eva,
2604 vm_prot_t prot)
2605 {
2606 struct pvo_entry *pvo, key;
2607
2608 CTR4(KTR_PMAP, "moea64_protect: pm=%p sva=%#x eva=%#x prot=%#x", pm,
2609 sva, eva, prot);
2610
2611 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap,
2612 ("moea64_protect: non current pmap"));
2613
2614 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
2615 moea64_remove(pm, sva, eva);
2616 return;
2617 }
2618
2619 PMAP_LOCK(pm);
2620 key.pvo_vaddr = sva;
2621 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key);
2622 pvo != NULL && PVO_VADDR(pvo) < eva;
2623 pvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo)) {
2624 if (PVO_IS_SP(pvo)) {
2625 if (moea64_sp_pvo_in_range(pvo, sva, eva)) {
2626 pvo = moea64_sp_protect(pvo, prot);
2627 continue;
2628 } else {
2629 CTR1(KTR_PMAP, "%s: demote before protect",
2630 __func__);
2631 moea64_sp_demote(pvo);
2632 }
2633 }
2634 moea64_pvo_protect(pm, pvo, prot);
2635 }
2636 PMAP_UNLOCK(pm);
2637 }
2638
2639 /*
2640 * Map a list of wired pages into kernel virtual address space. This is
2641 * intended for temporary mappings which do not need page modification or
2642 * references recorded. Existing mappings in the region are overwritten.
2643 */
2644 void
moea64_qenter(vm_offset_t va,vm_page_t * m,int count)2645 moea64_qenter(vm_offset_t va, vm_page_t *m, int count)
2646 {
2647 while (count-- > 0) {
2648 moea64_kenter(va, VM_PAGE_TO_PHYS(*m));
2649 va += PAGE_SIZE;
2650 m++;
2651 }
2652 }
2653
2654 /*
2655 * Remove page mappings from kernel virtual address space. Intended for
2656 * temporary mappings entered by moea64_qenter.
2657 */
2658 void
moea64_qremove(vm_offset_t va,int count)2659 moea64_qremove(vm_offset_t va, int count)
2660 {
2661 while (count-- > 0) {
2662 moea64_kremove(va);
2663 va += PAGE_SIZE;
2664 }
2665 }
2666
2667 void
moea64_release_vsid(uint64_t vsid)2668 moea64_release_vsid(uint64_t vsid)
2669 {
2670 int idx, mask;
2671
2672 mtx_lock(&moea64_slb_mutex);
2673 idx = vsid & (NVSIDS-1);
2674 mask = 1 << (idx % VSID_NBPW);
2675 idx /= VSID_NBPW;
2676 KASSERT(moea64_vsid_bitmap[idx] & mask,
2677 ("Freeing unallocated VSID %#jx", vsid));
2678 moea64_vsid_bitmap[idx] &= ~mask;
2679 mtx_unlock(&moea64_slb_mutex);
2680 }
2681
2682 void
moea64_release(pmap_t pmap)2683 moea64_release(pmap_t pmap)
2684 {
2685
2686 /*
2687 * Free segment registers' VSIDs
2688 */
2689 #ifdef __powerpc64__
2690 slb_free_tree(pmap);
2691 slb_free_user_cache(pmap->pm_slb);
2692 #else
2693 KASSERT(pmap->pm_sr[0] != 0, ("moea64_release: pm_sr[0] = 0"));
2694
2695 moea64_release_vsid(VSID_TO_HASH(pmap->pm_sr[0]));
2696 #endif
2697 }
2698
2699 /*
2700 * Remove all pages mapped by the specified pmap
2701 */
2702 void
moea64_remove_pages(pmap_t pm)2703 moea64_remove_pages(pmap_t pm)
2704 {
2705 struct pvo_entry *pvo, *tpvo;
2706 struct pvo_dlist tofree;
2707
2708 SLIST_INIT(&tofree);
2709
2710 PMAP_LOCK(pm);
2711 RB_FOREACH_SAFE(pvo, pvo_tree, &pm->pmap_pvo, tpvo) {
2712 if (pvo->pvo_vaddr & PVO_WIRED)
2713 continue;
2714
2715 /*
2716 * For locking reasons, remove this from the page table and
2717 * pmap, but save delinking from the vm_page for a second
2718 * pass
2719 */
2720 moea64_pvo_remove_from_pmap(pvo);
2721 SLIST_INSERT_HEAD(&tofree, pvo, pvo_dlink);
2722 }
2723 PMAP_UNLOCK(pm);
2724
2725 while (!SLIST_EMPTY(&tofree)) {
2726 pvo = SLIST_FIRST(&tofree);
2727 SLIST_REMOVE_HEAD(&tofree, pvo_dlink);
2728 moea64_pvo_remove_from_page(pvo);
2729 free_pvo_entry(pvo);
2730 }
2731 }
2732
2733 static void
moea64_remove_locked(pmap_t pm,vm_offset_t sva,vm_offset_t eva,struct pvo_dlist * tofree)2734 moea64_remove_locked(pmap_t pm, vm_offset_t sva, vm_offset_t eva,
2735 struct pvo_dlist *tofree)
2736 {
2737 struct pvo_entry *pvo, *tpvo, key;
2738
2739 PMAP_LOCK_ASSERT(pm, MA_OWNED);
2740
2741 key.pvo_vaddr = sva;
2742 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key);
2743 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) {
2744 if (PVO_IS_SP(pvo)) {
2745 if (moea64_sp_pvo_in_range(pvo, sva, eva)) {
2746 tpvo = moea64_sp_remove(pvo, tofree);
2747 continue;
2748 } else {
2749 CTR1(KTR_PMAP, "%s: demote before remove",
2750 __func__);
2751 moea64_sp_demote(pvo);
2752 }
2753 }
2754 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo);
2755
2756 /*
2757 * For locking reasons, remove this from the page table and
2758 * pmap, but save delinking from the vm_page for a second
2759 * pass
2760 */
2761 moea64_pvo_remove_from_pmap(pvo);
2762 SLIST_INSERT_HEAD(tofree, pvo, pvo_dlink);
2763 }
2764 }
2765
2766 /*
2767 * Remove the given range of addresses from the specified map.
2768 */
2769 void
moea64_remove(pmap_t pm,vm_offset_t sva,vm_offset_t eva)2770 moea64_remove(pmap_t pm, vm_offset_t sva, vm_offset_t eva)
2771 {
2772 struct pvo_entry *pvo;
2773 struct pvo_dlist tofree;
2774
2775 /*
2776 * Perform an unsynchronized read. This is, however, safe.
2777 */
2778 if (pm->pm_stats.resident_count == 0)
2779 return;
2780
2781 SLIST_INIT(&tofree);
2782 PMAP_LOCK(pm);
2783 moea64_remove_locked(pm, sva, eva, &tofree);
2784 PMAP_UNLOCK(pm);
2785
2786 while (!SLIST_EMPTY(&tofree)) {
2787 pvo = SLIST_FIRST(&tofree);
2788 SLIST_REMOVE_HEAD(&tofree, pvo_dlink);
2789 moea64_pvo_remove_from_page(pvo);
2790 free_pvo_entry(pvo);
2791 }
2792 }
2793
2794 /*
2795 * Remove physical page from all pmaps in which it resides. moea64_pvo_remove()
2796 * will reflect changes in pte's back to the vm_page.
2797 */
2798 void
moea64_remove_all(vm_page_t m)2799 moea64_remove_all(vm_page_t m)
2800 {
2801 struct pvo_entry *pvo, *next_pvo;
2802 struct pvo_head freequeue;
2803 int wasdead;
2804 pmap_t pmap;
2805
2806 LIST_INIT(&freequeue);
2807
2808 PV_PAGE_LOCK(m);
2809 LIST_FOREACH_SAFE(pvo, vm_page_to_pvoh(m), pvo_vlink, next_pvo) {
2810 pmap = pvo->pvo_pmap;
2811 PMAP_LOCK(pmap);
2812 wasdead = (pvo->pvo_vaddr & PVO_DEAD);
2813 if (!wasdead) {
2814 if (PVO_IS_SP(pvo)) {
2815 CTR1(KTR_PMAP, "%s: demote before remove_all",
2816 __func__);
2817 moea64_sp_demote(pvo);
2818 }
2819 moea64_pvo_remove_from_pmap(pvo);
2820 }
2821 moea64_pvo_remove_from_page_locked(pvo, m);
2822 if (!wasdead)
2823 LIST_INSERT_HEAD(&freequeue, pvo, pvo_vlink);
2824 PMAP_UNLOCK(pmap);
2825
2826 }
2827 KASSERT(!pmap_page_is_mapped(m), ("Page still has mappings"));
2828 KASSERT((m->a.flags & PGA_WRITEABLE) == 0, ("Page still writable"));
2829 PV_PAGE_UNLOCK(m);
2830
2831 /* Clean up UMA allocations */
2832 LIST_FOREACH_SAFE(pvo, &freequeue, pvo_vlink, next_pvo)
2833 free_pvo_entry(pvo);
2834 }
2835
2836 /*
2837 * Allocate a physical page of memory directly from the phys_avail map.
2838 * Can only be called from moea64_bootstrap before avail start and end are
2839 * calculated.
2840 */
2841 vm_offset_t
moea64_bootstrap_alloc(vm_size_t size,vm_size_t align)2842 moea64_bootstrap_alloc(vm_size_t size, vm_size_t align)
2843 {
2844 vm_offset_t s, e;
2845 int i, j;
2846
2847 size = round_page(size);
2848 for (i = 0; phys_avail[i + 1] != 0; i += 2) {
2849 if (align != 0)
2850 s = roundup2(phys_avail[i], align);
2851 else
2852 s = phys_avail[i];
2853 e = s + size;
2854
2855 if (s < phys_avail[i] || e > phys_avail[i + 1])
2856 continue;
2857
2858 if (s + size > platform_real_maxaddr())
2859 continue;
2860
2861 if (s == phys_avail[i]) {
2862 phys_avail[i] += size;
2863 } else if (e == phys_avail[i + 1]) {
2864 phys_avail[i + 1] -= size;
2865 } else {
2866 for (j = phys_avail_count * 2; j > i; j -= 2) {
2867 phys_avail[j] = phys_avail[j - 2];
2868 phys_avail[j + 1] = phys_avail[j - 1];
2869 }
2870
2871 phys_avail[i + 3] = phys_avail[i + 1];
2872 phys_avail[i + 1] = s;
2873 phys_avail[i + 2] = e;
2874 phys_avail_count++;
2875 }
2876
2877 return (s);
2878 }
2879 panic("moea64_bootstrap_alloc: could not allocate memory");
2880 }
2881
2882 static int
moea64_pvo_enter(struct pvo_entry * pvo,struct pvo_head * pvo_head,struct pvo_entry ** oldpvop)2883 moea64_pvo_enter(struct pvo_entry *pvo, struct pvo_head *pvo_head,
2884 struct pvo_entry **oldpvop)
2885 {
2886 struct pvo_entry *old_pvo;
2887 int err;
2888
2889 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED);
2890
2891 STAT_MOEA64(moea64_pvo_enter_calls++);
2892
2893 /*
2894 * Add to pmap list
2895 */
2896 old_pvo = RB_INSERT(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo);
2897
2898 if (old_pvo != NULL) {
2899 if (oldpvop != NULL)
2900 *oldpvop = old_pvo;
2901 return (EEXIST);
2902 }
2903
2904 if (pvo_head != NULL) {
2905 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink);
2906 }
2907
2908 if (pvo->pvo_vaddr & PVO_WIRED)
2909 pvo->pvo_pmap->pm_stats.wired_count++;
2910 pvo->pvo_pmap->pm_stats.resident_count++;
2911
2912 /*
2913 * Insert it into the hardware page table
2914 */
2915 err = moea64_pte_insert(pvo);
2916 if (err != 0) {
2917 panic("moea64_pvo_enter: overflow");
2918 }
2919
2920 STAT_MOEA64(moea64_pvo_entries++);
2921
2922 if (pvo->pvo_pmap == kernel_pmap)
2923 isync();
2924
2925 #ifdef __powerpc64__
2926 /*
2927 * Make sure all our bootstrap mappings are in the SLB as soon
2928 * as virtual memory is switched on.
2929 */
2930 if (!pmap_bootstrapped)
2931 moea64_bootstrap_slb_prefault(PVO_VADDR(pvo),
2932 pvo->pvo_vaddr & PVO_LARGE);
2933 #endif
2934
2935 return (0);
2936 }
2937
2938 static void
moea64_pvo_remove_from_pmap(struct pvo_entry * pvo)2939 moea64_pvo_remove_from_pmap(struct pvo_entry *pvo)
2940 {
2941 struct vm_page *pg;
2942 int32_t refchg;
2943
2944 KASSERT(pvo->pvo_pmap != NULL, ("Trying to remove PVO with no pmap"));
2945 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED);
2946 KASSERT(!(pvo->pvo_vaddr & PVO_DEAD), ("Trying to remove dead PVO"));
2947
2948 /*
2949 * If there is an active pte entry, we need to deactivate it
2950 */
2951 refchg = moea64_pte_unset(pvo);
2952 if (refchg < 0) {
2953 /*
2954 * If it was evicted from the page table, be pessimistic and
2955 * dirty the page.
2956 */
2957 if (pvo->pvo_pte.prot & VM_PROT_WRITE)
2958 refchg = LPTE_CHG;
2959 else
2960 refchg = 0;
2961 }
2962
2963 /*
2964 * Update our statistics.
2965 */
2966 pvo->pvo_pmap->pm_stats.resident_count--;
2967 if (pvo->pvo_vaddr & PVO_WIRED)
2968 pvo->pvo_pmap->pm_stats.wired_count--;
2969
2970 /*
2971 * Remove this PVO from the pmap list.
2972 */
2973 RB_REMOVE(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo);
2974
2975 /*
2976 * Mark this for the next sweep
2977 */
2978 pvo->pvo_vaddr |= PVO_DEAD;
2979
2980 /* Send RC bits to VM */
2981 if ((pvo->pvo_vaddr & PVO_MANAGED) &&
2982 (pvo->pvo_pte.prot & VM_PROT_WRITE)) {
2983 pg = PHYS_TO_VM_PAGE(PVO_PADDR(pvo));
2984 if (pg != NULL) {
2985 refchg |= atomic_readandclear_32(&pg->md.mdpg_attrs);
2986 if (refchg & LPTE_CHG)
2987 vm_page_dirty(pg);
2988 if (refchg & LPTE_REF)
2989 vm_page_aflag_set(pg, PGA_REFERENCED);
2990 }
2991 }
2992 }
2993
2994 static inline void
moea64_pvo_remove_from_page_locked(struct pvo_entry * pvo,vm_page_t m)2995 moea64_pvo_remove_from_page_locked(struct pvo_entry *pvo,
2996 vm_page_t m)
2997 {
2998
2999 KASSERT(pvo->pvo_vaddr & PVO_DEAD, ("Trying to delink live page"));
3000
3001 /* Use NULL pmaps as a sentinel for races in page deletion */
3002 if (pvo->pvo_pmap == NULL)
3003 return;
3004 pvo->pvo_pmap = NULL;
3005
3006 /*
3007 * Update vm about page writeability/executability if managed
3008 */
3009 PV_LOCKASSERT(PVO_PADDR(pvo));
3010 if (pvo->pvo_vaddr & PVO_MANAGED) {
3011 if (m != NULL) {
3012 LIST_REMOVE(pvo, pvo_vlink);
3013 if (LIST_EMPTY(vm_page_to_pvoh(m)))
3014 vm_page_aflag_clear(m,
3015 PGA_WRITEABLE | PGA_EXECUTABLE);
3016 }
3017 }
3018
3019 STAT_MOEA64(moea64_pvo_entries--);
3020 STAT_MOEA64(moea64_pvo_remove_calls++);
3021 }
3022
3023 static void
moea64_pvo_remove_from_page(struct pvo_entry * pvo)3024 moea64_pvo_remove_from_page(struct pvo_entry *pvo)
3025 {
3026 vm_page_t pg = NULL;
3027
3028 if (pvo->pvo_vaddr & PVO_MANAGED)
3029 pg = PHYS_TO_VM_PAGE(PVO_PADDR(pvo));
3030
3031 PV_LOCK(PVO_PADDR(pvo));
3032 moea64_pvo_remove_from_page_locked(pvo, pg);
3033 PV_UNLOCK(PVO_PADDR(pvo));
3034 }
3035
3036 static struct pvo_entry *
moea64_pvo_find_va(pmap_t pm,vm_offset_t va)3037 moea64_pvo_find_va(pmap_t pm, vm_offset_t va)
3038 {
3039 struct pvo_entry key;
3040
3041 PMAP_LOCK_ASSERT(pm, MA_OWNED);
3042
3043 key.pvo_vaddr = va & ~ADDR_POFF;
3044 return (RB_FIND(pvo_tree, &pm->pmap_pvo, &key));
3045 }
3046
3047 static bool
moea64_query_bit(vm_page_t m,uint64_t ptebit)3048 moea64_query_bit(vm_page_t m, uint64_t ptebit)
3049 {
3050 struct pvo_entry *pvo;
3051 int64_t ret;
3052 bool rv;
3053 vm_page_t sp;
3054
3055 /*
3056 * See if this bit is stored in the page already.
3057 *
3058 * For superpages, the bit is stored in the first vm page.
3059 */
3060 if ((m->md.mdpg_attrs & ptebit) != 0 ||
3061 ((sp = PHYS_TO_VM_PAGE(VM_PAGE_TO_PHYS(m) & ~HPT_SP_MASK)) != NULL &&
3062 (sp->md.mdpg_attrs & (ptebit | MDPG_ATTR_SP)) ==
3063 (ptebit | MDPG_ATTR_SP)))
3064 return (true);
3065
3066 /*
3067 * Examine each PTE. Sync so that any pending REF/CHG bits are
3068 * flushed to the PTEs.
3069 */
3070 rv = false;
3071 powerpc_sync();
3072 PV_PAGE_LOCK(m);
3073 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
3074 if (PVO_IS_SP(pvo)) {
3075 ret = moea64_sp_query(pvo, ptebit);
3076 /*
3077 * If SP was not demoted, check its REF/CHG bits here.
3078 */
3079 if (ret != -1) {
3080 if ((ret & ptebit) != 0) {
3081 rv = true;
3082 break;
3083 }
3084 continue;
3085 }
3086 /* else, fallthrough */
3087 }
3088
3089 ret = 0;
3090
3091 /*
3092 * See if this pvo has a valid PTE. if so, fetch the
3093 * REF/CHG bits from the valid PTE. If the appropriate
3094 * ptebit is set, return success.
3095 */
3096 PMAP_LOCK(pvo->pvo_pmap);
3097 if (!(pvo->pvo_vaddr & PVO_DEAD))
3098 ret = moea64_pte_synch(pvo);
3099 PMAP_UNLOCK(pvo->pvo_pmap);
3100
3101 if (ret > 0) {
3102 atomic_set_32(&m->md.mdpg_attrs,
3103 ret & (LPTE_CHG | LPTE_REF));
3104 if (ret & ptebit) {
3105 rv = true;
3106 break;
3107 }
3108 }
3109 }
3110 PV_PAGE_UNLOCK(m);
3111
3112 return (rv);
3113 }
3114
3115 static u_int
moea64_clear_bit(vm_page_t m,u_int64_t ptebit)3116 moea64_clear_bit(vm_page_t m, u_int64_t ptebit)
3117 {
3118 u_int count;
3119 struct pvo_entry *pvo;
3120 int64_t ret;
3121
3122 /*
3123 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so
3124 * we can reset the right ones).
3125 */
3126 powerpc_sync();
3127
3128 /*
3129 * For each pvo entry, clear the pte's ptebit.
3130 */
3131 count = 0;
3132 PV_PAGE_LOCK(m);
3133 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
3134 if (PVO_IS_SP(pvo)) {
3135 if ((ret = moea64_sp_clear(pvo, m, ptebit)) != -1) {
3136 count += ret;
3137 continue;
3138 }
3139 }
3140 ret = 0;
3141
3142 PMAP_LOCK(pvo->pvo_pmap);
3143 if (!(pvo->pvo_vaddr & PVO_DEAD))
3144 ret = moea64_pte_clear(pvo, ptebit);
3145 PMAP_UNLOCK(pvo->pvo_pmap);
3146
3147 if (ret > 0 && (ret & ptebit))
3148 count++;
3149 }
3150 atomic_clear_32(&m->md.mdpg_attrs, ptebit);
3151 PV_PAGE_UNLOCK(m);
3152
3153 return (count);
3154 }
3155
3156 int
moea64_dev_direct_mapped(vm_paddr_t pa,vm_size_t size)3157 moea64_dev_direct_mapped(vm_paddr_t pa, vm_size_t size)
3158 {
3159 struct pvo_entry *pvo, key;
3160 vm_offset_t ppa;
3161 int error = 0;
3162
3163 if (hw_direct_map && mem_valid(pa, size) == 0)
3164 return (0);
3165
3166 PMAP_LOCK(kernel_pmap);
3167 ppa = pa & ~ADDR_POFF;
3168 key.pvo_vaddr = DMAP_BASE_ADDRESS + ppa;
3169 for (pvo = RB_FIND(pvo_tree, &kernel_pmap->pmap_pvo, &key);
3170 ppa < pa + size; ppa += PAGE_SIZE,
3171 pvo = RB_NEXT(pvo_tree, &kernel_pmap->pmap_pvo, pvo)) {
3172 if (pvo == NULL || PVO_PADDR(pvo) != ppa) {
3173 error = EFAULT;
3174 break;
3175 }
3176 }
3177 PMAP_UNLOCK(kernel_pmap);
3178
3179 return (error);
3180 }
3181
3182 /*
3183 * Map a set of physical memory pages into the kernel virtual
3184 * address space. Return a pointer to where it is mapped. This
3185 * routine is intended to be used for mapping device memory,
3186 * NOT real memory.
3187 */
3188 void *
moea64_mapdev_attr(vm_paddr_t pa,vm_size_t size,vm_memattr_t ma)3189 moea64_mapdev_attr(vm_paddr_t pa, vm_size_t size, vm_memattr_t ma)
3190 {
3191 vm_offset_t va, tmpva, ppa, offset;
3192
3193 ppa = trunc_page(pa);
3194 offset = pa & PAGE_MASK;
3195 size = roundup2(offset + size, PAGE_SIZE);
3196
3197 va = kva_alloc(size);
3198
3199 if (!va)
3200 panic("moea64_mapdev: Couldn't alloc kernel virtual memory");
3201
3202 for (tmpva = va; size > 0;) {
3203 moea64_kenter_attr(tmpva, ppa, ma);
3204 size -= PAGE_SIZE;
3205 tmpva += PAGE_SIZE;
3206 ppa += PAGE_SIZE;
3207 }
3208
3209 return ((void *)(va + offset));
3210 }
3211
3212 void *
moea64_mapdev(vm_paddr_t pa,vm_size_t size)3213 moea64_mapdev(vm_paddr_t pa, vm_size_t size)
3214 {
3215
3216 return moea64_mapdev_attr(pa, size, VM_MEMATTR_DEFAULT);
3217 }
3218
3219 void
moea64_unmapdev(void * p,vm_size_t size)3220 moea64_unmapdev(void *p, vm_size_t size)
3221 {
3222 vm_offset_t base, offset, va;
3223
3224 va = (vm_offset_t)p;
3225 base = trunc_page(va);
3226 offset = va & PAGE_MASK;
3227 size = roundup2(offset + size, PAGE_SIZE);
3228
3229 moea64_qremove(base, atop(size));
3230 kva_free(base, size);
3231 }
3232
3233 void
moea64_sync_icache(pmap_t pm,vm_offset_t va,vm_size_t sz)3234 moea64_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
3235 {
3236 struct pvo_entry *pvo;
3237 vm_offset_t lim;
3238 vm_paddr_t pa;
3239 vm_size_t len;
3240
3241 if (__predict_false(pm == NULL))
3242 pm = &curthread->td_proc->p_vmspace->vm_pmap;
3243
3244 PMAP_LOCK(pm);
3245 while (sz > 0) {
3246 lim = round_page(va+1);
3247 len = MIN(lim - va, sz);
3248 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF);
3249 if (pvo != NULL && !(pvo->pvo_pte.pa & LPTE_I)) {
3250 pa = PVO_PADDR(pvo) | (va & ADDR_POFF);
3251 moea64_syncicache(pm, va, pa, len);
3252 }
3253 va += len;
3254 sz -= len;
3255 }
3256 PMAP_UNLOCK(pm);
3257 }
3258
3259 void
moea64_dumpsys_map(vm_paddr_t pa,size_t sz,void ** va)3260 moea64_dumpsys_map(vm_paddr_t pa, size_t sz, void **va)
3261 {
3262
3263 *va = (void *)(uintptr_t)pa;
3264 }
3265
3266 extern struct dump_pa dump_map[PHYS_AVAIL_SZ + 1];
3267
3268 void
moea64_scan_init(void)3269 moea64_scan_init(void)
3270 {
3271 struct pvo_entry *pvo;
3272 vm_offset_t va;
3273 int i;
3274
3275 if (!do_minidump) {
3276 /* Initialize phys. segments for dumpsys(). */
3277 memset(&dump_map, 0, sizeof(dump_map));
3278 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz);
3279 for (i = 0; i < pregions_sz; i++) {
3280 dump_map[i].pa_start = pregions[i].mr_start;
3281 dump_map[i].pa_size = pregions[i].mr_size;
3282 }
3283 return;
3284 }
3285
3286 /* Virtual segments for minidumps: */
3287 memset(&dump_map, 0, sizeof(dump_map));
3288
3289 /* 1st: kernel .data and .bss. */
3290 dump_map[0].pa_start = trunc_page((uintptr_t)_etext);
3291 dump_map[0].pa_size = round_page((uintptr_t)_end) -
3292 dump_map[0].pa_start;
3293
3294 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */
3295 dump_map[1].pa_start = (vm_paddr_t)(uintptr_t)msgbufp->msg_ptr;
3296 dump_map[1].pa_size = round_page(msgbufp->msg_size);
3297
3298 /* 3rd: kernel VM. */
3299 va = dump_map[1].pa_start + dump_map[1].pa_size;
3300 /* Find start of next chunk (from va). */
3301 while (va < virtual_end) {
3302 /* Don't dump the buffer cache. */
3303 if (va >= kmi.buffer_sva && va < kmi.buffer_eva) {
3304 va = kmi.buffer_eva;
3305 continue;
3306 }
3307 pvo = moea64_pvo_find_va(kernel_pmap, va & ~ADDR_POFF);
3308 if (pvo != NULL && !(pvo->pvo_vaddr & PVO_DEAD))
3309 break;
3310 va += PAGE_SIZE;
3311 }
3312 if (va < virtual_end) {
3313 dump_map[2].pa_start = va;
3314 va += PAGE_SIZE;
3315 /* Find last page in chunk. */
3316 while (va < virtual_end) {
3317 /* Don't run into the buffer cache. */
3318 if (va == kmi.buffer_sva)
3319 break;
3320 pvo = moea64_pvo_find_va(kernel_pmap, va & ~ADDR_POFF);
3321 if (pvo == NULL || (pvo->pvo_vaddr & PVO_DEAD))
3322 break;
3323 va += PAGE_SIZE;
3324 }
3325 dump_map[2].pa_size = va - dump_map[2].pa_start;
3326 }
3327 }
3328
3329 #ifdef __powerpc64__
3330
3331 static size_t
moea64_scan_pmap(struct bitset * dump_bitset)3332 moea64_scan_pmap(struct bitset *dump_bitset)
3333 {
3334 struct pvo_entry *pvo;
3335 vm_paddr_t pa, pa_end;
3336 vm_offset_t va, pgva, kstart, kend, kstart_lp, kend_lp;
3337 uint64_t lpsize;
3338
3339 lpsize = moea64_large_page_size;
3340 kstart = trunc_page((vm_offset_t)_etext);
3341 kend = round_page((vm_offset_t)_end);
3342 kstart_lp = kstart & ~moea64_large_page_mask;
3343 kend_lp = (kend + moea64_large_page_mask) & ~moea64_large_page_mask;
3344
3345 CTR4(KTR_PMAP, "moea64_scan_pmap: kstart=0x%016lx, kend=0x%016lx, "
3346 "kstart_lp=0x%016lx, kend_lp=0x%016lx",
3347 kstart, kend, kstart_lp, kend_lp);
3348
3349 PMAP_LOCK(kernel_pmap);
3350 RB_FOREACH(pvo, pvo_tree, &kernel_pmap->pmap_pvo) {
3351 va = pvo->pvo_vaddr;
3352
3353 if (va & PVO_DEAD)
3354 continue;
3355
3356 /* Skip DMAP (except kernel area) */
3357 if (va >= DMAP_BASE_ADDRESS && va <= DMAP_MAX_ADDRESS) {
3358 if (va & PVO_LARGE) {
3359 pgva = va & ~moea64_large_page_mask;
3360 if (pgva < kstart_lp || pgva >= kend_lp)
3361 continue;
3362 } else {
3363 pgva = trunc_page(va);
3364 if (pgva < kstart || pgva >= kend)
3365 continue;
3366 }
3367 }
3368
3369 pa = PVO_PADDR(pvo);
3370
3371 if (va & PVO_LARGE) {
3372 pa_end = pa + lpsize;
3373 for (; pa < pa_end; pa += PAGE_SIZE) {
3374 if (vm_phys_is_dumpable(pa))
3375 vm_page_dump_add(dump_bitset, pa);
3376 }
3377 } else {
3378 if (vm_phys_is_dumpable(pa))
3379 vm_page_dump_add(dump_bitset, pa);
3380 }
3381 }
3382 PMAP_UNLOCK(kernel_pmap);
3383
3384 return (sizeof(struct lpte) * moea64_pteg_count * 8);
3385 }
3386
3387 static struct dump_context dump_ctx;
3388
3389 static void *
moea64_dump_pmap_init(unsigned blkpgs)3390 moea64_dump_pmap_init(unsigned blkpgs)
3391 {
3392 dump_ctx.ptex = 0;
3393 dump_ctx.ptex_end = moea64_pteg_count * 8;
3394 dump_ctx.blksz = blkpgs * PAGE_SIZE;
3395 return (&dump_ctx);
3396 }
3397
3398 #else
3399
3400 static size_t
moea64_scan_pmap(struct bitset * dump_bitset __unused)3401 moea64_scan_pmap(struct bitset *dump_bitset __unused)
3402 {
3403 return (0);
3404 }
3405
3406 static void *
moea64_dump_pmap_init(unsigned blkpgs)3407 moea64_dump_pmap_init(unsigned blkpgs)
3408 {
3409 return (NULL);
3410 }
3411
3412 #endif
3413
3414 #ifdef __powerpc64__
3415 static void
moea64_map_range(vm_offset_t va,vm_paddr_t pa,vm_size_t npages)3416 moea64_map_range(vm_offset_t va, vm_paddr_t pa, vm_size_t npages)
3417 {
3418
3419 for (; npages > 0; --npages) {
3420 if (moea64_large_page_size != 0 &&
3421 (pa & moea64_large_page_mask) == 0 &&
3422 (va & moea64_large_page_mask) == 0 &&
3423 npages >= (moea64_large_page_size >> PAGE_SHIFT)) {
3424 PMAP_LOCK(kernel_pmap);
3425 moea64_kenter_large(va, pa, 0, 0);
3426 PMAP_UNLOCK(kernel_pmap);
3427 pa += moea64_large_page_size;
3428 va += moea64_large_page_size;
3429 npages -= (moea64_large_page_size >> PAGE_SHIFT) - 1;
3430 } else {
3431 moea64_kenter(va, pa);
3432 pa += PAGE_SIZE;
3433 va += PAGE_SIZE;
3434 }
3435 }
3436 }
3437
3438 static void
moea64_page_array_startup(long pages)3439 moea64_page_array_startup(long pages)
3440 {
3441 long dom_pages[MAXMEMDOM];
3442 vm_paddr_t pa;
3443 vm_offset_t va, vm_page_base;
3444 vm_size_t needed, size;
3445 int domain;
3446 int i;
3447
3448 vm_page_base = 0xd000000000000000ULL;
3449
3450 /* Short-circuit single-domain systems. */
3451 if (vm_ndomains == 1) {
3452 size = round_page(pages * sizeof(struct vm_page));
3453 pa = vm_phys_early_alloc(0, size);
3454 vm_page_base = moea64_map(&vm_page_base,
3455 pa, pa + size, VM_PROT_READ | VM_PROT_WRITE);
3456 vm_page_array_size = pages;
3457 vm_page_array = (vm_page_t)vm_page_base;
3458 return;
3459 }
3460
3461 for (i = 0; i < MAXMEMDOM; i++)
3462 dom_pages[i] = 0;
3463
3464 /* Now get the number of pages required per domain. */
3465 for (i = 0; i < vm_phys_nsegs; i++) {
3466 domain = vm_phys_segs[i].domain;
3467 KASSERT(domain < MAXMEMDOM,
3468 ("Invalid vm_phys_segs NUMA domain %d!\n", domain));
3469 /* Get size of vm_page_array needed for this segment. */
3470 size = btoc(vm_phys_segs[i].end - vm_phys_segs[i].start);
3471 dom_pages[domain] += size;
3472 }
3473
3474 for (i = 0; phys_avail[i + 1] != 0; i+= 2) {
3475 domain = vm_phys_domain(phys_avail[i]);
3476 KASSERT(domain < MAXMEMDOM,
3477 ("Invalid phys_avail NUMA domain %d!\n", domain));
3478 size = btoc(phys_avail[i + 1] - phys_avail[i]);
3479 dom_pages[domain] += size;
3480 }
3481
3482 /*
3483 * Map in chunks that can get us all 16MB pages. There will be some
3484 * overlap between domains, but that's acceptable for now.
3485 */
3486 vm_page_array_size = 0;
3487 va = vm_page_base;
3488 for (i = 0; i < MAXMEMDOM && vm_page_array_size < pages; i++) {
3489 if (dom_pages[i] == 0)
3490 continue;
3491 size = ulmin(pages - vm_page_array_size, dom_pages[i]);
3492 size = round_page(size * sizeof(struct vm_page));
3493 needed = size;
3494 size = roundup2(size, moea64_large_page_size);
3495 pa = vm_phys_early_alloc(i, size);
3496 vm_page_array_size += size / sizeof(struct vm_page);
3497 moea64_map_range(va, pa, size >> PAGE_SHIFT);
3498 /* Scoot up domain 0, to reduce the domain page overlap. */
3499 if (i == 0)
3500 vm_page_base += size - needed;
3501 va += size;
3502 }
3503 vm_page_array = (vm_page_t)vm_page_base;
3504 vm_page_array_size = pages;
3505 }
3506 #endif
3507
3508 static int64_t
moea64_null_method(void)3509 moea64_null_method(void)
3510 {
3511 return (0);
3512 }
3513
moea64_pte_replace_default(struct pvo_entry * pvo,int flags)3514 static int64_t moea64_pte_replace_default(struct pvo_entry *pvo, int flags)
3515 {
3516 int64_t refchg;
3517
3518 refchg = moea64_pte_unset(pvo);
3519 moea64_pte_insert(pvo);
3520
3521 return (refchg);
3522 }
3523
3524 struct moea64_funcs *moea64_ops;
3525
3526 #define DEFINE_OEA64_IFUNC(ret, func, args, def) \
3527 DEFINE_IFUNC(, ret, moea64_##func, args) { \
3528 moea64_##func##_t f; \
3529 if (moea64_ops == NULL) \
3530 return ((moea64_##func##_t)def); \
3531 f = moea64_ops->func; \
3532 return (f != NULL ? f : (moea64_##func##_t)def);\
3533 }
3534
3535 void
moea64_install(void)3536 moea64_install(void)
3537 {
3538 #ifdef __powerpc64__
3539 if (hw_direct_map == -1) {
3540 moea64_probe_large_page();
3541
3542 /* Use a direct map if we have large page support */
3543 if (moea64_large_page_size > 0)
3544 hw_direct_map = 1;
3545 else
3546 hw_direct_map = 0;
3547 }
3548 #endif
3549
3550 /*
3551 * Default to non-DMAP, and switch over to DMAP functions once we know
3552 * we have DMAP.
3553 */
3554 if (hw_direct_map) {
3555 moea64_methods.quick_enter_page = moea64_quick_enter_page_dmap;
3556 moea64_methods.quick_remove_page = NULL;
3557 moea64_methods.copy_page = moea64_copy_page_dmap;
3558 moea64_methods.zero_page = moea64_zero_page_dmap;
3559 moea64_methods.copy_pages = moea64_copy_pages_dmap;
3560 }
3561 }
3562
3563 DEFINE_OEA64_IFUNC(int64_t, pte_replace, (struct pvo_entry *, int),
3564 moea64_pte_replace_default)
3565 DEFINE_OEA64_IFUNC(int64_t, pte_insert, (struct pvo_entry *), moea64_null_method)
3566 DEFINE_OEA64_IFUNC(int64_t, pte_unset, (struct pvo_entry *), moea64_null_method)
3567 DEFINE_OEA64_IFUNC(int64_t, pte_clear, (struct pvo_entry *, uint64_t),
3568 moea64_null_method)
3569 DEFINE_OEA64_IFUNC(int64_t, pte_synch, (struct pvo_entry *), moea64_null_method)
3570 DEFINE_OEA64_IFUNC(int64_t, pte_insert_sp, (struct pvo_entry *), moea64_null_method)
3571 DEFINE_OEA64_IFUNC(int64_t, pte_unset_sp, (struct pvo_entry *), moea64_null_method)
3572 DEFINE_OEA64_IFUNC(int64_t, pte_replace_sp, (struct pvo_entry *), moea64_null_method)
3573
3574 /* Superpage functions */
3575
3576 /* MMU interface */
3577
3578 static bool
moea64_ps_enabled(pmap_t pmap)3579 moea64_ps_enabled(pmap_t pmap)
3580 {
3581 return (superpages_enabled);
3582 }
3583
3584 static void
moea64_align_superpage(vm_object_t object,vm_ooffset_t offset,vm_offset_t * addr,vm_size_t size)3585 moea64_align_superpage(vm_object_t object, vm_ooffset_t offset,
3586 vm_offset_t *addr, vm_size_t size)
3587 {
3588 vm_offset_t sp_offset;
3589
3590 if (size < HPT_SP_SIZE)
3591 return;
3592
3593 CTR4(KTR_PMAP, "%s: offs=%#jx, addr=%p, size=%#jx",
3594 __func__, (uintmax_t)offset, addr, (uintmax_t)size);
3595
3596 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
3597 offset += ptoa(object->pg_color);
3598 sp_offset = offset & HPT_SP_MASK;
3599 if (size - ((HPT_SP_SIZE - sp_offset) & HPT_SP_MASK) < HPT_SP_SIZE ||
3600 (*addr & HPT_SP_MASK) == sp_offset)
3601 return;
3602 if ((*addr & HPT_SP_MASK) < sp_offset)
3603 *addr = (*addr & ~HPT_SP_MASK) + sp_offset;
3604 else
3605 *addr = ((*addr + HPT_SP_MASK) & ~HPT_SP_MASK) + sp_offset;
3606 }
3607
3608 /* Helpers */
3609
3610 static __inline void
moea64_pvo_cleanup(struct pvo_dlist * tofree)3611 moea64_pvo_cleanup(struct pvo_dlist *tofree)
3612 {
3613 struct pvo_entry *pvo;
3614
3615 /* clean up */
3616 while (!SLIST_EMPTY(tofree)) {
3617 pvo = SLIST_FIRST(tofree);
3618 SLIST_REMOVE_HEAD(tofree, pvo_dlink);
3619 if (pvo->pvo_vaddr & PVO_DEAD)
3620 moea64_pvo_remove_from_page(pvo);
3621 free_pvo_entry(pvo);
3622 }
3623 }
3624
3625 static __inline uint16_t
pvo_to_vmpage_flags(struct pvo_entry * pvo)3626 pvo_to_vmpage_flags(struct pvo_entry *pvo)
3627 {
3628 uint16_t flags;
3629
3630 flags = 0;
3631 if ((pvo->pvo_pte.prot & VM_PROT_WRITE) != 0)
3632 flags |= PGA_WRITEABLE;
3633 if ((pvo->pvo_pte.prot & VM_PROT_EXECUTE) != 0)
3634 flags |= PGA_EXECUTABLE;
3635
3636 return (flags);
3637 }
3638
3639 /*
3640 * Check if the given pvo and its superpage are in sva-eva range.
3641 */
3642 static __inline bool
moea64_sp_pvo_in_range(struct pvo_entry * pvo,vm_offset_t sva,vm_offset_t eva)3643 moea64_sp_pvo_in_range(struct pvo_entry *pvo, vm_offset_t sva, vm_offset_t eva)
3644 {
3645 vm_offset_t spva;
3646
3647 spva = PVO_VADDR(pvo) & ~HPT_SP_MASK;
3648 if (spva >= sva && spva + HPT_SP_SIZE <= eva) {
3649 /*
3650 * Because this function is intended to be called from loops
3651 * that iterate over ordered pvo entries, if the condition
3652 * above is true then the pvo must be the first of its
3653 * superpage.
3654 */
3655 KASSERT(PVO_VADDR(pvo) == spva,
3656 ("%s: unexpected unaligned superpage pvo", __func__));
3657 return (true);
3658 }
3659 return (false);
3660 }
3661
3662 /*
3663 * Update vm about the REF/CHG bits if the superpage is managed and
3664 * has (or had) write access.
3665 */
3666 static void
moea64_sp_refchg_process(struct pvo_entry * sp,vm_page_t m,int64_t sp_refchg,vm_prot_t prot)3667 moea64_sp_refchg_process(struct pvo_entry *sp, vm_page_t m,
3668 int64_t sp_refchg, vm_prot_t prot)
3669 {
3670 vm_page_t m_end;
3671 int64_t refchg;
3672
3673 if ((sp->pvo_vaddr & PVO_MANAGED) != 0 && (prot & VM_PROT_WRITE) != 0) {
3674 for (m_end = &m[HPT_SP_PAGES]; m < m_end; m++) {
3675 refchg = sp_refchg |
3676 atomic_readandclear_32(&m->md.mdpg_attrs);
3677 if (refchg & LPTE_CHG)
3678 vm_page_dirty(m);
3679 if (refchg & LPTE_REF)
3680 vm_page_aflag_set(m, PGA_REFERENCED);
3681 }
3682 }
3683 }
3684
3685 /* Superpage ops */
3686
3687 static int
moea64_sp_enter(pmap_t pmap,vm_offset_t va,vm_page_t m,vm_prot_t prot,u_int flags,int8_t psind)3688 moea64_sp_enter(pmap_t pmap, vm_offset_t va, vm_page_t m,
3689 vm_prot_t prot, u_int flags, int8_t psind)
3690 {
3691 struct pvo_entry *pvo, **pvos;
3692 struct pvo_head *pvo_head;
3693 vm_offset_t sva;
3694 vm_page_t sm;
3695 vm_paddr_t pa, spa;
3696 bool sync;
3697 struct pvo_dlist tofree;
3698 int error __diagused, i;
3699 uint16_t aflags;
3700
3701 KASSERT((va & HPT_SP_MASK) == 0, ("%s: va %#jx unaligned",
3702 __func__, (uintmax_t)va));
3703 KASSERT(psind == 1, ("%s: invalid psind: %d", __func__, psind));
3704 KASSERT(m->psind == 1, ("%s: invalid m->psind: %d",
3705 __func__, m->psind));
3706 KASSERT(pmap != kernel_pmap,
3707 ("%s: function called with kernel pmap", __func__));
3708
3709 CTR5(KTR_PMAP, "%s: va=%#jx, pa=%#jx, prot=%#x, flags=%#x, psind=1",
3710 __func__, (uintmax_t)va, (uintmax_t)VM_PAGE_TO_PHYS(m),
3711 prot, flags);
3712
3713 SLIST_INIT(&tofree);
3714
3715 sva = va;
3716 sm = m;
3717 spa = pa = VM_PAGE_TO_PHYS(sm);
3718
3719 /* Try to allocate all PVOs first, to make failure handling easier. */
3720 pvos = malloc(HPT_SP_PAGES * sizeof(struct pvo_entry *), M_TEMP,
3721 M_NOWAIT);
3722 if (pvos == NULL) {
3723 CTR1(KTR_PMAP, "%s: failed to alloc pvo array", __func__);
3724 return (KERN_RESOURCE_SHORTAGE);
3725 }
3726
3727 for (i = 0; i < HPT_SP_PAGES; i++) {
3728 pvos[i] = alloc_pvo_entry(0);
3729 if (pvos[i] == NULL) {
3730 CTR1(KTR_PMAP, "%s: failed to alloc pvo", __func__);
3731 for (i = i - 1; i >= 0; i--)
3732 free_pvo_entry(pvos[i]);
3733 free(pvos, M_TEMP);
3734 return (KERN_RESOURCE_SHORTAGE);
3735 }
3736 }
3737
3738 SP_PV_LOCK_ALIGNED(spa);
3739 PMAP_LOCK(pmap);
3740
3741 /* Note: moea64_remove_locked() also clears cached REF/CHG bits. */
3742 moea64_remove_locked(pmap, va, va + HPT_SP_SIZE, &tofree);
3743
3744 /* Enter pages */
3745 for (i = 0; i < HPT_SP_PAGES;
3746 i++, va += PAGE_SIZE, pa += PAGE_SIZE, m++) {
3747 pvo = pvos[i];
3748
3749 pvo->pvo_pte.prot = prot;
3750 pvo->pvo_pte.pa = (pa & ~HPT_SP_MASK) | LPTE_LP_4K_16M |
3751 moea64_calc_wimg(pa, pmap_page_get_memattr(m));
3752
3753 if ((flags & PMAP_ENTER_WIRED) != 0)
3754 pvo->pvo_vaddr |= PVO_WIRED;
3755 pvo->pvo_vaddr |= PVO_LARGE;
3756
3757 if ((m->oflags & VPO_UNMANAGED) != 0)
3758 pvo_head = NULL;
3759 else {
3760 pvo_head = &m->md.mdpg_pvoh;
3761 pvo->pvo_vaddr |= PVO_MANAGED;
3762 }
3763
3764 init_pvo_entry(pvo, pmap, va);
3765
3766 error = moea64_pvo_enter(pvo, pvo_head, NULL);
3767 /*
3768 * All superpage PVOs were previously removed, so no errors
3769 * should occur while inserting the new ones.
3770 */
3771 KASSERT(error == 0, ("%s: unexpected error "
3772 "when inserting superpage PVO: %d",
3773 __func__, error));
3774 }
3775
3776 PMAP_UNLOCK(pmap);
3777 SP_PV_UNLOCK_ALIGNED(spa);
3778
3779 sync = (sm->a.flags & PGA_EXECUTABLE) == 0;
3780 /* Note: moea64_pvo_cleanup() also clears page prot. flags. */
3781 moea64_pvo_cleanup(&tofree);
3782 pvo = pvos[0];
3783
3784 /* Set vm page flags */
3785 aflags = pvo_to_vmpage_flags(pvo);
3786 if (aflags != 0)
3787 for (m = sm; m < &sm[HPT_SP_PAGES]; m++)
3788 vm_page_aflag_set(m, aflags);
3789
3790 /*
3791 * Flush the page from the instruction cache if this page is
3792 * mapped executable and cacheable.
3793 */
3794 if (sync && (pvo->pvo_pte.pa & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0)
3795 moea64_syncicache(pmap, sva, spa, HPT_SP_SIZE);
3796
3797 atomic_add_long(&sp_mappings, 1);
3798 CTR3(KTR_PMAP, "%s: SP success for va %#jx in pmap %p",
3799 __func__, (uintmax_t)sva, pmap);
3800
3801 free(pvos, M_TEMP);
3802 return (KERN_SUCCESS);
3803 }
3804
3805 #if VM_NRESERVLEVEL > 0
3806 static void
moea64_sp_promote(pmap_t pmap,vm_offset_t va,vm_page_t m)3807 moea64_sp_promote(pmap_t pmap, vm_offset_t va, vm_page_t m)
3808 {
3809 struct pvo_entry *first, *pvo;
3810 vm_paddr_t pa, pa_end;
3811 vm_offset_t sva, va_end;
3812 int64_t sp_refchg;
3813
3814 /* This CTR may generate a lot of output. */
3815 /* CTR2(KTR_PMAP, "%s: va=%#jx", __func__, (uintmax_t)va); */
3816
3817 va &= ~HPT_SP_MASK;
3818 sva = va;
3819 /* Get superpage */
3820 pa = VM_PAGE_TO_PHYS(m) & ~HPT_SP_MASK;
3821 m = PHYS_TO_VM_PAGE(pa);
3822
3823 PMAP_LOCK(pmap);
3824
3825 /*
3826 * Check if all pages meet promotion criteria.
3827 *
3828 * XXX In some cases the loop below may be executed for each or most
3829 * of the entered pages of a superpage, which can be expensive
3830 * (although it was not profiled) and need some optimization.
3831 *
3832 * Some cases where this seems to happen are:
3833 * - When a superpage is first entered read-only and later becomes
3834 * read-write.
3835 * - When some of the superpage's virtual addresses map to previously
3836 * wired/cached pages while others map to pages allocated from a
3837 * different physical address range. A common scenario where this
3838 * happens is when mmap'ing a file that is already present in FS
3839 * block cache and doesn't fill a superpage.
3840 */
3841 first = pvo = moea64_pvo_find_va(pmap, sva);
3842 for (pa_end = pa + HPT_SP_SIZE;
3843 pa < pa_end; pa += PAGE_SIZE, va += PAGE_SIZE) {
3844 if (pvo == NULL || (pvo->pvo_vaddr & PVO_DEAD) != 0) {
3845 CTR3(KTR_PMAP,
3846 "%s: NULL or dead PVO: pmap=%p, va=%#jx",
3847 __func__, pmap, (uintmax_t)va);
3848 goto error;
3849 }
3850 if (PVO_PADDR(pvo) != pa) {
3851 CTR5(KTR_PMAP, "%s: PAs don't match: "
3852 "pmap=%p, va=%#jx, pvo_pa=%#jx, exp_pa=%#jx",
3853 __func__, pmap, (uintmax_t)va,
3854 (uintmax_t)PVO_PADDR(pvo), (uintmax_t)pa);
3855 atomic_add_long(&sp_p_fail_pa, 1);
3856 goto error;
3857 }
3858 if ((first->pvo_vaddr & PVO_FLAGS_PROMOTE) !=
3859 (pvo->pvo_vaddr & PVO_FLAGS_PROMOTE)) {
3860 CTR5(KTR_PMAP, "%s: PVO flags don't match: "
3861 "pmap=%p, va=%#jx, pvo_flags=%#jx, exp_flags=%#jx",
3862 __func__, pmap, (uintmax_t)va,
3863 (uintmax_t)(pvo->pvo_vaddr & PVO_FLAGS_PROMOTE),
3864 (uintmax_t)(first->pvo_vaddr & PVO_FLAGS_PROMOTE));
3865 atomic_add_long(&sp_p_fail_flags, 1);
3866 goto error;
3867 }
3868 if (first->pvo_pte.prot != pvo->pvo_pte.prot) {
3869 CTR5(KTR_PMAP, "%s: PVO protections don't match: "
3870 "pmap=%p, va=%#jx, pvo_prot=%#x, exp_prot=%#x",
3871 __func__, pmap, (uintmax_t)va,
3872 pvo->pvo_pte.prot, first->pvo_pte.prot);
3873 atomic_add_long(&sp_p_fail_prot, 1);
3874 goto error;
3875 }
3876 if ((first->pvo_pte.pa & LPTE_WIMG) !=
3877 (pvo->pvo_pte.pa & LPTE_WIMG)) {
3878 CTR5(KTR_PMAP, "%s: WIMG bits don't match: "
3879 "pmap=%p, va=%#jx, pvo_wimg=%#jx, exp_wimg=%#jx",
3880 __func__, pmap, (uintmax_t)va,
3881 (uintmax_t)(pvo->pvo_pte.pa & LPTE_WIMG),
3882 (uintmax_t)(first->pvo_pte.pa & LPTE_WIMG));
3883 atomic_add_long(&sp_p_fail_wimg, 1);
3884 goto error;
3885 }
3886
3887 pvo = RB_NEXT(pvo_tree, &pmap->pmap_pvo, pvo);
3888 }
3889
3890 /* All OK, promote. */
3891
3892 /*
3893 * Handle superpage REF/CHG bits. If REF or CHG is set in
3894 * any page, then it must be set in the superpage.
3895 *
3896 * Instead of querying each page, we take advantage of two facts:
3897 * 1- If a page is being promoted, it was referenced.
3898 * 2- If promoted pages are writable, they were modified.
3899 */
3900 sp_refchg = LPTE_REF |
3901 ((first->pvo_pte.prot & VM_PROT_WRITE) != 0 ? LPTE_CHG : 0);
3902
3903 /* Promote pages */
3904
3905 for (pvo = first, va_end = PVO_VADDR(pvo) + HPT_SP_SIZE;
3906 pvo != NULL && PVO_VADDR(pvo) < va_end;
3907 pvo = RB_NEXT(pvo_tree, &pmap->pmap_pvo, pvo)) {
3908 pvo->pvo_pte.pa &= ADDR_POFF | ~HPT_SP_MASK;
3909 pvo->pvo_pte.pa |= LPTE_LP_4K_16M;
3910 pvo->pvo_vaddr |= PVO_LARGE;
3911 }
3912 moea64_pte_replace_sp(first);
3913
3914 /* Send REF/CHG bits to VM */
3915 moea64_sp_refchg_process(first, m, sp_refchg, first->pvo_pte.prot);
3916
3917 /* Use first page to cache REF/CHG bits */
3918 atomic_set_32(&m->md.mdpg_attrs, sp_refchg | MDPG_ATTR_SP);
3919
3920 PMAP_UNLOCK(pmap);
3921
3922 atomic_add_long(&sp_mappings, 1);
3923 atomic_add_long(&sp_promotions, 1);
3924 CTR3(KTR_PMAP, "%s: success for va %#jx in pmap %p",
3925 __func__, (uintmax_t)sva, pmap);
3926 return;
3927
3928 error:
3929 atomic_add_long(&sp_p_failures, 1);
3930 PMAP_UNLOCK(pmap);
3931 }
3932 #endif
3933
3934 static void
moea64_sp_demote_aligned(struct pvo_entry * sp)3935 moea64_sp_demote_aligned(struct pvo_entry *sp)
3936 {
3937 struct pvo_entry *pvo;
3938 vm_offset_t va, va_end;
3939 vm_paddr_t pa;
3940 vm_page_t m;
3941 pmap_t pmap __diagused;
3942 int64_t refchg;
3943
3944 CTR2(KTR_PMAP, "%s: va=%#jx", __func__, (uintmax_t)PVO_VADDR(sp));
3945
3946 pmap = sp->pvo_pmap;
3947 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3948
3949 pvo = sp;
3950
3951 /* Demote pages */
3952
3953 va = PVO_VADDR(pvo);
3954 pa = PVO_PADDR(pvo);
3955 m = PHYS_TO_VM_PAGE(pa);
3956
3957 for (pvo = sp, va_end = va + HPT_SP_SIZE;
3958 pvo != NULL && PVO_VADDR(pvo) < va_end;
3959 pvo = RB_NEXT(pvo_tree, &pmap->pmap_pvo, pvo),
3960 va += PAGE_SIZE, pa += PAGE_SIZE) {
3961 KASSERT(pvo && PVO_VADDR(pvo) == va,
3962 ("%s: missing PVO for va %#jx", __func__, (uintmax_t)va));
3963
3964 pvo->pvo_vaddr &= ~PVO_LARGE;
3965 pvo->pvo_pte.pa &= ~LPTE_RPGN;
3966 pvo->pvo_pte.pa |= pa;
3967
3968 }
3969 refchg = moea64_pte_replace_sp(sp);
3970
3971 /*
3972 * Clear SP flag
3973 *
3974 * XXX It is possible that another pmap has this page mapped as
3975 * part of a superpage, but as the SP flag is used only for
3976 * caching SP REF/CHG bits, that will be queried if not set
3977 * in cache, it should be ok to clear it here.
3978 */
3979 atomic_clear_32(&m->md.mdpg_attrs, MDPG_ATTR_SP);
3980
3981 /*
3982 * Handle superpage REF/CHG bits. A bit set in the superpage
3983 * means all pages should consider it set.
3984 */
3985 moea64_sp_refchg_process(sp, m, refchg, sp->pvo_pte.prot);
3986
3987 atomic_add_long(&sp_demotions, 1);
3988 CTR3(KTR_PMAP, "%s: success for va %#jx in pmap %p",
3989 __func__, (uintmax_t)PVO_VADDR(sp), pmap);
3990 }
3991
3992 static void
moea64_sp_demote(struct pvo_entry * pvo)3993 moea64_sp_demote(struct pvo_entry *pvo)
3994 {
3995 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED);
3996
3997 if ((PVO_VADDR(pvo) & HPT_SP_MASK) != 0) {
3998 pvo = moea64_pvo_find_va(pvo->pvo_pmap,
3999 PVO_VADDR(pvo) & ~HPT_SP_MASK);
4000 KASSERT(pvo != NULL, ("%s: missing PVO for va %#jx",
4001 __func__, (uintmax_t)(PVO_VADDR(pvo) & ~HPT_SP_MASK)));
4002 }
4003 moea64_sp_demote_aligned(pvo);
4004 }
4005
4006 static struct pvo_entry *
moea64_sp_unwire(struct pvo_entry * sp)4007 moea64_sp_unwire(struct pvo_entry *sp)
4008 {
4009 struct pvo_entry *pvo, *prev;
4010 vm_offset_t eva;
4011 pmap_t pm;
4012 int64_t ret, refchg;
4013
4014 CTR2(KTR_PMAP, "%s: va=%#jx", __func__, (uintmax_t)PVO_VADDR(sp));
4015
4016 pm = sp->pvo_pmap;
4017 PMAP_LOCK_ASSERT(pm, MA_OWNED);
4018
4019 eva = PVO_VADDR(sp) + HPT_SP_SIZE;
4020 refchg = 0;
4021 for (pvo = sp; pvo != NULL && PVO_VADDR(pvo) < eva;
4022 prev = pvo, pvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo)) {
4023 if ((pvo->pvo_vaddr & PVO_WIRED) == 0)
4024 panic("%s: pvo %p is missing PVO_WIRED",
4025 __func__, pvo);
4026 pvo->pvo_vaddr &= ~PVO_WIRED;
4027
4028 ret = moea64_pte_replace(pvo, 0 /* No invalidation */);
4029 if (ret < 0)
4030 refchg |= LPTE_CHG;
4031 else
4032 refchg |= ret;
4033
4034 pm->pm_stats.wired_count--;
4035 }
4036
4037 /* Send REF/CHG bits to VM */
4038 moea64_sp_refchg_process(sp, PHYS_TO_VM_PAGE(PVO_PADDR(sp)),
4039 refchg, sp->pvo_pte.prot);
4040
4041 return (prev);
4042 }
4043
4044 static struct pvo_entry *
moea64_sp_protect(struct pvo_entry * sp,vm_prot_t prot)4045 moea64_sp_protect(struct pvo_entry *sp, vm_prot_t prot)
4046 {
4047 struct pvo_entry *pvo, *prev;
4048 vm_offset_t eva;
4049 pmap_t pm;
4050 vm_page_t m, m_end;
4051 int64_t ret, refchg;
4052 vm_prot_t oldprot;
4053
4054 CTR3(KTR_PMAP, "%s: va=%#jx, prot=%x",
4055 __func__, (uintmax_t)PVO_VADDR(sp), prot);
4056
4057 pm = sp->pvo_pmap;
4058 PMAP_LOCK_ASSERT(pm, MA_OWNED);
4059
4060 oldprot = sp->pvo_pte.prot;
4061 m = PHYS_TO_VM_PAGE(PVO_PADDR(sp));
4062 KASSERT(m != NULL, ("%s: missing vm page for pa %#jx",
4063 __func__, (uintmax_t)PVO_PADDR(sp)));
4064 eva = PVO_VADDR(sp) + HPT_SP_SIZE;
4065 refchg = 0;
4066
4067 for (pvo = sp; pvo != NULL && PVO_VADDR(pvo) < eva;
4068 prev = pvo, pvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo)) {
4069 pvo->pvo_pte.prot = prot;
4070 /*
4071 * If the PVO is in the page table, update mapping
4072 */
4073 ret = moea64_pte_replace(pvo, MOEA64_PTE_PROT_UPDATE);
4074 if (ret < 0)
4075 refchg |= LPTE_CHG;
4076 else
4077 refchg |= ret;
4078 }
4079
4080 /* Send REF/CHG bits to VM */
4081 moea64_sp_refchg_process(sp, m, refchg, oldprot);
4082
4083 /* Handle pages that became executable */
4084 if ((m->a.flags & PGA_EXECUTABLE) == 0 &&
4085 (sp->pvo_pte.pa & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) {
4086 if ((m->oflags & VPO_UNMANAGED) == 0)
4087 for (m_end = &m[HPT_SP_PAGES]; m < m_end; m++)
4088 vm_page_aflag_set(m, PGA_EXECUTABLE);
4089 moea64_syncicache(pm, PVO_VADDR(sp), PVO_PADDR(sp),
4090 HPT_SP_SIZE);
4091 }
4092
4093 return (prev);
4094 }
4095
4096 static struct pvo_entry *
moea64_sp_remove(struct pvo_entry * sp,struct pvo_dlist * tofree)4097 moea64_sp_remove(struct pvo_entry *sp, struct pvo_dlist *tofree)
4098 {
4099 struct pvo_entry *pvo, *tpvo;
4100 vm_offset_t eva;
4101 pmap_t pm __diagused;
4102
4103 CTR2(KTR_PMAP, "%s: va=%#jx", __func__, (uintmax_t)PVO_VADDR(sp));
4104
4105 pm = sp->pvo_pmap;
4106 PMAP_LOCK_ASSERT(pm, MA_OWNED);
4107
4108 eva = PVO_VADDR(sp) + HPT_SP_SIZE;
4109 for (pvo = sp; pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) {
4110 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo);
4111
4112 /*
4113 * For locking reasons, remove this from the page table and
4114 * pmap, but save delinking from the vm_page for a second
4115 * pass
4116 */
4117 moea64_pvo_remove_from_pmap(pvo);
4118 SLIST_INSERT_HEAD(tofree, pvo, pvo_dlink);
4119 }
4120
4121 /*
4122 * Clear SP bit
4123 *
4124 * XXX See comment in moea64_sp_demote_aligned() for why it's
4125 * ok to always clear the SP bit on remove/demote.
4126 */
4127 atomic_clear_32(&PHYS_TO_VM_PAGE(PVO_PADDR(sp))->md.mdpg_attrs,
4128 MDPG_ATTR_SP);
4129
4130 return (tpvo);
4131 }
4132
4133 static int64_t
moea64_sp_query_locked(struct pvo_entry * pvo,uint64_t ptebit)4134 moea64_sp_query_locked(struct pvo_entry *pvo, uint64_t ptebit)
4135 {
4136 int64_t refchg, ret;
4137 vm_offset_t eva;
4138 vm_page_t m;
4139 pmap_t pmap;
4140 struct pvo_entry *sp;
4141
4142 pmap = pvo->pvo_pmap;
4143 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4144
4145 /* Get first SP PVO */
4146 if ((PVO_VADDR(pvo) & HPT_SP_MASK) != 0) {
4147 sp = moea64_pvo_find_va(pmap, PVO_VADDR(pvo) & ~HPT_SP_MASK);
4148 KASSERT(sp != NULL, ("%s: missing PVO for va %#jx",
4149 __func__, (uintmax_t)(PVO_VADDR(pvo) & ~HPT_SP_MASK)));
4150 } else
4151 sp = pvo;
4152 eva = PVO_VADDR(sp) + HPT_SP_SIZE;
4153
4154 refchg = 0;
4155 for (pvo = sp; pvo != NULL && PVO_VADDR(pvo) < eva;
4156 pvo = RB_NEXT(pvo_tree, &pmap->pmap_pvo, pvo)) {
4157 ret = moea64_pte_synch(pvo);
4158 if (ret > 0) {
4159 refchg |= ret & (LPTE_CHG | LPTE_REF);
4160 if ((refchg & ptebit) != 0)
4161 break;
4162 }
4163 }
4164
4165 /* Save results */
4166 if (refchg != 0) {
4167 m = PHYS_TO_VM_PAGE(PVO_PADDR(sp));
4168 atomic_set_32(&m->md.mdpg_attrs, refchg | MDPG_ATTR_SP);
4169 }
4170
4171 return (refchg);
4172 }
4173
4174 static int64_t
moea64_sp_query(struct pvo_entry * pvo,uint64_t ptebit)4175 moea64_sp_query(struct pvo_entry *pvo, uint64_t ptebit)
4176 {
4177 int64_t refchg;
4178 pmap_t pmap;
4179
4180 pmap = pvo->pvo_pmap;
4181 PMAP_LOCK(pmap);
4182
4183 /*
4184 * Check if SP was demoted/removed before pmap lock was acquired.
4185 */
4186 if (!PVO_IS_SP(pvo) || (pvo->pvo_vaddr & PVO_DEAD) != 0) {
4187 CTR2(KTR_PMAP, "%s: demoted/removed: pa=%#jx",
4188 __func__, (uintmax_t)PVO_PADDR(pvo));
4189 PMAP_UNLOCK(pmap);
4190 return (-1);
4191 }
4192
4193 refchg = moea64_sp_query_locked(pvo, ptebit);
4194 PMAP_UNLOCK(pmap);
4195
4196 CTR4(KTR_PMAP, "%s: va=%#jx, pa=%#jx: refchg=%#jx",
4197 __func__, (uintmax_t)PVO_VADDR(pvo),
4198 (uintmax_t)PVO_PADDR(pvo), (uintmax_t)refchg);
4199
4200 return (refchg);
4201 }
4202
4203 static int64_t
moea64_sp_pvo_clear(struct pvo_entry * pvo,uint64_t ptebit)4204 moea64_sp_pvo_clear(struct pvo_entry *pvo, uint64_t ptebit)
4205 {
4206 int64_t refchg, ret;
4207 pmap_t pmap;
4208 struct pvo_entry *sp;
4209 vm_offset_t eva;
4210 vm_page_t m;
4211
4212 pmap = pvo->pvo_pmap;
4213 PMAP_LOCK(pmap);
4214
4215 /*
4216 * Check if SP was demoted/removed before pmap lock was acquired.
4217 */
4218 if (!PVO_IS_SP(pvo) || (pvo->pvo_vaddr & PVO_DEAD) != 0) {
4219 CTR2(KTR_PMAP, "%s: demoted/removed: pa=%#jx",
4220 __func__, (uintmax_t)PVO_PADDR(pvo));
4221 PMAP_UNLOCK(pmap);
4222 return (-1);
4223 }
4224
4225 /* Get first SP PVO */
4226 if ((PVO_VADDR(pvo) & HPT_SP_MASK) != 0) {
4227 sp = moea64_pvo_find_va(pmap, PVO_VADDR(pvo) & ~HPT_SP_MASK);
4228 KASSERT(sp != NULL, ("%s: missing PVO for va %#jx",
4229 __func__, (uintmax_t)(PVO_VADDR(pvo) & ~HPT_SP_MASK)));
4230 } else
4231 sp = pvo;
4232 eva = PVO_VADDR(sp) + HPT_SP_SIZE;
4233
4234 refchg = 0;
4235 for (pvo = sp; pvo != NULL && PVO_VADDR(pvo) < eva;
4236 pvo = RB_NEXT(pvo_tree, &pmap->pmap_pvo, pvo)) {
4237 ret = moea64_pte_clear(pvo, ptebit);
4238 if (ret > 0)
4239 refchg |= ret & (LPTE_CHG | LPTE_REF);
4240 }
4241
4242 m = PHYS_TO_VM_PAGE(PVO_PADDR(sp));
4243 atomic_clear_32(&m->md.mdpg_attrs, ptebit);
4244 PMAP_UNLOCK(pmap);
4245
4246 CTR4(KTR_PMAP, "%s: va=%#jx, pa=%#jx: refchg=%#jx",
4247 __func__, (uintmax_t)PVO_VADDR(sp),
4248 (uintmax_t)PVO_PADDR(sp), (uintmax_t)refchg);
4249
4250 return (refchg);
4251 }
4252
4253 static int64_t
moea64_sp_clear(struct pvo_entry * pvo,vm_page_t m,uint64_t ptebit)4254 moea64_sp_clear(struct pvo_entry *pvo, vm_page_t m, uint64_t ptebit)
4255 {
4256 int64_t count, ret;
4257 pmap_t pmap;
4258
4259 count = 0;
4260 pmap = pvo->pvo_pmap;
4261
4262 /*
4263 * Since this reference bit is shared by 4096 4KB pages, it
4264 * should not be cleared every time it is tested. Apply a
4265 * simple "hash" function on the physical page number, the
4266 * virtual superpage number, and the pmap address to select
4267 * one 4KB page out of the 4096 on which testing the
4268 * reference bit will result in clearing that reference bit.
4269 * This function is designed to avoid the selection of the
4270 * same 4KB page for every 16MB page mapping.
4271 *
4272 * Always leave the reference bit of a wired mapping set, as
4273 * the current state of its reference bit won't affect page
4274 * replacement.
4275 */
4276 if (ptebit == LPTE_REF && (((VM_PAGE_TO_PHYS(m) >> PAGE_SHIFT) ^
4277 (PVO_VADDR(pvo) >> HPT_SP_SHIFT) ^ (uintptr_t)pmap) &
4278 (HPT_SP_PAGES - 1)) == 0 && (pvo->pvo_vaddr & PVO_WIRED) == 0) {
4279 if ((ret = moea64_sp_pvo_clear(pvo, ptebit)) == -1)
4280 return (-1);
4281
4282 if ((ret & ptebit) != 0)
4283 count++;
4284
4285 /*
4286 * If this page was not selected by the hash function, then assume
4287 * its REF bit was set.
4288 */
4289 } else if (ptebit == LPTE_REF) {
4290 count++;
4291
4292 /*
4293 * To clear the CHG bit of a single SP page, first it must be demoted.
4294 * But if no CHG bit is set, no bit clear and thus no SP demotion is
4295 * needed.
4296 */
4297 } else {
4298 CTR4(KTR_PMAP, "%s: ptebit=%#jx, va=%#jx, pa=%#jx",
4299 __func__, (uintmax_t)ptebit, (uintmax_t)PVO_VADDR(pvo),
4300 (uintmax_t)PVO_PADDR(pvo));
4301
4302 PMAP_LOCK(pmap);
4303
4304 /*
4305 * Make sure SP wasn't demoted/removed before pmap lock
4306 * was acquired.
4307 */
4308 if (!PVO_IS_SP(pvo) || (pvo->pvo_vaddr & PVO_DEAD) != 0) {
4309 CTR2(KTR_PMAP, "%s: demoted/removed: pa=%#jx",
4310 __func__, (uintmax_t)PVO_PADDR(pvo));
4311 PMAP_UNLOCK(pmap);
4312 return (-1);
4313 }
4314
4315 ret = moea64_sp_query_locked(pvo, ptebit);
4316 if ((ret & ptebit) != 0)
4317 count++;
4318 else {
4319 PMAP_UNLOCK(pmap);
4320 return (0);
4321 }
4322
4323 moea64_sp_demote(pvo);
4324 moea64_pte_clear(pvo, ptebit);
4325
4326 /*
4327 * Write protect the mapping to a single page so that a
4328 * subsequent write access may repromote.
4329 */
4330 if ((pvo->pvo_vaddr & PVO_WIRED) == 0)
4331 moea64_pvo_protect(pmap, pvo,
4332 pvo->pvo_pte.prot & ~VM_PROT_WRITE);
4333
4334 PMAP_UNLOCK(pmap);
4335 }
4336
4337 return (count);
4338 }
4339