1 /* 2 * 3 * Copyright (C) 2016 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included 13 * in all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 16 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 19 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #ifndef OSS_1_0_D_H 24 #define OSS_1_0_D_H 25 26 #define ixCLIENT0_BM 0x0220 27 #define ixCLIENT0_CD0 0x0210 28 #define ixCLIENT0_CD1 0x0214 29 #define ixCLIENT0_CD2 0x0218 30 #define ixCLIENT0_CD3 0x021C 31 #define ixCLIENT0_CK0 0x0200 32 #define ixCLIENT0_CK1 0x0204 33 #define ixCLIENT0_CK2 0x0208 34 #define ixCLIENT0_CK3 0x020C 35 #define ixCLIENT0_K0 0x01F0 36 #define ixCLIENT0_K1 0x01F4 37 #define ixCLIENT0_K2 0x01F8 38 #define ixCLIENT0_K3 0x01FC 39 #define ixCLIENT0_OFFSET 0x0224 40 #define ixCLIENT0_OFFSET_HI 0x0290 41 #define ixCLIENT0_STATUS 0x0228 42 #define ixCLIENT1_BM 0x025C 43 #define ixCLIENT1_CD0 0x024C 44 #define ixCLIENT1_CD1 0x0250 45 #define ixCLIENT1_CD2 0x0254 46 #define ixCLIENT1_CD3 0x0258 47 #define ixCLIENT1_CK0 0x023C 48 #define ixCLIENT1_CK1 0x0240 49 #define ixCLIENT1_CK2 0x0244 50 #define ixCLIENT1_CK3 0x0248 51 #define ixCLIENT1_K0 0x022C 52 #define ixCLIENT1_K1 0x0230 53 #define ixCLIENT1_K2 0x0234 54 #define ixCLIENT1_K3 0x0238 55 #define ixCLIENT1_OFFSET 0x0260 56 #define ixCLIENT1_OFFSET_HI 0x0294 57 #define ixCLIENT1_PORT_STATUS 0x0264 58 #define ixCLIENT2_BM 0x01E4 59 #define ixCLIENT2_CD0 0x01D4 60 #define ixCLIENT2_CD1 0x01D8 61 #define ixCLIENT2_CD2 0x01DC 62 #define ixCLIENT2_CD3 0x01E0 63 #define ixCLIENT2_CK0 0x01C4 64 #define ixCLIENT2_CK1 0x01C8 65 #define ixCLIENT2_CK2 0x01CC 66 #define ixCLIENT2_CK3 0x01D0 67 #define ixCLIENT2_K0 0x01B4 68 #define ixCLIENT2_K1 0x01B8 69 #define ixCLIENT2_K2 0x01BC 70 #define ixCLIENT2_K3 0x01C0 71 #define ixCLIENT2_OFFSET 0x01E8 72 #define ixCLIENT2_OFFSET_HI 0x0298 73 #define ixCLIENT2_STATUS 0x01EC 74 #define ixCLIENT3_BM 0x02D4 75 #define ixCLIENT3_CD0 0x02C4 76 #define ixCLIENT3_CD1 0x02C8 77 #define ixCLIENT3_CD2 0x02CC 78 #define ixCLIENT3_CD3 0x02D0 79 #define ixCLIENT3_CK0 0x02B4 80 #define ixCLIENT3_CK1 0x02B8 81 #define ixCLIENT3_CK2 0x02BC 82 #define ixCLIENT3_CK3 0x02C0 83 #define ixCLIENT3_K0 0x02A4 84 #define ixCLIENT3_K1 0x02A8 85 #define ixCLIENT3_K2 0x02AC 86 #define ixCLIENT3_K3 0x02B0 87 #define ixCLIENT3_OFFSET 0x02D8 88 #define ixCLIENT3_OFFSET_HI 0x02A0 89 #define ixCLIENT3_STATUS 0x02DC 90 #define ixDH_TEST 0x0000 91 #define ixEXP0 0x0034 92 #define ixEXP1 0x0038 93 #define ixEXP2 0x003C 94 #define ixEXP3 0x0040 95 #define ixEXP4 0x0044 96 #define ixEXP5 0x0048 97 #define ixEXP6 0x004C 98 #define ixEXP7 0x0050 99 #define ixHFS_SEED0 0x0278 100 #define ixHFS_SEED1 0x027C 101 #define ixHFS_SEED2 0x0280 102 #define ixHFS_SEED3 0x0284 103 #define ixKEFUSE0 0x0268 104 #define ixKEFUSE1 0x026C 105 #define ixKEFUSE2 0x0270 106 #define ixKEFUSE3 0x0274 107 #define ixKHFS0 0x0004 108 #define ixKHFS1 0x0008 109 #define ixKHFS2 0x000C 110 #define ixKHFS3 0x0010 111 #define ixKSESSION0 0x0014 112 #define ixKSESSION1 0x0018 113 #define ixKSESSION2 0x001C 114 #define ixKSESSION3 0x0020 115 #define ixKSIG0 0x0024 116 #define ixKSIG1 0x0028 117 #define ixKSIG2 0x002C 118 #define ixKSIG3 0x0030 119 #define ixLX0 0x0054 120 #define ixLX1 0x0058 121 #define ixLX2 0x005C 122 #define ixLX3 0x0060 123 #define ixRINGOSC_MASK 0x0288 124 #define ixSPU_PORT_STATUS 0x029C 125 #define mmCC_DRM_ID_STRAPS 0x1559 126 #define mmCC_SYS_RB_BACKEND_DISABLE 0x03A0 127 #define mmCC_SYS_RB_REDUNDANCY 0x039F 128 #define mmCGTT_DRM_CLK_CTRL0 0x1579 129 #define mmCP_CONFIG 0x0F92 130 #define mmDC_TEST_DEBUG_DATA 0x157D 131 #define mmDC_TEST_DEBUG_INDEX 0x157C 132 #define mmGC_USER_SYS_RB_BACKEND_DISABLE 0x03A1 133 #define mmHDP_ADDR_CONFIG 0x0BD2 134 #define mmHDP_DEBUG0 0x0BCC 135 #define mmHDP_DEBUG1 0x0BCD 136 #define mmHDP_HOST_PATH_CNTL 0x0B00 137 #define mmHDP_LAST_SURFACE_HIT 0x0BCE 138 #define mmHDP_MEMIO_ADDR 0x0BF7 139 #define mmHDP_MEMIO_CNTL 0x0BF6 140 #define mmHDP_MEMIO_RD_DATA 0x0BFA 141 #define mmHDP_MEMIO_STATUS 0x0BF8 142 #define mmHDP_MEMIO_WR_DATA 0x0BF9 143 #define mmHDP_MEM_POWER_LS 0x0BD4 144 #define mmHDP_MISC_CNTL 0x0BD3 145 #define mmHDP_NONSURFACE_BASE 0x0B01 146 #define mmHDP_NONSURFACE_INFO 0x0B02 147 #define mmHDP_NONSURFACE_PREFETCH 0x0BD5 148 #define mmHDP_NONSURFACE_SIZE 0x0B03 149 #define mmHDP_NONSURF_FLAGS 0x0BC9 150 #define mmHDP_NONSURF_FLAGS_CLR 0x0BCA 151 #define mmHDP_OUTSTANDING_REQ 0x0BD1 152 #define mmHDP_SC_MULTI_CHIP_CNTL 0x0BD0 153 #define mmHDP_SW_SEMAPHORE 0x0BCB 154 #define mmHDP_TILING_CONFIG 0x0BCF 155 #define mmHDP_XDP_BARS_ADDR_39_36 0x0C44 156 #define mmHDP_XDP_BUSY_STS 0x0C3E 157 #define mmHDP_XDP_CGTT_BLK_CTRL 0x0C33 158 #define mmHDP_XDP_CHKN 0x0C40 159 #define mmHDP_XDP_D2H_BAR_UPDATE 0x0C02 160 #define mmHDP_XDP_D2H_FLUSH 0x0C01 161 #define mmHDP_XDP_D2H_RSVD_10 0x0C0A 162 #define mmHDP_XDP_D2H_RSVD_11 0x0C0B 163 #define mmHDP_XDP_D2H_RSVD_12 0x0C0C 164 #define mmHDP_XDP_D2H_RSVD_13 0x0C0D 165 #define mmHDP_XDP_D2H_RSVD_14 0x0C0E 166 #define mmHDP_XDP_D2H_RSVD_15 0x0C0F 167 #define mmHDP_XDP_D2H_RSVD_16 0x0C10 168 #define mmHDP_XDP_D2H_RSVD_17 0x0C11 169 #define mmHDP_XDP_D2H_RSVD_18 0x0C12 170 #define mmHDP_XDP_D2H_RSVD_19 0x0C13 171 #define mmHDP_XDP_D2H_RSVD_20 0x0C14 172 #define mmHDP_XDP_D2H_RSVD_21 0x0C15 173 #define mmHDP_XDP_D2H_RSVD_22 0x0C16 174 #define mmHDP_XDP_D2H_RSVD_23 0x0C17 175 #define mmHDP_XDP_D2H_RSVD_24 0x0C18 176 #define mmHDP_XDP_D2H_RSVD_25 0x0C19 177 #define mmHDP_XDP_D2H_RSVD_26 0x0C1A 178 #define mmHDP_XDP_D2H_RSVD_27 0x0C1B 179 #define mmHDP_XDP_D2H_RSVD_28 0x0C1C 180 #define mmHDP_XDP_D2H_RSVD_29 0x0C1D 181 #define mmHDP_XDP_D2H_RSVD_30 0x0C1E 182 #define mmHDP_XDP_D2H_RSVD_3 0x0C03 183 #define mmHDP_XDP_D2H_RSVD_31 0x0C1F 184 #define mmHDP_XDP_D2H_RSVD_32 0x0C20 185 #define mmHDP_XDP_D2H_RSVD_33 0x0C21 186 #define mmHDP_XDP_D2H_RSVD_34 0x0C22 187 #define mmHDP_XDP_D2H_RSVD_4 0x0C04 188 #define mmHDP_XDP_D2H_RSVD_5 0x0C05 189 #define mmHDP_XDP_D2H_RSVD_6 0x0C06 190 #define mmHDP_XDP_D2H_RSVD_7 0x0C07 191 #define mmHDP_XDP_D2H_RSVD_8 0x0C08 192 #define mmHDP_XDP_D2H_RSVD_9 0x0C09 193 #define mmHDP_XDP_DBG_ADDR 0x0C41 194 #define mmHDP_XDP_DBG_DATA 0x0C42 195 #define mmHDP_XDP_DBG_MASK 0x0C43 196 #define mmHDP_XDP_DIRECT2HDP_FIRST 0x0C00 197 #define mmHDP_XDP_DIRECT2HDP_LAST 0x0C23 198 #define mmHDP_XDP_FLUSH_ARMED_STS 0x0C3C 199 #define mmHDP_XDP_FLUSH_CNTR0_STS 0x0C3D 200 #define mmHDP_XDP_HDP_IPH_CFG 0x0C31 201 #define mmHDP_XDP_HDP_MBX_MC_CFG 0x0C2D 202 #define mmHDP_XDP_HDP_MC_CFG 0x0C2E 203 #define mmHDP_XDP_HST_CFG 0x0C2F 204 #define mmHDP_XDP_P2P_BAR0 0x0C34 205 #define mmHDP_XDP_P2P_BAR1 0x0C35 206 #define mmHDP_XDP_P2P_BAR2 0x0C36 207 #define mmHDP_XDP_P2P_BAR3 0x0C37 208 #define mmHDP_XDP_P2P_BAR4 0x0C38 209 #define mmHDP_XDP_P2P_BAR5 0x0C39 210 #define mmHDP_XDP_P2P_BAR6 0x0C3A 211 #define mmHDP_XDP_P2P_BAR7 0x0C3B 212 #define mmHDP_XDP_P2P_BAR_CFG 0x0C24 213 #define mmHDP_XDP_P2P_MBX_ADDR0 0x0C26 214 #define mmHDP_XDP_P2P_MBX_ADDR1 0x0C27 215 #define mmHDP_XDP_P2P_MBX_ADDR2 0x0C28 216 #define mmHDP_XDP_P2P_MBX_ADDR3 0x0C29 217 #define mmHDP_XDP_P2P_MBX_ADDR4 0x0C2A 218 #define mmHDP_XDP_P2P_MBX_ADDR5 0x0C2B 219 #define mmHDP_XDP_P2P_MBX_ADDR6 0x0C2C 220 #define mmHDP_XDP_P2P_MBX_OFFSET 0x0C25 221 #define mmHDP_XDP_SID_CFG 0x0C30 222 #define mmHDP_XDP_SRBM_CFG 0x0C32 223 #define mmHDP_XDP_STICKY 0x0C3F 224 #define mmIH_ADVFAULT_CNTL 0x0F8C 225 #define mmIH_CNTL 0x0F86 226 #define mmIH_LEVEL_STATUS 0x0F87 227 #define mmIH_PERFCOUNTER0_RESULT 0x0F8A 228 #define mmIH_PERFCOUNTER1_RESULT 0x0F8B 229 #define mmIH_PERFMON_CNTL 0x0F89 230 #define mmIH_RB_BASE 0x0F81 231 #define mmIH_RB_CNTL 0x0F80 232 #define mmIH_RB_RPTR 0x0F82 233 #define mmIH_RB_WPTR 0x0F83 234 #define mmIH_RB_WPTR_ADDR_HI 0x0F84 235 #define mmIH_RB_WPTR_ADDR_LO 0x0F85 236 #define mmIH_STATUS 0x0F88 237 #define mmSEM_MAILBOX 0x0F9B 238 #define mmSEM_MAILBOX_CLIENTCONFIG 0x0F9A 239 #define mmSEM_MAILBOX_CONTROL 0x0F9C 240 #define mmSEM_MCIF_CONFIG 0x0F90 241 #define mmSRBM_CAM_DATA 0x0397 242 #define mmSRBM_CAM_INDEX 0x0396 243 #define mmSRBM_CHIP_REVISION 0x039B 244 #define mmSRBM_CNTL 0x0390 245 #define mmSRBM_DEBUG 0x03A4 246 #define mmSRBM_DEBUG_CNTL 0x0399 247 #define mmSRBM_DEBUG_DATA 0x039A 248 #define mmSRBM_DEBUG_SNAPSHOT 0x03A5 249 #define mmSRBM_GFX_CNTL 0x0391 250 #define mmSRBM_INT_ACK 0x03AA 251 #define mmSRBM_INT_CNTL 0x03A8 252 #define mmSRBM_INT_STATUS 0x03A9 253 #define mmSRBM_MC_CLKEN_CNTL 0x03B3 254 #define mmSRBM_PERFCOUNTER0_HI 0x0704 255 #define mmSRBM_PERFCOUNTER0_LO 0x0703 256 #define mmSRBM_PERFCOUNTER0_SELECT 0x0701 257 #define mmSRBM_PERFCOUNTER1_HI 0x0706 258 #define mmSRBM_PERFCOUNTER1_LO 0x0705 259 #define mmSRBM_PERFCOUNTER1_SELECT 0x0702 260 #define mmSRBM_PERFMON_CNTL 0x0700 261 #define mmSRBM_READ_ERROR 0x03A6 262 #define mmSRBM_SOFT_RESET 0x0398 263 #define mmSRBM_STATUS 0x0394 264 #define mmSRBM_STATUS2 0x0393 265 #define mmSRBM_SYS_CLKEN_CNTL 0x03B4 266 #define mmSRBM_UVD_CLKEN_CNTL 0x03B6 267 #define mmSRBM_VCE_CLKEN_CNTL 0x03B5 268 #define mmUVD_CONFIG 0x0F98 269 #define mmVCE_CONFIG 0x0F94 270 #define mmXDMA_MSTR_MEM_OVERFLOW_CNTL 0x03F8 271 272 /* from the old sid.h */ 273 #define mmDMA_TILING_CONFIG 0x342E 274 275 #endif 276