1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/pci.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/slab.h>
40 #include <linux/interrupt.h>
41 #include <linux/delay.h>
42 #include <linux/mlx5/driver.h>
43 #include <linux/mlx5/cq.h>
44 #include <linux/mlx5/qp.h>
45 #include <linux/debugfs.h>
46 #include <linux/kmod.h>
47 #include <linux/mlx5/mlx5_ifc.h>
48 #include <linux/mlx5/vport.h>
49 #include <linux/version.h>
50 #include <net/devlink.h>
51 #include "mlx5_core.h"
52 #include "lib/eq.h"
53 #include "fs_core.h"
54 #include "lib/mpfs.h"
55 #include "eswitch.h"
56 #include "devlink.h"
57 #include "fw_reset.h"
58 #include "lib/mlx5.h"
59 #include "lib/tout.h"
60 #include "fpga/core.h"
61 #include "en_accel/ipsec.h"
62 #include "lib/clock.h"
63 #include "lib/vxlan.h"
64 #include "lib/geneve.h"
65 #include "lib/devcom.h"
66 #include "lib/pci_vsc.h"
67 #include "diag/fw_tracer.h"
68 #include "ecpf.h"
69 #include "lib/hv_vhca.h"
70 #include "diag/rsc_dump.h"
71 #include "sf/vhca_event.h"
72 #include "sf/dev/dev.h"
73 #include "sf/sf.h"
74 #include "mlx5_irq.h"
75 #include "hwmon.h"
76 #include "lag/lag.h"
77
78 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
79 MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) core driver");
80 MODULE_LICENSE("Dual BSD/GPL");
81
82 unsigned int mlx5_core_debug_mask;
83 module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644);
84 MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
85
86 static unsigned int prof_sel = MLX5_DEFAULT_PROF;
87 module_param_named(prof_sel, prof_sel, uint, 0444);
88 MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
89
90 static u32 sw_owner_id[4];
91 #define MAX_SW_VHCA_ID (BIT(__mlx5_bit_sz(cmd_hca_cap_2, sw_vhca_id)) - 1)
92 static DEFINE_IDA(sw_vhca_ida);
93
94 enum {
95 MLX5_ATOMIC_REQ_MODE_BE = 0x0,
96 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1,
97 };
98
99 #define LOG_MAX_SUPPORTED_QPS 0xff
100
101 static struct mlx5_profile profile[] = {
102 [0] = {
103 .mask = 0,
104 .num_cmd_caches = MLX5_NUM_COMMAND_CACHES,
105 },
106 [1] = {
107 .mask = MLX5_PROF_MASK_QP_SIZE,
108 .log_max_qp = 12,
109 .num_cmd_caches = MLX5_NUM_COMMAND_CACHES,
110
111 },
112 [2] = {
113 .mask = MLX5_PROF_MASK_QP_SIZE |
114 MLX5_PROF_MASK_MR_CACHE,
115 .log_max_qp = LOG_MAX_SUPPORTED_QPS,
116 .num_cmd_caches = MLX5_NUM_COMMAND_CACHES,
117 .mr_cache[0] = {
118 .size = 500,
119 .limit = 250
120 },
121 .mr_cache[1] = {
122 .size = 500,
123 .limit = 250
124 },
125 .mr_cache[2] = {
126 .size = 500,
127 .limit = 250
128 },
129 .mr_cache[3] = {
130 .size = 500,
131 .limit = 250
132 },
133 .mr_cache[4] = {
134 .size = 500,
135 .limit = 250
136 },
137 .mr_cache[5] = {
138 .size = 500,
139 .limit = 250
140 },
141 .mr_cache[6] = {
142 .size = 500,
143 .limit = 250
144 },
145 .mr_cache[7] = {
146 .size = 500,
147 .limit = 250
148 },
149 .mr_cache[8] = {
150 .size = 500,
151 .limit = 250
152 },
153 .mr_cache[9] = {
154 .size = 500,
155 .limit = 250
156 },
157 .mr_cache[10] = {
158 .size = 500,
159 .limit = 250
160 },
161 .mr_cache[11] = {
162 .size = 500,
163 .limit = 250
164 },
165 .mr_cache[12] = {
166 .size = 64,
167 .limit = 32
168 },
169 .mr_cache[13] = {
170 .size = 32,
171 .limit = 16
172 },
173 .mr_cache[14] = {
174 .size = 16,
175 .limit = 8
176 },
177 .mr_cache[15] = {
178 .size = 8,
179 .limit = 4
180 },
181 },
182 [3] = {
183 .mask = MLX5_PROF_MASK_QP_SIZE,
184 .log_max_qp = LOG_MAX_SUPPORTED_QPS,
185 .num_cmd_caches = 0,
186 },
187 };
188
wait_fw_init(struct mlx5_core_dev * dev,u32 max_wait_mili,u32 warn_time_mili,const char * init_state)189 static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili,
190 u32 warn_time_mili, const char *init_state)
191 {
192 unsigned long warn = jiffies + msecs_to_jiffies(warn_time_mili);
193 unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili);
194 u32 fw_initializing;
195
196 do {
197 fw_initializing = ioread32be(&dev->iseg->initializing);
198 if (!(fw_initializing >> 31))
199 break;
200 if (time_after(jiffies, end)) {
201 mlx5_core_err(dev, "Firmware over %u MS in %s state, aborting\n",
202 max_wait_mili, init_state);
203 return -ETIMEDOUT;
204 }
205 if (test_bit(MLX5_BREAK_FW_WAIT, &dev->intf_state)) {
206 mlx5_core_warn(dev, "device is being removed, stop waiting for FW %s\n",
207 init_state);
208 return -ENODEV;
209 }
210 if (warn_time_mili && time_after(jiffies, warn)) {
211 mlx5_core_warn(dev, "Waiting for FW %s, timeout abort in %ds (0x%x)\n",
212 init_state, jiffies_to_msecs(end - warn) / 1000,
213 fw_initializing);
214 warn = jiffies + msecs_to_jiffies(warn_time_mili);
215 }
216 msleep(mlx5_tout_ms(dev, FW_PRE_INIT_WAIT));
217 } while (true);
218
219 return 0;
220 }
221
mlx5_set_driver_version(struct mlx5_core_dev * dev)222 static void mlx5_set_driver_version(struct mlx5_core_dev *dev)
223 {
224 int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in,
225 driver_version);
226 u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {};
227 char *string;
228
229 if (!MLX5_CAP_GEN(dev, driver_version))
230 return;
231
232 string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version);
233
234 snprintf(string, driver_ver_sz, "Linux,%s,%u.%u.%u",
235 KBUILD_MODNAME, LINUX_VERSION_MAJOR,
236 LINUX_VERSION_PATCHLEVEL, LINUX_VERSION_SUBLEVEL);
237
238 /*Send the command*/
239 MLX5_SET(set_driver_version_in, in, opcode,
240 MLX5_CMD_OP_SET_DRIVER_VERSION);
241
242 mlx5_cmd_exec_in(dev, set_driver_version, in);
243 }
244
set_dma_caps(struct pci_dev * pdev)245 static int set_dma_caps(struct pci_dev *pdev)
246 {
247 int err;
248
249 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
250 if (err) {
251 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
252 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
253 if (err) {
254 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
255 return err;
256 }
257 }
258
259 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
260 return err;
261 }
262
mlx5_pci_enable_device(struct mlx5_core_dev * dev)263 static int mlx5_pci_enable_device(struct mlx5_core_dev *dev)
264 {
265 struct pci_dev *pdev = dev->pdev;
266 int err = 0;
267
268 mutex_lock(&dev->pci_status_mutex);
269 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) {
270 err = pci_enable_device(pdev);
271 if (!err)
272 dev->pci_status = MLX5_PCI_STATUS_ENABLED;
273 }
274 mutex_unlock(&dev->pci_status_mutex);
275
276 return err;
277 }
278
mlx5_pci_disable_device(struct mlx5_core_dev * dev)279 static void mlx5_pci_disable_device(struct mlx5_core_dev *dev)
280 {
281 struct pci_dev *pdev = dev->pdev;
282
283 mutex_lock(&dev->pci_status_mutex);
284 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) {
285 pci_disable_device(pdev);
286 dev->pci_status = MLX5_PCI_STATUS_DISABLED;
287 }
288 mutex_unlock(&dev->pci_status_mutex);
289 }
290
request_bar(struct pci_dev * pdev)291 static int request_bar(struct pci_dev *pdev)
292 {
293 int err = 0;
294
295 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
296 dev_err(&pdev->dev, "Missing registers BAR, aborting\n");
297 return -ENODEV;
298 }
299
300 err = pci_request_regions(pdev, KBUILD_MODNAME);
301 if (err)
302 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
303
304 return err;
305 }
306
release_bar(struct pci_dev * pdev)307 static void release_bar(struct pci_dev *pdev)
308 {
309 pci_release_regions(pdev);
310 }
311
312 struct mlx5_reg_host_endianness {
313 u8 he;
314 u8 rsvd[15];
315 };
316
to_fw_pkey_sz(struct mlx5_core_dev * dev,u32 size)317 static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size)
318 {
319 switch (size) {
320 case 128:
321 return 0;
322 case 256:
323 return 1;
324 case 512:
325 return 2;
326 case 1024:
327 return 3;
328 case 2048:
329 return 4;
330 case 4096:
331 return 5;
332 default:
333 mlx5_core_warn(dev, "invalid pkey table size %d\n", size);
334 return 0;
335 }
336 }
337
mlx5_core_uplink_netdev_set(struct mlx5_core_dev * dev,struct net_device * netdev)338 void mlx5_core_uplink_netdev_set(struct mlx5_core_dev *dev, struct net_device *netdev)
339 {
340 mutex_lock(&dev->mlx5e_res.uplink_netdev_lock);
341 dev->mlx5e_res.uplink_netdev = netdev;
342 mlx5_blocking_notifier_call_chain(dev, MLX5_DRIVER_EVENT_UPLINK_NETDEV,
343 netdev);
344 mutex_unlock(&dev->mlx5e_res.uplink_netdev_lock);
345 }
346
mlx5_core_uplink_netdev_event_replay(struct mlx5_core_dev * dev)347 void mlx5_core_uplink_netdev_event_replay(struct mlx5_core_dev *dev)
348 {
349 mutex_lock(&dev->mlx5e_res.uplink_netdev_lock);
350 mlx5_blocking_notifier_call_chain(dev, MLX5_DRIVER_EVENT_UPLINK_NETDEV,
351 dev->mlx5e_res.uplink_netdev);
352 mutex_unlock(&dev->mlx5e_res.uplink_netdev_lock);
353 }
354 EXPORT_SYMBOL(mlx5_core_uplink_netdev_event_replay);
355
mlx5_core_mp_event_replay(struct mlx5_core_dev * dev,u32 event,void * data)356 void mlx5_core_mp_event_replay(struct mlx5_core_dev *dev, u32 event, void *data)
357 {
358 mlx5_blocking_notifier_call_chain(dev, event, data);
359 }
360 EXPORT_SYMBOL(mlx5_core_mp_event_replay);
361
mlx5_core_get_caps_mode(struct mlx5_core_dev * dev,enum mlx5_cap_type cap_type,enum mlx5_cap_mode cap_mode)362 int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type,
363 enum mlx5_cap_mode cap_mode)
364 {
365 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
366 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
367 void *out, *hca_caps;
368 u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
369 int err;
370
371 memset(in, 0, sizeof(in));
372 out = kzalloc(out_sz, GFP_KERNEL);
373 if (!out)
374 return -ENOMEM;
375
376 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
377 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
378 err = mlx5_cmd_exec_inout(dev, query_hca_cap, in, out);
379 if (err) {
380 mlx5_core_warn(dev,
381 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
382 cap_type, cap_mode, err);
383 goto query_ex;
384 }
385
386 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
387
388 switch (cap_mode) {
389 case HCA_CAP_OPMOD_GET_MAX:
390 memcpy(dev->caps.hca[cap_type]->max, hca_caps,
391 MLX5_UN_SZ_BYTES(hca_cap_union));
392 break;
393 case HCA_CAP_OPMOD_GET_CUR:
394 memcpy(dev->caps.hca[cap_type]->cur, hca_caps,
395 MLX5_UN_SZ_BYTES(hca_cap_union));
396 break;
397 default:
398 mlx5_core_warn(dev,
399 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
400 cap_type, cap_mode);
401 err = -EINVAL;
402 break;
403 }
404 query_ex:
405 kfree(out);
406 return err;
407 }
408
mlx5_core_get_caps(struct mlx5_core_dev * dev,enum mlx5_cap_type cap_type)409 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type)
410 {
411 int ret;
412
413 ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR);
414 if (ret)
415 return ret;
416 return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX);
417 }
418
set_caps(struct mlx5_core_dev * dev,void * in,int opmod)419 static int set_caps(struct mlx5_core_dev *dev, void *in, int opmod)
420 {
421 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
422 MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1);
423 return mlx5_cmd_exec_in(dev, set_hca_cap, in);
424 }
425
handle_hca_cap_atomic(struct mlx5_core_dev * dev,void * set_ctx)426 static int handle_hca_cap_atomic(struct mlx5_core_dev *dev, void *set_ctx)
427 {
428 void *set_hca_cap;
429 int req_endianness;
430 int err;
431
432 if (!MLX5_CAP_GEN(dev, atomic))
433 return 0;
434
435 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC);
436 if (err)
437 return err;
438
439 req_endianness =
440 MLX5_CAP_ATOMIC(dev,
441 supported_atomic_req_8B_endianness_mode_1);
442
443 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS)
444 return 0;
445
446 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
447
448 /* Set requestor to host endianness */
449 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianness_mode,
450 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS);
451
452 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC);
453 }
454
handle_hca_cap_odp(struct mlx5_core_dev * dev,void * set_ctx)455 static int handle_hca_cap_odp(struct mlx5_core_dev *dev, void *set_ctx)
456 {
457 bool do_set = false, mem_page_fault = false;
458 void *set_hca_cap;
459 int err;
460
461 if (!IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) ||
462 !MLX5_CAP_GEN(dev, pg))
463 return 0;
464
465 err = mlx5_core_get_caps(dev, MLX5_CAP_ODP);
466 if (err)
467 return err;
468
469 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
470 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_ODP]->cur,
471 MLX5_ST_SZ_BYTES(odp_cap));
472
473 /* For best performance, enable memory scheme ODP only when
474 * it has page prefetch enabled.
475 */
476 if (MLX5_CAP_ODP_MAX(dev, mem_page_fault) &&
477 MLX5_CAP_ODP_MAX(dev, memory_page_fault_scheme_cap.page_prefetch)) {
478 mem_page_fault = true;
479 do_set = true;
480 MLX5_SET(odp_cap, set_hca_cap, mem_page_fault, mem_page_fault);
481 goto set;
482 }
483
484 #define ODP_CAP_SET_MAX(dev, field) \
485 do { \
486 u32 _res = MLX5_CAP_ODP_MAX(dev, field); \
487 if (_res) { \
488 do_set = true; \
489 MLX5_SET(odp_cap, set_hca_cap, field, _res); \
490 } \
491 } while (0)
492
493 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.ud_odp_caps.srq_receive);
494 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.rc_odp_caps.srq_receive);
495 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.xrc_odp_caps.srq_receive);
496 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.xrc_odp_caps.send);
497 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.xrc_odp_caps.receive);
498 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.xrc_odp_caps.write);
499 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.xrc_odp_caps.read);
500 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.xrc_odp_caps.atomic);
501 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.dc_odp_caps.srq_receive);
502 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.dc_odp_caps.send);
503 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.dc_odp_caps.receive);
504 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.dc_odp_caps.write);
505 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.dc_odp_caps.read);
506 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.dc_odp_caps.atomic);
507
508 set:
509 if (do_set)
510 err = set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ODP);
511
512 mlx5_core_dbg(dev, "Using ODP %s scheme\n",
513 mem_page_fault ? "memory" : "transport");
514 return err;
515 }
516
max_uc_list_get_devlink_param(struct mlx5_core_dev * dev)517 static int max_uc_list_get_devlink_param(struct mlx5_core_dev *dev)
518 {
519 struct devlink *devlink = priv_to_devlink(dev);
520 union devlink_param_value val;
521 int err;
522
523 err = devl_param_driverinit_value_get(devlink,
524 DEVLINK_PARAM_GENERIC_ID_MAX_MACS,
525 &val);
526 if (!err)
527 return val.vu32;
528 mlx5_core_dbg(dev, "Failed to get param. err = %d\n", err);
529 return err;
530 }
531
mlx5_is_roce_on(struct mlx5_core_dev * dev)532 bool mlx5_is_roce_on(struct mlx5_core_dev *dev)
533 {
534 struct devlink *devlink = priv_to_devlink(dev);
535 union devlink_param_value val;
536 int err;
537
538 err = devl_param_driverinit_value_get(devlink,
539 DEVLINK_PARAM_GENERIC_ID_ENABLE_ROCE,
540 &val);
541
542 if (!err)
543 return val.vbool;
544
545 mlx5_core_dbg(dev, "Failed to get param. err = %d\n", err);
546 return MLX5_CAP_GEN(dev, roce);
547 }
548 EXPORT_SYMBOL(mlx5_is_roce_on);
549
handle_hca_cap_2(struct mlx5_core_dev * dev,void * set_ctx)550 static int handle_hca_cap_2(struct mlx5_core_dev *dev, void *set_ctx)
551 {
552 void *set_hca_cap;
553 int err;
554
555 if (!MLX5_CAP_GEN_MAX(dev, hca_cap_2))
556 return 0;
557
558 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL_2);
559 if (err)
560 return err;
561
562 if (!MLX5_CAP_GEN_2_MAX(dev, sw_vhca_id_valid) ||
563 !(dev->priv.sw_vhca_id > 0))
564 return 0;
565
566 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
567 capability);
568 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_GENERAL_2]->cur,
569 MLX5_ST_SZ_BYTES(cmd_hca_cap_2));
570 MLX5_SET(cmd_hca_cap_2, set_hca_cap, sw_vhca_id_valid, 1);
571
572 return set_caps(dev, set_ctx, MLX5_CAP_GENERAL_2);
573 }
574
handle_hca_cap(struct mlx5_core_dev * dev,void * set_ctx)575 static int handle_hca_cap(struct mlx5_core_dev *dev, void *set_ctx)
576 {
577 struct mlx5_profile *prof = &dev->profile;
578 void *set_hca_cap;
579 int max_uc_list;
580 int err;
581
582 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL);
583 if (err)
584 return err;
585
586 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
587 capability);
588 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_GENERAL]->cur,
589 MLX5_ST_SZ_BYTES(cmd_hca_cap));
590
591 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
592 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
593 128);
594 /* we limit the size of the pkey table to 128 entries for now */
595 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
596 to_fw_pkey_sz(dev, 128));
597
598 /* Check log_max_qp from HCA caps to set in current profile */
599 if (prof->log_max_qp == LOG_MAX_SUPPORTED_QPS) {
600 prof->log_max_qp = min_t(u8, 18, MLX5_CAP_GEN_MAX(dev, log_max_qp));
601 } else if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < prof->log_max_qp) {
602 mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n",
603 prof->log_max_qp,
604 MLX5_CAP_GEN_MAX(dev, log_max_qp));
605 prof->log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp);
606 }
607 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
608 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
609 prof->log_max_qp);
610
611 /* disable cmdif checksum */
612 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
613
614 /* Enable 4K UAR only when HCA supports it and page size is bigger
615 * than 4K.
616 */
617 if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096)
618 MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1);
619
620 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
621
622 if (MLX5_CAP_GEN_MAX(dev, cache_line_128byte))
623 MLX5_SET(cmd_hca_cap,
624 set_hca_cap,
625 cache_line_128byte,
626 cache_line_size() >= 128 ? 1 : 0);
627
628 if (MLX5_CAP_GEN_MAX(dev, dct))
629 MLX5_SET(cmd_hca_cap, set_hca_cap, dct, 1);
630
631 if (MLX5_CAP_GEN_MAX(dev, pci_sync_for_fw_update_event))
632 MLX5_SET(cmd_hca_cap, set_hca_cap, pci_sync_for_fw_update_event, 1);
633 if (MLX5_CAP_GEN_MAX(dev, pci_sync_for_fw_update_with_driver_unload))
634 MLX5_SET(cmd_hca_cap, set_hca_cap,
635 pci_sync_for_fw_update_with_driver_unload, 1);
636 if (MLX5_CAP_GEN_MAX(dev, pcie_reset_using_hotreset_method))
637 MLX5_SET(cmd_hca_cap, set_hca_cap,
638 pcie_reset_using_hotreset_method, 1);
639
640 if (MLX5_CAP_GEN_MAX(dev, num_vhca_ports))
641 MLX5_SET(cmd_hca_cap,
642 set_hca_cap,
643 num_vhca_ports,
644 MLX5_CAP_GEN_MAX(dev, num_vhca_ports));
645
646 if (MLX5_CAP_GEN_MAX(dev, release_all_pages))
647 MLX5_SET(cmd_hca_cap, set_hca_cap, release_all_pages, 1);
648
649 if (MLX5_CAP_GEN_MAX(dev, mkey_by_name))
650 MLX5_SET(cmd_hca_cap, set_hca_cap, mkey_by_name, 1);
651
652 mlx5_vhca_state_cap_handle(dev, set_hca_cap);
653
654 if (MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix))
655 MLX5_SET(cmd_hca_cap, set_hca_cap, num_total_dynamic_vf_msix,
656 MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix));
657
658 if (MLX5_CAP_GEN(dev, roce_rw_supported) && MLX5_CAP_GEN_MAX(dev, roce))
659 MLX5_SET(cmd_hca_cap, set_hca_cap, roce,
660 mlx5_is_roce_on(dev));
661
662 max_uc_list = max_uc_list_get_devlink_param(dev);
663 if (max_uc_list > 0)
664 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_current_uc_list,
665 ilog2(max_uc_list));
666
667 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE);
668 }
669
670 /* Cached MLX5_CAP_GEN(dev, roce) can be out of sync this early in the
671 * boot process.
672 * In case RoCE cap is writable in FW and user/devlink requested to change the
673 * cap, we are yet to query the final state of the above cap.
674 * Hence, the need for this function.
675 *
676 * Returns
677 * True:
678 * 1) RoCE cap is read only in FW and already disabled
679 * OR:
680 * 2) RoCE cap is writable in FW and user/devlink requested it off.
681 *
682 * In any other case, return False.
683 */
is_roce_fw_disabled(struct mlx5_core_dev * dev)684 static bool is_roce_fw_disabled(struct mlx5_core_dev *dev)
685 {
686 return (MLX5_CAP_GEN(dev, roce_rw_supported) && !mlx5_is_roce_on(dev)) ||
687 (!MLX5_CAP_GEN(dev, roce_rw_supported) && !MLX5_CAP_GEN(dev, roce));
688 }
689
handle_hca_cap_roce(struct mlx5_core_dev * dev,void * set_ctx)690 static int handle_hca_cap_roce(struct mlx5_core_dev *dev, void *set_ctx)
691 {
692 void *set_hca_cap;
693 int err;
694
695 if (is_roce_fw_disabled(dev))
696 return 0;
697
698 err = mlx5_core_get_caps(dev, MLX5_CAP_ROCE);
699 if (err)
700 return err;
701
702 if (MLX5_CAP_ROCE(dev, sw_r_roce_src_udp_port) ||
703 !MLX5_CAP_ROCE_MAX(dev, sw_r_roce_src_udp_port))
704 return 0;
705
706 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
707 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_ROCE]->cur,
708 MLX5_ST_SZ_BYTES(roce_cap));
709 MLX5_SET(roce_cap, set_hca_cap, sw_r_roce_src_udp_port, 1);
710
711 if (MLX5_CAP_ROCE_MAX(dev, qp_ooo_transmit_default))
712 MLX5_SET(roce_cap, set_hca_cap, qp_ooo_transmit_default, 1);
713
714 err = set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ROCE);
715 return err;
716 }
717
handle_hca_cap_port_selection(struct mlx5_core_dev * dev,void * set_ctx)718 static int handle_hca_cap_port_selection(struct mlx5_core_dev *dev,
719 void *set_ctx)
720 {
721 void *set_hca_cap;
722 int err;
723
724 if (!MLX5_CAP_GEN(dev, port_selection_cap))
725 return 0;
726
727 err = mlx5_core_get_caps(dev, MLX5_CAP_PORT_SELECTION);
728 if (err)
729 return err;
730
731 if (MLX5_CAP_PORT_SELECTION(dev, port_select_flow_table_bypass) ||
732 !MLX5_CAP_PORT_SELECTION_MAX(dev, port_select_flow_table_bypass))
733 return 0;
734
735 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
736 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_PORT_SELECTION]->cur,
737 MLX5_ST_SZ_BYTES(port_selection_cap));
738 MLX5_SET(port_selection_cap, set_hca_cap, port_select_flow_table_bypass, 1);
739
740 err = set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_PORT_SELECTION);
741
742 return err;
743 }
744
set_hca_cap(struct mlx5_core_dev * dev)745 static int set_hca_cap(struct mlx5_core_dev *dev)
746 {
747 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
748 void *set_ctx;
749 int err;
750
751 set_ctx = kzalloc(set_sz, GFP_KERNEL);
752 if (!set_ctx)
753 return -ENOMEM;
754
755 err = handle_hca_cap(dev, set_ctx);
756 if (err) {
757 mlx5_core_err(dev, "handle_hca_cap failed\n");
758 goto out;
759 }
760
761 memset(set_ctx, 0, set_sz);
762 err = handle_hca_cap_atomic(dev, set_ctx);
763 if (err) {
764 mlx5_core_err(dev, "handle_hca_cap_atomic failed\n");
765 goto out;
766 }
767
768 memset(set_ctx, 0, set_sz);
769 err = handle_hca_cap_odp(dev, set_ctx);
770 if (err) {
771 mlx5_core_err(dev, "handle_hca_cap_odp failed\n");
772 goto out;
773 }
774
775 memset(set_ctx, 0, set_sz);
776 err = handle_hca_cap_roce(dev, set_ctx);
777 if (err) {
778 mlx5_core_err(dev, "handle_hca_cap_roce failed\n");
779 goto out;
780 }
781
782 memset(set_ctx, 0, set_sz);
783 err = handle_hca_cap_2(dev, set_ctx);
784 if (err) {
785 mlx5_core_err(dev, "handle_hca_cap_2 failed\n");
786 goto out;
787 }
788
789 memset(set_ctx, 0, set_sz);
790 err = handle_hca_cap_port_selection(dev, set_ctx);
791 if (err) {
792 mlx5_core_err(dev, "handle_hca_cap_port_selection failed\n");
793 goto out;
794 }
795
796 out:
797 kfree(set_ctx);
798 return err;
799 }
800
set_hca_ctrl(struct mlx5_core_dev * dev)801 static int set_hca_ctrl(struct mlx5_core_dev *dev)
802 {
803 struct mlx5_reg_host_endianness he_in;
804 struct mlx5_reg_host_endianness he_out;
805 int err;
806
807 if (!mlx5_core_is_pf(dev))
808 return 0;
809
810 memset(&he_in, 0, sizeof(he_in));
811 he_in.he = MLX5_SET_HOST_ENDIANNESS;
812 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
813 &he_out, sizeof(he_out),
814 MLX5_REG_HOST_ENDIANNESS, 0, 1);
815 return err;
816 }
817
mlx5_core_set_hca_defaults(struct mlx5_core_dev * dev)818 static int mlx5_core_set_hca_defaults(struct mlx5_core_dev *dev)
819 {
820 int ret = 0;
821
822 /* Disable local_lb by default */
823 if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH)
824 ret = mlx5_nic_vport_update_local_lb(dev, false);
825
826 return ret;
827 }
828
mlx5_core_enable_hca(struct mlx5_core_dev * dev,u16 func_id)829 int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id)
830 {
831 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {};
832
833 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA);
834 MLX5_SET(enable_hca_in, in, function_id, func_id);
835 MLX5_SET(enable_hca_in, in, embedded_cpu_function,
836 dev->caps.embedded_cpu);
837 return mlx5_cmd_exec_in(dev, enable_hca, in);
838 }
839
mlx5_core_disable_hca(struct mlx5_core_dev * dev,u16 func_id)840 int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id)
841 {
842 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {};
843
844 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA);
845 MLX5_SET(disable_hca_in, in, function_id, func_id);
846 MLX5_SET(enable_hca_in, in, embedded_cpu_function,
847 dev->caps.embedded_cpu);
848 return mlx5_cmd_exec_in(dev, disable_hca, in);
849 }
850
mlx5_core_set_issi(struct mlx5_core_dev * dev)851 static int mlx5_core_set_issi(struct mlx5_core_dev *dev)
852 {
853 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {};
854 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {};
855 u32 sup_issi;
856 int err;
857
858 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI);
859 err = mlx5_cmd_exec_inout(dev, query_issi, query_in, query_out);
860 if (err) {
861 u32 syndrome = MLX5_GET(query_issi_out, query_out, syndrome);
862 u8 status = MLX5_GET(query_issi_out, query_out, status);
863
864 if (!status || syndrome == MLX5_DRIVER_SYND) {
865 mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n",
866 err, status, syndrome);
867 return err;
868 }
869
870 mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n");
871 dev->issi = 0;
872 return 0;
873 }
874
875 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0);
876
877 if (sup_issi & (1 << 1)) {
878 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {};
879
880 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI);
881 MLX5_SET(set_issi_in, set_in, current_issi, 1);
882 err = mlx5_cmd_exec_in(dev, set_issi, set_in);
883 if (err) {
884 mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n",
885 err);
886 return err;
887 }
888
889 dev->issi = 1;
890
891 return 0;
892 } else if (sup_issi & (1 << 0) || !sup_issi) {
893 return 0;
894 }
895
896 return -EOPNOTSUPP;
897 }
898
mlx5_pci_init(struct mlx5_core_dev * dev,struct pci_dev * pdev,const struct pci_device_id * id)899 static int mlx5_pci_init(struct mlx5_core_dev *dev, struct pci_dev *pdev,
900 const struct pci_device_id *id)
901 {
902 int err = 0;
903
904 mutex_init(&dev->pci_status_mutex);
905 pci_set_drvdata(dev->pdev, dev);
906
907 dev->bar_addr = pci_resource_start(pdev, 0);
908
909 err = mlx5_pci_enable_device(dev);
910 if (err) {
911 mlx5_core_err(dev, "Cannot enable PCI device, aborting\n");
912 return err;
913 }
914
915 err = request_bar(pdev);
916 if (err) {
917 mlx5_core_err(dev, "error requesting BARs, aborting\n");
918 goto err_disable;
919 }
920
921 pci_set_master(pdev);
922
923 err = set_dma_caps(pdev);
924 if (err) {
925 mlx5_core_err(dev, "Failed setting DMA capabilities mask, aborting\n");
926 goto err_clr_master;
927 }
928
929 if (pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP32) &&
930 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP64) &&
931 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP128))
932 mlx5_core_dbg(dev, "Enabling pci atomics failed\n");
933
934 dev->iseg_base = dev->bar_addr;
935 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
936 if (!dev->iseg) {
937 err = -ENOMEM;
938 mlx5_core_err(dev, "Failed mapping initialization segment, aborting\n");
939 goto err_clr_master;
940 }
941
942 mlx5_pci_vsc_init(dev);
943
944 err = pci_enable_ptm(pdev, NULL);
945 if (err)
946 mlx5_core_info(dev, "PTM is not supported by PCIe\n");
947
948 return 0;
949
950 err_clr_master:
951 release_bar(dev->pdev);
952 err_disable:
953 mlx5_pci_disable_device(dev);
954 return err;
955 }
956
mlx5_pci_close(struct mlx5_core_dev * dev)957 static void mlx5_pci_close(struct mlx5_core_dev *dev)
958 {
959 /* health work might still be active, and it needs pci bar in
960 * order to know the NIC state. Therefore, drain the health WQ
961 * before removing the pci bars
962 */
963 mlx5_drain_health_wq(dev);
964 pci_disable_ptm(dev->pdev);
965 iounmap(dev->iseg);
966 release_bar(dev->pdev);
967 mlx5_pci_disable_device(dev);
968 }
969
mlx5_register_hca_devcom_comp(struct mlx5_core_dev * dev)970 static void mlx5_register_hca_devcom_comp(struct mlx5_core_dev *dev)
971 {
972 /* This component is use to sync adding core_dev to lag_dev and to sync
973 * changes of mlx5_adev_devices between LAG layer and other layers.
974 */
975 if (!mlx5_lag_is_supported(dev))
976 return;
977
978 dev->priv.hca_devcom_comp =
979 mlx5_devcom_register_component(dev->priv.devc, MLX5_DEVCOM_HCA_PORTS,
980 mlx5_query_nic_system_image_guid(dev),
981 NULL, dev);
982 if (IS_ERR(dev->priv.hca_devcom_comp))
983 mlx5_core_err(dev, "Failed to register devcom HCA component\n");
984 }
985
mlx5_unregister_hca_devcom_comp(struct mlx5_core_dev * dev)986 static void mlx5_unregister_hca_devcom_comp(struct mlx5_core_dev *dev)
987 {
988 mlx5_devcom_unregister_component(dev->priv.hca_devcom_comp);
989 }
990
mlx5_init_once(struct mlx5_core_dev * dev)991 static int mlx5_init_once(struct mlx5_core_dev *dev)
992 {
993 int err;
994
995 dev->priv.devc = mlx5_devcom_register_device(dev);
996 if (IS_ERR(dev->priv.devc))
997 mlx5_core_warn(dev, "failed to register devcom device %ld\n",
998 PTR_ERR(dev->priv.devc));
999 mlx5_register_hca_devcom_comp(dev);
1000
1001 err = mlx5_query_board_id(dev);
1002 if (err) {
1003 mlx5_core_err(dev, "query board id failed\n");
1004 goto err_devcom;
1005 }
1006
1007 err = mlx5_irq_table_init(dev);
1008 if (err) {
1009 mlx5_core_err(dev, "failed to initialize irq table\n");
1010 goto err_devcom;
1011 }
1012
1013 err = mlx5_eq_table_init(dev);
1014 if (err) {
1015 mlx5_core_err(dev, "failed to initialize eq\n");
1016 goto err_irq_cleanup;
1017 }
1018
1019 err = mlx5_events_init(dev);
1020 if (err) {
1021 mlx5_core_err(dev, "failed to initialize events\n");
1022 goto err_eq_cleanup;
1023 }
1024
1025 err = mlx5_fw_reset_init(dev);
1026 if (err) {
1027 mlx5_core_err(dev, "failed to initialize fw reset events\n");
1028 goto err_events_cleanup;
1029 }
1030
1031 mlx5_cq_debugfs_init(dev);
1032
1033 mlx5_init_reserved_gids(dev);
1034
1035 mlx5_init_clock(dev);
1036
1037 dev->vxlan = mlx5_vxlan_create(dev);
1038 dev->geneve = mlx5_geneve_create(dev);
1039
1040 err = mlx5_init_rl_table(dev);
1041 if (err) {
1042 mlx5_core_err(dev, "Failed to init rate limiting\n");
1043 goto err_tables_cleanup;
1044 }
1045
1046 err = mlx5_mpfs_init(dev);
1047 if (err) {
1048 mlx5_core_err(dev, "Failed to init l2 table %d\n", err);
1049 goto err_rl_cleanup;
1050 }
1051
1052 err = mlx5_sriov_init(dev);
1053 if (err) {
1054 mlx5_core_err(dev, "Failed to init sriov %d\n", err);
1055 goto err_mpfs_cleanup;
1056 }
1057
1058 err = mlx5_eswitch_init(dev);
1059 if (err) {
1060 mlx5_core_err(dev, "Failed to init eswitch %d\n", err);
1061 goto err_sriov_cleanup;
1062 }
1063
1064 err = mlx5_fpga_init(dev);
1065 if (err) {
1066 mlx5_core_err(dev, "Failed to init fpga device %d\n", err);
1067 goto err_eswitch_cleanup;
1068 }
1069
1070 err = mlx5_vhca_event_init(dev);
1071 if (err) {
1072 mlx5_core_err(dev, "Failed to init vhca event notifier %d\n", err);
1073 goto err_fpga_cleanup;
1074 }
1075
1076 err = mlx5_sf_hw_table_init(dev);
1077 if (err) {
1078 mlx5_core_err(dev, "Failed to init SF HW table %d\n", err);
1079 goto err_sf_hw_table_cleanup;
1080 }
1081
1082 err = mlx5_sf_table_init(dev);
1083 if (err) {
1084 mlx5_core_err(dev, "Failed to init SF table %d\n", err);
1085 goto err_sf_table_cleanup;
1086 }
1087
1088 err = mlx5_fs_core_alloc(dev);
1089 if (err) {
1090 mlx5_core_err(dev, "Failed to alloc flow steering\n");
1091 goto err_fs;
1092 }
1093
1094 dev->dm = mlx5_dm_create(dev);
1095 if (IS_ERR(dev->dm))
1096 mlx5_core_warn(dev, "Failed to init device memory %ld\n", PTR_ERR(dev->dm));
1097
1098 dev->tracer = mlx5_fw_tracer_create(dev);
1099 dev->hv_vhca = mlx5_hv_vhca_create(dev);
1100 dev->rsc_dump = mlx5_rsc_dump_create(dev);
1101
1102 return 0;
1103
1104 err_fs:
1105 mlx5_sf_table_cleanup(dev);
1106 err_sf_table_cleanup:
1107 mlx5_sf_hw_table_cleanup(dev);
1108 err_sf_hw_table_cleanup:
1109 mlx5_vhca_event_cleanup(dev);
1110 err_fpga_cleanup:
1111 mlx5_fpga_cleanup(dev);
1112 err_eswitch_cleanup:
1113 mlx5_eswitch_cleanup(dev->priv.eswitch);
1114 err_sriov_cleanup:
1115 mlx5_sriov_cleanup(dev);
1116 err_mpfs_cleanup:
1117 mlx5_mpfs_cleanup(dev);
1118 err_rl_cleanup:
1119 mlx5_cleanup_rl_table(dev);
1120 err_tables_cleanup:
1121 mlx5_geneve_destroy(dev->geneve);
1122 mlx5_vxlan_destroy(dev->vxlan);
1123 mlx5_cleanup_clock(dev);
1124 mlx5_cleanup_reserved_gids(dev);
1125 mlx5_cq_debugfs_cleanup(dev);
1126 mlx5_fw_reset_cleanup(dev);
1127 err_events_cleanup:
1128 mlx5_events_cleanup(dev);
1129 err_eq_cleanup:
1130 mlx5_eq_table_cleanup(dev);
1131 err_irq_cleanup:
1132 mlx5_irq_table_cleanup(dev);
1133 err_devcom:
1134 mlx5_unregister_hca_devcom_comp(dev);
1135 mlx5_devcom_unregister_device(dev->priv.devc);
1136
1137 return err;
1138 }
1139
mlx5_cleanup_once(struct mlx5_core_dev * dev)1140 static void mlx5_cleanup_once(struct mlx5_core_dev *dev)
1141 {
1142 mlx5_rsc_dump_destroy(dev);
1143 mlx5_hv_vhca_destroy(dev->hv_vhca);
1144 mlx5_fw_tracer_destroy(dev->tracer);
1145 mlx5_dm_cleanup(dev);
1146 mlx5_fs_core_free(dev);
1147 mlx5_sf_table_cleanup(dev);
1148 mlx5_sf_hw_table_cleanup(dev);
1149 mlx5_vhca_event_cleanup(dev);
1150 mlx5_fpga_cleanup(dev);
1151 mlx5_eswitch_cleanup(dev->priv.eswitch);
1152 mlx5_sriov_cleanup(dev);
1153 mlx5_mpfs_cleanup(dev);
1154 mlx5_cleanup_rl_table(dev);
1155 mlx5_geneve_destroy(dev->geneve);
1156 mlx5_vxlan_destroy(dev->vxlan);
1157 mlx5_cleanup_clock(dev);
1158 mlx5_cleanup_reserved_gids(dev);
1159 mlx5_cq_debugfs_cleanup(dev);
1160 mlx5_fw_reset_cleanup(dev);
1161 mlx5_events_cleanup(dev);
1162 mlx5_eq_table_cleanup(dev);
1163 mlx5_irq_table_cleanup(dev);
1164 mlx5_unregister_hca_devcom_comp(dev);
1165 mlx5_devcom_unregister_device(dev->priv.devc);
1166 }
1167
mlx5_function_enable(struct mlx5_core_dev * dev,bool boot,u64 timeout)1168 static int mlx5_function_enable(struct mlx5_core_dev *dev, bool boot, u64 timeout)
1169 {
1170 int err;
1171
1172 mlx5_core_info(dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
1173 fw_rev_min(dev), fw_rev_sub(dev));
1174
1175 /* Only PFs hold the relevant PCIe information for this query */
1176 if (mlx5_core_is_pf(dev))
1177 pcie_print_link_status(dev->pdev);
1178
1179 /* wait for firmware to accept initialization segments configurations
1180 */
1181 err = wait_fw_init(dev, timeout,
1182 mlx5_tout_ms(dev, FW_PRE_INIT_WARN_MESSAGE_INTERVAL),
1183 "pre-initializing");
1184 if (err)
1185 return err;
1186
1187 err = mlx5_cmd_enable(dev);
1188 if (err) {
1189 mlx5_core_err(dev, "Failed initializing command interface, aborting\n");
1190 return err;
1191 }
1192
1193 mlx5_tout_query_iseg(dev);
1194
1195 err = wait_fw_init(dev, mlx5_tout_ms(dev, FW_INIT), 0, "initializing");
1196 if (err)
1197 goto err_cmd_cleanup;
1198
1199 dev->caps.embedded_cpu = mlx5_read_embedded_cpu(dev);
1200 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_UP);
1201
1202 mlx5_start_health_poll(dev);
1203
1204 err = mlx5_core_enable_hca(dev, 0);
1205 if (err) {
1206 mlx5_core_err(dev, "enable hca failed\n");
1207 goto stop_health_poll;
1208 }
1209
1210 err = mlx5_core_set_issi(dev);
1211 if (err) {
1212 mlx5_core_err(dev, "failed to set issi\n");
1213 goto err_disable_hca;
1214 }
1215
1216 err = mlx5_satisfy_startup_pages(dev, 1);
1217 if (err) {
1218 mlx5_core_err(dev, "failed to allocate boot pages\n");
1219 goto err_disable_hca;
1220 }
1221
1222 err = mlx5_tout_query_dtor(dev);
1223 if (err) {
1224 mlx5_core_err(dev, "failed to read dtor\n");
1225 goto reclaim_boot_pages;
1226 }
1227
1228 return 0;
1229
1230 reclaim_boot_pages:
1231 mlx5_reclaim_startup_pages(dev);
1232 err_disable_hca:
1233 mlx5_core_disable_hca(dev, 0);
1234 stop_health_poll:
1235 mlx5_stop_health_poll(dev, boot);
1236 err_cmd_cleanup:
1237 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN);
1238 mlx5_cmd_disable(dev);
1239
1240 return err;
1241 }
1242
mlx5_function_disable(struct mlx5_core_dev * dev,bool boot)1243 static void mlx5_function_disable(struct mlx5_core_dev *dev, bool boot)
1244 {
1245 mlx5_reclaim_startup_pages(dev);
1246 mlx5_core_disable_hca(dev, 0);
1247 mlx5_stop_health_poll(dev, boot);
1248 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN);
1249 mlx5_cmd_disable(dev);
1250 }
1251
mlx5_function_open(struct mlx5_core_dev * dev)1252 static int mlx5_function_open(struct mlx5_core_dev *dev)
1253 {
1254 int err;
1255
1256 err = set_hca_ctrl(dev);
1257 if (err) {
1258 mlx5_core_err(dev, "set_hca_ctrl failed\n");
1259 return err;
1260 }
1261
1262 err = set_hca_cap(dev);
1263 if (err) {
1264 mlx5_core_err(dev, "set_hca_cap failed\n");
1265 return err;
1266 }
1267
1268 err = mlx5_satisfy_startup_pages(dev, 0);
1269 if (err) {
1270 mlx5_core_err(dev, "failed to allocate init pages\n");
1271 return err;
1272 }
1273
1274 err = mlx5_cmd_init_hca(dev, sw_owner_id);
1275 if (err) {
1276 mlx5_core_err(dev, "init hca failed\n");
1277 return err;
1278 }
1279
1280 mlx5_set_driver_version(dev);
1281
1282 err = mlx5_query_hca_caps(dev);
1283 if (err) {
1284 mlx5_core_err(dev, "query hca failed\n");
1285 return err;
1286 }
1287 mlx5_start_health_fw_log_up(dev);
1288 return 0;
1289 }
1290
mlx5_function_close(struct mlx5_core_dev * dev)1291 static int mlx5_function_close(struct mlx5_core_dev *dev)
1292 {
1293 int err;
1294
1295 err = mlx5_cmd_teardown_hca(dev);
1296 if (err) {
1297 mlx5_core_err(dev, "tear_down_hca failed, skip cleanup\n");
1298 return err;
1299 }
1300
1301 return 0;
1302 }
1303
mlx5_function_setup(struct mlx5_core_dev * dev,bool boot,u64 timeout)1304 static int mlx5_function_setup(struct mlx5_core_dev *dev, bool boot, u64 timeout)
1305 {
1306 int err;
1307
1308 err = mlx5_function_enable(dev, boot, timeout);
1309 if (err)
1310 return err;
1311
1312 err = mlx5_function_open(dev);
1313 if (err)
1314 mlx5_function_disable(dev, boot);
1315 return err;
1316 }
1317
mlx5_function_teardown(struct mlx5_core_dev * dev,bool boot)1318 static int mlx5_function_teardown(struct mlx5_core_dev *dev, bool boot)
1319 {
1320 int err = mlx5_function_close(dev);
1321
1322 if (!err)
1323 mlx5_function_disable(dev, boot);
1324 else
1325 mlx5_stop_health_poll(dev, boot);
1326
1327 return err;
1328 }
1329
mlx5_load(struct mlx5_core_dev * dev)1330 static int mlx5_load(struct mlx5_core_dev *dev)
1331 {
1332 int err;
1333
1334 dev->priv.uar = mlx5_get_uars_page(dev);
1335 if (IS_ERR(dev->priv.uar)) {
1336 mlx5_core_err(dev, "Failed allocating uar, aborting\n");
1337 err = PTR_ERR(dev->priv.uar);
1338 return err;
1339 }
1340
1341 mlx5_events_start(dev);
1342 mlx5_pagealloc_start(dev);
1343
1344 err = mlx5_irq_table_create(dev);
1345 if (err) {
1346 mlx5_core_err(dev, "Failed to alloc IRQs\n");
1347 goto err_irq_table;
1348 }
1349
1350 err = mlx5_eq_table_create(dev);
1351 if (err) {
1352 mlx5_core_err(dev, "Failed to create EQs\n");
1353 goto err_eq_table;
1354 }
1355
1356 err = mlx5_fw_tracer_init(dev->tracer);
1357 if (err) {
1358 mlx5_core_err(dev, "Failed to init FW tracer %d\n", err);
1359 mlx5_fw_tracer_destroy(dev->tracer);
1360 dev->tracer = NULL;
1361 }
1362
1363 mlx5_fw_reset_events_start(dev);
1364 mlx5_hv_vhca_init(dev->hv_vhca);
1365
1366 err = mlx5_rsc_dump_init(dev);
1367 if (err) {
1368 mlx5_core_err(dev, "Failed to init Resource dump %d\n", err);
1369 mlx5_rsc_dump_destroy(dev);
1370 dev->rsc_dump = NULL;
1371 }
1372
1373 err = mlx5_fpga_device_start(dev);
1374 if (err) {
1375 mlx5_core_err(dev, "fpga device start failed %d\n", err);
1376 goto err_fpga_start;
1377 }
1378
1379 err = mlx5_fs_core_init(dev);
1380 if (err) {
1381 mlx5_core_err(dev, "Failed to init flow steering\n");
1382 goto err_fs;
1383 }
1384
1385 err = mlx5_core_set_hca_defaults(dev);
1386 if (err) {
1387 mlx5_core_err(dev, "Failed to set hca defaults\n");
1388 goto err_set_hca;
1389 }
1390
1391 mlx5_vhca_event_start(dev);
1392
1393 err = mlx5_sf_hw_table_create(dev);
1394 if (err) {
1395 mlx5_core_err(dev, "sf table create failed %d\n", err);
1396 goto err_vhca;
1397 }
1398
1399 err = mlx5_ec_init(dev);
1400 if (err) {
1401 mlx5_core_err(dev, "Failed to init embedded CPU\n");
1402 goto err_ec;
1403 }
1404
1405 mlx5_lag_add_mdev(dev);
1406 err = mlx5_sriov_attach(dev);
1407 if (err) {
1408 mlx5_core_err(dev, "sriov init failed %d\n", err);
1409 goto err_sriov;
1410 }
1411
1412 mlx5_sf_dev_table_create(dev);
1413
1414 err = mlx5_devlink_traps_register(priv_to_devlink(dev));
1415 if (err)
1416 goto err_traps_reg;
1417
1418 return 0;
1419
1420 err_traps_reg:
1421 mlx5_sf_dev_table_destroy(dev);
1422 mlx5_sriov_detach(dev);
1423 err_sriov:
1424 mlx5_lag_remove_mdev(dev);
1425 mlx5_ec_cleanup(dev);
1426 err_ec:
1427 mlx5_sf_hw_table_destroy(dev);
1428 err_vhca:
1429 mlx5_vhca_event_stop(dev);
1430 err_set_hca:
1431 mlx5_fs_core_cleanup(dev);
1432 err_fs:
1433 mlx5_fpga_device_stop(dev);
1434 err_fpga_start:
1435 mlx5_rsc_dump_cleanup(dev);
1436 mlx5_hv_vhca_cleanup(dev->hv_vhca);
1437 mlx5_fw_reset_events_stop(dev);
1438 mlx5_fw_tracer_cleanup(dev->tracer);
1439 mlx5_eq_table_destroy(dev);
1440 err_eq_table:
1441 mlx5_irq_table_destroy(dev);
1442 err_irq_table:
1443 mlx5_pagealloc_stop(dev);
1444 mlx5_events_stop(dev);
1445 mlx5_put_uars_page(dev, dev->priv.uar);
1446 return err;
1447 }
1448
mlx5_unload(struct mlx5_core_dev * dev)1449 static void mlx5_unload(struct mlx5_core_dev *dev)
1450 {
1451 mlx5_eswitch_disable(dev->priv.eswitch);
1452 mlx5_devlink_traps_unregister(priv_to_devlink(dev));
1453 mlx5_sf_dev_table_destroy(dev);
1454 mlx5_sriov_detach(dev);
1455 mlx5_lag_remove_mdev(dev);
1456 mlx5_ec_cleanup(dev);
1457 mlx5_sf_hw_table_destroy(dev);
1458 mlx5_vhca_event_stop(dev);
1459 mlx5_fs_core_cleanup(dev);
1460 mlx5_fpga_device_stop(dev);
1461 mlx5_rsc_dump_cleanup(dev);
1462 mlx5_hv_vhca_cleanup(dev->hv_vhca);
1463 mlx5_fw_reset_events_stop(dev);
1464 mlx5_fw_tracer_cleanup(dev->tracer);
1465 mlx5_eq_table_destroy(dev);
1466 mlx5_irq_table_destroy(dev);
1467 mlx5_pagealloc_stop(dev);
1468 mlx5_events_stop(dev);
1469 mlx5_put_uars_page(dev, dev->priv.uar);
1470 }
1471
mlx5_init_one_devl_locked(struct mlx5_core_dev * dev)1472 int mlx5_init_one_devl_locked(struct mlx5_core_dev *dev)
1473 {
1474 bool light_probe = mlx5_dev_is_lightweight(dev);
1475 int err = 0;
1476
1477 mutex_lock(&dev->intf_state_mutex);
1478 dev->state = MLX5_DEVICE_STATE_UP;
1479
1480 err = mlx5_function_setup(dev, true, mlx5_tout_ms(dev, FW_PRE_INIT_TIMEOUT));
1481 if (err)
1482 goto err_function;
1483
1484 err = mlx5_init_once(dev);
1485 if (err) {
1486 mlx5_core_err(dev, "sw objs init failed\n");
1487 goto function_teardown;
1488 }
1489
1490 /* In case of light_probe, mlx5_devlink is already registered.
1491 * Hence, don't register devlink again.
1492 */
1493 if (!light_probe) {
1494 err = mlx5_devlink_params_register(priv_to_devlink(dev));
1495 if (err)
1496 goto err_devlink_params_reg;
1497 }
1498
1499 err = mlx5_load(dev);
1500 if (err)
1501 goto err_load;
1502
1503 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1504
1505 err = mlx5_register_device(dev);
1506 if (err)
1507 goto err_register;
1508
1509 err = mlx5_crdump_enable(dev);
1510 if (err)
1511 mlx5_core_err(dev, "mlx5_crdump_enable failed with error code %d\n", err);
1512
1513 err = mlx5_hwmon_dev_register(dev);
1514 if (err)
1515 mlx5_core_err(dev, "mlx5_hwmon_dev_register failed with error code %d\n", err);
1516
1517 mutex_unlock(&dev->intf_state_mutex);
1518 return 0;
1519
1520 err_register:
1521 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1522 mlx5_unload(dev);
1523 err_load:
1524 if (!light_probe)
1525 mlx5_devlink_params_unregister(priv_to_devlink(dev));
1526 err_devlink_params_reg:
1527 mlx5_cleanup_once(dev);
1528 function_teardown:
1529 mlx5_function_teardown(dev, true);
1530 err_function:
1531 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1532 mutex_unlock(&dev->intf_state_mutex);
1533 return err;
1534 }
1535
mlx5_init_one(struct mlx5_core_dev * dev)1536 int mlx5_init_one(struct mlx5_core_dev *dev)
1537 {
1538 struct devlink *devlink = priv_to_devlink(dev);
1539 int err;
1540
1541 devl_lock(devlink);
1542 devl_register(devlink);
1543 err = mlx5_init_one_devl_locked(dev);
1544 if (err)
1545 devl_unregister(devlink);
1546 devl_unlock(devlink);
1547 return err;
1548 }
1549
mlx5_uninit_one(struct mlx5_core_dev * dev)1550 void mlx5_uninit_one(struct mlx5_core_dev *dev)
1551 {
1552 struct devlink *devlink = priv_to_devlink(dev);
1553
1554 devl_lock(devlink);
1555 mutex_lock(&dev->intf_state_mutex);
1556
1557 mlx5_hwmon_dev_unregister(dev);
1558 mlx5_crdump_disable(dev);
1559 mlx5_unregister_device(dev);
1560
1561 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1562 mlx5_core_warn(dev, "%s: interface is down, NOP\n",
1563 __func__);
1564 mlx5_devlink_params_unregister(priv_to_devlink(dev));
1565 mlx5_cleanup_once(dev);
1566 goto out;
1567 }
1568
1569 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1570 mlx5_unload(dev);
1571 mlx5_devlink_params_unregister(priv_to_devlink(dev));
1572 mlx5_cleanup_once(dev);
1573 mlx5_function_teardown(dev, true);
1574 out:
1575 mutex_unlock(&dev->intf_state_mutex);
1576 devl_unregister(devlink);
1577 devl_unlock(devlink);
1578 }
1579
mlx5_load_one_devl_locked(struct mlx5_core_dev * dev,bool recovery)1580 int mlx5_load_one_devl_locked(struct mlx5_core_dev *dev, bool recovery)
1581 {
1582 int err = 0;
1583 u64 timeout;
1584
1585 devl_assert_locked(priv_to_devlink(dev));
1586 mutex_lock(&dev->intf_state_mutex);
1587 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1588 mlx5_core_warn(dev, "interface is up, NOP\n");
1589 goto out;
1590 }
1591 /* remove any previous indication of internal error */
1592 dev->state = MLX5_DEVICE_STATE_UP;
1593
1594 if (recovery)
1595 timeout = mlx5_tout_ms(dev, FW_PRE_INIT_ON_RECOVERY_TIMEOUT);
1596 else
1597 timeout = mlx5_tout_ms(dev, FW_PRE_INIT_TIMEOUT);
1598 err = mlx5_function_setup(dev, false, timeout);
1599 if (err)
1600 goto err_function;
1601
1602 err = mlx5_load(dev);
1603 if (err)
1604 goto err_load;
1605
1606 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1607
1608 err = mlx5_attach_device(dev);
1609 if (err)
1610 goto err_attach;
1611
1612 mutex_unlock(&dev->intf_state_mutex);
1613 return 0;
1614
1615 err_attach:
1616 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1617 mlx5_unload(dev);
1618 err_load:
1619 mlx5_function_teardown(dev, false);
1620 err_function:
1621 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1622 out:
1623 mutex_unlock(&dev->intf_state_mutex);
1624 return err;
1625 }
1626
mlx5_load_one(struct mlx5_core_dev * dev,bool recovery)1627 int mlx5_load_one(struct mlx5_core_dev *dev, bool recovery)
1628 {
1629 struct devlink *devlink = priv_to_devlink(dev);
1630 int ret;
1631
1632 devl_lock(devlink);
1633 ret = mlx5_load_one_devl_locked(dev, recovery);
1634 devl_unlock(devlink);
1635 return ret;
1636 }
1637
mlx5_unload_one_devl_locked(struct mlx5_core_dev * dev,bool suspend)1638 void mlx5_unload_one_devl_locked(struct mlx5_core_dev *dev, bool suspend)
1639 {
1640 devl_assert_locked(priv_to_devlink(dev));
1641 mutex_lock(&dev->intf_state_mutex);
1642
1643 mlx5_detach_device(dev, suspend);
1644
1645 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1646 mlx5_core_warn(dev, "%s: interface is down, NOP\n",
1647 __func__);
1648 goto out;
1649 }
1650
1651 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1652 mlx5_unload(dev);
1653 mlx5_function_teardown(dev, false);
1654 out:
1655 mutex_unlock(&dev->intf_state_mutex);
1656 }
1657
mlx5_unload_one(struct mlx5_core_dev * dev,bool suspend)1658 void mlx5_unload_one(struct mlx5_core_dev *dev, bool suspend)
1659 {
1660 struct devlink *devlink = priv_to_devlink(dev);
1661
1662 devl_lock(devlink);
1663 mlx5_unload_one_devl_locked(dev, suspend);
1664 devl_unlock(devlink);
1665 }
1666
1667 /* In case of light probe, we don't need a full query of hca_caps, but only the bellow caps.
1668 * A full query of hca_caps will be done when the device will reload.
1669 */
mlx5_query_hca_caps_light(struct mlx5_core_dev * dev)1670 static int mlx5_query_hca_caps_light(struct mlx5_core_dev *dev)
1671 {
1672 int err;
1673
1674 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL);
1675 if (err)
1676 return err;
1677
1678 if (MLX5_CAP_GEN(dev, eth_net_offloads)) {
1679 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_ETHERNET_OFFLOADS,
1680 HCA_CAP_OPMOD_GET_CUR);
1681 if (err)
1682 return err;
1683 }
1684
1685 if (MLX5_CAP_GEN(dev, nic_flow_table) ||
1686 MLX5_CAP_GEN(dev, ipoib_enhanced_offloads)) {
1687 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_FLOW_TABLE,
1688 HCA_CAP_OPMOD_GET_CUR);
1689 if (err)
1690 return err;
1691 }
1692
1693 if (MLX5_CAP_GEN_64(dev, general_obj_types) &
1694 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q) {
1695 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_VDPA_EMULATION,
1696 HCA_CAP_OPMOD_GET_CUR);
1697 if (err)
1698 return err;
1699 }
1700
1701 return 0;
1702 }
1703
mlx5_init_one_light(struct mlx5_core_dev * dev)1704 int mlx5_init_one_light(struct mlx5_core_dev *dev)
1705 {
1706 struct devlink *devlink = priv_to_devlink(dev);
1707 int err;
1708
1709 devl_lock(devlink);
1710 devl_register(devlink);
1711 dev->state = MLX5_DEVICE_STATE_UP;
1712 err = mlx5_function_enable(dev, true, mlx5_tout_ms(dev, FW_PRE_INIT_TIMEOUT));
1713 if (err) {
1714 mlx5_core_warn(dev, "mlx5_function_enable err=%d\n", err);
1715 goto out;
1716 }
1717
1718 err = mlx5_query_hca_caps_light(dev);
1719 if (err) {
1720 mlx5_core_warn(dev, "mlx5_query_hca_caps_light err=%d\n", err);
1721 goto query_hca_caps_err;
1722 }
1723
1724 err = mlx5_devlink_params_register(priv_to_devlink(dev));
1725 if (err) {
1726 mlx5_core_warn(dev, "mlx5_devlink_param_reg err = %d\n", err);
1727 goto query_hca_caps_err;
1728 }
1729
1730 devl_unlock(devlink);
1731 return 0;
1732
1733 query_hca_caps_err:
1734 mlx5_function_disable(dev, true);
1735 out:
1736 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1737 devl_unregister(devlink);
1738 devl_unlock(devlink);
1739 return err;
1740 }
1741
mlx5_uninit_one_light(struct mlx5_core_dev * dev)1742 void mlx5_uninit_one_light(struct mlx5_core_dev *dev)
1743 {
1744 struct devlink *devlink = priv_to_devlink(dev);
1745
1746 devl_lock(devlink);
1747 mlx5_devlink_params_unregister(priv_to_devlink(dev));
1748 devl_unregister(devlink);
1749 devl_unlock(devlink);
1750 if (dev->state != MLX5_DEVICE_STATE_UP)
1751 return;
1752 mlx5_function_disable(dev, true);
1753 }
1754
1755 /* xxx_light() function are used in order to configure the device without full
1756 * init (light init). e.g.: There isn't a point in reload a device to light state.
1757 * Hence, mlx5_load_one_light() isn't needed.
1758 */
1759
mlx5_unload_one_light(struct mlx5_core_dev * dev)1760 void mlx5_unload_one_light(struct mlx5_core_dev *dev)
1761 {
1762 if (dev->state != MLX5_DEVICE_STATE_UP)
1763 return;
1764 mlx5_function_disable(dev, false);
1765 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1766 }
1767
1768 static const int types[] = {
1769 MLX5_CAP_GENERAL,
1770 MLX5_CAP_GENERAL_2,
1771 MLX5_CAP_ETHERNET_OFFLOADS,
1772 MLX5_CAP_IPOIB_ENHANCED_OFFLOADS,
1773 MLX5_CAP_ODP,
1774 MLX5_CAP_ATOMIC,
1775 MLX5_CAP_ROCE,
1776 MLX5_CAP_IPOIB_OFFLOADS,
1777 MLX5_CAP_FLOW_TABLE,
1778 MLX5_CAP_ESWITCH_FLOW_TABLE,
1779 MLX5_CAP_ESWITCH,
1780 MLX5_CAP_QOS,
1781 MLX5_CAP_DEBUG,
1782 MLX5_CAP_DEV_MEM,
1783 MLX5_CAP_DEV_EVENT,
1784 MLX5_CAP_TLS,
1785 MLX5_CAP_VDPA_EMULATION,
1786 MLX5_CAP_IPSEC,
1787 MLX5_CAP_PORT_SELECTION,
1788 MLX5_CAP_MACSEC,
1789 MLX5_CAP_ADV_VIRTUALIZATION,
1790 MLX5_CAP_CRYPTO,
1791 };
1792
mlx5_hca_caps_free(struct mlx5_core_dev * dev)1793 static void mlx5_hca_caps_free(struct mlx5_core_dev *dev)
1794 {
1795 int type;
1796 int i;
1797
1798 for (i = 0; i < ARRAY_SIZE(types); i++) {
1799 type = types[i];
1800 kfree(dev->caps.hca[type]);
1801 }
1802 }
1803
mlx5_hca_caps_alloc(struct mlx5_core_dev * dev)1804 static int mlx5_hca_caps_alloc(struct mlx5_core_dev *dev)
1805 {
1806 struct mlx5_hca_cap *cap;
1807 int type;
1808 int i;
1809
1810 for (i = 0; i < ARRAY_SIZE(types); i++) {
1811 cap = kzalloc(sizeof(*cap), GFP_KERNEL);
1812 if (!cap)
1813 goto err;
1814 type = types[i];
1815 dev->caps.hca[type] = cap;
1816 }
1817
1818 return 0;
1819
1820 err:
1821 mlx5_hca_caps_free(dev);
1822 return -ENOMEM;
1823 }
1824
vhca_id_show(struct seq_file * file,void * priv)1825 static int vhca_id_show(struct seq_file *file, void *priv)
1826 {
1827 struct mlx5_core_dev *dev = file->private;
1828
1829 seq_printf(file, "0x%x\n", MLX5_CAP_GEN(dev, vhca_id));
1830 return 0;
1831 }
1832
1833 DEFINE_SHOW_ATTRIBUTE(vhca_id);
1834
mlx5_mdev_init(struct mlx5_core_dev * dev,int profile_idx)1835 int mlx5_mdev_init(struct mlx5_core_dev *dev, int profile_idx)
1836 {
1837 struct mlx5_priv *priv = &dev->priv;
1838 int err;
1839
1840 memcpy(&dev->profile, &profile[profile_idx], sizeof(dev->profile));
1841 lockdep_register_key(&dev->lock_key);
1842 mutex_init(&dev->intf_state_mutex);
1843 lockdep_set_class(&dev->intf_state_mutex, &dev->lock_key);
1844 mutex_init(&dev->mlx5e_res.uplink_netdev_lock);
1845 mutex_init(&dev->wc_state_lock);
1846
1847 mutex_init(&priv->bfregs.reg_head.lock);
1848 mutex_init(&priv->bfregs.wc_head.lock);
1849 INIT_LIST_HEAD(&priv->bfregs.reg_head.list);
1850 INIT_LIST_HEAD(&priv->bfregs.wc_head.list);
1851
1852 mutex_init(&priv->alloc_mutex);
1853 mutex_init(&priv->pgdir_mutex);
1854 INIT_LIST_HEAD(&priv->pgdir_list);
1855
1856 priv->numa_node = dev_to_node(mlx5_core_dma_dev(dev));
1857 priv->dbg.dbg_root = debugfs_create_dir(dev_name(dev->device),
1858 mlx5_debugfs_root);
1859 debugfs_create_file("vhca_id", 0400, priv->dbg.dbg_root, dev, &vhca_id_fops);
1860 INIT_LIST_HEAD(&priv->traps);
1861
1862 err = mlx5_cmd_init(dev);
1863 if (err) {
1864 mlx5_core_err(dev, "Failed initializing cmdif SW structs, aborting\n");
1865 goto err_cmd_init;
1866 }
1867
1868 err = mlx5_tout_init(dev);
1869 if (err) {
1870 mlx5_core_err(dev, "Failed initializing timeouts, aborting\n");
1871 goto err_timeout_init;
1872 }
1873
1874 err = mlx5_health_init(dev);
1875 if (err)
1876 goto err_health_init;
1877
1878 err = mlx5_pagealloc_init(dev);
1879 if (err)
1880 goto err_pagealloc_init;
1881
1882 err = mlx5_adev_init(dev);
1883 if (err)
1884 goto err_adev_init;
1885
1886 err = mlx5_hca_caps_alloc(dev);
1887 if (err)
1888 goto err_hca_caps;
1889
1890 /* The conjunction of sw_vhca_id with sw_owner_id will be a global
1891 * unique id per function which uses mlx5_core.
1892 * Those values are supplied to FW as part of the init HCA command to
1893 * be used by both driver and FW when it's applicable.
1894 */
1895 dev->priv.sw_vhca_id = ida_alloc_range(&sw_vhca_ida, 1,
1896 MAX_SW_VHCA_ID,
1897 GFP_KERNEL);
1898 if (dev->priv.sw_vhca_id < 0)
1899 mlx5_core_err(dev, "failed to allocate sw_vhca_id, err=%d\n",
1900 dev->priv.sw_vhca_id);
1901
1902 return 0;
1903
1904 err_hca_caps:
1905 mlx5_adev_cleanup(dev);
1906 err_adev_init:
1907 mlx5_pagealloc_cleanup(dev);
1908 err_pagealloc_init:
1909 mlx5_health_cleanup(dev);
1910 err_health_init:
1911 mlx5_tout_cleanup(dev);
1912 err_timeout_init:
1913 mlx5_cmd_cleanup(dev);
1914 err_cmd_init:
1915 debugfs_remove(dev->priv.dbg.dbg_root);
1916 mutex_destroy(&priv->pgdir_mutex);
1917 mutex_destroy(&priv->alloc_mutex);
1918 mutex_destroy(&priv->bfregs.wc_head.lock);
1919 mutex_destroy(&priv->bfregs.reg_head.lock);
1920 mutex_destroy(&dev->intf_state_mutex);
1921 lockdep_unregister_key(&dev->lock_key);
1922 return err;
1923 }
1924
mlx5_mdev_uninit(struct mlx5_core_dev * dev)1925 void mlx5_mdev_uninit(struct mlx5_core_dev *dev)
1926 {
1927 struct mlx5_priv *priv = &dev->priv;
1928
1929 if (priv->sw_vhca_id > 0)
1930 ida_free(&sw_vhca_ida, dev->priv.sw_vhca_id);
1931
1932 mlx5_hca_caps_free(dev);
1933 mlx5_adev_cleanup(dev);
1934 mlx5_pagealloc_cleanup(dev);
1935 mlx5_health_cleanup(dev);
1936 mlx5_tout_cleanup(dev);
1937 mlx5_cmd_cleanup(dev);
1938 debugfs_remove_recursive(dev->priv.dbg.dbg_root);
1939 mutex_destroy(&priv->pgdir_mutex);
1940 mutex_destroy(&priv->alloc_mutex);
1941 mutex_destroy(&priv->bfregs.wc_head.lock);
1942 mutex_destroy(&priv->bfregs.reg_head.lock);
1943 mutex_destroy(&dev->wc_state_lock);
1944 mutex_destroy(&dev->mlx5e_res.uplink_netdev_lock);
1945 mutex_destroy(&dev->intf_state_mutex);
1946 lockdep_unregister_key(&dev->lock_key);
1947 }
1948
probe_one(struct pci_dev * pdev,const struct pci_device_id * id)1949 static int probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1950 {
1951 struct mlx5_core_dev *dev;
1952 struct devlink *devlink;
1953 int err;
1954
1955 devlink = mlx5_devlink_alloc(&pdev->dev);
1956 if (!devlink) {
1957 dev_err(&pdev->dev, "devlink alloc failed\n");
1958 return -ENOMEM;
1959 }
1960
1961 dev = devlink_priv(devlink);
1962 dev->device = &pdev->dev;
1963 dev->pdev = pdev;
1964
1965 dev->coredev_type = id->driver_data & MLX5_PCI_DEV_IS_VF ?
1966 MLX5_COREDEV_VF : MLX5_COREDEV_PF;
1967
1968 dev->priv.adev_idx = mlx5_adev_idx_alloc();
1969 if (dev->priv.adev_idx < 0) {
1970 err = dev->priv.adev_idx;
1971 goto adev_init_err;
1972 }
1973
1974 err = mlx5_mdev_init(dev, prof_sel);
1975 if (err)
1976 goto mdev_init_err;
1977
1978 err = mlx5_pci_init(dev, pdev, id);
1979 if (err) {
1980 mlx5_core_err(dev, "mlx5_pci_init failed with error code %d\n",
1981 err);
1982 goto pci_init_err;
1983 }
1984
1985 err = mlx5_init_one(dev);
1986 if (err) {
1987 mlx5_core_err(dev, "mlx5_init_one failed with error code %d\n",
1988 err);
1989 goto err_init_one;
1990 }
1991
1992 pci_save_state(pdev);
1993 return 0;
1994
1995 err_init_one:
1996 mlx5_pci_close(dev);
1997 pci_init_err:
1998 mlx5_mdev_uninit(dev);
1999 mdev_init_err:
2000 mlx5_adev_idx_free(dev->priv.adev_idx);
2001 adev_init_err:
2002 mlx5_devlink_free(devlink);
2003
2004 return err;
2005 }
2006
remove_one(struct pci_dev * pdev)2007 static void remove_one(struct pci_dev *pdev)
2008 {
2009 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
2010 struct devlink *devlink = priv_to_devlink(dev);
2011
2012 set_bit(MLX5_BREAK_FW_WAIT, &dev->intf_state);
2013 mlx5_drain_fw_reset(dev);
2014 mlx5_drain_health_wq(dev);
2015 mlx5_sriov_disable(pdev, false);
2016 mlx5_uninit_one(dev);
2017 mlx5_pci_close(dev);
2018 mlx5_mdev_uninit(dev);
2019 mlx5_adev_idx_free(dev->priv.adev_idx);
2020 mlx5_devlink_free(devlink);
2021 }
2022
2023 #define mlx5_pci_trace(dev, fmt, ...) ({ \
2024 struct mlx5_core_dev *__dev = (dev); \
2025 mlx5_core_info(__dev, "%s Device state = %d health sensors: %d pci_status: %d. " fmt, \
2026 __func__, __dev->state, mlx5_health_check_fatal_sensors(__dev), \
2027 __dev->pci_status, ##__VA_ARGS__); \
2028 })
2029
result2str(enum pci_ers_result result)2030 static const char *result2str(enum pci_ers_result result)
2031 {
2032 return result == PCI_ERS_RESULT_NEED_RESET ? "need reset" :
2033 result == PCI_ERS_RESULT_DISCONNECT ? "disconnect" :
2034 result == PCI_ERS_RESULT_RECOVERED ? "recovered" :
2035 "unknown";
2036 }
2037
mlx5_pci_err_detected(struct pci_dev * pdev,pci_channel_state_t state)2038 static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev,
2039 pci_channel_state_t state)
2040 {
2041 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
2042 enum pci_ers_result res;
2043
2044 mlx5_pci_trace(dev, "Enter, pci channel state = %d\n", state);
2045
2046 mlx5_enter_error_state(dev, false);
2047 mlx5_error_sw_reset(dev);
2048 mlx5_unload_one(dev, false);
2049 mlx5_drain_health_wq(dev);
2050 mlx5_pci_disable_device(dev);
2051
2052 res = state == pci_channel_io_perm_failure ?
2053 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
2054
2055 mlx5_core_info(dev, "%s Device state = %d pci_status: %d. Exit, result = %d, %s\n",
2056 __func__, dev->state, dev->pci_status, res, result2str(res));
2057 return res;
2058 }
2059
2060 /* wait for the device to show vital signs by waiting
2061 * for the health counter to start counting.
2062 */
wait_vital(struct pci_dev * pdev)2063 static int wait_vital(struct pci_dev *pdev)
2064 {
2065 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
2066 struct mlx5_core_health *health = &dev->priv.health;
2067 const int niter = 100;
2068 u32 last_count = 0;
2069 u32 count;
2070 int i;
2071
2072 for (i = 0; i < niter; i++) {
2073 count = ioread32be(health->health_counter);
2074 if (count && count != 0xffffffff) {
2075 if (last_count && last_count != count) {
2076 mlx5_core_info(dev,
2077 "wait vital counter value 0x%x after %d iterations\n",
2078 count, i);
2079 return 0;
2080 }
2081 last_count = count;
2082 }
2083 msleep(50);
2084 }
2085
2086 return -ETIMEDOUT;
2087 }
2088
mlx5_pci_slot_reset(struct pci_dev * pdev)2089 static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev)
2090 {
2091 enum pci_ers_result res = PCI_ERS_RESULT_DISCONNECT;
2092 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
2093 int err;
2094
2095 mlx5_core_info(dev, "%s Device state = %d pci_status: %d. Enter\n",
2096 __func__, dev->state, dev->pci_status);
2097
2098 err = mlx5_pci_enable_device(dev);
2099 if (err) {
2100 mlx5_core_err(dev, "%s: mlx5_pci_enable_device failed with error code: %d\n",
2101 __func__, err);
2102 goto out;
2103 }
2104
2105 pci_set_master(pdev);
2106 pci_restore_state(pdev);
2107 pci_save_state(pdev);
2108
2109 err = wait_vital(pdev);
2110 if (err) {
2111 mlx5_core_err(dev, "%s: wait vital failed with error code: %d\n",
2112 __func__, err);
2113 goto out;
2114 }
2115
2116 res = PCI_ERS_RESULT_RECOVERED;
2117 out:
2118 mlx5_core_info(dev, "%s Device state = %d pci_status: %d. Exit, err = %d, result = %d, %s\n",
2119 __func__, dev->state, dev->pci_status, err, res, result2str(res));
2120 return res;
2121 }
2122
mlx5_pci_resume(struct pci_dev * pdev)2123 static void mlx5_pci_resume(struct pci_dev *pdev)
2124 {
2125 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
2126 int err;
2127
2128 mlx5_pci_trace(dev, "Enter, loading driver..\n");
2129
2130 err = mlx5_load_one(dev, false);
2131
2132 if (!err)
2133 devlink_health_reporter_state_update(dev->priv.health.fw_fatal_reporter,
2134 DEVLINK_HEALTH_REPORTER_STATE_HEALTHY);
2135
2136 mlx5_pci_trace(dev, "Done, err = %d, device %s\n", err,
2137 !err ? "recovered" : "Failed");
2138 }
2139
2140 static const struct pci_error_handlers mlx5_err_handler = {
2141 .error_detected = mlx5_pci_err_detected,
2142 .slot_reset = mlx5_pci_slot_reset,
2143 .resume = mlx5_pci_resume
2144 };
2145
mlx5_try_fast_unload(struct mlx5_core_dev * dev)2146 static int mlx5_try_fast_unload(struct mlx5_core_dev *dev)
2147 {
2148 bool fast_teardown = false, force_teardown = false;
2149 int ret = 1;
2150
2151 fast_teardown = MLX5_CAP_GEN(dev, fast_teardown);
2152 force_teardown = MLX5_CAP_GEN(dev, force_teardown);
2153
2154 mlx5_core_dbg(dev, "force teardown firmware support=%d\n", force_teardown);
2155 mlx5_core_dbg(dev, "fast teardown firmware support=%d\n", fast_teardown);
2156
2157 if (!fast_teardown && !force_teardown)
2158 return -EOPNOTSUPP;
2159
2160 if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
2161 mlx5_core_dbg(dev, "Device in internal error state, giving up\n");
2162 return -EAGAIN;
2163 }
2164
2165 /* Panic tear down fw command will stop the PCI bus communication
2166 * with the HCA, so the health poll is no longer needed.
2167 */
2168 mlx5_stop_health_poll(dev, false);
2169
2170 ret = mlx5_cmd_fast_teardown_hca(dev);
2171 if (!ret)
2172 goto succeed;
2173
2174 ret = mlx5_cmd_force_teardown_hca(dev);
2175 if (!ret)
2176 goto succeed;
2177
2178 mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", ret);
2179 mlx5_start_health_poll(dev);
2180 return ret;
2181
2182 succeed:
2183 mlx5_enter_error_state(dev, true);
2184
2185 /* Some platforms requiring freeing the IRQ's in the shutdown
2186 * flow. If they aren't freed they can't be allocated after
2187 * kexec. There is no need to cleanup the mlx5_core software
2188 * contexts.
2189 */
2190 mlx5_core_eq_free_irqs(dev);
2191
2192 return 0;
2193 }
2194
shutdown(struct pci_dev * pdev)2195 static void shutdown(struct pci_dev *pdev)
2196 {
2197 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
2198 int err;
2199
2200 mlx5_core_info(dev, "Shutdown was called\n");
2201 set_bit(MLX5_BREAK_FW_WAIT, &dev->intf_state);
2202 mlx5_drain_health_wq(dev);
2203 err = mlx5_try_fast_unload(dev);
2204 if (err)
2205 mlx5_unload_one(dev, false);
2206 mlx5_pci_disable_device(dev);
2207 }
2208
mlx5_suspend(struct pci_dev * pdev,pm_message_t state)2209 static int mlx5_suspend(struct pci_dev *pdev, pm_message_t state)
2210 {
2211 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
2212
2213 mlx5_unload_one(dev, true);
2214
2215 return 0;
2216 }
2217
mlx5_resume(struct pci_dev * pdev)2218 static int mlx5_resume(struct pci_dev *pdev)
2219 {
2220 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
2221
2222 return mlx5_load_one(dev, false);
2223 }
2224
2225 static const struct pci_device_id mlx5_core_pci_table[] = {
2226 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTIB) },
2227 { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */
2228 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4) },
2229 { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */
2230 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) },
2231 { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */
2232 { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */
2233 { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */
2234 { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5 Ex */
2235 { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 Ex VF */
2236 { PCI_VDEVICE(MELLANOX, 0x101b) }, /* ConnectX-6 */
2237 { PCI_VDEVICE(MELLANOX, 0x101c), MLX5_PCI_DEV_IS_VF}, /* ConnectX-6 VF */
2238 { PCI_VDEVICE(MELLANOX, 0x101d) }, /* ConnectX-6 Dx */
2239 { PCI_VDEVICE(MELLANOX, 0x101e), MLX5_PCI_DEV_IS_VF}, /* ConnectX Family mlx5Gen Virtual Function */
2240 { PCI_VDEVICE(MELLANOX, 0x101f) }, /* ConnectX-6 LX */
2241 { PCI_VDEVICE(MELLANOX, 0x1021) }, /* ConnectX-7 */
2242 { PCI_VDEVICE(MELLANOX, 0x1023) }, /* ConnectX-8 */
2243 { PCI_VDEVICE(MELLANOX, 0x1025) }, /* ConnectX-9 */
2244 { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */
2245 { PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF}, /* BlueField integrated ConnectX-5 network controller VF */
2246 { PCI_VDEVICE(MELLANOX, 0xa2d6) }, /* BlueField-2 integrated ConnectX-6 Dx network controller */
2247 { PCI_VDEVICE(MELLANOX, 0xa2dc) }, /* BlueField-3 integrated ConnectX-7 network controller */
2248 { PCI_VDEVICE(MELLANOX, 0xa2df) }, /* BlueField-4 integrated ConnectX-8 network controller */
2249 { 0, }
2250 };
2251
2252 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
2253
mlx5_disable_device(struct mlx5_core_dev * dev)2254 void mlx5_disable_device(struct mlx5_core_dev *dev)
2255 {
2256 mlx5_error_sw_reset(dev);
2257 mlx5_unload_one_devl_locked(dev, false);
2258 }
2259
mlx5_recover_device(struct mlx5_core_dev * dev)2260 int mlx5_recover_device(struct mlx5_core_dev *dev)
2261 {
2262 if (!mlx5_core_is_sf(dev)) {
2263 mlx5_pci_disable_device(dev);
2264 if (mlx5_pci_slot_reset(dev->pdev) != PCI_ERS_RESULT_RECOVERED)
2265 return -EIO;
2266 }
2267
2268 return mlx5_load_one_devl_locked(dev, true);
2269 }
2270
2271 static struct pci_driver mlx5_core_driver = {
2272 .name = KBUILD_MODNAME,
2273 .id_table = mlx5_core_pci_table,
2274 .probe = probe_one,
2275 .remove = remove_one,
2276 .suspend = mlx5_suspend,
2277 .resume = mlx5_resume,
2278 .shutdown = shutdown,
2279 .err_handler = &mlx5_err_handler,
2280 .sriov_configure = mlx5_core_sriov_configure,
2281 .sriov_get_vf_total_msix = mlx5_sriov_get_vf_total_msix,
2282 .sriov_set_msix_vec_count = mlx5_core_sriov_set_msix_vec_count,
2283 };
2284
2285 /**
2286 * mlx5_vf_get_core_dev - Get the mlx5 core device from a given VF PCI device if
2287 * mlx5_core is its driver.
2288 * @pdev: The associated PCI device.
2289 *
2290 * Upon return the interface state lock stay held to let caller uses it safely.
2291 * Caller must ensure to use the returned mlx5 device for a narrow window
2292 * and put it back with mlx5_vf_put_core_dev() immediately once usage was over.
2293 *
2294 * Return: Pointer to the associated mlx5_core_dev or NULL.
2295 */
mlx5_vf_get_core_dev(struct pci_dev * pdev)2296 struct mlx5_core_dev *mlx5_vf_get_core_dev(struct pci_dev *pdev)
2297 {
2298 struct mlx5_core_dev *mdev;
2299
2300 mdev = pci_iov_get_pf_drvdata(pdev, &mlx5_core_driver);
2301 if (IS_ERR(mdev))
2302 return NULL;
2303
2304 mutex_lock(&mdev->intf_state_mutex);
2305 if (!test_bit(MLX5_INTERFACE_STATE_UP, &mdev->intf_state)) {
2306 mutex_unlock(&mdev->intf_state_mutex);
2307 return NULL;
2308 }
2309
2310 return mdev;
2311 }
2312 EXPORT_SYMBOL(mlx5_vf_get_core_dev);
2313
2314 /**
2315 * mlx5_vf_put_core_dev - Put the mlx5 core device back.
2316 * @mdev: The mlx5 core device.
2317 *
2318 * Upon return the interface state lock is unlocked and caller should not
2319 * access the mdev any more.
2320 */
mlx5_vf_put_core_dev(struct mlx5_core_dev * mdev)2321 void mlx5_vf_put_core_dev(struct mlx5_core_dev *mdev)
2322 {
2323 mutex_unlock(&mdev->intf_state_mutex);
2324 }
2325 EXPORT_SYMBOL(mlx5_vf_put_core_dev);
2326
mlx5_core_verify_params(void)2327 static void mlx5_core_verify_params(void)
2328 {
2329 if (prof_sel >= ARRAY_SIZE(profile)) {
2330 pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n",
2331 prof_sel,
2332 ARRAY_SIZE(profile) - 1,
2333 MLX5_DEFAULT_PROF);
2334 prof_sel = MLX5_DEFAULT_PROF;
2335 }
2336 }
2337
mlx5_init(void)2338 static int __init mlx5_init(void)
2339 {
2340 int err;
2341
2342 WARN_ONCE(strcmp(MLX5_ADEV_NAME, KBUILD_MODNAME),
2343 "mlx5_core name not in sync with kernel module name");
2344
2345 get_random_bytes(&sw_owner_id, sizeof(sw_owner_id));
2346
2347 mlx5_core_verify_params();
2348 mlx5_register_debugfs();
2349
2350 err = mlx5e_init();
2351 if (err)
2352 goto err_debug;
2353
2354 err = mlx5_sf_driver_register();
2355 if (err)
2356 goto err_sf;
2357
2358 err = pci_register_driver(&mlx5_core_driver);
2359 if (err)
2360 goto err_pci;
2361
2362 return 0;
2363
2364 err_pci:
2365 mlx5_sf_driver_unregister();
2366 err_sf:
2367 mlx5e_cleanup();
2368 err_debug:
2369 mlx5_unregister_debugfs();
2370 return err;
2371 }
2372
mlx5_cleanup(void)2373 static void __exit mlx5_cleanup(void)
2374 {
2375 pci_unregister_driver(&mlx5_core_driver);
2376 mlx5_sf_driver_unregister();
2377 mlx5e_cleanup();
2378 mlx5_unregister_debugfs();
2379 }
2380
2381 module_init(mlx5_init);
2382 module_exit(mlx5_cleanup);
2383