1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/pci.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/slab.h>
40 #include <linux/interrupt.h>
41 #include <linux/delay.h>
42 #include <linux/mlx5/driver.h>
43 #include <linux/mlx5/cq.h>
44 #include <linux/mlx5/qp.h>
45 #include <linux/debugfs.h>
46 #include <linux/kmod.h>
47 #include <linux/mlx5/mlx5_ifc.h>
48 #include <linux/mlx5/vport.h>
49 #include <linux/version.h>
50 #include <net/devlink.h>
51 #include "mlx5_core.h"
52 #include "lib/eq.h"
53 #include "fs_core.h"
54 #include "lib/mpfs.h"
55 #include "eswitch.h"
56 #include "devlink.h"
57 #include "fw_reset.h"
58 #include "lib/mlx5.h"
59 #include "lib/tout.h"
60 #include "fpga/core.h"
61 #include "en_accel/ipsec.h"
62 #include "lib/clock.h"
63 #include "lib/vxlan.h"
64 #include "lib/geneve.h"
65 #include "lib/devcom.h"
66 #include "lib/pci_vsc.h"
67 #include "diag/fw_tracer.h"
68 #include "ecpf.h"
69 #include "lib/hv_vhca.h"
70 #include "diag/rsc_dump.h"
71 #include "sf/vhca_event.h"
72 #include "sf/dev/dev.h"
73 #include "sf/sf.h"
74 #include "mlx5_irq.h"
75 #include "hwmon.h"
76 #include "lag/lag.h"
77
78 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
79 MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) core driver");
80 MODULE_LICENSE("Dual BSD/GPL");
81
82 unsigned int mlx5_core_debug_mask;
83 module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644);
84 MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
85
86 static unsigned int prof_sel = MLX5_DEFAULT_PROF;
87 module_param_named(prof_sel, prof_sel, uint, 0444);
88 MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
89
90 static u32 sw_owner_id[4];
91 #define MAX_SW_VHCA_ID (BIT(__mlx5_bit_sz(cmd_hca_cap_2, sw_vhca_id)) - 1)
92 static DEFINE_IDA(sw_vhca_ida);
93
94 enum {
95 MLX5_ATOMIC_REQ_MODE_BE = 0x0,
96 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1,
97 };
98
99 #define LOG_MAX_SUPPORTED_QPS 0xff
100
101 static struct mlx5_profile profile[] = {
102 [0] = {
103 .mask = 0,
104 .num_cmd_caches = MLX5_NUM_COMMAND_CACHES,
105 },
106 [1] = {
107 .mask = MLX5_PROF_MASK_QP_SIZE,
108 .log_max_qp = 12,
109 .num_cmd_caches = MLX5_NUM_COMMAND_CACHES,
110
111 },
112 [2] = {
113 .mask = MLX5_PROF_MASK_QP_SIZE |
114 MLX5_PROF_MASK_MR_CACHE,
115 .log_max_qp = LOG_MAX_SUPPORTED_QPS,
116 .num_cmd_caches = MLX5_NUM_COMMAND_CACHES,
117 .mr_cache[0] = {
118 .size = 500,
119 .limit = 250
120 },
121 .mr_cache[1] = {
122 .size = 500,
123 .limit = 250
124 },
125 .mr_cache[2] = {
126 .size = 500,
127 .limit = 250
128 },
129 .mr_cache[3] = {
130 .size = 500,
131 .limit = 250
132 },
133 .mr_cache[4] = {
134 .size = 500,
135 .limit = 250
136 },
137 .mr_cache[5] = {
138 .size = 500,
139 .limit = 250
140 },
141 .mr_cache[6] = {
142 .size = 500,
143 .limit = 250
144 },
145 .mr_cache[7] = {
146 .size = 500,
147 .limit = 250
148 },
149 .mr_cache[8] = {
150 .size = 500,
151 .limit = 250
152 },
153 .mr_cache[9] = {
154 .size = 500,
155 .limit = 250
156 },
157 .mr_cache[10] = {
158 .size = 500,
159 .limit = 250
160 },
161 .mr_cache[11] = {
162 .size = 500,
163 .limit = 250
164 },
165 .mr_cache[12] = {
166 .size = 64,
167 .limit = 32
168 },
169 .mr_cache[13] = {
170 .size = 32,
171 .limit = 16
172 },
173 .mr_cache[14] = {
174 .size = 16,
175 .limit = 8
176 },
177 .mr_cache[15] = {
178 .size = 8,
179 .limit = 4
180 },
181 },
182 [3] = {
183 .mask = MLX5_PROF_MASK_QP_SIZE,
184 .log_max_qp = LOG_MAX_SUPPORTED_QPS,
185 .num_cmd_caches = 0,
186 },
187 };
188
wait_fw_init(struct mlx5_core_dev * dev,u32 max_wait_mili,u32 warn_time_mili,const char * init_state)189 static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili,
190 u32 warn_time_mili, const char *init_state)
191 {
192 unsigned long warn = jiffies + msecs_to_jiffies(warn_time_mili);
193 unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili);
194 u32 fw_initializing;
195
196 do {
197 fw_initializing = ioread32be(&dev->iseg->initializing);
198 if (!(fw_initializing >> 31))
199 break;
200 if (time_after(jiffies, end)) {
201 mlx5_core_err(dev, "Firmware over %u MS in %s state, aborting\n",
202 max_wait_mili, init_state);
203 return -ETIMEDOUT;
204 }
205 if (test_bit(MLX5_BREAK_FW_WAIT, &dev->intf_state)) {
206 mlx5_core_warn(dev, "device is being removed, stop waiting for FW %s\n",
207 init_state);
208 return -ENODEV;
209 }
210 if (warn_time_mili && time_after(jiffies, warn)) {
211 mlx5_core_warn(dev, "Waiting for FW %s, timeout abort in %ds (0x%x)\n",
212 init_state, jiffies_to_msecs(end - warn) / 1000,
213 fw_initializing);
214 warn = jiffies + msecs_to_jiffies(warn_time_mili);
215 }
216 msleep(mlx5_tout_ms(dev, FW_PRE_INIT_WAIT));
217 } while (true);
218
219 return 0;
220 }
221
mlx5_set_driver_version(struct mlx5_core_dev * dev)222 static void mlx5_set_driver_version(struct mlx5_core_dev *dev)
223 {
224 int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in,
225 driver_version);
226 u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {};
227 char *string;
228
229 if (!MLX5_CAP_GEN(dev, driver_version))
230 return;
231
232 string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version);
233
234 snprintf(string, driver_ver_sz, "Linux,%s,%u.%u.%u",
235 KBUILD_MODNAME, LINUX_VERSION_MAJOR,
236 LINUX_VERSION_PATCHLEVEL, LINUX_VERSION_SUBLEVEL);
237
238 /*Send the command*/
239 MLX5_SET(set_driver_version_in, in, opcode,
240 MLX5_CMD_OP_SET_DRIVER_VERSION);
241
242 mlx5_cmd_exec_in(dev, set_driver_version, in);
243 }
244
set_dma_caps(struct pci_dev * pdev)245 static int set_dma_caps(struct pci_dev *pdev)
246 {
247 int err;
248
249 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
250 if (err) {
251 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
252 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
253 if (err) {
254 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
255 return err;
256 }
257 }
258
259 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
260 return err;
261 }
262
mlx5_pci_enable_device(struct mlx5_core_dev * dev)263 static int mlx5_pci_enable_device(struct mlx5_core_dev *dev)
264 {
265 struct pci_dev *pdev = dev->pdev;
266 int err = 0;
267
268 mutex_lock(&dev->pci_status_mutex);
269 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) {
270 err = pci_enable_device(pdev);
271 if (!err)
272 dev->pci_status = MLX5_PCI_STATUS_ENABLED;
273 }
274 mutex_unlock(&dev->pci_status_mutex);
275
276 return err;
277 }
278
mlx5_pci_disable_device(struct mlx5_core_dev * dev)279 static void mlx5_pci_disable_device(struct mlx5_core_dev *dev)
280 {
281 struct pci_dev *pdev = dev->pdev;
282
283 mutex_lock(&dev->pci_status_mutex);
284 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) {
285 pci_disable_device(pdev);
286 dev->pci_status = MLX5_PCI_STATUS_DISABLED;
287 }
288 mutex_unlock(&dev->pci_status_mutex);
289 }
290
request_bar(struct pci_dev * pdev)291 static int request_bar(struct pci_dev *pdev)
292 {
293 int err = 0;
294
295 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
296 dev_err(&pdev->dev, "Missing registers BAR, aborting\n");
297 return -ENODEV;
298 }
299
300 err = pci_request_regions(pdev, KBUILD_MODNAME);
301 if (err)
302 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
303
304 return err;
305 }
306
release_bar(struct pci_dev * pdev)307 static void release_bar(struct pci_dev *pdev)
308 {
309 pci_release_regions(pdev);
310 }
311
312 struct mlx5_reg_host_endianness {
313 u8 he;
314 u8 rsvd[15];
315 };
316
to_fw_pkey_sz(struct mlx5_core_dev * dev,u32 size)317 static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size)
318 {
319 switch (size) {
320 case 128:
321 return 0;
322 case 256:
323 return 1;
324 case 512:
325 return 2;
326 case 1024:
327 return 3;
328 case 2048:
329 return 4;
330 case 4096:
331 return 5;
332 default:
333 mlx5_core_warn(dev, "invalid pkey table size %d\n", size);
334 return 0;
335 }
336 }
337
mlx5_core_uplink_netdev_set(struct mlx5_core_dev * dev,struct net_device * netdev)338 void mlx5_core_uplink_netdev_set(struct mlx5_core_dev *dev, struct net_device *netdev)
339 {
340 mutex_lock(&dev->mlx5e_res.uplink_netdev_lock);
341 dev->mlx5e_res.uplink_netdev = netdev;
342 mlx5_blocking_notifier_call_chain(dev, MLX5_DRIVER_EVENT_UPLINK_NETDEV,
343 netdev);
344 mutex_unlock(&dev->mlx5e_res.uplink_netdev_lock);
345 }
346
mlx5_core_uplink_netdev_event_replay(struct mlx5_core_dev * dev)347 void mlx5_core_uplink_netdev_event_replay(struct mlx5_core_dev *dev)
348 {
349 mutex_lock(&dev->mlx5e_res.uplink_netdev_lock);
350 mlx5_blocking_notifier_call_chain(dev, MLX5_DRIVER_EVENT_UPLINK_NETDEV,
351 dev->mlx5e_res.uplink_netdev);
352 mutex_unlock(&dev->mlx5e_res.uplink_netdev_lock);
353 }
354 EXPORT_SYMBOL(mlx5_core_uplink_netdev_event_replay);
355
mlx5_core_mp_event_replay(struct mlx5_core_dev * dev,u32 event,void * data)356 void mlx5_core_mp_event_replay(struct mlx5_core_dev *dev, u32 event, void *data)
357 {
358 mlx5_blocking_notifier_call_chain(dev, event, data);
359 }
360 EXPORT_SYMBOL(mlx5_core_mp_event_replay);
361
mlx5_core_get_caps_mode(struct mlx5_core_dev * dev,enum mlx5_cap_type cap_type,enum mlx5_cap_mode cap_mode)362 int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type,
363 enum mlx5_cap_mode cap_mode)
364 {
365 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
366 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
367 void *out, *hca_caps;
368 u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
369 int err;
370
371 memset(in, 0, sizeof(in));
372 out = kzalloc(out_sz, GFP_KERNEL);
373 if (!out)
374 return -ENOMEM;
375
376 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
377 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
378 err = mlx5_cmd_exec_inout(dev, query_hca_cap, in, out);
379 if (err) {
380 mlx5_core_warn(dev,
381 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
382 cap_type, cap_mode, err);
383 goto query_ex;
384 }
385
386 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
387
388 switch (cap_mode) {
389 case HCA_CAP_OPMOD_GET_MAX:
390 memcpy(dev->caps.hca[cap_type]->max, hca_caps,
391 MLX5_UN_SZ_BYTES(hca_cap_union));
392 break;
393 case HCA_CAP_OPMOD_GET_CUR:
394 memcpy(dev->caps.hca[cap_type]->cur, hca_caps,
395 MLX5_UN_SZ_BYTES(hca_cap_union));
396 break;
397 default:
398 mlx5_core_warn(dev,
399 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
400 cap_type, cap_mode);
401 err = -EINVAL;
402 break;
403 }
404 query_ex:
405 kfree(out);
406 return err;
407 }
408
mlx5_core_get_caps(struct mlx5_core_dev * dev,enum mlx5_cap_type cap_type)409 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type)
410 {
411 int ret;
412
413 ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR);
414 if (ret)
415 return ret;
416 return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX);
417 }
418
set_caps(struct mlx5_core_dev * dev,void * in,int opmod)419 static int set_caps(struct mlx5_core_dev *dev, void *in, int opmod)
420 {
421 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
422 MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1);
423 return mlx5_cmd_exec_in(dev, set_hca_cap, in);
424 }
425
handle_hca_cap_atomic(struct mlx5_core_dev * dev,void * set_ctx)426 static int handle_hca_cap_atomic(struct mlx5_core_dev *dev, void *set_ctx)
427 {
428 void *set_hca_cap;
429 int req_endianness;
430 int err;
431
432 if (!MLX5_CAP_GEN(dev, atomic))
433 return 0;
434
435 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC);
436 if (err)
437 return err;
438
439 req_endianness =
440 MLX5_CAP_ATOMIC(dev,
441 supported_atomic_req_8B_endianness_mode_1);
442
443 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS)
444 return 0;
445
446 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
447
448 /* Set requestor to host endianness */
449 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianness_mode,
450 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS);
451
452 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC);
453 }
454
handle_hca_cap_odp(struct mlx5_core_dev * dev,void * set_ctx)455 static int handle_hca_cap_odp(struct mlx5_core_dev *dev, void *set_ctx)
456 {
457 void *set_hca_cap;
458 bool do_set = false;
459 int err;
460
461 if (!IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) ||
462 !MLX5_CAP_GEN(dev, pg))
463 return 0;
464
465 err = mlx5_core_get_caps(dev, MLX5_CAP_ODP);
466 if (err)
467 return err;
468
469 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
470 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_ODP]->cur,
471 MLX5_ST_SZ_BYTES(odp_cap));
472
473 #define ODP_CAP_SET_MAX(dev, field) \
474 do { \
475 u32 _res = MLX5_CAP_ODP_MAX(dev, field); \
476 if (_res) { \
477 do_set = true; \
478 MLX5_SET(odp_cap, set_hca_cap, field, _res); \
479 } \
480 } while (0)
481
482 ODP_CAP_SET_MAX(dev, ud_odp_caps.srq_receive);
483 ODP_CAP_SET_MAX(dev, rc_odp_caps.srq_receive);
484 ODP_CAP_SET_MAX(dev, xrc_odp_caps.srq_receive);
485 ODP_CAP_SET_MAX(dev, xrc_odp_caps.send);
486 ODP_CAP_SET_MAX(dev, xrc_odp_caps.receive);
487 ODP_CAP_SET_MAX(dev, xrc_odp_caps.write);
488 ODP_CAP_SET_MAX(dev, xrc_odp_caps.read);
489 ODP_CAP_SET_MAX(dev, xrc_odp_caps.atomic);
490 ODP_CAP_SET_MAX(dev, dc_odp_caps.srq_receive);
491 ODP_CAP_SET_MAX(dev, dc_odp_caps.send);
492 ODP_CAP_SET_MAX(dev, dc_odp_caps.receive);
493 ODP_CAP_SET_MAX(dev, dc_odp_caps.write);
494 ODP_CAP_SET_MAX(dev, dc_odp_caps.read);
495 ODP_CAP_SET_MAX(dev, dc_odp_caps.atomic);
496
497 if (!do_set)
498 return 0;
499
500 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ODP);
501 }
502
max_uc_list_get_devlink_param(struct mlx5_core_dev * dev)503 static int max_uc_list_get_devlink_param(struct mlx5_core_dev *dev)
504 {
505 struct devlink *devlink = priv_to_devlink(dev);
506 union devlink_param_value val;
507 int err;
508
509 err = devl_param_driverinit_value_get(devlink,
510 DEVLINK_PARAM_GENERIC_ID_MAX_MACS,
511 &val);
512 if (!err)
513 return val.vu32;
514 mlx5_core_dbg(dev, "Failed to get param. err = %d\n", err);
515 return err;
516 }
517
mlx5_is_roce_on(struct mlx5_core_dev * dev)518 bool mlx5_is_roce_on(struct mlx5_core_dev *dev)
519 {
520 struct devlink *devlink = priv_to_devlink(dev);
521 union devlink_param_value val;
522 int err;
523
524 err = devl_param_driverinit_value_get(devlink,
525 DEVLINK_PARAM_GENERIC_ID_ENABLE_ROCE,
526 &val);
527
528 if (!err)
529 return val.vbool;
530
531 mlx5_core_dbg(dev, "Failed to get param. err = %d\n", err);
532 return MLX5_CAP_GEN(dev, roce);
533 }
534 EXPORT_SYMBOL(mlx5_is_roce_on);
535
handle_hca_cap_2(struct mlx5_core_dev * dev,void * set_ctx)536 static int handle_hca_cap_2(struct mlx5_core_dev *dev, void *set_ctx)
537 {
538 void *set_hca_cap;
539 int err;
540
541 if (!MLX5_CAP_GEN_MAX(dev, hca_cap_2))
542 return 0;
543
544 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL_2);
545 if (err)
546 return err;
547
548 if (!MLX5_CAP_GEN_2_MAX(dev, sw_vhca_id_valid) ||
549 !(dev->priv.sw_vhca_id > 0))
550 return 0;
551
552 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
553 capability);
554 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_GENERAL_2]->cur,
555 MLX5_ST_SZ_BYTES(cmd_hca_cap_2));
556 MLX5_SET(cmd_hca_cap_2, set_hca_cap, sw_vhca_id_valid, 1);
557
558 return set_caps(dev, set_ctx, MLX5_CAP_GENERAL_2);
559 }
560
handle_hca_cap(struct mlx5_core_dev * dev,void * set_ctx)561 static int handle_hca_cap(struct mlx5_core_dev *dev, void *set_ctx)
562 {
563 struct mlx5_profile *prof = &dev->profile;
564 void *set_hca_cap;
565 int max_uc_list;
566 int err;
567
568 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL);
569 if (err)
570 return err;
571
572 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
573 capability);
574 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_GENERAL]->cur,
575 MLX5_ST_SZ_BYTES(cmd_hca_cap));
576
577 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
578 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
579 128);
580 /* we limit the size of the pkey table to 128 entries for now */
581 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
582 to_fw_pkey_sz(dev, 128));
583
584 /* Check log_max_qp from HCA caps to set in current profile */
585 if (prof->log_max_qp == LOG_MAX_SUPPORTED_QPS) {
586 prof->log_max_qp = min_t(u8, 18, MLX5_CAP_GEN_MAX(dev, log_max_qp));
587 } else if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < prof->log_max_qp) {
588 mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n",
589 prof->log_max_qp,
590 MLX5_CAP_GEN_MAX(dev, log_max_qp));
591 prof->log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp);
592 }
593 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
594 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
595 prof->log_max_qp);
596
597 /* disable cmdif checksum */
598 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
599
600 /* Enable 4K UAR only when HCA supports it and page size is bigger
601 * than 4K.
602 */
603 if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096)
604 MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1);
605
606 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
607
608 if (MLX5_CAP_GEN_MAX(dev, cache_line_128byte))
609 MLX5_SET(cmd_hca_cap,
610 set_hca_cap,
611 cache_line_128byte,
612 cache_line_size() >= 128 ? 1 : 0);
613
614 if (MLX5_CAP_GEN_MAX(dev, dct))
615 MLX5_SET(cmd_hca_cap, set_hca_cap, dct, 1);
616
617 if (MLX5_CAP_GEN_MAX(dev, pci_sync_for_fw_update_event))
618 MLX5_SET(cmd_hca_cap, set_hca_cap, pci_sync_for_fw_update_event, 1);
619 if (MLX5_CAP_GEN_MAX(dev, pci_sync_for_fw_update_with_driver_unload))
620 MLX5_SET(cmd_hca_cap, set_hca_cap,
621 pci_sync_for_fw_update_with_driver_unload, 1);
622 if (MLX5_CAP_GEN_MAX(dev, pcie_reset_using_hotreset_method))
623 MLX5_SET(cmd_hca_cap, set_hca_cap,
624 pcie_reset_using_hotreset_method, 1);
625
626 if (MLX5_CAP_GEN_MAX(dev, num_vhca_ports))
627 MLX5_SET(cmd_hca_cap,
628 set_hca_cap,
629 num_vhca_ports,
630 MLX5_CAP_GEN_MAX(dev, num_vhca_ports));
631
632 if (MLX5_CAP_GEN_MAX(dev, release_all_pages))
633 MLX5_SET(cmd_hca_cap, set_hca_cap, release_all_pages, 1);
634
635 if (MLX5_CAP_GEN_MAX(dev, mkey_by_name))
636 MLX5_SET(cmd_hca_cap, set_hca_cap, mkey_by_name, 1);
637
638 mlx5_vhca_state_cap_handle(dev, set_hca_cap);
639
640 if (MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix))
641 MLX5_SET(cmd_hca_cap, set_hca_cap, num_total_dynamic_vf_msix,
642 MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix));
643
644 if (MLX5_CAP_GEN(dev, roce_rw_supported) && MLX5_CAP_GEN_MAX(dev, roce))
645 MLX5_SET(cmd_hca_cap, set_hca_cap, roce,
646 mlx5_is_roce_on(dev));
647
648 max_uc_list = max_uc_list_get_devlink_param(dev);
649 if (max_uc_list > 0)
650 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_current_uc_list,
651 ilog2(max_uc_list));
652
653 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE);
654 }
655
656 /* Cached MLX5_CAP_GEN(dev, roce) can be out of sync this early in the
657 * boot process.
658 * In case RoCE cap is writable in FW and user/devlink requested to change the
659 * cap, we are yet to query the final state of the above cap.
660 * Hence, the need for this function.
661 *
662 * Returns
663 * True:
664 * 1) RoCE cap is read only in FW and already disabled
665 * OR:
666 * 2) RoCE cap is writable in FW and user/devlink requested it off.
667 *
668 * In any other case, return False.
669 */
is_roce_fw_disabled(struct mlx5_core_dev * dev)670 static bool is_roce_fw_disabled(struct mlx5_core_dev *dev)
671 {
672 return (MLX5_CAP_GEN(dev, roce_rw_supported) && !mlx5_is_roce_on(dev)) ||
673 (!MLX5_CAP_GEN(dev, roce_rw_supported) && !MLX5_CAP_GEN(dev, roce));
674 }
675
handle_hca_cap_roce(struct mlx5_core_dev * dev,void * set_ctx)676 static int handle_hca_cap_roce(struct mlx5_core_dev *dev, void *set_ctx)
677 {
678 void *set_hca_cap;
679 int err;
680
681 if (is_roce_fw_disabled(dev))
682 return 0;
683
684 err = mlx5_core_get_caps(dev, MLX5_CAP_ROCE);
685 if (err)
686 return err;
687
688 if (MLX5_CAP_ROCE(dev, sw_r_roce_src_udp_port) ||
689 !MLX5_CAP_ROCE_MAX(dev, sw_r_roce_src_udp_port))
690 return 0;
691
692 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
693 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_ROCE]->cur,
694 MLX5_ST_SZ_BYTES(roce_cap));
695 MLX5_SET(roce_cap, set_hca_cap, sw_r_roce_src_udp_port, 1);
696
697 if (MLX5_CAP_ROCE_MAX(dev, qp_ooo_transmit_default))
698 MLX5_SET(roce_cap, set_hca_cap, qp_ooo_transmit_default, 1);
699
700 err = set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ROCE);
701 return err;
702 }
703
handle_hca_cap_port_selection(struct mlx5_core_dev * dev,void * set_ctx)704 static int handle_hca_cap_port_selection(struct mlx5_core_dev *dev,
705 void *set_ctx)
706 {
707 void *set_hca_cap;
708 int err;
709
710 if (!MLX5_CAP_GEN(dev, port_selection_cap))
711 return 0;
712
713 err = mlx5_core_get_caps(dev, MLX5_CAP_PORT_SELECTION);
714 if (err)
715 return err;
716
717 if (MLX5_CAP_PORT_SELECTION(dev, port_select_flow_table_bypass) ||
718 !MLX5_CAP_PORT_SELECTION_MAX(dev, port_select_flow_table_bypass))
719 return 0;
720
721 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
722 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_PORT_SELECTION]->cur,
723 MLX5_ST_SZ_BYTES(port_selection_cap));
724 MLX5_SET(port_selection_cap, set_hca_cap, port_select_flow_table_bypass, 1);
725
726 err = set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_PORT_SELECTION);
727
728 return err;
729 }
730
set_hca_cap(struct mlx5_core_dev * dev)731 static int set_hca_cap(struct mlx5_core_dev *dev)
732 {
733 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
734 void *set_ctx;
735 int err;
736
737 set_ctx = kzalloc(set_sz, GFP_KERNEL);
738 if (!set_ctx)
739 return -ENOMEM;
740
741 err = handle_hca_cap(dev, set_ctx);
742 if (err) {
743 mlx5_core_err(dev, "handle_hca_cap failed\n");
744 goto out;
745 }
746
747 memset(set_ctx, 0, set_sz);
748 err = handle_hca_cap_atomic(dev, set_ctx);
749 if (err) {
750 mlx5_core_err(dev, "handle_hca_cap_atomic failed\n");
751 goto out;
752 }
753
754 memset(set_ctx, 0, set_sz);
755 err = handle_hca_cap_odp(dev, set_ctx);
756 if (err) {
757 mlx5_core_err(dev, "handle_hca_cap_odp failed\n");
758 goto out;
759 }
760
761 memset(set_ctx, 0, set_sz);
762 err = handle_hca_cap_roce(dev, set_ctx);
763 if (err) {
764 mlx5_core_err(dev, "handle_hca_cap_roce failed\n");
765 goto out;
766 }
767
768 memset(set_ctx, 0, set_sz);
769 err = handle_hca_cap_2(dev, set_ctx);
770 if (err) {
771 mlx5_core_err(dev, "handle_hca_cap_2 failed\n");
772 goto out;
773 }
774
775 memset(set_ctx, 0, set_sz);
776 err = handle_hca_cap_port_selection(dev, set_ctx);
777 if (err) {
778 mlx5_core_err(dev, "handle_hca_cap_port_selection failed\n");
779 goto out;
780 }
781
782 out:
783 kfree(set_ctx);
784 return err;
785 }
786
set_hca_ctrl(struct mlx5_core_dev * dev)787 static int set_hca_ctrl(struct mlx5_core_dev *dev)
788 {
789 struct mlx5_reg_host_endianness he_in;
790 struct mlx5_reg_host_endianness he_out;
791 int err;
792
793 if (!mlx5_core_is_pf(dev))
794 return 0;
795
796 memset(&he_in, 0, sizeof(he_in));
797 he_in.he = MLX5_SET_HOST_ENDIANNESS;
798 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
799 &he_out, sizeof(he_out),
800 MLX5_REG_HOST_ENDIANNESS, 0, 1);
801 return err;
802 }
803
mlx5_core_set_hca_defaults(struct mlx5_core_dev * dev)804 static int mlx5_core_set_hca_defaults(struct mlx5_core_dev *dev)
805 {
806 int ret = 0;
807
808 /* Disable local_lb by default */
809 if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH)
810 ret = mlx5_nic_vport_update_local_lb(dev, false);
811
812 return ret;
813 }
814
mlx5_core_enable_hca(struct mlx5_core_dev * dev,u16 func_id)815 int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id)
816 {
817 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {};
818
819 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA);
820 MLX5_SET(enable_hca_in, in, function_id, func_id);
821 MLX5_SET(enable_hca_in, in, embedded_cpu_function,
822 dev->caps.embedded_cpu);
823 return mlx5_cmd_exec_in(dev, enable_hca, in);
824 }
825
mlx5_core_disable_hca(struct mlx5_core_dev * dev,u16 func_id)826 int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id)
827 {
828 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {};
829
830 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA);
831 MLX5_SET(disable_hca_in, in, function_id, func_id);
832 MLX5_SET(enable_hca_in, in, embedded_cpu_function,
833 dev->caps.embedded_cpu);
834 return mlx5_cmd_exec_in(dev, disable_hca, in);
835 }
836
mlx5_core_set_issi(struct mlx5_core_dev * dev)837 static int mlx5_core_set_issi(struct mlx5_core_dev *dev)
838 {
839 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {};
840 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {};
841 u32 sup_issi;
842 int err;
843
844 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI);
845 err = mlx5_cmd_exec_inout(dev, query_issi, query_in, query_out);
846 if (err) {
847 u32 syndrome = MLX5_GET(query_issi_out, query_out, syndrome);
848 u8 status = MLX5_GET(query_issi_out, query_out, status);
849
850 if (!status || syndrome == MLX5_DRIVER_SYND) {
851 mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n",
852 err, status, syndrome);
853 return err;
854 }
855
856 mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n");
857 dev->issi = 0;
858 return 0;
859 }
860
861 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0);
862
863 if (sup_issi & (1 << 1)) {
864 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {};
865
866 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI);
867 MLX5_SET(set_issi_in, set_in, current_issi, 1);
868 err = mlx5_cmd_exec_in(dev, set_issi, set_in);
869 if (err) {
870 mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n",
871 err);
872 return err;
873 }
874
875 dev->issi = 1;
876
877 return 0;
878 } else if (sup_issi & (1 << 0) || !sup_issi) {
879 return 0;
880 }
881
882 return -EOPNOTSUPP;
883 }
884
mlx5_pci_init(struct mlx5_core_dev * dev,struct pci_dev * pdev,const struct pci_device_id * id)885 static int mlx5_pci_init(struct mlx5_core_dev *dev, struct pci_dev *pdev,
886 const struct pci_device_id *id)
887 {
888 int err = 0;
889
890 mutex_init(&dev->pci_status_mutex);
891 pci_set_drvdata(dev->pdev, dev);
892
893 dev->bar_addr = pci_resource_start(pdev, 0);
894
895 err = mlx5_pci_enable_device(dev);
896 if (err) {
897 mlx5_core_err(dev, "Cannot enable PCI device, aborting\n");
898 return err;
899 }
900
901 err = request_bar(pdev);
902 if (err) {
903 mlx5_core_err(dev, "error requesting BARs, aborting\n");
904 goto err_disable;
905 }
906
907 pci_set_master(pdev);
908
909 err = set_dma_caps(pdev);
910 if (err) {
911 mlx5_core_err(dev, "Failed setting DMA capabilities mask, aborting\n");
912 goto err_clr_master;
913 }
914
915 if (pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP32) &&
916 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP64) &&
917 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP128))
918 mlx5_core_dbg(dev, "Enabling pci atomics failed\n");
919
920 dev->iseg_base = dev->bar_addr;
921 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
922 if (!dev->iseg) {
923 err = -ENOMEM;
924 mlx5_core_err(dev, "Failed mapping initialization segment, aborting\n");
925 goto err_clr_master;
926 }
927
928 mlx5_pci_vsc_init(dev);
929
930 err = pci_enable_ptm(pdev, NULL);
931 if (err)
932 mlx5_core_info(dev, "PTM is not supported by PCIe\n");
933
934 return 0;
935
936 err_clr_master:
937 release_bar(dev->pdev);
938 err_disable:
939 mlx5_pci_disable_device(dev);
940 return err;
941 }
942
mlx5_pci_close(struct mlx5_core_dev * dev)943 static void mlx5_pci_close(struct mlx5_core_dev *dev)
944 {
945 /* health work might still be active, and it needs pci bar in
946 * order to know the NIC state. Therefore, drain the health WQ
947 * before removing the pci bars
948 */
949 mlx5_drain_health_wq(dev);
950 pci_disable_ptm(dev->pdev);
951 iounmap(dev->iseg);
952 release_bar(dev->pdev);
953 mlx5_pci_disable_device(dev);
954 }
955
mlx5_register_hca_devcom_comp(struct mlx5_core_dev * dev)956 static void mlx5_register_hca_devcom_comp(struct mlx5_core_dev *dev)
957 {
958 /* This component is use to sync adding core_dev to lag_dev and to sync
959 * changes of mlx5_adev_devices between LAG layer and other layers.
960 */
961 if (!mlx5_lag_is_supported(dev))
962 return;
963
964 dev->priv.hca_devcom_comp =
965 mlx5_devcom_register_component(dev->priv.devc, MLX5_DEVCOM_HCA_PORTS,
966 mlx5_query_nic_system_image_guid(dev),
967 NULL, dev);
968 if (IS_ERR(dev->priv.hca_devcom_comp))
969 mlx5_core_err(dev, "Failed to register devcom HCA component\n");
970 }
971
mlx5_unregister_hca_devcom_comp(struct mlx5_core_dev * dev)972 static void mlx5_unregister_hca_devcom_comp(struct mlx5_core_dev *dev)
973 {
974 mlx5_devcom_unregister_component(dev->priv.hca_devcom_comp);
975 }
976
mlx5_init_once(struct mlx5_core_dev * dev)977 static int mlx5_init_once(struct mlx5_core_dev *dev)
978 {
979 int err;
980
981 dev->priv.devc = mlx5_devcom_register_device(dev);
982 if (IS_ERR(dev->priv.devc))
983 mlx5_core_warn(dev, "failed to register devcom device %ld\n",
984 PTR_ERR(dev->priv.devc));
985 mlx5_register_hca_devcom_comp(dev);
986
987 err = mlx5_query_board_id(dev);
988 if (err) {
989 mlx5_core_err(dev, "query board id failed\n");
990 goto err_devcom;
991 }
992
993 err = mlx5_irq_table_init(dev);
994 if (err) {
995 mlx5_core_err(dev, "failed to initialize irq table\n");
996 goto err_devcom;
997 }
998
999 err = mlx5_eq_table_init(dev);
1000 if (err) {
1001 mlx5_core_err(dev, "failed to initialize eq\n");
1002 goto err_irq_cleanup;
1003 }
1004
1005 err = mlx5_events_init(dev);
1006 if (err) {
1007 mlx5_core_err(dev, "failed to initialize events\n");
1008 goto err_eq_cleanup;
1009 }
1010
1011 err = mlx5_fw_reset_init(dev);
1012 if (err) {
1013 mlx5_core_err(dev, "failed to initialize fw reset events\n");
1014 goto err_events_cleanup;
1015 }
1016
1017 mlx5_cq_debugfs_init(dev);
1018
1019 mlx5_init_reserved_gids(dev);
1020
1021 mlx5_init_clock(dev);
1022
1023 dev->vxlan = mlx5_vxlan_create(dev);
1024 dev->geneve = mlx5_geneve_create(dev);
1025
1026 err = mlx5_init_rl_table(dev);
1027 if (err) {
1028 mlx5_core_err(dev, "Failed to init rate limiting\n");
1029 goto err_tables_cleanup;
1030 }
1031
1032 err = mlx5_mpfs_init(dev);
1033 if (err) {
1034 mlx5_core_err(dev, "Failed to init l2 table %d\n", err);
1035 goto err_rl_cleanup;
1036 }
1037
1038 err = mlx5_sriov_init(dev);
1039 if (err) {
1040 mlx5_core_err(dev, "Failed to init sriov %d\n", err);
1041 goto err_mpfs_cleanup;
1042 }
1043
1044 err = mlx5_eswitch_init(dev);
1045 if (err) {
1046 mlx5_core_err(dev, "Failed to init eswitch %d\n", err);
1047 goto err_sriov_cleanup;
1048 }
1049
1050 err = mlx5_fpga_init(dev);
1051 if (err) {
1052 mlx5_core_err(dev, "Failed to init fpga device %d\n", err);
1053 goto err_eswitch_cleanup;
1054 }
1055
1056 err = mlx5_vhca_event_init(dev);
1057 if (err) {
1058 mlx5_core_err(dev, "Failed to init vhca event notifier %d\n", err);
1059 goto err_fpga_cleanup;
1060 }
1061
1062 err = mlx5_sf_hw_table_init(dev);
1063 if (err) {
1064 mlx5_core_err(dev, "Failed to init SF HW table %d\n", err);
1065 goto err_sf_hw_table_cleanup;
1066 }
1067
1068 err = mlx5_sf_table_init(dev);
1069 if (err) {
1070 mlx5_core_err(dev, "Failed to init SF table %d\n", err);
1071 goto err_sf_table_cleanup;
1072 }
1073
1074 err = mlx5_fs_core_alloc(dev);
1075 if (err) {
1076 mlx5_core_err(dev, "Failed to alloc flow steering\n");
1077 goto err_fs;
1078 }
1079
1080 dev->dm = mlx5_dm_create(dev);
1081 if (IS_ERR(dev->dm))
1082 mlx5_core_warn(dev, "Failed to init device memory %ld\n", PTR_ERR(dev->dm));
1083
1084 dev->tracer = mlx5_fw_tracer_create(dev);
1085 dev->hv_vhca = mlx5_hv_vhca_create(dev);
1086 dev->rsc_dump = mlx5_rsc_dump_create(dev);
1087
1088 return 0;
1089
1090 err_fs:
1091 mlx5_sf_table_cleanup(dev);
1092 err_sf_table_cleanup:
1093 mlx5_sf_hw_table_cleanup(dev);
1094 err_sf_hw_table_cleanup:
1095 mlx5_vhca_event_cleanup(dev);
1096 err_fpga_cleanup:
1097 mlx5_fpga_cleanup(dev);
1098 err_eswitch_cleanup:
1099 mlx5_eswitch_cleanup(dev->priv.eswitch);
1100 err_sriov_cleanup:
1101 mlx5_sriov_cleanup(dev);
1102 err_mpfs_cleanup:
1103 mlx5_mpfs_cleanup(dev);
1104 err_rl_cleanup:
1105 mlx5_cleanup_rl_table(dev);
1106 err_tables_cleanup:
1107 mlx5_geneve_destroy(dev->geneve);
1108 mlx5_vxlan_destroy(dev->vxlan);
1109 mlx5_cleanup_clock(dev);
1110 mlx5_cleanup_reserved_gids(dev);
1111 mlx5_cq_debugfs_cleanup(dev);
1112 mlx5_fw_reset_cleanup(dev);
1113 err_events_cleanup:
1114 mlx5_events_cleanup(dev);
1115 err_eq_cleanup:
1116 mlx5_eq_table_cleanup(dev);
1117 err_irq_cleanup:
1118 mlx5_irq_table_cleanup(dev);
1119 err_devcom:
1120 mlx5_unregister_hca_devcom_comp(dev);
1121 mlx5_devcom_unregister_device(dev->priv.devc);
1122
1123 return err;
1124 }
1125
mlx5_cleanup_once(struct mlx5_core_dev * dev)1126 static void mlx5_cleanup_once(struct mlx5_core_dev *dev)
1127 {
1128 mlx5_rsc_dump_destroy(dev);
1129 mlx5_hv_vhca_destroy(dev->hv_vhca);
1130 mlx5_fw_tracer_destroy(dev->tracer);
1131 mlx5_dm_cleanup(dev);
1132 mlx5_fs_core_free(dev);
1133 mlx5_sf_table_cleanup(dev);
1134 mlx5_sf_hw_table_cleanup(dev);
1135 mlx5_vhca_event_cleanup(dev);
1136 mlx5_fpga_cleanup(dev);
1137 mlx5_eswitch_cleanup(dev->priv.eswitch);
1138 mlx5_sriov_cleanup(dev);
1139 mlx5_mpfs_cleanup(dev);
1140 mlx5_cleanup_rl_table(dev);
1141 mlx5_geneve_destroy(dev->geneve);
1142 mlx5_vxlan_destroy(dev->vxlan);
1143 mlx5_cleanup_clock(dev);
1144 mlx5_cleanup_reserved_gids(dev);
1145 mlx5_cq_debugfs_cleanup(dev);
1146 mlx5_fw_reset_cleanup(dev);
1147 mlx5_events_cleanup(dev);
1148 mlx5_eq_table_cleanup(dev);
1149 mlx5_irq_table_cleanup(dev);
1150 mlx5_unregister_hca_devcom_comp(dev);
1151 mlx5_devcom_unregister_device(dev->priv.devc);
1152 }
1153
mlx5_function_enable(struct mlx5_core_dev * dev,bool boot,u64 timeout)1154 static int mlx5_function_enable(struct mlx5_core_dev *dev, bool boot, u64 timeout)
1155 {
1156 int err;
1157
1158 mlx5_core_info(dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
1159 fw_rev_min(dev), fw_rev_sub(dev));
1160
1161 /* Only PFs hold the relevant PCIe information for this query */
1162 if (mlx5_core_is_pf(dev))
1163 pcie_print_link_status(dev->pdev);
1164
1165 /* wait for firmware to accept initialization segments configurations
1166 */
1167 err = wait_fw_init(dev, timeout,
1168 mlx5_tout_ms(dev, FW_PRE_INIT_WARN_MESSAGE_INTERVAL),
1169 "pre-initializing");
1170 if (err)
1171 return err;
1172
1173 err = mlx5_cmd_enable(dev);
1174 if (err) {
1175 mlx5_core_err(dev, "Failed initializing command interface, aborting\n");
1176 return err;
1177 }
1178
1179 mlx5_tout_query_iseg(dev);
1180
1181 err = wait_fw_init(dev, mlx5_tout_ms(dev, FW_INIT), 0, "initializing");
1182 if (err)
1183 goto err_cmd_cleanup;
1184
1185 dev->caps.embedded_cpu = mlx5_read_embedded_cpu(dev);
1186 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_UP);
1187
1188 mlx5_start_health_poll(dev);
1189
1190 err = mlx5_core_enable_hca(dev, 0);
1191 if (err) {
1192 mlx5_core_err(dev, "enable hca failed\n");
1193 goto stop_health_poll;
1194 }
1195
1196 err = mlx5_core_set_issi(dev);
1197 if (err) {
1198 mlx5_core_err(dev, "failed to set issi\n");
1199 goto err_disable_hca;
1200 }
1201
1202 err = mlx5_satisfy_startup_pages(dev, 1);
1203 if (err) {
1204 mlx5_core_err(dev, "failed to allocate boot pages\n");
1205 goto err_disable_hca;
1206 }
1207
1208 err = mlx5_tout_query_dtor(dev);
1209 if (err) {
1210 mlx5_core_err(dev, "failed to read dtor\n");
1211 goto reclaim_boot_pages;
1212 }
1213
1214 return 0;
1215
1216 reclaim_boot_pages:
1217 mlx5_reclaim_startup_pages(dev);
1218 err_disable_hca:
1219 mlx5_core_disable_hca(dev, 0);
1220 stop_health_poll:
1221 mlx5_stop_health_poll(dev, boot);
1222 err_cmd_cleanup:
1223 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN);
1224 mlx5_cmd_disable(dev);
1225
1226 return err;
1227 }
1228
mlx5_function_disable(struct mlx5_core_dev * dev,bool boot)1229 static void mlx5_function_disable(struct mlx5_core_dev *dev, bool boot)
1230 {
1231 mlx5_reclaim_startup_pages(dev);
1232 mlx5_core_disable_hca(dev, 0);
1233 mlx5_stop_health_poll(dev, boot);
1234 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN);
1235 mlx5_cmd_disable(dev);
1236 }
1237
mlx5_function_open(struct mlx5_core_dev * dev)1238 static int mlx5_function_open(struct mlx5_core_dev *dev)
1239 {
1240 int err;
1241
1242 err = set_hca_ctrl(dev);
1243 if (err) {
1244 mlx5_core_err(dev, "set_hca_ctrl failed\n");
1245 return err;
1246 }
1247
1248 err = set_hca_cap(dev);
1249 if (err) {
1250 mlx5_core_err(dev, "set_hca_cap failed\n");
1251 return err;
1252 }
1253
1254 err = mlx5_satisfy_startup_pages(dev, 0);
1255 if (err) {
1256 mlx5_core_err(dev, "failed to allocate init pages\n");
1257 return err;
1258 }
1259
1260 err = mlx5_cmd_init_hca(dev, sw_owner_id);
1261 if (err) {
1262 mlx5_core_err(dev, "init hca failed\n");
1263 return err;
1264 }
1265
1266 mlx5_set_driver_version(dev);
1267
1268 err = mlx5_query_hca_caps(dev);
1269 if (err) {
1270 mlx5_core_err(dev, "query hca failed\n");
1271 return err;
1272 }
1273 mlx5_start_health_fw_log_up(dev);
1274 return 0;
1275 }
1276
mlx5_function_close(struct mlx5_core_dev * dev)1277 static int mlx5_function_close(struct mlx5_core_dev *dev)
1278 {
1279 int err;
1280
1281 err = mlx5_cmd_teardown_hca(dev);
1282 if (err) {
1283 mlx5_core_err(dev, "tear_down_hca failed, skip cleanup\n");
1284 return err;
1285 }
1286
1287 return 0;
1288 }
1289
mlx5_function_setup(struct mlx5_core_dev * dev,bool boot,u64 timeout)1290 static int mlx5_function_setup(struct mlx5_core_dev *dev, bool boot, u64 timeout)
1291 {
1292 int err;
1293
1294 err = mlx5_function_enable(dev, boot, timeout);
1295 if (err)
1296 return err;
1297
1298 err = mlx5_function_open(dev);
1299 if (err)
1300 mlx5_function_disable(dev, boot);
1301 return err;
1302 }
1303
mlx5_function_teardown(struct mlx5_core_dev * dev,bool boot)1304 static int mlx5_function_teardown(struct mlx5_core_dev *dev, bool boot)
1305 {
1306 int err = mlx5_function_close(dev);
1307
1308 if (!err)
1309 mlx5_function_disable(dev, boot);
1310 else
1311 mlx5_stop_health_poll(dev, boot);
1312
1313 return err;
1314 }
1315
mlx5_load(struct mlx5_core_dev * dev)1316 static int mlx5_load(struct mlx5_core_dev *dev)
1317 {
1318 int err;
1319
1320 dev->priv.uar = mlx5_get_uars_page(dev);
1321 if (IS_ERR(dev->priv.uar)) {
1322 mlx5_core_err(dev, "Failed allocating uar, aborting\n");
1323 err = PTR_ERR(dev->priv.uar);
1324 return err;
1325 }
1326
1327 mlx5_events_start(dev);
1328 mlx5_pagealloc_start(dev);
1329
1330 err = mlx5_irq_table_create(dev);
1331 if (err) {
1332 mlx5_core_err(dev, "Failed to alloc IRQs\n");
1333 goto err_irq_table;
1334 }
1335
1336 err = mlx5_eq_table_create(dev);
1337 if (err) {
1338 mlx5_core_err(dev, "Failed to create EQs\n");
1339 goto err_eq_table;
1340 }
1341
1342 err = mlx5_fw_tracer_init(dev->tracer);
1343 if (err) {
1344 mlx5_core_err(dev, "Failed to init FW tracer %d\n", err);
1345 mlx5_fw_tracer_destroy(dev->tracer);
1346 dev->tracer = NULL;
1347 }
1348
1349 mlx5_fw_reset_events_start(dev);
1350 mlx5_hv_vhca_init(dev->hv_vhca);
1351
1352 err = mlx5_rsc_dump_init(dev);
1353 if (err) {
1354 mlx5_core_err(dev, "Failed to init Resource dump %d\n", err);
1355 mlx5_rsc_dump_destroy(dev);
1356 dev->rsc_dump = NULL;
1357 }
1358
1359 err = mlx5_fpga_device_start(dev);
1360 if (err) {
1361 mlx5_core_err(dev, "fpga device start failed %d\n", err);
1362 goto err_fpga_start;
1363 }
1364
1365 err = mlx5_fs_core_init(dev);
1366 if (err) {
1367 mlx5_core_err(dev, "Failed to init flow steering\n");
1368 goto err_fs;
1369 }
1370
1371 err = mlx5_core_set_hca_defaults(dev);
1372 if (err) {
1373 mlx5_core_err(dev, "Failed to set hca defaults\n");
1374 goto err_set_hca;
1375 }
1376
1377 mlx5_vhca_event_start(dev);
1378
1379 err = mlx5_sf_hw_table_create(dev);
1380 if (err) {
1381 mlx5_core_err(dev, "sf table create failed %d\n", err);
1382 goto err_vhca;
1383 }
1384
1385 err = mlx5_ec_init(dev);
1386 if (err) {
1387 mlx5_core_err(dev, "Failed to init embedded CPU\n");
1388 goto err_ec;
1389 }
1390
1391 mlx5_lag_add_mdev(dev);
1392 err = mlx5_sriov_attach(dev);
1393 if (err) {
1394 mlx5_core_err(dev, "sriov init failed %d\n", err);
1395 goto err_sriov;
1396 }
1397
1398 mlx5_sf_dev_table_create(dev);
1399
1400 err = mlx5_devlink_traps_register(priv_to_devlink(dev));
1401 if (err)
1402 goto err_traps_reg;
1403
1404 return 0;
1405
1406 err_traps_reg:
1407 mlx5_sf_dev_table_destroy(dev);
1408 mlx5_sriov_detach(dev);
1409 err_sriov:
1410 mlx5_lag_remove_mdev(dev);
1411 mlx5_ec_cleanup(dev);
1412 err_ec:
1413 mlx5_sf_hw_table_destroy(dev);
1414 err_vhca:
1415 mlx5_vhca_event_stop(dev);
1416 err_set_hca:
1417 mlx5_fs_core_cleanup(dev);
1418 err_fs:
1419 mlx5_fpga_device_stop(dev);
1420 err_fpga_start:
1421 mlx5_rsc_dump_cleanup(dev);
1422 mlx5_hv_vhca_cleanup(dev->hv_vhca);
1423 mlx5_fw_reset_events_stop(dev);
1424 mlx5_fw_tracer_cleanup(dev->tracer);
1425 mlx5_eq_table_destroy(dev);
1426 err_eq_table:
1427 mlx5_irq_table_destroy(dev);
1428 err_irq_table:
1429 mlx5_pagealloc_stop(dev);
1430 mlx5_events_stop(dev);
1431 mlx5_put_uars_page(dev, dev->priv.uar);
1432 return err;
1433 }
1434
mlx5_unload(struct mlx5_core_dev * dev)1435 static void mlx5_unload(struct mlx5_core_dev *dev)
1436 {
1437 mlx5_eswitch_disable(dev->priv.eswitch);
1438 mlx5_devlink_traps_unregister(priv_to_devlink(dev));
1439 mlx5_sf_dev_table_destroy(dev);
1440 mlx5_sriov_detach(dev);
1441 mlx5_lag_remove_mdev(dev);
1442 mlx5_ec_cleanup(dev);
1443 mlx5_sf_hw_table_destroy(dev);
1444 mlx5_vhca_event_stop(dev);
1445 mlx5_fs_core_cleanup(dev);
1446 mlx5_fpga_device_stop(dev);
1447 mlx5_rsc_dump_cleanup(dev);
1448 mlx5_hv_vhca_cleanup(dev->hv_vhca);
1449 mlx5_fw_reset_events_stop(dev);
1450 mlx5_fw_tracer_cleanup(dev->tracer);
1451 mlx5_eq_table_destroy(dev);
1452 mlx5_irq_table_destroy(dev);
1453 mlx5_pagealloc_stop(dev);
1454 mlx5_events_stop(dev);
1455 mlx5_put_uars_page(dev, dev->priv.uar);
1456 }
1457
mlx5_init_one_devl_locked(struct mlx5_core_dev * dev)1458 int mlx5_init_one_devl_locked(struct mlx5_core_dev *dev)
1459 {
1460 bool light_probe = mlx5_dev_is_lightweight(dev);
1461 int err = 0;
1462
1463 mutex_lock(&dev->intf_state_mutex);
1464 dev->state = MLX5_DEVICE_STATE_UP;
1465
1466 err = mlx5_function_setup(dev, true, mlx5_tout_ms(dev, FW_PRE_INIT_TIMEOUT));
1467 if (err)
1468 goto err_function;
1469
1470 err = mlx5_init_once(dev);
1471 if (err) {
1472 mlx5_core_err(dev, "sw objs init failed\n");
1473 goto function_teardown;
1474 }
1475
1476 /* In case of light_probe, mlx5_devlink is already registered.
1477 * Hence, don't register devlink again.
1478 */
1479 if (!light_probe) {
1480 err = mlx5_devlink_params_register(priv_to_devlink(dev));
1481 if (err)
1482 goto err_devlink_params_reg;
1483 }
1484
1485 err = mlx5_load(dev);
1486 if (err)
1487 goto err_load;
1488
1489 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1490
1491 err = mlx5_register_device(dev);
1492 if (err)
1493 goto err_register;
1494
1495 err = mlx5_crdump_enable(dev);
1496 if (err)
1497 mlx5_core_err(dev, "mlx5_crdump_enable failed with error code %d\n", err);
1498
1499 err = mlx5_hwmon_dev_register(dev);
1500 if (err)
1501 mlx5_core_err(dev, "mlx5_hwmon_dev_register failed with error code %d\n", err);
1502
1503 mutex_unlock(&dev->intf_state_mutex);
1504 return 0;
1505
1506 err_register:
1507 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1508 mlx5_unload(dev);
1509 err_load:
1510 if (!light_probe)
1511 mlx5_devlink_params_unregister(priv_to_devlink(dev));
1512 err_devlink_params_reg:
1513 mlx5_cleanup_once(dev);
1514 function_teardown:
1515 mlx5_function_teardown(dev, true);
1516 err_function:
1517 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1518 mutex_unlock(&dev->intf_state_mutex);
1519 return err;
1520 }
1521
mlx5_init_one(struct mlx5_core_dev * dev)1522 int mlx5_init_one(struct mlx5_core_dev *dev)
1523 {
1524 struct devlink *devlink = priv_to_devlink(dev);
1525 int err;
1526
1527 devl_lock(devlink);
1528 devl_register(devlink);
1529 err = mlx5_init_one_devl_locked(dev);
1530 if (err)
1531 devl_unregister(devlink);
1532 devl_unlock(devlink);
1533 return err;
1534 }
1535
mlx5_uninit_one(struct mlx5_core_dev * dev)1536 void mlx5_uninit_one(struct mlx5_core_dev *dev)
1537 {
1538 struct devlink *devlink = priv_to_devlink(dev);
1539
1540 devl_lock(devlink);
1541 mutex_lock(&dev->intf_state_mutex);
1542
1543 mlx5_hwmon_dev_unregister(dev);
1544 mlx5_crdump_disable(dev);
1545 mlx5_unregister_device(dev);
1546
1547 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1548 mlx5_core_warn(dev, "%s: interface is down, NOP\n",
1549 __func__);
1550 mlx5_devlink_params_unregister(priv_to_devlink(dev));
1551 mlx5_cleanup_once(dev);
1552 goto out;
1553 }
1554
1555 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1556 mlx5_unload(dev);
1557 mlx5_devlink_params_unregister(priv_to_devlink(dev));
1558 mlx5_cleanup_once(dev);
1559 mlx5_function_teardown(dev, true);
1560 out:
1561 mutex_unlock(&dev->intf_state_mutex);
1562 devl_unregister(devlink);
1563 devl_unlock(devlink);
1564 }
1565
mlx5_load_one_devl_locked(struct mlx5_core_dev * dev,bool recovery)1566 int mlx5_load_one_devl_locked(struct mlx5_core_dev *dev, bool recovery)
1567 {
1568 int err = 0;
1569 u64 timeout;
1570
1571 devl_assert_locked(priv_to_devlink(dev));
1572 mutex_lock(&dev->intf_state_mutex);
1573 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1574 mlx5_core_warn(dev, "interface is up, NOP\n");
1575 goto out;
1576 }
1577 /* remove any previous indication of internal error */
1578 dev->state = MLX5_DEVICE_STATE_UP;
1579
1580 if (recovery)
1581 timeout = mlx5_tout_ms(dev, FW_PRE_INIT_ON_RECOVERY_TIMEOUT);
1582 else
1583 timeout = mlx5_tout_ms(dev, FW_PRE_INIT_TIMEOUT);
1584 err = mlx5_function_setup(dev, false, timeout);
1585 if (err)
1586 goto err_function;
1587
1588 err = mlx5_load(dev);
1589 if (err)
1590 goto err_load;
1591
1592 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1593
1594 err = mlx5_attach_device(dev);
1595 if (err)
1596 goto err_attach;
1597
1598 mutex_unlock(&dev->intf_state_mutex);
1599 return 0;
1600
1601 err_attach:
1602 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1603 mlx5_unload(dev);
1604 err_load:
1605 mlx5_function_teardown(dev, false);
1606 err_function:
1607 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1608 out:
1609 mutex_unlock(&dev->intf_state_mutex);
1610 return err;
1611 }
1612
mlx5_load_one(struct mlx5_core_dev * dev,bool recovery)1613 int mlx5_load_one(struct mlx5_core_dev *dev, bool recovery)
1614 {
1615 struct devlink *devlink = priv_to_devlink(dev);
1616 int ret;
1617
1618 devl_lock(devlink);
1619 ret = mlx5_load_one_devl_locked(dev, recovery);
1620 devl_unlock(devlink);
1621 return ret;
1622 }
1623
mlx5_unload_one_devl_locked(struct mlx5_core_dev * dev,bool suspend)1624 void mlx5_unload_one_devl_locked(struct mlx5_core_dev *dev, bool suspend)
1625 {
1626 devl_assert_locked(priv_to_devlink(dev));
1627 mutex_lock(&dev->intf_state_mutex);
1628
1629 mlx5_detach_device(dev, suspend);
1630
1631 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1632 mlx5_core_warn(dev, "%s: interface is down, NOP\n",
1633 __func__);
1634 goto out;
1635 }
1636
1637 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1638 mlx5_unload(dev);
1639 mlx5_function_teardown(dev, false);
1640 out:
1641 mutex_unlock(&dev->intf_state_mutex);
1642 }
1643
mlx5_unload_one(struct mlx5_core_dev * dev,bool suspend)1644 void mlx5_unload_one(struct mlx5_core_dev *dev, bool suspend)
1645 {
1646 struct devlink *devlink = priv_to_devlink(dev);
1647
1648 devl_lock(devlink);
1649 mlx5_unload_one_devl_locked(dev, suspend);
1650 devl_unlock(devlink);
1651 }
1652
1653 /* In case of light probe, we don't need a full query of hca_caps, but only the bellow caps.
1654 * A full query of hca_caps will be done when the device will reload.
1655 */
mlx5_query_hca_caps_light(struct mlx5_core_dev * dev)1656 static int mlx5_query_hca_caps_light(struct mlx5_core_dev *dev)
1657 {
1658 int err;
1659
1660 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL);
1661 if (err)
1662 return err;
1663
1664 if (MLX5_CAP_GEN(dev, eth_net_offloads)) {
1665 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_ETHERNET_OFFLOADS,
1666 HCA_CAP_OPMOD_GET_CUR);
1667 if (err)
1668 return err;
1669 }
1670
1671 if (MLX5_CAP_GEN(dev, nic_flow_table) ||
1672 MLX5_CAP_GEN(dev, ipoib_enhanced_offloads)) {
1673 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_FLOW_TABLE,
1674 HCA_CAP_OPMOD_GET_CUR);
1675 if (err)
1676 return err;
1677 }
1678
1679 if (MLX5_CAP_GEN_64(dev, general_obj_types) &
1680 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q) {
1681 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_VDPA_EMULATION,
1682 HCA_CAP_OPMOD_GET_CUR);
1683 if (err)
1684 return err;
1685 }
1686
1687 return 0;
1688 }
1689
mlx5_init_one_light(struct mlx5_core_dev * dev)1690 int mlx5_init_one_light(struct mlx5_core_dev *dev)
1691 {
1692 struct devlink *devlink = priv_to_devlink(dev);
1693 int err;
1694
1695 devl_lock(devlink);
1696 devl_register(devlink);
1697 dev->state = MLX5_DEVICE_STATE_UP;
1698 err = mlx5_function_enable(dev, true, mlx5_tout_ms(dev, FW_PRE_INIT_TIMEOUT));
1699 if (err) {
1700 mlx5_core_warn(dev, "mlx5_function_enable err=%d\n", err);
1701 goto out;
1702 }
1703
1704 err = mlx5_query_hca_caps_light(dev);
1705 if (err) {
1706 mlx5_core_warn(dev, "mlx5_query_hca_caps_light err=%d\n", err);
1707 goto query_hca_caps_err;
1708 }
1709
1710 err = mlx5_devlink_params_register(priv_to_devlink(dev));
1711 if (err) {
1712 mlx5_core_warn(dev, "mlx5_devlink_param_reg err = %d\n", err);
1713 goto query_hca_caps_err;
1714 }
1715
1716 devl_unlock(devlink);
1717 return 0;
1718
1719 query_hca_caps_err:
1720 mlx5_function_disable(dev, true);
1721 out:
1722 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1723 devl_unregister(devlink);
1724 devl_unlock(devlink);
1725 return err;
1726 }
1727
mlx5_uninit_one_light(struct mlx5_core_dev * dev)1728 void mlx5_uninit_one_light(struct mlx5_core_dev *dev)
1729 {
1730 struct devlink *devlink = priv_to_devlink(dev);
1731
1732 devl_lock(devlink);
1733 mlx5_devlink_params_unregister(priv_to_devlink(dev));
1734 devl_unregister(devlink);
1735 devl_unlock(devlink);
1736 if (dev->state != MLX5_DEVICE_STATE_UP)
1737 return;
1738 mlx5_function_disable(dev, true);
1739 }
1740
1741 /* xxx_light() function are used in order to configure the device without full
1742 * init (light init). e.g.: There isn't a point in reload a device to light state.
1743 * Hence, mlx5_load_one_light() isn't needed.
1744 */
1745
mlx5_unload_one_light(struct mlx5_core_dev * dev)1746 void mlx5_unload_one_light(struct mlx5_core_dev *dev)
1747 {
1748 if (dev->state != MLX5_DEVICE_STATE_UP)
1749 return;
1750 mlx5_function_disable(dev, false);
1751 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1752 }
1753
1754 static const int types[] = {
1755 MLX5_CAP_GENERAL,
1756 MLX5_CAP_GENERAL_2,
1757 MLX5_CAP_ETHERNET_OFFLOADS,
1758 MLX5_CAP_IPOIB_ENHANCED_OFFLOADS,
1759 MLX5_CAP_ODP,
1760 MLX5_CAP_ATOMIC,
1761 MLX5_CAP_ROCE,
1762 MLX5_CAP_IPOIB_OFFLOADS,
1763 MLX5_CAP_FLOW_TABLE,
1764 MLX5_CAP_ESWITCH_FLOW_TABLE,
1765 MLX5_CAP_ESWITCH,
1766 MLX5_CAP_QOS,
1767 MLX5_CAP_DEBUG,
1768 MLX5_CAP_DEV_MEM,
1769 MLX5_CAP_DEV_EVENT,
1770 MLX5_CAP_TLS,
1771 MLX5_CAP_VDPA_EMULATION,
1772 MLX5_CAP_IPSEC,
1773 MLX5_CAP_PORT_SELECTION,
1774 MLX5_CAP_MACSEC,
1775 MLX5_CAP_ADV_VIRTUALIZATION,
1776 MLX5_CAP_CRYPTO,
1777 };
1778
mlx5_hca_caps_free(struct mlx5_core_dev * dev)1779 static void mlx5_hca_caps_free(struct mlx5_core_dev *dev)
1780 {
1781 int type;
1782 int i;
1783
1784 for (i = 0; i < ARRAY_SIZE(types); i++) {
1785 type = types[i];
1786 kfree(dev->caps.hca[type]);
1787 }
1788 }
1789
mlx5_hca_caps_alloc(struct mlx5_core_dev * dev)1790 static int mlx5_hca_caps_alloc(struct mlx5_core_dev *dev)
1791 {
1792 struct mlx5_hca_cap *cap;
1793 int type;
1794 int i;
1795
1796 for (i = 0; i < ARRAY_SIZE(types); i++) {
1797 cap = kzalloc(sizeof(*cap), GFP_KERNEL);
1798 if (!cap)
1799 goto err;
1800 type = types[i];
1801 dev->caps.hca[type] = cap;
1802 }
1803
1804 return 0;
1805
1806 err:
1807 mlx5_hca_caps_free(dev);
1808 return -ENOMEM;
1809 }
1810
vhca_id_show(struct seq_file * file,void * priv)1811 static int vhca_id_show(struct seq_file *file, void *priv)
1812 {
1813 struct mlx5_core_dev *dev = file->private;
1814
1815 seq_printf(file, "0x%x\n", MLX5_CAP_GEN(dev, vhca_id));
1816 return 0;
1817 }
1818
1819 DEFINE_SHOW_ATTRIBUTE(vhca_id);
1820
mlx5_mdev_init(struct mlx5_core_dev * dev,int profile_idx)1821 int mlx5_mdev_init(struct mlx5_core_dev *dev, int profile_idx)
1822 {
1823 struct mlx5_priv *priv = &dev->priv;
1824 int err;
1825
1826 memcpy(&dev->profile, &profile[profile_idx], sizeof(dev->profile));
1827 lockdep_register_key(&dev->lock_key);
1828 mutex_init(&dev->intf_state_mutex);
1829 lockdep_set_class(&dev->intf_state_mutex, &dev->lock_key);
1830 mutex_init(&dev->mlx5e_res.uplink_netdev_lock);
1831 mutex_init(&dev->wc_state_lock);
1832
1833 mutex_init(&priv->bfregs.reg_head.lock);
1834 mutex_init(&priv->bfregs.wc_head.lock);
1835 INIT_LIST_HEAD(&priv->bfregs.reg_head.list);
1836 INIT_LIST_HEAD(&priv->bfregs.wc_head.list);
1837
1838 mutex_init(&priv->alloc_mutex);
1839 mutex_init(&priv->pgdir_mutex);
1840 INIT_LIST_HEAD(&priv->pgdir_list);
1841
1842 priv->numa_node = dev_to_node(mlx5_core_dma_dev(dev));
1843 priv->dbg.dbg_root = debugfs_create_dir(dev_name(dev->device),
1844 mlx5_debugfs_root);
1845 debugfs_create_file("vhca_id", 0400, priv->dbg.dbg_root, dev, &vhca_id_fops);
1846 INIT_LIST_HEAD(&priv->traps);
1847
1848 err = mlx5_cmd_init(dev);
1849 if (err) {
1850 mlx5_core_err(dev, "Failed initializing cmdif SW structs, aborting\n");
1851 goto err_cmd_init;
1852 }
1853
1854 err = mlx5_tout_init(dev);
1855 if (err) {
1856 mlx5_core_err(dev, "Failed initializing timeouts, aborting\n");
1857 goto err_timeout_init;
1858 }
1859
1860 err = mlx5_health_init(dev);
1861 if (err)
1862 goto err_health_init;
1863
1864 err = mlx5_pagealloc_init(dev);
1865 if (err)
1866 goto err_pagealloc_init;
1867
1868 err = mlx5_adev_init(dev);
1869 if (err)
1870 goto err_adev_init;
1871
1872 err = mlx5_hca_caps_alloc(dev);
1873 if (err)
1874 goto err_hca_caps;
1875
1876 /* The conjunction of sw_vhca_id with sw_owner_id will be a global
1877 * unique id per function which uses mlx5_core.
1878 * Those values are supplied to FW as part of the init HCA command to
1879 * be used by both driver and FW when it's applicable.
1880 */
1881 dev->priv.sw_vhca_id = ida_alloc_range(&sw_vhca_ida, 1,
1882 MAX_SW_VHCA_ID,
1883 GFP_KERNEL);
1884 if (dev->priv.sw_vhca_id < 0)
1885 mlx5_core_err(dev, "failed to allocate sw_vhca_id, err=%d\n",
1886 dev->priv.sw_vhca_id);
1887
1888 return 0;
1889
1890 err_hca_caps:
1891 mlx5_adev_cleanup(dev);
1892 err_adev_init:
1893 mlx5_pagealloc_cleanup(dev);
1894 err_pagealloc_init:
1895 mlx5_health_cleanup(dev);
1896 err_health_init:
1897 mlx5_tout_cleanup(dev);
1898 err_timeout_init:
1899 mlx5_cmd_cleanup(dev);
1900 err_cmd_init:
1901 debugfs_remove(dev->priv.dbg.dbg_root);
1902 mutex_destroy(&priv->pgdir_mutex);
1903 mutex_destroy(&priv->alloc_mutex);
1904 mutex_destroy(&priv->bfregs.wc_head.lock);
1905 mutex_destroy(&priv->bfregs.reg_head.lock);
1906 mutex_destroy(&dev->intf_state_mutex);
1907 lockdep_unregister_key(&dev->lock_key);
1908 return err;
1909 }
1910
mlx5_mdev_uninit(struct mlx5_core_dev * dev)1911 void mlx5_mdev_uninit(struct mlx5_core_dev *dev)
1912 {
1913 struct mlx5_priv *priv = &dev->priv;
1914
1915 if (priv->sw_vhca_id > 0)
1916 ida_free(&sw_vhca_ida, dev->priv.sw_vhca_id);
1917
1918 mlx5_hca_caps_free(dev);
1919 mlx5_adev_cleanup(dev);
1920 mlx5_pagealloc_cleanup(dev);
1921 mlx5_health_cleanup(dev);
1922 mlx5_tout_cleanup(dev);
1923 mlx5_cmd_cleanup(dev);
1924 debugfs_remove_recursive(dev->priv.dbg.dbg_root);
1925 mutex_destroy(&priv->pgdir_mutex);
1926 mutex_destroy(&priv->alloc_mutex);
1927 mutex_destroy(&priv->bfregs.wc_head.lock);
1928 mutex_destroy(&priv->bfregs.reg_head.lock);
1929 mutex_destroy(&dev->wc_state_lock);
1930 mutex_destroy(&dev->mlx5e_res.uplink_netdev_lock);
1931 mutex_destroy(&dev->intf_state_mutex);
1932 lockdep_unregister_key(&dev->lock_key);
1933 }
1934
probe_one(struct pci_dev * pdev,const struct pci_device_id * id)1935 static int probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1936 {
1937 struct mlx5_core_dev *dev;
1938 struct devlink *devlink;
1939 int err;
1940
1941 devlink = mlx5_devlink_alloc(&pdev->dev);
1942 if (!devlink) {
1943 dev_err(&pdev->dev, "devlink alloc failed\n");
1944 return -ENOMEM;
1945 }
1946
1947 dev = devlink_priv(devlink);
1948 dev->device = &pdev->dev;
1949 dev->pdev = pdev;
1950
1951 dev->coredev_type = id->driver_data & MLX5_PCI_DEV_IS_VF ?
1952 MLX5_COREDEV_VF : MLX5_COREDEV_PF;
1953
1954 dev->priv.adev_idx = mlx5_adev_idx_alloc();
1955 if (dev->priv.adev_idx < 0) {
1956 err = dev->priv.adev_idx;
1957 goto adev_init_err;
1958 }
1959
1960 err = mlx5_mdev_init(dev, prof_sel);
1961 if (err)
1962 goto mdev_init_err;
1963
1964 err = mlx5_pci_init(dev, pdev, id);
1965 if (err) {
1966 mlx5_core_err(dev, "mlx5_pci_init failed with error code %d\n",
1967 err);
1968 goto pci_init_err;
1969 }
1970
1971 err = mlx5_init_one(dev);
1972 if (err) {
1973 mlx5_core_err(dev, "mlx5_init_one failed with error code %d\n",
1974 err);
1975 goto err_init_one;
1976 }
1977
1978 pci_save_state(pdev);
1979 return 0;
1980
1981 err_init_one:
1982 mlx5_pci_close(dev);
1983 pci_init_err:
1984 mlx5_mdev_uninit(dev);
1985 mdev_init_err:
1986 mlx5_adev_idx_free(dev->priv.adev_idx);
1987 adev_init_err:
1988 mlx5_devlink_free(devlink);
1989
1990 return err;
1991 }
1992
remove_one(struct pci_dev * pdev)1993 static void remove_one(struct pci_dev *pdev)
1994 {
1995 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1996 struct devlink *devlink = priv_to_devlink(dev);
1997
1998 set_bit(MLX5_BREAK_FW_WAIT, &dev->intf_state);
1999 mlx5_drain_fw_reset(dev);
2000 mlx5_drain_health_wq(dev);
2001 mlx5_sriov_disable(pdev, false);
2002 mlx5_uninit_one(dev);
2003 mlx5_pci_close(dev);
2004 mlx5_mdev_uninit(dev);
2005 mlx5_adev_idx_free(dev->priv.adev_idx);
2006 mlx5_devlink_free(devlink);
2007 }
2008
2009 #define mlx5_pci_trace(dev, fmt, ...) ({ \
2010 struct mlx5_core_dev *__dev = (dev); \
2011 mlx5_core_info(__dev, "%s Device state = %d health sensors: %d pci_status: %d. " fmt, \
2012 __func__, __dev->state, mlx5_health_check_fatal_sensors(__dev), \
2013 __dev->pci_status, ##__VA_ARGS__); \
2014 })
2015
result2str(enum pci_ers_result result)2016 static const char *result2str(enum pci_ers_result result)
2017 {
2018 return result == PCI_ERS_RESULT_NEED_RESET ? "need reset" :
2019 result == PCI_ERS_RESULT_DISCONNECT ? "disconnect" :
2020 result == PCI_ERS_RESULT_RECOVERED ? "recovered" :
2021 "unknown";
2022 }
2023
mlx5_pci_err_detected(struct pci_dev * pdev,pci_channel_state_t state)2024 static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev,
2025 pci_channel_state_t state)
2026 {
2027 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
2028 enum pci_ers_result res;
2029
2030 mlx5_pci_trace(dev, "Enter, pci channel state = %d\n", state);
2031
2032 mlx5_enter_error_state(dev, false);
2033 mlx5_error_sw_reset(dev);
2034 mlx5_unload_one(dev, false);
2035 mlx5_drain_health_wq(dev);
2036 mlx5_pci_disable_device(dev);
2037
2038 res = state == pci_channel_io_perm_failure ?
2039 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
2040
2041 mlx5_core_info(dev, "%s Device state = %d pci_status: %d. Exit, result = %d, %s\n",
2042 __func__, dev->state, dev->pci_status, res, result2str(res));
2043 return res;
2044 }
2045
2046 /* wait for the device to show vital signs by waiting
2047 * for the health counter to start counting.
2048 */
wait_vital(struct pci_dev * pdev)2049 static int wait_vital(struct pci_dev *pdev)
2050 {
2051 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
2052 struct mlx5_core_health *health = &dev->priv.health;
2053 const int niter = 100;
2054 u32 last_count = 0;
2055 u32 count;
2056 int i;
2057
2058 for (i = 0; i < niter; i++) {
2059 count = ioread32be(health->health_counter);
2060 if (count && count != 0xffffffff) {
2061 if (last_count && last_count != count) {
2062 mlx5_core_info(dev,
2063 "wait vital counter value 0x%x after %d iterations\n",
2064 count, i);
2065 return 0;
2066 }
2067 last_count = count;
2068 }
2069 msleep(50);
2070 }
2071
2072 return -ETIMEDOUT;
2073 }
2074
mlx5_pci_slot_reset(struct pci_dev * pdev)2075 static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev)
2076 {
2077 enum pci_ers_result res = PCI_ERS_RESULT_DISCONNECT;
2078 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
2079 int err;
2080
2081 mlx5_core_info(dev, "%s Device state = %d pci_status: %d. Enter\n",
2082 __func__, dev->state, dev->pci_status);
2083
2084 err = mlx5_pci_enable_device(dev);
2085 if (err) {
2086 mlx5_core_err(dev, "%s: mlx5_pci_enable_device failed with error code: %d\n",
2087 __func__, err);
2088 goto out;
2089 }
2090
2091 pci_set_master(pdev);
2092 pci_restore_state(pdev);
2093 pci_save_state(pdev);
2094
2095 err = wait_vital(pdev);
2096 if (err) {
2097 mlx5_core_err(dev, "%s: wait vital failed with error code: %d\n",
2098 __func__, err);
2099 goto out;
2100 }
2101
2102 res = PCI_ERS_RESULT_RECOVERED;
2103 out:
2104 mlx5_core_info(dev, "%s Device state = %d pci_status: %d. Exit, err = %d, result = %d, %s\n",
2105 __func__, dev->state, dev->pci_status, err, res, result2str(res));
2106 return res;
2107 }
2108
mlx5_pci_resume(struct pci_dev * pdev)2109 static void mlx5_pci_resume(struct pci_dev *pdev)
2110 {
2111 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
2112 int err;
2113
2114 mlx5_pci_trace(dev, "Enter, loading driver..\n");
2115
2116 err = mlx5_load_one(dev, false);
2117
2118 if (!err)
2119 devlink_health_reporter_state_update(dev->priv.health.fw_fatal_reporter,
2120 DEVLINK_HEALTH_REPORTER_STATE_HEALTHY);
2121
2122 mlx5_pci_trace(dev, "Done, err = %d, device %s\n", err,
2123 !err ? "recovered" : "Failed");
2124 }
2125
2126 static const struct pci_error_handlers mlx5_err_handler = {
2127 .error_detected = mlx5_pci_err_detected,
2128 .slot_reset = mlx5_pci_slot_reset,
2129 .resume = mlx5_pci_resume
2130 };
2131
mlx5_try_fast_unload(struct mlx5_core_dev * dev)2132 static int mlx5_try_fast_unload(struct mlx5_core_dev *dev)
2133 {
2134 bool fast_teardown = false, force_teardown = false;
2135 int ret = 1;
2136
2137 fast_teardown = MLX5_CAP_GEN(dev, fast_teardown);
2138 force_teardown = MLX5_CAP_GEN(dev, force_teardown);
2139
2140 mlx5_core_dbg(dev, "force teardown firmware support=%d\n", force_teardown);
2141 mlx5_core_dbg(dev, "fast teardown firmware support=%d\n", fast_teardown);
2142
2143 if (!fast_teardown && !force_teardown)
2144 return -EOPNOTSUPP;
2145
2146 if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
2147 mlx5_core_dbg(dev, "Device in internal error state, giving up\n");
2148 return -EAGAIN;
2149 }
2150
2151 /* Panic tear down fw command will stop the PCI bus communication
2152 * with the HCA, so the health poll is no longer needed.
2153 */
2154 mlx5_stop_health_poll(dev, false);
2155
2156 ret = mlx5_cmd_fast_teardown_hca(dev);
2157 if (!ret)
2158 goto succeed;
2159
2160 ret = mlx5_cmd_force_teardown_hca(dev);
2161 if (!ret)
2162 goto succeed;
2163
2164 mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", ret);
2165 mlx5_start_health_poll(dev);
2166 return ret;
2167
2168 succeed:
2169 mlx5_enter_error_state(dev, true);
2170
2171 /* Some platforms requiring freeing the IRQ's in the shutdown
2172 * flow. If they aren't freed they can't be allocated after
2173 * kexec. There is no need to cleanup the mlx5_core software
2174 * contexts.
2175 */
2176 mlx5_core_eq_free_irqs(dev);
2177
2178 return 0;
2179 }
2180
shutdown(struct pci_dev * pdev)2181 static void shutdown(struct pci_dev *pdev)
2182 {
2183 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
2184 int err;
2185
2186 mlx5_core_info(dev, "Shutdown was called\n");
2187 set_bit(MLX5_BREAK_FW_WAIT, &dev->intf_state);
2188 mlx5_drain_health_wq(dev);
2189 err = mlx5_try_fast_unload(dev);
2190 if (err)
2191 mlx5_unload_one(dev, false);
2192 mlx5_pci_disable_device(dev);
2193 }
2194
mlx5_suspend(struct pci_dev * pdev,pm_message_t state)2195 static int mlx5_suspend(struct pci_dev *pdev, pm_message_t state)
2196 {
2197 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
2198
2199 mlx5_unload_one(dev, true);
2200
2201 return 0;
2202 }
2203
mlx5_resume(struct pci_dev * pdev)2204 static int mlx5_resume(struct pci_dev *pdev)
2205 {
2206 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
2207
2208 return mlx5_load_one(dev, false);
2209 }
2210
2211 static const struct pci_device_id mlx5_core_pci_table[] = {
2212 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTIB) },
2213 { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */
2214 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4) },
2215 { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */
2216 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) },
2217 { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */
2218 { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */
2219 { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */
2220 { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5 Ex */
2221 { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 Ex VF */
2222 { PCI_VDEVICE(MELLANOX, 0x101b) }, /* ConnectX-6 */
2223 { PCI_VDEVICE(MELLANOX, 0x101c), MLX5_PCI_DEV_IS_VF}, /* ConnectX-6 VF */
2224 { PCI_VDEVICE(MELLANOX, 0x101d) }, /* ConnectX-6 Dx */
2225 { PCI_VDEVICE(MELLANOX, 0x101e), MLX5_PCI_DEV_IS_VF}, /* ConnectX Family mlx5Gen Virtual Function */
2226 { PCI_VDEVICE(MELLANOX, 0x101f) }, /* ConnectX-6 LX */
2227 { PCI_VDEVICE(MELLANOX, 0x1021) }, /* ConnectX-7 */
2228 { PCI_VDEVICE(MELLANOX, 0x1023) }, /* ConnectX-8 */
2229 { PCI_VDEVICE(MELLANOX, 0x1025) }, /* ConnectX-9 */
2230 { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */
2231 { PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF}, /* BlueField integrated ConnectX-5 network controller VF */
2232 { PCI_VDEVICE(MELLANOX, 0xa2d6) }, /* BlueField-2 integrated ConnectX-6 Dx network controller */
2233 { PCI_VDEVICE(MELLANOX, 0xa2dc) }, /* BlueField-3 integrated ConnectX-7 network controller */
2234 { PCI_VDEVICE(MELLANOX, 0xa2df) }, /* BlueField-4 integrated ConnectX-8 network controller */
2235 { 0, }
2236 };
2237
2238 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
2239
mlx5_disable_device(struct mlx5_core_dev * dev)2240 void mlx5_disable_device(struct mlx5_core_dev *dev)
2241 {
2242 mlx5_error_sw_reset(dev);
2243 mlx5_unload_one_devl_locked(dev, false);
2244 }
2245
mlx5_recover_device(struct mlx5_core_dev * dev)2246 int mlx5_recover_device(struct mlx5_core_dev *dev)
2247 {
2248 if (!mlx5_core_is_sf(dev)) {
2249 mlx5_pci_disable_device(dev);
2250 if (mlx5_pci_slot_reset(dev->pdev) != PCI_ERS_RESULT_RECOVERED)
2251 return -EIO;
2252 }
2253
2254 return mlx5_load_one_devl_locked(dev, true);
2255 }
2256
2257 static struct pci_driver mlx5_core_driver = {
2258 .name = KBUILD_MODNAME,
2259 .id_table = mlx5_core_pci_table,
2260 .probe = probe_one,
2261 .remove = remove_one,
2262 .suspend = mlx5_suspend,
2263 .resume = mlx5_resume,
2264 .shutdown = shutdown,
2265 .err_handler = &mlx5_err_handler,
2266 .sriov_configure = mlx5_core_sriov_configure,
2267 .sriov_get_vf_total_msix = mlx5_sriov_get_vf_total_msix,
2268 .sriov_set_msix_vec_count = mlx5_core_sriov_set_msix_vec_count,
2269 };
2270
2271 /**
2272 * mlx5_vf_get_core_dev - Get the mlx5 core device from a given VF PCI device if
2273 * mlx5_core is its driver.
2274 * @pdev: The associated PCI device.
2275 *
2276 * Upon return the interface state lock stay held to let caller uses it safely.
2277 * Caller must ensure to use the returned mlx5 device for a narrow window
2278 * and put it back with mlx5_vf_put_core_dev() immediately once usage was over.
2279 *
2280 * Return: Pointer to the associated mlx5_core_dev or NULL.
2281 */
mlx5_vf_get_core_dev(struct pci_dev * pdev)2282 struct mlx5_core_dev *mlx5_vf_get_core_dev(struct pci_dev *pdev)
2283 {
2284 struct mlx5_core_dev *mdev;
2285
2286 mdev = pci_iov_get_pf_drvdata(pdev, &mlx5_core_driver);
2287 if (IS_ERR(mdev))
2288 return NULL;
2289
2290 mutex_lock(&mdev->intf_state_mutex);
2291 if (!test_bit(MLX5_INTERFACE_STATE_UP, &mdev->intf_state)) {
2292 mutex_unlock(&mdev->intf_state_mutex);
2293 return NULL;
2294 }
2295
2296 return mdev;
2297 }
2298 EXPORT_SYMBOL(mlx5_vf_get_core_dev);
2299
2300 /**
2301 * mlx5_vf_put_core_dev - Put the mlx5 core device back.
2302 * @mdev: The mlx5 core device.
2303 *
2304 * Upon return the interface state lock is unlocked and caller should not
2305 * access the mdev any more.
2306 */
mlx5_vf_put_core_dev(struct mlx5_core_dev * mdev)2307 void mlx5_vf_put_core_dev(struct mlx5_core_dev *mdev)
2308 {
2309 mutex_unlock(&mdev->intf_state_mutex);
2310 }
2311 EXPORT_SYMBOL(mlx5_vf_put_core_dev);
2312
mlx5_core_verify_params(void)2313 static void mlx5_core_verify_params(void)
2314 {
2315 if (prof_sel >= ARRAY_SIZE(profile)) {
2316 pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n",
2317 prof_sel,
2318 ARRAY_SIZE(profile) - 1,
2319 MLX5_DEFAULT_PROF);
2320 prof_sel = MLX5_DEFAULT_PROF;
2321 }
2322 }
2323
mlx5_init(void)2324 static int __init mlx5_init(void)
2325 {
2326 int err;
2327
2328 WARN_ONCE(strcmp(MLX5_ADEV_NAME, KBUILD_MODNAME),
2329 "mlx5_core name not in sync with kernel module name");
2330
2331 get_random_bytes(&sw_owner_id, sizeof(sw_owner_id));
2332
2333 mlx5_core_verify_params();
2334 mlx5_register_debugfs();
2335
2336 err = mlx5e_init();
2337 if (err)
2338 goto err_debug;
2339
2340 err = mlx5_sf_driver_register();
2341 if (err)
2342 goto err_sf;
2343
2344 err = pci_register_driver(&mlx5_core_driver);
2345 if (err)
2346 goto err_pci;
2347
2348 return 0;
2349
2350 err_pci:
2351 mlx5_sf_driver_unregister();
2352 err_sf:
2353 mlx5e_cleanup();
2354 err_debug:
2355 mlx5_unregister_debugfs();
2356 return err;
2357 }
2358
mlx5_cleanup(void)2359 static void __exit mlx5_cleanup(void)
2360 {
2361 pci_unregister_driver(&mlx5_core_driver);
2362 mlx5_sf_driver_unregister();
2363 mlx5e_cleanup();
2364 mlx5_unregister_debugfs();
2365 }
2366
2367 module_init(mlx5_init);
2368 module_exit(mlx5_cleanup);
2369