xref: /linux/drivers/net/ethernet/sgi/meth.c (revision 0ea5c948cb64bab5bc7a5516774eb8536f05aa0d)
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * meth.c -- O2 Builtin 10/100 Ethernet driver
4  *
5  * Copyright (C) 2001-2003 Ilya Volynets
6  */
7 #include <linux/delay.h>
8 #include <linux/dma-mapping.h>
9 #include <linux/kernel.h>
10 #include <linux/module.h>
11 #include <linux/platform_device.h>
12 #include <linux/slab.h>
13 #include <linux/errno.h>
14 #include <linux/types.h>
15 #include <linux/interrupt.h>
16 
17 #include <linux/in.h>
18 #include <linux/in6.h>
19 #include <linux/device.h> /* struct device, et al */
20 #include <linux/netdevice.h>   /* struct device, and other headers */
21 #include <linux/etherdevice.h> /* eth_type_trans */
22 #include <linux/ip.h>          /* struct iphdr */
23 #include <linux/tcp.h>         /* struct tcphdr */
24 #include <linux/skbuff.h>
25 #include <linux/mii.h>         /* MII definitions */
26 #include <linux/crc32.h>
27 
28 #include <asm/ip32/mace.h>
29 #include <asm/ip32/ip32_ints.h>
30 
31 #include <asm/io.h>
32 
33 #include "meth.h"
34 
35 #ifndef MFE_DEBUG
36 #define MFE_DEBUG 0
37 #endif
38 
39 #if MFE_DEBUG>=1
40 #define DPRINTK(str,args...) printk(KERN_DEBUG "meth: %s: " str, __func__ , ## args)
41 #define MFE_RX_DEBUG 2
42 #else
43 #define DPRINTK(str,args...)
44 #define MFE_RX_DEBUG 0
45 #endif
46 
47 
48 static const char *meth_str="SGI O2 Fast Ethernet";
49 
50 /* The maximum time waited (in jiffies) before assuming a Tx failed. (400ms) */
51 #define TX_TIMEOUT (400*HZ/1000)
52 
53 static int timeout = TX_TIMEOUT;
54 module_param(timeout, int, 0);
55 
56 /*
57  * Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
58  * MACE Ethernet uses a 64 element hash table based on the Ethernet CRC.
59  */
60 #define METH_MCF_LIMIT 32
61 
62 /*
63  * This structure is private to each device. It is used to pass
64  * packets in and out, so there is place for a packet
65  */
66 struct meth_private {
67 	struct platform_device *pdev;
68 
69 	/* in-memory copy of MAC Control register */
70 	u64 mac_ctrl;
71 
72 	/* in-memory copy of DMA Control register */
73 	unsigned long dma_ctrl;
74 	/* address of PHY, used by mdio_* functions, initialized in mdio_probe */
75 	unsigned long phy_addr;
76 	tx_packet *tx_ring;
77 	dma_addr_t tx_ring_dma;
78 	struct sk_buff *tx_skbs[TX_RING_ENTRIES];
79 	dma_addr_t tx_skb_dmas[TX_RING_ENTRIES];
80 	unsigned long tx_read, tx_write, tx_count;
81 
82 	rx_packet *rx_ring[RX_RING_ENTRIES];
83 	dma_addr_t rx_ring_dmas[RX_RING_ENTRIES];
84 	struct sk_buff *rx_skbs[RX_RING_ENTRIES];
85 	unsigned long rx_write;
86 
87 	/* Multicast filter. */
88 	u64 mcast_filter;
89 
90 	spinlock_t meth_lock;
91 };
92 
93 static void meth_tx_timeout(struct net_device *dev, unsigned int txqueue);
94 static irqreturn_t meth_interrupt(int irq, void *dev_id);
95 
96 /* global, initialized in ip32-setup.c */
97 char o2meth_eaddr[8]={0,0,0,0,0,0,0,0};
98 
load_eaddr(struct net_device * dev)99 static inline void load_eaddr(struct net_device *dev)
100 {
101 	int i;
102 	u64 macaddr;
103 
104 	DPRINTK("Loading MAC Address: %pM\n", dev->dev_addr);
105 	macaddr = 0;
106 	for (i = 0; i < 6; i++)
107 		macaddr |= (u64)dev->dev_addr[i] << ((5 - i) * 8);
108 
109 	mace->eth.mac_addr = macaddr;
110 }
111 
112 /*
113  * Waits for BUSY status of mdio bus to clear
114  */
115 #define WAIT_FOR_PHY(___rval)					\
116 	while ((___rval = mace->eth.phy_data) & MDIO_BUSY) {	\
117 		udelay(25);					\
118 	}
119 /*read phy register, return value read */
mdio_read(struct meth_private * priv,unsigned long phyreg)120 static unsigned long mdio_read(struct meth_private *priv, unsigned long phyreg)
121 {
122 	unsigned long rval;
123 	WAIT_FOR_PHY(rval);
124 	mace->eth.phy_regs = (priv->phy_addr << 5) | (phyreg & 0x1f);
125 	udelay(25);
126 	mace->eth.phy_trans_go = 1;
127 	udelay(25);
128 	WAIT_FOR_PHY(rval);
129 	return rval & MDIO_DATA_MASK;
130 }
131 
mdio_probe(struct meth_private * priv)132 static int mdio_probe(struct meth_private *priv)
133 {
134 	int i;
135 	unsigned long p2, p3, flags;
136 	/* check if phy is detected already */
137 	if(priv->phy_addr>=0&&priv->phy_addr<32)
138 		return 0;
139 	spin_lock_irqsave(&priv->meth_lock, flags);
140 	for (i=0;i<32;++i){
141 		priv->phy_addr=i;
142 		p2=mdio_read(priv,2);
143 		p3=mdio_read(priv,3);
144 #if MFE_DEBUG>=2
145 		switch ((p2<<12)|(p3>>4)){
146 		case PHY_QS6612X:
147 			DPRINTK("PHY is QS6612X\n");
148 			break;
149 		case PHY_ICS1889:
150 			DPRINTK("PHY is ICS1889\n");
151 			break;
152 		case PHY_ICS1890:
153 			DPRINTK("PHY is ICS1890\n");
154 			break;
155 		case PHY_DP83840:
156 			DPRINTK("PHY is DP83840\n");
157 			break;
158 		}
159 #endif
160 		if(p2!=0xffff&&p2!=0x0000){
161 			DPRINTK("PHY code: %x\n",(p2<<12)|(p3>>4));
162 			break;
163 		}
164 	}
165 	spin_unlock_irqrestore(&priv->meth_lock, flags);
166 	if(priv->phy_addr<32) {
167 		return 0;
168 	}
169 	DPRINTK("Oopsie! PHY is not known!\n");
170 	priv->phy_addr=-1;
171 	return -ENODEV;
172 }
173 
meth_check_link(struct net_device * dev)174 static void meth_check_link(struct net_device *dev)
175 {
176 	struct meth_private *priv = netdev_priv(dev);
177 	unsigned long mii_advertising = mdio_read(priv, 4);
178 	unsigned long mii_partner = mdio_read(priv, 5);
179 	unsigned long negotiated = mii_advertising & mii_partner;
180 	unsigned long duplex, speed;
181 
182 	if (mii_partner == 0xffff)
183 		return;
184 
185 	speed = (negotiated & 0x0380) ? METH_100MBIT : 0;
186 	duplex = ((negotiated & 0x0100) || (negotiated & 0x01C0) == 0x0040) ?
187 		 METH_PHY_FDX : 0;
188 
189 	if ((priv->mac_ctrl & METH_PHY_FDX) ^ duplex) {
190 		DPRINTK("Setting %s-duplex\n", duplex ? "full" : "half");
191 		if (duplex)
192 			priv->mac_ctrl |= METH_PHY_FDX;
193 		else
194 			priv->mac_ctrl &= ~METH_PHY_FDX;
195 		mace->eth.mac_ctrl = priv->mac_ctrl;
196 	}
197 
198 	if ((priv->mac_ctrl & METH_100MBIT) ^ speed) {
199 		DPRINTK("Setting %dMbs mode\n", speed ? 100 : 10);
200 		if (duplex)
201 			priv->mac_ctrl |= METH_100MBIT;
202 		else
203 			priv->mac_ctrl &= ~METH_100MBIT;
204 		mace->eth.mac_ctrl = priv->mac_ctrl;
205 	}
206 }
207 
208 
meth_init_tx_ring(struct meth_private * priv)209 static int meth_init_tx_ring(struct meth_private *priv)
210 {
211 	/* Init TX ring */
212 	priv->tx_ring = dma_alloc_coherent(&priv->pdev->dev,
213 			TX_RING_BUFFER_SIZE, &priv->tx_ring_dma, GFP_ATOMIC);
214 	if (!priv->tx_ring)
215 		return -ENOMEM;
216 
217 	priv->tx_count = priv->tx_read = priv->tx_write = 0;
218 	mace->eth.tx_ring_base = priv->tx_ring_dma;
219 	/* Now init skb save area */
220 	memset(priv->tx_skbs, 0, sizeof(priv->tx_skbs));
221 	memset(priv->tx_skb_dmas, 0, sizeof(priv->tx_skb_dmas));
222 	return 0;
223 }
224 
meth_init_rx_ring(struct meth_private * priv)225 static int meth_init_rx_ring(struct meth_private *priv)
226 {
227 	int i;
228 
229 	for (i = 0; i < RX_RING_ENTRIES; i++) {
230 		priv->rx_skbs[i] = alloc_skb(METH_RX_BUFF_SIZE, 0);
231 		/* 8byte status vector + 3quad padding + 2byte padding,
232 		 * to put data on 64bit aligned boundary */
233 		skb_reserve(priv->rx_skbs[i],METH_RX_HEAD);
234 		priv->rx_ring[i]=(rx_packet*)(priv->rx_skbs[i]->head);
235 		/* I'll need to re-sync it after each RX */
236 		priv->rx_ring_dmas[i] =
237 			dma_map_single(&priv->pdev->dev, priv->rx_ring[i],
238 				       METH_RX_BUFF_SIZE, DMA_FROM_DEVICE);
239 		mace->eth.rx_fifo = priv->rx_ring_dmas[i];
240 	}
241         priv->rx_write = 0;
242 	return 0;
243 }
meth_free_tx_ring(struct meth_private * priv)244 static void meth_free_tx_ring(struct meth_private *priv)
245 {
246 	int i;
247 
248 	/* Remove any pending skb */
249 	for (i = 0; i < TX_RING_ENTRIES; i++) {
250 		dev_kfree_skb(priv->tx_skbs[i]);
251 		priv->tx_skbs[i] = NULL;
252 	}
253 	dma_free_coherent(&priv->pdev->dev, TX_RING_BUFFER_SIZE, priv->tx_ring,
254 	                  priv->tx_ring_dma);
255 }
256 
257 /* Presumes RX DMA engine is stopped, and RX fifo ring is reset */
meth_free_rx_ring(struct meth_private * priv)258 static void meth_free_rx_ring(struct meth_private *priv)
259 {
260 	int i;
261 
262 	for (i = 0; i < RX_RING_ENTRIES; i++) {
263 		dma_unmap_single(&priv->pdev->dev, priv->rx_ring_dmas[i],
264 				 METH_RX_BUFF_SIZE, DMA_FROM_DEVICE);
265 		priv->rx_ring[i] = 0;
266 		priv->rx_ring_dmas[i] = 0;
267 		kfree_skb(priv->rx_skbs[i]);
268 	}
269 }
270 
meth_reset(struct net_device * dev)271 int meth_reset(struct net_device *dev)
272 {
273 	struct meth_private *priv = netdev_priv(dev);
274 
275 	/* Reset card */
276 	mace->eth.mac_ctrl = SGI_MAC_RESET;
277 	udelay(1);
278 	mace->eth.mac_ctrl = 0;
279 	udelay(25);
280 
281 	/* Load ethernet address */
282 	load_eaddr(dev);
283 	/* Should load some "errata", but later */
284 
285 	/* Check for device */
286 	if (mdio_probe(priv) < 0) {
287 		DPRINTK("Unable to find PHY\n");
288 		return -ENODEV;
289 	}
290 
291 	/* Initial mode: 10 | Half-duplex | Accept normal packets */
292 	priv->mac_ctrl = METH_ACCEPT_MCAST | METH_DEFAULT_IPG;
293 	if (dev->flags & IFF_PROMISC)
294 		priv->mac_ctrl |= METH_PROMISC;
295 	mace->eth.mac_ctrl = priv->mac_ctrl;
296 
297 	/* Autonegotiate speed and duplex mode */
298 	meth_check_link(dev);
299 
300 	/* Now set dma control, but don't enable DMA, yet */
301 	priv->dma_ctrl = (4 << METH_RX_OFFSET_SHIFT) |
302 			 (RX_RING_ENTRIES << METH_RX_DEPTH_SHIFT);
303 	mace->eth.dma_ctrl = priv->dma_ctrl;
304 
305 	return 0;
306 }
307 
308 /*============End Helper Routines=====================*/
309 
310 /*
311  * Open and close
312  */
meth_open(struct net_device * dev)313 static int meth_open(struct net_device *dev)
314 {
315 	struct meth_private *priv = netdev_priv(dev);
316 	int ret;
317 
318 	priv->phy_addr = -1;    /* No PHY is known yet... */
319 
320 	/* Initialize the hardware */
321 	ret = meth_reset(dev);
322 	if (ret < 0)
323 		return ret;
324 
325 	/* Allocate the ring buffers */
326 	ret = meth_init_tx_ring(priv);
327 	if (ret < 0)
328 		return ret;
329 	ret = meth_init_rx_ring(priv);
330 	if (ret < 0)
331 		goto out_free_tx_ring;
332 
333 	ret = request_irq(dev->irq, meth_interrupt, 0, meth_str, dev);
334 	if (ret) {
335 		printk(KERN_ERR "%s: Can't get irq %d\n", dev->name, dev->irq);
336 		goto out_free_rx_ring;
337 	}
338 
339 	/* Start DMA */
340 	priv->dma_ctrl |= METH_DMA_TX_EN | /*METH_DMA_TX_INT_EN |*/
341 			  METH_DMA_RX_EN | METH_DMA_RX_INT_EN;
342 	mace->eth.dma_ctrl = priv->dma_ctrl;
343 
344 	DPRINTK("About to start queue\n");
345 	netif_start_queue(dev);
346 
347 	return 0;
348 
349 out_free_rx_ring:
350 	meth_free_rx_ring(priv);
351 out_free_tx_ring:
352 	meth_free_tx_ring(priv);
353 
354 	return ret;
355 }
356 
meth_release(struct net_device * dev)357 static int meth_release(struct net_device *dev)
358 {
359 	struct meth_private *priv = netdev_priv(dev);
360 
361 	DPRINTK("Stopping queue\n");
362 	netif_stop_queue(dev); /* can't transmit any more */
363 	/* shut down DMA */
364 	priv->dma_ctrl &= ~(METH_DMA_TX_EN | METH_DMA_TX_INT_EN |
365 			    METH_DMA_RX_EN | METH_DMA_RX_INT_EN);
366 	mace->eth.dma_ctrl = priv->dma_ctrl;
367 	free_irq(dev->irq, dev);
368 	meth_free_tx_ring(priv);
369 	meth_free_rx_ring(priv);
370 
371 	return 0;
372 }
373 
374 /*
375  * Receive a packet: retrieve, encapsulate and pass over to upper levels
376  */
meth_rx(struct net_device * dev,unsigned long int_status)377 static void meth_rx(struct net_device* dev, unsigned long int_status)
378 {
379 	struct sk_buff *skb;
380 	unsigned long status, flags;
381 	struct meth_private *priv = netdev_priv(dev);
382 	unsigned long fifo_rptr = (int_status & METH_INT_RX_RPTR_MASK) >> 8;
383 
384 	spin_lock_irqsave(&priv->meth_lock, flags);
385 	priv->dma_ctrl &= ~METH_DMA_RX_INT_EN;
386 	mace->eth.dma_ctrl = priv->dma_ctrl;
387 	spin_unlock_irqrestore(&priv->meth_lock, flags);
388 
389 	if (int_status & METH_INT_RX_UNDERFLOW) {
390 		fifo_rptr = (fifo_rptr - 1) & 0x0f;
391 	}
392 	while (priv->rx_write != fifo_rptr) {
393 		dma_unmap_single(&priv->pdev->dev,
394 				 priv->rx_ring_dmas[priv->rx_write],
395 				 METH_RX_BUFF_SIZE, DMA_FROM_DEVICE);
396 		status = priv->rx_ring[priv->rx_write]->status.raw;
397 #if MFE_DEBUG
398 		if (!(status & METH_RX_ST_VALID)) {
399 			DPRINTK("Not received? status=%016lx\n",status);
400 		}
401 #endif
402 		if ((!(status & METH_RX_STATUS_ERRORS)) && (status & METH_RX_ST_VALID)) {
403 			int len = (status & 0xffff) - 4; /* omit CRC */
404 			/* length sanity check */
405 			if (len < 60 || len > 1518) {
406 				printk(KERN_DEBUG "%s: bogus packet size: %ld, status=%#2Lx.\n",
407 				       dev->name, priv->rx_write,
408 				       priv->rx_ring[priv->rx_write]->status.raw);
409 				dev->stats.rx_errors++;
410 				dev->stats.rx_length_errors++;
411 				skb = priv->rx_skbs[priv->rx_write];
412 			} else {
413 				skb = alloc_skb(METH_RX_BUFF_SIZE, GFP_ATOMIC);
414 				if (!skb) {
415 					/* Ouch! No memory! Drop packet on the floor */
416 					DPRINTK("No mem: dropping packet\n");
417 					dev->stats.rx_dropped++;
418 					skb = priv->rx_skbs[priv->rx_write];
419 				} else {
420 					struct sk_buff *skb_c = priv->rx_skbs[priv->rx_write];
421 					/* 8byte status vector + 3quad padding + 2byte padding,
422 					 * to put data on 64bit aligned boundary */
423 					skb_reserve(skb, METH_RX_HEAD);
424 					/* Write metadata, and then pass to the receive level */
425 					skb_put(skb_c, len);
426 					priv->rx_skbs[priv->rx_write] = skb;
427 					skb_c->protocol = eth_type_trans(skb_c, dev);
428 					dev->stats.rx_packets++;
429 					dev->stats.rx_bytes += len;
430 					netif_rx(skb_c);
431 				}
432 			}
433 		} else {
434 			dev->stats.rx_errors++;
435 			skb=priv->rx_skbs[priv->rx_write];
436 #if MFE_DEBUG>0
437 			printk(KERN_WARNING "meth: RX error: status=0x%016lx\n",status);
438 			if(status&METH_RX_ST_RCV_CODE_VIOLATION)
439 				printk(KERN_WARNING "Receive Code Violation\n");
440 			if(status&METH_RX_ST_CRC_ERR)
441 				printk(KERN_WARNING "CRC error\n");
442 			if(status&METH_RX_ST_INV_PREAMBLE_CTX)
443 				printk(KERN_WARNING "Invalid Preamble Context\n");
444 			if(status&METH_RX_ST_LONG_EVT_SEEN)
445 				printk(KERN_WARNING "Long Event Seen...\n");
446 			if(status&METH_RX_ST_BAD_PACKET)
447 				printk(KERN_WARNING "Bad Packet\n");
448 			if(status&METH_RX_ST_CARRIER_EVT_SEEN)
449 				printk(KERN_WARNING "Carrier Event Seen\n");
450 #endif
451 		}
452 		priv->rx_ring[priv->rx_write] = (rx_packet*)skb->head;
453 		priv->rx_ring[priv->rx_write]->status.raw = 0;
454 		priv->rx_ring_dmas[priv->rx_write] =
455 			dma_map_single(&priv->pdev->dev,
456 				       priv->rx_ring[priv->rx_write],
457 				       METH_RX_BUFF_SIZE, DMA_FROM_DEVICE);
458 		mace->eth.rx_fifo = priv->rx_ring_dmas[priv->rx_write];
459 		ADVANCE_RX_PTR(priv->rx_write);
460 	}
461 	spin_lock_irqsave(&priv->meth_lock, flags);
462 	/* In case there was underflow, and Rx DMA was disabled */
463 	priv->dma_ctrl |= METH_DMA_RX_INT_EN | METH_DMA_RX_EN;
464 	mace->eth.dma_ctrl = priv->dma_ctrl;
465 	mace->eth.int_stat = METH_INT_RX_THRESHOLD;
466 	spin_unlock_irqrestore(&priv->meth_lock, flags);
467 }
468 
meth_tx_full(struct net_device * dev)469 static int meth_tx_full(struct net_device *dev)
470 {
471 	struct meth_private *priv = netdev_priv(dev);
472 
473 	return priv->tx_count >= TX_RING_ENTRIES - 1;
474 }
475 
meth_tx_cleanup(struct net_device * dev,unsigned long int_status)476 static void meth_tx_cleanup(struct net_device* dev, unsigned long int_status)
477 {
478 	struct meth_private *priv = netdev_priv(dev);
479 	unsigned long status, flags;
480 	struct sk_buff *skb;
481 	unsigned long rptr = (int_status&TX_INFO_RPTR) >> 16;
482 
483 	spin_lock_irqsave(&priv->meth_lock, flags);
484 
485 	/* Stop DMA notification */
486 	priv->dma_ctrl &= ~(METH_DMA_TX_INT_EN);
487 	mace->eth.dma_ctrl = priv->dma_ctrl;
488 
489 	while (priv->tx_read != rptr) {
490 		skb = priv->tx_skbs[priv->tx_read];
491 		status = priv->tx_ring[priv->tx_read].header.raw;
492 #if MFE_DEBUG>=1
493 		if (priv->tx_read == priv->tx_write)
494 			DPRINTK("Auchi! tx_read=%d,tx_write=%d,rptr=%d?\n", priv->tx_read, priv->tx_write,rptr);
495 #endif
496 		if (status & METH_TX_ST_DONE) {
497 			if (status & METH_TX_ST_SUCCESS){
498 				dev->stats.tx_packets++;
499 				dev->stats.tx_bytes += skb->len;
500 			} else {
501 				dev->stats.tx_errors++;
502 #if MFE_DEBUG>=1
503 				DPRINTK("TX error: status=%016lx <",status);
504 				if(status & METH_TX_ST_SUCCESS)
505 					printk(" SUCCESS");
506 				if(status & METH_TX_ST_TOOLONG)
507 					printk(" TOOLONG");
508 				if(status & METH_TX_ST_UNDERRUN)
509 					printk(" UNDERRUN");
510 				if(status & METH_TX_ST_EXCCOLL)
511 					printk(" EXCCOLL");
512 				if(status & METH_TX_ST_DEFER)
513 					printk(" DEFER");
514 				if(status & METH_TX_ST_LATECOLL)
515 					printk(" LATECOLL");
516 				printk(" >\n");
517 #endif
518 			}
519 		} else {
520 			DPRINTK("RPTR points us here, but packet not done?\n");
521 			break;
522 		}
523 		dev_consume_skb_irq(skb);
524 		priv->tx_skbs[priv->tx_read] = NULL;
525 		priv->tx_ring[priv->tx_read].header.raw = 0;
526 		priv->tx_read = (priv->tx_read+1)&(TX_RING_ENTRIES-1);
527 		priv->tx_count--;
528 	}
529 
530 	/* wake up queue if it was stopped */
531 	if (netif_queue_stopped(dev) && !meth_tx_full(dev)) {
532 		netif_wake_queue(dev);
533 	}
534 
535 	mace->eth.int_stat = METH_INT_TX_EMPTY | METH_INT_TX_PKT;
536 	spin_unlock_irqrestore(&priv->meth_lock, flags);
537 }
538 
meth_error(struct net_device * dev,unsigned status)539 static void meth_error(struct net_device* dev, unsigned status)
540 {
541 	struct meth_private *priv = netdev_priv(dev);
542 	unsigned long flags;
543 
544 	printk(KERN_WARNING "meth: error status: 0x%08x\n",status);
545 	/* check for errors too... */
546 	if (status & (METH_INT_TX_LINK_FAIL))
547 		printk(KERN_WARNING "meth: link failure\n");
548 	/* Should I do full reset in this case? */
549 	if (status & (METH_INT_MEM_ERROR))
550 		printk(KERN_WARNING "meth: memory error\n");
551 	if (status & (METH_INT_TX_ABORT))
552 		printk(KERN_WARNING "meth: aborted\n");
553 	if (status & (METH_INT_RX_OVERFLOW))
554 		printk(KERN_WARNING "meth: Rx overflow\n");
555 	if (status & (METH_INT_RX_UNDERFLOW)) {
556 		printk(KERN_WARNING "meth: Rx underflow\n");
557 		spin_lock_irqsave(&priv->meth_lock, flags);
558 		mace->eth.int_stat = METH_INT_RX_UNDERFLOW;
559 		/* more underflow interrupts will be delivered,
560 		 * effectively throwing us into an infinite loop.
561 		 *  Thus I stop processing Rx in this case. */
562 		priv->dma_ctrl &= ~METH_DMA_RX_EN;
563 		mace->eth.dma_ctrl = priv->dma_ctrl;
564 		DPRINTK("Disabled meth Rx DMA temporarily\n");
565 		spin_unlock_irqrestore(&priv->meth_lock, flags);
566 	}
567 	mace->eth.int_stat = METH_INT_ERROR;
568 }
569 
570 /*
571  * The typical interrupt entry point
572  */
meth_interrupt(int irq,void * dev_id)573 static irqreturn_t meth_interrupt(int irq, void *dev_id)
574 {
575 	struct net_device *dev = (struct net_device *)dev_id;
576 	struct meth_private *priv = netdev_priv(dev);
577 	unsigned long status;
578 
579 	status = mace->eth.int_stat;
580 	while (status & 0xff) {
581 		/* First handle errors - if we get Rx underflow,
582 		 * Rx DMA will be disabled, and Rx handler will reenable
583 		 * it. I don't think it's possible to get Rx underflow,
584 		 * without getting Rx interrupt */
585 		if (status & METH_INT_ERROR) {
586 			meth_error(dev, status);
587 		}
588 		if (status & (METH_INT_TX_EMPTY | METH_INT_TX_PKT)) {
589 			/* a transmission is over: free the skb */
590 			meth_tx_cleanup(dev, status);
591 		}
592 		if (status & METH_INT_RX_THRESHOLD) {
593 			if (!(priv->dma_ctrl & METH_DMA_RX_INT_EN))
594 				break;
595 			/* send it to meth_rx for handling */
596 			meth_rx(dev, status);
597 		}
598 		status = mace->eth.int_stat;
599 	}
600 
601 	return IRQ_HANDLED;
602 }
603 
604 /*
605  * Transmits packets that fit into TX descriptor (are <=120B)
606  */
meth_tx_short_prepare(struct meth_private * priv,struct sk_buff * skb)607 static void meth_tx_short_prepare(struct meth_private *priv,
608 				  struct sk_buff *skb)
609 {
610 	tx_packet *desc = &priv->tx_ring[priv->tx_write];
611 	int len = (skb->len < ETH_ZLEN) ? ETH_ZLEN : skb->len;
612 
613 	desc->header.raw = METH_TX_CMD_INT_EN | (len-1) | ((128-len) << 16);
614 	/* maybe I should set whole thing to 0 first... */
615 	skb_copy_from_linear_data(skb, desc->data.dt + (120 - len), skb->len);
616 	if (skb->len < len)
617 		memset(desc->data.dt + 120 - len + skb->len, 0, len-skb->len);
618 }
619 #define TX_CATBUF1 BIT(25)
meth_tx_1page_prepare(struct meth_private * priv,struct sk_buff * skb)620 static void meth_tx_1page_prepare(struct meth_private *priv,
621 				  struct sk_buff *skb)
622 {
623 	tx_packet *desc = &priv->tx_ring[priv->tx_write];
624 	void *buffer_data = (void *)(((unsigned long)skb->data + 7) & ~7);
625 	int unaligned_len = (int)((unsigned long)buffer_data - (unsigned long)skb->data);
626 	int buffer_len = skb->len - unaligned_len;
627 	dma_addr_t catbuf;
628 
629 	desc->header.raw = METH_TX_CMD_INT_EN | TX_CATBUF1 | (skb->len - 1);
630 
631 	/* unaligned part */
632 	if (unaligned_len) {
633 		skb_copy_from_linear_data(skb, desc->data.dt + (120 - unaligned_len),
634 			      unaligned_len);
635 		desc->header.raw |= (128 - unaligned_len) << 16;
636 	}
637 
638 	/* first page */
639 	catbuf = dma_map_single(&priv->pdev->dev, buffer_data, buffer_len,
640 				DMA_TO_DEVICE);
641 	desc->data.cat_buf[0].form.start_addr = catbuf >> 3;
642 	desc->data.cat_buf[0].form.len = buffer_len - 1;
643 }
644 #define TX_CATBUF2 BIT(26)
meth_tx_2page_prepare(struct meth_private * priv,struct sk_buff * skb)645 static void meth_tx_2page_prepare(struct meth_private *priv,
646 				  struct sk_buff *skb)
647 {
648 	tx_packet *desc = &priv->tx_ring[priv->tx_write];
649 	void *buffer1_data = (void *)(((unsigned long)skb->data + 7) & ~7);
650 	void *buffer2_data = (void *)PAGE_ALIGN((unsigned long)skb->data);
651 	int unaligned_len = (int)((unsigned long)buffer1_data - (unsigned long)skb->data);
652 	int buffer1_len = (int)((unsigned long)buffer2_data - (unsigned long)buffer1_data);
653 	int buffer2_len = skb->len - buffer1_len - unaligned_len;
654 	dma_addr_t catbuf1, catbuf2;
655 
656 	desc->header.raw = METH_TX_CMD_INT_EN | TX_CATBUF1 | TX_CATBUF2| (skb->len - 1);
657 	/* unaligned part */
658 	if (unaligned_len){
659 		skb_copy_from_linear_data(skb, desc->data.dt + (120 - unaligned_len),
660 			      unaligned_len);
661 		desc->header.raw |= (128 - unaligned_len) << 16;
662 	}
663 
664 	/* first page */
665 	catbuf1 = dma_map_single(&priv->pdev->dev, buffer1_data, buffer1_len,
666 				 DMA_TO_DEVICE);
667 	desc->data.cat_buf[0].form.start_addr = catbuf1 >> 3;
668 	desc->data.cat_buf[0].form.len = buffer1_len - 1;
669 	/* second page */
670 	catbuf2 = dma_map_single(&priv->pdev->dev, buffer2_data, buffer2_len,
671 				 DMA_TO_DEVICE);
672 	desc->data.cat_buf[1].form.start_addr = catbuf2 >> 3;
673 	desc->data.cat_buf[1].form.len = buffer2_len - 1;
674 }
675 
meth_add_to_tx_ring(struct meth_private * priv,struct sk_buff * skb)676 static void meth_add_to_tx_ring(struct meth_private *priv, struct sk_buff *skb)
677 {
678 	/* Remember the skb, so we can free it at interrupt time */
679 	priv->tx_skbs[priv->tx_write] = skb;
680 	if (skb->len <= 120) {
681 		/* Whole packet fits into descriptor */
682 		meth_tx_short_prepare(priv, skb);
683 	} else if (PAGE_ALIGN((unsigned long)skb->data) !=
684 		   PAGE_ALIGN((unsigned long)skb->data + skb->len - 1)) {
685 		/* Packet crosses page boundary */
686 		meth_tx_2page_prepare(priv, skb);
687 	} else {
688 		/* Packet is in one page */
689 		meth_tx_1page_prepare(priv, skb);
690 	}
691 	priv->tx_write = (priv->tx_write + 1) & (TX_RING_ENTRIES - 1);
692 	mace->eth.tx_info = priv->tx_write;
693 	priv->tx_count++;
694 }
695 
696 /*
697  * Transmit a packet (called by the kernel)
698  */
meth_tx(struct sk_buff * skb,struct net_device * dev)699 static netdev_tx_t meth_tx(struct sk_buff *skb, struct net_device *dev)
700 {
701 	struct meth_private *priv = netdev_priv(dev);
702 	unsigned long flags;
703 
704 	spin_lock_irqsave(&priv->meth_lock, flags);
705 	/* Stop DMA notification */
706 	priv->dma_ctrl &= ~(METH_DMA_TX_INT_EN);
707 	mace->eth.dma_ctrl = priv->dma_ctrl;
708 
709 	meth_add_to_tx_ring(priv, skb);
710 	netif_trans_update(dev); /* save the timestamp */
711 
712 	/* If TX ring is full, tell the upper layer to stop sending packets */
713 	if (meth_tx_full(dev)) {
714 	        printk(KERN_DEBUG "TX full: stopping\n");
715 		netif_stop_queue(dev);
716 	}
717 
718 	/* Restart DMA notification */
719 	priv->dma_ctrl |= METH_DMA_TX_INT_EN;
720 	mace->eth.dma_ctrl = priv->dma_ctrl;
721 
722 	spin_unlock_irqrestore(&priv->meth_lock, flags);
723 
724 	return NETDEV_TX_OK;
725 }
726 
727 /*
728  * Deal with a transmit timeout.
729  */
meth_tx_timeout(struct net_device * dev,unsigned int txqueue)730 static void meth_tx_timeout(struct net_device *dev, unsigned int txqueue)
731 {
732 	struct meth_private *priv = netdev_priv(dev);
733 	unsigned long flags;
734 
735 	printk(KERN_WARNING "%s: transmit timed out\n", dev->name);
736 
737 	/* Protect against concurrent rx interrupts */
738 	spin_lock_irqsave(&priv->meth_lock,flags);
739 
740 	/* Try to reset the interface. */
741 	meth_reset(dev);
742 
743 	dev->stats.tx_errors++;
744 
745 	/* Clear all rings */
746 	meth_free_tx_ring(priv);
747 	meth_free_rx_ring(priv);
748 	meth_init_tx_ring(priv);
749 	meth_init_rx_ring(priv);
750 
751 	/* Restart dma */
752 	priv->dma_ctrl |= METH_DMA_TX_EN | METH_DMA_RX_EN | METH_DMA_RX_INT_EN;
753 	mace->eth.dma_ctrl = priv->dma_ctrl;
754 
755 	/* Enable interrupt */
756 	spin_unlock_irqrestore(&priv->meth_lock, flags);
757 
758 	netif_trans_update(dev); /* prevent tx timeout */
759 	netif_wake_queue(dev);
760 }
761 
762 /*
763  * Ioctl commands
764  */
meth_ioctl(struct net_device * dev,struct ifreq * rq,int cmd)765 static int meth_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
766 {
767 	/* XXX Not yet implemented */
768 	switch(cmd) {
769 	case SIOCGMIIPHY:
770 	case SIOCGMIIREG:
771 	case SIOCSMIIREG:
772 	default:
773 		return -EOPNOTSUPP;
774 	}
775 }
776 
meth_set_rx_mode(struct net_device * dev)777 static void meth_set_rx_mode(struct net_device *dev)
778 {
779 	struct meth_private *priv = netdev_priv(dev);
780 	unsigned long flags;
781 
782 	netif_stop_queue(dev);
783 	spin_lock_irqsave(&priv->meth_lock, flags);
784 	priv->mac_ctrl &= ~METH_PROMISC;
785 
786 	if (dev->flags & IFF_PROMISC) {
787 		priv->mac_ctrl |= METH_PROMISC;
788 		priv->mcast_filter = 0xffffffffffffffffUL;
789 	} else if ((netdev_mc_count(dev) > METH_MCF_LIMIT) ||
790 		   (dev->flags & IFF_ALLMULTI)) {
791 		priv->mac_ctrl |= METH_ACCEPT_AMCAST;
792 		priv->mcast_filter = 0xffffffffffffffffUL;
793 	} else {
794 		struct netdev_hw_addr *ha;
795 		priv->mac_ctrl |= METH_ACCEPT_MCAST;
796 
797 		netdev_for_each_mc_addr(ha, dev)
798 			set_bit((ether_crc(ETH_ALEN, ha->addr) >> 26),
799 			        (volatile unsigned long *)&priv->mcast_filter);
800 	}
801 
802 	/* Write the changes to the chip registers. */
803 	mace->eth.mac_ctrl = priv->mac_ctrl;
804 	mace->eth.mcast_filter = priv->mcast_filter;
805 
806 	/* Done! */
807 	spin_unlock_irqrestore(&priv->meth_lock, flags);
808 	netif_wake_queue(dev);
809 }
810 
811 static const struct net_device_ops meth_netdev_ops = {
812 	.ndo_open		= meth_open,
813 	.ndo_stop		= meth_release,
814 	.ndo_start_xmit		= meth_tx,
815 	.ndo_eth_ioctl		= meth_ioctl,
816 	.ndo_tx_timeout		= meth_tx_timeout,
817 	.ndo_validate_addr	= eth_validate_addr,
818 	.ndo_set_mac_address	= eth_mac_addr,
819 	.ndo_set_rx_mode    	= meth_set_rx_mode,
820 };
821 
822 /*
823  * The init function.
824  */
meth_probe(struct platform_device * pdev)825 static int meth_probe(struct platform_device *pdev)
826 {
827 	struct net_device *dev;
828 	struct meth_private *priv;
829 	int err;
830 
831 	dev = alloc_etherdev(sizeof(struct meth_private));
832 	if (!dev)
833 		return -ENOMEM;
834 
835 	dev->netdev_ops		= &meth_netdev_ops;
836 	dev->watchdog_timeo	= timeout;
837 	dev->irq		= MACE_ETHERNET_IRQ;
838 	dev->base_addr		= (unsigned long)&mace->eth;
839 	eth_hw_addr_set(dev, o2meth_eaddr);
840 
841 	priv = netdev_priv(dev);
842 	priv->pdev = pdev;
843 	spin_lock_init(&priv->meth_lock);
844 	SET_NETDEV_DEV(dev, &pdev->dev);
845 
846 	err = register_netdev(dev);
847 	if (err) {
848 		free_netdev(dev);
849 		return err;
850 	}
851 
852 	printk(KERN_INFO "%s: SGI MACE Ethernet rev. %d\n",
853 	       dev->name, (unsigned int)(mace->eth.mac_ctrl >> 29));
854 	return 0;
855 }
856 
meth_remove(struct platform_device * pdev)857 static void meth_remove(struct platform_device *pdev)
858 {
859 	struct net_device *dev = platform_get_drvdata(pdev);
860 
861 	unregister_netdev(dev);
862 	free_netdev(dev);
863 }
864 
865 static struct platform_driver meth_driver = {
866 	.probe	= meth_probe,
867 	.remove_new = meth_remove,
868 	.driver = {
869 		.name	= "meth",
870 	}
871 };
872 
873 module_platform_driver(meth_driver);
874 
875 MODULE_AUTHOR("Ilya Volynets <ilya@theIlya.com>");
876 MODULE_DESCRIPTION("SGI O2 Builtin Fast Ethernet driver");
877 MODULE_LICENSE("GPL");
878 MODULE_ALIAS("platform:meth");
879