1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2015 Endless Mobile, Inc.
4 * Author: Carlo Caione <carlo@endlessm.com>
5 *
6 * Copyright (c) 2018 Baylibre, SAS.
7 * Author: Jerome Brunet <jbrunet@baylibre.com>
8 */
9
10 /*
11 * In the most basic form, a Meson PLL is composed as follows:
12 *
13 * PLL
14 * +--------------------------------+
15 * | |
16 * | +--+ |
17 * in >>-----[ /N ]--->| | +-----+ |
18 * | | |------| DCO |---->> out
19 * | +--------->| | +--v--+ |
20 * | | +--+ | |
21 * | | | |
22 * | +--[ *(M + (F/Fmax) ]<--+ |
23 * | |
24 * +--------------------------------+
25 *
26 * out = in * (m + frac / frac_max) / n
27 */
28
29 #include <linux/clk-provider.h>
30 #include <linux/delay.h>
31 #include <linux/err.h>
32 #include <linux/io.h>
33 #include <linux/math64.h>
34 #include <linux/module.h>
35
36 #include "clk-regmap.h"
37 #include "clk-pll.h"
38
39 static inline struct meson_clk_pll_data *
meson_clk_pll_data(struct clk_regmap * clk)40 meson_clk_pll_data(struct clk_regmap *clk)
41 {
42 return (struct meson_clk_pll_data *)clk->data;
43 }
44
__pll_round_closest_mult(struct meson_clk_pll_data * pll)45 static int __pll_round_closest_mult(struct meson_clk_pll_data *pll)
46 {
47 if ((pll->flags & CLK_MESON_PLL_ROUND_CLOSEST) &&
48 !MESON_PARM_APPLICABLE(&pll->frac))
49 return 1;
50
51 return 0;
52 }
53
__pll_params_to_rate(unsigned long parent_rate,unsigned int m,unsigned int n,unsigned int frac,struct meson_clk_pll_data * pll)54 static unsigned long __pll_params_to_rate(unsigned long parent_rate,
55 unsigned int m, unsigned int n,
56 unsigned int frac,
57 struct meson_clk_pll_data *pll)
58 {
59 u64 rate = (u64)parent_rate * m;
60 unsigned int frac_max = pll->frac_max ? pll->frac_max :
61 (1 << pll->frac.width);
62
63 if (frac && MESON_PARM_APPLICABLE(&pll->frac)) {
64 u64 frac_rate = (u64)parent_rate * frac;
65
66 rate += DIV_ROUND_UP_ULL(frac_rate, frac_max);
67 }
68
69 return DIV_ROUND_UP_ULL(rate, n);
70 }
71
meson_clk_pll_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)72 static unsigned long meson_clk_pll_recalc_rate(struct clk_hw *hw,
73 unsigned long parent_rate)
74 {
75 struct clk_regmap *clk = to_clk_regmap(hw);
76 struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
77 unsigned int m, n, frac;
78
79 n = meson_parm_read(clk->map, &pll->n);
80
81 /*
82 * On some HW, N is set to zero on init. This value is invalid as
83 * it would result in a division by zero. The rate can't be
84 * calculated in this case
85 */
86 if (n == 0)
87 return 0;
88
89 m = meson_parm_read(clk->map, &pll->m);
90
91 frac = MESON_PARM_APPLICABLE(&pll->frac) ?
92 meson_parm_read(clk->map, &pll->frac) :
93 0;
94
95 return __pll_params_to_rate(parent_rate, m, n, frac, pll);
96 }
97
__pll_params_with_frac(unsigned long rate,unsigned long parent_rate,unsigned int m,unsigned int n,struct meson_clk_pll_data * pll)98 static unsigned int __pll_params_with_frac(unsigned long rate,
99 unsigned long parent_rate,
100 unsigned int m,
101 unsigned int n,
102 struct meson_clk_pll_data *pll)
103 {
104 unsigned int frac_max = pll->frac_max ? pll->frac_max :
105 (1 << pll->frac.width);
106 u64 val = (u64)rate * n;
107
108 /* Bail out if we are already over the requested rate */
109 if (rate < parent_rate * m / n)
110 return 0;
111
112 if (pll->flags & CLK_MESON_PLL_ROUND_CLOSEST)
113 val = DIV_ROUND_CLOSEST_ULL(val * frac_max, parent_rate);
114 else
115 val = div_u64(val * frac_max, parent_rate);
116
117 val -= m * frac_max;
118
119 return min((unsigned int)val, (frac_max - 1));
120 }
121
meson_clk_pll_is_better(unsigned long rate,unsigned long best,unsigned long now,struct meson_clk_pll_data * pll)122 static bool meson_clk_pll_is_better(unsigned long rate,
123 unsigned long best,
124 unsigned long now,
125 struct meson_clk_pll_data *pll)
126 {
127 if (__pll_round_closest_mult(pll)) {
128 /* Round Closest */
129 if (abs(now - rate) < abs(best - rate))
130 return true;
131 } else {
132 /* Round down */
133 if (now <= rate && best < now)
134 return true;
135 }
136
137 return false;
138 }
139
meson_clk_get_pll_table_index(unsigned int index,unsigned int * m,unsigned int * n,struct meson_clk_pll_data * pll)140 static int meson_clk_get_pll_table_index(unsigned int index,
141 unsigned int *m,
142 unsigned int *n,
143 struct meson_clk_pll_data *pll)
144 {
145 if (!pll->table[index].n)
146 return -EINVAL;
147
148 *m = pll->table[index].m;
149 *n = pll->table[index].n;
150
151 return 0;
152 }
153
meson_clk_get_pll_range_m(unsigned long rate,unsigned long parent_rate,unsigned int n,struct meson_clk_pll_data * pll)154 static unsigned int meson_clk_get_pll_range_m(unsigned long rate,
155 unsigned long parent_rate,
156 unsigned int n,
157 struct meson_clk_pll_data *pll)
158 {
159 u64 val = (u64)rate * n;
160
161 if (__pll_round_closest_mult(pll))
162 return DIV_ROUND_CLOSEST_ULL(val, parent_rate);
163
164 return div_u64(val, parent_rate);
165 }
166
meson_clk_get_pll_range_index(unsigned long rate,unsigned long parent_rate,unsigned int index,unsigned int * m,unsigned int * n,struct meson_clk_pll_data * pll)167 static int meson_clk_get_pll_range_index(unsigned long rate,
168 unsigned long parent_rate,
169 unsigned int index,
170 unsigned int *m,
171 unsigned int *n,
172 struct meson_clk_pll_data *pll)
173 {
174 *n = index + 1;
175
176 /* Check the predivider range */
177 if (*n >= (1 << pll->n.width))
178 return -EINVAL;
179
180 if (*n == 1) {
181 /* Get the boundaries out the way */
182 if (rate <= pll->range->min * parent_rate) {
183 *m = pll->range->min;
184 return -ENODATA;
185 } else if (rate >= pll->range->max * parent_rate) {
186 *m = pll->range->max;
187 return -ENODATA;
188 }
189 }
190
191 *m = meson_clk_get_pll_range_m(rate, parent_rate, *n, pll);
192
193 /* the pre-divider gives a multiplier too big - stop */
194 if (*m >= (1 << pll->m.width))
195 return -EINVAL;
196
197 return 0;
198 }
199
meson_clk_get_pll_get_index(unsigned long rate,unsigned long parent_rate,unsigned int index,unsigned int * m,unsigned int * n,struct meson_clk_pll_data * pll)200 static int meson_clk_get_pll_get_index(unsigned long rate,
201 unsigned long parent_rate,
202 unsigned int index,
203 unsigned int *m,
204 unsigned int *n,
205 struct meson_clk_pll_data *pll)
206 {
207 if (pll->range)
208 return meson_clk_get_pll_range_index(rate, parent_rate,
209 index, m, n, pll);
210 else if (pll->table)
211 return meson_clk_get_pll_table_index(index, m, n, pll);
212
213 return -EINVAL;
214 }
215
meson_clk_get_pll_settings(unsigned long rate,unsigned long parent_rate,unsigned int * best_m,unsigned int * best_n,struct meson_clk_pll_data * pll)216 static int meson_clk_get_pll_settings(unsigned long rate,
217 unsigned long parent_rate,
218 unsigned int *best_m,
219 unsigned int *best_n,
220 struct meson_clk_pll_data *pll)
221 {
222 unsigned long best = 0, now = 0;
223 unsigned int i, m, n;
224 int ret;
225
226 for (i = 0, ret = 0; !ret; i++) {
227 ret = meson_clk_get_pll_get_index(rate, parent_rate,
228 i, &m, &n, pll);
229 if (ret == -EINVAL)
230 break;
231
232 now = __pll_params_to_rate(parent_rate, m, n, 0, pll);
233 if (meson_clk_pll_is_better(rate, best, now, pll)) {
234 best = now;
235 *best_m = m;
236 *best_n = n;
237
238 if (now == rate)
239 break;
240 }
241 }
242
243 return best ? 0 : -EINVAL;
244 }
245
meson_clk_pll_determine_rate(struct clk_hw * hw,struct clk_rate_request * req)246 static int meson_clk_pll_determine_rate(struct clk_hw *hw,
247 struct clk_rate_request *req)
248 {
249 struct clk_regmap *clk = to_clk_regmap(hw);
250 struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
251 unsigned int m, n, frac;
252 unsigned long round;
253 int ret;
254
255 ret = meson_clk_get_pll_settings(req->rate, req->best_parent_rate,
256 &m, &n, pll);
257 if (ret)
258 return ret;
259
260 round = __pll_params_to_rate(req->best_parent_rate, m, n, 0, pll);
261
262 if (!MESON_PARM_APPLICABLE(&pll->frac) || req->rate == round) {
263 req->rate = round;
264 return 0;
265 }
266
267 /*
268 * The rate provided by the setting is not an exact match, let's
269 * try to improve the result using the fractional parameter
270 */
271 frac = __pll_params_with_frac(req->rate, req->best_parent_rate, m, n, pll);
272 req->rate = __pll_params_to_rate(req->best_parent_rate, m, n, frac, pll);
273
274 return 0;
275 }
276
meson_clk_pll_wait_lock(struct clk_hw * hw)277 static int meson_clk_pll_wait_lock(struct clk_hw *hw)
278 {
279 struct clk_regmap *clk = to_clk_regmap(hw);
280 struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
281 int delay = 5000;
282
283 do {
284 /* Is the clock locked now ? Time out after 100ms. */
285 if (meson_parm_read(clk->map, &pll->l))
286 return 0;
287
288 udelay(20);
289 } while (--delay);
290
291 return -ETIMEDOUT;
292 }
293
meson_clk_pll_is_enabled(struct clk_hw * hw)294 static int meson_clk_pll_is_enabled(struct clk_hw *hw)
295 {
296 struct clk_regmap *clk = to_clk_regmap(hw);
297 struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
298
299 if (MESON_PARM_APPLICABLE(&pll->rst) &&
300 meson_parm_read(clk->map, &pll->rst))
301 return 0;
302
303 if (!meson_parm_read(clk->map, &pll->en) ||
304 !meson_parm_read(clk->map, &pll->l))
305 return 0;
306
307 return 1;
308 }
309
meson_clk_pll_init(struct clk_hw * hw)310 static int meson_clk_pll_init(struct clk_hw *hw)
311 {
312 struct clk_regmap *clk = to_clk_regmap(hw);
313 struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
314
315 /*
316 * Keep the clock running, which was already initialized and enabled
317 * from the bootloader stage, to avoid any glitches.
318 */
319 if ((pll->flags & CLK_MESON_PLL_NOINIT_ENABLED) &&
320 meson_clk_pll_is_enabled(hw))
321 return 0;
322
323 if (pll->init_count) {
324 if (MESON_PARM_APPLICABLE(&pll->rst))
325 meson_parm_write(clk->map, &pll->rst, 1);
326
327 regmap_multi_reg_write(clk->map, pll->init_regs,
328 pll->init_count);
329
330 if (MESON_PARM_APPLICABLE(&pll->rst))
331 meson_parm_write(clk->map, &pll->rst, 0);
332 }
333
334 return 0;
335 }
336
meson_clk_pcie_pll_enable(struct clk_hw * hw)337 static int meson_clk_pcie_pll_enable(struct clk_hw *hw)
338 {
339 int retries = 10;
340
341 do {
342 meson_clk_pll_init(hw);
343 if (!meson_clk_pll_wait_lock(hw))
344 return 0;
345 pr_info("Retry enabling PCIe PLL clock\n");
346 } while (--retries);
347
348 return -EIO;
349 }
350
meson_clk_pll_enable(struct clk_hw * hw)351 static int meson_clk_pll_enable(struct clk_hw *hw)
352 {
353 struct clk_regmap *clk = to_clk_regmap(hw);
354 struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
355
356 /* do nothing if the PLL is already enabled */
357 if (clk_hw_is_enabled(hw))
358 return 0;
359
360 /* Make sure the pll is in reset */
361 if (MESON_PARM_APPLICABLE(&pll->rst))
362 meson_parm_write(clk->map, &pll->rst, 1);
363
364 /* Enable the pll */
365 meson_parm_write(clk->map, &pll->en, 1);
366
367 /* Take the pll out reset */
368 if (MESON_PARM_APPLICABLE(&pll->rst))
369 meson_parm_write(clk->map, &pll->rst, 0);
370
371 /*
372 * Compared with the previous SoCs, self-adaption current module
373 * is newly added for A1, keep the new power-on sequence to enable the
374 * PLL. The sequence is:
375 * 1. enable the pll, delay for 10us
376 * 2. enable the pll self-adaption current module, delay for 40us
377 * 3. enable the lock detect module
378 */
379 if (MESON_PARM_APPLICABLE(&pll->current_en)) {
380 udelay(10);
381 meson_parm_write(clk->map, &pll->current_en, 1);
382 udelay(40);
383 }
384
385 if (MESON_PARM_APPLICABLE(&pll->l_detect)) {
386 meson_parm_write(clk->map, &pll->l_detect, 1);
387 meson_parm_write(clk->map, &pll->l_detect, 0);
388 }
389
390 if (meson_clk_pll_wait_lock(hw))
391 return -EIO;
392
393 return 0;
394 }
395
meson_clk_pll_disable(struct clk_hw * hw)396 static void meson_clk_pll_disable(struct clk_hw *hw)
397 {
398 struct clk_regmap *clk = to_clk_regmap(hw);
399 struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
400
401 /* Put the pll is in reset */
402 if (MESON_PARM_APPLICABLE(&pll->rst))
403 meson_parm_write(clk->map, &pll->rst, 1);
404
405 /* Disable the pll */
406 meson_parm_write(clk->map, &pll->en, 0);
407
408 /* Disable PLL internal self-adaption current module */
409 if (MESON_PARM_APPLICABLE(&pll->current_en))
410 meson_parm_write(clk->map, &pll->current_en, 0);
411 }
412
meson_clk_pll_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)413 static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
414 unsigned long parent_rate)
415 {
416 struct clk_regmap *clk = to_clk_regmap(hw);
417 struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
418 unsigned int enabled, m, n, frac = 0;
419 unsigned long old_rate;
420 int ret;
421
422 if (parent_rate == 0 || rate == 0)
423 return -EINVAL;
424
425 old_rate = clk_hw_get_rate(hw);
426
427 ret = meson_clk_get_pll_settings(rate, parent_rate, &m, &n, pll);
428 if (ret)
429 return ret;
430
431 enabled = meson_parm_read(clk->map, &pll->en);
432 if (enabled)
433 meson_clk_pll_disable(hw);
434
435 meson_parm_write(clk->map, &pll->n, n);
436 meson_parm_write(clk->map, &pll->m, m);
437
438 if (MESON_PARM_APPLICABLE(&pll->frac)) {
439 frac = __pll_params_with_frac(rate, parent_rate, m, n, pll);
440 meson_parm_write(clk->map, &pll->frac, frac);
441 }
442
443 /* If the pll is stopped, bail out now */
444 if (!enabled)
445 return 0;
446
447 ret = meson_clk_pll_enable(hw);
448 if (ret) {
449 pr_warn("%s: pll %s didn't lock, trying to set old rate %lu\n",
450 __func__, clk_hw_get_name(hw), old_rate);
451 /*
452 * FIXME: Do we really need/want this HACK ?
453 * It looks unsafe. what happens if the clock gets into a
454 * broken state and we can't lock back on the old_rate ? Looks
455 * like an infinite recursion is possible
456 */
457 meson_clk_pll_set_rate(hw, old_rate, parent_rate);
458 }
459
460 return ret;
461 }
462
463 /*
464 * The Meson G12A PCIE PLL is fined tuned to deliver a very precise
465 * 100MHz reference clock for the PCIe Analog PHY, and thus requires
466 * a strict register sequence to enable the PLL.
467 * To simplify, re-use the _init() op to enable the PLL and keep
468 * the other ops except set_rate since the rate is fixed.
469 */
470 const struct clk_ops meson_clk_pcie_pll_ops = {
471 .recalc_rate = meson_clk_pll_recalc_rate,
472 .determine_rate = meson_clk_pll_determine_rate,
473 .is_enabled = meson_clk_pll_is_enabled,
474 .enable = meson_clk_pcie_pll_enable,
475 .disable = meson_clk_pll_disable
476 };
477 EXPORT_SYMBOL_NS_GPL(meson_clk_pcie_pll_ops, "CLK_MESON");
478
479 const struct clk_ops meson_clk_pll_ops = {
480 .init = meson_clk_pll_init,
481 .recalc_rate = meson_clk_pll_recalc_rate,
482 .determine_rate = meson_clk_pll_determine_rate,
483 .set_rate = meson_clk_pll_set_rate,
484 .is_enabled = meson_clk_pll_is_enabled,
485 .enable = meson_clk_pll_enable,
486 .disable = meson_clk_pll_disable
487 };
488 EXPORT_SYMBOL_NS_GPL(meson_clk_pll_ops, "CLK_MESON");
489
490 const struct clk_ops meson_clk_pll_ro_ops = {
491 .recalc_rate = meson_clk_pll_recalc_rate,
492 .is_enabled = meson_clk_pll_is_enabled,
493 };
494 EXPORT_SYMBOL_NS_GPL(meson_clk_pll_ro_ops, "CLK_MESON");
495
496 MODULE_DESCRIPTION("Amlogic PLL driver");
497 MODULE_AUTHOR("Carlo Caione <carlo@endlessm.com>");
498 MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
499 MODULE_LICENSE("GPL");
500 MODULE_IMPORT_NS("CLK_MESON");
501