1 /*
2 * Copyright 2023 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <linux/firmware.h>
25 #include <linux/module.h>
26 #include "amdgpu.h"
27 #include "gfx_v12_0.h"
28 #include "soc15_common.h"
29 #include "soc21.h"
30 #include "gc/gc_12_0_0_offset.h"
31 #include "gc/gc_12_0_0_sh_mask.h"
32 #include "gc/gc_11_0_0_default.h"
33 #include "v12_structs.h"
34 #include "mes_v12_api_def.h"
35
36 MODULE_FIRMWARE("amdgpu/gc_12_0_0_mes.bin");
37 MODULE_FIRMWARE("amdgpu/gc_12_0_0_mes1.bin");
38 MODULE_FIRMWARE("amdgpu/gc_12_0_0_uni_mes.bin");
39 MODULE_FIRMWARE("amdgpu/gc_12_0_1_mes.bin");
40 MODULE_FIRMWARE("amdgpu/gc_12_0_1_mes1.bin");
41 MODULE_FIRMWARE("amdgpu/gc_12_0_1_uni_mes.bin");
42
43 static int mes_v12_0_hw_init(struct amdgpu_ip_block *ip_block);
44 static int mes_v12_0_hw_fini(struct amdgpu_ip_block *ip_block);
45 static int mes_v12_0_kiq_hw_init(struct amdgpu_device *adev);
46 static int mes_v12_0_kiq_hw_fini(struct amdgpu_device *adev);
47
48 #define MES_EOP_SIZE 2048
49
mes_v12_0_ring_set_wptr(struct amdgpu_ring * ring)50 static void mes_v12_0_ring_set_wptr(struct amdgpu_ring *ring)
51 {
52 struct amdgpu_device *adev = ring->adev;
53
54 if (ring->use_doorbell) {
55 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
56 ring->wptr);
57 WDOORBELL64(ring->doorbell_index, ring->wptr);
58 } else {
59 BUG();
60 }
61 }
62
mes_v12_0_ring_get_rptr(struct amdgpu_ring * ring)63 static u64 mes_v12_0_ring_get_rptr(struct amdgpu_ring *ring)
64 {
65 return *ring->rptr_cpu_addr;
66 }
67
mes_v12_0_ring_get_wptr(struct amdgpu_ring * ring)68 static u64 mes_v12_0_ring_get_wptr(struct amdgpu_ring *ring)
69 {
70 u64 wptr;
71
72 if (ring->use_doorbell)
73 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
74 else
75 BUG();
76 return wptr;
77 }
78
79 static const struct amdgpu_ring_funcs mes_v12_0_ring_funcs = {
80 .type = AMDGPU_RING_TYPE_MES,
81 .align_mask = 1,
82 .nop = 0,
83 .support_64bit_ptrs = true,
84 .get_rptr = mes_v12_0_ring_get_rptr,
85 .get_wptr = mes_v12_0_ring_get_wptr,
86 .set_wptr = mes_v12_0_ring_set_wptr,
87 .insert_nop = amdgpu_ring_insert_nop,
88 };
89
90 static const char *mes_v12_0_opcodes[] = {
91 "SET_HW_RSRC",
92 "SET_SCHEDULING_CONFIG",
93 "ADD_QUEUE",
94 "REMOVE_QUEUE",
95 "PERFORM_YIELD",
96 "SET_GANG_PRIORITY_LEVEL",
97 "SUSPEND",
98 "RESUME",
99 "RESET",
100 "SET_LOG_BUFFER",
101 "CHANGE_GANG_PRORITY",
102 "QUERY_SCHEDULER_STATUS",
103 "unused",
104 "SET_DEBUG_VMID",
105 "MISC",
106 "UPDATE_ROOT_PAGE_TABLE",
107 "AMD_LOG",
108 "SET_SE_MODE",
109 "SET_GANG_SUBMIT",
110 "SET_HW_RSRC_1",
111 };
112
113 static const char *mes_v12_0_misc_opcodes[] = {
114 "WRITE_REG",
115 "INV_GART",
116 "QUERY_STATUS",
117 "READ_REG",
118 "WAIT_REG_MEM",
119 "SET_SHADER_DEBUGGER",
120 "NOTIFY_WORK_ON_UNMAPPED_QUEUE",
121 "NOTIFY_TO_UNMAP_PROCESSES",
122 };
123
mes_v12_0_get_op_string(union MESAPI__MISC * x_pkt)124 static const char *mes_v12_0_get_op_string(union MESAPI__MISC *x_pkt)
125 {
126 const char *op_str = NULL;
127
128 if (x_pkt->header.opcode < ARRAY_SIZE(mes_v12_0_opcodes))
129 op_str = mes_v12_0_opcodes[x_pkt->header.opcode];
130
131 return op_str;
132 }
133
mes_v12_0_get_misc_op_string(union MESAPI__MISC * x_pkt)134 static const char *mes_v12_0_get_misc_op_string(union MESAPI__MISC *x_pkt)
135 {
136 const char *op_str = NULL;
137
138 if ((x_pkt->header.opcode == MES_SCH_API_MISC) &&
139 (x_pkt->opcode < ARRAY_SIZE(mes_v12_0_misc_opcodes)))
140 op_str = mes_v12_0_misc_opcodes[x_pkt->opcode];
141
142 return op_str;
143 }
144
mes_v12_0_submit_pkt_and_poll_completion(struct amdgpu_mes * mes,int pipe,void * pkt,int size,int api_status_off)145 static int mes_v12_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes,
146 int pipe, void *pkt, int size,
147 int api_status_off)
148 {
149 union MESAPI__QUERY_MES_STATUS mes_status_pkt;
150 signed long timeout = 2100000; /* 2100 ms */
151 struct amdgpu_device *adev = mes->adev;
152 struct amdgpu_ring *ring = &mes->ring[pipe];
153 spinlock_t *ring_lock = &mes->ring_lock[pipe];
154 struct MES_API_STATUS *api_status;
155 union MESAPI__MISC *x_pkt = pkt;
156 const char *op_str, *misc_op_str;
157 unsigned long flags;
158 u64 status_gpu_addr;
159 u32 seq, status_offset;
160 u64 *status_ptr;
161 signed long r;
162 int ret;
163
164 if (x_pkt->header.opcode >= MES_SCH_API_MAX)
165 return -EINVAL;
166
167 if (amdgpu_emu_mode) {
168 timeout *= 100;
169 } else if (amdgpu_sriov_vf(adev)) {
170 /* Worst case in sriov where all other 15 VF timeout, each VF needs about 600ms */
171 timeout = 15 * 600 * 1000;
172 }
173
174 ret = amdgpu_device_wb_get(adev, &status_offset);
175 if (ret)
176 return ret;
177
178 status_gpu_addr = adev->wb.gpu_addr + (status_offset * 4);
179 status_ptr = (u64 *)&adev->wb.wb[status_offset];
180 *status_ptr = 0;
181
182 spin_lock_irqsave(ring_lock, flags);
183 r = amdgpu_ring_alloc(ring, (size + sizeof(mes_status_pkt)) / 4);
184 if (r)
185 goto error_unlock_free;
186
187 seq = ++ring->fence_drv.sync_seq;
188 r = amdgpu_fence_wait_polling(ring,
189 seq - ring->fence_drv.num_fences_mask,
190 timeout);
191 if (r < 1)
192 goto error_undo;
193
194 api_status = (struct MES_API_STATUS *)((char *)pkt + api_status_off);
195 api_status->api_completion_fence_addr = status_gpu_addr;
196 api_status->api_completion_fence_value = 1;
197
198 amdgpu_ring_write_multiple(ring, pkt, size / 4);
199
200 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt));
201 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER;
202 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS;
203 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
204 mes_status_pkt.api_status.api_completion_fence_addr =
205 ring->fence_drv.gpu_addr;
206 mes_status_pkt.api_status.api_completion_fence_value = seq;
207
208 amdgpu_ring_write_multiple(ring, &mes_status_pkt,
209 sizeof(mes_status_pkt) / 4);
210
211 amdgpu_ring_commit(ring);
212 spin_unlock_irqrestore(ring_lock, flags);
213
214 op_str = mes_v12_0_get_op_string(x_pkt);
215 misc_op_str = mes_v12_0_get_misc_op_string(x_pkt);
216
217 if (misc_op_str)
218 dev_dbg(adev->dev, "MES(%d) msg=%s (%s) was emitted\n",
219 pipe, op_str, misc_op_str);
220 else if (op_str)
221 dev_dbg(adev->dev, "MES(%d) msg=%s was emitted\n",
222 pipe, op_str);
223 else
224 dev_dbg(adev->dev, "MES(%d) msg=%d was emitted\n",
225 pipe, x_pkt->header.opcode);
226
227 r = amdgpu_fence_wait_polling(ring, seq, timeout);
228 if (r < 1 || !*status_ptr) {
229
230 if (misc_op_str)
231 dev_err(adev->dev, "MES(%d) failed to respond to msg=%s (%s)\n",
232 pipe, op_str, misc_op_str);
233 else if (op_str)
234 dev_err(adev->dev, "MES(%d) failed to respond to msg=%s\n",
235 pipe, op_str);
236 else
237 dev_err(adev->dev, "MES(%d) failed to respond to msg=%d\n",
238 pipe, x_pkt->header.opcode);
239
240 while (halt_if_hws_hang)
241 schedule();
242
243 r = -ETIMEDOUT;
244 goto error_wb_free;
245 }
246
247 amdgpu_device_wb_free(adev, status_offset);
248 return 0;
249
250 error_undo:
251 dev_err(adev->dev, "MES ring buffer is full.\n");
252 amdgpu_ring_undo(ring);
253
254 error_unlock_free:
255 spin_unlock_irqrestore(ring_lock, flags);
256
257 error_wb_free:
258 amdgpu_device_wb_free(adev, status_offset);
259 return r;
260 }
261
convert_to_mes_queue_type(int queue_type)262 static int convert_to_mes_queue_type(int queue_type)
263 {
264 if (queue_type == AMDGPU_RING_TYPE_GFX)
265 return MES_QUEUE_TYPE_GFX;
266 else if (queue_type == AMDGPU_RING_TYPE_COMPUTE)
267 return MES_QUEUE_TYPE_COMPUTE;
268 else if (queue_type == AMDGPU_RING_TYPE_SDMA)
269 return MES_QUEUE_TYPE_SDMA;
270 else if (queue_type == AMDGPU_RING_TYPE_MES)
271 return MES_QUEUE_TYPE_SCHQ;
272 else
273 BUG();
274 return -1;
275 }
276
mes_v12_0_add_hw_queue(struct amdgpu_mes * mes,struct mes_add_queue_input * input)277 static int mes_v12_0_add_hw_queue(struct amdgpu_mes *mes,
278 struct mes_add_queue_input *input)
279 {
280 struct amdgpu_device *adev = mes->adev;
281 union MESAPI__ADD_QUEUE mes_add_queue_pkt;
282 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)];
283 uint32_t vm_cntx_cntl = hub->vm_cntx_cntl;
284
285 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt));
286
287 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;
288 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE;
289 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
290
291 mes_add_queue_pkt.process_id = input->process_id;
292 mes_add_queue_pkt.page_table_base_addr = input->page_table_base_addr;
293 mes_add_queue_pkt.process_va_start = input->process_va_start;
294 mes_add_queue_pkt.process_va_end = input->process_va_end;
295 mes_add_queue_pkt.process_quantum = input->process_quantum;
296 mes_add_queue_pkt.process_context_addr = input->process_context_addr;
297 mes_add_queue_pkt.gang_quantum = input->gang_quantum;
298 mes_add_queue_pkt.gang_context_addr = input->gang_context_addr;
299 mes_add_queue_pkt.inprocess_gang_priority =
300 input->inprocess_gang_priority;
301 mes_add_queue_pkt.gang_global_priority_level =
302 input->gang_global_priority_level;
303 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset;
304 mes_add_queue_pkt.mqd_addr = input->mqd_addr;
305
306 mes_add_queue_pkt.wptr_addr = input->wptr_mc_addr;
307
308 mes_add_queue_pkt.queue_type =
309 convert_to_mes_queue_type(input->queue_type);
310 mes_add_queue_pkt.paging = input->paging;
311 mes_add_queue_pkt.vm_context_cntl = vm_cntx_cntl;
312 mes_add_queue_pkt.gws_base = input->gws_base;
313 mes_add_queue_pkt.gws_size = input->gws_size;
314 mes_add_queue_pkt.trap_handler_addr = input->tba_addr;
315 mes_add_queue_pkt.tma_addr = input->tma_addr;
316 mes_add_queue_pkt.trap_en = input->trap_en;
317 mes_add_queue_pkt.skip_process_ctx_clear = input->skip_process_ctx_clear;
318 mes_add_queue_pkt.is_kfd_process = input->is_kfd_process;
319
320 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */
321 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue;
322 mes_add_queue_pkt.gds_size = input->queue_size;
323
324 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */
325 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue;
326 mes_add_queue_pkt.gds_size = input->queue_size;
327
328 return mes_v12_0_submit_pkt_and_poll_completion(mes,
329 AMDGPU_MES_SCHED_PIPE,
330 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt),
331 offsetof(union MESAPI__ADD_QUEUE, api_status));
332 }
333
mes_v12_0_remove_hw_queue(struct amdgpu_mes * mes,struct mes_remove_queue_input * input)334 static int mes_v12_0_remove_hw_queue(struct amdgpu_mes *mes,
335 struct mes_remove_queue_input *input)
336 {
337 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt;
338
339 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt));
340
341 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;
342 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE;
343 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
344
345 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset;
346 mes_remove_queue_pkt.gang_context_addr = input->gang_context_addr;
347
348 return mes_v12_0_submit_pkt_and_poll_completion(mes,
349 AMDGPU_MES_SCHED_PIPE,
350 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt),
351 offsetof(union MESAPI__REMOVE_QUEUE, api_status));
352 }
353
gfx_v12_0_request_gfx_index_mutex(struct amdgpu_device * adev,bool req)354 int gfx_v12_0_request_gfx_index_mutex(struct amdgpu_device *adev,
355 bool req)
356 {
357 u32 i, tmp, val;
358
359 for (i = 0; i < adev->usec_timeout; i++) {
360 /* Request with MeId=2, PipeId=0 */
361 tmp = REG_SET_FIELD(0, CP_GFX_INDEX_MUTEX, REQUEST, req);
362 tmp = REG_SET_FIELD(tmp, CP_GFX_INDEX_MUTEX, CLIENTID, 4);
363 WREG32_SOC15(GC, 0, regCP_GFX_INDEX_MUTEX, tmp);
364
365 val = RREG32_SOC15(GC, 0, regCP_GFX_INDEX_MUTEX);
366 if (req) {
367 if (val == tmp)
368 break;
369 } else {
370 tmp = REG_SET_FIELD(tmp, CP_GFX_INDEX_MUTEX,
371 REQUEST, 1);
372
373 /* unlocked or locked by firmware */
374 if (val != tmp)
375 break;
376 }
377 udelay(1);
378 }
379
380 if (i >= adev->usec_timeout)
381 return -EINVAL;
382
383 return 0;
384 }
385
mes_v12_0_reset_queue_mmio(struct amdgpu_mes * mes,uint32_t queue_type,uint32_t me_id,uint32_t pipe_id,uint32_t queue_id,uint32_t vmid)386 static int mes_v12_0_reset_queue_mmio(struct amdgpu_mes *mes, uint32_t queue_type,
387 uint32_t me_id, uint32_t pipe_id,
388 uint32_t queue_id, uint32_t vmid)
389 {
390 struct amdgpu_device *adev = mes->adev;
391 uint32_t value, reg;
392 int i, r = 0;
393
394 amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
395
396 if (queue_type == AMDGPU_RING_TYPE_GFX) {
397 dev_info(adev->dev, "reset gfx queue (%d:%d:%d: vmid:%d)\n",
398 me_id, pipe_id, queue_id, vmid);
399
400 mutex_lock(&adev->gfx.reset_sem_mutex);
401 gfx_v12_0_request_gfx_index_mutex(adev, true);
402 /* all se allow writes */
403 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX,
404 (uint32_t)(0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT));
405 value = REG_SET_FIELD(0, CP_VMID_RESET, RESET_REQUEST, 1 << vmid);
406 if (pipe_id == 0)
407 value = REG_SET_FIELD(value, CP_VMID_RESET, PIPE0_QUEUES, 1 << queue_id);
408 else
409 value = REG_SET_FIELD(value, CP_VMID_RESET, PIPE1_QUEUES, 1 << queue_id);
410 WREG32_SOC15(GC, 0, regCP_VMID_RESET, value);
411 gfx_v12_0_request_gfx_index_mutex(adev, false);
412 mutex_unlock(&adev->gfx.reset_sem_mutex);
413
414 mutex_lock(&adev->srbm_mutex);
415 soc21_grbm_select(adev, me_id, pipe_id, queue_id, 0);
416 /* wait till dequeue take effects */
417 for (i = 0; i < adev->usec_timeout; i++) {
418 if (!(RREG32_SOC15(GC, 0, regCP_GFX_HQD_ACTIVE) & 1))
419 break;
420 udelay(1);
421 }
422 if (i >= adev->usec_timeout) {
423 dev_err(adev->dev, "failed to wait on gfx hqd deactivate\n");
424 r = -ETIMEDOUT;
425 }
426
427 soc21_grbm_select(adev, 0, 0, 0, 0);
428 mutex_unlock(&adev->srbm_mutex);
429 } else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) {
430 dev_info(adev->dev, "reset compute queue (%d:%d:%d)\n",
431 me_id, pipe_id, queue_id);
432 mutex_lock(&adev->srbm_mutex);
433 soc21_grbm_select(adev, me_id, pipe_id, queue_id, 0);
434 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0x2);
435 WREG32_SOC15(GC, 0, regSPI_COMPUTE_QUEUE_RESET, 0x1);
436
437 /* wait till dequeue take effects */
438 for (i = 0; i < adev->usec_timeout; i++) {
439 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1))
440 break;
441 udelay(1);
442 }
443 if (i >= adev->usec_timeout) {
444 dev_err(adev->dev, "failed to wait on hqd deactivate\n");
445 r = -ETIMEDOUT;
446 }
447 soc21_grbm_select(adev, 0, 0, 0, 0);
448 mutex_unlock(&adev->srbm_mutex);
449 } else if (queue_type == AMDGPU_RING_TYPE_SDMA) {
450 dev_info(adev->dev, "reset sdma queue (%d:%d:%d)\n",
451 me_id, pipe_id, queue_id);
452 switch (me_id) {
453 case 1:
454 reg = SOC15_REG_OFFSET(GC, 0, regSDMA1_QUEUE_RESET_REQ);
455 break;
456 case 0:
457 default:
458 reg = SOC15_REG_OFFSET(GC, 0, regSDMA0_QUEUE_RESET_REQ);
459 break;
460 }
461
462 value = 1 << queue_id;
463 WREG32(reg, value);
464 /* wait for queue reset done */
465 for (i = 0; i < adev->usec_timeout; i++) {
466 if (!(RREG32(reg) & value))
467 break;
468 udelay(1);
469 }
470 if (i >= adev->usec_timeout) {
471 dev_err(adev->dev, "failed to wait on sdma queue reset done\n");
472 r = -ETIMEDOUT;
473 }
474 }
475
476 amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
477 return r;
478 }
479
mes_v12_0_reset_hw_queue(struct amdgpu_mes * mes,struct mes_reset_queue_input * input)480 static int mes_v12_0_reset_hw_queue(struct amdgpu_mes *mes,
481 struct mes_reset_queue_input *input)
482 {
483 union MESAPI__RESET mes_reset_queue_pkt;
484 int pipe;
485
486 memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt));
487
488 mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;
489 mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET;
490 mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
491
492 mes_reset_queue_pkt.doorbell_offset = input->doorbell_offset;
493 mes_reset_queue_pkt.gang_context_addr = input->gang_context_addr;
494 /*mes_reset_queue_pkt.reset_queue_only = 1;*/
495
496 if (mes->adev->enable_uni_mes)
497 pipe = AMDGPU_MES_KIQ_PIPE;
498 else
499 pipe = AMDGPU_MES_SCHED_PIPE;
500
501 return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe,
502 &mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt),
503 offsetof(union MESAPI__REMOVE_QUEUE, api_status));
504 }
505
mes_v12_0_map_legacy_queue(struct amdgpu_mes * mes,struct mes_map_legacy_queue_input * input)506 static int mes_v12_0_map_legacy_queue(struct amdgpu_mes *mes,
507 struct mes_map_legacy_queue_input *input)
508 {
509 union MESAPI__ADD_QUEUE mes_add_queue_pkt;
510 int pipe;
511
512 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt));
513
514 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;
515 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE;
516 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
517
518 mes_add_queue_pkt.pipe_id = input->pipe_id;
519 mes_add_queue_pkt.queue_id = input->queue_id;
520 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset;
521 mes_add_queue_pkt.mqd_addr = input->mqd_addr;
522 mes_add_queue_pkt.wptr_addr = input->wptr_addr;
523 mes_add_queue_pkt.queue_type =
524 convert_to_mes_queue_type(input->queue_type);
525 mes_add_queue_pkt.map_legacy_kq = 1;
526
527 if (mes->adev->enable_uni_mes)
528 pipe = AMDGPU_MES_KIQ_PIPE;
529 else
530 pipe = AMDGPU_MES_SCHED_PIPE;
531
532 return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe,
533 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt),
534 offsetof(union MESAPI__ADD_QUEUE, api_status));
535 }
536
mes_v12_0_unmap_legacy_queue(struct amdgpu_mes * mes,struct mes_unmap_legacy_queue_input * input)537 static int mes_v12_0_unmap_legacy_queue(struct amdgpu_mes *mes,
538 struct mes_unmap_legacy_queue_input *input)
539 {
540 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt;
541 int pipe;
542
543 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt));
544
545 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;
546 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE;
547 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
548
549 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset;
550 mes_remove_queue_pkt.gang_context_addr = 0;
551
552 mes_remove_queue_pkt.pipe_id = input->pipe_id;
553 mes_remove_queue_pkt.queue_id = input->queue_id;
554
555 if (input->action == PREEMPT_QUEUES_NO_UNMAP) {
556 mes_remove_queue_pkt.preempt_legacy_gfx_queue = 1;
557 mes_remove_queue_pkt.tf_addr = input->trail_fence_addr;
558 mes_remove_queue_pkt.tf_data =
559 lower_32_bits(input->trail_fence_data);
560 } else {
561 mes_remove_queue_pkt.unmap_legacy_queue = 1;
562 mes_remove_queue_pkt.queue_type =
563 convert_to_mes_queue_type(input->queue_type);
564 }
565
566 if (mes->adev->enable_uni_mes)
567 pipe = AMDGPU_MES_KIQ_PIPE;
568 else
569 pipe = AMDGPU_MES_SCHED_PIPE;
570
571 return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe,
572 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt),
573 offsetof(union MESAPI__REMOVE_QUEUE, api_status));
574 }
575
mes_v12_0_suspend_gang(struct amdgpu_mes * mes,struct mes_suspend_gang_input * input)576 static int mes_v12_0_suspend_gang(struct amdgpu_mes *mes,
577 struct mes_suspend_gang_input *input)
578 {
579 return 0;
580 }
581
mes_v12_0_resume_gang(struct amdgpu_mes * mes,struct mes_resume_gang_input * input)582 static int mes_v12_0_resume_gang(struct amdgpu_mes *mes,
583 struct mes_resume_gang_input *input)
584 {
585 return 0;
586 }
587
mes_v12_0_query_sched_status(struct amdgpu_mes * mes,int pipe)588 static int mes_v12_0_query_sched_status(struct amdgpu_mes *mes, int pipe)
589 {
590 union MESAPI__QUERY_MES_STATUS mes_status_pkt;
591
592 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt));
593
594 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER;
595 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS;
596 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
597
598 return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe,
599 &mes_status_pkt, sizeof(mes_status_pkt),
600 offsetof(union MESAPI__QUERY_MES_STATUS, api_status));
601 }
602
mes_v12_0_misc_op(struct amdgpu_mes * mes,struct mes_misc_op_input * input)603 static int mes_v12_0_misc_op(struct amdgpu_mes *mes,
604 struct mes_misc_op_input *input)
605 {
606 union MESAPI__MISC misc_pkt;
607 int pipe;
608
609 if (mes->adev->enable_uni_mes)
610 pipe = AMDGPU_MES_KIQ_PIPE;
611 else
612 pipe = AMDGPU_MES_SCHED_PIPE;
613
614 memset(&misc_pkt, 0, sizeof(misc_pkt));
615
616 misc_pkt.header.type = MES_API_TYPE_SCHEDULER;
617 misc_pkt.header.opcode = MES_SCH_API_MISC;
618 misc_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
619
620 switch (input->op) {
621 case MES_MISC_OP_READ_REG:
622 misc_pkt.opcode = MESAPI_MISC__READ_REG;
623 misc_pkt.read_reg.reg_offset = input->read_reg.reg_offset;
624 misc_pkt.read_reg.buffer_addr = input->read_reg.buffer_addr;
625 break;
626 case MES_MISC_OP_WRITE_REG:
627 misc_pkt.opcode = MESAPI_MISC__WRITE_REG;
628 misc_pkt.write_reg.reg_offset = input->write_reg.reg_offset;
629 misc_pkt.write_reg.reg_value = input->write_reg.reg_value;
630 break;
631 case MES_MISC_OP_WRM_REG_WAIT:
632 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM;
633 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WAIT_REG_MEM;
634 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref;
635 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask;
636 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0;
637 misc_pkt.wait_reg_mem.reg_offset2 = 0;
638 break;
639 case MES_MISC_OP_WRM_REG_WR_WAIT:
640 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM;
641 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WR_WAIT_WR_REG;
642 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref;
643 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask;
644 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0;
645 misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1;
646 break;
647 case MES_MISC_OP_SET_SHADER_DEBUGGER:
648 pipe = AMDGPU_MES_SCHED_PIPE;
649 misc_pkt.opcode = MESAPI_MISC__SET_SHADER_DEBUGGER;
650 misc_pkt.set_shader_debugger.process_context_addr =
651 input->set_shader_debugger.process_context_addr;
652 misc_pkt.set_shader_debugger.flags.u32all =
653 input->set_shader_debugger.flags.u32all;
654 misc_pkt.set_shader_debugger.spi_gdbg_per_vmid_cntl =
655 input->set_shader_debugger.spi_gdbg_per_vmid_cntl;
656 memcpy(misc_pkt.set_shader_debugger.tcp_watch_cntl,
657 input->set_shader_debugger.tcp_watch_cntl,
658 sizeof(misc_pkt.set_shader_debugger.tcp_watch_cntl));
659 misc_pkt.set_shader_debugger.trap_en = input->set_shader_debugger.trap_en;
660 break;
661 case MES_MISC_OP_CHANGE_CONFIG:
662 misc_pkt.opcode = MESAPI_MISC__CHANGE_CONFIG;
663 misc_pkt.change_config.opcode =
664 MESAPI_MISC__CHANGE_CONFIG_OPTION_LIMIT_SINGLE_PROCESS;
665 misc_pkt.change_config.option.bits.limit_single_process =
666 input->change_config.option.limit_single_process;
667 break;
668
669 default:
670 DRM_ERROR("unsupported misc op (%d) \n", input->op);
671 return -EINVAL;
672 }
673
674 return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe,
675 &misc_pkt, sizeof(misc_pkt),
676 offsetof(union MESAPI__MISC, api_status));
677 }
678
mes_v12_0_set_hw_resources_1(struct amdgpu_mes * mes,int pipe)679 static int mes_v12_0_set_hw_resources_1(struct amdgpu_mes *mes, int pipe)
680 {
681 union MESAPI_SET_HW_RESOURCES_1 mes_set_hw_res_1_pkt;
682
683 memset(&mes_set_hw_res_1_pkt, 0, sizeof(mes_set_hw_res_1_pkt));
684
685 mes_set_hw_res_1_pkt.header.type = MES_API_TYPE_SCHEDULER;
686 mes_set_hw_res_1_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC_1;
687 mes_set_hw_res_1_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
688 mes_set_hw_res_1_pkt.mes_kiq_unmap_timeout = 0xa;
689 mes_set_hw_res_1_pkt.cleaner_shader_fence_mc_addr =
690 mes->resource_1_gpu_addr[pipe];
691
692 return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe,
693 &mes_set_hw_res_1_pkt, sizeof(mes_set_hw_res_1_pkt),
694 offsetof(union MESAPI_SET_HW_RESOURCES_1, api_status));
695 }
696
mes_v12_0_set_hw_resources(struct amdgpu_mes * mes,int pipe)697 static int mes_v12_0_set_hw_resources(struct amdgpu_mes *mes, int pipe)
698 {
699 int i;
700 struct amdgpu_device *adev = mes->adev;
701 union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt;
702
703 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt));
704
705 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER;
706 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC;
707 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
708
709 if (pipe == AMDGPU_MES_SCHED_PIPE) {
710 mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub;
711 mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub;
712 mes_set_hw_res_pkt.gds_size = adev->gds.gds_size;
713 mes_set_hw_res_pkt.paging_vmid = 0;
714
715 for (i = 0; i < MAX_COMPUTE_PIPES; i++)
716 mes_set_hw_res_pkt.compute_hqd_mask[i] =
717 mes->compute_hqd_mask[i];
718
719 for (i = 0; i < MAX_GFX_PIPES; i++)
720 mes_set_hw_res_pkt.gfx_hqd_mask[i] =
721 mes->gfx_hqd_mask[i];
722
723 for (i = 0; i < MAX_SDMA_PIPES; i++)
724 mes_set_hw_res_pkt.sdma_hqd_mask[i] =
725 mes->sdma_hqd_mask[i];
726
727 for (i = 0; i < AMD_PRIORITY_NUM_LEVELS; i++)
728 mes_set_hw_res_pkt.aggregated_doorbells[i] =
729 mes->aggregated_doorbells[i];
730 }
731
732 mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr =
733 mes->sch_ctx_gpu_addr[pipe];
734 mes_set_hw_res_pkt.query_status_fence_gpu_mc_ptr =
735 mes->query_status_fence_gpu_addr[pipe];
736
737 for (i = 0; i < 5; i++) {
738 mes_set_hw_res_pkt.gc_base[i] = adev->reg_offset[GC_HWIP][0][i];
739 mes_set_hw_res_pkt.mmhub_base[i] =
740 adev->reg_offset[MMHUB_HWIP][0][i];
741 mes_set_hw_res_pkt.osssys_base[i] =
742 adev->reg_offset[OSSSYS_HWIP][0][i];
743 }
744
745 mes_set_hw_res_pkt.disable_reset = 1;
746 mes_set_hw_res_pkt.disable_mes_log = 1;
747 mes_set_hw_res_pkt.use_different_vmid_compute = 1;
748 mes_set_hw_res_pkt.enable_reg_active_poll = 1;
749 mes_set_hw_res_pkt.enable_level_process_quantum_check = 1;
750
751 /*
752 * Keep oversubscribe timer for sdma . When we have unmapped doorbell
753 * handling support, other queue will not use the oversubscribe timer.
754 * handling mode - 0: disabled; 1: basic version; 2: basic+ version
755 */
756 mes_set_hw_res_pkt.oversubscription_timer = 50;
757 mes_set_hw_res_pkt.unmapped_doorbell_handling = 1;
758
759 if (amdgpu_mes_log_enable) {
760 mes_set_hw_res_pkt.enable_mes_event_int_logging = 1;
761 mes_set_hw_res_pkt.event_intr_history_gpu_mc_ptr = mes->event_log_gpu_addr +
762 pipe * (AMDGPU_MES_LOG_BUFFER_SIZE + AMDGPU_MES_MSCRATCH_SIZE);
763 }
764
765 if (enforce_isolation)
766 mes_set_hw_res_pkt.limit_single_process = 1;
767
768 return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe,
769 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt),
770 offsetof(union MESAPI_SET_HW_RESOURCES, api_status));
771 }
772
mes_v12_0_init_aggregated_doorbell(struct amdgpu_mes * mes)773 static void mes_v12_0_init_aggregated_doorbell(struct amdgpu_mes *mes)
774 {
775 struct amdgpu_device *adev = mes->adev;
776 uint32_t data;
777
778 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL1);
779 data &= ~(CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET_MASK |
780 CP_MES_DOORBELL_CONTROL1__DOORBELL_EN_MASK |
781 CP_MES_DOORBELL_CONTROL1__DOORBELL_HIT_MASK);
782 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_LOW] <<
783 CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET__SHIFT;
784 data |= 1 << CP_MES_DOORBELL_CONTROL1__DOORBELL_EN__SHIFT;
785 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL1, data);
786
787 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL2);
788 data &= ~(CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET_MASK |
789 CP_MES_DOORBELL_CONTROL2__DOORBELL_EN_MASK |
790 CP_MES_DOORBELL_CONTROL2__DOORBELL_HIT_MASK);
791 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_NORMAL] <<
792 CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET__SHIFT;
793 data |= 1 << CP_MES_DOORBELL_CONTROL2__DOORBELL_EN__SHIFT;
794 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL2, data);
795
796 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL3);
797 data &= ~(CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET_MASK |
798 CP_MES_DOORBELL_CONTROL3__DOORBELL_EN_MASK |
799 CP_MES_DOORBELL_CONTROL3__DOORBELL_HIT_MASK);
800 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_MEDIUM] <<
801 CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET__SHIFT;
802 data |= 1 << CP_MES_DOORBELL_CONTROL3__DOORBELL_EN__SHIFT;
803 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL3, data);
804
805 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL4);
806 data &= ~(CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET_MASK |
807 CP_MES_DOORBELL_CONTROL4__DOORBELL_EN_MASK |
808 CP_MES_DOORBELL_CONTROL4__DOORBELL_HIT_MASK);
809 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_HIGH] <<
810 CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET__SHIFT;
811 data |= 1 << CP_MES_DOORBELL_CONTROL4__DOORBELL_EN__SHIFT;
812 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL4, data);
813
814 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL5);
815 data &= ~(CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET_MASK |
816 CP_MES_DOORBELL_CONTROL5__DOORBELL_EN_MASK |
817 CP_MES_DOORBELL_CONTROL5__DOORBELL_HIT_MASK);
818 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_REALTIME] <<
819 CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET__SHIFT;
820 data |= 1 << CP_MES_DOORBELL_CONTROL5__DOORBELL_EN__SHIFT;
821 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL5, data);
822
823 data = 1 << CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN__SHIFT;
824 WREG32_SOC15(GC, 0, regCP_HQD_GFX_CONTROL, data);
825 }
826
827
mes_v12_0_enable_unmapped_doorbell_handling(struct amdgpu_mes * mes,bool enable)828 static void mes_v12_0_enable_unmapped_doorbell_handling(
829 struct amdgpu_mes *mes, bool enable)
830 {
831 struct amdgpu_device *adev = mes->adev;
832 uint32_t data = RREG32_SOC15(GC, 0, regCP_UNMAPPED_DOORBELL);
833
834 /*
835 * The default PROC_LSB settng is 0xc which means doorbell
836 * addr[16:12] gives the doorbell page number. For kfd, each
837 * process will use 2 pages of doorbell, we need to change the
838 * setting to 0xd
839 */
840 data &= ~CP_UNMAPPED_DOORBELL__PROC_LSB_MASK;
841 data |= 0xd << CP_UNMAPPED_DOORBELL__PROC_LSB__SHIFT;
842
843 data |= (enable ? 1 : 0) << CP_UNMAPPED_DOORBELL__ENABLE__SHIFT;
844
845 WREG32_SOC15(GC, 0, regCP_UNMAPPED_DOORBELL, data);
846 }
847
mes_v12_0_reset_legacy_queue(struct amdgpu_mes * mes,struct mes_reset_legacy_queue_input * input)848 static int mes_v12_0_reset_legacy_queue(struct amdgpu_mes *mes,
849 struct mes_reset_legacy_queue_input *input)
850 {
851 union MESAPI__RESET mes_reset_queue_pkt;
852 int pipe;
853
854 if (input->use_mmio)
855 return mes_v12_0_reset_queue_mmio(mes, input->queue_type,
856 input->me_id, input->pipe_id,
857 input->queue_id, input->vmid);
858
859 memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt));
860
861 mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;
862 mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET;
863 mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
864
865 mes_reset_queue_pkt.queue_type =
866 convert_to_mes_queue_type(input->queue_type);
867
868 if (mes_reset_queue_pkt.queue_type == MES_QUEUE_TYPE_GFX) {
869 mes_reset_queue_pkt.reset_legacy_gfx = 1;
870 mes_reset_queue_pkt.pipe_id_lp = input->pipe_id;
871 mes_reset_queue_pkt.queue_id_lp = input->queue_id;
872 mes_reset_queue_pkt.mqd_mc_addr_lp = input->mqd_addr;
873 mes_reset_queue_pkt.doorbell_offset_lp = input->doorbell_offset;
874 mes_reset_queue_pkt.wptr_addr_lp = input->wptr_addr;
875 mes_reset_queue_pkt.vmid_id_lp = input->vmid;
876 } else {
877 mes_reset_queue_pkt.reset_queue_only = 1;
878 mes_reset_queue_pkt.doorbell_offset = input->doorbell_offset;
879 }
880
881 if (mes->adev->enable_uni_mes)
882 pipe = AMDGPU_MES_KIQ_PIPE;
883 else
884 pipe = AMDGPU_MES_SCHED_PIPE;
885
886 return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe,
887 &mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt),
888 offsetof(union MESAPI__RESET, api_status));
889 }
890
891 static const struct amdgpu_mes_funcs mes_v12_0_funcs = {
892 .add_hw_queue = mes_v12_0_add_hw_queue,
893 .remove_hw_queue = mes_v12_0_remove_hw_queue,
894 .map_legacy_queue = mes_v12_0_map_legacy_queue,
895 .unmap_legacy_queue = mes_v12_0_unmap_legacy_queue,
896 .suspend_gang = mes_v12_0_suspend_gang,
897 .resume_gang = mes_v12_0_resume_gang,
898 .misc_op = mes_v12_0_misc_op,
899 .reset_legacy_queue = mes_v12_0_reset_legacy_queue,
900 .reset_hw_queue = mes_v12_0_reset_hw_queue,
901 };
902
mes_v12_0_allocate_ucode_buffer(struct amdgpu_device * adev,enum amdgpu_mes_pipe pipe)903 static int mes_v12_0_allocate_ucode_buffer(struct amdgpu_device *adev,
904 enum amdgpu_mes_pipe pipe)
905 {
906 int r;
907 const struct mes_firmware_header_v1_0 *mes_hdr;
908 const __le32 *fw_data;
909 unsigned fw_size;
910
911 mes_hdr = (const struct mes_firmware_header_v1_0 *)
912 adev->mes.fw[pipe]->data;
913
914 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data +
915 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes));
916 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes);
917
918 r = amdgpu_bo_create_reserved(adev, fw_size,
919 PAGE_SIZE,
920 AMDGPU_GEM_DOMAIN_VRAM,
921 &adev->mes.ucode_fw_obj[pipe],
922 &adev->mes.ucode_fw_gpu_addr[pipe],
923 (void **)&adev->mes.ucode_fw_ptr[pipe]);
924 if (r) {
925 dev_err(adev->dev, "(%d) failed to create mes fw bo\n", r);
926 return r;
927 }
928
929 memcpy(adev->mes.ucode_fw_ptr[pipe], fw_data, fw_size);
930
931 amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[pipe]);
932 amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[pipe]);
933
934 return 0;
935 }
936
mes_v12_0_allocate_ucode_data_buffer(struct amdgpu_device * adev,enum amdgpu_mes_pipe pipe)937 static int mes_v12_0_allocate_ucode_data_buffer(struct amdgpu_device *adev,
938 enum amdgpu_mes_pipe pipe)
939 {
940 int r;
941 const struct mes_firmware_header_v1_0 *mes_hdr;
942 const __le32 *fw_data;
943 unsigned fw_size;
944
945 mes_hdr = (const struct mes_firmware_header_v1_0 *)
946 adev->mes.fw[pipe]->data;
947
948 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data +
949 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes));
950 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes);
951
952 r = amdgpu_bo_create_reserved(adev, fw_size,
953 64 * 1024,
954 AMDGPU_GEM_DOMAIN_VRAM,
955 &adev->mes.data_fw_obj[pipe],
956 &adev->mes.data_fw_gpu_addr[pipe],
957 (void **)&adev->mes.data_fw_ptr[pipe]);
958 if (r) {
959 dev_err(adev->dev, "(%d) failed to create mes data fw bo\n", r);
960 return r;
961 }
962
963 memcpy(adev->mes.data_fw_ptr[pipe], fw_data, fw_size);
964
965 amdgpu_bo_kunmap(adev->mes.data_fw_obj[pipe]);
966 amdgpu_bo_unreserve(adev->mes.data_fw_obj[pipe]);
967
968 return 0;
969 }
970
mes_v12_0_free_ucode_buffers(struct amdgpu_device * adev,enum amdgpu_mes_pipe pipe)971 static void mes_v12_0_free_ucode_buffers(struct amdgpu_device *adev,
972 enum amdgpu_mes_pipe pipe)
973 {
974 amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[pipe],
975 &adev->mes.data_fw_gpu_addr[pipe],
976 (void **)&adev->mes.data_fw_ptr[pipe]);
977
978 amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[pipe],
979 &adev->mes.ucode_fw_gpu_addr[pipe],
980 (void **)&adev->mes.ucode_fw_ptr[pipe]);
981 }
982
mes_v12_0_enable(struct amdgpu_device * adev,bool enable)983 static void mes_v12_0_enable(struct amdgpu_device *adev, bool enable)
984 {
985 uint64_t ucode_addr;
986 uint32_t pipe, data = 0;
987
988 if (enable) {
989 mutex_lock(&adev->srbm_mutex);
990 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
991 soc21_grbm_select(adev, 3, pipe, 0, 0);
992 if (amdgpu_mes_log_enable) {
993 u32 log_size = AMDGPU_MES_LOG_BUFFER_SIZE + AMDGPU_MES_MSCRATCH_SIZE;
994 /* In case uni mes is not enabled, only program for pipe 0 */
995 if (adev->mes.event_log_size >= (pipe + 1) * log_size) {
996 WREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_LO,
997 lower_32_bits(adev->mes.event_log_gpu_addr +
998 pipe * log_size + AMDGPU_MES_LOG_BUFFER_SIZE));
999 WREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_HI,
1000 upper_32_bits(adev->mes.event_log_gpu_addr +
1001 pipe * log_size + AMDGPU_MES_LOG_BUFFER_SIZE));
1002 dev_info(adev->dev, "Setup CP MES MSCRATCH address : 0x%x. 0x%x\n",
1003 RREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_HI),
1004 RREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_LO));
1005 }
1006 }
1007
1008 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL);
1009 if (pipe == 0)
1010 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1);
1011 else
1012 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 1);
1013 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data);
1014
1015 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2;
1016 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START,
1017 lower_32_bits(ucode_addr));
1018 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI,
1019 upper_32_bits(ucode_addr));
1020
1021 /* unhalt MES and activate one pipe each loop */
1022 data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1);
1023 if (pipe)
1024 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 1);
1025 dev_info(adev->dev, "program CP_MES_CNTL : 0x%x\n", data);
1026
1027 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data);
1028
1029 }
1030 soc21_grbm_select(adev, 0, 0, 0, 0);
1031 mutex_unlock(&adev->srbm_mutex);
1032
1033 if (amdgpu_emu_mode)
1034 msleep(100);
1035 else if (adev->enable_uni_mes)
1036 udelay(500);
1037 else
1038 udelay(50);
1039 } else {
1040 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL);
1041 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0);
1042 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 0);
1043 data = REG_SET_FIELD(data, CP_MES_CNTL,
1044 MES_INVALIDATE_ICACHE, 1);
1045 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1);
1046 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 1);
1047 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1);
1048 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data);
1049 }
1050 }
1051
mes_v12_0_set_ucode_start_addr(struct amdgpu_device * adev)1052 static void mes_v12_0_set_ucode_start_addr(struct amdgpu_device *adev)
1053 {
1054 uint64_t ucode_addr;
1055 int pipe;
1056
1057 mes_v12_0_enable(adev, false);
1058
1059 mutex_lock(&adev->srbm_mutex);
1060 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
1061 /* me=3, queue=0 */
1062 soc21_grbm_select(adev, 3, pipe, 0, 0);
1063
1064 /* set ucode start address */
1065 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2;
1066 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START,
1067 lower_32_bits(ucode_addr));
1068 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI,
1069 upper_32_bits(ucode_addr));
1070
1071 soc21_grbm_select(adev, 0, 0, 0, 0);
1072 }
1073 mutex_unlock(&adev->srbm_mutex);
1074 }
1075
1076 /* This function is for backdoor MES firmware */
mes_v12_0_load_microcode(struct amdgpu_device * adev,enum amdgpu_mes_pipe pipe,bool prime_icache)1077 static int mes_v12_0_load_microcode(struct amdgpu_device *adev,
1078 enum amdgpu_mes_pipe pipe, bool prime_icache)
1079 {
1080 int r;
1081 uint32_t data;
1082
1083 mes_v12_0_enable(adev, false);
1084
1085 if (!adev->mes.fw[pipe])
1086 return -EINVAL;
1087
1088 r = mes_v12_0_allocate_ucode_buffer(adev, pipe);
1089 if (r)
1090 return r;
1091
1092 r = mes_v12_0_allocate_ucode_data_buffer(adev, pipe);
1093 if (r) {
1094 mes_v12_0_free_ucode_buffers(adev, pipe);
1095 return r;
1096 }
1097
1098 mutex_lock(&adev->srbm_mutex);
1099 /* me=3, pipe=0, queue=0 */
1100 soc21_grbm_select(adev, 3, pipe, 0, 0);
1101
1102 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_CNTL, 0);
1103
1104 /* set ucode fimrware address */
1105 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_LO,
1106 lower_32_bits(adev->mes.ucode_fw_gpu_addr[pipe]));
1107 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_HI,
1108 upper_32_bits(adev->mes.ucode_fw_gpu_addr[pipe]));
1109
1110 /* set ucode instruction cache boundary to 2M-1 */
1111 WREG32_SOC15(GC, 0, regCP_MES_MIBOUND_LO, 0x1FFFFF);
1112
1113 /* set ucode data firmware address */
1114 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_LO,
1115 lower_32_bits(adev->mes.data_fw_gpu_addr[pipe]));
1116 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_HI,
1117 upper_32_bits(adev->mes.data_fw_gpu_addr[pipe]));
1118
1119 /* Set data cache boundary CP_MES_MDBOUND_LO */
1120 WREG32_SOC15(GC, 0, regCP_MES_MDBOUND_LO, 0x7FFFF);
1121
1122 if (prime_icache) {
1123 /* invalidate ICACHE */
1124 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL);
1125 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0);
1126 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1);
1127 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data);
1128
1129 /* prime the ICACHE. */
1130 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL);
1131 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1);
1132 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data);
1133 }
1134
1135 soc21_grbm_select(adev, 0, 0, 0, 0);
1136 mutex_unlock(&adev->srbm_mutex);
1137
1138 return 0;
1139 }
1140
mes_v12_0_allocate_eop_buf(struct amdgpu_device * adev,enum amdgpu_mes_pipe pipe)1141 static int mes_v12_0_allocate_eop_buf(struct amdgpu_device *adev,
1142 enum amdgpu_mes_pipe pipe)
1143 {
1144 int r;
1145 u32 *eop;
1146
1147 r = amdgpu_bo_create_reserved(adev, MES_EOP_SIZE, PAGE_SIZE,
1148 AMDGPU_GEM_DOMAIN_GTT,
1149 &adev->mes.eop_gpu_obj[pipe],
1150 &adev->mes.eop_gpu_addr[pipe],
1151 (void **)&eop);
1152 if (r) {
1153 dev_warn(adev->dev, "(%d) create EOP bo failed\n", r);
1154 return r;
1155 }
1156
1157 memset(eop, 0,
1158 adev->mes.eop_gpu_obj[pipe]->tbo.base.size);
1159
1160 amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[pipe]);
1161 amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[pipe]);
1162
1163 return 0;
1164 }
1165
mes_v12_0_mqd_init(struct amdgpu_ring * ring)1166 static int mes_v12_0_mqd_init(struct amdgpu_ring *ring)
1167 {
1168 struct v12_compute_mqd *mqd = ring->mqd_ptr;
1169 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
1170 uint32_t tmp;
1171
1172 mqd->header = 0xC0310800;
1173 mqd->compute_pipelinestat_enable = 0x00000001;
1174 mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
1175 mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
1176 mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
1177 mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
1178 mqd->compute_misc_reserved = 0x00000007;
1179
1180 eop_base_addr = ring->eop_gpu_addr >> 8;
1181
1182 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
1183 tmp = regCP_HQD_EOP_CONTROL_DEFAULT;
1184 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
1185 (order_base_2(MES_EOP_SIZE / 4) - 1));
1186
1187 mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr);
1188 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
1189 mqd->cp_hqd_eop_control = tmp;
1190
1191 /* disable the queue if it's active */
1192 ring->wptr = 0;
1193 mqd->cp_hqd_pq_rptr = 0;
1194 mqd->cp_hqd_pq_wptr_lo = 0;
1195 mqd->cp_hqd_pq_wptr_hi = 0;
1196
1197 /* set the pointer to the MQD */
1198 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
1199 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
1200
1201 /* set MQD vmid to 0 */
1202 tmp = regCP_MQD_CONTROL_DEFAULT;
1203 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
1204 mqd->cp_mqd_control = tmp;
1205
1206 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
1207 hqd_gpu_addr = ring->gpu_addr >> 8;
1208 mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr);
1209 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
1210
1211 /* set the wb address whether it's enabled or not */
1212 wb_gpu_addr = ring->rptr_gpu_addr;
1213 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
1214 mqd->cp_hqd_pq_rptr_report_addr_hi =
1215 upper_32_bits(wb_gpu_addr) & 0xffff;
1216
1217 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
1218 wb_gpu_addr = ring->wptr_gpu_addr;
1219 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8;
1220 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
1221
1222 /* set up the HQD, this is similar to CP_RB0_CNTL */
1223 tmp = regCP_HQD_PQ_CONTROL_DEFAULT;
1224 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
1225 (order_base_2(ring->ring_size / 4) - 1));
1226 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
1227 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
1228 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1);
1229 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
1230 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
1231 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
1232 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1);
1233 mqd->cp_hqd_pq_control = tmp;
1234
1235 /* enable doorbell */
1236 tmp = 0;
1237 if (ring->use_doorbell) {
1238 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1239 DOORBELL_OFFSET, ring->doorbell_index);
1240 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1241 DOORBELL_EN, 1);
1242 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1243 DOORBELL_SOURCE, 0);
1244 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1245 DOORBELL_HIT, 0);
1246 } else {
1247 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1248 DOORBELL_EN, 0);
1249 }
1250 mqd->cp_hqd_pq_doorbell_control = tmp;
1251
1252 mqd->cp_hqd_vmid = 0;
1253 /* activate the queue */
1254 mqd->cp_hqd_active = 1;
1255
1256 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT;
1257 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE,
1258 PRELOAD_SIZE, 0x55);
1259 mqd->cp_hqd_persistent_state = tmp;
1260
1261 mqd->cp_hqd_ib_control = regCP_HQD_IB_CONTROL_DEFAULT;
1262 mqd->cp_hqd_iq_timer = regCP_HQD_IQ_TIMER_DEFAULT;
1263 mqd->cp_hqd_quantum = regCP_HQD_QUANTUM_DEFAULT;
1264
1265 /*
1266 * Set CP_HQD_GFX_CONTROL.DB_UPDATED_MSG_EN[15] to enable unmapped
1267 * doorbell handling. This is a reserved CP internal register can
1268 * not be accesss by others
1269 */
1270 mqd->reserved_184 = BIT(15);
1271
1272 return 0;
1273 }
1274
mes_v12_0_queue_init_register(struct amdgpu_ring * ring)1275 static void mes_v12_0_queue_init_register(struct amdgpu_ring *ring)
1276 {
1277 struct v12_compute_mqd *mqd = ring->mqd_ptr;
1278 struct amdgpu_device *adev = ring->adev;
1279 uint32_t data = 0;
1280
1281 mutex_lock(&adev->srbm_mutex);
1282 soc21_grbm_select(adev, 3, ring->pipe, 0, 0);
1283
1284 /* set CP_HQD_VMID.VMID = 0. */
1285 data = RREG32_SOC15(GC, 0, regCP_HQD_VMID);
1286 data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0);
1287 WREG32_SOC15(GC, 0, regCP_HQD_VMID, data);
1288
1289 /* set CP_HQD_PQ_DOORBELL_CONTROL.DOORBELL_EN=0 */
1290 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL);
1291 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL,
1292 DOORBELL_EN, 0);
1293 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data);
1294
1295 /* set CP_MQD_BASE_ADDR/HI with the MQD base address */
1296 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo);
1297 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
1298
1299 /* set CP_MQD_CONTROL.VMID=0 */
1300 data = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL);
1301 data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0);
1302 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 0);
1303
1304 /* set CP_HQD_PQ_BASE/HI with the ring buffer base address */
1305 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo);
1306 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi);
1307
1308 /* set CP_HQD_PQ_RPTR_REPORT_ADDR/HI */
1309 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR,
1310 mqd->cp_hqd_pq_rptr_report_addr_lo);
1311 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
1312 mqd->cp_hqd_pq_rptr_report_addr_hi);
1313
1314 /* set CP_HQD_PQ_CONTROL */
1315 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control);
1316
1317 /* set CP_HQD_PQ_WPTR_POLL_ADDR/HI */
1318 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR,
1319 mqd->cp_hqd_pq_wptr_poll_addr_lo);
1320 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI,
1321 mqd->cp_hqd_pq_wptr_poll_addr_hi);
1322
1323 /* set CP_HQD_PQ_DOORBELL_CONTROL */
1324 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL,
1325 mqd->cp_hqd_pq_doorbell_control);
1326
1327 /* set CP_HQD_PERSISTENT_STATE.PRELOAD_SIZE=0x53 */
1328 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state);
1329
1330 /* set CP_HQD_ACTIVE.ACTIVE=1 */
1331 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, mqd->cp_hqd_active);
1332
1333 soc21_grbm_select(adev, 0, 0, 0, 0);
1334 mutex_unlock(&adev->srbm_mutex);
1335 }
1336
mes_v12_0_kiq_enable_queue(struct amdgpu_device * adev)1337 static int mes_v12_0_kiq_enable_queue(struct amdgpu_device *adev)
1338 {
1339 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
1340 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring;
1341 int r;
1342
1343 if (!kiq->pmf || !kiq->pmf->kiq_map_queues)
1344 return -EINVAL;
1345
1346 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size);
1347 if (r) {
1348 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
1349 return r;
1350 }
1351
1352 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring[0]);
1353
1354 r = amdgpu_ring_test_ring(kiq_ring);
1355 if (r) {
1356 DRM_ERROR("kfq enable failed\n");
1357 kiq_ring->sched.ready = false;
1358 }
1359 return r;
1360 }
1361
mes_v12_0_queue_init(struct amdgpu_device * adev,enum amdgpu_mes_pipe pipe)1362 static int mes_v12_0_queue_init(struct amdgpu_device *adev,
1363 enum amdgpu_mes_pipe pipe)
1364 {
1365 struct amdgpu_ring *ring;
1366 int r;
1367
1368 if (!adev->enable_uni_mes && pipe == AMDGPU_MES_KIQ_PIPE)
1369 ring = &adev->gfx.kiq[0].ring;
1370 else
1371 ring = &adev->mes.ring[pipe];
1372
1373 if ((adev->enable_uni_mes || pipe == AMDGPU_MES_SCHED_PIPE) &&
1374 (amdgpu_in_reset(adev) || adev->in_suspend)) {
1375 *(ring->wptr_cpu_addr) = 0;
1376 *(ring->rptr_cpu_addr) = 0;
1377 amdgpu_ring_clear_ring(ring);
1378 }
1379
1380 r = mes_v12_0_mqd_init(ring);
1381 if (r)
1382 return r;
1383
1384 if (pipe == AMDGPU_MES_SCHED_PIPE) {
1385 if (adev->enable_uni_mes)
1386 r = amdgpu_mes_map_legacy_queue(adev, ring);
1387 else
1388 r = mes_v12_0_kiq_enable_queue(adev);
1389 if (r)
1390 return r;
1391 } else {
1392 mes_v12_0_queue_init_register(ring);
1393 }
1394
1395 /* get MES scheduler/KIQ versions */
1396 mutex_lock(&adev->srbm_mutex);
1397 soc21_grbm_select(adev, 3, pipe, 0, 0);
1398
1399 if (pipe == AMDGPU_MES_SCHED_PIPE)
1400 adev->mes.sched_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO);
1401 else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq)
1402 adev->mes.kiq_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO);
1403
1404 soc21_grbm_select(adev, 0, 0, 0, 0);
1405 mutex_unlock(&adev->srbm_mutex);
1406
1407 return 0;
1408 }
1409
mes_v12_0_ring_init(struct amdgpu_device * adev,int pipe)1410 static int mes_v12_0_ring_init(struct amdgpu_device *adev, int pipe)
1411 {
1412 struct amdgpu_ring *ring;
1413
1414 ring = &adev->mes.ring[pipe];
1415
1416 ring->funcs = &mes_v12_0_ring_funcs;
1417
1418 ring->me = 3;
1419 ring->pipe = pipe;
1420 ring->queue = 0;
1421
1422 ring->ring_obj = NULL;
1423 ring->use_doorbell = true;
1424 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[pipe];
1425 ring->no_scheduler = true;
1426 sprintf(ring->name, "mes_%d.%d.%d", ring->me, ring->pipe, ring->queue);
1427
1428 if (pipe == AMDGPU_MES_SCHED_PIPE)
1429 ring->doorbell_index = adev->doorbell_index.mes_ring0 << 1;
1430 else
1431 ring->doorbell_index = adev->doorbell_index.mes_ring1 << 1;
1432
1433 return amdgpu_ring_init(adev, ring, 1024, NULL, 0,
1434 AMDGPU_RING_PRIO_DEFAULT, NULL);
1435 }
1436
mes_v12_0_kiq_ring_init(struct amdgpu_device * adev)1437 static int mes_v12_0_kiq_ring_init(struct amdgpu_device *adev)
1438 {
1439 struct amdgpu_ring *ring;
1440
1441 spin_lock_init(&adev->gfx.kiq[0].ring_lock);
1442
1443 ring = &adev->gfx.kiq[0].ring;
1444
1445 ring->me = 3;
1446 ring->pipe = 1;
1447 ring->queue = 0;
1448
1449 ring->adev = NULL;
1450 ring->ring_obj = NULL;
1451 ring->use_doorbell = true;
1452 ring->doorbell_index = adev->doorbell_index.mes_ring1 << 1;
1453 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_KIQ_PIPE];
1454 ring->no_scheduler = true;
1455 sprintf(ring->name, "mes_kiq_%d.%d.%d",
1456 ring->me, ring->pipe, ring->queue);
1457
1458 return amdgpu_ring_init(adev, ring, 1024, NULL, 0,
1459 AMDGPU_RING_PRIO_DEFAULT, NULL);
1460 }
1461
mes_v12_0_mqd_sw_init(struct amdgpu_device * adev,enum amdgpu_mes_pipe pipe)1462 static int mes_v12_0_mqd_sw_init(struct amdgpu_device *adev,
1463 enum amdgpu_mes_pipe pipe)
1464 {
1465 int r, mqd_size = sizeof(struct v12_compute_mqd);
1466 struct amdgpu_ring *ring;
1467
1468 if (!adev->enable_uni_mes && pipe == AMDGPU_MES_KIQ_PIPE)
1469 ring = &adev->gfx.kiq[0].ring;
1470 else
1471 ring = &adev->mes.ring[pipe];
1472
1473 if (ring->mqd_obj)
1474 return 0;
1475
1476 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,
1477 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj,
1478 &ring->mqd_gpu_addr, &ring->mqd_ptr);
1479 if (r) {
1480 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r);
1481 return r;
1482 }
1483
1484 memset(ring->mqd_ptr, 0, mqd_size);
1485
1486 /* prepare MQD backup */
1487 adev->mes.mqd_backup[pipe] = kmalloc(mqd_size, GFP_KERNEL);
1488 if (!adev->mes.mqd_backup[pipe])
1489 dev_warn(adev->dev,
1490 "no memory to create MQD backup for ring %s\n",
1491 ring->name);
1492
1493 return 0;
1494 }
1495
mes_v12_0_sw_init(struct amdgpu_ip_block * ip_block)1496 static int mes_v12_0_sw_init(struct amdgpu_ip_block *ip_block)
1497 {
1498 struct amdgpu_device *adev = ip_block->adev;
1499 int pipe, r;
1500
1501 adev->mes.funcs = &mes_v12_0_funcs;
1502 adev->mes.kiq_hw_init = &mes_v12_0_kiq_hw_init;
1503 adev->mes.kiq_hw_fini = &mes_v12_0_kiq_hw_fini;
1504 adev->mes.enable_legacy_queue_map = true;
1505
1506 adev->mes.event_log_size = adev->enable_uni_mes ?
1507 (AMDGPU_MAX_MES_PIPES * (AMDGPU_MES_LOG_BUFFER_SIZE + AMDGPU_MES_MSCRATCH_SIZE)) :
1508 (AMDGPU_MES_LOG_BUFFER_SIZE + AMDGPU_MES_MSCRATCH_SIZE);
1509 r = amdgpu_mes_init(adev);
1510 if (r)
1511 return r;
1512
1513 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
1514 r = mes_v12_0_allocate_eop_buf(adev, pipe);
1515 if (r)
1516 return r;
1517
1518 r = mes_v12_0_mqd_sw_init(adev, pipe);
1519 if (r)
1520 return r;
1521
1522 if (!adev->enable_uni_mes && pipe == AMDGPU_MES_KIQ_PIPE) {
1523 r = mes_v12_0_kiq_ring_init(adev);
1524 }
1525 else {
1526 r = mes_v12_0_ring_init(adev, pipe);
1527 if (r)
1528 return r;
1529 r = amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE, PAGE_SIZE,
1530 AMDGPU_GEM_DOMAIN_VRAM,
1531 &adev->mes.resource_1[pipe],
1532 &adev->mes.resource_1_gpu_addr[pipe],
1533 &adev->mes.resource_1_addr[pipe]);
1534 if (r) {
1535 dev_err(adev->dev, "(%d) failed to create mes resource_1 bo pipe[%d]\n", r, pipe);
1536 return r;
1537 }
1538 }
1539 }
1540
1541 return 0;
1542 }
1543
mes_v12_0_sw_fini(struct amdgpu_ip_block * ip_block)1544 static int mes_v12_0_sw_fini(struct amdgpu_ip_block *ip_block)
1545 {
1546 struct amdgpu_device *adev = ip_block->adev;
1547 int pipe;
1548
1549 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
1550 amdgpu_bo_free_kernel(&adev->mes.resource_1[pipe],
1551 &adev->mes.resource_1_gpu_addr[pipe],
1552 &adev->mes.resource_1_addr[pipe]);
1553
1554 kfree(adev->mes.mqd_backup[pipe]);
1555
1556 amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[pipe],
1557 &adev->mes.eop_gpu_addr[pipe],
1558 NULL);
1559 amdgpu_ucode_release(&adev->mes.fw[pipe]);
1560
1561 if (adev->enable_uni_mes || pipe == AMDGPU_MES_SCHED_PIPE) {
1562 amdgpu_bo_free_kernel(&adev->mes.ring[pipe].mqd_obj,
1563 &adev->mes.ring[pipe].mqd_gpu_addr,
1564 &adev->mes.ring[pipe].mqd_ptr);
1565 amdgpu_ring_fini(&adev->mes.ring[pipe]);
1566 }
1567 }
1568
1569 if (!adev->enable_uni_mes) {
1570 amdgpu_bo_free_kernel(&adev->gfx.kiq[0].ring.mqd_obj,
1571 &adev->gfx.kiq[0].ring.mqd_gpu_addr,
1572 &adev->gfx.kiq[0].ring.mqd_ptr);
1573 amdgpu_ring_fini(&adev->gfx.kiq[0].ring);
1574 }
1575
1576 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
1577 mes_v12_0_free_ucode_buffers(adev, AMDGPU_MES_KIQ_PIPE);
1578 mes_v12_0_free_ucode_buffers(adev, AMDGPU_MES_SCHED_PIPE);
1579 }
1580
1581 amdgpu_mes_fini(adev);
1582 return 0;
1583 }
1584
mes_v12_0_kiq_dequeue_sched(struct amdgpu_device * adev)1585 static void mes_v12_0_kiq_dequeue_sched(struct amdgpu_device *adev)
1586 {
1587 uint32_t data;
1588 int i;
1589
1590 mutex_lock(&adev->srbm_mutex);
1591 soc21_grbm_select(adev, 3, AMDGPU_MES_SCHED_PIPE, 0, 0);
1592
1593 /* disable the queue if it's active */
1594 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) {
1595 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1);
1596 for (i = 0; i < adev->usec_timeout; i++) {
1597 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1))
1598 break;
1599 udelay(1);
1600 }
1601 }
1602 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL);
1603 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL,
1604 DOORBELL_EN, 0);
1605 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL,
1606 DOORBELL_HIT, 1);
1607 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data);
1608
1609 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 0);
1610
1611 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 0);
1612 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 0);
1613 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 0);
1614
1615 soc21_grbm_select(adev, 0, 0, 0, 0);
1616 mutex_unlock(&adev->srbm_mutex);
1617
1618 adev->mes.ring[0].sched.ready = false;
1619 }
1620
mes_v12_0_kiq_setting(struct amdgpu_ring * ring)1621 static void mes_v12_0_kiq_setting(struct amdgpu_ring *ring)
1622 {
1623 uint32_t tmp;
1624 struct amdgpu_device *adev = ring->adev;
1625
1626 /* tell RLC which is KIQ queue */
1627 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);
1628 tmp &= 0xffffff00;
1629 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
1630 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp | 0x80);
1631 }
1632
mes_v12_0_kiq_hw_init(struct amdgpu_device * adev)1633 static int mes_v12_0_kiq_hw_init(struct amdgpu_device *adev)
1634 {
1635 int r = 0;
1636 struct amdgpu_ip_block *ip_block;
1637
1638 if (adev->enable_uni_mes)
1639 mes_v12_0_kiq_setting(&adev->mes.ring[AMDGPU_MES_KIQ_PIPE]);
1640 else
1641 mes_v12_0_kiq_setting(&adev->gfx.kiq[0].ring);
1642
1643 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
1644
1645 r = mes_v12_0_load_microcode(adev, AMDGPU_MES_SCHED_PIPE, false);
1646 if (r) {
1647 DRM_ERROR("failed to load MES fw, r=%d\n", r);
1648 return r;
1649 }
1650
1651 r = mes_v12_0_load_microcode(adev, AMDGPU_MES_KIQ_PIPE, true);
1652 if (r) {
1653 DRM_ERROR("failed to load MES kiq fw, r=%d\n", r);
1654 return r;
1655 }
1656
1657 mes_v12_0_set_ucode_start_addr(adev);
1658
1659 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
1660 mes_v12_0_set_ucode_start_addr(adev);
1661
1662 mes_v12_0_enable(adev, true);
1663
1664 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_MES);
1665 if (unlikely(!ip_block)) {
1666 dev_err(adev->dev, "Failed to get MES handle\n");
1667 return -EINVAL;
1668 }
1669
1670 r = mes_v12_0_queue_init(adev, AMDGPU_MES_KIQ_PIPE);
1671 if (r)
1672 goto failure;
1673
1674 if (adev->enable_uni_mes) {
1675 r = mes_v12_0_set_hw_resources(&adev->mes, AMDGPU_MES_KIQ_PIPE);
1676 if (r)
1677 goto failure;
1678
1679 mes_v12_0_set_hw_resources_1(&adev->mes, AMDGPU_MES_KIQ_PIPE);
1680 }
1681
1682 if (adev->mes.enable_legacy_queue_map) {
1683 r = mes_v12_0_hw_init(ip_block);
1684 if (r)
1685 goto failure;
1686 }
1687
1688 return r;
1689
1690 failure:
1691 mes_v12_0_hw_fini(ip_block);
1692 return r;
1693 }
1694
mes_v12_0_kiq_hw_fini(struct amdgpu_device * adev)1695 static int mes_v12_0_kiq_hw_fini(struct amdgpu_device *adev)
1696 {
1697 if (adev->mes.ring[0].sched.ready) {
1698 if (adev->enable_uni_mes)
1699 amdgpu_mes_unmap_legacy_queue(adev,
1700 &adev->mes.ring[AMDGPU_MES_SCHED_PIPE],
1701 RESET_QUEUES, 0, 0);
1702 else
1703 mes_v12_0_kiq_dequeue_sched(adev);
1704
1705 adev->mes.ring[0].sched.ready = false;
1706 }
1707
1708 mes_v12_0_enable(adev, false);
1709
1710 return 0;
1711 }
1712
mes_v12_0_hw_init(struct amdgpu_ip_block * ip_block)1713 static int mes_v12_0_hw_init(struct amdgpu_ip_block *ip_block)
1714 {
1715 int r;
1716 struct amdgpu_device *adev = ip_block->adev;
1717
1718 if (adev->mes.ring[0].sched.ready)
1719 goto out;
1720
1721 if (!adev->enable_mes_kiq) {
1722 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
1723 r = mes_v12_0_load_microcode(adev,
1724 AMDGPU_MES_SCHED_PIPE, true);
1725 if (r) {
1726 DRM_ERROR("failed to MES fw, r=%d\n", r);
1727 return r;
1728 }
1729
1730 mes_v12_0_set_ucode_start_addr(adev);
1731
1732 } else if (adev->firmware.load_type ==
1733 AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
1734
1735 mes_v12_0_set_ucode_start_addr(adev);
1736 }
1737
1738 mes_v12_0_enable(adev, true);
1739 }
1740
1741 /* Enable the MES to handle doorbell ring on unmapped queue */
1742 mes_v12_0_enable_unmapped_doorbell_handling(&adev->mes, true);
1743
1744 r = mes_v12_0_queue_init(adev, AMDGPU_MES_SCHED_PIPE);
1745 if (r)
1746 goto failure;
1747
1748 r = mes_v12_0_set_hw_resources(&adev->mes, AMDGPU_MES_SCHED_PIPE);
1749 if (r)
1750 goto failure;
1751
1752 mes_v12_0_set_hw_resources_1(&adev->mes, AMDGPU_MES_SCHED_PIPE);
1753
1754 mes_v12_0_init_aggregated_doorbell(&adev->mes);
1755
1756 r = mes_v12_0_query_sched_status(&adev->mes, AMDGPU_MES_SCHED_PIPE);
1757 if (r) {
1758 DRM_ERROR("MES is busy\n");
1759 goto failure;
1760 }
1761
1762 r = amdgpu_mes_update_enforce_isolation(adev);
1763 if (r)
1764 goto failure;
1765
1766 out:
1767 /*
1768 * Disable KIQ ring usage from the driver once MES is enabled.
1769 * MES uses KIQ ring exclusively so driver cannot access KIQ ring
1770 * with MES enabled.
1771 */
1772 adev->gfx.kiq[0].ring.sched.ready = false;
1773 adev->mes.ring[0].sched.ready = true;
1774
1775 return 0;
1776
1777 failure:
1778 mes_v12_0_hw_fini(ip_block);
1779 return r;
1780 }
1781
mes_v12_0_hw_fini(struct amdgpu_ip_block * ip_block)1782 static int mes_v12_0_hw_fini(struct amdgpu_ip_block *ip_block)
1783 {
1784 return 0;
1785 }
1786
mes_v12_0_suspend(struct amdgpu_ip_block * ip_block)1787 static int mes_v12_0_suspend(struct amdgpu_ip_block *ip_block)
1788 {
1789 return mes_v12_0_hw_fini(ip_block);
1790 }
1791
mes_v12_0_resume(struct amdgpu_ip_block * ip_block)1792 static int mes_v12_0_resume(struct amdgpu_ip_block *ip_block)
1793 {
1794 return mes_v12_0_hw_init(ip_block);
1795 }
1796
mes_v12_0_early_init(struct amdgpu_ip_block * ip_block)1797 static int mes_v12_0_early_init(struct amdgpu_ip_block *ip_block)
1798 {
1799 struct amdgpu_device *adev = ip_block->adev;
1800 int pipe, r;
1801
1802 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
1803 r = amdgpu_mes_init_microcode(adev, pipe);
1804 if (r)
1805 return r;
1806 }
1807
1808 return 0;
1809 }
1810
mes_v12_0_late_init(struct amdgpu_ip_block * ip_block)1811 static int mes_v12_0_late_init(struct amdgpu_ip_block *ip_block)
1812 {
1813 struct amdgpu_device *adev = ip_block->adev;
1814
1815 /* it's only intended for use in mes_self_test case, not for s0ix and reset */
1816 if (!amdgpu_in_reset(adev) && !adev->in_s0ix && !adev->in_suspend)
1817 amdgpu_mes_self_test(adev);
1818
1819 return 0;
1820 }
1821
1822 static const struct amd_ip_funcs mes_v12_0_ip_funcs = {
1823 .name = "mes_v12_0",
1824 .early_init = mes_v12_0_early_init,
1825 .late_init = mes_v12_0_late_init,
1826 .sw_init = mes_v12_0_sw_init,
1827 .sw_fini = mes_v12_0_sw_fini,
1828 .hw_init = mes_v12_0_hw_init,
1829 .hw_fini = mes_v12_0_hw_fini,
1830 .suspend = mes_v12_0_suspend,
1831 .resume = mes_v12_0_resume,
1832 };
1833
1834 const struct amdgpu_ip_block_version mes_v12_0_ip_block = {
1835 .type = AMD_IP_BLOCK_TYPE_MES,
1836 .major = 12,
1837 .minor = 0,
1838 .rev = 0,
1839 .funcs = &mes_v12_0_ip_funcs,
1840 };
1841