1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <linux/firmware.h>
25 #include <linux/module.h>
26 #include "amdgpu.h"
27 #include "soc15_common.h"
28 #include "soc21.h"
29 #include "gfx_v11_0.h"
30 #include "gc/gc_11_0_0_offset.h"
31 #include "gc/gc_11_0_0_sh_mask.h"
32 #include "gc/gc_11_0_0_default.h"
33 #include "v11_structs.h"
34 #include "mes_v11_api_def.h"
35
36 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes.bin");
37 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes_2.bin");
38 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes1.bin");
39 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes.bin");
40 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes_2.bin");
41 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes1.bin");
42 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes.bin");
43 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes_2.bin");
44 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes1.bin");
45 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes.bin");
46 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes_2.bin");
47 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes1.bin");
48 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes.bin");
49 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes_2.bin");
50 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes1.bin");
51 MODULE_FIRMWARE("amdgpu/gc_11_5_0_mes_2.bin");
52 MODULE_FIRMWARE("amdgpu/gc_11_5_0_mes1.bin");
53 MODULE_FIRMWARE("amdgpu/gc_11_5_1_mes_2.bin");
54 MODULE_FIRMWARE("amdgpu/gc_11_5_1_mes1.bin");
55 MODULE_FIRMWARE("amdgpu/gc_11_5_2_mes_2.bin");
56 MODULE_FIRMWARE("amdgpu/gc_11_5_2_mes1.bin");
57 MODULE_FIRMWARE("amdgpu/gc_11_5_3_mes_2.bin");
58 MODULE_FIRMWARE("amdgpu/gc_11_5_3_mes1.bin");
59
60 static int mes_v11_0_hw_init(struct amdgpu_ip_block *ip_block);
61 static int mes_v11_0_hw_fini(struct amdgpu_ip_block *ip_block);
62 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev);
63 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev);
64
65 #define MES_EOP_SIZE 2048
66 #define GFX_MES_DRAM_SIZE 0x80000
67 #define MES11_HW_RESOURCE_1_SIZE (128 * AMDGPU_GPU_PAGE_SIZE)
68
mes_v11_0_ring_set_wptr(struct amdgpu_ring * ring)69 static void mes_v11_0_ring_set_wptr(struct amdgpu_ring *ring)
70 {
71 struct amdgpu_device *adev = ring->adev;
72
73 if (ring->use_doorbell) {
74 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
75 ring->wptr);
76 WDOORBELL64(ring->doorbell_index, ring->wptr);
77 } else {
78 BUG();
79 }
80 }
81
mes_v11_0_ring_get_rptr(struct amdgpu_ring * ring)82 static u64 mes_v11_0_ring_get_rptr(struct amdgpu_ring *ring)
83 {
84 return *ring->rptr_cpu_addr;
85 }
86
mes_v11_0_ring_get_wptr(struct amdgpu_ring * ring)87 static u64 mes_v11_0_ring_get_wptr(struct amdgpu_ring *ring)
88 {
89 u64 wptr;
90
91 if (ring->use_doorbell)
92 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
93 else
94 BUG();
95 return wptr;
96 }
97
98 static const struct amdgpu_ring_funcs mes_v11_0_ring_funcs = {
99 .type = AMDGPU_RING_TYPE_MES,
100 .align_mask = 1,
101 .nop = 0,
102 .support_64bit_ptrs = true,
103 .get_rptr = mes_v11_0_ring_get_rptr,
104 .get_wptr = mes_v11_0_ring_get_wptr,
105 .set_wptr = mes_v11_0_ring_set_wptr,
106 .insert_nop = amdgpu_ring_insert_nop,
107 };
108
109 static const char *mes_v11_0_opcodes[] = {
110 "SET_HW_RSRC",
111 "SET_SCHEDULING_CONFIG",
112 "ADD_QUEUE",
113 "REMOVE_QUEUE",
114 "PERFORM_YIELD",
115 "SET_GANG_PRIORITY_LEVEL",
116 "SUSPEND",
117 "RESUME",
118 "RESET",
119 "SET_LOG_BUFFER",
120 "CHANGE_GANG_PRORITY",
121 "QUERY_SCHEDULER_STATUS",
122 "PROGRAM_GDS",
123 "SET_DEBUG_VMID",
124 "MISC",
125 "UPDATE_ROOT_PAGE_TABLE",
126 "AMD_LOG",
127 "unused",
128 "unused",
129 "SET_HW_RSRC_1",
130 };
131
132 static const char *mes_v11_0_misc_opcodes[] = {
133 "WRITE_REG",
134 "INV_GART",
135 "QUERY_STATUS",
136 "READ_REG",
137 "WAIT_REG_MEM",
138 "SET_SHADER_DEBUGGER",
139 };
140
mes_v11_0_get_op_string(union MESAPI__MISC * x_pkt)141 static const char *mes_v11_0_get_op_string(union MESAPI__MISC *x_pkt)
142 {
143 const char *op_str = NULL;
144
145 if (x_pkt->header.opcode < ARRAY_SIZE(mes_v11_0_opcodes))
146 op_str = mes_v11_0_opcodes[x_pkt->header.opcode];
147
148 return op_str;
149 }
150
mes_v11_0_get_misc_op_string(union MESAPI__MISC * x_pkt)151 static const char *mes_v11_0_get_misc_op_string(union MESAPI__MISC *x_pkt)
152 {
153 const char *op_str = NULL;
154
155 if ((x_pkt->header.opcode == MES_SCH_API_MISC) &&
156 (x_pkt->opcode < ARRAY_SIZE(mes_v11_0_misc_opcodes)))
157 op_str = mes_v11_0_misc_opcodes[x_pkt->opcode];
158
159 return op_str;
160 }
161
mes_v11_0_submit_pkt_and_poll_completion(struct amdgpu_mes * mes,void * pkt,int size,int api_status_off)162 static int mes_v11_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes,
163 void *pkt, int size,
164 int api_status_off)
165 {
166 union MESAPI__QUERY_MES_STATUS mes_status_pkt;
167 signed long timeout = 2100000; /* 2100 ms */
168 struct amdgpu_device *adev = mes->adev;
169 struct amdgpu_ring *ring = &mes->ring[0];
170 struct MES_API_STATUS *api_status;
171 union MESAPI__MISC *x_pkt = pkt;
172 const char *op_str, *misc_op_str;
173 unsigned long flags;
174 u64 status_gpu_addr;
175 u32 seq, status_offset;
176 u64 *status_ptr;
177 signed long r;
178 int ret;
179
180 if (x_pkt->header.opcode >= MES_SCH_API_MAX)
181 return -EINVAL;
182
183 if (amdgpu_emu_mode) {
184 timeout *= 100;
185 } else if (amdgpu_sriov_vf(adev)) {
186 /* Worst case in sriov where all other 15 VF timeout, each VF needs about 600ms */
187 timeout = 15 * 600 * 1000;
188 }
189
190 ret = amdgpu_device_wb_get(adev, &status_offset);
191 if (ret)
192 return ret;
193
194 status_gpu_addr = adev->wb.gpu_addr + (status_offset * 4);
195 status_ptr = (u64 *)&adev->wb.wb[status_offset];
196 *status_ptr = 0;
197
198 spin_lock_irqsave(&mes->ring_lock[0], flags);
199 r = amdgpu_ring_alloc(ring, (size + sizeof(mes_status_pkt)) / 4);
200 if (r)
201 goto error_unlock_free;
202
203 seq = ++ring->fence_drv.sync_seq;
204 r = amdgpu_fence_wait_polling(ring,
205 seq - ring->fence_drv.num_fences_mask,
206 timeout);
207 if (r < 1)
208 goto error_undo;
209
210 api_status = (struct MES_API_STATUS *)((char *)pkt + api_status_off);
211 api_status->api_completion_fence_addr = status_gpu_addr;
212 api_status->api_completion_fence_value = 1;
213
214 amdgpu_ring_write_multiple(ring, pkt, size / 4);
215
216 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt));
217 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER;
218 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS;
219 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
220 mes_status_pkt.api_status.api_completion_fence_addr =
221 ring->fence_drv.gpu_addr;
222 mes_status_pkt.api_status.api_completion_fence_value = seq;
223
224 amdgpu_ring_write_multiple(ring, &mes_status_pkt,
225 sizeof(mes_status_pkt) / 4);
226
227 amdgpu_ring_commit(ring);
228 spin_unlock_irqrestore(&mes->ring_lock[0], flags);
229
230 op_str = mes_v11_0_get_op_string(x_pkt);
231 misc_op_str = mes_v11_0_get_misc_op_string(x_pkt);
232
233 if (misc_op_str)
234 dev_dbg(adev->dev, "MES msg=%s (%s) was emitted\n", op_str,
235 misc_op_str);
236 else if (op_str)
237 dev_dbg(adev->dev, "MES msg=%s was emitted\n", op_str);
238 else
239 dev_dbg(adev->dev, "MES msg=%d was emitted\n",
240 x_pkt->header.opcode);
241
242 r = amdgpu_fence_wait_polling(ring, seq, timeout);
243 if (r < 1 || !*status_ptr) {
244
245 if (misc_op_str)
246 dev_err(adev->dev, "MES failed to respond to msg=%s (%s)\n",
247 op_str, misc_op_str);
248 else if (op_str)
249 dev_err(adev->dev, "MES failed to respond to msg=%s\n",
250 op_str);
251 else
252 dev_err(adev->dev, "MES failed to respond to msg=%d\n",
253 x_pkt->header.opcode);
254
255 while (halt_if_hws_hang)
256 schedule();
257
258 r = -ETIMEDOUT;
259 goto error_wb_free;
260 }
261
262 amdgpu_device_wb_free(adev, status_offset);
263 return 0;
264
265 error_undo:
266 dev_err(adev->dev, "MES ring buffer is full.\n");
267 amdgpu_ring_undo(ring);
268
269 error_unlock_free:
270 spin_unlock_irqrestore(&mes->ring_lock[0], flags);
271
272 error_wb_free:
273 amdgpu_device_wb_free(adev, status_offset);
274 return r;
275 }
276
convert_to_mes_queue_type(int queue_type)277 static int convert_to_mes_queue_type(int queue_type)
278 {
279 if (queue_type == AMDGPU_RING_TYPE_GFX)
280 return MES_QUEUE_TYPE_GFX;
281 else if (queue_type == AMDGPU_RING_TYPE_COMPUTE)
282 return MES_QUEUE_TYPE_COMPUTE;
283 else if (queue_type == AMDGPU_RING_TYPE_SDMA)
284 return MES_QUEUE_TYPE_SDMA;
285 else
286 BUG();
287 return -1;
288 }
289
convert_to_mes_priority_level(int priority_level)290 static int convert_to_mes_priority_level(int priority_level)
291 {
292 switch (priority_level) {
293 case AMDGPU_MES_PRIORITY_LEVEL_LOW:
294 return AMD_PRIORITY_LEVEL_LOW;
295 case AMDGPU_MES_PRIORITY_LEVEL_NORMAL:
296 default:
297 return AMD_PRIORITY_LEVEL_NORMAL;
298 case AMDGPU_MES_PRIORITY_LEVEL_MEDIUM:
299 return AMD_PRIORITY_LEVEL_MEDIUM;
300 case AMDGPU_MES_PRIORITY_LEVEL_HIGH:
301 return AMD_PRIORITY_LEVEL_HIGH;
302 case AMDGPU_MES_PRIORITY_LEVEL_REALTIME:
303 return AMD_PRIORITY_LEVEL_REALTIME;
304 }
305 }
306
mes_v11_0_add_hw_queue(struct amdgpu_mes * mes,struct mes_add_queue_input * input)307 static int mes_v11_0_add_hw_queue(struct amdgpu_mes *mes,
308 struct mes_add_queue_input *input)
309 {
310 struct amdgpu_device *adev = mes->adev;
311 union MESAPI__ADD_QUEUE mes_add_queue_pkt;
312 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)];
313 uint32_t vm_cntx_cntl = hub->vm_cntx_cntl;
314
315 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt));
316
317 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;
318 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE;
319 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
320
321 mes_add_queue_pkt.process_id = input->process_id;
322 mes_add_queue_pkt.page_table_base_addr = input->page_table_base_addr;
323 mes_add_queue_pkt.process_va_start = input->process_va_start;
324 mes_add_queue_pkt.process_va_end = input->process_va_end;
325 mes_add_queue_pkt.process_quantum = input->process_quantum;
326 mes_add_queue_pkt.process_context_addr = input->process_context_addr;
327 mes_add_queue_pkt.gang_quantum = input->gang_quantum;
328 mes_add_queue_pkt.gang_context_addr = input->gang_context_addr;
329 mes_add_queue_pkt.inprocess_gang_priority =
330 convert_to_mes_priority_level(input->inprocess_gang_priority);
331 mes_add_queue_pkt.gang_global_priority_level =
332 convert_to_mes_priority_level(input->gang_global_priority_level);
333 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset;
334 mes_add_queue_pkt.mqd_addr = input->mqd_addr;
335
336 if (((adev->mes.sched_version & AMDGPU_MES_API_VERSION_MASK) >>
337 AMDGPU_MES_API_VERSION_SHIFT) >= 2)
338 mes_add_queue_pkt.wptr_addr = input->wptr_mc_addr;
339 else
340 mes_add_queue_pkt.wptr_addr = input->wptr_addr;
341
342 mes_add_queue_pkt.queue_type =
343 convert_to_mes_queue_type(input->queue_type);
344 mes_add_queue_pkt.paging = input->paging;
345 mes_add_queue_pkt.vm_context_cntl = vm_cntx_cntl;
346 mes_add_queue_pkt.gws_base = input->gws_base;
347 mes_add_queue_pkt.gws_size = input->gws_size;
348 mes_add_queue_pkt.trap_handler_addr = input->tba_addr;
349 mes_add_queue_pkt.tma_addr = input->tma_addr;
350 mes_add_queue_pkt.trap_en = input->trap_en;
351 mes_add_queue_pkt.skip_process_ctx_clear = input->skip_process_ctx_clear;
352 mes_add_queue_pkt.is_kfd_process = input->is_kfd_process;
353
354 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */
355 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue;
356 mes_add_queue_pkt.gds_size = input->queue_size;
357
358 mes_add_queue_pkt.exclusively_scheduled = input->exclusively_scheduled;
359
360 return mes_v11_0_submit_pkt_and_poll_completion(mes,
361 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt),
362 offsetof(union MESAPI__ADD_QUEUE, api_status));
363 }
364
mes_v11_0_remove_hw_queue(struct amdgpu_mes * mes,struct mes_remove_queue_input * input)365 static int mes_v11_0_remove_hw_queue(struct amdgpu_mes *mes,
366 struct mes_remove_queue_input *input)
367 {
368 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt;
369
370 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt));
371
372 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;
373 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE;
374 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
375
376 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset;
377 mes_remove_queue_pkt.gang_context_addr = input->gang_context_addr;
378
379 return mes_v11_0_submit_pkt_and_poll_completion(mes,
380 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt),
381 offsetof(union MESAPI__REMOVE_QUEUE, api_status));
382 }
383
mes_v11_0_reset_queue_mmio(struct amdgpu_mes * mes,uint32_t queue_type,uint32_t me_id,uint32_t pipe_id,uint32_t queue_id,uint32_t vmid)384 static int mes_v11_0_reset_queue_mmio(struct amdgpu_mes *mes, uint32_t queue_type,
385 uint32_t me_id, uint32_t pipe_id,
386 uint32_t queue_id, uint32_t vmid)
387 {
388 struct amdgpu_device *adev = mes->adev;
389 uint32_t value, reg;
390 int i, r = 0;
391
392 amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
393
394 if (queue_type == AMDGPU_RING_TYPE_GFX) {
395 dev_info(adev->dev, "reset gfx queue (%d:%d:%d: vmid:%d)\n",
396 me_id, pipe_id, queue_id, vmid);
397
398 mutex_lock(&adev->gfx.reset_sem_mutex);
399 gfx_v11_0_request_gfx_index_mutex(adev, true);
400 /* all se allow writes */
401 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX,
402 (uint32_t)(0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT));
403 value = REG_SET_FIELD(0, CP_VMID_RESET, RESET_REQUEST, 1 << vmid);
404 if (pipe_id == 0)
405 value = REG_SET_FIELD(value, CP_VMID_RESET, PIPE0_QUEUES, 1 << queue_id);
406 else
407 value = REG_SET_FIELD(value, CP_VMID_RESET, PIPE1_QUEUES, 1 << queue_id);
408 WREG32_SOC15(GC, 0, regCP_VMID_RESET, value);
409 gfx_v11_0_request_gfx_index_mutex(adev, false);
410 mutex_unlock(&adev->gfx.reset_sem_mutex);
411
412 mutex_lock(&adev->srbm_mutex);
413 soc21_grbm_select(adev, me_id, pipe_id, queue_id, 0);
414 /* wait till dequeue take effects */
415 for (i = 0; i < adev->usec_timeout; i++) {
416 if (!(RREG32_SOC15(GC, 0, regCP_GFX_HQD_ACTIVE) & 1))
417 break;
418 udelay(1);
419 }
420 if (i >= adev->usec_timeout) {
421 dev_err(adev->dev, "failed to wait on gfx hqd deactivate\n");
422 r = -ETIMEDOUT;
423 }
424
425 soc21_grbm_select(adev, 0, 0, 0, 0);
426 mutex_unlock(&adev->srbm_mutex);
427 } else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) {
428 dev_info(adev->dev, "reset compute queue (%d:%d:%d)\n",
429 me_id, pipe_id, queue_id);
430 mutex_lock(&adev->srbm_mutex);
431 soc21_grbm_select(adev, me_id, pipe_id, queue_id, 0);
432 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0x2);
433 WREG32_SOC15(GC, 0, regSPI_COMPUTE_QUEUE_RESET, 0x1);
434
435 /* wait till dequeue take effects */
436 for (i = 0; i < adev->usec_timeout; i++) {
437 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1))
438 break;
439 udelay(1);
440 }
441 if (i >= adev->usec_timeout) {
442 dev_err(adev->dev, "failed to wait on hqd deactivate\n");
443 r = -ETIMEDOUT;
444 }
445 soc21_grbm_select(adev, 0, 0, 0, 0);
446 mutex_unlock(&adev->srbm_mutex);
447 } else if (queue_type == AMDGPU_RING_TYPE_SDMA) {
448 dev_info(adev->dev, "reset sdma queue (%d:%d:%d)\n",
449 me_id, pipe_id, queue_id);
450 switch (me_id) {
451 case 1:
452 reg = SOC15_REG_OFFSET(GC, 0, regSDMA1_QUEUE_RESET_REQ);
453 break;
454 case 0:
455 default:
456 reg = SOC15_REG_OFFSET(GC, 0, regSDMA0_QUEUE_RESET_REQ);
457 break;
458 }
459
460 value = 1 << queue_id;
461 WREG32(reg, value);
462 /* wait for queue reset done */
463 for (i = 0; i < adev->usec_timeout; i++) {
464 if (!(RREG32(reg) & value))
465 break;
466 udelay(1);
467 }
468 if (i >= adev->usec_timeout) {
469 dev_err(adev->dev, "failed to wait on sdma queue reset done\n");
470 r = -ETIMEDOUT;
471 }
472 }
473
474 amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
475 return r;
476 }
477
mes_v11_0_map_legacy_queue(struct amdgpu_mes * mes,struct mes_map_legacy_queue_input * input)478 static int mes_v11_0_map_legacy_queue(struct amdgpu_mes *mes,
479 struct mes_map_legacy_queue_input *input)
480 {
481 union MESAPI__ADD_QUEUE mes_add_queue_pkt;
482
483 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt));
484
485 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;
486 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE;
487 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
488
489 mes_add_queue_pkt.pipe_id = input->pipe_id;
490 mes_add_queue_pkt.queue_id = input->queue_id;
491 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset;
492 mes_add_queue_pkt.mqd_addr = input->mqd_addr;
493 mes_add_queue_pkt.wptr_addr = input->wptr_addr;
494 mes_add_queue_pkt.queue_type =
495 convert_to_mes_queue_type(input->queue_type);
496 mes_add_queue_pkt.map_legacy_kq = 1;
497
498 return mes_v11_0_submit_pkt_and_poll_completion(mes,
499 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt),
500 offsetof(union MESAPI__ADD_QUEUE, api_status));
501 }
502
mes_v11_0_unmap_legacy_queue(struct amdgpu_mes * mes,struct mes_unmap_legacy_queue_input * input)503 static int mes_v11_0_unmap_legacy_queue(struct amdgpu_mes *mes,
504 struct mes_unmap_legacy_queue_input *input)
505 {
506 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt;
507
508 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt));
509
510 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;
511 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE;
512 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
513
514 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset;
515 mes_remove_queue_pkt.gang_context_addr = 0;
516
517 mes_remove_queue_pkt.pipe_id = input->pipe_id;
518 mes_remove_queue_pkt.queue_id = input->queue_id;
519
520 if (input->action == PREEMPT_QUEUES_NO_UNMAP) {
521 mes_remove_queue_pkt.preempt_legacy_gfx_queue = 1;
522 mes_remove_queue_pkt.tf_addr = input->trail_fence_addr;
523 mes_remove_queue_pkt.tf_data =
524 lower_32_bits(input->trail_fence_data);
525 } else {
526 mes_remove_queue_pkt.unmap_legacy_queue = 1;
527 mes_remove_queue_pkt.queue_type =
528 convert_to_mes_queue_type(input->queue_type);
529 }
530
531 return mes_v11_0_submit_pkt_and_poll_completion(mes,
532 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt),
533 offsetof(union MESAPI__REMOVE_QUEUE, api_status));
534 }
535
mes_v11_0_suspend_gang(struct amdgpu_mes * mes,struct mes_suspend_gang_input * input)536 static int mes_v11_0_suspend_gang(struct amdgpu_mes *mes,
537 struct mes_suspend_gang_input *input)
538 {
539 union MESAPI__SUSPEND mes_suspend_gang_pkt;
540
541 memset(&mes_suspend_gang_pkt, 0, sizeof(mes_suspend_gang_pkt));
542
543 mes_suspend_gang_pkt.header.type = MES_API_TYPE_SCHEDULER;
544 mes_suspend_gang_pkt.header.opcode = MES_SCH_API_SUSPEND;
545 mes_suspend_gang_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
546
547 mes_suspend_gang_pkt.suspend_all_gangs = input->suspend_all_gangs;
548 mes_suspend_gang_pkt.gang_context_addr = input->gang_context_addr;
549 mes_suspend_gang_pkt.suspend_fence_addr = input->suspend_fence_addr;
550 mes_suspend_gang_pkt.suspend_fence_value = input->suspend_fence_value;
551
552 return mes_v11_0_submit_pkt_and_poll_completion(mes,
553 &mes_suspend_gang_pkt, sizeof(mes_suspend_gang_pkt),
554 offsetof(union MESAPI__SUSPEND, api_status));
555 }
556
mes_v11_0_resume_gang(struct amdgpu_mes * mes,struct mes_resume_gang_input * input)557 static int mes_v11_0_resume_gang(struct amdgpu_mes *mes,
558 struct mes_resume_gang_input *input)
559 {
560 union MESAPI__RESUME mes_resume_gang_pkt;
561
562 memset(&mes_resume_gang_pkt, 0, sizeof(mes_resume_gang_pkt));
563
564 mes_resume_gang_pkt.header.type = MES_API_TYPE_SCHEDULER;
565 mes_resume_gang_pkt.header.opcode = MES_SCH_API_RESUME;
566 mes_resume_gang_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
567
568 mes_resume_gang_pkt.resume_all_gangs = input->resume_all_gangs;
569 mes_resume_gang_pkt.gang_context_addr = input->gang_context_addr;
570
571 return mes_v11_0_submit_pkt_and_poll_completion(mes,
572 &mes_resume_gang_pkt, sizeof(mes_resume_gang_pkt),
573 offsetof(union MESAPI__RESUME, api_status));
574 }
575
mes_v11_0_query_sched_status(struct amdgpu_mes * mes)576 static int mes_v11_0_query_sched_status(struct amdgpu_mes *mes)
577 {
578 union MESAPI__QUERY_MES_STATUS mes_status_pkt;
579
580 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt));
581
582 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER;
583 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS;
584 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
585
586 return mes_v11_0_submit_pkt_and_poll_completion(mes,
587 &mes_status_pkt, sizeof(mes_status_pkt),
588 offsetof(union MESAPI__QUERY_MES_STATUS, api_status));
589 }
590
mes_v11_0_misc_op(struct amdgpu_mes * mes,struct mes_misc_op_input * input)591 static int mes_v11_0_misc_op(struct amdgpu_mes *mes,
592 struct mes_misc_op_input *input)
593 {
594 union MESAPI__MISC misc_pkt;
595
596 memset(&misc_pkt, 0, sizeof(misc_pkt));
597
598 misc_pkt.header.type = MES_API_TYPE_SCHEDULER;
599 misc_pkt.header.opcode = MES_SCH_API_MISC;
600 misc_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
601
602 switch (input->op) {
603 case MES_MISC_OP_READ_REG:
604 misc_pkt.opcode = MESAPI_MISC__READ_REG;
605 misc_pkt.read_reg.reg_offset = input->read_reg.reg_offset;
606 misc_pkt.read_reg.buffer_addr = input->read_reg.buffer_addr;
607 break;
608 case MES_MISC_OP_WRITE_REG:
609 misc_pkt.opcode = MESAPI_MISC__WRITE_REG;
610 misc_pkt.write_reg.reg_offset = input->write_reg.reg_offset;
611 misc_pkt.write_reg.reg_value = input->write_reg.reg_value;
612 break;
613 case MES_MISC_OP_WRM_REG_WAIT:
614 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM;
615 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WAIT_REG_MEM;
616 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref;
617 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask;
618 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0;
619 misc_pkt.wait_reg_mem.reg_offset2 = 0;
620 break;
621 case MES_MISC_OP_WRM_REG_WR_WAIT:
622 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM;
623 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WR_WAIT_WR_REG;
624 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref;
625 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask;
626 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0;
627 misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1;
628 break;
629 case MES_MISC_OP_SET_SHADER_DEBUGGER:
630 misc_pkt.opcode = MESAPI_MISC__SET_SHADER_DEBUGGER;
631 misc_pkt.set_shader_debugger.process_context_addr =
632 input->set_shader_debugger.process_context_addr;
633 misc_pkt.set_shader_debugger.flags.u32all =
634 input->set_shader_debugger.flags.u32all;
635 misc_pkt.set_shader_debugger.spi_gdbg_per_vmid_cntl =
636 input->set_shader_debugger.spi_gdbg_per_vmid_cntl;
637 memcpy(misc_pkt.set_shader_debugger.tcp_watch_cntl,
638 input->set_shader_debugger.tcp_watch_cntl,
639 sizeof(misc_pkt.set_shader_debugger.tcp_watch_cntl));
640 misc_pkt.set_shader_debugger.trap_en = input->set_shader_debugger.trap_en;
641 break;
642 case MES_MISC_OP_CHANGE_CONFIG:
643 if ((mes->adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) < 0x63) {
644 dev_err(mes->adev->dev, "MES FW version must be larger than 0x63 to support limit single process feature.\n");
645 return -EINVAL;
646 }
647 misc_pkt.opcode = MESAPI_MISC__CHANGE_CONFIG;
648 misc_pkt.change_config.opcode =
649 MESAPI_MISC__CHANGE_CONFIG_OPTION_LIMIT_SINGLE_PROCESS;
650 misc_pkt.change_config.option.bits.limit_single_process =
651 input->change_config.option.limit_single_process;
652 break;
653
654 default:
655 DRM_ERROR("unsupported misc op (%d) \n", input->op);
656 return -EINVAL;
657 }
658
659 return mes_v11_0_submit_pkt_and_poll_completion(mes,
660 &misc_pkt, sizeof(misc_pkt),
661 offsetof(union MESAPI__MISC, api_status));
662 }
663
mes_v11_0_set_hw_resources(struct amdgpu_mes * mes)664 static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes)
665 {
666 int i;
667 struct amdgpu_device *adev = mes->adev;
668 union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt;
669
670 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt));
671
672 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER;
673 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC;
674 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
675
676 mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub;
677 mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub;
678 mes_set_hw_res_pkt.gds_size = adev->gds.gds_size;
679 mes_set_hw_res_pkt.paging_vmid = 0;
680 mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = mes->sch_ctx_gpu_addr[0];
681 mes_set_hw_res_pkt.query_status_fence_gpu_mc_ptr =
682 mes->query_status_fence_gpu_addr[0];
683
684 for (i = 0; i < MAX_COMPUTE_PIPES; i++)
685 mes_set_hw_res_pkt.compute_hqd_mask[i] =
686 mes->compute_hqd_mask[i];
687
688 for (i = 0; i < MAX_GFX_PIPES; i++)
689 mes_set_hw_res_pkt.gfx_hqd_mask[i] =
690 mes->gfx_hqd_mask[i];
691
692 for (i = 0; i < MAX_SDMA_PIPES; i++)
693 mes_set_hw_res_pkt.sdma_hqd_mask[i] = mes->sdma_hqd_mask[i];
694
695 for (i = 0; i < AMD_PRIORITY_NUM_LEVELS; i++)
696 mes_set_hw_res_pkt.aggregated_doorbells[i] =
697 mes->aggregated_doorbells[i];
698
699 for (i = 0; i < 5; i++) {
700 mes_set_hw_res_pkt.gc_base[i] = adev->reg_offset[GC_HWIP][0][i];
701 mes_set_hw_res_pkt.mmhub_base[i] =
702 adev->reg_offset[MMHUB_HWIP][0][i];
703 mes_set_hw_res_pkt.osssys_base[i] =
704 adev->reg_offset[OSSSYS_HWIP][0][i];
705 }
706
707 mes_set_hw_res_pkt.disable_reset = 1;
708 mes_set_hw_res_pkt.disable_mes_log = 1;
709 mes_set_hw_res_pkt.use_different_vmid_compute = 1;
710 mes_set_hw_res_pkt.enable_reg_active_poll = 1;
711 mes_set_hw_res_pkt.enable_level_process_quantum_check = 1;
712 mes_set_hw_res_pkt.oversubscription_timer = 50;
713 if (amdgpu_mes_log_enable) {
714 mes_set_hw_res_pkt.enable_mes_event_int_logging = 1;
715 mes_set_hw_res_pkt.event_intr_history_gpu_mc_ptr =
716 mes->event_log_gpu_addr;
717 }
718
719 if (adev->enforce_isolation[0] == AMDGPU_ENFORCE_ISOLATION_ENABLE)
720 mes_set_hw_res_pkt.limit_single_process = 1;
721
722 return mes_v11_0_submit_pkt_and_poll_completion(mes,
723 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt),
724 offsetof(union MESAPI_SET_HW_RESOURCES, api_status));
725 }
726
mes_v11_0_set_hw_resources_1(struct amdgpu_mes * mes)727 static int mes_v11_0_set_hw_resources_1(struct amdgpu_mes *mes)
728 {
729 union MESAPI_SET_HW_RESOURCES_1 mes_set_hw_res_pkt;
730 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt));
731
732 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER;
733 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC_1;
734 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
735 mes_set_hw_res_pkt.enable_mes_info_ctx = 1;
736
737 mes_set_hw_res_pkt.cleaner_shader_fence_mc_addr = mes->resource_1_gpu_addr[0];
738 if (amdgpu_sriov_is_mes_info_enable(mes->adev)) {
739 mes_set_hw_res_pkt.mes_info_ctx_mc_addr =
740 mes->resource_1_gpu_addr[0] + AMDGPU_GPU_PAGE_SIZE;
741 mes_set_hw_res_pkt.mes_info_ctx_size = MES11_HW_RESOURCE_1_SIZE;
742 }
743
744 return mes_v11_0_submit_pkt_and_poll_completion(mes,
745 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt),
746 offsetof(union MESAPI_SET_HW_RESOURCES_1, api_status));
747 }
748
mes_v11_0_reset_hw_queue(struct amdgpu_mes * mes,struct mes_reset_queue_input * input)749 static int mes_v11_0_reset_hw_queue(struct amdgpu_mes *mes,
750 struct mes_reset_queue_input *input)
751 {
752 union MESAPI__RESET mes_reset_queue_pkt;
753
754 if (input->use_mmio)
755 return mes_v11_0_reset_queue_mmio(mes, input->queue_type,
756 input->me_id, input->pipe_id,
757 input->queue_id, input->vmid);
758
759 memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt));
760
761 mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;
762 mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET;
763 mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
764
765 mes_reset_queue_pkt.queue_type =
766 convert_to_mes_queue_type(input->queue_type);
767
768 if (input->legacy_gfx) {
769 mes_reset_queue_pkt.reset_legacy_gfx = 1;
770 mes_reset_queue_pkt.pipe_id_lp = input->pipe_id;
771 mes_reset_queue_pkt.queue_id_lp = input->queue_id;
772 mes_reset_queue_pkt.mqd_mc_addr_lp = input->mqd_addr;
773 mes_reset_queue_pkt.doorbell_offset_lp = input->doorbell_offset;
774 mes_reset_queue_pkt.wptr_addr_lp = input->wptr_addr;
775 mes_reset_queue_pkt.vmid_id_lp = input->vmid;
776 } else {
777 mes_reset_queue_pkt.reset_queue_only = 1;
778 mes_reset_queue_pkt.doorbell_offset = input->doorbell_offset;
779 }
780
781 return mes_v11_0_submit_pkt_and_poll_completion(mes,
782 &mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt),
783 offsetof(union MESAPI__RESET, api_status));
784 }
785
786 static const struct amdgpu_mes_funcs mes_v11_0_funcs = {
787 .add_hw_queue = mes_v11_0_add_hw_queue,
788 .remove_hw_queue = mes_v11_0_remove_hw_queue,
789 .map_legacy_queue = mes_v11_0_map_legacy_queue,
790 .unmap_legacy_queue = mes_v11_0_unmap_legacy_queue,
791 .suspend_gang = mes_v11_0_suspend_gang,
792 .resume_gang = mes_v11_0_resume_gang,
793 .misc_op = mes_v11_0_misc_op,
794 .reset_hw_queue = mes_v11_0_reset_hw_queue,
795 };
796
mes_v11_0_allocate_ucode_buffer(struct amdgpu_device * adev,enum amdgpu_mes_pipe pipe)797 static int mes_v11_0_allocate_ucode_buffer(struct amdgpu_device *adev,
798 enum amdgpu_mes_pipe pipe)
799 {
800 int r;
801 const struct mes_firmware_header_v1_0 *mes_hdr;
802 const __le32 *fw_data;
803 unsigned fw_size;
804
805 mes_hdr = (const struct mes_firmware_header_v1_0 *)
806 adev->mes.fw[pipe]->data;
807
808 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data +
809 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes));
810 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes);
811
812 r = amdgpu_bo_create_reserved(adev, fw_size,
813 PAGE_SIZE,
814 AMDGPU_GEM_DOMAIN_VRAM |
815 AMDGPU_GEM_DOMAIN_GTT,
816 &adev->mes.ucode_fw_obj[pipe],
817 &adev->mes.ucode_fw_gpu_addr[pipe],
818 (void **)&adev->mes.ucode_fw_ptr[pipe]);
819 if (r) {
820 dev_err(adev->dev, "(%d) failed to create mes fw bo\n", r);
821 return r;
822 }
823
824 memcpy(adev->mes.ucode_fw_ptr[pipe], fw_data, fw_size);
825
826 amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[pipe]);
827 amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[pipe]);
828
829 return 0;
830 }
831
mes_v11_0_allocate_ucode_data_buffer(struct amdgpu_device * adev,enum amdgpu_mes_pipe pipe)832 static int mes_v11_0_allocate_ucode_data_buffer(struct amdgpu_device *adev,
833 enum amdgpu_mes_pipe pipe)
834 {
835 int r;
836 const struct mes_firmware_header_v1_0 *mes_hdr;
837 const __le32 *fw_data;
838 unsigned fw_size;
839
840 mes_hdr = (const struct mes_firmware_header_v1_0 *)
841 adev->mes.fw[pipe]->data;
842
843 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data +
844 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes));
845 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes);
846
847 if (fw_size > GFX_MES_DRAM_SIZE) {
848 dev_err(adev->dev, "PIPE%d ucode data fw size (%d) is greater than dram size (%d)\n",
849 pipe, fw_size, GFX_MES_DRAM_SIZE);
850 return -EINVAL;
851 }
852
853 r = amdgpu_bo_create_reserved(adev, GFX_MES_DRAM_SIZE,
854 64 * 1024,
855 AMDGPU_GEM_DOMAIN_VRAM |
856 AMDGPU_GEM_DOMAIN_GTT,
857 &adev->mes.data_fw_obj[pipe],
858 &adev->mes.data_fw_gpu_addr[pipe],
859 (void **)&adev->mes.data_fw_ptr[pipe]);
860 if (r) {
861 dev_err(adev->dev, "(%d) failed to create mes data fw bo\n", r);
862 return r;
863 }
864
865 memcpy(adev->mes.data_fw_ptr[pipe], fw_data, fw_size);
866
867 amdgpu_bo_kunmap(adev->mes.data_fw_obj[pipe]);
868 amdgpu_bo_unreserve(adev->mes.data_fw_obj[pipe]);
869
870 return 0;
871 }
872
mes_v11_0_free_ucode_buffers(struct amdgpu_device * adev,enum amdgpu_mes_pipe pipe)873 static void mes_v11_0_free_ucode_buffers(struct amdgpu_device *adev,
874 enum amdgpu_mes_pipe pipe)
875 {
876 amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[pipe],
877 &adev->mes.data_fw_gpu_addr[pipe],
878 (void **)&adev->mes.data_fw_ptr[pipe]);
879
880 amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[pipe],
881 &adev->mes.ucode_fw_gpu_addr[pipe],
882 (void **)&adev->mes.ucode_fw_ptr[pipe]);
883 }
884
mes_v11_0_get_fw_version(struct amdgpu_device * adev)885 static void mes_v11_0_get_fw_version(struct amdgpu_device *adev)
886 {
887 int pipe;
888
889 /* return early if we have already fetched these */
890 if (adev->mes.sched_version && adev->mes.kiq_version)
891 return;
892
893 /* get MES scheduler/KIQ versions */
894 mutex_lock(&adev->srbm_mutex);
895
896 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
897 soc21_grbm_select(adev, 3, pipe, 0, 0);
898
899 if (pipe == AMDGPU_MES_SCHED_PIPE)
900 adev->mes.sched_version =
901 RREG32_SOC15(GC, 0, regCP_MES_GP3_LO);
902 else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq)
903 adev->mes.kiq_version =
904 RREG32_SOC15(GC, 0, regCP_MES_GP3_LO);
905 }
906
907 soc21_grbm_select(adev, 0, 0, 0, 0);
908 mutex_unlock(&adev->srbm_mutex);
909 }
910
mes_v11_0_enable(struct amdgpu_device * adev,bool enable)911 static void mes_v11_0_enable(struct amdgpu_device *adev, bool enable)
912 {
913 uint64_t ucode_addr;
914 uint32_t pipe, data = 0;
915
916 if (enable) {
917 if (amdgpu_mes_log_enable) {
918 WREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_LO,
919 lower_32_bits(adev->mes.event_log_gpu_addr + AMDGPU_MES_LOG_BUFFER_SIZE));
920 WREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_HI,
921 upper_32_bits(adev->mes.event_log_gpu_addr + AMDGPU_MES_LOG_BUFFER_SIZE));
922 dev_info(adev->dev, "Setup CP MES MSCRATCH address : 0x%x. 0x%x\n",
923 RREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_HI),
924 RREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_LO));
925 }
926
927 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL);
928 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1);
929 data = REG_SET_FIELD(data, CP_MES_CNTL,
930 MES_PIPE1_RESET, adev->enable_mes_kiq ? 1 : 0);
931 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data);
932
933 mutex_lock(&adev->srbm_mutex);
934 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
935 if (!adev->enable_mes_kiq &&
936 pipe == AMDGPU_MES_KIQ_PIPE)
937 continue;
938
939 soc21_grbm_select(adev, 3, pipe, 0, 0);
940
941 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2;
942 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START,
943 lower_32_bits(ucode_addr));
944 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI,
945 upper_32_bits(ucode_addr));
946 }
947 soc21_grbm_select(adev, 0, 0, 0, 0);
948 mutex_unlock(&adev->srbm_mutex);
949
950 /* unhalt MES and activate pipe0 */
951 data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1);
952 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE,
953 adev->enable_mes_kiq ? 1 : 0);
954 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data);
955
956 if (amdgpu_emu_mode)
957 msleep(100);
958 else
959 udelay(500);
960 } else {
961 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL);
962 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0);
963 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 0);
964 data = REG_SET_FIELD(data, CP_MES_CNTL,
965 MES_INVALIDATE_ICACHE, 1);
966 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1);
967 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET,
968 adev->enable_mes_kiq ? 1 : 0);
969 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1);
970 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data);
971 }
972 }
973
974 /* This function is for backdoor MES firmware */
mes_v11_0_load_microcode(struct amdgpu_device * adev,enum amdgpu_mes_pipe pipe,bool prime_icache)975 static int mes_v11_0_load_microcode(struct amdgpu_device *adev,
976 enum amdgpu_mes_pipe pipe, bool prime_icache)
977 {
978 int r;
979 uint32_t data;
980 uint64_t ucode_addr;
981
982 mes_v11_0_enable(adev, false);
983
984 if (!adev->mes.fw[pipe])
985 return -EINVAL;
986
987 r = mes_v11_0_allocate_ucode_buffer(adev, pipe);
988 if (r)
989 return r;
990
991 r = mes_v11_0_allocate_ucode_data_buffer(adev, pipe);
992 if (r) {
993 mes_v11_0_free_ucode_buffers(adev, pipe);
994 return r;
995 }
996
997 mutex_lock(&adev->srbm_mutex);
998 /* me=3, pipe=0, queue=0 */
999 soc21_grbm_select(adev, 3, pipe, 0, 0);
1000
1001 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_CNTL, 0);
1002
1003 /* set ucode start address */
1004 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2;
1005 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START,
1006 lower_32_bits(ucode_addr));
1007 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI,
1008 upper_32_bits(ucode_addr));
1009
1010 /* set ucode fimrware address */
1011 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_LO,
1012 lower_32_bits(adev->mes.ucode_fw_gpu_addr[pipe]));
1013 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_HI,
1014 upper_32_bits(adev->mes.ucode_fw_gpu_addr[pipe]));
1015
1016 /* set ucode instruction cache boundary to 2M-1 */
1017 WREG32_SOC15(GC, 0, regCP_MES_MIBOUND_LO, 0x1FFFFF);
1018
1019 /* set ucode data firmware address */
1020 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_LO,
1021 lower_32_bits(adev->mes.data_fw_gpu_addr[pipe]));
1022 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_HI,
1023 upper_32_bits(adev->mes.data_fw_gpu_addr[pipe]));
1024
1025 /* Set 0x7FFFF (512K-1) to CP_MES_MDBOUND_LO */
1026 WREG32_SOC15(GC, 0, regCP_MES_MDBOUND_LO, 0x7FFFF);
1027
1028 if (prime_icache) {
1029 /* invalidate ICACHE */
1030 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL);
1031 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0);
1032 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1);
1033 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data);
1034
1035 /* prime the ICACHE. */
1036 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL);
1037 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1);
1038 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data);
1039 }
1040
1041 soc21_grbm_select(adev, 0, 0, 0, 0);
1042 mutex_unlock(&adev->srbm_mutex);
1043
1044 return 0;
1045 }
1046
mes_v11_0_allocate_eop_buf(struct amdgpu_device * adev,enum amdgpu_mes_pipe pipe)1047 static int mes_v11_0_allocate_eop_buf(struct amdgpu_device *adev,
1048 enum amdgpu_mes_pipe pipe)
1049 {
1050 int r;
1051 u32 *eop;
1052
1053 r = amdgpu_bo_create_reserved(adev, MES_EOP_SIZE, PAGE_SIZE,
1054 AMDGPU_GEM_DOMAIN_GTT,
1055 &adev->mes.eop_gpu_obj[pipe],
1056 &adev->mes.eop_gpu_addr[pipe],
1057 (void **)&eop);
1058 if (r) {
1059 dev_warn(adev->dev, "(%d) create EOP bo failed\n", r);
1060 return r;
1061 }
1062
1063 memset(eop, 0,
1064 adev->mes.eop_gpu_obj[pipe]->tbo.base.size);
1065
1066 amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[pipe]);
1067 amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[pipe]);
1068
1069 return 0;
1070 }
1071
mes_v11_0_mqd_init(struct amdgpu_ring * ring)1072 static int mes_v11_0_mqd_init(struct amdgpu_ring *ring)
1073 {
1074 struct v11_compute_mqd *mqd = ring->mqd_ptr;
1075 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
1076 uint32_t tmp;
1077
1078 memset(mqd, 0, sizeof(*mqd));
1079
1080 mqd->header = 0xC0310800;
1081 mqd->compute_pipelinestat_enable = 0x00000001;
1082 mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
1083 mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
1084 mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
1085 mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
1086 mqd->compute_misc_reserved = 0x00000007;
1087
1088 eop_base_addr = ring->eop_gpu_addr >> 8;
1089
1090 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
1091 tmp = regCP_HQD_EOP_CONTROL_DEFAULT;
1092 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
1093 (order_base_2(MES_EOP_SIZE / 4) - 1));
1094
1095 mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr);
1096 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
1097 mqd->cp_hqd_eop_control = tmp;
1098
1099 /* disable the queue if it's active */
1100 ring->wptr = 0;
1101 mqd->cp_hqd_pq_rptr = 0;
1102 mqd->cp_hqd_pq_wptr_lo = 0;
1103 mqd->cp_hqd_pq_wptr_hi = 0;
1104
1105 /* set the pointer to the MQD */
1106 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
1107 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
1108
1109 /* set MQD vmid to 0 */
1110 tmp = regCP_MQD_CONTROL_DEFAULT;
1111 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
1112 mqd->cp_mqd_control = tmp;
1113
1114 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
1115 hqd_gpu_addr = ring->gpu_addr >> 8;
1116 mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr);
1117 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
1118
1119 /* set the wb address whether it's enabled or not */
1120 wb_gpu_addr = ring->rptr_gpu_addr;
1121 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
1122 mqd->cp_hqd_pq_rptr_report_addr_hi =
1123 upper_32_bits(wb_gpu_addr) & 0xffff;
1124
1125 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
1126 wb_gpu_addr = ring->wptr_gpu_addr;
1127 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8;
1128 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
1129
1130 /* set up the HQD, this is similar to CP_RB0_CNTL */
1131 tmp = regCP_HQD_PQ_CONTROL_DEFAULT;
1132 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
1133 (order_base_2(ring->ring_size / 4) - 1));
1134 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
1135 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
1136 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1);
1137 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
1138 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
1139 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
1140 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1);
1141 mqd->cp_hqd_pq_control = tmp;
1142
1143 /* enable doorbell */
1144 tmp = 0;
1145 if (ring->use_doorbell) {
1146 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1147 DOORBELL_OFFSET, ring->doorbell_index);
1148 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1149 DOORBELL_EN, 1);
1150 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1151 DOORBELL_SOURCE, 0);
1152 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1153 DOORBELL_HIT, 0);
1154 } else
1155 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1156 DOORBELL_EN, 0);
1157 mqd->cp_hqd_pq_doorbell_control = tmp;
1158
1159 mqd->cp_hqd_vmid = 0;
1160 /* activate the queue */
1161 mqd->cp_hqd_active = 1;
1162
1163 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT;
1164 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE,
1165 PRELOAD_SIZE, 0x55);
1166 mqd->cp_hqd_persistent_state = tmp;
1167
1168 mqd->cp_hqd_ib_control = regCP_HQD_IB_CONTROL_DEFAULT;
1169 mqd->cp_hqd_iq_timer = regCP_HQD_IQ_TIMER_DEFAULT;
1170 mqd->cp_hqd_quantum = regCP_HQD_QUANTUM_DEFAULT;
1171
1172 amdgpu_device_flush_hdp(ring->adev, NULL);
1173 return 0;
1174 }
1175
mes_v11_0_queue_init_register(struct amdgpu_ring * ring)1176 static void mes_v11_0_queue_init_register(struct amdgpu_ring *ring)
1177 {
1178 struct v11_compute_mqd *mqd = ring->mqd_ptr;
1179 struct amdgpu_device *adev = ring->adev;
1180 uint32_t data = 0;
1181
1182 mutex_lock(&adev->srbm_mutex);
1183 soc21_grbm_select(adev, 3, ring->pipe, 0, 0);
1184
1185 /* set CP_HQD_VMID.VMID = 0. */
1186 data = RREG32_SOC15(GC, 0, regCP_HQD_VMID);
1187 data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0);
1188 WREG32_SOC15(GC, 0, regCP_HQD_VMID, data);
1189
1190 /* set CP_HQD_PQ_DOORBELL_CONTROL.DOORBELL_EN=0 */
1191 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL);
1192 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL,
1193 DOORBELL_EN, 0);
1194 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data);
1195
1196 /* set CP_MQD_BASE_ADDR/HI with the MQD base address */
1197 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo);
1198 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
1199
1200 /* set CP_MQD_CONTROL.VMID=0 */
1201 data = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL);
1202 data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0);
1203 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 0);
1204
1205 /* set CP_HQD_PQ_BASE/HI with the ring buffer base address */
1206 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo);
1207 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi);
1208
1209 /* set CP_HQD_PQ_RPTR_REPORT_ADDR/HI */
1210 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR,
1211 mqd->cp_hqd_pq_rptr_report_addr_lo);
1212 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
1213 mqd->cp_hqd_pq_rptr_report_addr_hi);
1214
1215 /* set CP_HQD_PQ_CONTROL */
1216 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control);
1217
1218 /* set CP_HQD_PQ_WPTR_POLL_ADDR/HI */
1219 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR,
1220 mqd->cp_hqd_pq_wptr_poll_addr_lo);
1221 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI,
1222 mqd->cp_hqd_pq_wptr_poll_addr_hi);
1223
1224 /* set CP_HQD_PQ_DOORBELL_CONTROL */
1225 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL,
1226 mqd->cp_hqd_pq_doorbell_control);
1227
1228 /* set CP_HQD_PERSISTENT_STATE.PRELOAD_SIZE=0x53 */
1229 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state);
1230
1231 /* set CP_HQD_ACTIVE.ACTIVE=1 */
1232 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, mqd->cp_hqd_active);
1233
1234 soc21_grbm_select(adev, 0, 0, 0, 0);
1235 mutex_unlock(&adev->srbm_mutex);
1236 }
1237
mes_v11_0_kiq_enable_queue(struct amdgpu_device * adev)1238 static int mes_v11_0_kiq_enable_queue(struct amdgpu_device *adev)
1239 {
1240 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
1241 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring;
1242 int r;
1243
1244 if (!kiq->pmf || !kiq->pmf->kiq_map_queues)
1245 return -EINVAL;
1246
1247 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size);
1248 if (r) {
1249 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
1250 return r;
1251 }
1252
1253 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring[0]);
1254
1255 return amdgpu_ring_test_helper(kiq_ring);
1256 }
1257
mes_v11_0_queue_init(struct amdgpu_device * adev,enum amdgpu_mes_pipe pipe)1258 static int mes_v11_0_queue_init(struct amdgpu_device *adev,
1259 enum amdgpu_mes_pipe pipe)
1260 {
1261 struct amdgpu_ring *ring;
1262 int r;
1263
1264 if (pipe == AMDGPU_MES_KIQ_PIPE)
1265 ring = &adev->gfx.kiq[0].ring;
1266 else if (pipe == AMDGPU_MES_SCHED_PIPE)
1267 ring = &adev->mes.ring[0];
1268 else
1269 BUG();
1270
1271 if ((pipe == AMDGPU_MES_SCHED_PIPE) &&
1272 (amdgpu_in_reset(adev) || adev->in_suspend)) {
1273 *(ring->wptr_cpu_addr) = 0;
1274 *(ring->rptr_cpu_addr) = 0;
1275 amdgpu_ring_clear_ring(ring);
1276 }
1277
1278 r = mes_v11_0_mqd_init(ring);
1279 if (r)
1280 return r;
1281
1282 if (pipe == AMDGPU_MES_SCHED_PIPE) {
1283 r = mes_v11_0_kiq_enable_queue(adev);
1284 if (r)
1285 return r;
1286 } else {
1287 mes_v11_0_queue_init_register(ring);
1288 }
1289
1290 return 0;
1291 }
1292
mes_v11_0_ring_init(struct amdgpu_device * adev)1293 static int mes_v11_0_ring_init(struct amdgpu_device *adev)
1294 {
1295 struct amdgpu_ring *ring;
1296
1297 ring = &adev->mes.ring[0];
1298
1299 ring->funcs = &mes_v11_0_ring_funcs;
1300
1301 ring->me = 3;
1302 ring->pipe = 0;
1303 ring->queue = 0;
1304
1305 ring->ring_obj = NULL;
1306 ring->use_doorbell = true;
1307 ring->doorbell_index = adev->doorbell_index.mes_ring0 << 1;
1308 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_SCHED_PIPE];
1309 ring->no_scheduler = true;
1310 sprintf(ring->name, "mes_%d.%d.%d", ring->me, ring->pipe, ring->queue);
1311
1312 return amdgpu_ring_init(adev, ring, 1024, NULL, 0,
1313 AMDGPU_RING_PRIO_DEFAULT, NULL);
1314 }
1315
mes_v11_0_kiq_ring_init(struct amdgpu_device * adev)1316 static int mes_v11_0_kiq_ring_init(struct amdgpu_device *adev)
1317 {
1318 struct amdgpu_ring *ring;
1319
1320 spin_lock_init(&adev->gfx.kiq[0].ring_lock);
1321
1322 ring = &adev->gfx.kiq[0].ring;
1323
1324 ring->me = 3;
1325 ring->pipe = 1;
1326 ring->queue = 0;
1327
1328 ring->adev = NULL;
1329 ring->ring_obj = NULL;
1330 ring->use_doorbell = true;
1331 ring->doorbell_index = adev->doorbell_index.mes_ring1 << 1;
1332 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_KIQ_PIPE];
1333 ring->no_scheduler = true;
1334 sprintf(ring->name, "mes_kiq_%d.%d.%d",
1335 ring->me, ring->pipe, ring->queue);
1336
1337 return amdgpu_ring_init(adev, ring, 1024, NULL, 0,
1338 AMDGPU_RING_PRIO_DEFAULT, NULL);
1339 }
1340
mes_v11_0_mqd_sw_init(struct amdgpu_device * adev,enum amdgpu_mes_pipe pipe)1341 static int mes_v11_0_mqd_sw_init(struct amdgpu_device *adev,
1342 enum amdgpu_mes_pipe pipe)
1343 {
1344 int r, mqd_size = sizeof(struct v11_compute_mqd);
1345 struct amdgpu_ring *ring;
1346
1347 if (pipe == AMDGPU_MES_KIQ_PIPE)
1348 ring = &adev->gfx.kiq[0].ring;
1349 else if (pipe == AMDGPU_MES_SCHED_PIPE)
1350 ring = &adev->mes.ring[0];
1351 else
1352 BUG();
1353
1354 if (ring->mqd_obj)
1355 return 0;
1356
1357 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,
1358 AMDGPU_GEM_DOMAIN_VRAM |
1359 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj,
1360 &ring->mqd_gpu_addr, &ring->mqd_ptr);
1361 if (r) {
1362 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r);
1363 return r;
1364 }
1365
1366 memset(ring->mqd_ptr, 0, mqd_size);
1367
1368 /* prepare MQD backup */
1369 adev->mes.mqd_backup[pipe] = kmalloc(mqd_size, GFP_KERNEL);
1370 if (!adev->mes.mqd_backup[pipe]) {
1371 dev_warn(adev->dev,
1372 "no memory to create MQD backup for ring %s\n",
1373 ring->name);
1374 return -ENOMEM;
1375 }
1376
1377 return 0;
1378 }
1379
mes_v11_0_sw_init(struct amdgpu_ip_block * ip_block)1380 static int mes_v11_0_sw_init(struct amdgpu_ip_block *ip_block)
1381 {
1382 struct amdgpu_device *adev = ip_block->adev;
1383 int pipe, r, bo_size;
1384
1385 adev->mes.funcs = &mes_v11_0_funcs;
1386 adev->mes.kiq_hw_init = &mes_v11_0_kiq_hw_init;
1387 adev->mes.kiq_hw_fini = &mes_v11_0_kiq_hw_fini;
1388
1389 adev->mes.event_log_size = AMDGPU_MES_LOG_BUFFER_SIZE + AMDGPU_MES_MSCRATCH_SIZE;
1390
1391 r = amdgpu_mes_init(adev);
1392 if (r)
1393 return r;
1394
1395 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
1396 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE)
1397 continue;
1398
1399 r = mes_v11_0_allocate_eop_buf(adev, pipe);
1400 if (r)
1401 return r;
1402
1403 r = mes_v11_0_mqd_sw_init(adev, pipe);
1404 if (r)
1405 return r;
1406 }
1407
1408 if (adev->enable_mes_kiq) {
1409 r = mes_v11_0_kiq_ring_init(adev);
1410 if (r)
1411 return r;
1412 }
1413
1414 r = mes_v11_0_ring_init(adev);
1415 if (r)
1416 return r;
1417
1418 bo_size = AMDGPU_GPU_PAGE_SIZE;
1419 if (amdgpu_sriov_is_mes_info_enable(adev))
1420 bo_size += MES11_HW_RESOURCE_1_SIZE;
1421
1422 /* Only needed for AMDGPU_MES_SCHED_PIPE on MES 11*/
1423 r = amdgpu_bo_create_kernel(adev,
1424 bo_size,
1425 PAGE_SIZE,
1426 AMDGPU_GEM_DOMAIN_VRAM,
1427 &adev->mes.resource_1[0],
1428 &adev->mes.resource_1_gpu_addr[0],
1429 &adev->mes.resource_1_addr[0]);
1430 if (r) {
1431 dev_err(adev->dev, "(%d) failed to create mes resource_1 bo\n", r);
1432 return r;
1433 }
1434
1435 return 0;
1436 }
1437
mes_v11_0_sw_fini(struct amdgpu_ip_block * ip_block)1438 static int mes_v11_0_sw_fini(struct amdgpu_ip_block *ip_block)
1439 {
1440 struct amdgpu_device *adev = ip_block->adev;
1441 int pipe;
1442
1443 amdgpu_bo_free_kernel(&adev->mes.resource_1[0], &adev->mes.resource_1_gpu_addr[0],
1444 &adev->mes.resource_1_addr[0]);
1445
1446 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
1447 kfree(adev->mes.mqd_backup[pipe]);
1448
1449 amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[pipe],
1450 &adev->mes.eop_gpu_addr[pipe],
1451 NULL);
1452 amdgpu_ucode_release(&adev->mes.fw[pipe]);
1453 }
1454
1455 amdgpu_bo_free_kernel(&adev->gfx.kiq[0].ring.mqd_obj,
1456 &adev->gfx.kiq[0].ring.mqd_gpu_addr,
1457 &adev->gfx.kiq[0].ring.mqd_ptr);
1458
1459 amdgpu_bo_free_kernel(&adev->mes.ring[0].mqd_obj,
1460 &adev->mes.ring[0].mqd_gpu_addr,
1461 &adev->mes.ring[0].mqd_ptr);
1462
1463 amdgpu_ring_fini(&adev->gfx.kiq[0].ring);
1464 amdgpu_ring_fini(&adev->mes.ring[0]);
1465
1466 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
1467 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_KIQ_PIPE);
1468 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_SCHED_PIPE);
1469 }
1470
1471 amdgpu_mes_fini(adev);
1472 return 0;
1473 }
1474
mes_v11_0_kiq_dequeue(struct amdgpu_ring * ring)1475 static void mes_v11_0_kiq_dequeue(struct amdgpu_ring *ring)
1476 {
1477 uint32_t data;
1478 int i;
1479 struct amdgpu_device *adev = ring->adev;
1480
1481 mutex_lock(&adev->srbm_mutex);
1482 soc21_grbm_select(adev, 3, ring->pipe, 0, 0);
1483
1484 /* disable the queue if it's active */
1485 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) {
1486 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1);
1487 for (i = 0; i < adev->usec_timeout; i++) {
1488 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1))
1489 break;
1490 udelay(1);
1491 }
1492 }
1493 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL);
1494 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL,
1495 DOORBELL_EN, 0);
1496 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL,
1497 DOORBELL_HIT, 1);
1498 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data);
1499
1500 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 0);
1501
1502 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 0);
1503 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 0);
1504 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 0);
1505
1506 soc21_grbm_select(adev, 0, 0, 0, 0);
1507 mutex_unlock(&adev->srbm_mutex);
1508 }
1509
mes_v11_0_kiq_setting(struct amdgpu_ring * ring)1510 static void mes_v11_0_kiq_setting(struct amdgpu_ring *ring)
1511 {
1512 uint32_t tmp;
1513 struct amdgpu_device *adev = ring->adev;
1514
1515 /* tell RLC which is KIQ queue */
1516 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);
1517 tmp &= 0xffffff00;
1518 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
1519 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp | 0x80);
1520 }
1521
mes_v11_0_kiq_clear(struct amdgpu_device * adev)1522 static void mes_v11_0_kiq_clear(struct amdgpu_device *adev)
1523 {
1524 uint32_t tmp;
1525
1526 /* tell RLC which is KIQ dequeue */
1527 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);
1528 tmp &= ~RLC_CP_SCHEDULERS__scheduler0_MASK;
1529 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp);
1530 }
1531
mes_v11_0_kiq_hw_init(struct amdgpu_device * adev)1532 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev)
1533 {
1534 int r = 0;
1535 struct amdgpu_ip_block *ip_block;
1536
1537 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
1538
1539 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_SCHED_PIPE, false);
1540 if (r) {
1541 DRM_ERROR("failed to load MES fw, r=%d\n", r);
1542 return r;
1543 }
1544
1545 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_KIQ_PIPE, true);
1546 if (r) {
1547 DRM_ERROR("failed to load MES kiq fw, r=%d\n", r);
1548 return r;
1549 }
1550
1551 }
1552
1553 mes_v11_0_enable(adev, true);
1554
1555 mes_v11_0_get_fw_version(adev);
1556
1557 mes_v11_0_kiq_setting(&adev->gfx.kiq[0].ring);
1558
1559 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_MES);
1560 if (unlikely(!ip_block)) {
1561 dev_err(adev->dev, "Failed to get MES handle\n");
1562 return -EINVAL;
1563 }
1564
1565 r = mes_v11_0_queue_init(adev, AMDGPU_MES_KIQ_PIPE);
1566 if (r)
1567 goto failure;
1568
1569 if ((adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x47)
1570 adev->mes.enable_legacy_queue_map = true;
1571 else
1572 adev->mes.enable_legacy_queue_map = false;
1573
1574 if (adev->mes.enable_legacy_queue_map) {
1575 r = mes_v11_0_hw_init(ip_block);
1576 if (r)
1577 goto failure;
1578 }
1579
1580 return r;
1581
1582 failure:
1583 mes_v11_0_hw_fini(ip_block);
1584 return r;
1585 }
1586
mes_v11_0_kiq_hw_fini(struct amdgpu_device * adev)1587 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev)
1588 {
1589 if (adev->mes.ring[0].sched.ready) {
1590 mes_v11_0_kiq_dequeue(&adev->mes.ring[0]);
1591 adev->mes.ring[0].sched.ready = false;
1592 }
1593
1594 if (amdgpu_sriov_vf(adev)) {
1595 mes_v11_0_kiq_dequeue(&adev->gfx.kiq[0].ring);
1596 mes_v11_0_kiq_clear(adev);
1597 }
1598
1599 mes_v11_0_enable(adev, false);
1600
1601 return 0;
1602 }
1603
mes_v11_0_hw_init(struct amdgpu_ip_block * ip_block)1604 static int mes_v11_0_hw_init(struct amdgpu_ip_block *ip_block)
1605 {
1606 int r;
1607 struct amdgpu_device *adev = ip_block->adev;
1608
1609 if (adev->mes.ring[0].sched.ready)
1610 goto out;
1611
1612 if (!adev->enable_mes_kiq) {
1613 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
1614 r = mes_v11_0_load_microcode(adev,
1615 AMDGPU_MES_SCHED_PIPE, true);
1616 if (r) {
1617 DRM_ERROR("failed to MES fw, r=%d\n", r);
1618 return r;
1619 }
1620 }
1621
1622 mes_v11_0_enable(adev, true);
1623 }
1624
1625 r = mes_v11_0_queue_init(adev, AMDGPU_MES_SCHED_PIPE);
1626 if (r)
1627 goto failure;
1628
1629 r = mes_v11_0_set_hw_resources(&adev->mes);
1630 if (r)
1631 goto failure;
1632
1633 if ((adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x50) {
1634 r = mes_v11_0_set_hw_resources_1(&adev->mes);
1635 if (r) {
1636 DRM_ERROR("failed mes_v11_0_set_hw_resources_1, r=%d\n", r);
1637 goto failure;
1638 }
1639 }
1640
1641 r = mes_v11_0_query_sched_status(&adev->mes);
1642 if (r) {
1643 DRM_ERROR("MES is busy\n");
1644 goto failure;
1645 }
1646
1647 r = amdgpu_mes_update_enforce_isolation(adev);
1648 if (r)
1649 goto failure;
1650
1651 out:
1652 /*
1653 * Disable KIQ ring usage from the driver once MES is enabled.
1654 * MES uses KIQ ring exclusively so driver cannot access KIQ ring
1655 * with MES enabled.
1656 */
1657 adev->gfx.kiq[0].ring.sched.ready = false;
1658 adev->mes.ring[0].sched.ready = true;
1659
1660 return 0;
1661
1662 failure:
1663 mes_v11_0_hw_fini(ip_block);
1664 return r;
1665 }
1666
mes_v11_0_hw_fini(struct amdgpu_ip_block * ip_block)1667 static int mes_v11_0_hw_fini(struct amdgpu_ip_block *ip_block)
1668 {
1669 return 0;
1670 }
1671
mes_v11_0_suspend(struct amdgpu_ip_block * ip_block)1672 static int mes_v11_0_suspend(struct amdgpu_ip_block *ip_block)
1673 {
1674 return mes_v11_0_hw_fini(ip_block);
1675 }
1676
mes_v11_0_resume(struct amdgpu_ip_block * ip_block)1677 static int mes_v11_0_resume(struct amdgpu_ip_block *ip_block)
1678 {
1679 return mes_v11_0_hw_init(ip_block);
1680 }
1681
mes_v11_0_early_init(struct amdgpu_ip_block * ip_block)1682 static int mes_v11_0_early_init(struct amdgpu_ip_block *ip_block)
1683 {
1684 struct amdgpu_device *adev = ip_block->adev;
1685 int pipe, r;
1686
1687 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
1688 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE)
1689 continue;
1690 r = amdgpu_mes_init_microcode(adev, pipe);
1691 if (r)
1692 return r;
1693 }
1694
1695 return 0;
1696 }
1697
1698 static const struct amd_ip_funcs mes_v11_0_ip_funcs = {
1699 .name = "mes_v11_0",
1700 .early_init = mes_v11_0_early_init,
1701 .late_init = NULL,
1702 .sw_init = mes_v11_0_sw_init,
1703 .sw_fini = mes_v11_0_sw_fini,
1704 .hw_init = mes_v11_0_hw_init,
1705 .hw_fini = mes_v11_0_hw_fini,
1706 .suspend = mes_v11_0_suspend,
1707 .resume = mes_v11_0_resume,
1708 };
1709
1710 const struct amdgpu_ip_block_version mes_v11_0_ip_block = {
1711 .type = AMD_IP_BLOCK_TYPE_MES,
1712 .major = 11,
1713 .minor = 0,
1714 .rev = 0,
1715 .funcs = &mes_v11_0_ip_funcs,
1716 };
1717