1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <linux/firmware.h>
25 #include <linux/module.h>
26 #include "amdgpu.h"
27 #include "soc15_common.h"
28 #include "soc21.h"
29 #include "gfx_v11_0.h"
30 #include "gc/gc_11_0_0_offset.h"
31 #include "gc/gc_11_0_0_sh_mask.h"
32 #include "gc/gc_11_0_0_default.h"
33 #include "v11_structs.h"
34 #include "mes_v11_api_def.h"
35
36 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes.bin");
37 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes_2.bin");
38 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes1.bin");
39 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes.bin");
40 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes_2.bin");
41 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes1.bin");
42 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes.bin");
43 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes_2.bin");
44 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes1.bin");
45 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes.bin");
46 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes_2.bin");
47 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes1.bin");
48 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes.bin");
49 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes_2.bin");
50 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes1.bin");
51 MODULE_FIRMWARE("amdgpu/gc_11_5_0_mes_2.bin");
52 MODULE_FIRMWARE("amdgpu/gc_11_5_0_mes1.bin");
53 MODULE_FIRMWARE("amdgpu/gc_11_5_1_mes_2.bin");
54 MODULE_FIRMWARE("amdgpu/gc_11_5_1_mes1.bin");
55 MODULE_FIRMWARE("amdgpu/gc_11_5_2_mes_2.bin");
56 MODULE_FIRMWARE("amdgpu/gc_11_5_2_mes1.bin");
57 MODULE_FIRMWARE("amdgpu/gc_11_5_3_mes_2.bin");
58 MODULE_FIRMWARE("amdgpu/gc_11_5_3_mes1.bin");
59 MODULE_FIRMWARE("amdgpu/gc_11_5_4_mes_2.bin");
60 MODULE_FIRMWARE("amdgpu/gc_11_5_4_mes1.bin");
61 MODULE_FIRMWARE("amdgpu/gc_11_5_6_mes_2.bin");
62 MODULE_FIRMWARE("amdgpu/gc_11_5_6_mes1.bin");
63 MODULE_FIRMWARE("amdgpu/gc_11_7_0_mes_2.bin");
64 MODULE_FIRMWARE("amdgpu/gc_11_7_0_mes1.bin");
65 MODULE_FIRMWARE("amdgpu/gc_11_7_1_mes_2.bin");
66 MODULE_FIRMWARE("amdgpu/gc_11_7_1_mes1.bin");
67
68 static int mes_v11_0_hw_init(struct amdgpu_ip_block *ip_block);
69 static int mes_v11_0_hw_fini(struct amdgpu_ip_block *ip_block);
70 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev, uint32_t xcc_id);
71 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev, uint32_t xcc_id);
72
73 #define MES_EOP_SIZE 2048
74 #define GFX_MES_DRAM_SIZE 0x80000
75 #define MES11_HW_RESOURCE_1_SIZE (128 * AMDGPU_GPU_PAGE_SIZE)
76
77 #define MES11_HUNG_DB_OFFSET_ARRAY_SIZE 8 /* [0:3] = db offset, [4:7] = hqd info */
78 #define MES11_HUNG_HQD_INFO_OFFSET 4
79
mes_v11_0_ring_set_wptr(struct amdgpu_ring * ring)80 static void mes_v11_0_ring_set_wptr(struct amdgpu_ring *ring)
81 {
82 struct amdgpu_device *adev = ring->adev;
83
84 if (ring->use_doorbell) {
85 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
86 ring->wptr);
87 WDOORBELL64(ring->doorbell_index, ring->wptr);
88 } else {
89 dev_warn_once(adev->dev, "%s requires doorbell!\n", __func__);
90 }
91 }
92
mes_v11_0_ring_get_rptr(struct amdgpu_ring * ring)93 static u64 mes_v11_0_ring_get_rptr(struct amdgpu_ring *ring)
94 {
95 return *ring->rptr_cpu_addr;
96 }
97
mes_v11_0_ring_get_wptr(struct amdgpu_ring * ring)98 static u64 mes_v11_0_ring_get_wptr(struct amdgpu_ring *ring)
99 {
100 struct amdgpu_device *adev = ring->adev;
101 u64 wptr;
102
103 if (ring->use_doorbell) {
104 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
105 } else {
106 dev_warn_once(adev->dev, "%s requires doorbell!\n", __func__);
107 wptr = 0;
108 }
109 return wptr;
110 }
111
112 static const struct amdgpu_ring_funcs mes_v11_0_ring_funcs = {
113 .type = AMDGPU_RING_TYPE_MES,
114 .align_mask = 1,
115 .nop = 0,
116 .support_64bit_ptrs = true,
117 .get_rptr = mes_v11_0_ring_get_rptr,
118 .get_wptr = mes_v11_0_ring_get_wptr,
119 .set_wptr = mes_v11_0_ring_set_wptr,
120 .insert_nop = amdgpu_ring_insert_nop,
121 };
122
123 static const char *mes_v11_0_opcodes[] = {
124 "SET_HW_RSRC",
125 "SET_SCHEDULING_CONFIG",
126 "ADD_QUEUE",
127 "REMOVE_QUEUE",
128 "PERFORM_YIELD",
129 "SET_GANG_PRIORITY_LEVEL",
130 "SUSPEND",
131 "RESUME",
132 "RESET",
133 "SET_LOG_BUFFER",
134 "CHANGE_GANG_PRORITY",
135 "QUERY_SCHEDULER_STATUS",
136 "PROGRAM_GDS",
137 "SET_DEBUG_VMID",
138 "MISC",
139 "UPDATE_ROOT_PAGE_TABLE",
140 "AMD_LOG",
141 "unused",
142 "unused",
143 "SET_HW_RSRC_1",
144 };
145
146 static const char *mes_v11_0_misc_opcodes[] = {
147 "WRITE_REG",
148 "INV_GART",
149 "QUERY_STATUS",
150 "READ_REG",
151 "WAIT_REG_MEM",
152 "SET_SHADER_DEBUGGER",
153 };
154
mes_v11_0_get_op_string(union MESAPI__MISC * x_pkt)155 static const char *mes_v11_0_get_op_string(union MESAPI__MISC *x_pkt)
156 {
157 const char *op_str = NULL;
158
159 if (x_pkt->header.opcode < ARRAY_SIZE(mes_v11_0_opcodes))
160 op_str = mes_v11_0_opcodes[x_pkt->header.opcode];
161
162 return op_str;
163 }
164
mes_v11_0_get_misc_op_string(union MESAPI__MISC * x_pkt)165 static const char *mes_v11_0_get_misc_op_string(union MESAPI__MISC *x_pkt)
166 {
167 const char *op_str = NULL;
168
169 if ((x_pkt->header.opcode == MES_SCH_API_MISC) &&
170 (x_pkt->opcode < ARRAY_SIZE(mes_v11_0_misc_opcodes)))
171 op_str = mes_v11_0_misc_opcodes[x_pkt->opcode];
172
173 return op_str;
174 }
175
mes_v11_0_submit_pkt_and_poll_completion(struct amdgpu_mes * mes,void * pkt,int size,int api_status_off)176 static int mes_v11_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes,
177 void *pkt, int size,
178 int api_status_off)
179 {
180 union MESAPI__QUERY_MES_STATUS mes_status_pkt;
181 signed long timeout = 2100000; /* 2100 ms */
182 struct amdgpu_device *adev = mes->adev;
183 struct amdgpu_ring *ring = &mes->ring[0];
184 struct MES_API_STATUS *api_status;
185 union MESAPI__MISC *x_pkt = pkt;
186 const char *op_str, *misc_op_str;
187 unsigned long flags;
188 u64 status_gpu_addr;
189 u32 seq, status_offset;
190 u64 *status_ptr;
191 signed long r;
192 int ret;
193
194 if (x_pkt->header.opcode >= MES_SCH_API_MAX)
195 return -EINVAL;
196
197 if (amdgpu_emu_mode) {
198 timeout *= 100;
199 } else if (amdgpu_sriov_vf(adev)) {
200 /* Worst case in sriov where all other 15 VF timeout, each VF needs about 600ms */
201 timeout = 15 * 600 * 1000;
202 }
203
204 ret = amdgpu_wb_get(adev, &status_offset);
205 if (ret)
206 return ret;
207
208 status_gpu_addr = adev->wb.gpu_addr + (status_offset * 4);
209 status_ptr = (u64 *)&adev->wb.wb[status_offset];
210 *status_ptr = 0;
211
212 spin_lock_irqsave(&mes->ring_lock[0], flags);
213 r = amdgpu_ring_alloc(ring, (size + sizeof(mes_status_pkt)) / 4);
214 if (r)
215 goto error_unlock_free;
216
217 seq = ++ring->fence_drv.sync_seq;
218 r = amdgpu_fence_wait_polling(ring,
219 seq - ring->fence_drv.num_fences_mask,
220 timeout);
221 if (r < 1)
222 goto error_undo;
223
224 api_status = (struct MES_API_STATUS *)((char *)pkt + api_status_off);
225 api_status->api_completion_fence_addr = status_gpu_addr;
226 api_status->api_completion_fence_value = 1;
227
228 amdgpu_ring_write_multiple(ring, pkt, size / 4);
229
230 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt));
231 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER;
232 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS;
233 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
234 mes_status_pkt.api_status.api_completion_fence_addr =
235 ring->fence_drv.gpu_addr;
236 mes_status_pkt.api_status.api_completion_fence_value = seq;
237
238 amdgpu_ring_write_multiple(ring, &mes_status_pkt,
239 sizeof(mes_status_pkt) / 4);
240
241 amdgpu_ring_commit(ring);
242 spin_unlock_irqrestore(&mes->ring_lock[0], flags);
243
244 op_str = mes_v11_0_get_op_string(x_pkt);
245 misc_op_str = mes_v11_0_get_misc_op_string(x_pkt);
246
247 if (misc_op_str)
248 dev_dbg(adev->dev, "MES msg=%s (%s) was emitted\n", op_str,
249 misc_op_str);
250 else if (op_str)
251 dev_dbg(adev->dev, "MES msg=%s was emitted\n", op_str);
252 else
253 dev_dbg(adev->dev, "MES msg=%d was emitted\n",
254 x_pkt->header.opcode);
255
256 r = amdgpu_fence_wait_polling(ring, seq, timeout);
257 if (r < 1 || !*status_ptr) {
258
259 if (misc_op_str)
260 dev_err(adev->dev, "MES failed to respond to msg=%s (%s)\n",
261 op_str, misc_op_str);
262 else if (op_str)
263 dev_err(adev->dev, "MES failed to respond to msg=%s\n",
264 op_str);
265 else
266 dev_err(adev->dev, "MES failed to respond to msg=%d\n",
267 x_pkt->header.opcode);
268
269 while (halt_if_hws_hang)
270 schedule();
271
272 r = -ETIMEDOUT;
273 goto error_wb_free;
274 }
275
276 amdgpu_wb_free(adev, status_offset);
277 return 0;
278
279 error_undo:
280 dev_err(adev->dev, "MES ring buffer is full.\n");
281 amdgpu_ring_undo(ring);
282
283 error_unlock_free:
284 spin_unlock_irqrestore(&mes->ring_lock[0], flags);
285
286 error_wb_free:
287 amdgpu_wb_free(adev, status_offset);
288 return r;
289 }
290
convert_to_mes_queue_type(int queue_type)291 static int convert_to_mes_queue_type(int queue_type)
292 {
293 if (queue_type == AMDGPU_RING_TYPE_GFX)
294 return MES_QUEUE_TYPE_GFX;
295 else if (queue_type == AMDGPU_RING_TYPE_COMPUTE)
296 return MES_QUEUE_TYPE_COMPUTE;
297 else if (queue_type == AMDGPU_RING_TYPE_SDMA)
298 return MES_QUEUE_TYPE_SDMA;
299 else
300 WARN(1, "Invalid queue type %d\n", queue_type);
301 return MES_QUEUE_TYPE_GFX;
302 }
303
convert_to_mes_priority_level(int priority_level)304 static int convert_to_mes_priority_level(int priority_level)
305 {
306 switch (priority_level) {
307 case AMDGPU_MES_PRIORITY_LEVEL_LOW:
308 return AMD_PRIORITY_LEVEL_LOW;
309 case AMDGPU_MES_PRIORITY_LEVEL_NORMAL:
310 default:
311 return AMD_PRIORITY_LEVEL_NORMAL;
312 case AMDGPU_MES_PRIORITY_LEVEL_MEDIUM:
313 return AMD_PRIORITY_LEVEL_MEDIUM;
314 case AMDGPU_MES_PRIORITY_LEVEL_HIGH:
315 return AMD_PRIORITY_LEVEL_HIGH;
316 case AMDGPU_MES_PRIORITY_LEVEL_REALTIME:
317 return AMD_PRIORITY_LEVEL_REALTIME;
318 }
319 }
320
mes_v11_0_add_hw_queue(struct amdgpu_mes * mes,struct mes_add_queue_input * input)321 static int mes_v11_0_add_hw_queue(struct amdgpu_mes *mes,
322 struct mes_add_queue_input *input)
323 {
324 struct amdgpu_device *adev = mes->adev;
325 union MESAPI__ADD_QUEUE mes_add_queue_pkt;
326 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)];
327 uint32_t vm_cntx_cntl = hub->vm_cntx_cntl;
328
329 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt));
330
331 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;
332 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE;
333 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
334
335 mes_add_queue_pkt.process_id = input->process_id;
336 mes_add_queue_pkt.page_table_base_addr = input->page_table_base_addr;
337 mes_add_queue_pkt.process_va_start = input->process_va_start;
338 mes_add_queue_pkt.process_va_end = input->process_va_end;
339 mes_add_queue_pkt.process_quantum = input->process_quantum;
340 mes_add_queue_pkt.process_context_addr = input->process_context_addr;
341 mes_add_queue_pkt.process_context_array_index = input->process_context_array_index;
342 mes_add_queue_pkt.gang_quantum = input->gang_quantum;
343 mes_add_queue_pkt.gang_context_addr = input->gang_context_addr;
344 mes_add_queue_pkt.gang_context_array_index = input->gang_context_array_index;
345 mes_add_queue_pkt.inprocess_gang_priority =
346 convert_to_mes_priority_level(input->inprocess_gang_priority);
347 mes_add_queue_pkt.gang_global_priority_level =
348 convert_to_mes_priority_level(input->gang_global_priority_level);
349 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset;
350 mes_add_queue_pkt.mqd_addr = input->mqd_addr;
351
352 if (((adev->mes.sched_version & AMDGPU_MES_API_VERSION_MASK) >>
353 AMDGPU_MES_API_VERSION_SHIFT) >= 2)
354 mes_add_queue_pkt.wptr_addr = input->wptr_mc_addr;
355 else
356 mes_add_queue_pkt.wptr_addr = input->wptr_addr;
357
358 mes_add_queue_pkt.queue_type =
359 convert_to_mes_queue_type(input->queue_type);
360 mes_add_queue_pkt.paging = input->paging;
361 mes_add_queue_pkt.vm_context_cntl = vm_cntx_cntl;
362 mes_add_queue_pkt.gws_base = input->gws_base;
363 mes_add_queue_pkt.gws_size = input->gws_size;
364 mes_add_queue_pkt.trap_handler_addr = input->tba_addr;
365 mes_add_queue_pkt.tma_addr = input->tma_addr;
366 mes_add_queue_pkt.trap_en = input->trap_en;
367 mes_add_queue_pkt.skip_process_ctx_clear = input->skip_process_ctx_clear;
368 mes_add_queue_pkt.is_kfd_process = input->is_kfd_process;
369
370 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */
371 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue;
372 mes_add_queue_pkt.gds_size = input->queue_size;
373
374 mes_add_queue_pkt.exclusively_scheduled = input->exclusively_scheduled;
375
376 return mes_v11_0_submit_pkt_and_poll_completion(mes,
377 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt),
378 offsetof(union MESAPI__ADD_QUEUE, api_status));
379 }
380
mes_v11_0_remove_hw_queue(struct amdgpu_mes * mes,struct mes_remove_queue_input * input)381 static int mes_v11_0_remove_hw_queue(struct amdgpu_mes *mes,
382 struct mes_remove_queue_input *input)
383 {
384 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt;
385 uint32_t mes_rev = mes->sched_version & AMDGPU_MES_VERSION_MASK;
386
387 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt));
388
389 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;
390 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE;
391 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
392
393 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset;
394 mes_remove_queue_pkt.gang_context_addr = input->gang_context_addr;
395 mes_remove_queue_pkt.gang_context_array_index = input->gang_context_array_index;
396 mes_remove_queue_pkt.queue_type =
397 convert_to_mes_queue_type(input->queue_type);
398
399 if (mes_rev >= 0x60)
400 mes_remove_queue_pkt.remove_queue_after_reset = input->remove_queue_after_reset;
401
402 return mes_v11_0_submit_pkt_and_poll_completion(mes,
403 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt),
404 offsetof(union MESAPI__REMOVE_QUEUE, api_status));
405 }
406
mes_v11_0_pipe_reset_support(struct amdgpu_device * adev)407 static bool mes_v11_0_pipe_reset_support(struct amdgpu_device *adev)
408 {
409 /* Disable the pipe reset until the CPFW fully support it.*/
410 dev_warn_once(adev->dev, "The CPFW hasn't support pipe reset yet.\n");
411 return false;
412 }
mes_v11_0_reset_gfx_pipe_mmio(struct amdgpu_device * adev,u32 me,u32 pipe,u32 queue)413 static int mes_v11_0_reset_gfx_pipe_mmio(struct amdgpu_device *adev,
414 u32 me, u32 pipe, u32 queue)
415 {
416 uint32_t reset_pipe = 0, clean_pipe = 0;
417 int r;
418
419 if (!mes_v11_0_pipe_reset_support(adev))
420 return -EOPNOTSUPP;
421
422 amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
423 mutex_lock(&adev->srbm_mutex);
424 soc21_grbm_select(adev, me, pipe, queue, 0);
425
426 switch (pipe) {
427 case 0:
428 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL,
429 PFP_PIPE0_RESET, 1);
430 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL,
431 ME_PIPE0_RESET, 1);
432 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL,
433 PFP_PIPE0_RESET, 0);
434 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL,
435 ME_PIPE0_RESET, 0);
436 break;
437 case 1:
438 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL,
439 PFP_PIPE1_RESET, 1);
440 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL,
441 ME_PIPE1_RESET, 1);
442 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL,
443 PFP_PIPE1_RESET, 0);
444 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL,
445 ME_PIPE1_RESET, 0);
446 break;
447 default:
448 break;
449 }
450
451 WREG32_SOC15(GC, 0, regCP_ME_CNTL, reset_pipe);
452 WREG32_SOC15(GC, 0, regCP_ME_CNTL, clean_pipe);
453
454 r = (RREG32(SOC15_REG_OFFSET(GC, 0, regCP_GFX_RS64_INSTR_PNTR1)) << 2) -
455 RS64_FW_UC_START_ADDR_LO;
456 soc21_grbm_select(adev, 0, 0, 0, 0);
457 mutex_unlock(&adev->srbm_mutex);
458 amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
459
460 dev_info(adev->dev, "The gfx pipe reset to the ME firmware start PC: %s\n",
461 r == 0 ? "successfully" : "failed");
462 /* FIXME: Sometimes driver can't cache the ME firmware start PC correctly,
463 * so the pipe reset status relies on the later gfx ring test result.
464 */
465 return 0;
466 }
467
468 /*
469 * With MEC pipe reset asserted, clear CP_HQD_ACTIVE / CP_HQD_DEQUEUE_REQUEST for
470 * every queue on (me, pipe). HQDs must be torn down while pipe reset stays
471 * asserted; only then clear the pipe reset bit.
472 * Caller must hold adev->srbm_mutex.
473 */
mes_v11_0_clear_hqds_on_mec_pipe(struct amdgpu_device * adev,u32 me,u32 pipe)474 static void mes_v11_0_clear_hqds_on_mec_pipe(struct amdgpu_device *adev, u32 me,
475 u32 pipe)
476 {
477 unsigned int q;
478
479 for (q = 0; q < adev->gfx.mec.num_queue_per_pipe; q++) {
480 soc21_grbm_select(adev, me, pipe, q, 0);
481 /* Start from a clean HQD dequeue state before forcing HQD inactive. */
482 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 0);
483 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0);
484 }
485 }
486
mes_v11_0_reset_compute_pipe_mmio(struct amdgpu_device * adev,u32 me,u32 pipe,u32 queue)487 static int mes_v11_0_reset_compute_pipe_mmio(struct amdgpu_device *adev,
488 u32 me, u32 pipe, u32 queue)
489 {
490 uint32_t reset_val, clean_val;
491 int r;
492
493 amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
494 mutex_lock(&adev->srbm_mutex);
495 soc21_grbm_select(adev, me, pipe, queue, 0);
496
497 if (adev->gfx.rs64_enable) {
498 reset_val = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL);
499 clean_val = reset_val;
500
501 switch (pipe) {
502 case 0:
503 reset_val = REG_SET_FIELD(reset_val, CP_MEC_RS64_CNTL,
504 MEC_PIPE0_RESET, 1);
505 clean_val = REG_SET_FIELD(clean_val, CP_MEC_RS64_CNTL,
506 MEC_PIPE0_RESET, 0);
507 break;
508 case 1:
509 reset_val = REG_SET_FIELD(reset_val, CP_MEC_RS64_CNTL,
510 MEC_PIPE1_RESET, 1);
511 clean_val = REG_SET_FIELD(clean_val, CP_MEC_RS64_CNTL,
512 MEC_PIPE1_RESET, 0);
513 break;
514 case 2:
515 reset_val = REG_SET_FIELD(reset_val, CP_MEC_RS64_CNTL,
516 MEC_PIPE2_RESET, 1);
517 clean_val = REG_SET_FIELD(clean_val, CP_MEC_RS64_CNTL,
518 MEC_PIPE2_RESET, 0);
519 break;
520 case 3:
521 reset_val = REG_SET_FIELD(reset_val, CP_MEC_RS64_CNTL,
522 MEC_PIPE3_RESET, 1);
523 clean_val = REG_SET_FIELD(clean_val, CP_MEC_RS64_CNTL,
524 MEC_PIPE3_RESET, 0);
525 break;
526 default:
527 break;
528 }
529 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, reset_val);
530 mes_v11_0_clear_hqds_on_mec_pipe(adev, me, pipe);
531 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, clean_val);
532 r = (RREG32_SOC15(GC, 0, regCP_MEC_RS64_INSTR_PNTR) << 2) -
533 RS64_FW_UC_START_ADDR_LO;
534 } else {
535 reset_val = RREG32_SOC15(GC, 0, regCP_MEC_CNTL);
536 clean_val = reset_val;
537
538 if (me == 1) {
539 switch (pipe) {
540 case 0:
541 reset_val = REG_SET_FIELD(reset_val, CP_MEC_CNTL,
542 MEC_ME1_PIPE0_RESET, 1);
543 clean_val = REG_SET_FIELD(clean_val, CP_MEC_CNTL,
544 MEC_ME1_PIPE0_RESET, 0);
545 break;
546 case 1:
547 reset_val = REG_SET_FIELD(reset_val, CP_MEC_CNTL,
548 MEC_ME1_PIPE1_RESET, 1);
549 clean_val = REG_SET_FIELD(clean_val, CP_MEC_CNTL,
550 MEC_ME1_PIPE1_RESET, 0);
551 break;
552 case 2:
553 reset_val = REG_SET_FIELD(reset_val, CP_MEC_CNTL,
554 MEC_ME1_PIPE2_RESET, 1);
555 clean_val = REG_SET_FIELD(clean_val, CP_MEC_CNTL,
556 MEC_ME1_PIPE2_RESET, 0);
557 break;
558 case 3:
559 reset_val = REG_SET_FIELD(reset_val, CP_MEC_CNTL,
560 MEC_ME1_PIPE3_RESET, 1);
561 clean_val = REG_SET_FIELD(clean_val, CP_MEC_CNTL,
562 MEC_ME1_PIPE3_RESET, 0);
563 break;
564 default:
565 break;
566 }
567 /* mec1 fw pc: CP_MEC1_INSTR_PNTR */
568 } else {
569 switch (pipe) {
570 case 0:
571 reset_val = REG_SET_FIELD(reset_val, CP_MEC_CNTL,
572 MEC_ME2_PIPE0_RESET, 1);
573 clean_val = REG_SET_FIELD(clean_val, CP_MEC_CNTL,
574 MEC_ME2_PIPE0_RESET, 0);
575 break;
576 case 1:
577 reset_val = REG_SET_FIELD(reset_val, CP_MEC_CNTL,
578 MEC_ME2_PIPE1_RESET, 1);
579 clean_val = REG_SET_FIELD(clean_val, CP_MEC_CNTL,
580 MEC_ME2_PIPE1_RESET, 0);
581 break;
582 case 2:
583 reset_val = REG_SET_FIELD(reset_val, CP_MEC_CNTL,
584 MEC_ME2_PIPE2_RESET, 1);
585 clean_val = REG_SET_FIELD(clean_val, CP_MEC_CNTL,
586 MEC_ME2_PIPE2_RESET, 0);
587 break;
588 case 3:
589 reset_val = REG_SET_FIELD(reset_val, CP_MEC_CNTL,
590 MEC_ME2_PIPE3_RESET, 1);
591 clean_val = REG_SET_FIELD(clean_val, CP_MEC_CNTL,
592 MEC_ME2_PIPE3_RESET, 0);
593 break;
594 default:
595 break;
596 }
597 /* mec2 fw pc: CP:CP_MEC2_INSTR_PNTR */
598 }
599 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, reset_val);
600 mes_v11_0_clear_hqds_on_mec_pipe(adev, me, pipe);
601 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, clean_val);
602 r = RREG32(SOC15_REG_OFFSET(GC, 0, regCP_MEC1_INSTR_PNTR));
603 }
604
605 soc21_grbm_select(adev, 0, 0, 0, 0);
606 mutex_unlock(&adev->srbm_mutex);
607 amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
608
609 dev_dbg(adev->dev, "MEC pipe me%u pipe%u queue%u resets to MEC FW start PC: %s\n",
610 me, pipe, queue, r == 0 ? "successfully" : "failed");
611 /*FIXME:Sometimes driver can't cache the MEC firmware start PC correctly, so the pipe
612 * reset status relies on the compute ring test result.
613 */
614 return 0;
615 }
616
mes_v11_0_reset_pipe_mmio(struct amdgpu_mes * mes,uint32_t queue_type,uint32_t me_id,uint32_t pipe_id,uint32_t queue_id,uint32_t vmid)617 static int mes_v11_0_reset_pipe_mmio(struct amdgpu_mes *mes, uint32_t queue_type,
618 uint32_t me_id, uint32_t pipe_id,
619 uint32_t queue_id, uint32_t vmid)
620 {
621 struct amdgpu_device *adev = mes->adev;
622
623 if (queue_type == AMDGPU_RING_TYPE_GFX)
624 return mes_v11_0_reset_gfx_pipe_mmio(adev, me_id, pipe_id, queue_id);
625 else if (queue_type == AMDGPU_RING_TYPE_COMPUTE)
626 return mes_v11_0_reset_compute_pipe_mmio(adev, me_id, pipe_id, queue_id);
627 else
628 return -EOPNOTSUPP;
629 }
630
mes_v11_0_reset_queue_mmio(struct amdgpu_mes * mes,uint32_t queue_type,uint32_t me_id,uint32_t pipe_id,uint32_t queue_id,uint32_t vmid)631 static int mes_v11_0_reset_queue_mmio(struct amdgpu_mes *mes, uint32_t queue_type,
632 uint32_t me_id, uint32_t pipe_id,
633 uint32_t queue_id, uint32_t vmid)
634 {
635 struct amdgpu_device *adev = mes->adev;
636 uint32_t value, reg;
637 int i, r = 0;
638
639 amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
640
641 if (queue_type == AMDGPU_RING_TYPE_GFX) {
642 dev_info(adev->dev, "reset gfx queue (%d:%d:%d: vmid:%d)\n",
643 me_id, pipe_id, queue_id, vmid);
644
645 mutex_lock(&adev->gfx.reset_sem_mutex);
646 gfx_v11_0_request_gfx_index_mutex(adev, true);
647 /* all se allow writes */
648 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX,
649 (uint32_t)(0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT));
650 value = REG_SET_FIELD(0, CP_VMID_RESET, RESET_REQUEST, 1 << vmid);
651 if (pipe_id == 0)
652 value = REG_SET_FIELD(value, CP_VMID_RESET, PIPE0_QUEUES, 1 << queue_id);
653 else
654 value = REG_SET_FIELD(value, CP_VMID_RESET, PIPE1_QUEUES, 1 << queue_id);
655 WREG32_SOC15(GC, 0, regCP_VMID_RESET, value);
656 gfx_v11_0_request_gfx_index_mutex(adev, false);
657 mutex_unlock(&adev->gfx.reset_sem_mutex);
658
659 mutex_lock(&adev->srbm_mutex);
660 soc21_grbm_select(adev, me_id, pipe_id, queue_id, 0);
661 /* wait till dequeue take effects */
662 for (i = 0; i < adev->usec_timeout; i++) {
663 if (!(RREG32_SOC15(GC, 0, regCP_GFX_HQD_ACTIVE) & 1))
664 break;
665 udelay(1);
666 }
667 if (i >= adev->usec_timeout) {
668 dev_err(adev->dev, "failed to wait on gfx hqd deactivate\n");
669 r = -ETIMEDOUT;
670 }
671
672 soc21_grbm_select(adev, 0, 0, 0, 0);
673 mutex_unlock(&adev->srbm_mutex);
674 } else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) {
675 dev_info(adev->dev, "reset compute queue (%d:%d:%d)\n",
676 me_id, pipe_id, queue_id);
677 mutex_lock(&adev->srbm_mutex);
678 soc21_grbm_select(adev, me_id, pipe_id, queue_id, 0);
679 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0x2);
680 WREG32_SOC15(GC, 0, regSPI_COMPUTE_QUEUE_RESET, 0x1);
681
682 /* wait till dequeue take effects */
683 for (i = 0; i < adev->usec_timeout; i++) {
684 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1))
685 break;
686 udelay(1);
687 }
688 if (i >= adev->usec_timeout) {
689 dev_err(adev->dev, "failed to wait on hqd deactivate\n");
690 r = -ETIMEDOUT;
691 }
692 soc21_grbm_select(adev, 0, 0, 0, 0);
693 mutex_unlock(&adev->srbm_mutex);
694 } else if (queue_type == AMDGPU_RING_TYPE_SDMA) {
695 dev_info(adev->dev, "reset sdma queue (%d:%d:%d)\n",
696 me_id, pipe_id, queue_id);
697 switch (me_id) {
698 case 1:
699 reg = SOC15_REG_OFFSET(GC, 0, regSDMA1_QUEUE_RESET_REQ);
700 break;
701 case 0:
702 default:
703 reg = SOC15_REG_OFFSET(GC, 0, regSDMA0_QUEUE_RESET_REQ);
704 break;
705 }
706
707 value = 1 << queue_id;
708 WREG32(reg, value);
709 /* wait for queue reset done */
710 for (i = 0; i < adev->usec_timeout; i++) {
711 if (!(RREG32(reg) & value))
712 break;
713 udelay(1);
714 }
715 if (i >= adev->usec_timeout) {
716 dev_err(adev->dev, "failed to wait on sdma queue reset done\n");
717 r = -ETIMEDOUT;
718 }
719 }
720
721 amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
722 return r;
723 }
724
mes_v11_0_map_legacy_queue(struct amdgpu_mes * mes,struct mes_map_legacy_queue_input * input)725 static int mes_v11_0_map_legacy_queue(struct amdgpu_mes *mes,
726 struct mes_map_legacy_queue_input *input)
727 {
728 union MESAPI__ADD_QUEUE mes_add_queue_pkt;
729
730 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt));
731
732 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;
733 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE;
734 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
735
736 mes_add_queue_pkt.pipe_id = input->pipe_id;
737 mes_add_queue_pkt.queue_id = input->queue_id;
738 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset;
739 mes_add_queue_pkt.mqd_addr = input->mqd_addr;
740 mes_add_queue_pkt.wptr_addr = input->wptr_addr;
741 mes_add_queue_pkt.queue_type =
742 convert_to_mes_queue_type(input->queue_type);
743 mes_add_queue_pkt.map_legacy_kq = 1;
744
745 return mes_v11_0_submit_pkt_and_poll_completion(mes,
746 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt),
747 offsetof(union MESAPI__ADD_QUEUE, api_status));
748 }
749
mes_v11_0_unmap_legacy_queue(struct amdgpu_mes * mes,struct mes_unmap_legacy_queue_input * input)750 static int mes_v11_0_unmap_legacy_queue(struct amdgpu_mes *mes,
751 struct mes_unmap_legacy_queue_input *input)
752 {
753 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt;
754
755 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt));
756
757 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;
758 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE;
759 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
760
761 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset;
762 mes_remove_queue_pkt.gang_context_addr = 0;
763
764 mes_remove_queue_pkt.pipe_id = input->pipe_id;
765 mes_remove_queue_pkt.queue_id = input->queue_id;
766
767 if (input->action == PREEMPT_QUEUES_NO_UNMAP) {
768 mes_remove_queue_pkt.preempt_legacy_gfx_queue = 1;
769 mes_remove_queue_pkt.tf_addr = input->trail_fence_addr;
770 mes_remove_queue_pkt.tf_data =
771 lower_32_bits(input->trail_fence_data);
772 } else {
773 mes_remove_queue_pkt.unmap_legacy_queue = 1;
774 mes_remove_queue_pkt.queue_type =
775 convert_to_mes_queue_type(input->queue_type);
776 }
777
778 if (input->action == RESET_QUEUES &&
779 (mes->sched_version & AMDGPU_MES_VERSION_MASK) >= 0x60)
780 mes_remove_queue_pkt.remove_queue_after_reset = 1;
781
782
783 return mes_v11_0_submit_pkt_and_poll_completion(mes,
784 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt),
785 offsetof(union MESAPI__REMOVE_QUEUE, api_status));
786 }
787
mes_v11_0_suspend_gang(struct amdgpu_mes * mes,struct mes_suspend_gang_input * input)788 static int mes_v11_0_suspend_gang(struct amdgpu_mes *mes,
789 struct mes_suspend_gang_input *input)
790 {
791 union MESAPI__SUSPEND mes_suspend_gang_pkt;
792
793 memset(&mes_suspend_gang_pkt, 0, sizeof(mes_suspend_gang_pkt));
794
795 mes_suspend_gang_pkt.header.type = MES_API_TYPE_SCHEDULER;
796 mes_suspend_gang_pkt.header.opcode = MES_SCH_API_SUSPEND;
797 mes_suspend_gang_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
798
799 mes_suspend_gang_pkt.suspend_all_gangs = input->suspend_all_gangs;
800 mes_suspend_gang_pkt.gang_context_addr = input->gang_context_addr;
801 mes_suspend_gang_pkt.suspend_fence_addr = input->suspend_fence_addr;
802 mes_suspend_gang_pkt.suspend_fence_value = input->suspend_fence_value;
803 mes_suspend_gang_pkt.doorbell_offset = input->doorbell_offset;
804
805 return mes_v11_0_submit_pkt_and_poll_completion(mes,
806 &mes_suspend_gang_pkt, sizeof(mes_suspend_gang_pkt),
807 offsetof(union MESAPI__SUSPEND, api_status));
808 }
809
mes_v11_0_resume_gang(struct amdgpu_mes * mes,struct mes_resume_gang_input * input)810 static int mes_v11_0_resume_gang(struct amdgpu_mes *mes,
811 struct mes_resume_gang_input *input)
812 {
813 union MESAPI__RESUME mes_resume_gang_pkt;
814
815 memset(&mes_resume_gang_pkt, 0, sizeof(mes_resume_gang_pkt));
816
817 mes_resume_gang_pkt.header.type = MES_API_TYPE_SCHEDULER;
818 mes_resume_gang_pkt.header.opcode = MES_SCH_API_RESUME;
819 mes_resume_gang_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
820
821 mes_resume_gang_pkt.resume_all_gangs = input->resume_all_gangs;
822 mes_resume_gang_pkt.gang_context_addr = input->gang_context_addr;
823 mes_resume_gang_pkt.doorbell_offset = input->doorbell_offset;
824
825 return mes_v11_0_submit_pkt_and_poll_completion(mes,
826 &mes_resume_gang_pkt, sizeof(mes_resume_gang_pkt),
827 offsetof(union MESAPI__RESUME, api_status));
828 }
829
mes_v11_0_query_sched_status(struct amdgpu_mes * mes)830 static int mes_v11_0_query_sched_status(struct amdgpu_mes *mes)
831 {
832 union MESAPI__QUERY_MES_STATUS mes_status_pkt;
833
834 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt));
835
836 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER;
837 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS;
838 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
839
840 return mes_v11_0_submit_pkt_and_poll_completion(mes,
841 &mes_status_pkt, sizeof(mes_status_pkt),
842 offsetof(union MESAPI__QUERY_MES_STATUS, api_status));
843 }
844
845 /*
846 * QUERY_SCHEDULER_STATUS: get proc/gang context array sizes
847 */
mes_v11_0_query_ctx_array_sizes(struct amdgpu_mes * mes)848 static int mes_v11_0_query_ctx_array_sizes(struct amdgpu_mes *mes)
849 {
850 struct amdgpu_device *adev = mes->adev;
851 union MESAPI__QUERY_MES_STATUS mes_query_pkt;
852 int r;
853
854 if (!mes->ctx_array_size_cpu_ptr)
855 return -EINVAL;
856
857 /* Clear the output buffer */
858 mes->ctx_array_size_cpu_ptr[0] = 0; /* proc_ctx_array_size */
859 mes->ctx_array_size_cpu_ptr[1] = 0; /* gang_ctx_array_size */
860
861 memset(&mes_query_pkt, 0, sizeof(mes_query_pkt));
862
863 mes_query_pkt.header.type = MES_API_TYPE_SCHEDULER;
864 mes_query_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS;
865 mes_query_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
866
867 mes_query_pkt.subopcode = MES_API_QUERY_MES__GET_CTX_ARRAY_SIZE;
868
869 /*
870 * MES FW will write the array sizes to these GPU addresses:
871 * proc_ctx_array_size_addr -> uint32_t N (e.g., 50)
872 * gang_ctx_array_size_addr -> uint32_t M (e.g., 300)
873 */
874 mes_query_pkt.ctx_array_size.proc_ctx_array_size_addr =
875 mes->ctx_array_size_gpu_addr;
876 mes_query_pkt.ctx_array_size.gang_ctx_array_size_addr =
877 mes->ctx_array_size_gpu_addr + sizeof(uint32_t);
878
879 mes_query_pkt.api_status.api_completion_fence_addr =
880 mes->ring[0].fence_drv.gpu_addr;
881 mes_query_pkt.api_status.api_completion_fence_value =
882 ++mes->ring[0].fence_drv.sync_seq;
883
884 r = mes_v11_0_submit_pkt_and_poll_completion(mes,
885 &mes_query_pkt, sizeof(mes_query_pkt),
886 offsetof(union MESAPI__QUERY_MES_STATUS, api_status));
887 if (r) {
888 dev_err(adev->dev,
889 "MES QUERY_SCHEDULER_STATUS (GET_CTX_ARRAY_SIZE) failed, r=%d\n", r);
890 return r;
891 }
892
893 /* MES has written the sizes - now set up bitmaps */
894 return amdgpu_mes_rs64mem_setup_bitmaps(mes);
895 }
896
mes_v11_0_misc_op(struct amdgpu_mes * mes,struct mes_misc_op_input * input)897 static int mes_v11_0_misc_op(struct amdgpu_mes *mes,
898 struct mes_misc_op_input *input)
899 {
900 union MESAPI__MISC misc_pkt;
901
902 memset(&misc_pkt, 0, sizeof(misc_pkt));
903
904 misc_pkt.header.type = MES_API_TYPE_SCHEDULER;
905 misc_pkt.header.opcode = MES_SCH_API_MISC;
906 misc_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
907
908 switch (input->op) {
909 case MES_MISC_OP_READ_REG:
910 misc_pkt.opcode = MESAPI_MISC__READ_REG;
911 misc_pkt.read_reg.reg_offset = input->read_reg.reg_offset;
912 misc_pkt.read_reg.buffer_addr = input->read_reg.buffer_addr;
913 break;
914 case MES_MISC_OP_WRITE_REG:
915 misc_pkt.opcode = MESAPI_MISC__WRITE_REG;
916 misc_pkt.write_reg.reg_offset = input->write_reg.reg_offset;
917 misc_pkt.write_reg.reg_value = input->write_reg.reg_value;
918 break;
919 case MES_MISC_OP_WRM_REG_WAIT:
920 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM;
921 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WAIT_REG_MEM;
922 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref;
923 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask;
924 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0;
925 misc_pkt.wait_reg_mem.reg_offset2 = 0;
926 break;
927 case MES_MISC_OP_WRM_REG_WR_WAIT:
928 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM;
929 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WR_WAIT_WR_REG;
930 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref;
931 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask;
932 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0;
933 misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1;
934 break;
935 case MES_MISC_OP_SET_SHADER_DEBUGGER:
936 misc_pkt.opcode = MESAPI_MISC__SET_SHADER_DEBUGGER;
937 misc_pkt.set_shader_debugger.process_context_addr =
938 input->set_shader_debugger.process_context_addr;
939 misc_pkt.set_shader_debugger.flags.u32all =
940 input->set_shader_debugger.flags.u32all;
941 misc_pkt.set_shader_debugger.spi_gdbg_per_vmid_cntl =
942 input->set_shader_debugger.spi_gdbg_per_vmid_cntl;
943 memcpy(misc_pkt.set_shader_debugger.tcp_watch_cntl,
944 input->set_shader_debugger.tcp_watch_cntl,
945 sizeof(misc_pkt.set_shader_debugger.tcp_watch_cntl));
946 misc_pkt.set_shader_debugger.trap_en = input->set_shader_debugger.trap_en;
947 break;
948 case MES_MISC_OP_CHANGE_CONFIG:
949 if ((mes->adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) < 0x63) {
950 dev_warn_once(mes->adev->dev,
951 "MES FW version must be larger than 0x63 to support limit single process feature.\n");
952 return 0;
953 }
954 misc_pkt.opcode = MESAPI_MISC__CHANGE_CONFIG;
955 misc_pkt.change_config.opcode =
956 MESAPI_MISC__CHANGE_CONFIG_OPTION_LIMIT_SINGLE_PROCESS;
957 misc_pkt.change_config.option.bits.limit_single_process =
958 input->change_config.option.limit_single_process;
959 break;
960
961 default:
962 drm_err(adev_to_drm(mes->adev), "unsupported misc op (%d)\n", input->op);
963 return -EINVAL;
964 }
965
966 return mes_v11_0_submit_pkt_and_poll_completion(mes,
967 &misc_pkt, sizeof(misc_pkt),
968 offsetof(union MESAPI__MISC, api_status));
969 }
970
mes_v11_0_set_hw_resources(struct amdgpu_mes * mes)971 static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes)
972 {
973 int i;
974 struct amdgpu_device *adev = mes->adev;
975 union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt;
976
977 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt));
978
979 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER;
980 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC;
981 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
982
983 mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub;
984 mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub;
985 mes_set_hw_res_pkt.gds_size = adev->gds.gds_size;
986 mes_set_hw_res_pkt.paging_vmid = 0;
987 mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = mes->sch_ctx_gpu_addr[0];
988 mes_set_hw_res_pkt.query_status_fence_gpu_mc_ptr =
989 mes->query_status_fence_gpu_addr[0];
990
991 for (i = 0; i < MAX_COMPUTE_PIPES; i++)
992 mes_set_hw_res_pkt.compute_hqd_mask[i] =
993 mes->compute_hqd_mask[i];
994
995 for (i = 0; i < MAX_GFX_PIPES; i++)
996 mes_set_hw_res_pkt.gfx_hqd_mask[i] =
997 mes->gfx_hqd_mask[i];
998
999 for (i = 0; i < MAX_SDMA_PIPES; i++)
1000 mes_set_hw_res_pkt.sdma_hqd_mask[i] = mes->sdma_hqd_mask[i];
1001
1002 for (i = 0; i < AMD_PRIORITY_NUM_LEVELS; i++)
1003 mes_set_hw_res_pkt.aggregated_doorbells[i] =
1004 mes->aggregated_doorbells[i];
1005
1006 for (i = 0; i < 5; i++) {
1007 mes_set_hw_res_pkt.gc_base[i] = adev->reg_offset[GC_HWIP][0][i];
1008 mes_set_hw_res_pkt.mmhub_base[i] =
1009 adev->reg_offset[MMHUB_HWIP][0][i];
1010 mes_set_hw_res_pkt.osssys_base[i] =
1011 adev->reg_offset[OSSSYS_HWIP][0][i];
1012 }
1013
1014 mes_set_hw_res_pkt.disable_reset = 1;
1015 mes_set_hw_res_pkt.disable_mes_log = 1;
1016 mes_set_hw_res_pkt.use_different_vmid_compute = 1;
1017 mes_set_hw_res_pkt.enable_reg_active_poll = 1;
1018 mes_set_hw_res_pkt.enable_level_process_quantum_check = 1;
1019 mes_set_hw_res_pkt.oversubscription_timer = 50;
1020 if (adev->mes.use_rs64mem)
1021 mes_set_hw_res_pkt.use_rs64mem_for_proc_gang_ctx = 1;
1022
1023 if (amdgpu_mes_log_enable) {
1024 mes_set_hw_res_pkt.enable_mes_event_int_logging = 1;
1025 mes_set_hw_res_pkt.event_intr_history_gpu_mc_ptr =
1026 mes->event_log_gpu_addr;
1027 }
1028
1029 if (adev->enforce_isolation[0] == AMDGPU_ENFORCE_ISOLATION_ENABLE)
1030 mes_set_hw_res_pkt.limit_single_process = 1;
1031
1032 return mes_v11_0_submit_pkt_and_poll_completion(mes,
1033 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt),
1034 offsetof(union MESAPI_SET_HW_RESOURCES, api_status));
1035 }
1036
mes_v11_0_set_hw_resources_1(struct amdgpu_mes * mes)1037 static int mes_v11_0_set_hw_resources_1(struct amdgpu_mes *mes)
1038 {
1039 union MESAPI_SET_HW_RESOURCES_1 mes_set_hw_res_pkt;
1040 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt));
1041
1042 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER;
1043 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC_1;
1044 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
1045 mes_set_hw_res_pkt.enable_mes_info_ctx = 1;
1046
1047 mes_set_hw_res_pkt.cleaner_shader_fence_mc_addr = mes->resource_1_gpu_addr[0];
1048 if (amdgpu_sriov_is_mes_info_enable(mes->adev)) {
1049 mes_set_hw_res_pkt.mes_info_ctx_mc_addr =
1050 mes->resource_1_gpu_addr[0] + AMDGPU_GPU_PAGE_SIZE;
1051 mes_set_hw_res_pkt.mes_info_ctx_size = MES11_HW_RESOURCE_1_SIZE;
1052 }
1053
1054 return mes_v11_0_submit_pkt_and_poll_completion(mes,
1055 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt),
1056 offsetof(union MESAPI_SET_HW_RESOURCES_1, api_status));
1057 }
1058
mes_v11_0_reset_hw_queue(struct amdgpu_mes * mes,struct mes_reset_queue_input * input)1059 static int mes_v11_0_reset_hw_queue(struct amdgpu_mes *mes,
1060 struct mes_reset_queue_input *input)
1061 {
1062 union MESAPI__RESET mes_reset_queue_pkt;
1063
1064 if (input->use_mmio) {
1065 int r = mes_v11_0_reset_queue_mmio(mes, input->queue_type,
1066 input->me_id, input->pipe_id,
1067 input->queue_id, input->vmid);
1068 if (r)
1069 return mes_v11_0_reset_pipe_mmio(mes, input->queue_type,
1070 input->me_id, input->pipe_id,
1071 input->queue_id, input->vmid);
1072 return 0;
1073 }
1074
1075 memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt));
1076
1077 mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;
1078 mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET;
1079 mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
1080
1081 mes_reset_queue_pkt.queue_type =
1082 convert_to_mes_queue_type(input->queue_type);
1083
1084 if (input->legacy_gfx) {
1085 mes_reset_queue_pkt.reset_legacy_gfx = 1;
1086 mes_reset_queue_pkt.pipe_id_lp = input->pipe_id;
1087 mes_reset_queue_pkt.queue_id_lp = input->queue_id;
1088 mes_reset_queue_pkt.mqd_mc_addr_lp = input->mqd_addr;
1089 mes_reset_queue_pkt.doorbell_offset_lp = input->doorbell_offset;
1090 mes_reset_queue_pkt.wptr_addr_lp = input->wptr_addr;
1091 mes_reset_queue_pkt.vmid_id_lp = input->vmid;
1092 } else {
1093 mes_reset_queue_pkt.reset_queue_only = 1;
1094 mes_reset_queue_pkt.doorbell_offset = input->doorbell_offset;
1095 }
1096
1097 return mes_v11_0_submit_pkt_and_poll_completion(mes,
1098 &mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt),
1099 offsetof(union MESAPI__RESET, api_status));
1100 }
1101
mes_v11_0_detect_and_reset_hung_queues(struct amdgpu_mes * mes,struct mes_detect_and_reset_queue_input * input)1102 static int mes_v11_0_detect_and_reset_hung_queues(struct amdgpu_mes *mes,
1103 struct mes_detect_and_reset_queue_input *input)
1104 {
1105 union MESAPI__RESET mes_reset_queue_pkt;
1106
1107 memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt));
1108
1109 mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;
1110 mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET;
1111 mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
1112
1113 mes_reset_queue_pkt.queue_type =
1114 convert_to_mes_queue_type(input->queue_type);
1115 mes_reset_queue_pkt.doorbell_offset_addr =
1116 mes->hung_queue_db_array_gpu_addr[0];
1117
1118 if (input->detect_only)
1119 mes_reset_queue_pkt.hang_detect_only = 1;
1120 else
1121 mes_reset_queue_pkt.hang_detect_then_reset = 1;
1122
1123 return mes_v11_0_submit_pkt_and_poll_completion(mes,
1124 &mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt),
1125 offsetof(union MESAPI__RESET, api_status));
1126 }
1127
1128 static const struct amdgpu_mes_funcs mes_v11_0_funcs = {
1129 .add_hw_queue = mes_v11_0_add_hw_queue,
1130 .remove_hw_queue = mes_v11_0_remove_hw_queue,
1131 .map_legacy_queue = mes_v11_0_map_legacy_queue,
1132 .unmap_legacy_queue = mes_v11_0_unmap_legacy_queue,
1133 .suspend_gang = mes_v11_0_suspend_gang,
1134 .resume_gang = mes_v11_0_resume_gang,
1135 .misc_op = mes_v11_0_misc_op,
1136 .reset_hw_queue = mes_v11_0_reset_hw_queue,
1137 .detect_and_reset_hung_queues = mes_v11_0_detect_and_reset_hung_queues,
1138 };
1139
mes_v11_0_allocate_ucode_buffer(struct amdgpu_device * adev,enum amdgpu_mes_pipe pipe)1140 static int mes_v11_0_allocate_ucode_buffer(struct amdgpu_device *adev,
1141 enum amdgpu_mes_pipe pipe)
1142 {
1143 int r;
1144 const struct mes_firmware_header_v1_0 *mes_hdr;
1145 const __le32 *fw_data;
1146 unsigned fw_size;
1147
1148 mes_hdr = (const struct mes_firmware_header_v1_0 *)
1149 adev->mes.fw[pipe]->data;
1150
1151 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data +
1152 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes));
1153 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes);
1154
1155 r = amdgpu_bo_create_reserved(adev, fw_size,
1156 PAGE_SIZE,
1157 AMDGPU_GEM_DOMAIN_VRAM |
1158 AMDGPU_GEM_DOMAIN_GTT,
1159 &adev->mes.ucode_fw_obj[pipe],
1160 &adev->mes.ucode_fw_gpu_addr[pipe],
1161 (void **)&adev->mes.ucode_fw_ptr[pipe]);
1162 if (r) {
1163 dev_err(adev->dev, "(%d) failed to create mes fw bo\n", r);
1164 return r;
1165 }
1166
1167 memcpy(adev->mes.ucode_fw_ptr[pipe], fw_data, fw_size);
1168
1169 amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[pipe]);
1170 amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[pipe]);
1171
1172 return 0;
1173 }
1174
mes_v11_0_allocate_ucode_data_buffer(struct amdgpu_device * adev,enum amdgpu_mes_pipe pipe)1175 static int mes_v11_0_allocate_ucode_data_buffer(struct amdgpu_device *adev,
1176 enum amdgpu_mes_pipe pipe)
1177 {
1178 int r;
1179 const struct mes_firmware_header_v1_0 *mes_hdr;
1180 const __le32 *fw_data;
1181 unsigned fw_size;
1182
1183 mes_hdr = (const struct mes_firmware_header_v1_0 *)
1184 adev->mes.fw[pipe]->data;
1185
1186 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data +
1187 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes));
1188 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes);
1189
1190 if (fw_size > GFX_MES_DRAM_SIZE) {
1191 dev_err(adev->dev, "PIPE%d ucode data fw size (%d) is greater than dram size (%d)\n",
1192 pipe, fw_size, GFX_MES_DRAM_SIZE);
1193 return -EINVAL;
1194 }
1195
1196 r = amdgpu_bo_create_reserved(adev, GFX_MES_DRAM_SIZE,
1197 64 * 1024,
1198 AMDGPU_GEM_DOMAIN_VRAM |
1199 AMDGPU_GEM_DOMAIN_GTT,
1200 &adev->mes.data_fw_obj[pipe],
1201 &adev->mes.data_fw_gpu_addr[pipe],
1202 (void **)&adev->mes.data_fw_ptr[pipe]);
1203 if (r) {
1204 dev_err(adev->dev, "(%d) failed to create mes data fw bo\n", r);
1205 return r;
1206 }
1207
1208 memcpy(adev->mes.data_fw_ptr[pipe], fw_data, fw_size);
1209
1210 amdgpu_bo_kunmap(adev->mes.data_fw_obj[pipe]);
1211 amdgpu_bo_unreserve(adev->mes.data_fw_obj[pipe]);
1212
1213 return 0;
1214 }
1215
mes_v11_0_free_ucode_buffers(struct amdgpu_device * adev,enum amdgpu_mes_pipe pipe)1216 static void mes_v11_0_free_ucode_buffers(struct amdgpu_device *adev,
1217 enum amdgpu_mes_pipe pipe)
1218 {
1219 amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[pipe],
1220 &adev->mes.data_fw_gpu_addr[pipe],
1221 (void **)&adev->mes.data_fw_ptr[pipe]);
1222
1223 amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[pipe],
1224 &adev->mes.ucode_fw_gpu_addr[pipe],
1225 (void **)&adev->mes.ucode_fw_ptr[pipe]);
1226 }
1227
mes_v11_0_get_fw_version(struct amdgpu_device * adev)1228 static void mes_v11_0_get_fw_version(struct amdgpu_device *adev)
1229 {
1230 int pipe;
1231
1232 /* return early if we have already fetched these */
1233 if (adev->mes.sched_version && adev->mes.kiq_version)
1234 return;
1235
1236 /* get MES scheduler/KIQ versions */
1237 mutex_lock(&adev->srbm_mutex);
1238
1239 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
1240 soc21_grbm_select(adev, 3, pipe, 0, 0);
1241
1242 if (pipe == AMDGPU_MES_SCHED_PIPE)
1243 adev->mes.sched_version =
1244 RREG32_SOC15(GC, 0, regCP_MES_GP3_LO);
1245 else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq)
1246 adev->mes.kiq_version =
1247 RREG32_SOC15(GC, 0, regCP_MES_GP3_LO);
1248 }
1249
1250 soc21_grbm_select(adev, 0, 0, 0, 0);
1251 mutex_unlock(&adev->srbm_mutex);
1252 }
1253
mes_v11_0_enable(struct amdgpu_device * adev,bool enable)1254 static void mes_v11_0_enable(struct amdgpu_device *adev, bool enable)
1255 {
1256 uint64_t ucode_addr;
1257 uint32_t pipe, data = 0;
1258
1259 if (enable) {
1260 if (amdgpu_mes_log_enable) {
1261 WREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_LO,
1262 lower_32_bits(adev->mes.event_log_gpu_addr + AMDGPU_MES_LOG_BUFFER_SIZE));
1263 WREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_HI,
1264 upper_32_bits(adev->mes.event_log_gpu_addr + AMDGPU_MES_LOG_BUFFER_SIZE));
1265 dev_info(adev->dev, "Setup CP MES MSCRATCH address : 0x%x. 0x%x\n",
1266 RREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_HI),
1267 RREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_LO));
1268 }
1269
1270 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL);
1271 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1);
1272 data = REG_SET_FIELD(data, CP_MES_CNTL,
1273 MES_PIPE1_RESET, adev->enable_mes_kiq ? 1 : 0);
1274 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data);
1275
1276 mutex_lock(&adev->srbm_mutex);
1277 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
1278 if (!adev->enable_mes_kiq &&
1279 pipe == AMDGPU_MES_KIQ_PIPE)
1280 continue;
1281
1282 soc21_grbm_select(adev, 3, pipe, 0, 0);
1283
1284 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2;
1285 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START,
1286 lower_32_bits(ucode_addr));
1287 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI,
1288 upper_32_bits(ucode_addr));
1289 }
1290 soc21_grbm_select(adev, 0, 0, 0, 0);
1291 mutex_unlock(&adev->srbm_mutex);
1292
1293 /* unhalt MES and activate pipe0 */
1294 data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1);
1295 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE,
1296 adev->enable_mes_kiq ? 1 : 0);
1297 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data);
1298
1299 if (amdgpu_emu_mode)
1300 msleep(100);
1301 else
1302 udelay(500);
1303 } else {
1304 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL);
1305 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0);
1306 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 0);
1307 data = REG_SET_FIELD(data, CP_MES_CNTL,
1308 MES_INVALIDATE_ICACHE, 1);
1309 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1);
1310 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET,
1311 adev->enable_mes_kiq ? 1 : 0);
1312 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1);
1313 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data);
1314 }
1315 }
1316
1317 /* This function is for backdoor MES firmware */
mes_v11_0_load_microcode(struct amdgpu_device * adev,enum amdgpu_mes_pipe pipe,bool prime_icache)1318 static int mes_v11_0_load_microcode(struct amdgpu_device *adev,
1319 enum amdgpu_mes_pipe pipe, bool prime_icache)
1320 {
1321 int r;
1322 uint32_t data;
1323 uint64_t ucode_addr;
1324
1325 mes_v11_0_enable(adev, false);
1326
1327 if (!adev->mes.fw[pipe])
1328 return -EINVAL;
1329
1330 r = mes_v11_0_allocate_ucode_buffer(adev, pipe);
1331 if (r)
1332 return r;
1333
1334 r = mes_v11_0_allocate_ucode_data_buffer(adev, pipe);
1335 if (r) {
1336 mes_v11_0_free_ucode_buffers(adev, pipe);
1337 return r;
1338 }
1339
1340 mutex_lock(&adev->srbm_mutex);
1341 /* me=3, pipe=0, queue=0 */
1342 soc21_grbm_select(adev, 3, pipe, 0, 0);
1343
1344 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_CNTL, 0);
1345
1346 /* set ucode start address */
1347 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2;
1348 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START,
1349 lower_32_bits(ucode_addr));
1350 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI,
1351 upper_32_bits(ucode_addr));
1352
1353 /* set ucode fimrware address */
1354 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_LO,
1355 lower_32_bits(adev->mes.ucode_fw_gpu_addr[pipe]));
1356 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_HI,
1357 upper_32_bits(adev->mes.ucode_fw_gpu_addr[pipe]));
1358
1359 /* set ucode instruction cache boundary to 2M-1 */
1360 WREG32_SOC15(GC, 0, regCP_MES_MIBOUND_LO, 0x1FFFFF);
1361
1362 /* set ucode data firmware address */
1363 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_LO,
1364 lower_32_bits(adev->mes.data_fw_gpu_addr[pipe]));
1365 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_HI,
1366 upper_32_bits(adev->mes.data_fw_gpu_addr[pipe]));
1367
1368 /* Set 0x7FFFF (512K-1) to CP_MES_MDBOUND_LO */
1369 WREG32_SOC15(GC, 0, regCP_MES_MDBOUND_LO, 0x7FFFF);
1370
1371 if (prime_icache) {
1372 /* invalidate ICACHE */
1373 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL);
1374 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0);
1375 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1);
1376 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data);
1377
1378 /* prime the ICACHE. */
1379 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL);
1380 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1);
1381 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data);
1382 }
1383
1384 soc21_grbm_select(adev, 0, 0, 0, 0);
1385 mutex_unlock(&adev->srbm_mutex);
1386
1387 return 0;
1388 }
1389
mes_v11_0_allocate_eop_buf(struct amdgpu_device * adev,enum amdgpu_mes_pipe pipe)1390 static int mes_v11_0_allocate_eop_buf(struct amdgpu_device *adev,
1391 enum amdgpu_mes_pipe pipe)
1392 {
1393 int r;
1394 u32 *eop;
1395
1396 r = amdgpu_bo_create_reserved(adev, MES_EOP_SIZE, PAGE_SIZE,
1397 AMDGPU_GEM_DOMAIN_GTT,
1398 &adev->mes.eop_gpu_obj[pipe],
1399 &adev->mes.eop_gpu_addr[pipe],
1400 (void **)&eop);
1401 if (r) {
1402 dev_warn(adev->dev, "(%d) create EOP bo failed\n", r);
1403 return r;
1404 }
1405
1406 memset(eop, 0,
1407 adev->mes.eop_gpu_obj[pipe]->tbo.base.size);
1408
1409 amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[pipe]);
1410 amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[pipe]);
1411
1412 return 0;
1413 }
1414
mes_v11_0_mqd_init(struct amdgpu_ring * ring)1415 static int mes_v11_0_mqd_init(struct amdgpu_ring *ring)
1416 {
1417 struct v11_compute_mqd *mqd = ring->mqd_ptr;
1418 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
1419 uint32_t tmp;
1420
1421 memset(mqd, 0, sizeof(*mqd));
1422
1423 mqd->header = 0xC0310800;
1424 mqd->compute_pipelinestat_enable = 0x00000001;
1425 mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
1426 mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
1427 mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
1428 mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
1429 mqd->compute_misc_reserved = 0x00000007;
1430
1431 eop_base_addr = ring->eop_gpu_addr >> 8;
1432
1433 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
1434 tmp = regCP_HQD_EOP_CONTROL_DEFAULT;
1435 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
1436 (order_base_2(MES_EOP_SIZE / 4) - 1));
1437
1438 mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr);
1439 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
1440 mqd->cp_hqd_eop_control = tmp;
1441
1442 /* disable the queue if it's active */
1443 ring->wptr = 0;
1444 mqd->cp_hqd_pq_rptr = 0;
1445 mqd->cp_hqd_pq_wptr_lo = 0;
1446 mqd->cp_hqd_pq_wptr_hi = 0;
1447
1448 /* set the pointer to the MQD */
1449 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
1450 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
1451
1452 /* set MQD vmid to 0 */
1453 tmp = regCP_MQD_CONTROL_DEFAULT;
1454 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
1455 mqd->cp_mqd_control = tmp;
1456
1457 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
1458 hqd_gpu_addr = ring->gpu_addr >> 8;
1459 mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr);
1460 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
1461
1462 /* set the wb address whether it's enabled or not */
1463 wb_gpu_addr = ring->rptr_gpu_addr;
1464 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
1465 mqd->cp_hqd_pq_rptr_report_addr_hi =
1466 upper_32_bits(wb_gpu_addr) & 0xffff;
1467
1468 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
1469 wb_gpu_addr = ring->wptr_gpu_addr;
1470 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8;
1471 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
1472
1473 /* set up the HQD, this is similar to CP_RB0_CNTL */
1474 tmp = regCP_HQD_PQ_CONTROL_DEFAULT;
1475 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
1476 (order_base_2(ring->ring_size / 4) - 1));
1477 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
1478 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
1479 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1);
1480 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
1481 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
1482 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
1483 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1);
1484 mqd->cp_hqd_pq_control = tmp;
1485
1486 /* enable doorbell */
1487 tmp = 0;
1488 if (ring->use_doorbell) {
1489 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1490 DOORBELL_OFFSET, ring->doorbell_index);
1491 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1492 DOORBELL_EN, 1);
1493 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1494 DOORBELL_SOURCE, 0);
1495 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1496 DOORBELL_HIT, 0);
1497 } else
1498 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1499 DOORBELL_EN, 0);
1500 mqd->cp_hqd_pq_doorbell_control = tmp;
1501
1502 mqd->cp_hqd_vmid = 0;
1503 /* activate the queue */
1504 mqd->cp_hqd_active = 1;
1505
1506 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT;
1507 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE,
1508 PRELOAD_SIZE, 0x55);
1509 mqd->cp_hqd_persistent_state = tmp;
1510
1511 mqd->cp_hqd_ib_control = regCP_HQD_IB_CONTROL_DEFAULT;
1512 mqd->cp_hqd_iq_timer = regCP_HQD_IQ_TIMER_DEFAULT;
1513 mqd->cp_hqd_quantum = regCP_HQD_QUANTUM_DEFAULT;
1514
1515 amdgpu_device_flush_hdp(ring->adev, NULL);
1516 return 0;
1517 }
1518
mes_v11_0_queue_init_register(struct amdgpu_ring * ring)1519 static void mes_v11_0_queue_init_register(struct amdgpu_ring *ring)
1520 {
1521 struct v11_compute_mqd *mqd = ring->mqd_ptr;
1522 struct amdgpu_device *adev = ring->adev;
1523 uint32_t data = 0;
1524
1525 mutex_lock(&adev->srbm_mutex);
1526 soc21_grbm_select(adev, 3, ring->pipe, 0, 0);
1527
1528 /* set CP_HQD_VMID.VMID = 0. */
1529 data = RREG32_SOC15(GC, 0, regCP_HQD_VMID);
1530 data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0);
1531 WREG32_SOC15(GC, 0, regCP_HQD_VMID, data);
1532
1533 /* set CP_HQD_PQ_DOORBELL_CONTROL.DOORBELL_EN=0 */
1534 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL);
1535 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL,
1536 DOORBELL_EN, 0);
1537 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data);
1538
1539 /* set CP_MQD_BASE_ADDR/HI with the MQD base address */
1540 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo);
1541 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
1542
1543 /* set CP_MQD_CONTROL.VMID=0 */
1544 data = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL);
1545 data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0);
1546 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 0);
1547
1548 /* set CP_HQD_PQ_BASE/HI with the ring buffer base address */
1549 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo);
1550 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi);
1551
1552 /* set CP_HQD_PQ_RPTR_REPORT_ADDR/HI */
1553 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR,
1554 mqd->cp_hqd_pq_rptr_report_addr_lo);
1555 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
1556 mqd->cp_hqd_pq_rptr_report_addr_hi);
1557
1558 /* set CP_HQD_PQ_CONTROL */
1559 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control);
1560
1561 /* set CP_HQD_PQ_WPTR_POLL_ADDR/HI */
1562 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR,
1563 mqd->cp_hqd_pq_wptr_poll_addr_lo);
1564 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI,
1565 mqd->cp_hqd_pq_wptr_poll_addr_hi);
1566
1567 /* set CP_HQD_PQ_DOORBELL_CONTROL */
1568 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL,
1569 mqd->cp_hqd_pq_doorbell_control);
1570
1571 /* set CP_HQD_PERSISTENT_STATE.PRELOAD_SIZE=0x53 */
1572 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state);
1573
1574 /* set CP_HQD_ACTIVE.ACTIVE=1 */
1575 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, mqd->cp_hqd_active);
1576
1577 soc21_grbm_select(adev, 0, 0, 0, 0);
1578 mutex_unlock(&adev->srbm_mutex);
1579 }
1580
mes_v11_0_kiq_enable_queue(struct amdgpu_device * adev)1581 static int mes_v11_0_kiq_enable_queue(struct amdgpu_device *adev)
1582 {
1583 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
1584 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring;
1585 int r;
1586
1587 if (!kiq->pmf || !kiq->pmf->kiq_map_queues)
1588 return -EINVAL;
1589
1590 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size);
1591 if (r) {
1592 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
1593 return r;
1594 }
1595
1596 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring[0]);
1597
1598 return amdgpu_ring_test_helper(kiq_ring);
1599 }
1600
mes_v11_0_queue_init(struct amdgpu_device * adev,enum amdgpu_mes_pipe pipe)1601 static int mes_v11_0_queue_init(struct amdgpu_device *adev,
1602 enum amdgpu_mes_pipe pipe)
1603 {
1604 struct amdgpu_ring *ring;
1605 int r;
1606
1607 if (pipe == AMDGPU_MES_KIQ_PIPE) {
1608 ring = &adev->gfx.kiq[0].ring;
1609 } else if (pipe == AMDGPU_MES_SCHED_PIPE) {
1610 ring = &adev->mes.ring[0];
1611 } else {
1612 WARN(1, "Invalid MES pipe %d\n", pipe);
1613 return -EINVAL;
1614 }
1615
1616 if ((pipe == AMDGPU_MES_SCHED_PIPE) &&
1617 (amdgpu_in_reset(adev) || adev->in_suspend)) {
1618 *(ring->wptr_cpu_addr) = 0;
1619 *(ring->rptr_cpu_addr) = 0;
1620 amdgpu_ring_clear_ring(ring);
1621 }
1622
1623 r = mes_v11_0_mqd_init(ring);
1624 if (r)
1625 return r;
1626
1627 if (pipe == AMDGPU_MES_SCHED_PIPE) {
1628 r = mes_v11_0_kiq_enable_queue(adev);
1629 if (r)
1630 return r;
1631 } else {
1632 mes_v11_0_queue_init_register(ring);
1633 }
1634
1635 return 0;
1636 }
1637
mes_v11_0_ring_init(struct amdgpu_device * adev)1638 static int mes_v11_0_ring_init(struct amdgpu_device *adev)
1639 {
1640 struct amdgpu_ring *ring;
1641
1642 ring = &adev->mes.ring[0];
1643
1644 ring->funcs = &mes_v11_0_ring_funcs;
1645
1646 ring->me = 3;
1647 ring->pipe = 0;
1648 ring->queue = 0;
1649
1650 ring->ring_obj = NULL;
1651 ring->use_doorbell = true;
1652 ring->doorbell_index = adev->doorbell_index.mes_ring0 << 1;
1653 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_SCHED_PIPE];
1654 ring->no_scheduler = true;
1655 sprintf(ring->name, "mes_%d.%d.%d", ring->me, ring->pipe, ring->queue);
1656
1657 return amdgpu_ring_init(adev, ring, 1024, NULL, 0,
1658 AMDGPU_RING_PRIO_DEFAULT, NULL);
1659 }
1660
mes_v11_0_kiq_ring_init(struct amdgpu_device * adev)1661 static int mes_v11_0_kiq_ring_init(struct amdgpu_device *adev)
1662 {
1663 struct amdgpu_ring *ring;
1664
1665 spin_lock_init(&adev->gfx.kiq[0].ring_lock);
1666
1667 ring = &adev->gfx.kiq[0].ring;
1668
1669 ring->me = 3;
1670 ring->pipe = 1;
1671 ring->queue = 0;
1672
1673 ring->adev = NULL;
1674 ring->ring_obj = NULL;
1675 ring->use_doorbell = true;
1676 ring->doorbell_index = adev->doorbell_index.mes_ring1 << 1;
1677 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_KIQ_PIPE];
1678 ring->no_scheduler = true;
1679 sprintf(ring->name, "mes_kiq_%d.%d.%d",
1680 ring->me, ring->pipe, ring->queue);
1681
1682 return amdgpu_ring_init(adev, ring, 1024, NULL, 0,
1683 AMDGPU_RING_PRIO_DEFAULT, NULL);
1684 }
1685
mes_v11_0_mqd_sw_init(struct amdgpu_device * adev,enum amdgpu_mes_pipe pipe)1686 static int mes_v11_0_mqd_sw_init(struct amdgpu_device *adev,
1687 enum amdgpu_mes_pipe pipe)
1688 {
1689 int r, mqd_size = sizeof(struct v11_compute_mqd);
1690 struct amdgpu_ring *ring;
1691
1692 if (pipe == AMDGPU_MES_KIQ_PIPE)
1693 ring = &adev->gfx.kiq[0].ring;
1694 else if (pipe == AMDGPU_MES_SCHED_PIPE)
1695 ring = &adev->mes.ring[0];
1696 else
1697 return -EINVAL;
1698
1699 if (ring->mqd_obj)
1700 return 0;
1701
1702 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,
1703 AMDGPU_GEM_DOMAIN_VRAM |
1704 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj,
1705 &ring->mqd_gpu_addr, &ring->mqd_ptr);
1706 if (r) {
1707 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r);
1708 return r;
1709 }
1710
1711 memset(ring->mqd_ptr, 0, mqd_size);
1712
1713 /* prepare MQD backup */
1714 adev->mes.mqd_backup[pipe] = kmalloc(mqd_size, GFP_KERNEL);
1715 if (!adev->mes.mqd_backup[pipe]) {
1716 dev_warn(adev->dev,
1717 "no memory to create MQD backup for ring %s\n",
1718 ring->name);
1719 return -ENOMEM;
1720 }
1721
1722 return 0;
1723 }
1724
mes_v11_0_sw_init(struct amdgpu_ip_block * ip_block)1725 static int mes_v11_0_sw_init(struct amdgpu_ip_block *ip_block)
1726 {
1727 struct amdgpu_device *adev = ip_block->adev;
1728 int pipe, r, bo_size;
1729
1730 adev->mes.funcs = &mes_v11_0_funcs;
1731 adev->mes.kiq_hw_init = &mes_v11_0_kiq_hw_init;
1732 adev->mes.kiq_hw_fini = &mes_v11_0_kiq_hw_fini;
1733
1734 adev->mes.event_log_size = AMDGPU_MES_LOG_BUFFER_SIZE + AMDGPU_MES_MSCRATCH_SIZE;
1735
1736 r = amdgpu_mes_init(adev);
1737 if (r)
1738 return r;
1739
1740 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
1741 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE)
1742 continue;
1743
1744 r = mes_v11_0_allocate_eop_buf(adev, pipe);
1745 if (r)
1746 return r;
1747
1748 r = mes_v11_0_mqd_sw_init(adev, pipe);
1749 if (r)
1750 return r;
1751 }
1752
1753 if (adev->enable_mes_kiq) {
1754 r = mes_v11_0_kiq_ring_init(adev);
1755 if (r)
1756 return r;
1757 }
1758
1759 r = mes_v11_0_ring_init(adev);
1760 if (r)
1761 return r;
1762
1763 bo_size = AMDGPU_GPU_PAGE_SIZE;
1764 if (amdgpu_sriov_is_mes_info_enable(adev))
1765 bo_size += MES11_HW_RESOURCE_1_SIZE;
1766
1767 /* Only needed for AMDGPU_MES_SCHED_PIPE on MES 11*/
1768 r = amdgpu_bo_create_kernel(adev,
1769 bo_size,
1770 PAGE_SIZE,
1771 AMDGPU_GEM_DOMAIN_VRAM,
1772 &adev->mes.resource_1[0],
1773 &adev->mes.resource_1_gpu_addr[0],
1774 &adev->mes.resource_1_addr[0]);
1775 if (r) {
1776 dev_err(adev->dev, "(%d) failed to create mes resource_1 bo\n", r);
1777 return r;
1778 }
1779
1780 return 0;
1781 }
1782
mes_v11_0_sw_fini(struct amdgpu_ip_block * ip_block)1783 static int mes_v11_0_sw_fini(struct amdgpu_ip_block *ip_block)
1784 {
1785 struct amdgpu_device *adev = ip_block->adev;
1786 int pipe;
1787
1788 amdgpu_bo_free_kernel(&adev->mes.resource_1[0], &adev->mes.resource_1_gpu_addr[0],
1789 &adev->mes.resource_1_addr[0]);
1790
1791 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
1792 kfree(adev->mes.mqd_backup[pipe]);
1793
1794 amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[pipe],
1795 &adev->mes.eop_gpu_addr[pipe],
1796 NULL);
1797 amdgpu_ucode_release(&adev->mes.fw[pipe]);
1798 }
1799
1800 amdgpu_bo_free_kernel(&adev->gfx.kiq[0].ring.mqd_obj,
1801 &adev->gfx.kiq[0].ring.mqd_gpu_addr,
1802 &adev->gfx.kiq[0].ring.mqd_ptr);
1803
1804 amdgpu_bo_free_kernel(&adev->mes.ring[0].mqd_obj,
1805 &adev->mes.ring[0].mqd_gpu_addr,
1806 &adev->mes.ring[0].mqd_ptr);
1807
1808 amdgpu_ring_fini(&adev->gfx.kiq[0].ring);
1809 amdgpu_ring_fini(&adev->mes.ring[0]);
1810
1811 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
1812 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_KIQ_PIPE);
1813 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_SCHED_PIPE);
1814 }
1815
1816 amdgpu_mes_fini(adev);
1817 return 0;
1818 }
1819
mes_v11_0_kiq_dequeue(struct amdgpu_ring * ring)1820 static void mes_v11_0_kiq_dequeue(struct amdgpu_ring *ring)
1821 {
1822 uint32_t data;
1823 int i;
1824 struct amdgpu_device *adev = ring->adev;
1825
1826 mutex_lock(&adev->srbm_mutex);
1827 soc21_grbm_select(adev, 3, ring->pipe, 0, 0);
1828
1829 /* disable the queue if it's active */
1830 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) {
1831 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1);
1832 for (i = 0; i < adev->usec_timeout; i++) {
1833 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1))
1834 break;
1835 udelay(1);
1836 }
1837 }
1838 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL);
1839 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL,
1840 DOORBELL_EN, 0);
1841 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL,
1842 DOORBELL_HIT, 1);
1843 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data);
1844
1845 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 0);
1846
1847 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 0);
1848 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 0);
1849 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 0);
1850
1851 soc21_grbm_select(adev, 0, 0, 0, 0);
1852 mutex_unlock(&adev->srbm_mutex);
1853 }
1854
mes_v11_0_kiq_setting(struct amdgpu_ring * ring)1855 static void mes_v11_0_kiq_setting(struct amdgpu_ring *ring)
1856 {
1857 uint32_t tmp;
1858 struct amdgpu_device *adev = ring->adev;
1859
1860 /* tell RLC which is KIQ queue */
1861 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);
1862 tmp &= 0xffffff00;
1863 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
1864 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp | 0x80);
1865 }
1866
mes_v11_0_kiq_clear(struct amdgpu_device * adev)1867 static void mes_v11_0_kiq_clear(struct amdgpu_device *adev)
1868 {
1869 uint32_t tmp;
1870
1871 /* tell RLC which is KIQ dequeue */
1872 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);
1873 tmp &= ~RLC_CP_SCHEDULERS__scheduler0_MASK;
1874 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp);
1875 }
1876
mes_v11_0_kiq_hw_init(struct amdgpu_device * adev,uint32_t xcc_id)1877 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev, uint32_t xcc_id)
1878 {
1879 int r = 0;
1880 struct amdgpu_ip_block *ip_block;
1881
1882 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
1883
1884 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_SCHED_PIPE, false);
1885 if (r) {
1886 DRM_ERROR("failed to load MES fw, r=%d\n", r);
1887 return r;
1888 }
1889
1890 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_KIQ_PIPE, true);
1891 if (r) {
1892 DRM_ERROR("failed to load MES kiq fw, r=%d\n", r);
1893 return r;
1894 }
1895
1896 }
1897
1898 mes_v11_0_enable(adev, true);
1899
1900 mes_v11_0_get_fw_version(adev);
1901
1902 mes_v11_0_kiq_setting(&adev->gfx.kiq[0].ring);
1903
1904 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_MES);
1905 if (unlikely(!ip_block)) {
1906 dev_err(adev->dev, "Failed to get MES handle\n");
1907 return -EINVAL;
1908 }
1909
1910 r = mes_v11_0_queue_init(adev, AMDGPU_MES_KIQ_PIPE);
1911 if (r)
1912 goto failure;
1913
1914 if ((adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x47)
1915 adev->mes.enable_legacy_queue_map = true;
1916 else
1917 adev->mes.enable_legacy_queue_map = false;
1918
1919 if (adev->mes.enable_legacy_queue_map) {
1920 r = mes_v11_0_hw_init(ip_block);
1921 if (r)
1922 goto failure;
1923 }
1924
1925 return r;
1926
1927 failure:
1928 mes_v11_0_hw_fini(ip_block);
1929 return r;
1930 }
1931
mes_v11_0_kiq_hw_fini(struct amdgpu_device * adev,uint32_t xcc_id)1932 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev, uint32_t xcc_id)
1933 {
1934 if (adev->mes.ring[0].sched.ready) {
1935 mes_v11_0_kiq_dequeue(&adev->mes.ring[0]);
1936 adev->mes.ring[0].sched.ready = false;
1937 }
1938
1939 if (amdgpu_sriov_vf(adev)) {
1940 mes_v11_0_kiq_dequeue(&adev->gfx.kiq[0].ring);
1941 mes_v11_0_kiq_clear(adev);
1942 }
1943
1944 mes_v11_0_enable(adev, false);
1945
1946 return 0;
1947 }
1948
mes_v11_0_hw_init(struct amdgpu_ip_block * ip_block)1949 static int mes_v11_0_hw_init(struct amdgpu_ip_block *ip_block)
1950 {
1951 int r;
1952 struct amdgpu_device *adev = ip_block->adev;
1953
1954 if (adev->mes.ring[0].sched.ready)
1955 goto out;
1956
1957 adev->mes.use_rs64mem = false;
1958
1959 if (!adev->enable_mes_kiq) {
1960 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
1961 r = mes_v11_0_load_microcode(adev,
1962 AMDGPU_MES_SCHED_PIPE, true);
1963 if (r) {
1964 DRM_ERROR("failed to MES fw, r=%d\n", r);
1965 return r;
1966 }
1967 }
1968
1969 mes_v11_0_enable(adev, true);
1970 }
1971
1972 r = mes_v11_0_queue_init(adev, AMDGPU_MES_SCHED_PIPE);
1973 if (r)
1974 goto failure;
1975
1976 /* Allocate GPU buffer for array size query results */
1977 r = amdgpu_mes_rs64mem_init(&adev->mes);
1978 if (r) {
1979 dev_warn(adev->dev,
1980 "RS64 local memory init failed (%d),"
1981 "falling back to system memory path\n", r);
1982 adev->mes.use_rs64mem = false;
1983 }
1984 r = mes_v11_0_set_hw_resources(&adev->mes);
1985
1986 if (r)
1987 goto failure;
1988
1989 /*
1990 * QUERY_SCHEDULER_STATUS to get array sizes (N, M).
1991 * MES writes the sizes to the GPU buffer, then we allocate bitmaps.
1992 */
1993 if (adev->mes.use_rs64mem) {
1994 r = mes_v11_0_query_ctx_array_sizes(&adev->mes);
1995 if (r) {
1996 dev_warn(adev->dev,
1997 "Failed to query ctx array sizes (%d),"
1998 "disabling RS64 local memory\n", r);
1999 /* Continue without optimization - not fatal */
2000 adev->mes.use_rs64mem = false;
2001 }
2002 }
2003
2004
2005 if ((adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x52) {
2006 r = mes_v11_0_set_hw_resources_1(&adev->mes);
2007 if (r) {
2008 DRM_ERROR("failed mes_v11_0_set_hw_resources_1, r=%d\n", r);
2009 goto failure;
2010 }
2011 }
2012
2013 r = mes_v11_0_query_sched_status(&adev->mes);
2014 if (r) {
2015 DRM_ERROR("MES is busy\n");
2016 goto failure;
2017 }
2018
2019 r = amdgpu_mes_update_enforce_isolation(adev);
2020 if (r)
2021 goto failure;
2022
2023 amdgpu_mes_validate_fw_version(adev);
2024 out:
2025 /*
2026 * Disable KIQ ring usage from the driver once MES is enabled.
2027 * MES uses KIQ ring exclusively so driver cannot access KIQ ring
2028 * with MES enabled.
2029 */
2030 adev->gfx.kiq[0].ring.sched.ready = false;
2031 adev->mes.ring[0].sched.ready = true;
2032
2033 return 0;
2034
2035 failure:
2036 mes_v11_0_hw_fini(ip_block);
2037 return r;
2038 }
2039
mes_v11_0_hw_fini(struct amdgpu_ip_block * ip_block)2040 static int mes_v11_0_hw_fini(struct amdgpu_ip_block *ip_block)
2041 {
2042 return 0;
2043 }
2044
mes_v11_0_suspend(struct amdgpu_ip_block * ip_block)2045 static int mes_v11_0_suspend(struct amdgpu_ip_block *ip_block)
2046 {
2047 return mes_v11_0_hw_fini(ip_block);
2048 }
2049
mes_v11_0_resume(struct amdgpu_ip_block * ip_block)2050 static int mes_v11_0_resume(struct amdgpu_ip_block *ip_block)
2051 {
2052 return mes_v11_0_hw_init(ip_block);
2053 }
2054
mes_v11_0_early_init(struct amdgpu_ip_block * ip_block)2055 static int mes_v11_0_early_init(struct amdgpu_ip_block *ip_block)
2056 {
2057 struct amdgpu_device *adev = ip_block->adev;
2058 int pipe, r;
2059
2060 adev->mes.hung_queue_db_array_size = MES11_HUNG_DB_OFFSET_ARRAY_SIZE;
2061 adev->mes.hung_queue_hqd_info_offset = MES11_HUNG_HQD_INFO_OFFSET;
2062
2063 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
2064 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE)
2065 continue;
2066 r = amdgpu_mes_init_microcode(adev, pipe);
2067 if (r)
2068 return r;
2069 }
2070
2071 return 0;
2072 }
2073
2074 static const struct amd_ip_funcs mes_v11_0_ip_funcs = {
2075 .name = "mes_v11_0",
2076 .early_init = mes_v11_0_early_init,
2077 .late_init = NULL,
2078 .sw_init = mes_v11_0_sw_init,
2079 .sw_fini = mes_v11_0_sw_fini,
2080 .hw_init = mes_v11_0_hw_init,
2081 .hw_fini = mes_v11_0_hw_fini,
2082 .suspend = mes_v11_0_suspend,
2083 .resume = mes_v11_0_resume,
2084 };
2085
2086 const struct amdgpu_ip_block_version mes_v11_0_ip_block = {
2087 .type = AMD_IP_BLOCK_TYPE_MES,
2088 .major = 11,
2089 .minor = 0,
2090 .rev = 0,
2091 .funcs = &mes_v11_0_ip_funcs,
2092 };
2093