1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved.
24 * Copyright 2016 Nexenta Systems, Inc. All rights reserved.
25 * Copyright (c) 2017, Joyent, Inc.
26 * Copyright 2014 OmniTI Computer Consulting, Inc. All rights reserved.
27 * Copyright (c) 2014, Tegile Systems Inc. All rights reserved.
28 */
29
30 /*
31 * Copyright (c) 2000 to 2010, LSI Corporation.
32 * All rights reserved.
33 *
34 * Redistribution and use in source and binary forms of all code within
35 * this file that is exclusively owned by LSI, with or without
36 * modification, is permitted provided that, in addition to the CDDL 1.0
37 * License requirements, the following conditions are met:
38 *
39 * Neither the name of the author nor the names of its contributors may be
40 * used to endorse or promote products derived from this software without
41 * specific prior written permission.
42 *
43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
46 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
47 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
48 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
49 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
50 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
51 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
52 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
53 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
54 * DAMAGE.
55 */
56
57 /*
58 * mptsas - This is a driver based on LSI Logic's MPT2.0/2.5 interface.
59 *
60 */
61
62 #if defined(lint) || defined(DEBUG)
63 #define MPTSAS_DEBUG
64 #endif
65
66 /*
67 * standard header files.
68 */
69 #include <sys/note.h>
70 #include <sys/scsi/scsi.h>
71 #include <sys/pci.h>
72 #include <sys/file.h>
73 #include <sys/policy.h>
74 #include <sys/model.h>
75 #include <sys/sysevent.h>
76 #include <sys/sysevent/eventdefs.h>
77 #include <sys/sysevent/dr.h>
78 #include <sys/sata/sata_defs.h>
79 #include <sys/sata/sata_hba.h>
80 #include <sys/scsi/generic/sas.h>
81 #include <sys/scsi/impl/scsi_sas.h>
82
83 #pragma pack(1)
84 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_type.h>
85 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2.h>
86 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_cnfg.h>
87 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_init.h>
88 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_ioc.h>
89 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_sas.h>
90 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_tool.h>
91 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_raid.h>
92 #pragma pack()
93
94 /*
95 * private header files.
96 *
97 */
98 #include <sys/scsi/impl/scsi_reset_notify.h>
99 #include <sys/scsi/adapters/mpt_sas/mptsas_var.h>
100 #include <sys/scsi/adapters/mpt_sas/mptsas_ioctl.h>
101 #include <sys/scsi/adapters/mpt_sas/mptsas_smhba.h>
102 #include <sys/scsi/adapters/mpt_sas/mptsas_hash.h>
103 #include <sys/raidioctl.h>
104
105 #include <sys/fs/dv_node.h> /* devfs_clean */
106
107 /*
108 * FMA header files
109 */
110 #include <sys/ddifm.h>
111 #include <sys/fm/protocol.h>
112 #include <sys/fm/util.h>
113 #include <sys/fm/io/ddi.h>
114
115 /*
116 * autoconfiguration data and routines.
117 */
118 static int mptsas_attach(dev_info_t *dip, ddi_attach_cmd_t cmd);
119 static int mptsas_detach(dev_info_t *devi, ddi_detach_cmd_t cmd);
120 static int mptsas_power(dev_info_t *dip, int component, int level);
121
122 /*
123 * cb_ops function
124 */
125 static int mptsas_ioctl(dev_t dev, int cmd, intptr_t data, int mode,
126 cred_t *credp, int *rval);
127 #ifdef __sparc
128 static int mptsas_reset(dev_info_t *devi, ddi_reset_cmd_t cmd);
129 #else /* __sparc */
130 static int mptsas_quiesce(dev_info_t *devi);
131 #endif /* __sparc */
132
133 /*
134 * Resource initilaization for hardware
135 */
136 static void mptsas_setup_cmd_reg(mptsas_t *mpt);
137 static void mptsas_disable_bus_master(mptsas_t *mpt);
138 static void mptsas_hba_fini(mptsas_t *mpt);
139 static void mptsas_cfg_fini(mptsas_t *mptsas_blkp);
140 static int mptsas_hba_setup(mptsas_t *mpt);
141 static void mptsas_hba_teardown(mptsas_t *mpt);
142 static int mptsas_config_space_init(mptsas_t *mpt);
143 static void mptsas_config_space_fini(mptsas_t *mpt);
144 static void mptsas_iport_register(mptsas_t *mpt);
145 static int mptsas_smp_setup(mptsas_t *mpt);
146 static void mptsas_smp_teardown(mptsas_t *mpt);
147 static int mptsas_enc_setup(mptsas_t *mpt);
148 static void mptsas_enc_teardown(mptsas_t *mpt);
149 static int mptsas_cache_create(mptsas_t *mpt);
150 static void mptsas_cache_destroy(mptsas_t *mpt);
151 static int mptsas_alloc_request_frames(mptsas_t *mpt);
152 static int mptsas_alloc_sense_bufs(mptsas_t *mpt);
153 static int mptsas_alloc_reply_frames(mptsas_t *mpt);
154 static int mptsas_alloc_free_queue(mptsas_t *mpt);
155 static int mptsas_alloc_post_queue(mptsas_t *mpt);
156 static void mptsas_alloc_reply_args(mptsas_t *mpt);
157 static int mptsas_alloc_extra_sgl_frame(mptsas_t *mpt, mptsas_cmd_t *cmd);
158 static void mptsas_free_extra_sgl_frame(mptsas_t *mpt, mptsas_cmd_t *cmd);
159 static int mptsas_init_chip(mptsas_t *mpt, int first_time);
160 static void mptsas_update_hashtab(mptsas_t *mpt);
161
162 /*
163 * SCSA function prototypes
164 */
165 static int mptsas_scsi_start(struct scsi_address *ap, struct scsi_pkt *pkt);
166 static int mptsas_scsi_reset(struct scsi_address *ap, int level);
167 static int mptsas_scsi_abort(struct scsi_address *ap, struct scsi_pkt *pkt);
168 static int mptsas_scsi_getcap(struct scsi_address *ap, char *cap, int tgtonly);
169 static int mptsas_scsi_setcap(struct scsi_address *ap, char *cap, int value,
170 int tgtonly);
171 static void mptsas_scsi_dmafree(struct scsi_address *ap, struct scsi_pkt *pkt);
172 static struct scsi_pkt *mptsas_scsi_init_pkt(struct scsi_address *ap,
173 struct scsi_pkt *pkt, struct buf *bp, int cmdlen, int statuslen,
174 int tgtlen, int flags, int (*callback)(), caddr_t arg);
175 static void mptsas_scsi_sync_pkt(struct scsi_address *ap, struct scsi_pkt *pkt);
176 static void mptsas_scsi_destroy_pkt(struct scsi_address *ap,
177 struct scsi_pkt *pkt);
178 static int mptsas_scsi_tgt_init(dev_info_t *hba_dip, dev_info_t *tgt_dip,
179 scsi_hba_tran_t *hba_tran, struct scsi_device *sd);
180 static void mptsas_scsi_tgt_free(dev_info_t *hba_dip, dev_info_t *tgt_dip,
181 scsi_hba_tran_t *hba_tran, struct scsi_device *sd);
182 static int mptsas_scsi_reset_notify(struct scsi_address *ap, int flag,
183 void (*callback)(caddr_t), caddr_t arg);
184 static int mptsas_get_name(struct scsi_device *sd, char *name, int len);
185 static int mptsas_get_bus_addr(struct scsi_device *sd, char *name, int len);
186 static int mptsas_scsi_quiesce(dev_info_t *dip);
187 static int mptsas_scsi_unquiesce(dev_info_t *dip);
188 static int mptsas_bus_config(dev_info_t *pdip, uint_t flags,
189 ddi_bus_config_op_t op, void *arg, dev_info_t **childp);
190
191 /*
192 * SMP functions
193 */
194 static int mptsas_smp_start(struct smp_pkt *smp_pkt);
195
196 /*
197 * internal function prototypes.
198 */
199 static void mptsas_list_add(mptsas_t *mpt);
200 static void mptsas_list_del(mptsas_t *mpt);
201
202 static int mptsas_quiesce_bus(mptsas_t *mpt);
203 static int mptsas_unquiesce_bus(mptsas_t *mpt);
204
205 static int mptsas_alloc_handshake_msg(mptsas_t *mpt, size_t alloc_size);
206 static void mptsas_free_handshake_msg(mptsas_t *mpt);
207
208 static void mptsas_ncmds_checkdrain(void *arg);
209
210 static int mptsas_prepare_pkt(mptsas_cmd_t *cmd);
211 static int mptsas_accept_pkt(mptsas_t *mpt, mptsas_cmd_t *sp);
212 static int mptsas_accept_txwq_and_pkt(mptsas_t *mpt, mptsas_cmd_t *sp);
213 static void mptsas_accept_tx_waitq(mptsas_t *mpt);
214
215 static int mptsas_do_detach(dev_info_t *dev);
216 static int mptsas_do_scsi_reset(mptsas_t *mpt, uint16_t devhdl);
217 static int mptsas_do_scsi_abort(mptsas_t *mpt, int target, int lun,
218 struct scsi_pkt *pkt);
219 static int mptsas_scsi_capchk(char *cap, int tgtonly, int *cidxp);
220
221 static void mptsas_handle_qfull(mptsas_t *mpt, mptsas_cmd_t *cmd);
222 static void mptsas_handle_event(void *args);
223 static int mptsas_handle_event_sync(void *args);
224 static void mptsas_handle_dr(void *args);
225 static void mptsas_handle_topo_change(mptsas_topo_change_list_t *topo_node,
226 dev_info_t *pdip);
227
228 static void mptsas_restart_cmd(void *);
229
230 static void mptsas_flush_hba(mptsas_t *mpt);
231 static void mptsas_flush_target(mptsas_t *mpt, ushort_t target, int lun,
232 uint8_t tasktype);
233 static void mptsas_set_pkt_reason(mptsas_t *mpt, mptsas_cmd_t *cmd,
234 uchar_t reason, uint_t stat);
235
236 static uint_t mptsas_intr(caddr_t arg1, caddr_t arg2);
237 static void mptsas_process_intr(mptsas_t *mpt,
238 pMpi2ReplyDescriptorsUnion_t reply_desc_union);
239 static void mptsas_handle_scsi_io_success(mptsas_t *mpt,
240 pMpi2ReplyDescriptorsUnion_t reply_desc);
241 static void mptsas_handle_address_reply(mptsas_t *mpt,
242 pMpi2ReplyDescriptorsUnion_t reply_desc);
243 static int mptsas_wait_intr(mptsas_t *mpt, int polltime);
244 static void mptsas_sge_setup(mptsas_t *mpt, mptsas_cmd_t *cmd,
245 uint32_t *control, pMpi2SCSIIORequest_t frame, ddi_acc_handle_t acc_hdl);
246
247 static void mptsas_watch(void *arg);
248 static void mptsas_watchsubr(mptsas_t *mpt);
249 static void mptsas_cmd_timeout(mptsas_t *mpt, mptsas_target_t *ptgt);
250
251 static void mptsas_start_passthru(mptsas_t *mpt, mptsas_cmd_t *cmd);
252 static int mptsas_do_passthru(mptsas_t *mpt, uint8_t *request, uint8_t *reply,
253 uint8_t *data, uint32_t request_size, uint32_t reply_size,
254 uint32_t data_size, uint32_t direction, uint8_t *dataout,
255 uint32_t dataout_size, short timeout, int mode);
256 static int mptsas_free_devhdl(mptsas_t *mpt, uint16_t devhdl);
257
258 static uint8_t mptsas_get_fw_diag_buffer_number(mptsas_t *mpt,
259 uint32_t unique_id);
260 static void mptsas_start_diag(mptsas_t *mpt, mptsas_cmd_t *cmd);
261 static int mptsas_post_fw_diag_buffer(mptsas_t *mpt,
262 mptsas_fw_diagnostic_buffer_t *pBuffer, uint32_t *return_code);
263 static int mptsas_release_fw_diag_buffer(mptsas_t *mpt,
264 mptsas_fw_diagnostic_buffer_t *pBuffer, uint32_t *return_code,
265 uint32_t diag_type);
266 static int mptsas_diag_register(mptsas_t *mpt,
267 mptsas_fw_diag_register_t *diag_register, uint32_t *return_code);
268 static int mptsas_diag_unregister(mptsas_t *mpt,
269 mptsas_fw_diag_unregister_t *diag_unregister, uint32_t *return_code);
270 static int mptsas_diag_query(mptsas_t *mpt, mptsas_fw_diag_query_t *diag_query,
271 uint32_t *return_code);
272 static int mptsas_diag_read_buffer(mptsas_t *mpt,
273 mptsas_diag_read_buffer_t *diag_read_buffer, uint8_t *ioctl_buf,
274 uint32_t *return_code, int ioctl_mode);
275 static int mptsas_diag_release(mptsas_t *mpt,
276 mptsas_fw_diag_release_t *diag_release, uint32_t *return_code);
277 static int mptsas_do_diag_action(mptsas_t *mpt, uint32_t action,
278 uint8_t *diag_action, uint32_t length, uint32_t *return_code,
279 int ioctl_mode);
280 static int mptsas_diag_action(mptsas_t *mpt, mptsas_diag_action_t *data,
281 int mode);
282
283 static int mptsas_pkt_alloc_extern(mptsas_t *mpt, mptsas_cmd_t *cmd,
284 int cmdlen, int tgtlen, int statuslen, int kf);
285 static void mptsas_pkt_destroy_extern(mptsas_t *mpt, mptsas_cmd_t *cmd);
286
287 static int mptsas_kmem_cache_constructor(void *buf, void *cdrarg, int kmflags);
288 static void mptsas_kmem_cache_destructor(void *buf, void *cdrarg);
289
290 static int mptsas_cache_frames_constructor(void *buf, void *cdrarg,
291 int kmflags);
292 static void mptsas_cache_frames_destructor(void *buf, void *cdrarg);
293
294 static void mptsas_check_scsi_io_error(mptsas_t *mpt, pMpi2SCSIIOReply_t reply,
295 mptsas_cmd_t *cmd);
296 static void mptsas_check_task_mgt(mptsas_t *mpt,
297 pMpi2SCSIManagementReply_t reply, mptsas_cmd_t *cmd);
298 static int mptsas_send_scsi_cmd(mptsas_t *mpt, struct scsi_address *ap,
299 mptsas_target_t *ptgt, uchar_t *cdb, int cdblen, struct buf *data_bp,
300 int *resid);
301
302 static int mptsas_alloc_active_slots(mptsas_t *mpt, int flag);
303 static void mptsas_free_active_slots(mptsas_t *mpt);
304 static int mptsas_start_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd);
305
306 static void mptsas_restart_hba(mptsas_t *mpt);
307 static void mptsas_restart_waitq(mptsas_t *mpt);
308
309 static void mptsas_deliver_doneq_thread(mptsas_t *mpt);
310 static void mptsas_doneq_add(mptsas_t *mpt, mptsas_cmd_t *cmd);
311 static void mptsas_doneq_mv(mptsas_t *mpt, uint64_t t);
312
313 static mptsas_cmd_t *mptsas_doneq_thread_rm(mptsas_t *mpt, uint64_t t);
314 static void mptsas_doneq_empty(mptsas_t *mpt);
315 static void mptsas_doneq_thread(mptsas_doneq_thread_arg_t *arg);
316
317 static mptsas_cmd_t *mptsas_waitq_rm(mptsas_t *mpt);
318 static void mptsas_waitq_delete(mptsas_t *mpt, mptsas_cmd_t *cmd);
319 static mptsas_cmd_t *mptsas_tx_waitq_rm(mptsas_t *mpt);
320 static void mptsas_tx_waitq_delete(mptsas_t *mpt, mptsas_cmd_t *cmd);
321
322
323 static void mptsas_start_watch_reset_delay();
324 static void mptsas_setup_bus_reset_delay(mptsas_t *mpt);
325 static void mptsas_watch_reset_delay(void *arg);
326 static int mptsas_watch_reset_delay_subr(mptsas_t *mpt);
327
328 /*
329 * helper functions
330 */
331 static void mptsas_dump_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd);
332
333 static dev_info_t *mptsas_find_child(dev_info_t *pdip, char *name);
334 static dev_info_t *mptsas_find_child_phy(dev_info_t *pdip, uint8_t phy);
335 static dev_info_t *mptsas_find_child_addr(dev_info_t *pdip, uint64_t sasaddr,
336 int lun);
337 static mdi_pathinfo_t *mptsas_find_path_addr(dev_info_t *pdip, uint64_t sasaddr,
338 int lun);
339 static mdi_pathinfo_t *mptsas_find_path_phy(dev_info_t *pdip, uint8_t phy);
340 static dev_info_t *mptsas_find_smp_child(dev_info_t *pdip, char *str_wwn);
341
342 static int mptsas_parse_address(char *name, uint64_t *wwid, uint8_t *phy,
343 int *lun);
344 static int mptsas_parse_smp_name(char *name, uint64_t *wwn);
345
346 static mptsas_target_t *mptsas_phy_to_tgt(mptsas_t *mpt,
347 mptsas_phymask_t phymask, uint8_t phy);
348 static mptsas_target_t *mptsas_wwid_to_ptgt(mptsas_t *mpt,
349 mptsas_phymask_t phymask, uint64_t wwid);
350 static mptsas_smp_t *mptsas_wwid_to_psmp(mptsas_t *mpt,
351 mptsas_phymask_t phymask, uint64_t wwid);
352
353 static int mptsas_inquiry(mptsas_t *mpt, mptsas_target_t *ptgt, int lun,
354 uchar_t page, unsigned char *buf, int len, int *rlen, uchar_t evpd);
355
356 static int mptsas_get_target_device_info(mptsas_t *mpt, uint32_t page_address,
357 uint16_t *handle, mptsas_target_t **pptgt);
358 static void mptsas_update_phymask(mptsas_t *mpt);
359
360 static int mptsas_flush_led_status(mptsas_t *mpt, mptsas_enclosure_t *mep,
361 uint16_t idx);
362 static int mptsas_send_sep(mptsas_t *mpt, mptsas_enclosure_t *mep, uint16_t idx,
363 uint32_t *status, uint8_t cmd);
364 static dev_info_t *mptsas_get_dip_from_dev(dev_t dev,
365 mptsas_phymask_t *phymask);
366 static mptsas_target_t *mptsas_addr_to_ptgt(mptsas_t *mpt, char *addr,
367 mptsas_phymask_t phymask);
368
369
370 /*
371 * Enumeration / DR functions
372 */
373 static void mptsas_config_all(dev_info_t *pdip);
374 static int mptsas_config_one_addr(dev_info_t *pdip, uint64_t sasaddr, int lun,
375 dev_info_t **lundip);
376 static int mptsas_config_one_phy(dev_info_t *pdip, uint8_t phy, int lun,
377 dev_info_t **lundip);
378
379 static int mptsas_config_target(dev_info_t *pdip, mptsas_target_t *ptgt);
380 static int mptsas_offline_target(dev_info_t *pdip, char *name);
381
382 static int mptsas_config_raid(dev_info_t *pdip, uint16_t target,
383 dev_info_t **dip);
384
385 static int mptsas_config_luns(dev_info_t *pdip, mptsas_target_t *ptgt);
386 static int mptsas_probe_lun(dev_info_t *pdip, int lun,
387 dev_info_t **dip, mptsas_target_t *ptgt);
388
389 static int mptsas_create_lun(dev_info_t *pdip, struct scsi_inquiry *sd_inq,
390 dev_info_t **dip, mptsas_target_t *ptgt, int lun);
391
392 static int mptsas_create_phys_lun(dev_info_t *pdip, struct scsi_inquiry *sd,
393 char *guid, dev_info_t **dip, mptsas_target_t *ptgt, int lun);
394 static int mptsas_create_virt_lun(dev_info_t *pdip, struct scsi_inquiry *sd,
395 char *guid, dev_info_t **dip, mdi_pathinfo_t **pip, mptsas_target_t *ptgt,
396 int lun);
397
398 static void mptsas_offline_missed_luns(dev_info_t *pdip,
399 uint16_t *repluns, int lun_cnt, mptsas_target_t *ptgt);
400 static int mptsas_offline_lun(dev_info_t *pdip, dev_info_t *rdip,
401 mdi_pathinfo_t *rpip, uint_t flags);
402
403 static int mptsas_config_smp(dev_info_t *pdip, uint64_t sas_wwn,
404 dev_info_t **smp_dip);
405 static int mptsas_offline_smp(dev_info_t *pdip, mptsas_smp_t *smp_node,
406 uint_t flags);
407
408 static int mptsas_event_query(mptsas_t *mpt, mptsas_event_query_t *data,
409 int mode, int *rval);
410 static int mptsas_event_enable(mptsas_t *mpt, mptsas_event_enable_t *data,
411 int mode, int *rval);
412 static int mptsas_event_report(mptsas_t *mpt, mptsas_event_report_t *data,
413 int mode, int *rval);
414 static void mptsas_record_event(void *args);
415 static int mptsas_reg_access(mptsas_t *mpt, mptsas_reg_access_t *data,
416 int mode);
417
418 mptsas_target_t *mptsas_tgt_alloc(refhash_t *, uint16_t, uint64_t,
419 uint32_t, mptsas_phymask_t, uint8_t);
420 static mptsas_smp_t *mptsas_smp_alloc(mptsas_t *, mptsas_smp_t *);
421 static int mptsas_online_smp(dev_info_t *pdip, mptsas_smp_t *smp_node,
422 dev_info_t **smp_dip);
423
424 /*
425 * Power management functions
426 */
427 static int mptsas_get_pci_cap(mptsas_t *mpt);
428 static int mptsas_init_pm(mptsas_t *mpt);
429
430 /*
431 * MPT MSI tunable:
432 *
433 * By default MSI is enabled on all supported platforms.
434 */
435 boolean_t mptsas_enable_msi = B_TRUE;
436 boolean_t mptsas_physical_bind_failed_page_83 = B_FALSE;
437
438 /*
439 * Global switch for use of MPI2.5 FAST PATH.
440 * We don't really know what FAST PATH actually does, so if it is suspected
441 * to cause problems it can be turned off by setting this variable to B_FALSE.
442 */
443 boolean_t mptsas_use_fastpath = B_TRUE;
444
445 static int mptsas_register_intrs(mptsas_t *);
446 static void mptsas_unregister_intrs(mptsas_t *);
447 static int mptsas_add_intrs(mptsas_t *, int);
448 static void mptsas_rem_intrs(mptsas_t *);
449
450 /*
451 * FMA Prototypes
452 */
453 static void mptsas_fm_init(mptsas_t *mpt);
454 static void mptsas_fm_fini(mptsas_t *mpt);
455 static int mptsas_fm_error_cb(dev_info_t *, ddi_fm_error_t *, const void *);
456
457 extern pri_t minclsyspri, maxclsyspri;
458
459 /*
460 * This device is created by the SCSI pseudo nexus driver (SCSI vHCI). It is
461 * under this device that the paths to a physical device are created when
462 * MPxIO is used.
463 */
464 extern dev_info_t *scsi_vhci_dip;
465
466 /*
467 * Tunable timeout value for Inquiry VPD page 0x83
468 * By default the value is 30 seconds.
469 */
470 int mptsas_inq83_retry_timeout = 30;
471
472 /*
473 * This is used to allocate memory for message frame storage, not for
474 * data I/O DMA. All message frames must be stored in the first 4G of
475 * physical memory.
476 */
477 ddi_dma_attr_t mptsas_dma_attrs = {
478 DMA_ATTR_V0, /* attribute layout version */
479 0x0ull, /* address low - should be 0 (longlong) */
480 0xffffffffull, /* address high - 32-bit max range */
481 0x00ffffffull, /* count max - max DMA object size */
482 4, /* allocation alignment requirements */
483 0x78, /* burstsizes - binary encoded values */
484 1, /* minxfer - gran. of DMA engine */
485 0x00ffffffull, /* maxxfer - gran. of DMA engine */
486 0xffffffffull, /* max segment size (DMA boundary) */
487 MPTSAS_MAX_DMA_SEGS, /* scatter/gather list length */
488 512, /* granularity - device transfer size */
489 0 /* flags, set to 0 */
490 };
491
492 /*
493 * This is used for data I/O DMA memory allocation. (full 64-bit DMA
494 * physical addresses are supported.)
495 */
496 ddi_dma_attr_t mptsas_dma_attrs64 = {
497 DMA_ATTR_V0, /* attribute layout version */
498 0x0ull, /* address low - should be 0 (longlong) */
499 0xffffffffffffffffull, /* address high - 64-bit max */
500 0x00ffffffull, /* count max - max DMA object size */
501 4, /* allocation alignment requirements */
502 0x78, /* burstsizes - binary encoded values */
503 1, /* minxfer - gran. of DMA engine */
504 0x00ffffffull, /* maxxfer - gran. of DMA engine */
505 0xffffffffull, /* max segment size (DMA boundary) */
506 MPTSAS_MAX_DMA_SEGS, /* scatter/gather list length */
507 512, /* granularity - device transfer size */
508 0 /* flags, set to 0 */
509 };
510
511 ddi_device_acc_attr_t mptsas_dev_attr = {
512 DDI_DEVICE_ATTR_V1,
513 DDI_STRUCTURE_LE_ACC,
514 DDI_STRICTORDER_ACC,
515 DDI_DEFAULT_ACC
516 };
517
518 static struct cb_ops mptsas_cb_ops = {
519 scsi_hba_open, /* open */
520 scsi_hba_close, /* close */
521 nodev, /* strategy */
522 nodev, /* print */
523 nodev, /* dump */
524 nodev, /* read */
525 nodev, /* write */
526 mptsas_ioctl, /* ioctl */
527 nodev, /* devmap */
528 nodev, /* mmap */
529 nodev, /* segmap */
530 nochpoll, /* chpoll */
531 ddi_prop_op, /* cb_prop_op */
532 NULL, /* streamtab */
533 D_MP, /* cb_flag */
534 CB_REV, /* rev */
535 nodev, /* aread */
536 nodev /* awrite */
537 };
538
539 static struct dev_ops mptsas_ops = {
540 DEVO_REV, /* devo_rev, */
541 0, /* refcnt */
542 ddi_no_info, /* info */
543 nulldev, /* identify */
544 nulldev, /* probe */
545 mptsas_attach, /* attach */
546 mptsas_detach, /* detach */
547 #ifdef __sparc
548 mptsas_reset,
549 #else
550 nodev, /* reset */
551 #endif /* __sparc */
552 &mptsas_cb_ops, /* driver operations */
553 NULL, /* bus operations */
554 mptsas_power, /* power management */
555 #ifdef __sparc
556 ddi_quiesce_not_needed
557 #else
558 mptsas_quiesce /* quiesce */
559 #endif /* __sparc */
560 };
561
562
563 #define MPTSAS_MOD_STRING "MPTSAS HBA Driver 00.00.00.24"
564
565 static struct modldrv modldrv = {
566 &mod_driverops, /* Type of module. This one is a driver */
567 MPTSAS_MOD_STRING, /* Name of the module. */
568 &mptsas_ops, /* driver ops */
569 };
570
571 static struct modlinkage modlinkage = {
572 MODREV_1, &modldrv, NULL
573 };
574 #define TARGET_PROP "target"
575 #define LUN_PROP "lun"
576 #define LUN64_PROP "lun64"
577 #define SAS_PROP "sas-mpt"
578 #define MDI_GUID "wwn"
579 #define NDI_GUID "guid"
580 #define MPTSAS_DEV_GONE "mptsas_dev_gone"
581
582 /*
583 * Local static data
584 */
585 #if defined(MPTSAS_DEBUG)
586 /*
587 * Flags to indicate which debug messages are to be printed and which go to the
588 * debug log ring buffer. Default is to not print anything, and to log
589 * everything except the watchsubr() output which normally happens every second.
590 */
591 uint32_t mptsas_debugprt_flags = 0x0;
592 uint32_t mptsas_debuglog_flags = ~(1U << 30);
593 #endif /* defined(MPTSAS_DEBUG) */
594 uint32_t mptsas_debug_resets = 0;
595
596 static kmutex_t mptsas_global_mutex;
597 static void *mptsas_state; /* soft state ptr */
598 static krwlock_t mptsas_global_rwlock;
599
600 static kmutex_t mptsas_log_mutex;
601 static char mptsas_log_buf[256];
602 _NOTE(MUTEX_PROTECTS_DATA(mptsas_log_mutex, mptsas_log_buf))
603
604 static mptsas_t *mptsas_head, *mptsas_tail;
605 static clock_t mptsas_scsi_watchdog_tick;
606 static clock_t mptsas_tick;
607 static timeout_id_t mptsas_reset_watch;
608 static timeout_id_t mptsas_timeout_id;
609 static int mptsas_timeouts_enabled = 0;
610
611 /*
612 * Default length for extended auto request sense buffers.
613 * All sense buffers need to be under the same alloc because there
614 * is only one common top 32bits (of 64bits) address register.
615 * Most requests only require 32 bytes, but some request >256.
616 * We use rmalloc()/rmfree() on this additional memory to manage the
617 * "extended" requests.
618 */
619 int mptsas_extreq_sense_bufsize = 256*64;
620
621 /*
622 * We believe that all software resrictions of having to run with DMA
623 * attributes to limit allocation to the first 4G are removed.
624 * However, this flag remains to enable quick switchback should suspicious
625 * problems emerge.
626 * Note that scsi_alloc_consistent_buf() does still adhere to allocating
627 * 32 bit addressable memory, but we can cope if that is changed now.
628 */
629 int mptsas_use_64bit_msgaddr = 1;
630
631 /*
632 * warlock directives
633 */
634 _NOTE(SCHEME_PROTECTS_DATA("unique per pkt", scsi_pkt \
635 mptsas_cmd NcrTableIndirect buf scsi_cdb scsi_status))
636 _NOTE(SCHEME_PROTECTS_DATA("unique per pkt", smp_pkt))
637 _NOTE(SCHEME_PROTECTS_DATA("stable data", scsi_device scsi_address))
638 _NOTE(SCHEME_PROTECTS_DATA("No Mutex Needed", mptsas_tgt_private))
639 _NOTE(SCHEME_PROTECTS_DATA("No Mutex Needed", scsi_hba_tran::tran_tgt_private))
640
641 /*
642 * SM - HBA statics
643 */
644 char *mptsas_driver_rev = MPTSAS_MOD_STRING;
645
646 #ifdef MPTSAS_DEBUG
647 void debug_enter(char *);
648 #endif
649
650 /*
651 * Notes:
652 * - scsi_hba_init(9F) initializes SCSI HBA modules
653 * - must call scsi_hba_fini(9F) if modload() fails
654 */
655 int
_init(void)656 _init(void)
657 {
658 int status;
659 /* CONSTCOND */
660 ASSERT(NO_COMPETING_THREADS);
661
662 NDBG0(("_init"));
663
664 status = ddi_soft_state_init(&mptsas_state, MPTSAS_SIZE,
665 MPTSAS_INITIAL_SOFT_SPACE);
666 if (status != 0) {
667 return (status);
668 }
669
670 if ((status = scsi_hba_init(&modlinkage)) != 0) {
671 ddi_soft_state_fini(&mptsas_state);
672 return (status);
673 }
674
675 mutex_init(&mptsas_global_mutex, NULL, MUTEX_DRIVER, NULL);
676 rw_init(&mptsas_global_rwlock, NULL, RW_DRIVER, NULL);
677 mutex_init(&mptsas_log_mutex, NULL, MUTEX_DRIVER, NULL);
678
679 if ((status = mod_install(&modlinkage)) != 0) {
680 mutex_destroy(&mptsas_log_mutex);
681 rw_destroy(&mptsas_global_rwlock);
682 mutex_destroy(&mptsas_global_mutex);
683 ddi_soft_state_fini(&mptsas_state);
684 scsi_hba_fini(&modlinkage);
685 }
686
687 return (status);
688 }
689
690 /*
691 * Notes:
692 * - scsi_hba_fini(9F) uninitializes SCSI HBA modules
693 */
694 int
_fini(void)695 _fini(void)
696 {
697 int status;
698 /* CONSTCOND */
699 ASSERT(NO_COMPETING_THREADS);
700
701 NDBG0(("_fini"));
702
703 if ((status = mod_remove(&modlinkage)) == 0) {
704 ddi_soft_state_fini(&mptsas_state);
705 scsi_hba_fini(&modlinkage);
706 mutex_destroy(&mptsas_global_mutex);
707 rw_destroy(&mptsas_global_rwlock);
708 mutex_destroy(&mptsas_log_mutex);
709 }
710 return (status);
711 }
712
713 /*
714 * The loadable-module _info(9E) entry point
715 */
716 int
_info(struct modinfo * modinfop)717 _info(struct modinfo *modinfop)
718 {
719 /* CONSTCOND */
720 ASSERT(NO_COMPETING_THREADS);
721 NDBG0(("mptsas _info"));
722
723 return (mod_info(&modlinkage, modinfop));
724 }
725
726 static int
mptsas_target_eval_devhdl(const void * op,void * arg)727 mptsas_target_eval_devhdl(const void *op, void *arg)
728 {
729 uint16_t dh = *(uint16_t *)arg;
730 const mptsas_target_t *tp = op;
731
732 return ((int)tp->m_devhdl - (int)dh);
733 }
734
735 static int
mptsas_target_eval_nowwn(const void * op,void * arg)736 mptsas_target_eval_nowwn(const void *op, void *arg)
737 {
738 uint8_t phy = *(uint8_t *)arg;
739 const mptsas_target_t *tp = op;
740
741 if (tp->m_addr.mta_wwn != 0)
742 return (-1);
743
744 return ((int)tp->m_phynum - (int)phy);
745 }
746
747 static int
mptsas_smp_eval_devhdl(const void * op,void * arg)748 mptsas_smp_eval_devhdl(const void *op, void *arg)
749 {
750 uint16_t dh = *(uint16_t *)arg;
751 const mptsas_smp_t *sp = op;
752
753 return ((int)sp->m_devhdl - (int)dh);
754 }
755
756 static uint64_t
mptsas_target_addr_hash(const void * tp)757 mptsas_target_addr_hash(const void *tp)
758 {
759 const mptsas_target_addr_t *tap = tp;
760
761 return ((tap->mta_wwn & 0xffffffffffffULL) |
762 ((uint64_t)tap->mta_phymask << 48));
763 }
764
765 static int
mptsas_target_addr_cmp(const void * a,const void * b)766 mptsas_target_addr_cmp(const void *a, const void *b)
767 {
768 const mptsas_target_addr_t *aap = a;
769 const mptsas_target_addr_t *bap = b;
770
771 if (aap->mta_wwn < bap->mta_wwn)
772 return (-1);
773 if (aap->mta_wwn > bap->mta_wwn)
774 return (1);
775 return ((int)bap->mta_phymask - (int)aap->mta_phymask);
776 }
777
778 static uint64_t
mptsas_tmp_target_hash(const void * tp)779 mptsas_tmp_target_hash(const void *tp)
780 {
781 return ((uint64_t)(uintptr_t)tp);
782 }
783
784 static int
mptsas_tmp_target_cmp(const void * a,const void * b)785 mptsas_tmp_target_cmp(const void *a, const void *b)
786 {
787 if (a > b)
788 return (1);
789 if (b < a)
790 return (-1);
791
792 return (0);
793 }
794
795 static void
mptsas_target_free(void * op)796 mptsas_target_free(void *op)
797 {
798 kmem_free(op, sizeof (mptsas_target_t));
799 }
800
801 static void
mptsas_smp_free(void * op)802 mptsas_smp_free(void *op)
803 {
804 kmem_free(op, sizeof (mptsas_smp_t));
805 }
806
807 static void
mptsas_destroy_hashes(mptsas_t * mpt)808 mptsas_destroy_hashes(mptsas_t *mpt)
809 {
810 mptsas_target_t *tp;
811 mptsas_smp_t *sp;
812
813 for (tp = refhash_first(mpt->m_targets); tp != NULL;
814 tp = refhash_next(mpt->m_targets, tp)) {
815 refhash_remove(mpt->m_targets, tp);
816 }
817 for (sp = refhash_first(mpt->m_smp_targets); sp != NULL;
818 sp = refhash_next(mpt->m_smp_targets, sp)) {
819 refhash_remove(mpt->m_smp_targets, sp);
820 }
821 refhash_destroy(mpt->m_tmp_targets);
822 refhash_destroy(mpt->m_targets);
823 refhash_destroy(mpt->m_smp_targets);
824 mpt->m_targets = NULL;
825 mpt->m_smp_targets = NULL;
826 }
827
828 static int
mptsas_iport_attach(dev_info_t * dip,ddi_attach_cmd_t cmd)829 mptsas_iport_attach(dev_info_t *dip, ddi_attach_cmd_t cmd)
830 {
831 dev_info_t *pdip;
832 mptsas_t *mpt;
833 scsi_hba_tran_t *hba_tran;
834 char *iport = NULL;
835 char phymask[MPTSAS_MAX_PHYS];
836 mptsas_phymask_t phy_mask = 0;
837 int dynamic_port = 0;
838 uint32_t page_address;
839 char initiator_wwnstr[MPTSAS_WWN_STRLEN];
840 int rval = DDI_FAILURE;
841 int i = 0;
842 uint8_t numphys = 0;
843 uint8_t phy_id;
844 uint8_t phy_port = 0;
845 uint16_t attached_devhdl = 0;
846 uint32_t dev_info;
847 uint64_t attached_sas_wwn;
848 uint16_t dev_hdl;
849 uint16_t pdev_hdl;
850 uint16_t bay_num, enclosure, io_flags;
851 char attached_wwnstr[MPTSAS_WWN_STRLEN];
852
853 /* CONSTCOND */
854 ASSERT(NO_COMPETING_THREADS);
855
856 switch (cmd) {
857 case DDI_ATTACH:
858 break;
859
860 case DDI_RESUME:
861 /*
862 * If this a scsi-iport node, nothing to do here.
863 */
864 return (DDI_SUCCESS);
865
866 default:
867 return (DDI_FAILURE);
868 }
869
870 pdip = ddi_get_parent(dip);
871
872 if ((hba_tran = ndi_flavorv_get(pdip, SCSA_FLAVOR_SCSI_DEVICE)) ==
873 NULL) {
874 cmn_err(CE_WARN, "Failed attach iport because fail to "
875 "get tran vector for the HBA node");
876 return (DDI_FAILURE);
877 }
878
879 mpt = TRAN2MPT(hba_tran);
880 ASSERT(mpt != NULL);
881 if (mpt == NULL)
882 return (DDI_FAILURE);
883
884 if ((hba_tran = ndi_flavorv_get(dip, SCSA_FLAVOR_SCSI_DEVICE)) ==
885 NULL) {
886 mptsas_log(mpt, CE_WARN, "Failed attach iport because fail to "
887 "get tran vector for the iport node");
888 return (DDI_FAILURE);
889 }
890
891 /*
892 * Overwrite parent's tran_hba_private to iport's tran vector
893 */
894 hba_tran->tran_hba_private = mpt;
895
896 ddi_report_dev(dip);
897
898 /*
899 * Get SAS address for initiator port according dev_handle
900 */
901 iport = ddi_get_name_addr(dip);
902 if (iport && strncmp(iport, "v0", 2) == 0) {
903 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip,
904 MPTSAS_VIRTUAL_PORT, 1) !=
905 DDI_PROP_SUCCESS) {
906 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip,
907 MPTSAS_VIRTUAL_PORT);
908 mptsas_log(mpt, CE_WARN, "mptsas virtual port "
909 "prop update failed");
910 return (DDI_FAILURE);
911 }
912 return (DDI_SUCCESS);
913 }
914
915 mutex_enter(&mpt->m_mutex);
916 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
917 bzero(phymask, sizeof (phymask));
918 (void) sprintf(phymask,
919 "%x", mpt->m_phy_info[i].phy_mask);
920 if (strcmp(phymask, iport) == 0) {
921 break;
922 }
923 }
924
925 if (i == MPTSAS_MAX_PHYS) {
926 mptsas_log(mpt, CE_WARN, "Failed attach port %s because port"
927 "seems not exist", iport);
928 mutex_exit(&mpt->m_mutex);
929 return (DDI_FAILURE);
930 }
931
932 phy_mask = mpt->m_phy_info[i].phy_mask;
933
934 if (mpt->m_phy_info[i].port_flags & AUTO_PORT_CONFIGURATION)
935 dynamic_port = 1;
936 else
937 dynamic_port = 0;
938
939 /*
940 * Update PHY info for smhba
941 */
942 if (mptsas_smhba_phy_init(mpt)) {
943 mutex_exit(&mpt->m_mutex);
944 mptsas_log(mpt, CE_WARN, "mptsas phy update "
945 "failed");
946 return (DDI_FAILURE);
947 }
948
949 mutex_exit(&mpt->m_mutex);
950
951 numphys = 0;
952 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
953 if ((phy_mask >> i) & 0x01) {
954 numphys++;
955 }
956 }
957
958 bzero(initiator_wwnstr, sizeof (initiator_wwnstr));
959 (void) sprintf(initiator_wwnstr, "w%016"PRIx64,
960 mpt->un.m_base_wwid);
961
962 if (ddi_prop_update_string(DDI_DEV_T_NONE, dip,
963 SCSI_ADDR_PROP_INITIATOR_PORT, initiator_wwnstr) !=
964 DDI_PROP_SUCCESS) {
965 (void) ddi_prop_remove(DDI_DEV_T_NONE,
966 dip, SCSI_ADDR_PROP_INITIATOR_PORT);
967 mptsas_log(mpt, CE_WARN, "mptsas Initiator port "
968 "prop update failed");
969 return (DDI_FAILURE);
970 }
971 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip,
972 MPTSAS_NUM_PHYS, numphys) !=
973 DDI_PROP_SUCCESS) {
974 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, MPTSAS_NUM_PHYS);
975 return (DDI_FAILURE);
976 }
977
978 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip,
979 "phymask", phy_mask) !=
980 DDI_PROP_SUCCESS) {
981 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "phymask");
982 mptsas_log(mpt, CE_WARN, "mptsas phy mask "
983 "prop update failed");
984 return (DDI_FAILURE);
985 }
986
987 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip,
988 "dynamic-port", dynamic_port) !=
989 DDI_PROP_SUCCESS) {
990 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "dynamic-port");
991 mptsas_log(mpt, CE_WARN, "mptsas dynamic port "
992 "prop update failed");
993 return (DDI_FAILURE);
994 }
995 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip,
996 MPTSAS_VIRTUAL_PORT, 0) !=
997 DDI_PROP_SUCCESS) {
998 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip,
999 MPTSAS_VIRTUAL_PORT);
1000 mptsas_log(mpt, CE_WARN, "mptsas virtual port "
1001 "prop update failed");
1002 return (DDI_FAILURE);
1003 }
1004 mptsas_smhba_set_all_phy_props(mpt, dip, numphys, phy_mask,
1005 &attached_devhdl);
1006
1007 mutex_enter(&mpt->m_mutex);
1008 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
1009 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | (uint32_t)attached_devhdl;
1010 rval = mptsas_get_sas_device_page0(mpt, page_address, &dev_hdl,
1011 &attached_sas_wwn, &dev_info, &phy_port, &phy_id,
1012 &pdev_hdl, &bay_num, &enclosure, &io_flags);
1013 if (rval != DDI_SUCCESS) {
1014 mptsas_log(mpt, CE_WARN,
1015 "Failed to get device page0 for handle:%d",
1016 attached_devhdl);
1017 mutex_exit(&mpt->m_mutex);
1018 return (DDI_FAILURE);
1019 }
1020
1021 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
1022 bzero(phymask, sizeof (phymask));
1023 (void) sprintf(phymask, "%x", mpt->m_phy_info[i].phy_mask);
1024 if (strcmp(phymask, iport) == 0) {
1025 (void) sprintf(&mpt->m_phy_info[i].smhba_info.path[0],
1026 "%x",
1027 mpt->m_phy_info[i].phy_mask);
1028 }
1029 }
1030 mutex_exit(&mpt->m_mutex);
1031
1032 bzero(attached_wwnstr, sizeof (attached_wwnstr));
1033 (void) sprintf(attached_wwnstr, "w%016"PRIx64,
1034 attached_sas_wwn);
1035 if (ddi_prop_update_string(DDI_DEV_T_NONE, dip,
1036 SCSI_ADDR_PROP_ATTACHED_PORT, attached_wwnstr) !=
1037 DDI_PROP_SUCCESS) {
1038 (void) ddi_prop_remove(DDI_DEV_T_NONE,
1039 dip, SCSI_ADDR_PROP_ATTACHED_PORT);
1040 return (DDI_FAILURE);
1041 }
1042
1043 /* Create kstats for each phy on this iport */
1044
1045 mptsas_create_phy_stats(mpt, iport, dip);
1046
1047 /*
1048 * register sas hba iport with mdi (MPxIO/vhci)
1049 */
1050 if (mdi_phci_register(MDI_HCI_CLASS_SCSI,
1051 dip, 0) == MDI_SUCCESS) {
1052 mpt->m_mpxio_enable = TRUE;
1053 }
1054 return (DDI_SUCCESS);
1055 }
1056
1057 /*
1058 * Notes:
1059 * Set up all device state and allocate data structures,
1060 * mutexes, condition variables, etc. for device operation.
1061 * Add interrupts needed.
1062 * Return DDI_SUCCESS if device is ready, else return DDI_FAILURE.
1063 */
1064 static int
mptsas_attach(dev_info_t * dip,ddi_attach_cmd_t cmd)1065 mptsas_attach(dev_info_t *dip, ddi_attach_cmd_t cmd)
1066 {
1067 mptsas_t *mpt = NULL;
1068 int instance, i, j;
1069 int doneq_thread_num;
1070 char intr_added = 0;
1071 char map_setup = 0;
1072 char config_setup = 0;
1073 char hba_attach_setup = 0;
1074 char smp_attach_setup = 0;
1075 char enc_attach_setup = 0;
1076 char mutex_init_done = 0;
1077 char event_taskq_create = 0;
1078 char dr_taskq_create = 0;
1079 char doneq_thread_create = 0;
1080 char added_watchdog = 0;
1081 scsi_hba_tran_t *hba_tran;
1082 uint_t mem_bar = MEM_SPACE;
1083 int rval = DDI_FAILURE;
1084
1085 /* CONSTCOND */
1086 ASSERT(NO_COMPETING_THREADS);
1087
1088 if (scsi_hba_iport_unit_address(dip)) {
1089 return (mptsas_iport_attach(dip, cmd));
1090 }
1091
1092 switch (cmd) {
1093 case DDI_ATTACH:
1094 break;
1095
1096 case DDI_RESUME:
1097 if ((hba_tran = ddi_get_driver_private(dip)) == NULL)
1098 return (DDI_FAILURE);
1099
1100 mpt = TRAN2MPT(hba_tran);
1101
1102 if (!mpt) {
1103 return (DDI_FAILURE);
1104 }
1105
1106 /*
1107 * Reset hardware and softc to "no outstanding commands"
1108 * Note that a check condition can result on first command
1109 * to a target.
1110 */
1111 mutex_enter(&mpt->m_mutex);
1112
1113 /*
1114 * raise power.
1115 */
1116 if (mpt->m_options & MPTSAS_OPT_PM) {
1117 mutex_exit(&mpt->m_mutex);
1118 (void) pm_busy_component(dip, 0);
1119 rval = pm_power_has_changed(dip, 0, PM_LEVEL_D0);
1120 if (rval == DDI_SUCCESS) {
1121 mutex_enter(&mpt->m_mutex);
1122 } else {
1123 /*
1124 * The pm_raise_power() call above failed,
1125 * and that can only occur if we were unable
1126 * to reset the hardware. This is probably
1127 * due to unhealty hardware, and because
1128 * important filesystems(such as the root
1129 * filesystem) could be on the attached disks,
1130 * it would not be a good idea to continue,
1131 * as we won't be entirely certain we are
1132 * writing correct data. So we panic() here
1133 * to not only prevent possible data corruption,
1134 * but to give developers or end users a hope
1135 * of identifying and correcting any problems.
1136 */
1137 fm_panic("mptsas could not reset hardware "
1138 "during resume");
1139 }
1140 }
1141
1142 mpt->m_suspended = 0;
1143
1144 /*
1145 * Reinitialize ioc
1146 */
1147 mpt->m_softstate |= MPTSAS_SS_MSG_UNIT_RESET;
1148 if (mptsas_init_chip(mpt, FALSE) == DDI_FAILURE) {
1149 mutex_exit(&mpt->m_mutex);
1150 if (mpt->m_options & MPTSAS_OPT_PM) {
1151 (void) pm_idle_component(dip, 0);
1152 }
1153 fm_panic("mptsas init chip fail during resume");
1154 }
1155 /*
1156 * mptsas_update_driver_data needs interrupts so enable them
1157 * first.
1158 */
1159 MPTSAS_ENABLE_INTR(mpt);
1160 mptsas_update_driver_data(mpt);
1161
1162 /* start requests, if possible */
1163 mptsas_restart_hba(mpt);
1164
1165 mutex_exit(&mpt->m_mutex);
1166
1167 /*
1168 * Restart watch thread
1169 */
1170 mutex_enter(&mptsas_global_mutex);
1171 if (mptsas_timeout_id == 0) {
1172 mptsas_timeout_id = timeout(mptsas_watch, NULL,
1173 mptsas_tick);
1174 mptsas_timeouts_enabled = 1;
1175 }
1176 mutex_exit(&mptsas_global_mutex);
1177
1178 /* report idle status to pm framework */
1179 if (mpt->m_options & MPTSAS_OPT_PM) {
1180 (void) pm_idle_component(dip, 0);
1181 }
1182
1183 return (DDI_SUCCESS);
1184
1185 default:
1186 return (DDI_FAILURE);
1187
1188 }
1189
1190 instance = ddi_get_instance(dip);
1191
1192 /*
1193 * Allocate softc information.
1194 */
1195 if (ddi_soft_state_zalloc(mptsas_state, instance) != DDI_SUCCESS) {
1196 mptsas_log(NULL, CE_WARN,
1197 "mptsas%d: cannot allocate soft state", instance);
1198 goto fail;
1199 }
1200
1201 mpt = ddi_get_soft_state(mptsas_state, instance);
1202
1203 if (mpt == NULL) {
1204 mptsas_log(NULL, CE_WARN,
1205 "mptsas%d: cannot get soft state", instance);
1206 goto fail;
1207 }
1208
1209 /* Indicate that we are 'sizeof (scsi_*(9S))' clean. */
1210 scsi_size_clean(dip);
1211
1212 mpt->m_dip = dip;
1213 mpt->m_instance = instance;
1214
1215 /* Make a per-instance copy of the structures */
1216 mpt->m_io_dma_attr = mptsas_dma_attrs64;
1217 if (mptsas_use_64bit_msgaddr) {
1218 mpt->m_msg_dma_attr = mptsas_dma_attrs64;
1219 } else {
1220 mpt->m_msg_dma_attr = mptsas_dma_attrs;
1221 }
1222 mpt->m_reg_acc_attr = mptsas_dev_attr;
1223 mpt->m_dev_acc_attr = mptsas_dev_attr;
1224
1225 /*
1226 * Size of individual request sense buffer
1227 */
1228 mpt->m_req_sense_size = EXTCMDS_STATUS_SIZE;
1229
1230 /*
1231 * Initialize FMA
1232 */
1233 mpt->m_fm_capabilities = ddi_getprop(DDI_DEV_T_ANY, mpt->m_dip,
1234 DDI_PROP_CANSLEEP | DDI_PROP_DONTPASS, "fm-capable",
1235 DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE |
1236 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE);
1237
1238 mptsas_fm_init(mpt);
1239
1240 if (mptsas_alloc_handshake_msg(mpt,
1241 sizeof (Mpi2SCSITaskManagementRequest_t)) == DDI_FAILURE) {
1242 mptsas_log(mpt, CE_WARN, "cannot initialize handshake msg.");
1243 goto fail;
1244 }
1245
1246 /*
1247 * Setup configuration space
1248 */
1249 if (mptsas_config_space_init(mpt) == FALSE) {
1250 mptsas_log(mpt, CE_WARN, "mptsas_config_space_init failed");
1251 goto fail;
1252 }
1253 config_setup++;
1254
1255 if (ddi_regs_map_setup(dip, mem_bar, (caddr_t *)&mpt->m_reg,
1256 0, 0, &mpt->m_reg_acc_attr, &mpt->m_datap) != DDI_SUCCESS) {
1257 mptsas_log(mpt, CE_WARN, "map setup failed");
1258 goto fail;
1259 }
1260 map_setup++;
1261
1262 /*
1263 * A taskq is created for dealing with the event handler
1264 */
1265 if ((mpt->m_event_taskq = ddi_taskq_create(dip, "mptsas_event_taskq",
1266 1, TASKQ_DEFAULTPRI, 0)) == NULL) {
1267 mptsas_log(mpt, CE_NOTE, "ddi_taskq_create failed");
1268 goto fail;
1269 }
1270 event_taskq_create++;
1271
1272 /*
1273 * A taskq is created for dealing with dr events
1274 */
1275 if ((mpt->m_dr_taskq = ddi_taskq_create(dip,
1276 "mptsas_dr_taskq",
1277 1, TASKQ_DEFAULTPRI, 0)) == NULL) {
1278 mptsas_log(mpt, CE_NOTE, "ddi_taskq_create for discovery "
1279 "failed");
1280 goto fail;
1281 }
1282 dr_taskq_create++;
1283
1284 mpt->m_doneq_thread_threshold = ddi_prop_get_int(DDI_DEV_T_ANY, dip,
1285 0, "mptsas_doneq_thread_threshold_prop", 10);
1286 mpt->m_doneq_length_threshold = ddi_prop_get_int(DDI_DEV_T_ANY, dip,
1287 0, "mptsas_doneq_length_threshold_prop", 8);
1288 mpt->m_doneq_thread_n = ddi_prop_get_int(DDI_DEV_T_ANY, dip,
1289 0, "mptsas_doneq_thread_n_prop", 8);
1290
1291 if (mpt->m_doneq_thread_n) {
1292 cv_init(&mpt->m_doneq_thread_cv, NULL, CV_DRIVER, NULL);
1293 mutex_init(&mpt->m_doneq_mutex, NULL, MUTEX_DRIVER, NULL);
1294
1295 mutex_enter(&mpt->m_doneq_mutex);
1296 mpt->m_doneq_thread_id =
1297 kmem_zalloc(sizeof (mptsas_doneq_thread_list_t)
1298 * mpt->m_doneq_thread_n, KM_SLEEP);
1299
1300 for (j = 0; j < mpt->m_doneq_thread_n; j++) {
1301 cv_init(&mpt->m_doneq_thread_id[j].cv, NULL,
1302 CV_DRIVER, NULL);
1303 mutex_init(&mpt->m_doneq_thread_id[j].mutex, NULL,
1304 MUTEX_DRIVER, NULL);
1305 mutex_enter(&mpt->m_doneq_thread_id[j].mutex);
1306 mpt->m_doneq_thread_id[j].flag |=
1307 MPTSAS_DONEQ_THREAD_ACTIVE;
1308 mpt->m_doneq_thread_id[j].arg.mpt = mpt;
1309 mpt->m_doneq_thread_id[j].arg.t = j;
1310 mpt->m_doneq_thread_id[j].threadp =
1311 thread_create(NULL, 0, mptsas_doneq_thread,
1312 &mpt->m_doneq_thread_id[j].arg,
1313 0, &p0, TS_RUN, minclsyspri);
1314 mpt->m_doneq_thread_id[j].donetail =
1315 &mpt->m_doneq_thread_id[j].doneq;
1316 mutex_exit(&mpt->m_doneq_thread_id[j].mutex);
1317 }
1318 mutex_exit(&mpt->m_doneq_mutex);
1319 doneq_thread_create++;
1320 }
1321
1322 /*
1323 * Disable hardware interrupt since we're not ready to
1324 * handle it yet.
1325 */
1326 MPTSAS_DISABLE_INTR(mpt);
1327 if (mptsas_register_intrs(mpt) == FALSE)
1328 goto fail;
1329 intr_added++;
1330
1331 /* Initialize mutex used in interrupt handler */
1332 mutex_init(&mpt->m_mutex, NULL, MUTEX_DRIVER,
1333 DDI_INTR_PRI(mpt->m_intr_pri));
1334 mutex_init(&mpt->m_passthru_mutex, NULL, MUTEX_DRIVER, NULL);
1335 mutex_init(&mpt->m_tx_waitq_mutex, NULL, MUTEX_DRIVER,
1336 DDI_INTR_PRI(mpt->m_intr_pri));
1337 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
1338 mutex_init(&mpt->m_phy_info[i].smhba_info.phy_mutex,
1339 NULL, MUTEX_DRIVER,
1340 DDI_INTR_PRI(mpt->m_intr_pri));
1341 }
1342
1343 cv_init(&mpt->m_cv, NULL, CV_DRIVER, NULL);
1344 cv_init(&mpt->m_passthru_cv, NULL, CV_DRIVER, NULL);
1345 cv_init(&mpt->m_fw_cv, NULL, CV_DRIVER, NULL);
1346 cv_init(&mpt->m_config_cv, NULL, CV_DRIVER, NULL);
1347 cv_init(&mpt->m_fw_diag_cv, NULL, CV_DRIVER, NULL);
1348 cv_init(&mpt->m_extreq_sense_refcount_cv, NULL, CV_DRIVER, NULL);
1349 mutex_init_done++;
1350
1351 mutex_enter(&mpt->m_mutex);
1352 /*
1353 * Initialize power management component
1354 */
1355 if (mpt->m_options & MPTSAS_OPT_PM) {
1356 if (mptsas_init_pm(mpt)) {
1357 mutex_exit(&mpt->m_mutex);
1358 mptsas_log(mpt, CE_WARN, "mptsas pm initialization "
1359 "failed");
1360 goto fail;
1361 }
1362 }
1363
1364 /*
1365 * Initialize chip using Message Unit Reset, if allowed
1366 */
1367 mpt->m_softstate |= MPTSAS_SS_MSG_UNIT_RESET;
1368 if (mptsas_init_chip(mpt, TRUE) == DDI_FAILURE) {
1369 mutex_exit(&mpt->m_mutex);
1370 mptsas_log(mpt, CE_WARN, "mptsas chip initialization failed");
1371 goto fail;
1372 }
1373
1374 mpt->m_targets = refhash_create(MPTSAS_TARGET_BUCKET_COUNT,
1375 mptsas_target_addr_hash, mptsas_target_addr_cmp,
1376 mptsas_target_free, sizeof (mptsas_target_t),
1377 offsetof(mptsas_target_t, m_link),
1378 offsetof(mptsas_target_t, m_addr), KM_SLEEP);
1379
1380 /*
1381 * The refhash for temporary targets uses the address of the target
1382 * struct itself as tag, so the tag offset is 0. See the implementation
1383 * of mptsas_tmp_target_hash() and mptsas_tmp_target_cmp().
1384 */
1385 mpt->m_tmp_targets = refhash_create(MPTSAS_TMP_TARGET_BUCKET_COUNT,
1386 mptsas_tmp_target_hash, mptsas_tmp_target_cmp,
1387 mptsas_target_free, sizeof (mptsas_target_t),
1388 offsetof(mptsas_target_t, m_link), 0, KM_SLEEP);
1389
1390 /*
1391 * Fill in the phy_info structure and get the base WWID
1392 */
1393 if (mptsas_get_manufacture_page5(mpt) == DDI_FAILURE) {
1394 mptsas_log(mpt, CE_WARN,
1395 "mptsas_get_manufacture_page5 failed!");
1396 goto fail;
1397 }
1398
1399 if (mptsas_get_sas_io_unit_page_hndshk(mpt)) {
1400 mptsas_log(mpt, CE_WARN,
1401 "mptsas_get_sas_io_unit_page_hndshk failed!");
1402 goto fail;
1403 }
1404
1405 if (mptsas_get_manufacture_page0(mpt) == DDI_FAILURE) {
1406 mptsas_log(mpt, CE_WARN,
1407 "mptsas_get_manufacture_page0 failed!");
1408 goto fail;
1409 }
1410
1411 mutex_exit(&mpt->m_mutex);
1412
1413 /*
1414 * Register the iport for multiple port HBA
1415 */
1416 mptsas_iport_register(mpt);
1417
1418 /*
1419 * initialize SCSI HBA transport structure
1420 */
1421 if (mptsas_hba_setup(mpt) == FALSE)
1422 goto fail;
1423 hba_attach_setup++;
1424
1425 if (mptsas_smp_setup(mpt) == FALSE)
1426 goto fail;
1427 smp_attach_setup++;
1428
1429 if (mptsas_enc_setup(mpt) == FALSE)
1430 goto fail;
1431 enc_attach_setup++;
1432
1433 if (mptsas_cache_create(mpt) == FALSE)
1434 goto fail;
1435
1436 mpt->m_scsi_reset_delay = ddi_prop_get_int(DDI_DEV_T_ANY,
1437 dip, 0, "scsi-reset-delay", SCSI_DEFAULT_RESET_DELAY);
1438 if (mpt->m_scsi_reset_delay == 0) {
1439 mptsas_log(mpt, CE_NOTE,
1440 "scsi_reset_delay of 0 is not recommended,"
1441 " resetting to SCSI_DEFAULT_RESET_DELAY\n");
1442 mpt->m_scsi_reset_delay = SCSI_DEFAULT_RESET_DELAY;
1443 }
1444
1445 /*
1446 * Initialize the wait and done FIFO queue
1447 */
1448 mpt->m_donetail = &mpt->m_doneq;
1449 mpt->m_waitqtail = &mpt->m_waitq;
1450 mpt->m_tx_waitqtail = &mpt->m_tx_waitq;
1451 mpt->m_tx_draining = 0;
1452
1453 /*
1454 * ioc cmd queue initialize
1455 */
1456 mpt->m_ioc_event_cmdtail = &mpt->m_ioc_event_cmdq;
1457 mpt->m_dev_handle = 0xFFFF;
1458
1459 MPTSAS_ENABLE_INTR(mpt);
1460
1461 /*
1462 * enable event notification
1463 */
1464 mutex_enter(&mpt->m_mutex);
1465 if (mptsas_ioc_enable_event_notification(mpt)) {
1466 mutex_exit(&mpt->m_mutex);
1467 goto fail;
1468 }
1469 mutex_exit(&mpt->m_mutex);
1470
1471 /*
1472 * used for mptsas_watch
1473 */
1474 mptsas_list_add(mpt);
1475
1476 mutex_enter(&mptsas_global_mutex);
1477 if (mptsas_timeouts_enabled == 0) {
1478 mptsas_scsi_watchdog_tick = ddi_prop_get_int(DDI_DEV_T_ANY,
1479 dip, 0, "scsi-watchdog-tick", DEFAULT_WD_TICK);
1480
1481 mptsas_tick = mptsas_scsi_watchdog_tick *
1482 drv_usectohz((clock_t)1000000);
1483
1484 mptsas_timeout_id = timeout(mptsas_watch, NULL, mptsas_tick);
1485 mptsas_timeouts_enabled = 1;
1486 }
1487 mutex_exit(&mptsas_global_mutex);
1488 added_watchdog++;
1489
1490 /*
1491 * Initialize PHY info for smhba.
1492 * This requires watchdog to be enabled otherwise if interrupts
1493 * don't work the system will hang.
1494 */
1495 if (mptsas_smhba_setup(mpt)) {
1496 mptsas_log(mpt, CE_WARN, "mptsas phy initialization "
1497 "failed");
1498 goto fail;
1499 }
1500
1501 /* Check all dma handles allocated in attach */
1502 if ((mptsas_check_dma_handle(mpt->m_dma_req_frame_hdl)
1503 != DDI_SUCCESS) ||
1504 (mptsas_check_dma_handle(mpt->m_dma_req_sense_hdl)
1505 != DDI_SUCCESS) ||
1506 (mptsas_check_dma_handle(mpt->m_dma_reply_frame_hdl)
1507 != DDI_SUCCESS) ||
1508 (mptsas_check_dma_handle(mpt->m_dma_free_queue_hdl)
1509 != DDI_SUCCESS) ||
1510 (mptsas_check_dma_handle(mpt->m_dma_post_queue_hdl)
1511 != DDI_SUCCESS) ||
1512 (mptsas_check_dma_handle(mpt->m_hshk_dma_hdl)
1513 != DDI_SUCCESS)) {
1514 goto fail;
1515 }
1516
1517 /* Check all acc handles allocated in attach */
1518 if ((mptsas_check_acc_handle(mpt->m_datap) != DDI_SUCCESS) ||
1519 (mptsas_check_acc_handle(mpt->m_acc_req_frame_hdl)
1520 != DDI_SUCCESS) ||
1521 (mptsas_check_acc_handle(mpt->m_acc_req_sense_hdl)
1522 != DDI_SUCCESS) ||
1523 (mptsas_check_acc_handle(mpt->m_acc_reply_frame_hdl)
1524 != DDI_SUCCESS) ||
1525 (mptsas_check_acc_handle(mpt->m_acc_free_queue_hdl)
1526 != DDI_SUCCESS) ||
1527 (mptsas_check_acc_handle(mpt->m_acc_post_queue_hdl)
1528 != DDI_SUCCESS) ||
1529 (mptsas_check_acc_handle(mpt->m_hshk_acc_hdl)
1530 != DDI_SUCCESS) ||
1531 (mptsas_check_acc_handle(mpt->m_config_handle)
1532 != DDI_SUCCESS)) {
1533 goto fail;
1534 }
1535
1536 /*
1537 * After this point, we are not going to fail the attach.
1538 */
1539
1540 /* Print message of HBA present */
1541 ddi_report_dev(dip);
1542
1543 /* report idle status to pm framework */
1544 if (mpt->m_options & MPTSAS_OPT_PM) {
1545 (void) pm_idle_component(dip, 0);
1546 }
1547
1548 return (DDI_SUCCESS);
1549
1550 fail:
1551 mptsas_log(mpt, CE_WARN, "attach failed");
1552 mptsas_fm_ereport(mpt, DDI_FM_DEVICE_NO_RESPONSE);
1553 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_LOST);
1554 if (mpt) {
1555 /* deallocate in reverse order */
1556 if (added_watchdog) {
1557 mptsas_list_del(mpt);
1558 mutex_enter(&mptsas_global_mutex);
1559
1560 if (mptsas_timeout_id && (mptsas_head == NULL)) {
1561 timeout_id_t tid = mptsas_timeout_id;
1562 mptsas_timeouts_enabled = 0;
1563 mptsas_timeout_id = 0;
1564 mutex_exit(&mptsas_global_mutex);
1565 (void) untimeout(tid);
1566 mutex_enter(&mptsas_global_mutex);
1567 }
1568 mutex_exit(&mptsas_global_mutex);
1569 }
1570
1571 mptsas_cache_destroy(mpt);
1572
1573 if (smp_attach_setup) {
1574 mptsas_smp_teardown(mpt);
1575 }
1576 if (enc_attach_setup) {
1577 mptsas_enc_teardown(mpt);
1578 }
1579 if (hba_attach_setup) {
1580 mptsas_hba_teardown(mpt);
1581 }
1582
1583 if (mpt->m_tmp_targets)
1584 refhash_destroy(mpt->m_tmp_targets);
1585 if (mpt->m_targets)
1586 refhash_destroy(mpt->m_targets);
1587 if (mpt->m_smp_targets)
1588 refhash_destroy(mpt->m_smp_targets);
1589
1590 if (mpt->m_active) {
1591 mptsas_free_active_slots(mpt);
1592 }
1593 if (intr_added) {
1594 mptsas_unregister_intrs(mpt);
1595 }
1596
1597 if (doneq_thread_create) {
1598 mutex_enter(&mpt->m_doneq_mutex);
1599 doneq_thread_num = mpt->m_doneq_thread_n;
1600 for (j = 0; j < mpt->m_doneq_thread_n; j++) {
1601 mutex_enter(&mpt->m_doneq_thread_id[j].mutex);
1602 mpt->m_doneq_thread_id[j].flag &=
1603 (~MPTSAS_DONEQ_THREAD_ACTIVE);
1604 cv_signal(&mpt->m_doneq_thread_id[j].cv);
1605 mutex_exit(&mpt->m_doneq_thread_id[j].mutex);
1606 }
1607 while (mpt->m_doneq_thread_n) {
1608 cv_wait(&mpt->m_doneq_thread_cv,
1609 &mpt->m_doneq_mutex);
1610 }
1611 for (j = 0; j < doneq_thread_num; j++) {
1612 cv_destroy(&mpt->m_doneq_thread_id[j].cv);
1613 mutex_destroy(&mpt->m_doneq_thread_id[j].mutex);
1614 }
1615 kmem_free(mpt->m_doneq_thread_id,
1616 sizeof (mptsas_doneq_thread_list_t)
1617 * doneq_thread_num);
1618 mutex_exit(&mpt->m_doneq_mutex);
1619 cv_destroy(&mpt->m_doneq_thread_cv);
1620 mutex_destroy(&mpt->m_doneq_mutex);
1621 }
1622 if (event_taskq_create) {
1623 ddi_taskq_destroy(mpt->m_event_taskq);
1624 }
1625 if (dr_taskq_create) {
1626 ddi_taskq_destroy(mpt->m_dr_taskq);
1627 }
1628 if (mutex_init_done) {
1629 mutex_destroy(&mpt->m_tx_waitq_mutex);
1630 mutex_destroy(&mpt->m_passthru_mutex);
1631 mutex_destroy(&mpt->m_mutex);
1632 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
1633 mutex_destroy(
1634 &mpt->m_phy_info[i].smhba_info.phy_mutex);
1635 }
1636 cv_destroy(&mpt->m_cv);
1637 cv_destroy(&mpt->m_passthru_cv);
1638 cv_destroy(&mpt->m_fw_cv);
1639 cv_destroy(&mpt->m_config_cv);
1640 cv_destroy(&mpt->m_fw_diag_cv);
1641 cv_destroy(&mpt->m_extreq_sense_refcount_cv);
1642 }
1643
1644 if (map_setup) {
1645 mptsas_cfg_fini(mpt);
1646 }
1647 if (config_setup) {
1648 mptsas_config_space_fini(mpt);
1649 }
1650 mptsas_free_handshake_msg(mpt);
1651 mptsas_hba_fini(mpt);
1652
1653 mptsas_fm_fini(mpt);
1654 ddi_soft_state_free(mptsas_state, instance);
1655 ddi_prop_remove_all(dip);
1656 }
1657 return (DDI_FAILURE);
1658 }
1659
1660 static int
mptsas_suspend(dev_info_t * devi)1661 mptsas_suspend(dev_info_t *devi)
1662 {
1663 mptsas_t *mpt, *g;
1664 scsi_hba_tran_t *tran;
1665
1666 if (scsi_hba_iport_unit_address(devi)) {
1667 return (DDI_SUCCESS);
1668 }
1669
1670 if ((tran = ddi_get_driver_private(devi)) == NULL)
1671 return (DDI_SUCCESS);
1672
1673 mpt = TRAN2MPT(tran);
1674 if (!mpt) {
1675 return (DDI_SUCCESS);
1676 }
1677
1678 mutex_enter(&mpt->m_mutex);
1679
1680 if (mpt->m_suspended++) {
1681 mutex_exit(&mpt->m_mutex);
1682 return (DDI_SUCCESS);
1683 }
1684
1685 /*
1686 * Cancel timeout threads for this mpt
1687 */
1688 if (mpt->m_quiesce_timeid) {
1689 timeout_id_t tid = mpt->m_quiesce_timeid;
1690 mpt->m_quiesce_timeid = 0;
1691 mutex_exit(&mpt->m_mutex);
1692 (void) untimeout(tid);
1693 mutex_enter(&mpt->m_mutex);
1694 }
1695
1696 if (mpt->m_restart_cmd_timeid) {
1697 timeout_id_t tid = mpt->m_restart_cmd_timeid;
1698 mpt->m_restart_cmd_timeid = 0;
1699 mutex_exit(&mpt->m_mutex);
1700 (void) untimeout(tid);
1701 mutex_enter(&mpt->m_mutex);
1702 }
1703
1704 mutex_exit(&mpt->m_mutex);
1705
1706 (void) pm_idle_component(mpt->m_dip, 0);
1707
1708 /*
1709 * Cancel watch threads if all mpts suspended
1710 */
1711 rw_enter(&mptsas_global_rwlock, RW_WRITER);
1712 for (g = mptsas_head; g != NULL; g = g->m_next) {
1713 if (!g->m_suspended)
1714 break;
1715 }
1716 rw_exit(&mptsas_global_rwlock);
1717
1718 mutex_enter(&mptsas_global_mutex);
1719 if (g == NULL) {
1720 timeout_id_t tid;
1721
1722 mptsas_timeouts_enabled = 0;
1723 if (mptsas_timeout_id) {
1724 tid = mptsas_timeout_id;
1725 mptsas_timeout_id = 0;
1726 mutex_exit(&mptsas_global_mutex);
1727 (void) untimeout(tid);
1728 mutex_enter(&mptsas_global_mutex);
1729 }
1730 if (mptsas_reset_watch) {
1731 tid = mptsas_reset_watch;
1732 mptsas_reset_watch = 0;
1733 mutex_exit(&mptsas_global_mutex);
1734 (void) untimeout(tid);
1735 mutex_enter(&mptsas_global_mutex);
1736 }
1737 }
1738 mutex_exit(&mptsas_global_mutex);
1739
1740 mutex_enter(&mpt->m_mutex);
1741
1742 /*
1743 * If this mpt is not in full power(PM_LEVEL_D0), just return.
1744 */
1745 if ((mpt->m_options & MPTSAS_OPT_PM) &&
1746 (mpt->m_power_level != PM_LEVEL_D0)) {
1747 mutex_exit(&mpt->m_mutex);
1748 return (DDI_SUCCESS);
1749 }
1750
1751 /* Disable HBA interrupts in hardware */
1752 MPTSAS_DISABLE_INTR(mpt);
1753 /*
1754 * Send RAID action system shutdown to sync IR
1755 */
1756 mptsas_raid_action_system_shutdown(mpt);
1757
1758 mutex_exit(&mpt->m_mutex);
1759
1760 /* drain the taskq */
1761 ddi_taskq_wait(mpt->m_event_taskq);
1762 ddi_taskq_wait(mpt->m_dr_taskq);
1763
1764 return (DDI_SUCCESS);
1765 }
1766
1767 #ifdef __sparc
1768 /*ARGSUSED*/
1769 static int
mptsas_reset(dev_info_t * devi,ddi_reset_cmd_t cmd)1770 mptsas_reset(dev_info_t *devi, ddi_reset_cmd_t cmd)
1771 {
1772 mptsas_t *mpt;
1773 scsi_hba_tran_t *tran;
1774
1775 /*
1776 * If this call is for iport, just return.
1777 */
1778 if (scsi_hba_iport_unit_address(devi))
1779 return (DDI_SUCCESS);
1780
1781 if ((tran = ddi_get_driver_private(devi)) == NULL)
1782 return (DDI_SUCCESS);
1783
1784 if ((mpt = TRAN2MPT(tran)) == NULL)
1785 return (DDI_SUCCESS);
1786
1787 /*
1788 * Send RAID action system shutdown to sync IR. Disable HBA
1789 * interrupts in hardware first.
1790 */
1791 MPTSAS_DISABLE_INTR(mpt);
1792 mptsas_raid_action_system_shutdown(mpt);
1793
1794 return (DDI_SUCCESS);
1795 }
1796 #else /* __sparc */
1797 /*
1798 * quiesce(9E) entry point.
1799 *
1800 * This function is called when the system is single-threaded at high
1801 * PIL with preemption disabled. Therefore, this function must not be
1802 * blocked.
1803 *
1804 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure.
1805 * DDI_FAILURE indicates an error condition and should almost never happen.
1806 */
1807 static int
mptsas_quiesce(dev_info_t * devi)1808 mptsas_quiesce(dev_info_t *devi)
1809 {
1810 mptsas_t *mpt;
1811 scsi_hba_tran_t *tran;
1812
1813 /*
1814 * If this call is for iport, just return.
1815 */
1816 if (scsi_hba_iport_unit_address(devi))
1817 return (DDI_SUCCESS);
1818
1819 if ((tran = ddi_get_driver_private(devi)) == NULL)
1820 return (DDI_SUCCESS);
1821
1822 if ((mpt = TRAN2MPT(tran)) == NULL)
1823 return (DDI_SUCCESS);
1824
1825 /* Disable HBA interrupts in hardware */
1826 MPTSAS_DISABLE_INTR(mpt);
1827 /* Send RAID action system shutdonw to sync IR */
1828 mptsas_raid_action_system_shutdown(mpt);
1829
1830 return (DDI_SUCCESS);
1831 }
1832 #endif /* __sparc */
1833
1834 /*
1835 * detach(9E). Remove all device allocations and system resources;
1836 * disable device interrupts.
1837 * Return DDI_SUCCESS if done; DDI_FAILURE if there's a problem.
1838 */
1839 static int
mptsas_detach(dev_info_t * devi,ddi_detach_cmd_t cmd)1840 mptsas_detach(dev_info_t *devi, ddi_detach_cmd_t cmd)
1841 {
1842 /* CONSTCOND */
1843 ASSERT(NO_COMPETING_THREADS);
1844 NDBG0(("mptsas_detach: dip=0x%p cmd=0x%p", (void *)devi, (void *)cmd));
1845
1846 switch (cmd) {
1847 case DDI_DETACH:
1848 return (mptsas_do_detach(devi));
1849
1850 case DDI_SUSPEND:
1851 return (mptsas_suspend(devi));
1852
1853 default:
1854 return (DDI_FAILURE);
1855 }
1856 /* NOTREACHED */
1857 }
1858
1859 static int
mptsas_do_detach(dev_info_t * dip)1860 mptsas_do_detach(dev_info_t *dip)
1861 {
1862 mptsas_t *mpt;
1863 scsi_hba_tran_t *tran;
1864 int circ = 0;
1865 int circ1 = 0;
1866 mdi_pathinfo_t *pip = NULL;
1867 int i;
1868 int doneq_thread_num = 0;
1869
1870 NDBG0(("mptsas_do_detach: dip=0x%p", (void *)dip));
1871
1872 if ((tran = ndi_flavorv_get(dip, SCSA_FLAVOR_SCSI_DEVICE)) == NULL)
1873 return (DDI_FAILURE);
1874
1875 mpt = TRAN2MPT(tran);
1876 if (!mpt) {
1877 return (DDI_FAILURE);
1878 }
1879 /*
1880 * Still have pathinfo child, should not detach mpt driver
1881 */
1882 if (scsi_hba_iport_unit_address(dip)) {
1883 if (mpt->m_mpxio_enable) {
1884 /*
1885 * MPxIO enabled for the iport
1886 */
1887 ndi_devi_enter(scsi_vhci_dip, &circ1);
1888 ndi_devi_enter(dip, &circ);
1889 while ((pip = mdi_get_next_client_path(dip, NULL)) !=
1890 NULL) {
1891 if (mdi_pi_free(pip, 0) == MDI_SUCCESS) {
1892 continue;
1893 }
1894 ndi_devi_exit(dip, circ);
1895 ndi_devi_exit(scsi_vhci_dip, circ1);
1896 NDBG12(("detach failed because of "
1897 "outstanding path info"));
1898 return (DDI_FAILURE);
1899 }
1900 ndi_devi_exit(dip, circ);
1901 ndi_devi_exit(scsi_vhci_dip, circ1);
1902 (void) mdi_phci_unregister(dip, 0);
1903 }
1904
1905 ddi_prop_remove_all(dip);
1906
1907 return (DDI_SUCCESS);
1908 }
1909
1910 /* Make sure power level is D0 before accessing registers */
1911 if (mpt->m_options & MPTSAS_OPT_PM) {
1912 (void) pm_busy_component(dip, 0);
1913 if (mpt->m_power_level != PM_LEVEL_D0) {
1914 if (pm_raise_power(dip, 0, PM_LEVEL_D0) !=
1915 DDI_SUCCESS) {
1916 mptsas_log(mpt, CE_WARN,
1917 "mptsas%d: Raise power request failed.",
1918 mpt->m_instance);
1919 (void) pm_idle_component(dip, 0);
1920 return (DDI_FAILURE);
1921 }
1922 }
1923 }
1924
1925 /*
1926 * Send RAID action system shutdown to sync IR. After action, send a
1927 * Message Unit Reset. Since after that DMA resource will be freed,
1928 * set ioc to READY state will avoid HBA initiated DMA operation.
1929 */
1930 mutex_enter(&mpt->m_mutex);
1931 MPTSAS_DISABLE_INTR(mpt);
1932 mptsas_raid_action_system_shutdown(mpt);
1933 mpt->m_softstate |= MPTSAS_SS_MSG_UNIT_RESET;
1934 (void) mptsas_ioc_reset(mpt, FALSE);
1935 mutex_exit(&mpt->m_mutex);
1936 mptsas_rem_intrs(mpt);
1937 ddi_taskq_destroy(mpt->m_event_taskq);
1938 ddi_taskq_destroy(mpt->m_dr_taskq);
1939
1940 if (mpt->m_doneq_thread_n) {
1941 mutex_enter(&mpt->m_doneq_mutex);
1942 doneq_thread_num = mpt->m_doneq_thread_n;
1943 for (i = 0; i < mpt->m_doneq_thread_n; i++) {
1944 mutex_enter(&mpt->m_doneq_thread_id[i].mutex);
1945 mpt->m_doneq_thread_id[i].flag &=
1946 (~MPTSAS_DONEQ_THREAD_ACTIVE);
1947 cv_signal(&mpt->m_doneq_thread_id[i].cv);
1948 mutex_exit(&mpt->m_doneq_thread_id[i].mutex);
1949 }
1950 while (mpt->m_doneq_thread_n) {
1951 cv_wait(&mpt->m_doneq_thread_cv,
1952 &mpt->m_doneq_mutex);
1953 }
1954 for (i = 0; i < doneq_thread_num; i++) {
1955 cv_destroy(&mpt->m_doneq_thread_id[i].cv);
1956 mutex_destroy(&mpt->m_doneq_thread_id[i].mutex);
1957 }
1958 kmem_free(mpt->m_doneq_thread_id,
1959 sizeof (mptsas_doneq_thread_list_t)
1960 * doneq_thread_num);
1961 mutex_exit(&mpt->m_doneq_mutex);
1962 cv_destroy(&mpt->m_doneq_thread_cv);
1963 mutex_destroy(&mpt->m_doneq_mutex);
1964 }
1965
1966 scsi_hba_reset_notify_tear_down(mpt->m_reset_notify_listf);
1967
1968 mptsas_list_del(mpt);
1969
1970 /*
1971 * Cancel timeout threads for this mpt
1972 */
1973 mutex_enter(&mpt->m_mutex);
1974 if (mpt->m_quiesce_timeid) {
1975 timeout_id_t tid = mpt->m_quiesce_timeid;
1976 mpt->m_quiesce_timeid = 0;
1977 mutex_exit(&mpt->m_mutex);
1978 (void) untimeout(tid);
1979 mutex_enter(&mpt->m_mutex);
1980 }
1981
1982 if (mpt->m_restart_cmd_timeid) {
1983 timeout_id_t tid = mpt->m_restart_cmd_timeid;
1984 mpt->m_restart_cmd_timeid = 0;
1985 mutex_exit(&mpt->m_mutex);
1986 (void) untimeout(tid);
1987 mutex_enter(&mpt->m_mutex);
1988 }
1989
1990 mutex_exit(&mpt->m_mutex);
1991
1992 /*
1993 * last mpt? ... if active, CANCEL watch threads.
1994 */
1995 mutex_enter(&mptsas_global_mutex);
1996 if (mptsas_head == NULL) {
1997 timeout_id_t tid;
1998 /*
1999 * Clear mptsas_timeouts_enable so that the watch thread
2000 * gets restarted on DDI_ATTACH
2001 */
2002 mptsas_timeouts_enabled = 0;
2003 if (mptsas_timeout_id) {
2004 tid = mptsas_timeout_id;
2005 mptsas_timeout_id = 0;
2006 mutex_exit(&mptsas_global_mutex);
2007 (void) untimeout(tid);
2008 mutex_enter(&mptsas_global_mutex);
2009 }
2010 if (mptsas_reset_watch) {
2011 tid = mptsas_reset_watch;
2012 mptsas_reset_watch = 0;
2013 mutex_exit(&mptsas_global_mutex);
2014 (void) untimeout(tid);
2015 mutex_enter(&mptsas_global_mutex);
2016 }
2017 }
2018 mutex_exit(&mptsas_global_mutex);
2019
2020 /*
2021 * Delete Phy stats
2022 */
2023 mptsas_destroy_phy_stats(mpt);
2024
2025 mptsas_destroy_hashes(mpt);
2026
2027 /*
2028 * Delete nt_active.
2029 */
2030 mutex_enter(&mpt->m_mutex);
2031 mptsas_free_active_slots(mpt);
2032 mutex_exit(&mpt->m_mutex);
2033
2034 /* deallocate everything that was allocated in mptsas_attach */
2035 mptsas_cache_destroy(mpt);
2036
2037 mptsas_hba_fini(mpt);
2038 mptsas_cfg_fini(mpt);
2039
2040 /* Lower the power informing PM Framework */
2041 if (mpt->m_options & MPTSAS_OPT_PM) {
2042 if (pm_lower_power(dip, 0, PM_LEVEL_D3) != DDI_SUCCESS)
2043 mptsas_log(mpt, CE_WARN,
2044 "!mptsas%d: Lower power request failed "
2045 "during detach, ignoring.",
2046 mpt->m_instance);
2047 }
2048
2049 mutex_destroy(&mpt->m_tx_waitq_mutex);
2050 mutex_destroy(&mpt->m_passthru_mutex);
2051 mutex_destroy(&mpt->m_mutex);
2052 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
2053 mutex_destroy(&mpt->m_phy_info[i].smhba_info.phy_mutex);
2054 }
2055 cv_destroy(&mpt->m_cv);
2056 cv_destroy(&mpt->m_passthru_cv);
2057 cv_destroy(&mpt->m_fw_cv);
2058 cv_destroy(&mpt->m_config_cv);
2059 cv_destroy(&mpt->m_fw_diag_cv);
2060 cv_destroy(&mpt->m_extreq_sense_refcount_cv);
2061
2062 mptsas_smp_teardown(mpt);
2063 mptsas_enc_teardown(mpt);
2064 mptsas_hba_teardown(mpt);
2065
2066 mptsas_config_space_fini(mpt);
2067
2068 mptsas_free_handshake_msg(mpt);
2069
2070 mptsas_fm_fini(mpt);
2071 ddi_soft_state_free(mptsas_state, ddi_get_instance(dip));
2072 ddi_prop_remove_all(dip);
2073
2074 return (DDI_SUCCESS);
2075 }
2076
2077 static void
mptsas_list_add(mptsas_t * mpt)2078 mptsas_list_add(mptsas_t *mpt)
2079 {
2080 rw_enter(&mptsas_global_rwlock, RW_WRITER);
2081
2082 if (mptsas_head == NULL) {
2083 mptsas_head = mpt;
2084 } else {
2085 mptsas_tail->m_next = mpt;
2086 }
2087 mptsas_tail = mpt;
2088 rw_exit(&mptsas_global_rwlock);
2089 }
2090
2091 static void
mptsas_list_del(mptsas_t * mpt)2092 mptsas_list_del(mptsas_t *mpt)
2093 {
2094 mptsas_t *m;
2095 /*
2096 * Remove device instance from the global linked list
2097 */
2098 rw_enter(&mptsas_global_rwlock, RW_WRITER);
2099 if (mptsas_head == mpt) {
2100 m = mptsas_head = mpt->m_next;
2101 } else {
2102 for (m = mptsas_head; m != NULL; m = m->m_next) {
2103 if (m->m_next == mpt) {
2104 m->m_next = mpt->m_next;
2105 break;
2106 }
2107 }
2108 if (m == NULL) {
2109 mptsas_log(mpt, CE_PANIC, "Not in softc list!");
2110 }
2111 }
2112
2113 if (mptsas_tail == mpt) {
2114 mptsas_tail = m;
2115 }
2116 rw_exit(&mptsas_global_rwlock);
2117 }
2118
2119 static int
mptsas_alloc_handshake_msg(mptsas_t * mpt,size_t alloc_size)2120 mptsas_alloc_handshake_msg(mptsas_t *mpt, size_t alloc_size)
2121 {
2122 ddi_dma_attr_t task_dma_attrs;
2123
2124 mpt->m_hshk_dma_size = 0;
2125 task_dma_attrs = mpt->m_msg_dma_attr;
2126 task_dma_attrs.dma_attr_sgllen = 1;
2127 task_dma_attrs.dma_attr_granular = (uint32_t)(alloc_size);
2128
2129 /* allocate Task Management ddi_dma resources */
2130 if (mptsas_dma_addr_create(mpt, task_dma_attrs,
2131 &mpt->m_hshk_dma_hdl, &mpt->m_hshk_acc_hdl, &mpt->m_hshk_memp,
2132 alloc_size, NULL) == FALSE) {
2133 return (DDI_FAILURE);
2134 }
2135 mpt->m_hshk_dma_size = alloc_size;
2136
2137 return (DDI_SUCCESS);
2138 }
2139
2140 static void
mptsas_free_handshake_msg(mptsas_t * mpt)2141 mptsas_free_handshake_msg(mptsas_t *mpt)
2142 {
2143 if (mpt->m_hshk_dma_size == 0)
2144 return;
2145 mptsas_dma_addr_destroy(&mpt->m_hshk_dma_hdl, &mpt->m_hshk_acc_hdl);
2146 mpt->m_hshk_dma_size = 0;
2147 }
2148
2149 static int
mptsas_hba_setup(mptsas_t * mpt)2150 mptsas_hba_setup(mptsas_t *mpt)
2151 {
2152 scsi_hba_tran_t *hba_tran;
2153 int tran_flags;
2154
2155 /* Allocate a transport structure */
2156 hba_tran = mpt->m_tran = scsi_hba_tran_alloc(mpt->m_dip,
2157 SCSI_HBA_CANSLEEP);
2158 ASSERT(mpt->m_tran != NULL);
2159
2160 hba_tran->tran_hba_private = mpt;
2161 hba_tran->tran_tgt_private = NULL;
2162
2163 hba_tran->tran_tgt_init = mptsas_scsi_tgt_init;
2164 hba_tran->tran_tgt_free = mptsas_scsi_tgt_free;
2165
2166 hba_tran->tran_start = mptsas_scsi_start;
2167 hba_tran->tran_reset = mptsas_scsi_reset;
2168 hba_tran->tran_abort = mptsas_scsi_abort;
2169 hba_tran->tran_getcap = mptsas_scsi_getcap;
2170 hba_tran->tran_setcap = mptsas_scsi_setcap;
2171 hba_tran->tran_init_pkt = mptsas_scsi_init_pkt;
2172 hba_tran->tran_destroy_pkt = mptsas_scsi_destroy_pkt;
2173
2174 hba_tran->tran_dmafree = mptsas_scsi_dmafree;
2175 hba_tran->tran_sync_pkt = mptsas_scsi_sync_pkt;
2176 hba_tran->tran_reset_notify = mptsas_scsi_reset_notify;
2177
2178 hba_tran->tran_get_bus_addr = mptsas_get_bus_addr;
2179 hba_tran->tran_get_name = mptsas_get_name;
2180
2181 hba_tran->tran_quiesce = mptsas_scsi_quiesce;
2182 hba_tran->tran_unquiesce = mptsas_scsi_unquiesce;
2183 hba_tran->tran_bus_reset = NULL;
2184
2185 hba_tran->tran_add_eventcall = NULL;
2186 hba_tran->tran_get_eventcookie = NULL;
2187 hba_tran->tran_post_event = NULL;
2188 hba_tran->tran_remove_eventcall = NULL;
2189
2190 hba_tran->tran_bus_config = mptsas_bus_config;
2191
2192 hba_tran->tran_interconnect_type = INTERCONNECT_SAS;
2193
2194 /*
2195 * All children of the HBA are iports. We need tran was cloned.
2196 * So we pass the flags to SCSA. SCSI_HBA_TRAN_CLONE will be
2197 * inherited to iport's tran vector.
2198 */
2199 tran_flags = (SCSI_HBA_HBA | SCSI_HBA_TRAN_CLONE);
2200
2201 if (scsi_hba_attach_setup(mpt->m_dip, &mpt->m_msg_dma_attr,
2202 hba_tran, tran_flags) != DDI_SUCCESS) {
2203 mptsas_log(mpt, CE_WARN, "hba attach setup failed");
2204 scsi_hba_tran_free(hba_tran);
2205 mpt->m_tran = NULL;
2206 return (FALSE);
2207 }
2208 return (TRUE);
2209 }
2210
2211 static void
mptsas_hba_teardown(mptsas_t * mpt)2212 mptsas_hba_teardown(mptsas_t *mpt)
2213 {
2214 (void) scsi_hba_detach(mpt->m_dip);
2215 if (mpt->m_tran != NULL) {
2216 scsi_hba_tran_free(mpt->m_tran);
2217 mpt->m_tran = NULL;
2218 }
2219 }
2220
2221 static void
mptsas_iport_register(mptsas_t * mpt)2222 mptsas_iport_register(mptsas_t *mpt)
2223 {
2224 int i, j;
2225 mptsas_phymask_t mask = 0x0;
2226 /*
2227 * initial value of mask is 0
2228 */
2229 mutex_enter(&mpt->m_mutex);
2230 for (i = 0; i < mpt->m_num_phys; i++) {
2231 mptsas_phymask_t phy_mask = 0x0;
2232 char phy_mask_name[MPTSAS_MAX_PHYS];
2233 uint8_t current_port;
2234
2235 if (mpt->m_phy_info[i].attached_devhdl == 0)
2236 continue;
2237
2238 bzero(phy_mask_name, sizeof (phy_mask_name));
2239
2240 current_port = mpt->m_phy_info[i].port_num;
2241
2242 if ((mask & (1 << i)) != 0)
2243 continue;
2244
2245 for (j = 0; j < mpt->m_num_phys; j++) {
2246 if (mpt->m_phy_info[j].attached_devhdl &&
2247 (mpt->m_phy_info[j].port_num == current_port)) {
2248 phy_mask |= (1 << j);
2249 }
2250 }
2251 mask = mask | phy_mask;
2252
2253 for (j = 0; j < mpt->m_num_phys; j++) {
2254 if ((phy_mask >> j) & 0x01) {
2255 mpt->m_phy_info[j].phy_mask = phy_mask;
2256 }
2257 }
2258
2259 (void) sprintf(phy_mask_name, "%x", phy_mask);
2260
2261 mutex_exit(&mpt->m_mutex);
2262 /*
2263 * register a iport
2264 */
2265 (void) scsi_hba_iport_register(mpt->m_dip, phy_mask_name);
2266 mutex_enter(&mpt->m_mutex);
2267 }
2268 mutex_exit(&mpt->m_mutex);
2269 /*
2270 * register a virtual port for RAID volume always
2271 */
2272 (void) scsi_hba_iport_register(mpt->m_dip, "v0");
2273
2274 }
2275
2276 static int
mptsas_smp_setup(mptsas_t * mpt)2277 mptsas_smp_setup(mptsas_t *mpt)
2278 {
2279 mpt->m_smptran = smp_hba_tran_alloc(mpt->m_dip);
2280 ASSERT(mpt->m_smptran != NULL);
2281 mpt->m_smptran->smp_tran_hba_private = mpt;
2282 mpt->m_smptran->smp_tran_start = mptsas_smp_start;
2283 if (smp_hba_attach_setup(mpt->m_dip, mpt->m_smptran) != DDI_SUCCESS) {
2284 mptsas_log(mpt, CE_WARN, "smp attach setup failed");
2285 smp_hba_tran_free(mpt->m_smptran);
2286 mpt->m_smptran = NULL;
2287 return (FALSE);
2288 }
2289 /*
2290 * Initialize smp hash table
2291 */
2292 mpt->m_smp_targets = refhash_create(MPTSAS_SMP_BUCKET_COUNT,
2293 mptsas_target_addr_hash, mptsas_target_addr_cmp,
2294 mptsas_smp_free, sizeof (mptsas_smp_t),
2295 offsetof(mptsas_smp_t, m_link), offsetof(mptsas_smp_t, m_addr),
2296 KM_SLEEP);
2297 mpt->m_smp_devhdl = 0xFFFF;
2298
2299 return (TRUE);
2300 }
2301
2302 static void
mptsas_smp_teardown(mptsas_t * mpt)2303 mptsas_smp_teardown(mptsas_t *mpt)
2304 {
2305 (void) smp_hba_detach(mpt->m_dip);
2306 if (mpt->m_smptran != NULL) {
2307 smp_hba_tran_free(mpt->m_smptran);
2308 mpt->m_smptran = NULL;
2309 }
2310 mpt->m_smp_devhdl = 0;
2311 }
2312
2313 static int
mptsas_enc_setup(mptsas_t * mpt)2314 mptsas_enc_setup(mptsas_t *mpt)
2315 {
2316 list_create(&mpt->m_enclosures, sizeof (mptsas_enclosure_t),
2317 offsetof(mptsas_enclosure_t, me_link));
2318 return (TRUE);
2319 }
2320
2321 static void
mptsas_enc_free(mptsas_enclosure_t * mep)2322 mptsas_enc_free(mptsas_enclosure_t *mep)
2323 {
2324 if (mep == NULL)
2325 return;
2326 if (mep->me_slotleds != NULL) {
2327 VERIFY3U(mep->me_nslots, >, 0);
2328 kmem_free(mep->me_slotleds, sizeof (uint8_t) * mep->me_nslots);
2329 }
2330 kmem_free(mep, sizeof (mptsas_enclosure_t));
2331 }
2332
2333 static void
mptsas_enc_teardown(mptsas_t * mpt)2334 mptsas_enc_teardown(mptsas_t *mpt)
2335 {
2336 mptsas_enclosure_t *mep;
2337
2338 while ((mep = list_remove_head(&mpt->m_enclosures)) != NULL) {
2339 mptsas_enc_free(mep);
2340 }
2341 list_destroy(&mpt->m_enclosures);
2342 }
2343
2344 static mptsas_enclosure_t *
mptsas_enc_lookup(mptsas_t * mpt,uint16_t hdl)2345 mptsas_enc_lookup(mptsas_t *mpt, uint16_t hdl)
2346 {
2347 mptsas_enclosure_t *mep;
2348
2349 ASSERT(MUTEX_HELD(&mpt->m_mutex));
2350
2351 for (mep = list_head(&mpt->m_enclosures); mep != NULL;
2352 mep = list_next(&mpt->m_enclosures, mep)) {
2353 if (hdl == mep->me_enchdl) {
2354 return (mep);
2355 }
2356 }
2357
2358 return (NULL);
2359 }
2360
2361 static int
mptsas_cache_create(mptsas_t * mpt)2362 mptsas_cache_create(mptsas_t *mpt)
2363 {
2364 int instance = mpt->m_instance;
2365 char buf[64];
2366
2367 /*
2368 * create kmem cache for packets
2369 */
2370 (void) sprintf(buf, "mptsas%d_cache", instance);
2371 mpt->m_kmem_cache = kmem_cache_create(buf,
2372 sizeof (struct mptsas_cmd) + scsi_pkt_size(), 8,
2373 mptsas_kmem_cache_constructor, mptsas_kmem_cache_destructor,
2374 NULL, (void *)mpt, NULL, 0);
2375
2376 if (mpt->m_kmem_cache == NULL) {
2377 mptsas_log(mpt, CE_WARN, "creating kmem cache failed");
2378 return (FALSE);
2379 }
2380
2381 /*
2382 * create kmem cache for extra SGL frames if SGL cannot
2383 * be accomodated into main request frame.
2384 */
2385 (void) sprintf(buf, "mptsas%d_cache_frames", instance);
2386 mpt->m_cache_frames = kmem_cache_create(buf,
2387 sizeof (mptsas_cache_frames_t), 8,
2388 mptsas_cache_frames_constructor, mptsas_cache_frames_destructor,
2389 NULL, (void *)mpt, NULL, 0);
2390
2391 if (mpt->m_cache_frames == NULL) {
2392 mptsas_log(mpt, CE_WARN, "creating cache for frames failed");
2393 return (FALSE);
2394 }
2395
2396 return (TRUE);
2397 }
2398
2399 static void
mptsas_cache_destroy(mptsas_t * mpt)2400 mptsas_cache_destroy(mptsas_t *mpt)
2401 {
2402 /* deallocate in reverse order */
2403 if (mpt->m_cache_frames) {
2404 kmem_cache_destroy(mpt->m_cache_frames);
2405 mpt->m_cache_frames = NULL;
2406 }
2407 if (mpt->m_kmem_cache) {
2408 kmem_cache_destroy(mpt->m_kmem_cache);
2409 mpt->m_kmem_cache = NULL;
2410 }
2411 }
2412
2413 static int
mptsas_power(dev_info_t * dip,int component,int level)2414 mptsas_power(dev_info_t *dip, int component, int level)
2415 {
2416 #ifndef __lock_lint
2417 _NOTE(ARGUNUSED(component))
2418 #endif
2419 mptsas_t *mpt;
2420 int rval = DDI_SUCCESS;
2421 int polls = 0;
2422 uint32_t ioc_status;
2423
2424 if (scsi_hba_iport_unit_address(dip) != 0)
2425 return (DDI_SUCCESS);
2426
2427 mpt = ddi_get_soft_state(mptsas_state, ddi_get_instance(dip));
2428 if (mpt == NULL) {
2429 return (DDI_FAILURE);
2430 }
2431
2432 mutex_enter(&mpt->m_mutex);
2433
2434 /*
2435 * If the device is busy, don't lower its power level
2436 */
2437 if (mpt->m_busy && (mpt->m_power_level > level)) {
2438 mutex_exit(&mpt->m_mutex);
2439 return (DDI_FAILURE);
2440 }
2441 switch (level) {
2442 case PM_LEVEL_D0:
2443 NDBG11(("mptsas%d: turning power ON.", mpt->m_instance));
2444 MPTSAS_POWER_ON(mpt);
2445 /*
2446 * Wait up to 30 seconds for IOC to come out of reset.
2447 */
2448 while (((ioc_status = ddi_get32(mpt->m_datap,
2449 &mpt->m_reg->Doorbell)) &
2450 MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_RESET) {
2451 if (polls++ > 3000) {
2452 break;
2453 }
2454 delay(drv_usectohz(10000));
2455 }
2456 /*
2457 * If IOC is not in operational state, try to hard reset it.
2458 */
2459 if ((ioc_status & MPI2_IOC_STATE_MASK) !=
2460 MPI2_IOC_STATE_OPERATIONAL) {
2461 mpt->m_softstate &= ~MPTSAS_SS_MSG_UNIT_RESET;
2462 if (mptsas_restart_ioc(mpt) == DDI_FAILURE) {
2463 mptsas_log(mpt, CE_WARN,
2464 "mptsas_power: hard reset failed");
2465 mutex_exit(&mpt->m_mutex);
2466 return (DDI_FAILURE);
2467 }
2468 }
2469 mpt->m_power_level = PM_LEVEL_D0;
2470 break;
2471 case PM_LEVEL_D3:
2472 NDBG11(("mptsas%d: turning power OFF.", mpt->m_instance));
2473 MPTSAS_POWER_OFF(mpt);
2474 break;
2475 default:
2476 mptsas_log(mpt, CE_WARN, "mptsas%d: unknown power level <%x>.",
2477 mpt->m_instance, level);
2478 rval = DDI_FAILURE;
2479 break;
2480 }
2481 mutex_exit(&mpt->m_mutex);
2482 return (rval);
2483 }
2484
2485 /*
2486 * Initialize configuration space and figure out which
2487 * chip and revison of the chip the mpt driver is using.
2488 */
2489 static int
mptsas_config_space_init(mptsas_t * mpt)2490 mptsas_config_space_init(mptsas_t *mpt)
2491 {
2492 NDBG0(("mptsas_config_space_init"));
2493
2494 if (mpt->m_config_handle != NULL)
2495 return (TRUE);
2496
2497 if (pci_config_setup(mpt->m_dip,
2498 &mpt->m_config_handle) != DDI_SUCCESS) {
2499 mptsas_log(mpt, CE_WARN, "cannot map configuration space.");
2500 return (FALSE);
2501 }
2502
2503 /*
2504 * This is a workaround for a XMITS ASIC bug which does not
2505 * drive the CBE upper bits.
2506 */
2507 if (pci_config_get16(mpt->m_config_handle, PCI_CONF_STAT) &
2508 PCI_STAT_PERROR) {
2509 pci_config_put16(mpt->m_config_handle, PCI_CONF_STAT,
2510 PCI_STAT_PERROR);
2511 }
2512
2513 mptsas_setup_cmd_reg(mpt);
2514
2515 /*
2516 * Get the chip device id:
2517 */
2518 mpt->m_devid = pci_config_get16(mpt->m_config_handle, PCI_CONF_DEVID);
2519
2520 /*
2521 * Save the revision.
2522 */
2523 mpt->m_revid = pci_config_get8(mpt->m_config_handle, PCI_CONF_REVID);
2524
2525 /*
2526 * Save the SubSystem Vendor and Device IDs
2527 */
2528 mpt->m_svid = pci_config_get16(mpt->m_config_handle, PCI_CONF_SUBVENID);
2529 mpt->m_ssid = pci_config_get16(mpt->m_config_handle, PCI_CONF_SUBSYSID);
2530
2531 /*
2532 * Set the latency timer to 0x40 as specified by the upa -> pci
2533 * bridge chip design team. This may be done by the sparc pci
2534 * bus nexus driver, but the driver should make sure the latency
2535 * timer is correct for performance reasons.
2536 */
2537 pci_config_put8(mpt->m_config_handle, PCI_CONF_LATENCY_TIMER,
2538 MPTSAS_LATENCY_TIMER);
2539
2540 (void) mptsas_get_pci_cap(mpt);
2541 return (TRUE);
2542 }
2543
2544 static void
mptsas_config_space_fini(mptsas_t * mpt)2545 mptsas_config_space_fini(mptsas_t *mpt)
2546 {
2547 if (mpt->m_config_handle != NULL) {
2548 mptsas_disable_bus_master(mpt);
2549 pci_config_teardown(&mpt->m_config_handle);
2550 mpt->m_config_handle = NULL;
2551 }
2552 }
2553
2554 static void
mptsas_setup_cmd_reg(mptsas_t * mpt)2555 mptsas_setup_cmd_reg(mptsas_t *mpt)
2556 {
2557 ushort_t cmdreg;
2558
2559 /*
2560 * Set the command register to the needed values.
2561 */
2562 cmdreg = pci_config_get16(mpt->m_config_handle, PCI_CONF_COMM);
2563 cmdreg |= (PCI_COMM_ME | PCI_COMM_SERR_ENABLE |
2564 PCI_COMM_PARITY_DETECT | PCI_COMM_MAE);
2565 cmdreg &= ~PCI_COMM_IO;
2566 pci_config_put16(mpt->m_config_handle, PCI_CONF_COMM, cmdreg);
2567 }
2568
2569 static void
mptsas_disable_bus_master(mptsas_t * mpt)2570 mptsas_disable_bus_master(mptsas_t *mpt)
2571 {
2572 ushort_t cmdreg;
2573
2574 /*
2575 * Clear the master enable bit in the PCI command register.
2576 * This prevents any bus mastering activity like DMA.
2577 */
2578 cmdreg = pci_config_get16(mpt->m_config_handle, PCI_CONF_COMM);
2579 cmdreg &= ~PCI_COMM_ME;
2580 pci_config_put16(mpt->m_config_handle, PCI_CONF_COMM, cmdreg);
2581 }
2582
2583 int
mptsas_dma_alloc(mptsas_t * mpt,mptsas_dma_alloc_state_t * dma_statep)2584 mptsas_dma_alloc(mptsas_t *mpt, mptsas_dma_alloc_state_t *dma_statep)
2585 {
2586 ddi_dma_attr_t attrs;
2587
2588 attrs = mpt->m_io_dma_attr;
2589 attrs.dma_attr_sgllen = 1;
2590
2591 ASSERT(dma_statep != NULL);
2592
2593 if (mptsas_dma_addr_create(mpt, attrs, &dma_statep->handle,
2594 &dma_statep->accessp, &dma_statep->memp, dma_statep->size,
2595 &dma_statep->cookie) == FALSE) {
2596 return (DDI_FAILURE);
2597 }
2598
2599 return (DDI_SUCCESS);
2600 }
2601
2602 void
mptsas_dma_free(mptsas_dma_alloc_state_t * dma_statep)2603 mptsas_dma_free(mptsas_dma_alloc_state_t *dma_statep)
2604 {
2605 ASSERT(dma_statep != NULL);
2606 mptsas_dma_addr_destroy(&dma_statep->handle, &dma_statep->accessp);
2607 dma_statep->size = 0;
2608 }
2609
2610 int
mptsas_do_dma(mptsas_t * mpt,uint32_t size,int var,int (* callback)())2611 mptsas_do_dma(mptsas_t *mpt, uint32_t size, int var, int (*callback)())
2612 {
2613 ddi_dma_attr_t attrs;
2614 ddi_dma_handle_t dma_handle;
2615 caddr_t memp;
2616 ddi_acc_handle_t accessp;
2617 int rval;
2618
2619 ASSERT(mutex_owned(&mpt->m_mutex));
2620
2621 attrs = mpt->m_msg_dma_attr;
2622 attrs.dma_attr_sgllen = 1;
2623 attrs.dma_attr_granular = size;
2624
2625 if (mptsas_dma_addr_create(mpt, attrs, &dma_handle,
2626 &accessp, &memp, size, NULL) == FALSE) {
2627 return (DDI_FAILURE);
2628 }
2629
2630 rval = (*callback) (mpt, memp, var, accessp);
2631
2632 if ((mptsas_check_dma_handle(dma_handle) != DDI_SUCCESS) ||
2633 (mptsas_check_acc_handle(accessp) != DDI_SUCCESS)) {
2634 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
2635 rval = DDI_FAILURE;
2636 }
2637
2638 mptsas_dma_addr_destroy(&dma_handle, &accessp);
2639 return (rval);
2640
2641 }
2642
2643 static int
mptsas_alloc_request_frames(mptsas_t * mpt)2644 mptsas_alloc_request_frames(mptsas_t *mpt)
2645 {
2646 ddi_dma_attr_t frame_dma_attrs;
2647 caddr_t memp;
2648 ddi_dma_cookie_t cookie;
2649 size_t mem_size;
2650
2651 /*
2652 * re-alloc when it has already alloced
2653 */
2654 if (mpt->m_dma_req_frame_hdl)
2655 mptsas_dma_addr_destroy(&mpt->m_dma_req_frame_hdl,
2656 &mpt->m_acc_req_frame_hdl);
2657
2658 /*
2659 * The size of the request frame pool is:
2660 * Number of Request Frames * Request Frame Size
2661 */
2662 mem_size = mpt->m_max_requests * mpt->m_req_frame_size;
2663
2664 /*
2665 * set the DMA attributes. System Request Message Frames must be
2666 * aligned on a 16-byte boundry.
2667 */
2668 frame_dma_attrs = mpt->m_msg_dma_attr;
2669 frame_dma_attrs.dma_attr_align = 16;
2670 frame_dma_attrs.dma_attr_sgllen = 1;
2671
2672 /*
2673 * allocate the request frame pool.
2674 */
2675 if (mptsas_dma_addr_create(mpt, frame_dma_attrs,
2676 &mpt->m_dma_req_frame_hdl, &mpt->m_acc_req_frame_hdl, &memp,
2677 mem_size, &cookie) == FALSE) {
2678 return (DDI_FAILURE);
2679 }
2680
2681 /*
2682 * Store the request frame memory address. This chip uses this
2683 * address to dma to and from the driver's frame. The second
2684 * address is the address mpt uses to fill in the frame.
2685 */
2686 mpt->m_req_frame_dma_addr = cookie.dmac_laddress;
2687 mpt->m_req_frame = memp;
2688
2689 /*
2690 * Clear the request frame pool.
2691 */
2692 bzero(mpt->m_req_frame, mem_size);
2693
2694 return (DDI_SUCCESS);
2695 }
2696
2697 static int
mptsas_alloc_sense_bufs(mptsas_t * mpt)2698 mptsas_alloc_sense_bufs(mptsas_t *mpt)
2699 {
2700 ddi_dma_attr_t sense_dma_attrs;
2701 caddr_t memp;
2702 ddi_dma_cookie_t cookie;
2703 size_t mem_size;
2704 int num_extrqsense_bufs;
2705
2706 ASSERT(mpt->m_extreq_sense_refcount == 0);
2707
2708 /*
2709 * re-alloc when it has already alloced
2710 */
2711 if (mpt->m_dma_req_sense_hdl) {
2712 rmfreemap(mpt->m_erqsense_map);
2713 mptsas_dma_addr_destroy(&mpt->m_dma_req_sense_hdl,
2714 &mpt->m_acc_req_sense_hdl);
2715 }
2716
2717 /*
2718 * The size of the request sense pool is:
2719 * (Number of Request Frames - 2 ) * Request Sense Size +
2720 * extra memory for extended sense requests.
2721 */
2722 mem_size = ((mpt->m_max_requests - 2) * mpt->m_req_sense_size) +
2723 mptsas_extreq_sense_bufsize;
2724
2725 /*
2726 * set the DMA attributes. ARQ buffers
2727 * aligned on a 16-byte boundry.
2728 */
2729 sense_dma_attrs = mpt->m_msg_dma_attr;
2730 sense_dma_attrs.dma_attr_align = 16;
2731 sense_dma_attrs.dma_attr_sgllen = 1;
2732
2733 /*
2734 * allocate the request sense buffer pool.
2735 */
2736 if (mptsas_dma_addr_create(mpt, sense_dma_attrs,
2737 &mpt->m_dma_req_sense_hdl, &mpt->m_acc_req_sense_hdl, &memp,
2738 mem_size, &cookie) == FALSE) {
2739 return (DDI_FAILURE);
2740 }
2741
2742 /*
2743 * Store the request sense base memory address. This chip uses this
2744 * address to dma the request sense data. The second
2745 * address is the address mpt uses to access the data.
2746 * The third is the base for the extended rqsense buffers.
2747 */
2748 mpt->m_req_sense_dma_addr = cookie.dmac_laddress;
2749 mpt->m_req_sense = memp;
2750 memp += (mpt->m_max_requests - 2) * mpt->m_req_sense_size;
2751 mpt->m_extreq_sense = memp;
2752
2753 /*
2754 * The extra memory is divided up into multiples of the base
2755 * buffer size in order to allocate via rmalloc().
2756 * Note that the rmallocmap cannot start at zero!
2757 */
2758 num_extrqsense_bufs = mptsas_extreq_sense_bufsize /
2759 mpt->m_req_sense_size;
2760 mpt->m_erqsense_map = rmallocmap_wait(num_extrqsense_bufs);
2761 rmfree(mpt->m_erqsense_map, num_extrqsense_bufs, 1);
2762
2763 /*
2764 * Clear the pool.
2765 */
2766 bzero(mpt->m_req_sense, mem_size);
2767
2768 return (DDI_SUCCESS);
2769 }
2770
2771 static int
mptsas_alloc_reply_frames(mptsas_t * mpt)2772 mptsas_alloc_reply_frames(mptsas_t *mpt)
2773 {
2774 ddi_dma_attr_t frame_dma_attrs;
2775 caddr_t memp;
2776 ddi_dma_cookie_t cookie;
2777 size_t mem_size;
2778
2779 /*
2780 * re-alloc when it has already alloced
2781 */
2782 if (mpt->m_dma_reply_frame_hdl) {
2783 mptsas_dma_addr_destroy(&mpt->m_dma_reply_frame_hdl,
2784 &mpt->m_acc_reply_frame_hdl);
2785 }
2786
2787 /*
2788 * The size of the reply frame pool is:
2789 * Number of Reply Frames * Reply Frame Size
2790 */
2791 mem_size = mpt->m_max_replies * mpt->m_reply_frame_size;
2792
2793 /*
2794 * set the DMA attributes. System Reply Message Frames must be
2795 * aligned on a 4-byte boundry. This is the default.
2796 */
2797 frame_dma_attrs = mpt->m_msg_dma_attr;
2798 frame_dma_attrs.dma_attr_sgllen = 1;
2799
2800 /*
2801 * allocate the reply frame pool
2802 */
2803 if (mptsas_dma_addr_create(mpt, frame_dma_attrs,
2804 &mpt->m_dma_reply_frame_hdl, &mpt->m_acc_reply_frame_hdl, &memp,
2805 mem_size, &cookie) == FALSE) {
2806 return (DDI_FAILURE);
2807 }
2808
2809 /*
2810 * Store the reply frame memory address. This chip uses this
2811 * address to dma to and from the driver's frame. The second
2812 * address is the address mpt uses to process the frame.
2813 */
2814 mpt->m_reply_frame_dma_addr = cookie.dmac_laddress;
2815 mpt->m_reply_frame = memp;
2816
2817 /*
2818 * Clear the reply frame pool.
2819 */
2820 bzero(mpt->m_reply_frame, mem_size);
2821
2822 return (DDI_SUCCESS);
2823 }
2824
2825 static int
mptsas_alloc_free_queue(mptsas_t * mpt)2826 mptsas_alloc_free_queue(mptsas_t *mpt)
2827 {
2828 ddi_dma_attr_t frame_dma_attrs;
2829 caddr_t memp;
2830 ddi_dma_cookie_t cookie;
2831 size_t mem_size;
2832
2833 /*
2834 * re-alloc when it has already alloced
2835 */
2836 if (mpt->m_dma_free_queue_hdl) {
2837 mptsas_dma_addr_destroy(&mpt->m_dma_free_queue_hdl,
2838 &mpt->m_acc_free_queue_hdl);
2839 }
2840
2841 /*
2842 * The reply free queue size is:
2843 * Reply Free Queue Depth * 4
2844 * The "4" is the size of one 32 bit address (low part of 64-bit
2845 * address)
2846 */
2847 mem_size = mpt->m_free_queue_depth * 4;
2848
2849 /*
2850 * set the DMA attributes The Reply Free Queue must be aligned on a
2851 * 16-byte boundry.
2852 */
2853 frame_dma_attrs = mpt->m_msg_dma_attr;
2854 frame_dma_attrs.dma_attr_align = 16;
2855 frame_dma_attrs.dma_attr_sgllen = 1;
2856
2857 /*
2858 * allocate the reply free queue
2859 */
2860 if (mptsas_dma_addr_create(mpt, frame_dma_attrs,
2861 &mpt->m_dma_free_queue_hdl, &mpt->m_acc_free_queue_hdl, &memp,
2862 mem_size, &cookie) == FALSE) {
2863 return (DDI_FAILURE);
2864 }
2865
2866 /*
2867 * Store the reply free queue memory address. This chip uses this
2868 * address to read from the reply free queue. The second address
2869 * is the address mpt uses to manage the queue.
2870 */
2871 mpt->m_free_queue_dma_addr = cookie.dmac_laddress;
2872 mpt->m_free_queue = memp;
2873
2874 /*
2875 * Clear the reply free queue memory.
2876 */
2877 bzero(mpt->m_free_queue, mem_size);
2878
2879 return (DDI_SUCCESS);
2880 }
2881
2882 static int
mptsas_alloc_post_queue(mptsas_t * mpt)2883 mptsas_alloc_post_queue(mptsas_t *mpt)
2884 {
2885 ddi_dma_attr_t frame_dma_attrs;
2886 caddr_t memp;
2887 ddi_dma_cookie_t cookie;
2888 size_t mem_size;
2889
2890 /*
2891 * re-alloc when it has already alloced
2892 */
2893 if (mpt->m_dma_post_queue_hdl) {
2894 mptsas_dma_addr_destroy(&mpt->m_dma_post_queue_hdl,
2895 &mpt->m_acc_post_queue_hdl);
2896 }
2897
2898 /*
2899 * The reply descriptor post queue size is:
2900 * Reply Descriptor Post Queue Depth * 8
2901 * The "8" is the size of each descriptor (8 bytes or 64 bits).
2902 */
2903 mem_size = mpt->m_post_queue_depth * 8;
2904
2905 /*
2906 * set the DMA attributes. The Reply Descriptor Post Queue must be
2907 * aligned on a 16-byte boundry.
2908 */
2909 frame_dma_attrs = mpt->m_msg_dma_attr;
2910 frame_dma_attrs.dma_attr_align = 16;
2911 frame_dma_attrs.dma_attr_sgllen = 1;
2912
2913 /*
2914 * allocate the reply post queue
2915 */
2916 if (mptsas_dma_addr_create(mpt, frame_dma_attrs,
2917 &mpt->m_dma_post_queue_hdl, &mpt->m_acc_post_queue_hdl, &memp,
2918 mem_size, &cookie) == FALSE) {
2919 return (DDI_FAILURE);
2920 }
2921
2922 /*
2923 * Store the reply descriptor post queue memory address. This chip
2924 * uses this address to write to the reply descriptor post queue. The
2925 * second address is the address mpt uses to manage the queue.
2926 */
2927 mpt->m_post_queue_dma_addr = cookie.dmac_laddress;
2928 mpt->m_post_queue = memp;
2929
2930 /*
2931 * Clear the reply post queue memory.
2932 */
2933 bzero(mpt->m_post_queue, mem_size);
2934
2935 return (DDI_SUCCESS);
2936 }
2937
2938 static void
mptsas_alloc_reply_args(mptsas_t * mpt)2939 mptsas_alloc_reply_args(mptsas_t *mpt)
2940 {
2941 if (mpt->m_replyh_args == NULL) {
2942 mpt->m_replyh_args = kmem_zalloc(sizeof (m_replyh_arg_t) *
2943 mpt->m_max_replies, KM_SLEEP);
2944 }
2945 }
2946
2947 static int
mptsas_alloc_extra_sgl_frame(mptsas_t * mpt,mptsas_cmd_t * cmd)2948 mptsas_alloc_extra_sgl_frame(mptsas_t *mpt, mptsas_cmd_t *cmd)
2949 {
2950 mptsas_cache_frames_t *frames = NULL;
2951 if (cmd->cmd_extra_frames == NULL) {
2952 frames = kmem_cache_alloc(mpt->m_cache_frames, KM_NOSLEEP);
2953 if (frames == NULL) {
2954 return (DDI_FAILURE);
2955 }
2956 cmd->cmd_extra_frames = frames;
2957 }
2958 return (DDI_SUCCESS);
2959 }
2960
2961 static void
mptsas_free_extra_sgl_frame(mptsas_t * mpt,mptsas_cmd_t * cmd)2962 mptsas_free_extra_sgl_frame(mptsas_t *mpt, mptsas_cmd_t *cmd)
2963 {
2964 if (cmd->cmd_extra_frames) {
2965 kmem_cache_free(mpt->m_cache_frames,
2966 (void *)cmd->cmd_extra_frames);
2967 cmd->cmd_extra_frames = NULL;
2968 }
2969 }
2970
2971 static void
mptsas_cfg_fini(mptsas_t * mpt)2972 mptsas_cfg_fini(mptsas_t *mpt)
2973 {
2974 NDBG0(("mptsas_cfg_fini"));
2975 ddi_regs_map_free(&mpt->m_datap);
2976 }
2977
2978 static void
mptsas_hba_fini(mptsas_t * mpt)2979 mptsas_hba_fini(mptsas_t *mpt)
2980 {
2981 NDBG0(("mptsas_hba_fini"));
2982
2983 /*
2984 * Free up any allocated memory
2985 */
2986 if (mpt->m_dma_req_frame_hdl) {
2987 mptsas_dma_addr_destroy(&mpt->m_dma_req_frame_hdl,
2988 &mpt->m_acc_req_frame_hdl);
2989 }
2990
2991 if (mpt->m_dma_req_sense_hdl) {
2992 rmfreemap(mpt->m_erqsense_map);
2993 mptsas_dma_addr_destroy(&mpt->m_dma_req_sense_hdl,
2994 &mpt->m_acc_req_sense_hdl);
2995 }
2996
2997 if (mpt->m_dma_reply_frame_hdl) {
2998 mptsas_dma_addr_destroy(&mpt->m_dma_reply_frame_hdl,
2999 &mpt->m_acc_reply_frame_hdl);
3000 }
3001
3002 if (mpt->m_dma_free_queue_hdl) {
3003 mptsas_dma_addr_destroy(&mpt->m_dma_free_queue_hdl,
3004 &mpt->m_acc_free_queue_hdl);
3005 }
3006
3007 if (mpt->m_dma_post_queue_hdl) {
3008 mptsas_dma_addr_destroy(&mpt->m_dma_post_queue_hdl,
3009 &mpt->m_acc_post_queue_hdl);
3010 }
3011
3012 if (mpt->m_replyh_args != NULL) {
3013 kmem_free(mpt->m_replyh_args, sizeof (m_replyh_arg_t)
3014 * mpt->m_max_replies);
3015 }
3016 }
3017
3018 static int
mptsas_name_child(dev_info_t * lun_dip,char * name,int len)3019 mptsas_name_child(dev_info_t *lun_dip, char *name, int len)
3020 {
3021 int lun = 0;
3022 char *sas_wwn = NULL;
3023 int phynum = -1;
3024 int reallen = 0;
3025
3026 /* Get the target num */
3027 lun = ddi_prop_get_int(DDI_DEV_T_ANY, lun_dip, DDI_PROP_DONTPASS,
3028 LUN_PROP, 0);
3029
3030 if ((phynum = ddi_prop_get_int(DDI_DEV_T_ANY, lun_dip,
3031 DDI_PROP_DONTPASS, "sata-phy", -1)) != -1) {
3032 /*
3033 * Stick in the address of form "pPHY,LUN"
3034 */
3035 reallen = snprintf(name, len, "p%x,%x", phynum, lun);
3036 } else if (ddi_prop_lookup_string(DDI_DEV_T_ANY, lun_dip,
3037 DDI_PROP_DONTPASS, SCSI_ADDR_PROP_TARGET_PORT, &sas_wwn)
3038 == DDI_PROP_SUCCESS) {
3039 /*
3040 * Stick in the address of the form "wWWN,LUN"
3041 */
3042 reallen = snprintf(name, len, "%s,%x", sas_wwn, lun);
3043 ddi_prop_free(sas_wwn);
3044 } else {
3045 return (DDI_FAILURE);
3046 }
3047
3048 ASSERT(reallen < len);
3049 if (reallen >= len) {
3050 mptsas_log(0, CE_WARN, "!mptsas_get_name: name parameter "
3051 "length too small, it needs to be %d bytes", reallen + 1);
3052 }
3053 return (DDI_SUCCESS);
3054 }
3055
3056 /*
3057 * tran_tgt_init(9E) - target device instance initialization
3058 */
3059 static int
mptsas_scsi_tgt_init(dev_info_t * hba_dip,dev_info_t * tgt_dip,scsi_hba_tran_t * hba_tran,struct scsi_device * sd)3060 mptsas_scsi_tgt_init(dev_info_t *hba_dip, dev_info_t *tgt_dip,
3061 scsi_hba_tran_t *hba_tran, struct scsi_device *sd)
3062 {
3063 #ifndef __lock_lint
3064 _NOTE(ARGUNUSED(hba_tran))
3065 #endif
3066
3067 /*
3068 * At this point, the scsi_device structure already exists
3069 * and has been initialized.
3070 *
3071 * Use this function to allocate target-private data structures,
3072 * if needed by this HBA. Add revised flow-control and queue
3073 * properties for child here, if desired and if you can tell they
3074 * support tagged queueing by now.
3075 */
3076 mptsas_t *mpt;
3077 int lun = sd->sd_address.a_lun;
3078 mdi_pathinfo_t *pip = NULL;
3079 mptsas_tgt_private_t *tgt_private = NULL;
3080 mptsas_target_t *ptgt = NULL;
3081 char *psas_wwn = NULL;
3082 mptsas_phymask_t phymask = 0;
3083 uint64_t sas_wwn = 0;
3084 mptsas_target_addr_t addr;
3085 mpt = SDEV2MPT(sd);
3086
3087 ASSERT(scsi_hba_iport_unit_address(hba_dip) != 0);
3088
3089 NDBG0(("mptsas_scsi_tgt_init: hbadip=0x%p tgtdip=0x%p lun=%d",
3090 (void *)hba_dip, (void *)tgt_dip, lun));
3091
3092 if (ndi_dev_is_persistent_node(tgt_dip) == 0) {
3093 (void) ndi_merge_node(tgt_dip, mptsas_name_child);
3094 ddi_set_name_addr(tgt_dip, NULL);
3095 return (DDI_FAILURE);
3096 }
3097 /*
3098 * phymask is 0 means the virtual port for RAID
3099 */
3100 phymask = (mptsas_phymask_t)ddi_prop_get_int(DDI_DEV_T_ANY, hba_dip, 0,
3101 "phymask", 0);
3102 if (mdi_component_is_client(tgt_dip, NULL) == MDI_SUCCESS) {
3103 if ((pip = (void *)(sd->sd_private)) == NULL) {
3104 /*
3105 * Very bad news if this occurs. Somehow scsi_vhci has
3106 * lost the pathinfo node for this target.
3107 */
3108 return (DDI_NOT_WELL_FORMED);
3109 }
3110
3111 if (mdi_prop_lookup_int(pip, LUN_PROP, &lun) !=
3112 DDI_PROP_SUCCESS) {
3113 mptsas_log(mpt, CE_WARN, "Get lun property failed\n");
3114 return (DDI_FAILURE);
3115 }
3116
3117 if (mdi_prop_lookup_string(pip, SCSI_ADDR_PROP_TARGET_PORT,
3118 &psas_wwn) == MDI_SUCCESS) {
3119 if (scsi_wwnstr_to_wwn(psas_wwn, &sas_wwn)) {
3120 sas_wwn = 0;
3121 }
3122 (void) mdi_prop_free(psas_wwn);
3123 }
3124 } else {
3125 lun = ddi_prop_get_int(DDI_DEV_T_ANY, tgt_dip,
3126 DDI_PROP_DONTPASS, LUN_PROP, 0);
3127 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, tgt_dip,
3128 DDI_PROP_DONTPASS, SCSI_ADDR_PROP_TARGET_PORT, &psas_wwn) ==
3129 DDI_PROP_SUCCESS) {
3130 if (scsi_wwnstr_to_wwn(psas_wwn, &sas_wwn)) {
3131 sas_wwn = 0;
3132 }
3133 ddi_prop_free(psas_wwn);
3134 } else {
3135 sas_wwn = 0;
3136 }
3137 }
3138
3139 ASSERT((sas_wwn != 0) || (phymask != 0));
3140 addr.mta_wwn = sas_wwn;
3141 addr.mta_phymask = phymask;
3142 mutex_enter(&mpt->m_mutex);
3143 ptgt = refhash_lookup(mpt->m_targets, &addr);
3144 mutex_exit(&mpt->m_mutex);
3145 if (ptgt == NULL) {
3146 mptsas_log(mpt, CE_WARN, "!tgt_init: target doesn't exist or "
3147 "gone already! phymask:%x, saswwn %"PRIx64, phymask,
3148 sas_wwn);
3149 return (DDI_FAILURE);
3150 }
3151 if (hba_tran->tran_tgt_private == NULL) {
3152 tgt_private = kmem_zalloc(sizeof (mptsas_tgt_private_t),
3153 KM_SLEEP);
3154 tgt_private->t_lun = lun;
3155 tgt_private->t_private = ptgt;
3156 hba_tran->tran_tgt_private = tgt_private;
3157 }
3158
3159 if (mdi_component_is_client(tgt_dip, NULL) == MDI_SUCCESS) {
3160 return (DDI_SUCCESS);
3161 }
3162 mutex_enter(&mpt->m_mutex);
3163
3164 if (ptgt->m_deviceinfo &
3165 (MPI2_SAS_DEVICE_INFO_SATA_DEVICE |
3166 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) {
3167 uchar_t *inq89 = NULL;
3168 int inq89_len = 0x238;
3169 int reallen = 0;
3170 int rval = 0;
3171 struct sata_id *sid = NULL;
3172 char model[SATA_ID_MODEL_LEN + 1];
3173 char fw[SATA_ID_FW_LEN + 1];
3174 char *vid, *pid;
3175
3176 mutex_exit(&mpt->m_mutex);
3177 /*
3178 * According SCSI/ATA Translation -2 (SAT-2) revision 01a
3179 * chapter 12.4.2 VPD page 89h includes 512 bytes ATA IDENTIFY
3180 * DEVICE data or ATA IDENTIFY PACKET DEVICE data.
3181 */
3182 inq89 = kmem_zalloc(inq89_len, KM_SLEEP);
3183 rval = mptsas_inquiry(mpt, ptgt, 0, 0x89,
3184 inq89, inq89_len, &reallen, 1);
3185
3186 if (rval != 0) {
3187 if (inq89 != NULL) {
3188 kmem_free(inq89, inq89_len);
3189 }
3190
3191 mptsas_log(mpt, CE_WARN, "!mptsas request inquiry page "
3192 "0x89 for SATA target:%x failed!", ptgt->m_devhdl);
3193 return (DDI_SUCCESS);
3194 }
3195 sid = (void *)(&inq89[60]);
3196
3197 swab(sid->ai_model, model, SATA_ID_MODEL_LEN);
3198 swab(sid->ai_fw, fw, SATA_ID_FW_LEN);
3199
3200 model[SATA_ID_MODEL_LEN] = 0;
3201 fw[SATA_ID_FW_LEN] = 0;
3202
3203 sata_split_model(model, &vid, &pid);
3204
3205 /*
3206 * override SCSA "inquiry-*" properties
3207 */
3208 if (vid)
3209 (void) scsi_device_prop_update_inqstring(sd,
3210 INQUIRY_VENDOR_ID, vid, strlen(vid));
3211 if (pid)
3212 (void) scsi_device_prop_update_inqstring(sd,
3213 INQUIRY_PRODUCT_ID, pid, strlen(pid));
3214 (void) scsi_device_prop_update_inqstring(sd,
3215 INQUIRY_REVISION_ID, fw, strlen(fw));
3216
3217 if (inq89 != NULL) {
3218 kmem_free(inq89, inq89_len);
3219 }
3220 } else {
3221 mutex_exit(&mpt->m_mutex);
3222 }
3223
3224 return (DDI_SUCCESS);
3225 }
3226 /*
3227 * tran_tgt_free(9E) - target device instance deallocation
3228 */
3229 static void
mptsas_scsi_tgt_free(dev_info_t * hba_dip,dev_info_t * tgt_dip,scsi_hba_tran_t * hba_tran,struct scsi_device * sd)3230 mptsas_scsi_tgt_free(dev_info_t *hba_dip, dev_info_t *tgt_dip,
3231 scsi_hba_tran_t *hba_tran, struct scsi_device *sd)
3232 {
3233 #ifndef __lock_lint
3234 _NOTE(ARGUNUSED(hba_dip, tgt_dip, hba_tran, sd))
3235 #endif
3236
3237 mptsas_tgt_private_t *tgt_private = hba_tran->tran_tgt_private;
3238
3239 if (tgt_private != NULL) {
3240 kmem_free(tgt_private, sizeof (mptsas_tgt_private_t));
3241 hba_tran->tran_tgt_private = NULL;
3242 }
3243 }
3244
3245 /*
3246 * scsi_pkt handling
3247 *
3248 * Visible to the external world via the transport structure.
3249 */
3250
3251 /*
3252 * Notes:
3253 * - transport the command to the addressed SCSI target/lun device
3254 * - normal operation is to schedule the command to be transported,
3255 * and return TRAN_ACCEPT if this is successful.
3256 * - if NO_INTR, tran_start must poll device for command completion
3257 */
3258 static int
mptsas_scsi_start(struct scsi_address * ap,struct scsi_pkt * pkt)3259 mptsas_scsi_start(struct scsi_address *ap, struct scsi_pkt *pkt)
3260 {
3261 #ifndef __lock_lint
3262 _NOTE(ARGUNUSED(ap))
3263 #endif
3264 mptsas_t *mpt = PKT2MPT(pkt);
3265 mptsas_cmd_t *cmd = PKT2CMD(pkt);
3266 int rval;
3267 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
3268
3269 NDBG1(("mptsas_scsi_start: pkt=0x%p", (void *)pkt));
3270 ASSERT(ptgt);
3271 if (ptgt == NULL)
3272 return (TRAN_FATAL_ERROR);
3273
3274 /*
3275 * prepare the pkt before taking mutex.
3276 */
3277 rval = mptsas_prepare_pkt(cmd);
3278 if (rval != TRAN_ACCEPT) {
3279 return (rval);
3280 }
3281
3282 /*
3283 * Send the command to target/lun, however your HBA requires it.
3284 * If busy, return TRAN_BUSY; if there's some other formatting error
3285 * in the packet, return TRAN_BADPKT; otherwise, fall through to the
3286 * return of TRAN_ACCEPT.
3287 *
3288 * Remember that access to shared resources, including the mptsas_t
3289 * data structure and the HBA hardware registers, must be protected
3290 * with mutexes, here and everywhere.
3291 *
3292 * Also remember that at interrupt time, you'll get an argument
3293 * to the interrupt handler which is a pointer to your mptsas_t
3294 * structure; you'll have to remember which commands are outstanding
3295 * and which scsi_pkt is the currently-running command so the
3296 * interrupt handler can refer to the pkt to set completion
3297 * status, call the target driver back through pkt_comp, etc.
3298 *
3299 * If the instance lock is held by other thread, don't spin to wait
3300 * for it. Instead, queue the cmd and next time when the instance lock
3301 * is not held, accept all the queued cmd. A extra tx_waitq is
3302 * introduced to protect the queue.
3303 *
3304 * The polled cmd will not be queud and accepted as usual.
3305 *
3306 * Under the tx_waitq mutex, record whether a thread is draining
3307 * the tx_waitq. An IO requesting thread that finds the instance
3308 * mutex contended appends to the tx_waitq and while holding the
3309 * tx_wait mutex, if the draining flag is not set, sets it and then
3310 * proceeds to spin for the instance mutex. This scheme ensures that
3311 * the last cmd in a burst be processed.
3312 *
3313 * we enable this feature only when the helper threads are enabled,
3314 * at which we think the loads are heavy.
3315 *
3316 * per instance mutex m_tx_waitq_mutex is introduced to protect the
3317 * m_tx_waitqtail, m_tx_waitq, m_tx_draining.
3318 */
3319
3320 if (mpt->m_doneq_thread_n) {
3321 if (mutex_tryenter(&mpt->m_mutex) != 0) {
3322 rval = mptsas_accept_txwq_and_pkt(mpt, cmd);
3323 mutex_exit(&mpt->m_mutex);
3324 } else if (cmd->cmd_pkt_flags & FLAG_NOINTR) {
3325 mutex_enter(&mpt->m_mutex);
3326 rval = mptsas_accept_txwq_and_pkt(mpt, cmd);
3327 mutex_exit(&mpt->m_mutex);
3328 } else {
3329 mutex_enter(&mpt->m_tx_waitq_mutex);
3330 /*
3331 * ptgt->m_dr_flag is protected by m_mutex or
3332 * m_tx_waitq_mutex. In this case, m_tx_waitq_mutex
3333 * is acquired.
3334 */
3335 if (ptgt->m_dr_flag == MPTSAS_DR_INTRANSITION) {
3336 if (cmd->cmd_pkt_flags & FLAG_NOQUEUE) {
3337 /*
3338 * The command should be allowed to
3339 * retry by returning TRAN_BUSY to
3340 * to stall the I/O's which come from
3341 * scsi_vhci since the device/path is
3342 * in unstable state now.
3343 */
3344 mutex_exit(&mpt->m_tx_waitq_mutex);
3345 return (TRAN_BUSY);
3346 } else {
3347 /*
3348 * The device is offline, just fail the
3349 * command by returning
3350 * TRAN_FATAL_ERROR.
3351 */
3352 mutex_exit(&mpt->m_tx_waitq_mutex);
3353 return (TRAN_FATAL_ERROR);
3354 }
3355 }
3356 if (mpt->m_tx_draining) {
3357 cmd->cmd_flags |= CFLAG_TXQ;
3358 *mpt->m_tx_waitqtail = cmd;
3359 mpt->m_tx_waitqtail = &cmd->cmd_linkp;
3360 mutex_exit(&mpt->m_tx_waitq_mutex);
3361 } else { /* drain the queue */
3362 mpt->m_tx_draining = 1;
3363 mutex_exit(&mpt->m_tx_waitq_mutex);
3364 mutex_enter(&mpt->m_mutex);
3365 rval = mptsas_accept_txwq_and_pkt(mpt, cmd);
3366 mutex_exit(&mpt->m_mutex);
3367 }
3368 }
3369 } else {
3370 mutex_enter(&mpt->m_mutex);
3371 /*
3372 * ptgt->m_dr_flag is protected by m_mutex or m_tx_waitq_mutex
3373 * in this case, m_mutex is acquired.
3374 */
3375 if (ptgt->m_dr_flag == MPTSAS_DR_INTRANSITION) {
3376 if (cmd->cmd_pkt_flags & FLAG_NOQUEUE) {
3377 /*
3378 * commands should be allowed to retry by
3379 * returning TRAN_BUSY to stall the I/O's
3380 * which come from scsi_vhci since the device/
3381 * path is in unstable state now.
3382 */
3383 mutex_exit(&mpt->m_mutex);
3384 return (TRAN_BUSY);
3385 } else {
3386 /*
3387 * The device is offline, just fail the
3388 * command by returning TRAN_FATAL_ERROR.
3389 */
3390 mutex_exit(&mpt->m_mutex);
3391 return (TRAN_FATAL_ERROR);
3392 }
3393 }
3394 rval = mptsas_accept_pkt(mpt, cmd);
3395 mutex_exit(&mpt->m_mutex);
3396 }
3397
3398 return (rval);
3399 }
3400
3401 /*
3402 * Accept all the queued cmds(if any) before accept the current one.
3403 */
3404 static int
mptsas_accept_txwq_and_pkt(mptsas_t * mpt,mptsas_cmd_t * cmd)3405 mptsas_accept_txwq_and_pkt(mptsas_t *mpt, mptsas_cmd_t *cmd)
3406 {
3407 int rval;
3408 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
3409
3410 ASSERT(mutex_owned(&mpt->m_mutex));
3411 /*
3412 * The call to mptsas_accept_tx_waitq() must always be performed
3413 * because that is where mpt->m_tx_draining is cleared.
3414 */
3415 mutex_enter(&mpt->m_tx_waitq_mutex);
3416 mptsas_accept_tx_waitq(mpt);
3417 mutex_exit(&mpt->m_tx_waitq_mutex);
3418 /*
3419 * ptgt->m_dr_flag is protected by m_mutex or m_tx_waitq_mutex
3420 * in this case, m_mutex is acquired.
3421 */
3422 if (ptgt->m_dr_flag == MPTSAS_DR_INTRANSITION) {
3423 if (cmd->cmd_pkt_flags & FLAG_NOQUEUE) {
3424 /*
3425 * The command should be allowed to retry by returning
3426 * TRAN_BUSY to stall the I/O's which come from
3427 * scsi_vhci since the device/path is in unstable state
3428 * now.
3429 */
3430 return (TRAN_BUSY);
3431 } else {
3432 /*
3433 * The device is offline, just fail the command by
3434 * return TRAN_FATAL_ERROR.
3435 */
3436 return (TRAN_FATAL_ERROR);
3437 }
3438 }
3439 rval = mptsas_accept_pkt(mpt, cmd);
3440
3441 return (rval);
3442 }
3443
3444 static int
mptsas_accept_pkt(mptsas_t * mpt,mptsas_cmd_t * cmd)3445 mptsas_accept_pkt(mptsas_t *mpt, mptsas_cmd_t *cmd)
3446 {
3447 int rval = TRAN_ACCEPT;
3448 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
3449
3450 NDBG1(("mptsas_accept_pkt: cmd=0x%p", (void *)cmd));
3451
3452 ASSERT(mutex_owned(&mpt->m_mutex));
3453
3454 if ((cmd->cmd_flags & CFLAG_PREPARED) == 0) {
3455 rval = mptsas_prepare_pkt(cmd);
3456 if (rval != TRAN_ACCEPT) {
3457 cmd->cmd_flags &= ~CFLAG_TRANFLAG;
3458 return (rval);
3459 }
3460 }
3461
3462 /*
3463 * reset the throttle if we were draining
3464 */
3465 if ((ptgt->m_t_ncmds == 0) &&
3466 (ptgt->m_t_throttle == DRAIN_THROTTLE)) {
3467 NDBG23(("reset throttle"));
3468 ASSERT(ptgt->m_reset_delay == 0);
3469 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE);
3470 }
3471
3472 /*
3473 * If HBA is being reset, the DevHandles are being re-initialized,
3474 * which means that they could be invalid even if the target is still
3475 * attached. Check if being reset and if DevHandle is being
3476 * re-initialized. If this is the case, return BUSY so the I/O can be
3477 * retried later.
3478 */
3479 if ((ptgt->m_devhdl == MPTSAS_INVALID_DEVHDL) && mpt->m_in_reset) {
3480 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET, STAT_BUS_RESET);
3481 if (cmd->cmd_flags & CFLAG_TXQ) {
3482 mptsas_doneq_add(mpt, cmd);
3483 mptsas_doneq_empty(mpt);
3484 return (rval);
3485 } else {
3486 return (TRAN_BUSY);
3487 }
3488 }
3489
3490 /*
3491 * If device handle has already been invalidated, just
3492 * fail the command. In theory, command from scsi_vhci
3493 * client is impossible send down command with invalid
3494 * devhdl since devhdl is set after path offline, target
3495 * driver is not suppose to select a offlined path.
3496 */
3497 if (ptgt->m_devhdl == MPTSAS_INVALID_DEVHDL) {
3498 NDBG3(("rejecting command, it might because invalid devhdl "
3499 "request."));
3500 mptsas_set_pkt_reason(mpt, cmd, CMD_DEV_GONE, STAT_TERMINATED);
3501 if (cmd->cmd_flags & CFLAG_TXQ) {
3502 mptsas_doneq_add(mpt, cmd);
3503 mptsas_doneq_empty(mpt);
3504 return (rval);
3505 } else {
3506 return (TRAN_FATAL_ERROR);
3507 }
3508 }
3509 /*
3510 * The first case is the normal case. mpt gets a command from the
3511 * target driver and starts it.
3512 * Since SMID 0 is reserved and the TM slot is reserved, the actual max
3513 * commands is m_max_requests - 2.
3514 */
3515 if ((mpt->m_ncmds <= (mpt->m_max_requests - 2)) &&
3516 (ptgt->m_t_throttle > HOLD_THROTTLE) &&
3517 (ptgt->m_t_ncmds < ptgt->m_t_throttle) &&
3518 (ptgt->m_reset_delay == 0) &&
3519 (ptgt->m_t_nwait == 0) &&
3520 ((cmd->cmd_pkt_flags & FLAG_NOINTR) == 0)) {
3521 if (mptsas_save_cmd(mpt, cmd) == TRUE) {
3522 (void) mptsas_start_cmd(mpt, cmd);
3523 } else {
3524 mptsas_waitq_add(mpt, cmd);
3525 }
3526 } else {
3527 /*
3528 * Add this pkt to the work queue
3529 */
3530 mptsas_waitq_add(mpt, cmd);
3531
3532 if (cmd->cmd_pkt_flags & FLAG_NOINTR) {
3533 (void) mptsas_poll(mpt, cmd, MPTSAS_POLL_TIME);
3534
3535 /*
3536 * Only flush the doneq if this is not a TM
3537 * cmd. For TM cmds the flushing of the
3538 * doneq will be done in those routines.
3539 */
3540 if ((cmd->cmd_flags & CFLAG_TM_CMD) == 0) {
3541 mptsas_doneq_empty(mpt);
3542 }
3543 }
3544 }
3545 return (rval);
3546 }
3547
3548 int
mptsas_save_cmd(mptsas_t * mpt,mptsas_cmd_t * cmd)3549 mptsas_save_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd)
3550 {
3551 mptsas_slots_t *slots = mpt->m_active;
3552 uint_t slot, start_rotor;
3553 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
3554
3555 ASSERT(MUTEX_HELD(&mpt->m_mutex));
3556
3557 /*
3558 * Account for reserved TM request slot and reserved SMID of 0.
3559 */
3560 ASSERT(slots->m_n_normal == (mpt->m_max_requests - 2));
3561
3562 /*
3563 * Find the next available slot, beginning at m_rotor. If no slot is
3564 * available, we'll return FALSE to indicate that. This mechanism
3565 * considers only the normal slots, not the reserved slot 0 nor the
3566 * task management slot m_n_normal + 1. The rotor is left to point to
3567 * the normal slot after the one we select, unless we select the last
3568 * normal slot in which case it returns to slot 1.
3569 */
3570 start_rotor = slots->m_rotor;
3571 do {
3572 slot = slots->m_rotor++;
3573 if (slots->m_rotor > slots->m_n_normal)
3574 slots->m_rotor = 1;
3575
3576 if (slots->m_rotor == start_rotor)
3577 break;
3578 } while (slots->m_slot[slot] != NULL);
3579
3580 if (slots->m_slot[slot] != NULL)
3581 return (FALSE);
3582
3583 ASSERT(slot != 0 && slot <= slots->m_n_normal);
3584
3585 cmd->cmd_slot = slot;
3586 slots->m_slot[slot] = cmd;
3587 mpt->m_ncmds++;
3588
3589 /*
3590 * only increment per target ncmds if this is not a
3591 * command that has no target associated with it (i.e. a
3592 * event acknoledgment)
3593 */
3594 if ((cmd->cmd_flags & CFLAG_CMDIOC) == 0) {
3595 /*
3596 * Expiration time is set in mptsas_start_cmd
3597 */
3598 ptgt->m_t_ncmds++;
3599 cmd->cmd_active_expiration = 0;
3600 } else {
3601 /*
3602 * Initialize expiration time for passthrough commands,
3603 */
3604 cmd->cmd_active_expiration = gethrtime() +
3605 (hrtime_t)cmd->cmd_pkt->pkt_time * NANOSEC;
3606 }
3607 return (TRUE);
3608 }
3609
3610 /*
3611 * prepare the pkt:
3612 * the pkt may have been resubmitted or just reused so
3613 * initialize some fields and do some checks.
3614 */
3615 static int
mptsas_prepare_pkt(mptsas_cmd_t * cmd)3616 mptsas_prepare_pkt(mptsas_cmd_t *cmd)
3617 {
3618 struct scsi_pkt *pkt = CMD2PKT(cmd);
3619
3620 NDBG1(("mptsas_prepare_pkt: cmd=0x%p", (void *)cmd));
3621
3622 /*
3623 * Reinitialize some fields that need it; the packet may
3624 * have been resubmitted
3625 */
3626 pkt->pkt_reason = CMD_CMPLT;
3627 pkt->pkt_state = 0;
3628 pkt->pkt_statistics = 0;
3629 pkt->pkt_resid = 0;
3630 cmd->cmd_age = 0;
3631 cmd->cmd_pkt_flags = pkt->pkt_flags;
3632
3633 /*
3634 * zero status byte.
3635 */
3636 *(pkt->pkt_scbp) = 0;
3637
3638 if (cmd->cmd_flags & CFLAG_DMAVALID) {
3639 pkt->pkt_resid = cmd->cmd_dmacount;
3640
3641 /*
3642 * consistent packets need to be sync'ed first
3643 * (only for data going out)
3644 */
3645 if ((cmd->cmd_flags & CFLAG_CMDIOPB) &&
3646 (cmd->cmd_flags & CFLAG_DMASEND)) {
3647 (void) ddi_dma_sync(cmd->cmd_dmahandle, 0, 0,
3648 DDI_DMA_SYNC_FORDEV);
3649 }
3650 }
3651
3652 cmd->cmd_flags =
3653 (cmd->cmd_flags & ~(CFLAG_TRANFLAG)) |
3654 CFLAG_PREPARED | CFLAG_IN_TRANSPORT;
3655
3656 return (TRAN_ACCEPT);
3657 }
3658
3659 /*
3660 * tran_init_pkt(9E) - allocate scsi_pkt(9S) for command
3661 *
3662 * One of three possibilities:
3663 * - allocate scsi_pkt
3664 * - allocate scsi_pkt and DMA resources
3665 * - allocate DMA resources to an already-allocated pkt
3666 */
3667 static struct scsi_pkt *
mptsas_scsi_init_pkt(struct scsi_address * ap,struct scsi_pkt * pkt,struct buf * bp,int cmdlen,int statuslen,int tgtlen,int flags,int (* callback)(),caddr_t arg)3668 mptsas_scsi_init_pkt(struct scsi_address *ap, struct scsi_pkt *pkt,
3669 struct buf *bp, int cmdlen, int statuslen, int tgtlen, int flags,
3670 int (*callback)(), caddr_t arg)
3671 {
3672 mptsas_cmd_t *cmd, *new_cmd;
3673 mptsas_t *mpt = ADDR2MPT(ap);
3674 uint_t oldcookiec;
3675 mptsas_target_t *ptgt = NULL;
3676 int rval;
3677 mptsas_tgt_private_t *tgt_private;
3678 int kf;
3679
3680 kf = (callback == SLEEP_FUNC)? KM_SLEEP: KM_NOSLEEP;
3681
3682 tgt_private = (mptsas_tgt_private_t *)ap->a_hba_tran->
3683 tran_tgt_private;
3684 ASSERT(tgt_private != NULL);
3685 if (tgt_private == NULL) {
3686 return (NULL);
3687 }
3688 ptgt = tgt_private->t_private;
3689 ASSERT(ptgt != NULL);
3690 if (ptgt == NULL)
3691 return (NULL);
3692 ap->a_target = ptgt->m_devhdl;
3693 ap->a_lun = tgt_private->t_lun;
3694
3695 ASSERT(callback == NULL_FUNC || callback == SLEEP_FUNC);
3696 #ifdef MPTSAS_TEST_EXTRN_ALLOC
3697 statuslen *= 100; tgtlen *= 4;
3698 #endif
3699 NDBG3(("mptsas_scsi_init_pkt:\n"
3700 "\ttgt=%d in=0x%p bp=0x%p clen=%d slen=%d tlen=%d flags=%x",
3701 ap->a_target, (void *)pkt, (void *)bp,
3702 cmdlen, statuslen, tgtlen, flags));
3703
3704 /*
3705 * Allocate the new packet.
3706 */
3707 if (pkt == NULL) {
3708 ddi_dma_handle_t save_dma_handle;
3709
3710 cmd = kmem_cache_alloc(mpt->m_kmem_cache, kf);
3711 if (cmd == NULL)
3712 return (NULL);
3713
3714 save_dma_handle = cmd->cmd_dmahandle;
3715 bzero(cmd, sizeof (*cmd) + scsi_pkt_size());
3716 cmd->cmd_dmahandle = save_dma_handle;
3717
3718 pkt = (void *)((uchar_t *)cmd +
3719 sizeof (struct mptsas_cmd));
3720 pkt->pkt_ha_private = (opaque_t)cmd;
3721 pkt->pkt_address = *ap;
3722 pkt->pkt_private = (opaque_t)cmd->cmd_pkt_private;
3723 pkt->pkt_scbp = (opaque_t)&cmd->cmd_scb;
3724 pkt->pkt_cdbp = (opaque_t)&cmd->cmd_cdb;
3725 cmd->cmd_pkt = (struct scsi_pkt *)pkt;
3726 cmd->cmd_cdblen = (uchar_t)cmdlen;
3727 cmd->cmd_scblen = statuslen;
3728 cmd->cmd_rqslen = SENSE_LENGTH;
3729 cmd->cmd_tgt_addr = ptgt;
3730
3731 if ((cmdlen > sizeof (cmd->cmd_cdb)) ||
3732 (tgtlen > PKT_PRIV_LEN) ||
3733 (statuslen > EXTCMDS_STATUS_SIZE)) {
3734 int failure;
3735
3736 /*
3737 * We are going to allocate external packet space which
3738 * might include the sense data buffer for DMA so we
3739 * need to increase the reference counter here. In a
3740 * case the HBA is in reset we just simply free the
3741 * allocated packet and bail out.
3742 */
3743 mutex_enter(&mpt->m_mutex);
3744 if (mpt->m_in_reset) {
3745 mutex_exit(&mpt->m_mutex);
3746
3747 cmd->cmd_flags = CFLAG_FREE;
3748 kmem_cache_free(mpt->m_kmem_cache, cmd);
3749 return (NULL);
3750 }
3751 mpt->m_extreq_sense_refcount++;
3752 ASSERT(mpt->m_extreq_sense_refcount > 0);
3753 mutex_exit(&mpt->m_mutex);
3754
3755 /*
3756 * if extern alloc fails, all will be
3757 * deallocated, including cmd
3758 */
3759 failure = mptsas_pkt_alloc_extern(mpt, cmd,
3760 cmdlen, tgtlen, statuslen, kf);
3761
3762 if (failure != 0 || cmd->cmd_extrqslen == 0) {
3763 /*
3764 * If the external packet space allocation
3765 * failed, or we didn't allocate the sense
3766 * data buffer for DMA we need to decrease the
3767 * reference counter.
3768 */
3769 mutex_enter(&mpt->m_mutex);
3770 ASSERT(mpt->m_extreq_sense_refcount > 0);
3771 mpt->m_extreq_sense_refcount--;
3772 if (mpt->m_extreq_sense_refcount == 0)
3773 cv_broadcast(
3774 &mpt->m_extreq_sense_refcount_cv);
3775 mutex_exit(&mpt->m_mutex);
3776
3777 if (failure != 0) {
3778 /*
3779 * if extern allocation fails, it will
3780 * deallocate the new pkt as well
3781 */
3782 return (NULL);
3783 }
3784 }
3785 }
3786 new_cmd = cmd;
3787
3788 } else {
3789 cmd = PKT2CMD(pkt);
3790 new_cmd = NULL;
3791 }
3792
3793
3794 /* grab cmd->cmd_cookiec here as oldcookiec */
3795
3796 oldcookiec = cmd->cmd_cookiec;
3797
3798 /*
3799 * If the dma was broken up into PARTIAL transfers cmd_nwin will be
3800 * greater than 0 and we'll need to grab the next dma window
3801 */
3802 /*
3803 * SLM-not doing extra command frame right now; may add later
3804 */
3805
3806 if (cmd->cmd_nwin > 0) {
3807
3808 /*
3809 * Make sure we havn't gone past the the total number
3810 * of windows
3811 */
3812 if (++cmd->cmd_winindex >= cmd->cmd_nwin) {
3813 return (NULL);
3814 }
3815 if (ddi_dma_getwin(cmd->cmd_dmahandle, cmd->cmd_winindex,
3816 &cmd->cmd_dma_offset, &cmd->cmd_dma_len,
3817 &cmd->cmd_cookie, &cmd->cmd_cookiec) == DDI_FAILURE) {
3818 return (NULL);
3819 }
3820 goto get_dma_cookies;
3821 }
3822
3823
3824 if (flags & PKT_XARQ) {
3825 cmd->cmd_flags |= CFLAG_XARQ;
3826 }
3827
3828 /*
3829 * DMA resource allocation. This version assumes your
3830 * HBA has some sort of bus-mastering or onboard DMA capability, with a
3831 * scatter-gather list of length MPTSAS_MAX_DMA_SEGS, as given in the
3832 * ddi_dma_attr_t structure and passed to scsi_impl_dmaget.
3833 */
3834 if (bp && (bp->b_bcount != 0) &&
3835 (cmd->cmd_flags & CFLAG_DMAVALID) == 0) {
3836
3837 int cnt, dma_flags;
3838 mptti_t *dmap; /* ptr to the S/G list */
3839
3840 /*
3841 * Set up DMA memory and position to the next DMA segment.
3842 */
3843 ASSERT(cmd->cmd_dmahandle != NULL);
3844
3845 if (bp->b_flags & B_READ) {
3846 dma_flags = DDI_DMA_READ;
3847 cmd->cmd_flags &= ~CFLAG_DMASEND;
3848 } else {
3849 dma_flags = DDI_DMA_WRITE;
3850 cmd->cmd_flags |= CFLAG_DMASEND;
3851 }
3852 if (flags & PKT_CONSISTENT) {
3853 cmd->cmd_flags |= CFLAG_CMDIOPB;
3854 dma_flags |= DDI_DMA_CONSISTENT;
3855 }
3856
3857 if (flags & PKT_DMA_PARTIAL) {
3858 dma_flags |= DDI_DMA_PARTIAL;
3859 }
3860
3861 /*
3862 * workaround for byte hole issue on psycho and
3863 * schizo pre 2.1
3864 */
3865 if ((bp->b_flags & B_READ) && ((bp->b_flags &
3866 (B_PAGEIO|B_REMAPPED)) != B_PAGEIO) &&
3867 ((uintptr_t)bp->b_un.b_addr & 0x7)) {
3868 dma_flags |= DDI_DMA_CONSISTENT;
3869 }
3870
3871 rval = ddi_dma_buf_bind_handle(cmd->cmd_dmahandle, bp,
3872 dma_flags, callback, arg,
3873 &cmd->cmd_cookie, &cmd->cmd_cookiec);
3874 if (rval == DDI_DMA_PARTIAL_MAP) {
3875 (void) ddi_dma_numwin(cmd->cmd_dmahandle,
3876 &cmd->cmd_nwin);
3877 cmd->cmd_winindex = 0;
3878 (void) ddi_dma_getwin(cmd->cmd_dmahandle,
3879 cmd->cmd_winindex, &cmd->cmd_dma_offset,
3880 &cmd->cmd_dma_len, &cmd->cmd_cookie,
3881 &cmd->cmd_cookiec);
3882 } else if (rval && (rval != DDI_DMA_MAPPED)) {
3883 switch (rval) {
3884 case DDI_DMA_NORESOURCES:
3885 bioerror(bp, 0);
3886 break;
3887 case DDI_DMA_BADATTR:
3888 case DDI_DMA_NOMAPPING:
3889 bioerror(bp, EFAULT);
3890 break;
3891 case DDI_DMA_TOOBIG:
3892 default:
3893 bioerror(bp, EINVAL);
3894 break;
3895 }
3896 cmd->cmd_flags &= ~CFLAG_DMAVALID;
3897 if (new_cmd) {
3898 mptsas_scsi_destroy_pkt(ap, pkt);
3899 }
3900 return ((struct scsi_pkt *)NULL);
3901 }
3902
3903 get_dma_cookies:
3904 cmd->cmd_flags |= CFLAG_DMAVALID;
3905 ASSERT(cmd->cmd_cookiec > 0);
3906
3907 if (cmd->cmd_cookiec > MPTSAS_MAX_CMD_SEGS) {
3908 mptsas_log(mpt, CE_NOTE, "large cookiec received %d\n",
3909 cmd->cmd_cookiec);
3910 bioerror(bp, EINVAL);
3911 if (new_cmd) {
3912 mptsas_scsi_destroy_pkt(ap, pkt);
3913 }
3914 return ((struct scsi_pkt *)NULL);
3915 }
3916
3917 /*
3918 * Allocate extra SGL buffer if needed.
3919 */
3920 if ((cmd->cmd_cookiec > MPTSAS_MAX_FRAME_SGES64(mpt)) &&
3921 (cmd->cmd_extra_frames == NULL)) {
3922 if (mptsas_alloc_extra_sgl_frame(mpt, cmd) ==
3923 DDI_FAILURE) {
3924 mptsas_log(mpt, CE_WARN, "MPT SGL mem alloc "
3925 "failed");
3926 bioerror(bp, ENOMEM);
3927 if (new_cmd) {
3928 mptsas_scsi_destroy_pkt(ap, pkt);
3929 }
3930 return ((struct scsi_pkt *)NULL);
3931 }
3932 }
3933
3934 /*
3935 * Always use scatter-gather transfer
3936 * Use the loop below to store physical addresses of
3937 * DMA segments, from the DMA cookies, into your HBA's
3938 * scatter-gather list.
3939 * We need to ensure we have enough kmem alloc'd
3940 * for the sg entries since we are no longer using an
3941 * array inside mptsas_cmd_t.
3942 *
3943 * We check cmd->cmd_cookiec against oldcookiec so
3944 * the scatter-gather list is correctly allocated
3945 */
3946
3947 if (oldcookiec != cmd->cmd_cookiec) {
3948 if (cmd->cmd_sg != (mptti_t *)NULL) {
3949 kmem_free(cmd->cmd_sg, sizeof (mptti_t) *
3950 oldcookiec);
3951 cmd->cmd_sg = NULL;
3952 }
3953 }
3954
3955 if (cmd->cmd_sg == (mptti_t *)NULL) {
3956 cmd->cmd_sg = kmem_alloc((size_t)(sizeof (mptti_t)*
3957 cmd->cmd_cookiec), kf);
3958
3959 if (cmd->cmd_sg == (mptti_t *)NULL) {
3960 mptsas_log(mpt, CE_WARN,
3961 "unable to kmem_alloc enough memory "
3962 "for scatter/gather list");
3963 /*
3964 * if we have an ENOMEM condition we need to behave
3965 * the same way as the rest of this routine
3966 */
3967
3968 bioerror(bp, ENOMEM);
3969 if (new_cmd) {
3970 mptsas_scsi_destroy_pkt(ap, pkt);
3971 }
3972 return ((struct scsi_pkt *)NULL);
3973 }
3974 }
3975
3976 dmap = cmd->cmd_sg;
3977
3978 ASSERT(cmd->cmd_cookie.dmac_size != 0);
3979
3980 /*
3981 * store the first segment into the S/G list
3982 */
3983 dmap->count = cmd->cmd_cookie.dmac_size;
3984 dmap->addr.address64.Low = (uint32_t)
3985 (cmd->cmd_cookie.dmac_laddress & 0xffffffffull);
3986 dmap->addr.address64.High = (uint32_t)
3987 (cmd->cmd_cookie.dmac_laddress >> 32);
3988
3989 /*
3990 * dmacount counts the size of the dma for this window
3991 * (if partial dma is being used). totaldmacount
3992 * keeps track of the total amount of dma we have
3993 * transferred for all the windows (needed to calculate
3994 * the resid value below).
3995 */
3996 cmd->cmd_dmacount = cmd->cmd_cookie.dmac_size;
3997 cmd->cmd_totaldmacount += cmd->cmd_cookie.dmac_size;
3998
3999 /*
4000 * We already stored the first DMA scatter gather segment,
4001 * start at 1 if we need to store more.
4002 */
4003 for (cnt = 1; cnt < cmd->cmd_cookiec; cnt++) {
4004 /*
4005 * Get next DMA cookie
4006 */
4007 ddi_dma_nextcookie(cmd->cmd_dmahandle,
4008 &cmd->cmd_cookie);
4009 dmap++;
4010
4011 cmd->cmd_dmacount += cmd->cmd_cookie.dmac_size;
4012 cmd->cmd_totaldmacount += cmd->cmd_cookie.dmac_size;
4013
4014 /*
4015 * store the segment parms into the S/G list
4016 */
4017 dmap->count = cmd->cmd_cookie.dmac_size;
4018 dmap->addr.address64.Low = (uint32_t)
4019 (cmd->cmd_cookie.dmac_laddress & 0xffffffffull);
4020 dmap->addr.address64.High = (uint32_t)
4021 (cmd->cmd_cookie.dmac_laddress >> 32);
4022 }
4023
4024 /*
4025 * If this was partially allocated we set the resid
4026 * the amount of data NOT transferred in this window
4027 * If there is only one window, the resid will be 0
4028 */
4029 pkt->pkt_resid = (bp->b_bcount - cmd->cmd_totaldmacount);
4030 NDBG3(("mptsas_scsi_init_pkt: cmd_dmacount=%d.",
4031 cmd->cmd_dmacount));
4032 }
4033 return (pkt);
4034 }
4035
4036 /*
4037 * tran_destroy_pkt(9E) - scsi_pkt(9s) deallocation
4038 *
4039 * Notes:
4040 * - also frees DMA resources if allocated
4041 * - implicit DMA synchonization
4042 */
4043 static void
mptsas_scsi_destroy_pkt(struct scsi_address * ap,struct scsi_pkt * pkt)4044 mptsas_scsi_destroy_pkt(struct scsi_address *ap, struct scsi_pkt *pkt)
4045 {
4046 mptsas_cmd_t *cmd = PKT2CMD(pkt);
4047 mptsas_t *mpt = ADDR2MPT(ap);
4048
4049 NDBG3(("mptsas_scsi_destroy_pkt: target=%d pkt=0x%p",
4050 ap->a_target, (void *)pkt));
4051
4052 if (cmd->cmd_flags & CFLAG_DMAVALID) {
4053 (void) ddi_dma_unbind_handle(cmd->cmd_dmahandle);
4054 cmd->cmd_flags &= ~CFLAG_DMAVALID;
4055 }
4056
4057 if (cmd->cmd_sg) {
4058 kmem_free(cmd->cmd_sg, sizeof (mptti_t) * cmd->cmd_cookiec);
4059 cmd->cmd_sg = NULL;
4060 }
4061
4062 mptsas_free_extra_sgl_frame(mpt, cmd);
4063
4064 if ((cmd->cmd_flags &
4065 (CFLAG_FREE | CFLAG_CDBEXTERN | CFLAG_PRIVEXTERN |
4066 CFLAG_SCBEXTERN)) == 0) {
4067 cmd->cmd_flags = CFLAG_FREE;
4068 kmem_cache_free(mpt->m_kmem_cache, (void *)cmd);
4069 } else {
4070 boolean_t extrqslen = cmd->cmd_extrqslen != 0;
4071
4072 mptsas_pkt_destroy_extern(mpt, cmd);
4073
4074 /*
4075 * If the packet had the sense data buffer for DMA allocated we
4076 * need to decrease the reference counter.
4077 */
4078 if (extrqslen) {
4079 mutex_enter(&mpt->m_mutex);
4080 ASSERT(mpt->m_extreq_sense_refcount > 0);
4081 mpt->m_extreq_sense_refcount--;
4082 if (mpt->m_extreq_sense_refcount == 0)
4083 cv_broadcast(&mpt->m_extreq_sense_refcount_cv);
4084 mutex_exit(&mpt->m_mutex);
4085 }
4086 }
4087 }
4088
4089 /*
4090 * kmem cache constructor and destructor:
4091 * When constructing, we bzero the cmd and allocate the dma handle
4092 * When destructing, just free the dma handle
4093 */
4094 static int
mptsas_kmem_cache_constructor(void * buf,void * cdrarg,int kmflags)4095 mptsas_kmem_cache_constructor(void *buf, void *cdrarg, int kmflags)
4096 {
4097 mptsas_cmd_t *cmd = buf;
4098 mptsas_t *mpt = cdrarg;
4099 int (*callback)(caddr_t);
4100
4101 callback = (kmflags == KM_SLEEP)? DDI_DMA_SLEEP: DDI_DMA_DONTWAIT;
4102
4103 NDBG4(("mptsas_kmem_cache_constructor"));
4104
4105 /*
4106 * allocate a dma handle
4107 */
4108 if ((ddi_dma_alloc_handle(mpt->m_dip, &mpt->m_io_dma_attr, callback,
4109 NULL, &cmd->cmd_dmahandle)) != DDI_SUCCESS) {
4110 cmd->cmd_dmahandle = NULL;
4111 return (-1);
4112 }
4113 return (0);
4114 }
4115
4116 static void
mptsas_kmem_cache_destructor(void * buf,void * cdrarg)4117 mptsas_kmem_cache_destructor(void *buf, void *cdrarg)
4118 {
4119 #ifndef __lock_lint
4120 _NOTE(ARGUNUSED(cdrarg))
4121 #endif
4122 mptsas_cmd_t *cmd = buf;
4123
4124 NDBG4(("mptsas_kmem_cache_destructor"));
4125
4126 if (cmd->cmd_dmahandle) {
4127 ddi_dma_free_handle(&cmd->cmd_dmahandle);
4128 cmd->cmd_dmahandle = NULL;
4129 }
4130 }
4131
4132 static int
mptsas_cache_frames_constructor(void * buf,void * cdrarg,int kmflags)4133 mptsas_cache_frames_constructor(void *buf, void *cdrarg, int kmflags)
4134 {
4135 mptsas_cache_frames_t *p = buf;
4136 mptsas_t *mpt = cdrarg;
4137 ddi_dma_attr_t frame_dma_attr;
4138 size_t mem_size, alloc_len;
4139 ddi_dma_cookie_t cookie;
4140 uint_t ncookie;
4141 int (*callback)(caddr_t) = (kmflags == KM_SLEEP)
4142 ? DDI_DMA_SLEEP: DDI_DMA_DONTWAIT;
4143
4144 frame_dma_attr = mpt->m_msg_dma_attr;
4145 frame_dma_attr.dma_attr_align = 0x10;
4146 frame_dma_attr.dma_attr_sgllen = 1;
4147
4148 if (ddi_dma_alloc_handle(mpt->m_dip, &frame_dma_attr, callback, NULL,
4149 &p->m_dma_hdl) != DDI_SUCCESS) {
4150 mptsas_log(mpt, CE_WARN, "Unable to allocate dma handle for"
4151 " extra SGL.");
4152 return (DDI_FAILURE);
4153 }
4154
4155 mem_size = (mpt->m_max_request_frames - 1) * mpt->m_req_frame_size;
4156
4157 if (ddi_dma_mem_alloc(p->m_dma_hdl, mem_size, &mpt->m_dev_acc_attr,
4158 DDI_DMA_CONSISTENT, callback, NULL, (caddr_t *)&p->m_frames_addr,
4159 &alloc_len, &p->m_acc_hdl) != DDI_SUCCESS) {
4160 ddi_dma_free_handle(&p->m_dma_hdl);
4161 p->m_dma_hdl = NULL;
4162 mptsas_log(mpt, CE_WARN, "Unable to allocate dma memory for"
4163 " extra SGL.");
4164 return (DDI_FAILURE);
4165 }
4166
4167 if (ddi_dma_addr_bind_handle(p->m_dma_hdl, NULL, p->m_frames_addr,
4168 alloc_len, DDI_DMA_RDWR | DDI_DMA_CONSISTENT, callback, NULL,
4169 &cookie, &ncookie) != DDI_DMA_MAPPED) {
4170 (void) ddi_dma_mem_free(&p->m_acc_hdl);
4171 ddi_dma_free_handle(&p->m_dma_hdl);
4172 p->m_dma_hdl = NULL;
4173 mptsas_log(mpt, CE_WARN, "Unable to bind DMA resources for"
4174 " extra SGL");
4175 return (DDI_FAILURE);
4176 }
4177
4178 /*
4179 * Store the SGL memory address. This chip uses this
4180 * address to dma to and from the driver. The second
4181 * address is the address mpt uses to fill in the SGL.
4182 */
4183 p->m_phys_addr = cookie.dmac_laddress;
4184
4185 return (DDI_SUCCESS);
4186 }
4187
4188 static void
mptsas_cache_frames_destructor(void * buf,void * cdrarg)4189 mptsas_cache_frames_destructor(void *buf, void *cdrarg)
4190 {
4191 #ifndef __lock_lint
4192 _NOTE(ARGUNUSED(cdrarg))
4193 #endif
4194 mptsas_cache_frames_t *p = buf;
4195 if (p->m_dma_hdl != NULL) {
4196 (void) ddi_dma_unbind_handle(p->m_dma_hdl);
4197 (void) ddi_dma_mem_free(&p->m_acc_hdl);
4198 ddi_dma_free_handle(&p->m_dma_hdl);
4199 p->m_phys_addr = 0;
4200 p->m_frames_addr = NULL;
4201 p->m_dma_hdl = NULL;
4202 p->m_acc_hdl = NULL;
4203 }
4204
4205 }
4206
4207 /*
4208 * Figure out if we need to use a different method for the request
4209 * sense buffer and allocate from the map if necessary.
4210 */
4211 static boolean_t
mptsas_cmdarqsize(mptsas_t * mpt,mptsas_cmd_t * cmd,size_t senselength,int kf)4212 mptsas_cmdarqsize(mptsas_t *mpt, mptsas_cmd_t *cmd, size_t senselength, int kf)
4213 {
4214 if (senselength > mpt->m_req_sense_size) {
4215 unsigned long i;
4216
4217 /* Sense length is limited to an 8 bit value in MPI Spec. */
4218 if (senselength > 255)
4219 senselength = 255;
4220 cmd->cmd_extrqschunks = (senselength +
4221 (mpt->m_req_sense_size - 1))/mpt->m_req_sense_size;
4222 i = (kf == KM_SLEEP ? rmalloc_wait : rmalloc)
4223 (mpt->m_erqsense_map, cmd->cmd_extrqschunks);
4224
4225 if (i == 0)
4226 return (B_FALSE);
4227
4228 cmd->cmd_extrqslen = (uint16_t)senselength;
4229 cmd->cmd_extrqsidx = i - 1;
4230 cmd->cmd_arq_buf = mpt->m_extreq_sense +
4231 (cmd->cmd_extrqsidx * mpt->m_req_sense_size);
4232 } else {
4233 cmd->cmd_rqslen = (uchar_t)senselength;
4234 }
4235
4236 return (B_TRUE);
4237 }
4238
4239 /*
4240 * allocate and deallocate external pkt space (ie. not part of mptsas_cmd)
4241 * for non-standard length cdb, pkt_private, status areas
4242 * if allocation fails, then deallocate all external space and the pkt
4243 */
4244 /* ARGSUSED */
4245 static int
mptsas_pkt_alloc_extern(mptsas_t * mpt,mptsas_cmd_t * cmd,int cmdlen,int tgtlen,int statuslen,int kf)4246 mptsas_pkt_alloc_extern(mptsas_t *mpt, mptsas_cmd_t *cmd,
4247 int cmdlen, int tgtlen, int statuslen, int kf)
4248 {
4249 caddr_t cdbp, scbp, tgt;
4250
4251 NDBG3(("mptsas_pkt_alloc_extern: "
4252 "cmd=0x%p cmdlen=%d tgtlen=%d statuslen=%d kf=%x",
4253 (void *)cmd, cmdlen, tgtlen, statuslen, kf));
4254
4255 tgt = cdbp = scbp = NULL;
4256 cmd->cmd_scblen = statuslen;
4257 cmd->cmd_privlen = (uchar_t)tgtlen;
4258
4259 if (cmdlen > sizeof (cmd->cmd_cdb)) {
4260 if ((cdbp = kmem_zalloc((size_t)cmdlen, kf)) == NULL) {
4261 goto fail;
4262 }
4263 cmd->cmd_pkt->pkt_cdbp = (opaque_t)cdbp;
4264 cmd->cmd_flags |= CFLAG_CDBEXTERN;
4265 }
4266 if (tgtlen > PKT_PRIV_LEN) {
4267 if ((tgt = kmem_zalloc((size_t)tgtlen, kf)) == NULL) {
4268 goto fail;
4269 }
4270 cmd->cmd_flags |= CFLAG_PRIVEXTERN;
4271 cmd->cmd_pkt->pkt_private = tgt;
4272 }
4273 if (statuslen > EXTCMDS_STATUS_SIZE) {
4274 if ((scbp = kmem_zalloc((size_t)statuslen, kf)) == NULL) {
4275 goto fail;
4276 }
4277 cmd->cmd_flags |= CFLAG_SCBEXTERN;
4278 cmd->cmd_pkt->pkt_scbp = (opaque_t)scbp;
4279
4280 /* allocate sense data buf for DMA */
4281 if (mptsas_cmdarqsize(mpt, cmd, statuslen -
4282 MPTSAS_GET_ITEM_OFF(struct scsi_arq_status, sts_sensedata),
4283 kf) == B_FALSE)
4284 goto fail;
4285 }
4286 return (0);
4287 fail:
4288 mptsas_pkt_destroy_extern(mpt, cmd);
4289 return (1);
4290 }
4291
4292 /*
4293 * deallocate external pkt space and deallocate the pkt
4294 */
4295 static void
mptsas_pkt_destroy_extern(mptsas_t * mpt,mptsas_cmd_t * cmd)4296 mptsas_pkt_destroy_extern(mptsas_t *mpt, mptsas_cmd_t *cmd)
4297 {
4298 NDBG3(("mptsas_pkt_destroy_extern: cmd=0x%p", (void *)cmd));
4299
4300 if (cmd->cmd_flags & CFLAG_FREE) {
4301 mptsas_log(mpt, CE_PANIC,
4302 "mptsas_pkt_destroy_extern: freeing free packet");
4303 _NOTE(NOT_REACHED)
4304 /* NOTREACHED */
4305 }
4306 if (cmd->cmd_extrqslen != 0) {
4307 rmfree(mpt->m_erqsense_map, cmd->cmd_extrqschunks,
4308 cmd->cmd_extrqsidx + 1);
4309 }
4310 if (cmd->cmd_flags & CFLAG_CDBEXTERN) {
4311 kmem_free(cmd->cmd_pkt->pkt_cdbp, (size_t)cmd->cmd_cdblen);
4312 }
4313 if (cmd->cmd_flags & CFLAG_SCBEXTERN) {
4314 kmem_free(cmd->cmd_pkt->pkt_scbp, (size_t)cmd->cmd_scblen);
4315 }
4316 if (cmd->cmd_flags & CFLAG_PRIVEXTERN) {
4317 kmem_free(cmd->cmd_pkt->pkt_private, (size_t)cmd->cmd_privlen);
4318 }
4319 cmd->cmd_flags = CFLAG_FREE;
4320 kmem_cache_free(mpt->m_kmem_cache, (void *)cmd);
4321 }
4322
4323 /*
4324 * tran_sync_pkt(9E) - explicit DMA synchronization
4325 */
4326 /*ARGSUSED*/
4327 static void
mptsas_scsi_sync_pkt(struct scsi_address * ap,struct scsi_pkt * pkt)4328 mptsas_scsi_sync_pkt(struct scsi_address *ap, struct scsi_pkt *pkt)
4329 {
4330 mptsas_cmd_t *cmd = PKT2CMD(pkt);
4331
4332 NDBG3(("mptsas_scsi_sync_pkt: target=%d, pkt=0x%p",
4333 ap->a_target, (void *)pkt));
4334
4335 if (cmd->cmd_dmahandle) {
4336 (void) ddi_dma_sync(cmd->cmd_dmahandle, 0, 0,
4337 (cmd->cmd_flags & CFLAG_DMASEND) ?
4338 DDI_DMA_SYNC_FORDEV : DDI_DMA_SYNC_FORCPU);
4339 }
4340 }
4341
4342 /*
4343 * tran_dmafree(9E) - deallocate DMA resources allocated for command
4344 */
4345 /*ARGSUSED*/
4346 static void
mptsas_scsi_dmafree(struct scsi_address * ap,struct scsi_pkt * pkt)4347 mptsas_scsi_dmafree(struct scsi_address *ap, struct scsi_pkt *pkt)
4348 {
4349 mptsas_cmd_t *cmd = PKT2CMD(pkt);
4350 mptsas_t *mpt = ADDR2MPT(ap);
4351
4352 NDBG3(("mptsas_scsi_dmafree: target=%d pkt=0x%p",
4353 ap->a_target, (void *)pkt));
4354
4355 if (cmd->cmd_flags & CFLAG_DMAVALID) {
4356 (void) ddi_dma_unbind_handle(cmd->cmd_dmahandle);
4357 cmd->cmd_flags &= ~CFLAG_DMAVALID;
4358 }
4359
4360 mptsas_free_extra_sgl_frame(mpt, cmd);
4361 }
4362
4363 static void
mptsas_pkt_comp(struct scsi_pkt * pkt,mptsas_cmd_t * cmd)4364 mptsas_pkt_comp(struct scsi_pkt *pkt, mptsas_cmd_t *cmd)
4365 {
4366 if ((cmd->cmd_flags & CFLAG_CMDIOPB) &&
4367 (!(cmd->cmd_flags & CFLAG_DMASEND))) {
4368 (void) ddi_dma_sync(cmd->cmd_dmahandle, 0, 0,
4369 DDI_DMA_SYNC_FORCPU);
4370 }
4371 (*pkt->pkt_comp)(pkt);
4372 }
4373
4374 static void
mptsas_sge_mainframe(mptsas_cmd_t * cmd,pMpi2SCSIIORequest_t frame,ddi_acc_handle_t acc_hdl,uint_t cookiec,uint32_t end_flags)4375 mptsas_sge_mainframe(mptsas_cmd_t *cmd, pMpi2SCSIIORequest_t frame,
4376 ddi_acc_handle_t acc_hdl, uint_t cookiec, uint32_t end_flags)
4377 {
4378 pMpi2SGESimple64_t sge;
4379 mptti_t *dmap;
4380 uint32_t flags;
4381
4382 dmap = cmd->cmd_sg;
4383
4384 sge = (pMpi2SGESimple64_t)(&frame->SGL);
4385 while (cookiec--) {
4386 ddi_put32(acc_hdl,
4387 &sge->Address.Low, dmap->addr.address64.Low);
4388 ddi_put32(acc_hdl,
4389 &sge->Address.High, dmap->addr.address64.High);
4390 ddi_put32(acc_hdl, &sge->FlagsLength,
4391 dmap->count);
4392 flags = ddi_get32(acc_hdl, &sge->FlagsLength);
4393 flags |= ((uint32_t)
4394 (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
4395 MPI2_SGE_FLAGS_SYSTEM_ADDRESS |
4396 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) <<
4397 MPI2_SGE_FLAGS_SHIFT);
4398
4399 /*
4400 * If this is the last cookie, we set the flags
4401 * to indicate so
4402 */
4403 if (cookiec == 0) {
4404 flags |= end_flags;
4405 }
4406 if (cmd->cmd_flags & CFLAG_DMASEND) {
4407 flags |= (MPI2_SGE_FLAGS_HOST_TO_IOC <<
4408 MPI2_SGE_FLAGS_SHIFT);
4409 } else {
4410 flags |= (MPI2_SGE_FLAGS_IOC_TO_HOST <<
4411 MPI2_SGE_FLAGS_SHIFT);
4412 }
4413 ddi_put32(acc_hdl, &sge->FlagsLength, flags);
4414 dmap++;
4415 sge++;
4416 }
4417 }
4418
4419 static void
mptsas_sge_chain(mptsas_t * mpt,mptsas_cmd_t * cmd,pMpi2SCSIIORequest_t frame,ddi_acc_handle_t acc_hdl)4420 mptsas_sge_chain(mptsas_t *mpt, mptsas_cmd_t *cmd,
4421 pMpi2SCSIIORequest_t frame, ddi_acc_handle_t acc_hdl)
4422 {
4423 pMpi2SGESimple64_t sge;
4424 pMpi2SGEChain64_t sgechain;
4425 uint64_t nframe_phys_addr;
4426 uint_t cookiec;
4427 mptti_t *dmap;
4428 uint32_t flags;
4429
4430 /*
4431 * Save the number of entries in the DMA
4432 * Scatter/Gather list
4433 */
4434 cookiec = cmd->cmd_cookiec;
4435
4436 /*
4437 * Hereby we start to deal with multiple frames.
4438 * The process is as follows:
4439 * 1. Determine how many frames are needed for SGL element
4440 * storage; Note that all frames are stored in contiguous
4441 * memory space and in 64-bit DMA mode each element is
4442 * 3 double-words (12 bytes) long.
4443 * 2. Fill up the main frame. We need to do this separately
4444 * since it contains the SCSI IO request header and needs
4445 * dedicated processing. Note that the last 4 double-words
4446 * of the SCSI IO header is for SGL element storage
4447 * (MPI2_SGE_IO_UNION).
4448 * 3. Fill the chain element in the main frame, so the DMA
4449 * engine can use the following frames.
4450 * 4. Enter a loop to fill the remaining frames. Note that the
4451 * last frame contains no chain element. The remaining
4452 * frames go into the mpt SGL buffer allocated on the fly,
4453 * not immediately following the main message frame, as in
4454 * Gen1.
4455 * Some restrictions:
4456 * 1. For 64-bit DMA, the simple element and chain element
4457 * are both of 3 double-words (12 bytes) in size, even
4458 * though all frames are stored in the first 4G of mem
4459 * range and the higher 32-bits of the address are always 0.
4460 * 2. On some controllers (like the 1064/1068), a frame can
4461 * hold SGL elements with the last 1 or 2 double-words
4462 * (4 or 8 bytes) un-used. On these controllers, we should
4463 * recognize that there's not enough room for another SGL
4464 * element and move the sge pointer to the next frame.
4465 */
4466 int i, j, k, l, frames, sgemax;
4467 int temp;
4468 uint8_t chainflags;
4469 uint16_t chainlength;
4470 mptsas_cache_frames_t *p;
4471
4472 /*
4473 * Sgemax is the number of SGE's that will fit
4474 * each extra frame and frames is total
4475 * number of frames we'll need. 1 sge entry per
4476 * frame is reseverd for the chain element thus the -1 below.
4477 */
4478 sgemax = ((mpt->m_req_frame_size / sizeof (MPI2_SGE_SIMPLE64))
4479 - 1);
4480 temp = (cookiec - (MPTSAS_MAX_FRAME_SGES64(mpt) - 1)) / sgemax;
4481
4482 /*
4483 * A little check to see if we need to round up the number
4484 * of frames we need
4485 */
4486 if ((cookiec - (MPTSAS_MAX_FRAME_SGES64(mpt) - 1)) - (temp *
4487 sgemax) > 1) {
4488 frames = (temp + 1);
4489 } else {
4490 frames = temp;
4491 }
4492 dmap = cmd->cmd_sg;
4493 sge = (pMpi2SGESimple64_t)(&frame->SGL);
4494
4495 /*
4496 * First fill in the main frame
4497 */
4498 j = MPTSAS_MAX_FRAME_SGES64(mpt) - 1;
4499 mptsas_sge_mainframe(cmd, frame, acc_hdl, j,
4500 ((uint32_t)(MPI2_SGE_FLAGS_LAST_ELEMENT) <<
4501 MPI2_SGE_FLAGS_SHIFT));
4502 dmap += j;
4503 sge += j;
4504 j++;
4505
4506 /*
4507 * Fill in the chain element in the main frame.
4508 * About calculation on ChainOffset:
4509 * 1. Struct msg_scsi_io_request has 4 double-words (16 bytes)
4510 * in the end reserved for SGL element storage
4511 * (MPI2_SGE_IO_UNION); we should count it in our
4512 * calculation. See its definition in the header file.
4513 * 2. Constant j is the counter of the current SGL element
4514 * that will be processed, and (j - 1) is the number of
4515 * SGL elements that have been processed (stored in the
4516 * main frame).
4517 * 3. ChainOffset value should be in units of double-words (4
4518 * bytes) so the last value should be divided by 4.
4519 */
4520 ddi_put8(acc_hdl, &frame->ChainOffset,
4521 (sizeof (MPI2_SCSI_IO_REQUEST) -
4522 sizeof (MPI2_SGE_IO_UNION) +
4523 (j - 1) * sizeof (MPI2_SGE_SIMPLE64)) >> 2);
4524 sgechain = (pMpi2SGEChain64_t)sge;
4525 chainflags = (MPI2_SGE_FLAGS_CHAIN_ELEMENT |
4526 MPI2_SGE_FLAGS_SYSTEM_ADDRESS |
4527 MPI2_SGE_FLAGS_64_BIT_ADDRESSING);
4528 ddi_put8(acc_hdl, &sgechain->Flags, chainflags);
4529
4530 /*
4531 * The size of the next frame is the accurate size of space
4532 * (in bytes) used to store the SGL elements. j is the counter
4533 * of SGL elements. (j - 1) is the number of SGL elements that
4534 * have been processed (stored in frames).
4535 */
4536 if (frames >= 2) {
4537 ASSERT(mpt->m_req_frame_size >= sizeof (MPI2_SGE_SIMPLE64));
4538 chainlength = mpt->m_req_frame_size /
4539 sizeof (MPI2_SGE_SIMPLE64) *
4540 sizeof (MPI2_SGE_SIMPLE64);
4541 } else {
4542 chainlength = ((cookiec - (j - 1)) *
4543 sizeof (MPI2_SGE_SIMPLE64));
4544 }
4545
4546 p = cmd->cmd_extra_frames;
4547
4548 ddi_put16(acc_hdl, &sgechain->Length, chainlength);
4549 ddi_put32(acc_hdl, &sgechain->Address.Low, p->m_phys_addr);
4550 ddi_put32(acc_hdl, &sgechain->Address.High, p->m_phys_addr >> 32);
4551
4552 /*
4553 * If there are more than 2 frames left we have to
4554 * fill in the next chain offset to the location of
4555 * the chain element in the next frame.
4556 * sgemax is the number of simple elements in an extra
4557 * frame. Note that the value NextChainOffset should be
4558 * in double-words (4 bytes).
4559 */
4560 if (frames >= 2) {
4561 ddi_put8(acc_hdl, &sgechain->NextChainOffset,
4562 (sgemax * sizeof (MPI2_SGE_SIMPLE64)) >> 2);
4563 } else {
4564 ddi_put8(acc_hdl, &sgechain->NextChainOffset, 0);
4565 }
4566
4567 /*
4568 * Jump to next frame;
4569 * Starting here, chain buffers go into the per command SGL.
4570 * This buffer is allocated when chain buffers are needed.
4571 */
4572 sge = (pMpi2SGESimple64_t)p->m_frames_addr;
4573 i = cookiec;
4574
4575 /*
4576 * Start filling in frames with SGE's. If we
4577 * reach the end of frame and still have SGE's
4578 * to fill we need to add a chain element and
4579 * use another frame. j will be our counter
4580 * for what cookie we are at and i will be
4581 * the total cookiec. k is the current frame
4582 */
4583 for (k = 1; k <= frames; k++) {
4584 for (l = 1; (l <= (sgemax + 1)) && (j <= i); j++, l++) {
4585
4586 /*
4587 * If we have reached the end of frame
4588 * and we have more SGE's to fill in
4589 * we have to fill the final entry
4590 * with a chain element and then
4591 * continue to the next frame
4592 */
4593 if ((l == (sgemax + 1)) && (k != frames)) {
4594 sgechain = (pMpi2SGEChain64_t)sge;
4595 j--;
4596 chainflags = (
4597 MPI2_SGE_FLAGS_CHAIN_ELEMENT |
4598 MPI2_SGE_FLAGS_SYSTEM_ADDRESS |
4599 MPI2_SGE_FLAGS_64_BIT_ADDRESSING);
4600 ddi_put8(p->m_acc_hdl,
4601 &sgechain->Flags, chainflags);
4602 /*
4603 * k is the frame counter and (k + 1)
4604 * is the number of the next frame.
4605 * Note that frames are in contiguous
4606 * memory space.
4607 */
4608 nframe_phys_addr = p->m_phys_addr +
4609 (mpt->m_req_frame_size * k);
4610 ddi_put32(p->m_acc_hdl,
4611 &sgechain->Address.Low,
4612 nframe_phys_addr);
4613 ddi_put32(p->m_acc_hdl,
4614 &sgechain->Address.High,
4615 nframe_phys_addr >> 32);
4616
4617 /*
4618 * If there are more than 2 frames left
4619 * we have to next chain offset to
4620 * the location of the chain element
4621 * in the next frame and fill in the
4622 * length of the next chain
4623 */
4624 if ((frames - k) >= 2) {
4625 ddi_put8(p->m_acc_hdl,
4626 &sgechain->NextChainOffset,
4627 (sgemax *
4628 sizeof (MPI2_SGE_SIMPLE64))
4629 >> 2);
4630 ddi_put16(p->m_acc_hdl,
4631 &sgechain->Length,
4632 mpt->m_req_frame_size /
4633 sizeof (MPI2_SGE_SIMPLE64) *
4634 sizeof (MPI2_SGE_SIMPLE64));
4635 } else {
4636 /*
4637 * This is the last frame. Set
4638 * the NextChainOffset to 0 and
4639 * Length is the total size of
4640 * all remaining simple elements
4641 */
4642 ddi_put8(p->m_acc_hdl,
4643 &sgechain->NextChainOffset,
4644 0);
4645 ddi_put16(p->m_acc_hdl,
4646 &sgechain->Length,
4647 (cookiec - j) *
4648 sizeof (MPI2_SGE_SIMPLE64));
4649 }
4650
4651 /* Jump to the next frame */
4652 sge = (pMpi2SGESimple64_t)
4653 ((char *)p->m_frames_addr +
4654 (int)mpt->m_req_frame_size * k);
4655
4656 continue;
4657 }
4658
4659 ddi_put32(p->m_acc_hdl,
4660 &sge->Address.Low,
4661 dmap->addr.address64.Low);
4662 ddi_put32(p->m_acc_hdl,
4663 &sge->Address.High,
4664 dmap->addr.address64.High);
4665 ddi_put32(p->m_acc_hdl,
4666 &sge->FlagsLength, dmap->count);
4667 flags = ddi_get32(p->m_acc_hdl,
4668 &sge->FlagsLength);
4669 flags |= ((uint32_t)(
4670 MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
4671 MPI2_SGE_FLAGS_SYSTEM_ADDRESS |
4672 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) <<
4673 MPI2_SGE_FLAGS_SHIFT);
4674
4675 /*
4676 * If we are at the end of the frame and
4677 * there is another frame to fill in
4678 * we set the last simple element as last
4679 * element
4680 */
4681 if ((l == sgemax) && (k != frames)) {
4682 flags |= ((uint32_t)
4683 (MPI2_SGE_FLAGS_LAST_ELEMENT) <<
4684 MPI2_SGE_FLAGS_SHIFT);
4685 }
4686
4687 /*
4688 * If this is the final cookie we
4689 * indicate it by setting the flags
4690 */
4691 if (j == i) {
4692 flags |= ((uint32_t)
4693 (MPI2_SGE_FLAGS_LAST_ELEMENT |
4694 MPI2_SGE_FLAGS_END_OF_BUFFER |
4695 MPI2_SGE_FLAGS_END_OF_LIST) <<
4696 MPI2_SGE_FLAGS_SHIFT);
4697 }
4698 if (cmd->cmd_flags & CFLAG_DMASEND) {
4699 flags |=
4700 (MPI2_SGE_FLAGS_HOST_TO_IOC <<
4701 MPI2_SGE_FLAGS_SHIFT);
4702 } else {
4703 flags |=
4704 (MPI2_SGE_FLAGS_IOC_TO_HOST <<
4705 MPI2_SGE_FLAGS_SHIFT);
4706 }
4707 ddi_put32(p->m_acc_hdl,
4708 &sge->FlagsLength, flags);
4709 dmap++;
4710 sge++;
4711 }
4712 }
4713
4714 /*
4715 * Sync DMA with the chain buffers that were just created
4716 */
4717 (void) ddi_dma_sync(p->m_dma_hdl, 0, 0, DDI_DMA_SYNC_FORDEV);
4718 }
4719
4720 static void
mptsas_ieee_sge_mainframe(mptsas_cmd_t * cmd,pMpi2SCSIIORequest_t frame,ddi_acc_handle_t acc_hdl,uint_t cookiec,uint8_t end_flag)4721 mptsas_ieee_sge_mainframe(mptsas_cmd_t *cmd, pMpi2SCSIIORequest_t frame,
4722 ddi_acc_handle_t acc_hdl, uint_t cookiec, uint8_t end_flag)
4723 {
4724 pMpi2IeeeSgeSimple64_t ieeesge;
4725 mptti_t *dmap;
4726 uint8_t flags;
4727
4728 dmap = cmd->cmd_sg;
4729
4730 NDBG1(("mptsas_ieee_sge_mainframe: cookiec=%d, %s", cookiec,
4731 cmd->cmd_flags & CFLAG_DMASEND?"Out":"In"));
4732
4733 ieeesge = (pMpi2IeeeSgeSimple64_t)(&frame->SGL);
4734 while (cookiec--) {
4735 ddi_put32(acc_hdl,
4736 &ieeesge->Address.Low, dmap->addr.address64.Low);
4737 ddi_put32(acc_hdl,
4738 &ieeesge->Address.High, dmap->addr.address64.High);
4739 ddi_put32(acc_hdl, &ieeesge->Length,
4740 dmap->count);
4741 NDBG1(("mptsas_ieee_sge_mainframe: len=%d", dmap->count));
4742 flags = (MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
4743 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR);
4744
4745 /*
4746 * If this is the last cookie, we set the flags
4747 * to indicate so
4748 */
4749 if (cookiec == 0) {
4750 flags |= end_flag;
4751 }
4752
4753 ddi_put8(acc_hdl, &ieeesge->Flags, flags);
4754 dmap++;
4755 ieeesge++;
4756 }
4757 }
4758
4759 static void
mptsas_ieee_sge_chain(mptsas_t * mpt,mptsas_cmd_t * cmd,pMpi2SCSIIORequest_t frame,ddi_acc_handle_t acc_hdl)4760 mptsas_ieee_sge_chain(mptsas_t *mpt, mptsas_cmd_t *cmd,
4761 pMpi2SCSIIORequest_t frame, ddi_acc_handle_t acc_hdl)
4762 {
4763 pMpi2IeeeSgeSimple64_t ieeesge;
4764 pMpi25IeeeSgeChain64_t ieeesgechain;
4765 uint64_t nframe_phys_addr;
4766 uint_t cookiec;
4767 mptti_t *dmap;
4768 uint8_t flags;
4769
4770 /*
4771 * Save the number of entries in the DMA
4772 * Scatter/Gather list
4773 */
4774 cookiec = cmd->cmd_cookiec;
4775
4776 NDBG1(("mptsas_ieee_sge_chain: cookiec=%d", cookiec));
4777
4778 /*
4779 * Hereby we start to deal with multiple frames.
4780 * The process is as follows:
4781 * 1. Determine how many frames are needed for SGL element
4782 * storage; Note that all frames are stored in contiguous
4783 * memory space and in 64-bit DMA mode each element is
4784 * 4 double-words (16 bytes) long.
4785 * 2. Fill up the main frame. We need to do this separately
4786 * since it contains the SCSI IO request header and needs
4787 * dedicated processing. Note that the last 4 double-words
4788 * of the SCSI IO header is for SGL element storage
4789 * (MPI2_SGE_IO_UNION).
4790 * 3. Fill the chain element in the main frame, so the DMA
4791 * engine can use the following frames.
4792 * 4. Enter a loop to fill the remaining frames. Note that the
4793 * last frame contains no chain element. The remaining
4794 * frames go into the mpt SGL buffer allocated on the fly,
4795 * not immediately following the main message frame, as in
4796 * Gen1.
4797 * Restrictions:
4798 * For 64-bit DMA, the simple element and chain element
4799 * are both of 4 double-words (16 bytes) in size, even
4800 * though all frames are stored in the first 4G of mem
4801 * range and the higher 32-bits of the address are always 0.
4802 */
4803 int i, j, k, l, frames, sgemax;
4804 int temp;
4805 uint8_t chainflags;
4806 uint32_t chainlength;
4807 mptsas_cache_frames_t *p;
4808
4809 /*
4810 * Sgemax is the number of SGE's that will fit
4811 * each extra frame and frames is total
4812 * number of frames we'll need. 1 sge entry per
4813 * frame is reseverd for the chain element thus the -1 below.
4814 */
4815 sgemax = ((mpt->m_req_frame_size / sizeof (MPI2_IEEE_SGE_SIMPLE64))
4816 - 1);
4817 temp = (cookiec - (MPTSAS_MAX_FRAME_SGES64(mpt) - 1)) / sgemax;
4818
4819 /*
4820 * A little check to see if we need to round up the number
4821 * of frames we need
4822 */
4823 if ((cookiec - (MPTSAS_MAX_FRAME_SGES64(mpt) - 1)) - (temp *
4824 sgemax) > 1) {
4825 frames = (temp + 1);
4826 } else {
4827 frames = temp;
4828 }
4829 NDBG1(("mptsas_ieee_sge_chain: temp=%d, frames=%d", temp, frames));
4830 dmap = cmd->cmd_sg;
4831 ieeesge = (pMpi2IeeeSgeSimple64_t)(&frame->SGL);
4832
4833 /*
4834 * First fill in the main frame
4835 */
4836 j = MPTSAS_MAX_FRAME_SGES64(mpt) - 1;
4837 mptsas_ieee_sge_mainframe(cmd, frame, acc_hdl, j, 0);
4838 dmap += j;
4839 ieeesge += j;
4840 j++;
4841
4842 /*
4843 * Fill in the chain element in the main frame.
4844 * About calculation on ChainOffset:
4845 * 1. Struct msg_scsi_io_request has 4 double-words (16 bytes)
4846 * in the end reserved for SGL element storage
4847 * (MPI2_SGE_IO_UNION); we should count it in our
4848 * calculation. See its definition in the header file.
4849 * 2. Constant j is the counter of the current SGL element
4850 * that will be processed, and (j - 1) is the number of
4851 * SGL elements that have been processed (stored in the
4852 * main frame).
4853 * 3. ChainOffset value should be in units of quad-words (16
4854 * bytes) so the last value should be divided by 16.
4855 */
4856 ddi_put8(acc_hdl, &frame->ChainOffset,
4857 (sizeof (MPI2_SCSI_IO_REQUEST) -
4858 sizeof (MPI2_SGE_IO_UNION) +
4859 (j - 1) * sizeof (MPI2_IEEE_SGE_SIMPLE64)) >> 4);
4860 ieeesgechain = (pMpi25IeeeSgeChain64_t)ieeesge;
4861 chainflags = (MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT |
4862 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR);
4863 ddi_put8(acc_hdl, &ieeesgechain->Flags, chainflags);
4864
4865 /*
4866 * The size of the next frame is the accurate size of space
4867 * (in bytes) used to store the SGL elements. j is the counter
4868 * of SGL elements. (j - 1) is the number of SGL elements that
4869 * have been processed (stored in frames).
4870 */
4871 if (frames >= 2) {
4872 ASSERT(mpt->m_req_frame_size >=
4873 sizeof (MPI2_IEEE_SGE_SIMPLE64));
4874 chainlength = mpt->m_req_frame_size /
4875 sizeof (MPI2_IEEE_SGE_SIMPLE64) *
4876 sizeof (MPI2_IEEE_SGE_SIMPLE64);
4877 } else {
4878 chainlength = ((cookiec - (j - 1)) *
4879 sizeof (MPI2_IEEE_SGE_SIMPLE64));
4880 }
4881
4882 p = cmd->cmd_extra_frames;
4883
4884 ddi_put32(acc_hdl, &ieeesgechain->Length, chainlength);
4885 ddi_put32(acc_hdl, &ieeesgechain->Address.Low, p->m_phys_addr);
4886 ddi_put32(acc_hdl, &ieeesgechain->Address.High, p->m_phys_addr >> 32);
4887
4888 /*
4889 * If there are more than 2 frames left we have to
4890 * fill in the next chain offset to the location of
4891 * the chain element in the next frame.
4892 * sgemax is the number of simple elements in an extra
4893 * frame. Note that the value NextChainOffset should be
4894 * in double-words (4 bytes).
4895 */
4896 if (frames >= 2) {
4897 ddi_put8(acc_hdl, &ieeesgechain->NextChainOffset,
4898 (sgemax * sizeof (MPI2_IEEE_SGE_SIMPLE64)) >> 4);
4899 } else {
4900 ddi_put8(acc_hdl, &ieeesgechain->NextChainOffset, 0);
4901 }
4902
4903 /*
4904 * Jump to next frame;
4905 * Starting here, chain buffers go into the per command SGL.
4906 * This buffer is allocated when chain buffers are needed.
4907 */
4908 ieeesge = (pMpi2IeeeSgeSimple64_t)p->m_frames_addr;
4909 i = cookiec;
4910
4911 /*
4912 * Start filling in frames with SGE's. If we
4913 * reach the end of frame and still have SGE's
4914 * to fill we need to add a chain element and
4915 * use another frame. j will be our counter
4916 * for what cookie we are at and i will be
4917 * the total cookiec. k is the current frame
4918 */
4919 for (k = 1; k <= frames; k++) {
4920 for (l = 1; (l <= (sgemax + 1)) && (j <= i); j++, l++) {
4921
4922 /*
4923 * If we have reached the end of frame
4924 * and we have more SGE's to fill in
4925 * we have to fill the final entry
4926 * with a chain element and then
4927 * continue to the next frame
4928 */
4929 if ((l == (sgemax + 1)) && (k != frames)) {
4930 ieeesgechain = (pMpi25IeeeSgeChain64_t)ieeesge;
4931 j--;
4932 chainflags =
4933 MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT |
4934 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
4935 ddi_put8(p->m_acc_hdl,
4936 &ieeesgechain->Flags, chainflags);
4937 /*
4938 * k is the frame counter and (k + 1)
4939 * is the number of the next frame.
4940 * Note that frames are in contiguous
4941 * memory space.
4942 */
4943 nframe_phys_addr = p->m_phys_addr +
4944 (mpt->m_req_frame_size * k);
4945 ddi_put32(p->m_acc_hdl,
4946 &ieeesgechain->Address.Low,
4947 nframe_phys_addr);
4948 ddi_put32(p->m_acc_hdl,
4949 &ieeesgechain->Address.High,
4950 nframe_phys_addr >> 32);
4951
4952 /*
4953 * If there are more than 2 frames left
4954 * we have to next chain offset to
4955 * the location of the chain element
4956 * in the next frame and fill in the
4957 * length of the next chain
4958 */
4959 if ((frames - k) >= 2) {
4960 ddi_put8(p->m_acc_hdl,
4961 &ieeesgechain->NextChainOffset,
4962 (sgemax *
4963 sizeof (MPI2_IEEE_SGE_SIMPLE64))
4964 >> 4);
4965 ASSERT(mpt->m_req_frame_size >=
4966 sizeof (MPI2_IEEE_SGE_SIMPLE64));
4967 ddi_put32(p->m_acc_hdl,
4968 &ieeesgechain->Length,
4969 mpt->m_req_frame_size /
4970 sizeof (MPI2_IEEE_SGE_SIMPLE64) *
4971 sizeof (MPI2_IEEE_SGE_SIMPLE64));
4972 } else {
4973 /*
4974 * This is the last frame. Set
4975 * the NextChainOffset to 0 and
4976 * Length is the total size of
4977 * all remaining simple elements
4978 */
4979 ddi_put8(p->m_acc_hdl,
4980 &ieeesgechain->NextChainOffset,
4981 0);
4982 ddi_put32(p->m_acc_hdl,
4983 &ieeesgechain->Length,
4984 (cookiec - j) *
4985 sizeof (MPI2_IEEE_SGE_SIMPLE64));
4986 }
4987
4988 /* Jump to the next frame */
4989 ieeesge = (pMpi2IeeeSgeSimple64_t)
4990 ((char *)p->m_frames_addr +
4991 (int)mpt->m_req_frame_size * k);
4992
4993 continue;
4994 }
4995
4996 ddi_put32(p->m_acc_hdl,
4997 &ieeesge->Address.Low,
4998 dmap->addr.address64.Low);
4999 ddi_put32(p->m_acc_hdl,
5000 &ieeesge->Address.High,
5001 dmap->addr.address64.High);
5002 ddi_put32(p->m_acc_hdl,
5003 &ieeesge->Length, dmap->count);
5004 flags = (MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
5005 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR);
5006
5007 /*
5008 * If we are at the end of the frame and
5009 * there is another frame to fill in
5010 * do we need to do anything?
5011 * if ((l == sgemax) && (k != frames)) {
5012 * }
5013 */
5014
5015 /*
5016 * If this is the final cookie set end of list.
5017 */
5018 if (j == i) {
5019 flags |= MPI25_IEEE_SGE_FLAGS_END_OF_LIST;
5020 }
5021
5022 ddi_put8(p->m_acc_hdl, &ieeesge->Flags, flags);
5023 dmap++;
5024 ieeesge++;
5025 }
5026 }
5027
5028 /*
5029 * Sync DMA with the chain buffers that were just created
5030 */
5031 (void) ddi_dma_sync(p->m_dma_hdl, 0, 0, DDI_DMA_SYNC_FORDEV);
5032 }
5033
5034 static void
mptsas_sge_setup(mptsas_t * mpt,mptsas_cmd_t * cmd,uint32_t * control,pMpi2SCSIIORequest_t frame,ddi_acc_handle_t acc_hdl)5035 mptsas_sge_setup(mptsas_t *mpt, mptsas_cmd_t *cmd, uint32_t *control,
5036 pMpi2SCSIIORequest_t frame, ddi_acc_handle_t acc_hdl)
5037 {
5038 ASSERT(cmd->cmd_flags & CFLAG_DMAVALID);
5039
5040 NDBG1(("mptsas_sge_setup: cookiec=%d", cmd->cmd_cookiec));
5041
5042 /*
5043 * Set read/write bit in control.
5044 */
5045 if (cmd->cmd_flags & CFLAG_DMASEND) {
5046 *control |= MPI2_SCSIIO_CONTROL_WRITE;
5047 } else {
5048 *control |= MPI2_SCSIIO_CONTROL_READ;
5049 }
5050
5051 ddi_put32(acc_hdl, &frame->DataLength, cmd->cmd_dmacount);
5052
5053 /*
5054 * We have 4 cases here. First where we can fit all the
5055 * SG elements into the main frame, and the case
5056 * where we can't. The SG element is also different when using
5057 * MPI2.5 interface.
5058 * If we have more cookies than we can attach to a frame
5059 * we will need to use a chain element to point
5060 * a location of memory where the rest of the S/G
5061 * elements reside.
5062 */
5063 if (cmd->cmd_cookiec <= MPTSAS_MAX_FRAME_SGES64(mpt)) {
5064 if (mpt->m_MPI25) {
5065 mptsas_ieee_sge_mainframe(cmd, frame, acc_hdl,
5066 cmd->cmd_cookiec,
5067 MPI25_IEEE_SGE_FLAGS_END_OF_LIST);
5068 } else {
5069 mptsas_sge_mainframe(cmd, frame, acc_hdl,
5070 cmd->cmd_cookiec,
5071 ((uint32_t)(MPI2_SGE_FLAGS_LAST_ELEMENT
5072 | MPI2_SGE_FLAGS_END_OF_BUFFER
5073 | MPI2_SGE_FLAGS_END_OF_LIST) <<
5074 MPI2_SGE_FLAGS_SHIFT));
5075 }
5076 } else {
5077 if (mpt->m_MPI25) {
5078 mptsas_ieee_sge_chain(mpt, cmd, frame, acc_hdl);
5079 } else {
5080 mptsas_sge_chain(mpt, cmd, frame, acc_hdl);
5081 }
5082 }
5083 }
5084
5085 /*
5086 * Interrupt handling
5087 * Utility routine. Poll for status of a command sent to HBA
5088 * without interrupts (a FLAG_NOINTR command).
5089 */
5090 int
mptsas_poll(mptsas_t * mpt,mptsas_cmd_t * poll_cmd,int polltime)5091 mptsas_poll(mptsas_t *mpt, mptsas_cmd_t *poll_cmd, int polltime)
5092 {
5093 int rval = TRUE;
5094
5095 NDBG5(("mptsas_poll: cmd=0x%p", (void *)poll_cmd));
5096
5097 if ((poll_cmd->cmd_flags & CFLAG_TM_CMD) == 0) {
5098 mptsas_restart_hba(mpt);
5099 }
5100
5101 /*
5102 * Wait, using drv_usecwait(), long enough for the command to
5103 * reasonably return from the target if the target isn't
5104 * "dead". A polled command may well be sent from scsi_poll, and
5105 * there are retries built in to scsi_poll if the transport
5106 * accepted the packet (TRAN_ACCEPT). scsi_poll waits 1 second
5107 * and retries the transport up to scsi_poll_busycnt times
5108 * (currently 60) if
5109 * 1. pkt_reason is CMD_INCOMPLETE and pkt_state is 0, or
5110 * 2. pkt_reason is CMD_CMPLT and *pkt_scbp has STATUS_BUSY
5111 *
5112 * limit the waiting to avoid a hang in the event that the
5113 * cmd never gets started but we are still receiving interrupts
5114 */
5115 while (!(poll_cmd->cmd_flags & CFLAG_FINISHED)) {
5116 if (mptsas_wait_intr(mpt, polltime) == FALSE) {
5117 NDBG5(("mptsas_poll: command incomplete"));
5118 rval = FALSE;
5119 break;
5120 }
5121 }
5122
5123 if (rval == FALSE) {
5124
5125 /*
5126 * this isn't supposed to happen, the hba must be wedged
5127 * Mark this cmd as a timeout.
5128 */
5129 mptsas_set_pkt_reason(mpt, poll_cmd, CMD_TIMEOUT,
5130 (STAT_TIMEOUT|STAT_ABORTED));
5131
5132 if (poll_cmd->cmd_queued == FALSE) {
5133
5134 NDBG5(("mptsas_poll: not on waitq"));
5135
5136 poll_cmd->cmd_pkt->pkt_state |=
5137 (STATE_GOT_BUS|STATE_GOT_TARGET|STATE_SENT_CMD);
5138 } else {
5139
5140 /* find and remove it from the waitq */
5141 NDBG5(("mptsas_poll: delete from waitq"));
5142 mptsas_waitq_delete(mpt, poll_cmd);
5143 }
5144
5145 }
5146 mptsas_fma_check(mpt, poll_cmd);
5147 NDBG5(("mptsas_poll: done"));
5148 return (rval);
5149 }
5150
5151 /*
5152 * Used for polling cmds and TM function
5153 */
5154 static int
mptsas_wait_intr(mptsas_t * mpt,int polltime)5155 mptsas_wait_intr(mptsas_t *mpt, int polltime)
5156 {
5157 int cnt;
5158 pMpi2ReplyDescriptorsUnion_t reply_desc_union;
5159 uint32_t int_mask;
5160
5161 NDBG5(("mptsas_wait_intr"));
5162
5163 mpt->m_polled_intr = 1;
5164
5165 /*
5166 * Get the current interrupt mask and disable interrupts. When
5167 * re-enabling ints, set mask to saved value.
5168 */
5169 int_mask = ddi_get32(mpt->m_datap, &mpt->m_reg->HostInterruptMask);
5170 MPTSAS_DISABLE_INTR(mpt);
5171
5172 /*
5173 * Keep polling for at least (polltime * 1000) seconds
5174 */
5175 for (cnt = 0; cnt < polltime; cnt++) {
5176 (void) ddi_dma_sync(mpt->m_dma_post_queue_hdl, 0, 0,
5177 DDI_DMA_SYNC_FORCPU);
5178
5179 reply_desc_union = (pMpi2ReplyDescriptorsUnion_t)
5180 MPTSAS_GET_NEXT_REPLY(mpt, mpt->m_post_index);
5181
5182 if (ddi_get32(mpt->m_acc_post_queue_hdl,
5183 &reply_desc_union->Words.Low) == 0xFFFFFFFF ||
5184 ddi_get32(mpt->m_acc_post_queue_hdl,
5185 &reply_desc_union->Words.High) == 0xFFFFFFFF) {
5186 drv_usecwait(1000);
5187 continue;
5188 }
5189
5190 /*
5191 * The reply is valid, process it according to its
5192 * type.
5193 */
5194 mptsas_process_intr(mpt, reply_desc_union);
5195
5196 if (++mpt->m_post_index == mpt->m_post_queue_depth) {
5197 mpt->m_post_index = 0;
5198 }
5199
5200 /*
5201 * Update the global reply index
5202 */
5203 ddi_put32(mpt->m_datap,
5204 &mpt->m_reg->ReplyPostHostIndex, mpt->m_post_index);
5205 mpt->m_polled_intr = 0;
5206
5207 /*
5208 * Re-enable interrupts and quit.
5209 */
5210 ddi_put32(mpt->m_datap, &mpt->m_reg->HostInterruptMask,
5211 int_mask);
5212 return (TRUE);
5213
5214 }
5215
5216 /*
5217 * Clear polling flag, re-enable interrupts and quit.
5218 */
5219 mpt->m_polled_intr = 0;
5220 ddi_put32(mpt->m_datap, &mpt->m_reg->HostInterruptMask, int_mask);
5221 return (FALSE);
5222 }
5223
5224 static void
mptsas_handle_scsi_io_success(mptsas_t * mpt,pMpi2ReplyDescriptorsUnion_t reply_desc)5225 mptsas_handle_scsi_io_success(mptsas_t *mpt,
5226 pMpi2ReplyDescriptorsUnion_t reply_desc)
5227 {
5228 pMpi2SCSIIOSuccessReplyDescriptor_t scsi_io_success;
5229 uint16_t SMID;
5230 mptsas_slots_t *slots = mpt->m_active;
5231 mptsas_cmd_t *cmd = NULL;
5232 struct scsi_pkt *pkt;
5233
5234 ASSERT(mutex_owned(&mpt->m_mutex));
5235
5236 scsi_io_success = (pMpi2SCSIIOSuccessReplyDescriptor_t)reply_desc;
5237 SMID = ddi_get16(mpt->m_acc_post_queue_hdl, &scsi_io_success->SMID);
5238
5239 /*
5240 * This is a success reply so just complete the IO. First, do a sanity
5241 * check on the SMID. The final slot is used for TM requests, which
5242 * would not come into this reply handler.
5243 */
5244 if ((SMID == 0) || (SMID > slots->m_n_normal)) {
5245 mptsas_log(mpt, CE_WARN, "?Received invalid SMID of %d\n",
5246 SMID);
5247 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
5248 return;
5249 }
5250
5251 cmd = slots->m_slot[SMID];
5252
5253 /*
5254 * print warning and return if the slot is empty
5255 */
5256 if (cmd == NULL) {
5257 mptsas_log(mpt, CE_WARN, "?NULL command for successful SCSI IO "
5258 "in slot %d", SMID);
5259 return;
5260 }
5261
5262 pkt = CMD2PKT(cmd);
5263 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET | STATE_SENT_CMD |
5264 STATE_GOT_STATUS);
5265 if (cmd->cmd_flags & CFLAG_DMAVALID) {
5266 pkt->pkt_state |= STATE_XFERRED_DATA;
5267 }
5268 pkt->pkt_resid = 0;
5269
5270 if (cmd->cmd_flags & CFLAG_PASSTHRU) {
5271 cmd->cmd_flags |= CFLAG_FINISHED;
5272 cv_broadcast(&mpt->m_passthru_cv);
5273 return;
5274 } else {
5275 mptsas_remove_cmd(mpt, cmd);
5276 }
5277
5278 if (cmd->cmd_flags & CFLAG_RETRY) {
5279 /*
5280 * The target returned QFULL or busy, do not add tihs
5281 * pkt to the doneq since the hba will retry
5282 * this cmd.
5283 *
5284 * The pkt has already been resubmitted in
5285 * mptsas_handle_qfull() or in mptsas_check_scsi_io_error().
5286 * Remove this cmd_flag here.
5287 */
5288 cmd->cmd_flags &= ~CFLAG_RETRY;
5289 } else {
5290 mptsas_doneq_add(mpt, cmd);
5291 }
5292 }
5293
5294 static void
mptsas_handle_address_reply(mptsas_t * mpt,pMpi2ReplyDescriptorsUnion_t reply_desc)5295 mptsas_handle_address_reply(mptsas_t *mpt,
5296 pMpi2ReplyDescriptorsUnion_t reply_desc)
5297 {
5298 pMpi2AddressReplyDescriptor_t address_reply;
5299 pMPI2DefaultReply_t reply;
5300 mptsas_fw_diagnostic_buffer_t *pBuffer;
5301 uint32_t reply_addr, reply_frame_dma_baseaddr;
5302 uint16_t SMID, iocstatus;
5303 mptsas_slots_t *slots = mpt->m_active;
5304 mptsas_cmd_t *cmd = NULL;
5305 uint8_t function, buffer_type;
5306 m_replyh_arg_t *args;
5307 int reply_frame_no;
5308
5309 ASSERT(mutex_owned(&mpt->m_mutex));
5310
5311 address_reply = (pMpi2AddressReplyDescriptor_t)reply_desc;
5312 reply_addr = ddi_get32(mpt->m_acc_post_queue_hdl,
5313 &address_reply->ReplyFrameAddress);
5314 SMID = ddi_get16(mpt->m_acc_post_queue_hdl, &address_reply->SMID);
5315
5316 /*
5317 * If reply frame is not in the proper range we should ignore this
5318 * message and exit the interrupt handler.
5319 */
5320 reply_frame_dma_baseaddr = mpt->m_reply_frame_dma_addr & 0xffffffffu;
5321 if ((reply_addr < reply_frame_dma_baseaddr) ||
5322 (reply_addr >= (reply_frame_dma_baseaddr +
5323 (mpt->m_reply_frame_size * mpt->m_max_replies))) ||
5324 ((reply_addr - reply_frame_dma_baseaddr) %
5325 mpt->m_reply_frame_size != 0)) {
5326 mptsas_log(mpt, CE_WARN, "?Received invalid reply frame "
5327 "address 0x%x\n", reply_addr);
5328 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
5329 return;
5330 }
5331
5332 (void) ddi_dma_sync(mpt->m_dma_reply_frame_hdl, 0, 0,
5333 DDI_DMA_SYNC_FORCPU);
5334 reply = (pMPI2DefaultReply_t)(mpt->m_reply_frame + (reply_addr -
5335 reply_frame_dma_baseaddr));
5336 function = ddi_get8(mpt->m_acc_reply_frame_hdl, &reply->Function);
5337
5338 NDBG31(("mptsas_handle_address_reply: function 0x%x, reply_addr=0x%x",
5339 function, reply_addr));
5340
5341 /*
5342 * don't get slot information and command for events since these values
5343 * don't exist
5344 */
5345 if ((function != MPI2_FUNCTION_EVENT_NOTIFICATION) &&
5346 (function != MPI2_FUNCTION_DIAG_BUFFER_POST)) {
5347 /*
5348 * This could be a TM reply, which use the last allocated SMID,
5349 * so allow for that.
5350 */
5351 if ((SMID == 0) || (SMID > (slots->m_n_normal + 1))) {
5352 mptsas_log(mpt, CE_WARN, "?Received invalid SMID of "
5353 "%d\n", SMID);
5354 ddi_fm_service_impact(mpt->m_dip,
5355 DDI_SERVICE_UNAFFECTED);
5356 return;
5357 }
5358
5359 cmd = slots->m_slot[SMID];
5360
5361 /*
5362 * print warning and return if the slot is empty
5363 */
5364 if (cmd == NULL) {
5365 mptsas_log(mpt, CE_WARN, "?NULL command for address "
5366 "reply in slot %d", SMID);
5367 return;
5368 }
5369 if ((cmd->cmd_flags &
5370 (CFLAG_PASSTHRU | CFLAG_CONFIG | CFLAG_FW_DIAG))) {
5371 cmd->cmd_rfm = reply_addr;
5372 cmd->cmd_flags |= CFLAG_FINISHED;
5373 cv_broadcast(&mpt->m_passthru_cv);
5374 cv_broadcast(&mpt->m_config_cv);
5375 cv_broadcast(&mpt->m_fw_diag_cv);
5376 return;
5377 } else if (!(cmd->cmd_flags & CFLAG_FW_CMD)) {
5378 mptsas_remove_cmd(mpt, cmd);
5379 }
5380 NDBG31(("\t\tmptsas_process_intr: slot=%d", SMID));
5381 }
5382 /*
5383 * Depending on the function, we need to handle
5384 * the reply frame (and cmd) differently.
5385 */
5386 switch (function) {
5387 case MPI2_FUNCTION_SCSI_IO_REQUEST:
5388 mptsas_check_scsi_io_error(mpt, (pMpi2SCSIIOReply_t)reply, cmd);
5389 break;
5390 case MPI2_FUNCTION_SCSI_TASK_MGMT:
5391 cmd->cmd_rfm = reply_addr;
5392 mptsas_check_task_mgt(mpt, (pMpi2SCSIManagementReply_t)reply,
5393 cmd);
5394 break;
5395 case MPI2_FUNCTION_FW_DOWNLOAD:
5396 cmd->cmd_flags |= CFLAG_FINISHED;
5397 cv_signal(&mpt->m_fw_cv);
5398 break;
5399 case MPI2_FUNCTION_EVENT_NOTIFICATION:
5400 reply_frame_no = (reply_addr - reply_frame_dma_baseaddr) /
5401 mpt->m_reply_frame_size;
5402 args = &mpt->m_replyh_args[reply_frame_no];
5403 args->mpt = (void *)mpt;
5404 args->rfm = reply_addr;
5405
5406 /*
5407 * Record the event if its type is enabled in
5408 * this mpt instance by ioctl.
5409 */
5410 mptsas_record_event(args);
5411
5412 /*
5413 * Handle time critical events
5414 * NOT_RESPONDING/ADDED only now
5415 */
5416 if (mptsas_handle_event_sync(args) == DDI_SUCCESS) {
5417 /*
5418 * Would not return main process,
5419 * just let taskq resolve ack action
5420 * and ack would be sent in taskq thread
5421 */
5422 NDBG20(("send mptsas_handle_event_sync success"));
5423 }
5424
5425 if (mpt->m_in_reset) {
5426 NDBG20(("dropping event received during reset"));
5427 return;
5428 }
5429
5430 if ((ddi_taskq_dispatch(mpt->m_event_taskq, mptsas_handle_event,
5431 (void *)args, DDI_NOSLEEP)) != DDI_SUCCESS) {
5432 mptsas_log(mpt, CE_WARN, "No memory available"
5433 "for dispatch taskq");
5434 /*
5435 * Return the reply frame to the free queue.
5436 */
5437 ddi_put32(mpt->m_acc_free_queue_hdl,
5438 &((uint32_t *)(void *)
5439 mpt->m_free_queue)[mpt->m_free_index], reply_addr);
5440 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0,
5441 DDI_DMA_SYNC_FORDEV);
5442 if (++mpt->m_free_index == mpt->m_free_queue_depth) {
5443 mpt->m_free_index = 0;
5444 }
5445
5446 ddi_put32(mpt->m_datap,
5447 &mpt->m_reg->ReplyFreeHostIndex, mpt->m_free_index);
5448 }
5449 return;
5450 case MPI2_FUNCTION_DIAG_BUFFER_POST:
5451 /*
5452 * If SMID is 0, this implies that the reply is due to a
5453 * release function with a status that the buffer has been
5454 * released. Set the buffer flags accordingly.
5455 */
5456 if (SMID == 0) {
5457 iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl,
5458 &reply->IOCStatus);
5459 buffer_type = ddi_get8(mpt->m_acc_reply_frame_hdl,
5460 &(((pMpi2DiagBufferPostReply_t)reply)->BufferType));
5461 if (iocstatus == MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED) {
5462 pBuffer =
5463 &mpt->m_fw_diag_buffer_list[buffer_type];
5464 pBuffer->valid_data = TRUE;
5465 pBuffer->owned_by_firmware = FALSE;
5466 pBuffer->immediate = FALSE;
5467 }
5468 } else {
5469 /*
5470 * Normal handling of diag post reply with SMID.
5471 */
5472 cmd = slots->m_slot[SMID];
5473
5474 /*
5475 * print warning and return if the slot is empty
5476 */
5477 if (cmd == NULL) {
5478 mptsas_log(mpt, CE_WARN, "?NULL command for "
5479 "address reply in slot %d", SMID);
5480 return;
5481 }
5482 cmd->cmd_rfm = reply_addr;
5483 cmd->cmd_flags |= CFLAG_FINISHED;
5484 cv_broadcast(&mpt->m_fw_diag_cv);
5485 }
5486 return;
5487 default:
5488 mptsas_log(mpt, CE_WARN, "Unknown function 0x%x ", function);
5489 break;
5490 }
5491
5492 /*
5493 * Return the reply frame to the free queue.
5494 */
5495 ddi_put32(mpt->m_acc_free_queue_hdl,
5496 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index],
5497 reply_addr);
5498 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0,
5499 DDI_DMA_SYNC_FORDEV);
5500 if (++mpt->m_free_index == mpt->m_free_queue_depth) {
5501 mpt->m_free_index = 0;
5502 }
5503 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex,
5504 mpt->m_free_index);
5505
5506 if (cmd->cmd_flags & CFLAG_FW_CMD)
5507 return;
5508
5509 if (cmd->cmd_flags & CFLAG_RETRY) {
5510 /*
5511 * The target returned QFULL or busy, do not add this
5512 * pkt to the doneq since the hba will retry
5513 * this cmd.
5514 *
5515 * The pkt has already been resubmitted in
5516 * mptsas_handle_qfull() or in mptsas_check_scsi_io_error().
5517 * Remove this cmd_flag here.
5518 */
5519 cmd->cmd_flags &= ~CFLAG_RETRY;
5520 } else {
5521 mptsas_doneq_add(mpt, cmd);
5522 }
5523 }
5524
5525 #ifdef MPTSAS_DEBUG
5526 static uint8_t mptsas_last_sense[256];
5527 #endif
5528
5529 static void
mptsas_check_scsi_io_error(mptsas_t * mpt,pMpi2SCSIIOReply_t reply,mptsas_cmd_t * cmd)5530 mptsas_check_scsi_io_error(mptsas_t *mpt, pMpi2SCSIIOReply_t reply,
5531 mptsas_cmd_t *cmd)
5532 {
5533 uint8_t scsi_status, scsi_state;
5534 uint16_t ioc_status, cmd_rqs_len;
5535 uint32_t xferred, sensecount, responsedata, loginfo = 0;
5536 struct scsi_pkt *pkt;
5537 struct scsi_arq_status *arqstat;
5538 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
5539 uint8_t *sensedata = NULL;
5540 uint64_t sas_wwn;
5541 uint8_t phy;
5542 char wwn_str[MPTSAS_WWN_STRLEN];
5543
5544 scsi_status = ddi_get8(mpt->m_acc_reply_frame_hdl, &reply->SCSIStatus);
5545 ioc_status = ddi_get16(mpt->m_acc_reply_frame_hdl, &reply->IOCStatus);
5546 scsi_state = ddi_get8(mpt->m_acc_reply_frame_hdl, &reply->SCSIState);
5547 xferred = ddi_get32(mpt->m_acc_reply_frame_hdl, &reply->TransferCount);
5548 sensecount = ddi_get32(mpt->m_acc_reply_frame_hdl, &reply->SenseCount);
5549 responsedata = ddi_get32(mpt->m_acc_reply_frame_hdl,
5550 &reply->ResponseInfo);
5551
5552 if (ioc_status & MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) {
5553 sas_wwn = ptgt->m_addr.mta_wwn;
5554 phy = ptgt->m_phynum;
5555 if (sas_wwn == 0) {
5556 (void) sprintf(wwn_str, "p%x", phy);
5557 } else {
5558 (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn);
5559 }
5560 loginfo = ddi_get32(mpt->m_acc_reply_frame_hdl,
5561 &reply->IOCLogInfo);
5562 mptsas_log(mpt, CE_NOTE,
5563 "?Log info 0x%x received for target %d %s.\n"
5564 "\tscsi_status=0x%x, ioc_status=0x%x, scsi_state=0x%x",
5565 loginfo, Tgt(cmd), wwn_str, scsi_status, ioc_status,
5566 scsi_state);
5567 }
5568
5569 NDBG31(("\t\tscsi_status=0x%x, ioc_status=0x%x, scsi_state=0x%x",
5570 scsi_status, ioc_status, scsi_state));
5571
5572 pkt = CMD2PKT(cmd);
5573 *(pkt->pkt_scbp) = scsi_status;
5574
5575 if (loginfo == 0x31170000) {
5576 /*
5577 * if loginfo PL_LOGINFO_CODE_IO_DEVICE_MISSING_DELAY_RETRY
5578 * 0x31170000 comes, that means the device missing delay
5579 * is in progressing, the command need retry later.
5580 */
5581 *(pkt->pkt_scbp) = STATUS_BUSY;
5582 return;
5583 }
5584
5585 if ((scsi_state & MPI2_SCSI_STATE_NO_SCSI_STATUS) &&
5586 ((ioc_status & MPI2_IOCSTATUS_MASK) ==
5587 MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE)) {
5588 pkt->pkt_reason = CMD_INCOMPLETE;
5589 pkt->pkt_state |= STATE_GOT_BUS;
5590 if (ptgt->m_reset_delay == 0) {
5591 mptsas_set_throttle(mpt, ptgt,
5592 DRAIN_THROTTLE);
5593 }
5594 return;
5595 }
5596
5597 if (scsi_state & MPI2_SCSI_STATE_RESPONSE_INFO_VALID) {
5598 responsedata &= 0x000000FF;
5599 if (responsedata & MPTSAS_SCSI_RESPONSE_CODE_TLR_OFF) {
5600 mptsas_log(mpt, CE_NOTE, "Do not support the TLR\n");
5601 pkt->pkt_reason = CMD_TLR_OFF;
5602 return;
5603 }
5604 }
5605
5606
5607 switch (scsi_status) {
5608 case MPI2_SCSI_STATUS_CHECK_CONDITION:
5609 pkt->pkt_resid = (cmd->cmd_dmacount - xferred);
5610 arqstat = (void*)(pkt->pkt_scbp);
5611 arqstat->sts_rqpkt_status = *((struct scsi_status *)
5612 (pkt->pkt_scbp));
5613 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET |
5614 STATE_SENT_CMD | STATE_GOT_STATUS | STATE_ARQ_DONE);
5615 if (cmd->cmd_flags & CFLAG_XARQ) {
5616 pkt->pkt_state |= STATE_XARQ_DONE;
5617 }
5618 if (pkt->pkt_resid != cmd->cmd_dmacount) {
5619 pkt->pkt_state |= STATE_XFERRED_DATA;
5620 }
5621 arqstat->sts_rqpkt_reason = pkt->pkt_reason;
5622 arqstat->sts_rqpkt_state = pkt->pkt_state;
5623 arqstat->sts_rqpkt_state |= STATE_XFERRED_DATA;
5624 arqstat->sts_rqpkt_statistics = pkt->pkt_statistics;
5625 sensedata = (uint8_t *)&arqstat->sts_sensedata;
5626 cmd_rqs_len = cmd->cmd_extrqslen ?
5627 cmd->cmd_extrqslen : cmd->cmd_rqslen;
5628 (void) ddi_dma_sync(mpt->m_dma_req_sense_hdl, 0, 0,
5629 DDI_DMA_SYNC_FORKERNEL);
5630 #ifdef MPTSAS_DEBUG
5631 bcopy(cmd->cmd_arq_buf, mptsas_last_sense,
5632 ((cmd_rqs_len >= sizeof (mptsas_last_sense)) ?
5633 sizeof (mptsas_last_sense):cmd_rqs_len));
5634 #endif
5635 bcopy((uchar_t *)cmd->cmd_arq_buf, sensedata,
5636 ((cmd_rqs_len >= sensecount) ? sensecount :
5637 cmd_rqs_len));
5638 arqstat->sts_rqpkt_resid = (cmd_rqs_len - sensecount);
5639 cmd->cmd_flags |= CFLAG_CMDARQ;
5640 /*
5641 * Set proper status for pkt if autosense was valid
5642 */
5643 if (scsi_state & MPI2_SCSI_STATE_AUTOSENSE_VALID) {
5644 struct scsi_status zero_status = { 0 };
5645 arqstat->sts_rqpkt_status = zero_status;
5646 }
5647
5648 /*
5649 * ASC=0x47 is parity error
5650 * ASC=0x48 is initiator detected error received
5651 */
5652 if ((scsi_sense_key(sensedata) == KEY_ABORTED_COMMAND) &&
5653 ((scsi_sense_asc(sensedata) == 0x47) ||
5654 (scsi_sense_asc(sensedata) == 0x48))) {
5655 mptsas_log(mpt, CE_NOTE, "Aborted_command!");
5656 }
5657
5658 /*
5659 * ASC/ASCQ=0x3F/0x0E means report_luns data changed
5660 * ASC/ASCQ=0x25/0x00 means invalid lun
5661 */
5662 if (((scsi_sense_key(sensedata) == KEY_UNIT_ATTENTION) &&
5663 (scsi_sense_asc(sensedata) == 0x3F) &&
5664 (scsi_sense_ascq(sensedata) == 0x0E)) ||
5665 ((scsi_sense_key(sensedata) == KEY_ILLEGAL_REQUEST) &&
5666 (scsi_sense_asc(sensedata) == 0x25) &&
5667 (scsi_sense_ascq(sensedata) == 0x00))) {
5668 mptsas_topo_change_list_t *topo_node = NULL;
5669
5670 topo_node = kmem_zalloc(
5671 sizeof (mptsas_topo_change_list_t),
5672 KM_NOSLEEP);
5673 if (topo_node == NULL) {
5674 mptsas_log(mpt, CE_NOTE, "No memory"
5675 "resource for handle SAS dynamic"
5676 "reconfigure.\n");
5677 break;
5678 }
5679 topo_node->mpt = mpt;
5680 topo_node->event = MPTSAS_DR_EVENT_RECONFIG_TARGET;
5681 topo_node->un.phymask = ptgt->m_addr.mta_phymask;
5682 topo_node->devhdl = ptgt->m_devhdl;
5683 topo_node->object = (void *)ptgt;
5684 topo_node->flags = MPTSAS_TOPO_FLAG_LUN_ASSOCIATED;
5685
5686 if ((ddi_taskq_dispatch(mpt->m_dr_taskq,
5687 mptsas_handle_dr,
5688 (void *)topo_node,
5689 DDI_NOSLEEP)) != DDI_SUCCESS) {
5690 kmem_free(topo_node,
5691 sizeof (mptsas_topo_change_list_t));
5692 mptsas_log(mpt, CE_NOTE, "mptsas start taskq"
5693 "for handle SAS dynamic reconfigure"
5694 "failed. \n");
5695 }
5696 }
5697 break;
5698 case MPI2_SCSI_STATUS_GOOD:
5699 switch (ioc_status & MPI2_IOCSTATUS_MASK) {
5700 case MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE:
5701 pkt->pkt_reason = CMD_DEV_GONE;
5702 pkt->pkt_state |= STATE_GOT_BUS;
5703 if (ptgt->m_reset_delay == 0) {
5704 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE);
5705 }
5706 NDBG31(("lost disk for target%d, command:%x",
5707 Tgt(cmd), pkt->pkt_cdbp[0]));
5708 break;
5709 case MPI2_IOCSTATUS_SCSI_DATA_OVERRUN:
5710 NDBG31(("data overrun: xferred=%d", xferred));
5711 NDBG31(("dmacount=%d", cmd->cmd_dmacount));
5712 pkt->pkt_reason = CMD_DATA_OVR;
5713 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET
5714 | STATE_SENT_CMD | STATE_GOT_STATUS
5715 | STATE_XFERRED_DATA);
5716 pkt->pkt_resid = 0;
5717 break;
5718 case MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH:
5719 case MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN:
5720 NDBG31(("data underrun: xferred=%d", xferred));
5721 NDBG31(("dmacount=%d", cmd->cmd_dmacount));
5722 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET
5723 | STATE_SENT_CMD | STATE_GOT_STATUS);
5724 pkt->pkt_resid = (cmd->cmd_dmacount - xferred);
5725 if (pkt->pkt_resid != cmd->cmd_dmacount) {
5726 pkt->pkt_state |= STATE_XFERRED_DATA;
5727 }
5728 break;
5729 case MPI2_IOCSTATUS_SCSI_TASK_TERMINATED:
5730 if (cmd->cmd_active_expiration <= gethrtime()) {
5731 /*
5732 * When timeout requested, propagate
5733 * proper reason and statistics to
5734 * target drivers.
5735 */
5736 mptsas_set_pkt_reason(mpt, cmd, CMD_TIMEOUT,
5737 STAT_BUS_RESET | STAT_TIMEOUT);
5738 } else {
5739 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET,
5740 STAT_BUS_RESET);
5741 }
5742 break;
5743 case MPI2_IOCSTATUS_SCSI_IOC_TERMINATED:
5744 case MPI2_IOCSTATUS_SCSI_EXT_TERMINATED:
5745 mptsas_set_pkt_reason(mpt,
5746 cmd, CMD_RESET, STAT_DEV_RESET);
5747 break;
5748 case MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR:
5749 case MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR:
5750 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET);
5751 mptsas_set_pkt_reason(mpt,
5752 cmd, CMD_TERMINATED, STAT_TERMINATED);
5753 break;
5754 case MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES:
5755 case MPI2_IOCSTATUS_BUSY:
5756 /*
5757 * set throttles to drain
5758 */
5759 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
5760 ptgt = refhash_next(mpt->m_targets, ptgt)) {
5761 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE);
5762 }
5763
5764 /*
5765 * retry command
5766 */
5767 cmd->cmd_flags |= CFLAG_RETRY;
5768 cmd->cmd_pkt_flags |= FLAG_HEAD;
5769
5770 (void) mptsas_accept_pkt(mpt, cmd);
5771 break;
5772 default:
5773 mptsas_log(mpt, CE_WARN,
5774 "unknown ioc_status = %x\n", ioc_status);
5775 mptsas_log(mpt, CE_CONT, "scsi_state = %x, transfer "
5776 "count = %x, scsi_status = %x", scsi_state,
5777 xferred, scsi_status);
5778 break;
5779 }
5780 break;
5781 case MPI2_SCSI_STATUS_TASK_SET_FULL:
5782 mptsas_handle_qfull(mpt, cmd);
5783 break;
5784 case MPI2_SCSI_STATUS_BUSY:
5785 NDBG31(("scsi_status busy received"));
5786 break;
5787 case MPI2_SCSI_STATUS_RESERVATION_CONFLICT:
5788 NDBG31(("scsi_status reservation conflict received"));
5789 break;
5790 default:
5791 mptsas_log(mpt, CE_WARN, "scsi_status=%x, ioc_status=%x\n",
5792 scsi_status, ioc_status);
5793 mptsas_log(mpt, CE_WARN,
5794 "mptsas_process_intr: invalid scsi status\n");
5795 break;
5796 }
5797 }
5798
5799 static void
mptsas_check_task_mgt(mptsas_t * mpt,pMpi2SCSIManagementReply_t reply,mptsas_cmd_t * cmd)5800 mptsas_check_task_mgt(mptsas_t *mpt, pMpi2SCSIManagementReply_t reply,
5801 mptsas_cmd_t *cmd)
5802 {
5803 uint8_t task_type;
5804 uint16_t ioc_status;
5805 uint32_t log_info;
5806 uint16_t dev_handle;
5807 struct scsi_pkt *pkt = CMD2PKT(cmd);
5808
5809 task_type = ddi_get8(mpt->m_acc_reply_frame_hdl, &reply->TaskType);
5810 ioc_status = ddi_get16(mpt->m_acc_reply_frame_hdl, &reply->IOCStatus);
5811 log_info = ddi_get32(mpt->m_acc_reply_frame_hdl, &reply->IOCLogInfo);
5812 dev_handle = ddi_get16(mpt->m_acc_reply_frame_hdl, &reply->DevHandle);
5813
5814 if (ioc_status != MPI2_IOCSTATUS_SUCCESS) {
5815 mptsas_log(mpt, CE_WARN, "mptsas_check_task_mgt: Task 0x%x "
5816 "failed. IOCStatus=0x%x IOCLogInfo=0x%x target=%d\n",
5817 task_type, ioc_status, log_info, dev_handle);
5818 pkt->pkt_reason = CMD_INCOMPLETE;
5819 return;
5820 }
5821
5822 switch (task_type) {
5823 case MPI2_SCSITASKMGMT_TASKTYPE_ABORT_TASK:
5824 case MPI2_SCSITASKMGMT_TASKTYPE_CLEAR_TASK_SET:
5825 case MPI2_SCSITASKMGMT_TASKTYPE_QUERY_TASK:
5826 case MPI2_SCSITASKMGMT_TASKTYPE_CLR_ACA:
5827 case MPI2_SCSITASKMGMT_TASKTYPE_QRY_TASK_SET:
5828 case MPI2_SCSITASKMGMT_TASKTYPE_QRY_UNIT_ATTENTION:
5829 break;
5830 case MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET:
5831 case MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET:
5832 case MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET:
5833 /*
5834 * Check for invalid DevHandle of 0 in case application
5835 * sends bad command. DevHandle of 0 could cause problems.
5836 */
5837 if (dev_handle == 0) {
5838 mptsas_log(mpt, CE_WARN, "!Can't flush target with"
5839 " DevHandle of 0.");
5840 } else {
5841 mptsas_flush_target(mpt, dev_handle, Lun(cmd),
5842 task_type);
5843 }
5844 break;
5845 default:
5846 mptsas_log(mpt, CE_WARN, "Unknown task management type %d.",
5847 task_type);
5848 mptsas_log(mpt, CE_WARN, "ioc status = %x", ioc_status);
5849 break;
5850 }
5851 }
5852
5853 static void
mptsas_doneq_thread(mptsas_doneq_thread_arg_t * arg)5854 mptsas_doneq_thread(mptsas_doneq_thread_arg_t *arg)
5855 {
5856 mptsas_t *mpt = arg->mpt;
5857 uint64_t t = arg->t;
5858 mptsas_cmd_t *cmd;
5859 struct scsi_pkt *pkt;
5860 mptsas_doneq_thread_list_t *item = &mpt->m_doneq_thread_id[t];
5861
5862 mutex_enter(&item->mutex);
5863 while (item->flag & MPTSAS_DONEQ_THREAD_ACTIVE) {
5864 if (!item->doneq) {
5865 cv_wait(&item->cv, &item->mutex);
5866 }
5867 pkt = NULL;
5868 if ((cmd = mptsas_doneq_thread_rm(mpt, t)) != NULL) {
5869 cmd->cmd_flags |= CFLAG_COMPLETED;
5870 pkt = CMD2PKT(cmd);
5871 }
5872 mutex_exit(&item->mutex);
5873 if (pkt) {
5874 mptsas_pkt_comp(pkt, cmd);
5875 }
5876 mutex_enter(&item->mutex);
5877 }
5878 mutex_exit(&item->mutex);
5879 mutex_enter(&mpt->m_doneq_mutex);
5880 mpt->m_doneq_thread_n--;
5881 cv_broadcast(&mpt->m_doneq_thread_cv);
5882 mutex_exit(&mpt->m_doneq_mutex);
5883 }
5884
5885
5886 /*
5887 * mpt interrupt handler.
5888 */
5889 static uint_t
mptsas_intr(caddr_t arg1,caddr_t arg2)5890 mptsas_intr(caddr_t arg1, caddr_t arg2)
5891 {
5892 mptsas_t *mpt = (void *)arg1;
5893 pMpi2ReplyDescriptorsUnion_t reply_desc_union;
5894 uchar_t did_reply = FALSE;
5895
5896 NDBG1(("mptsas_intr: arg1 0x%p arg2 0x%p", (void *)arg1, (void *)arg2));
5897
5898 mutex_enter(&mpt->m_mutex);
5899
5900 /*
5901 * If interrupts are shared by two channels then check whether this
5902 * interrupt is genuinely for this channel by making sure first the
5903 * chip is in high power state.
5904 */
5905 if ((mpt->m_options & MPTSAS_OPT_PM) &&
5906 (mpt->m_power_level != PM_LEVEL_D0)) {
5907 mutex_exit(&mpt->m_mutex);
5908 return (DDI_INTR_UNCLAIMED);
5909 }
5910
5911 /*
5912 * If polling, interrupt was triggered by some shared interrupt because
5913 * IOC interrupts are disabled during polling, so polling routine will
5914 * handle any replies. Considering this, if polling is happening,
5915 * return with interrupt unclaimed.
5916 */
5917 if (mpt->m_polled_intr) {
5918 mutex_exit(&mpt->m_mutex);
5919 mptsas_log(mpt, CE_WARN, "mpt_sas: Unclaimed interrupt");
5920 return (DDI_INTR_UNCLAIMED);
5921 }
5922
5923 /*
5924 * Read the istat register.
5925 */
5926 if ((INTPENDING(mpt)) != 0) {
5927 /*
5928 * read fifo until empty.
5929 */
5930 #ifndef __lock_lint
5931 _NOTE(CONSTCOND)
5932 #endif
5933 while (TRUE) {
5934 (void) ddi_dma_sync(mpt->m_dma_post_queue_hdl, 0, 0,
5935 DDI_DMA_SYNC_FORCPU);
5936 reply_desc_union = (pMpi2ReplyDescriptorsUnion_t)
5937 MPTSAS_GET_NEXT_REPLY(mpt, mpt->m_post_index);
5938
5939 if (ddi_get32(mpt->m_acc_post_queue_hdl,
5940 &reply_desc_union->Words.Low) == 0xFFFFFFFF ||
5941 ddi_get32(mpt->m_acc_post_queue_hdl,
5942 &reply_desc_union->Words.High) == 0xFFFFFFFF) {
5943 break;
5944 }
5945
5946 /*
5947 * The reply is valid, process it according to its
5948 * type. Also, set a flag for updating the reply index
5949 * after they've all been processed.
5950 */
5951 did_reply = TRUE;
5952
5953 mptsas_process_intr(mpt, reply_desc_union);
5954
5955 /*
5956 * Increment post index and roll over if needed.
5957 */
5958 if (++mpt->m_post_index == mpt->m_post_queue_depth) {
5959 mpt->m_post_index = 0;
5960 }
5961 }
5962
5963 /*
5964 * Update the global reply index if at least one reply was
5965 * processed.
5966 */
5967 if (did_reply) {
5968 ddi_put32(mpt->m_datap,
5969 &mpt->m_reg->ReplyPostHostIndex, mpt->m_post_index);
5970 }
5971 } else {
5972 mutex_exit(&mpt->m_mutex);
5973 return (DDI_INTR_UNCLAIMED);
5974 }
5975 NDBG1(("mptsas_intr complete"));
5976
5977 /*
5978 * If no helper threads are created, process the doneq in ISR. If
5979 * helpers are created, use the doneq length as a metric to measure the
5980 * load on the interrupt CPU. If it is long enough, which indicates the
5981 * load is heavy, then we deliver the IO completions to the helpers.
5982 * This measurement has some limitations, although it is simple and
5983 * straightforward and works well for most of the cases at present.
5984 */
5985 if (!mpt->m_doneq_thread_n ||
5986 (mpt->m_doneq_len <= mpt->m_doneq_length_threshold)) {
5987 mptsas_doneq_empty(mpt);
5988 } else {
5989 mptsas_deliver_doneq_thread(mpt);
5990 }
5991
5992 /*
5993 * If there are queued cmd, start them now.
5994 */
5995 if (mpt->m_waitq != NULL) {
5996 mptsas_restart_waitq(mpt);
5997 }
5998
5999 mutex_exit(&mpt->m_mutex);
6000 return (DDI_INTR_CLAIMED);
6001 }
6002
6003 static void
mptsas_process_intr(mptsas_t * mpt,pMpi2ReplyDescriptorsUnion_t reply_desc_union)6004 mptsas_process_intr(mptsas_t *mpt,
6005 pMpi2ReplyDescriptorsUnion_t reply_desc_union)
6006 {
6007 uint8_t reply_type;
6008
6009 ASSERT(mutex_owned(&mpt->m_mutex));
6010
6011 /*
6012 * The reply is valid, process it according to its
6013 * type. Also, set a flag for updated the reply index
6014 * after they've all been processed.
6015 */
6016 reply_type = ddi_get8(mpt->m_acc_post_queue_hdl,
6017 &reply_desc_union->Default.ReplyFlags);
6018 reply_type &= MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
6019 if (reply_type == MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS ||
6020 reply_type == MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS) {
6021 mptsas_handle_scsi_io_success(mpt, reply_desc_union);
6022 } else if (reply_type == MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY) {
6023 mptsas_handle_address_reply(mpt, reply_desc_union);
6024 } else {
6025 mptsas_log(mpt, CE_WARN, "?Bad reply type %x", reply_type);
6026 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
6027 }
6028
6029 /*
6030 * Clear the reply descriptor for re-use and increment
6031 * index.
6032 */
6033 ddi_put64(mpt->m_acc_post_queue_hdl,
6034 &((uint64_t *)(void *)mpt->m_post_queue)[mpt->m_post_index],
6035 0xFFFFFFFFFFFFFFFF);
6036 (void) ddi_dma_sync(mpt->m_dma_post_queue_hdl, 0, 0,
6037 DDI_DMA_SYNC_FORDEV);
6038 }
6039
6040 /*
6041 * handle qfull condition
6042 */
6043 static void
mptsas_handle_qfull(mptsas_t * mpt,mptsas_cmd_t * cmd)6044 mptsas_handle_qfull(mptsas_t *mpt, mptsas_cmd_t *cmd)
6045 {
6046 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
6047
6048 if ((++cmd->cmd_qfull_retries > ptgt->m_qfull_retries) ||
6049 (ptgt->m_qfull_retries == 0)) {
6050 /*
6051 * We have exhausted the retries on QFULL, or,
6052 * the target driver has indicated that it
6053 * wants to handle QFULL itself by setting
6054 * qfull-retries capability to 0. In either case
6055 * we want the target driver's QFULL handling
6056 * to kick in. We do this by having pkt_reason
6057 * as CMD_CMPLT and pkt_scbp as STATUS_QFULL.
6058 */
6059 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE);
6060 } else {
6061 if (ptgt->m_reset_delay == 0) {
6062 ptgt->m_t_throttle =
6063 max((ptgt->m_t_ncmds - 2), 0);
6064 }
6065
6066 cmd->cmd_pkt_flags |= FLAG_HEAD;
6067 cmd->cmd_flags &= ~(CFLAG_TRANFLAG);
6068 cmd->cmd_flags |= CFLAG_RETRY;
6069
6070 (void) mptsas_accept_pkt(mpt, cmd);
6071
6072 /*
6073 * when target gives queue full status with no commands
6074 * outstanding (m_t_ncmds == 0), throttle is set to 0
6075 * (HOLD_THROTTLE), and the queue full handling start
6076 * (see psarc/1994/313); if there are commands outstanding,
6077 * throttle is set to (m_t_ncmds - 2)
6078 */
6079 if (ptgt->m_t_throttle == HOLD_THROTTLE) {
6080 /*
6081 * By setting throttle to QFULL_THROTTLE, we
6082 * avoid submitting new commands and in
6083 * mptsas_restart_cmd find out slots which need
6084 * their throttles to be cleared.
6085 */
6086 mptsas_set_throttle(mpt, ptgt, QFULL_THROTTLE);
6087 if (mpt->m_restart_cmd_timeid == 0) {
6088 mpt->m_restart_cmd_timeid =
6089 timeout(mptsas_restart_cmd, mpt,
6090 ptgt->m_qfull_retry_interval);
6091 }
6092 }
6093 }
6094 }
6095
6096 mptsas_phymask_t
mptsas_physport_to_phymask(mptsas_t * mpt,uint8_t physport)6097 mptsas_physport_to_phymask(mptsas_t *mpt, uint8_t physport)
6098 {
6099 mptsas_phymask_t phy_mask = 0;
6100 uint8_t i = 0;
6101
6102 NDBG20(("mptsas%d physport_to_phymask enter", mpt->m_instance));
6103
6104 ASSERT(mutex_owned(&mpt->m_mutex));
6105
6106 /*
6107 * If physport is 0xFF, this is a RAID volume. Use phymask of 0.
6108 */
6109 if (physport == 0xFF) {
6110 return (0);
6111 }
6112
6113 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
6114 if (mpt->m_phy_info[i].attached_devhdl &&
6115 (mpt->m_phy_info[i].phy_mask != 0) &&
6116 (mpt->m_phy_info[i].port_num == physport)) {
6117 phy_mask = mpt->m_phy_info[i].phy_mask;
6118 break;
6119 }
6120 }
6121 NDBG20(("mptsas%d physport_to_phymask:physport :%x phymask :%x, ",
6122 mpt->m_instance, physport, phy_mask));
6123 return (phy_mask);
6124 }
6125
6126 /*
6127 * mpt free device handle after device gone, by use of passthrough
6128 */
6129 static int
mptsas_free_devhdl(mptsas_t * mpt,uint16_t devhdl)6130 mptsas_free_devhdl(mptsas_t *mpt, uint16_t devhdl)
6131 {
6132 Mpi2SasIoUnitControlRequest_t req;
6133 Mpi2SasIoUnitControlReply_t rep;
6134 int ret;
6135
6136 ASSERT(mutex_owned(&mpt->m_mutex));
6137
6138 /*
6139 * Need to compose a SAS IO Unit Control request message
6140 * and call mptsas_do_passthru() function
6141 */
6142 bzero(&req, sizeof (req));
6143 bzero(&rep, sizeof (rep));
6144
6145 req.Function = MPI2_FUNCTION_SAS_IO_UNIT_CONTROL;
6146 req.Operation = MPI2_SAS_OP_REMOVE_DEVICE;
6147 req.DevHandle = LE_16(devhdl);
6148
6149 ret = mptsas_do_passthru(mpt, (uint8_t *)&req, (uint8_t *)&rep, NULL,
6150 sizeof (req), sizeof (rep), 0, MPTSAS_PASS_THRU_DIRECTION_NONE,
6151 NULL, 0, 60, FKIOCTL);
6152 if (ret != 0) {
6153 cmn_err(CE_WARN, "mptsas_free_devhdl: passthru SAS IO Unit "
6154 "Control error %d", ret);
6155 return (DDI_FAILURE);
6156 }
6157
6158 /* do passthrough success, check the ioc status */
6159 if (LE_16(rep.IOCStatus) != MPI2_IOCSTATUS_SUCCESS) {
6160 cmn_err(CE_WARN, "mptsas_free_devhdl: passthru SAS IO Unit "
6161 "Control IOCStatus %d", LE_16(rep.IOCStatus));
6162 return (DDI_FAILURE);
6163 }
6164
6165 return (DDI_SUCCESS);
6166 }
6167
6168 /*
6169 * We have a SATA target that has changed, which means the "bridge-port"
6170 * property must be updated to reflect the SAS WWN of the new attachment point.
6171 * This may change if a SATA device changes which bay, and therefore phy, it is
6172 * plugged into. This SATA device may be a multipath virtual device or may be a
6173 * physical device. We have to handle both cases.
6174 */
6175 static boolean_t
mptsas_update_sata_bridge(mptsas_t * mpt,dev_info_t * parent,mptsas_target_t * ptgt)6176 mptsas_update_sata_bridge(mptsas_t *mpt, dev_info_t *parent,
6177 mptsas_target_t *ptgt)
6178 {
6179 int rval;
6180 uint16_t dev_hdl;
6181 uint16_t pdev_hdl;
6182 uint64_t dev_sas_wwn;
6183 uint8_t physport;
6184 uint8_t phy_id;
6185 uint32_t page_address;
6186 uint16_t bay_num, enclosure, io_flags;
6187 uint32_t dev_info;
6188 char uabuf[SCSI_WWN_BUFLEN];
6189 dev_info_t *dip;
6190 mdi_pathinfo_t *pip;
6191
6192 mutex_enter(&mpt->m_mutex);
6193 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
6194 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | (uint32_t)ptgt->m_devhdl;
6195 rval = mptsas_get_sas_device_page0(mpt, page_address, &dev_hdl,
6196 &dev_sas_wwn, &dev_info, &physport, &phy_id, &pdev_hdl, &bay_num,
6197 &enclosure, &io_flags);
6198 mutex_exit(&mpt->m_mutex);
6199 if (rval != DDI_SUCCESS) {
6200 mptsas_log(mpt, CE_WARN, "unable to get SAS page 0 for "
6201 "handle %d", page_address);
6202 return (B_FALSE);
6203 }
6204
6205 if (scsi_wwn_to_wwnstr(dev_sas_wwn, 1, uabuf) == NULL) {
6206 mptsas_log(mpt, CE_WARN,
6207 "mptsas unable to format SATA bridge WWN");
6208 return (B_FALSE);
6209 }
6210
6211 if (mpt->m_mpxio_enable == TRUE && (pip = mptsas_find_path_addr(parent,
6212 ptgt->m_addr.mta_wwn, 0)) != NULL) {
6213 if (mdi_prop_update_string(pip, SCSI_ADDR_PROP_BRIDGE_PORT,
6214 uabuf) != DDI_SUCCESS) {
6215 mptsas_log(mpt, CE_WARN,
6216 "mptsas unable to create SCSI bridge port "
6217 "property for SATA device");
6218 return (B_FALSE);
6219 }
6220 return (B_TRUE);
6221 }
6222
6223 if ((dip = mptsas_find_child_addr(parent, ptgt->m_addr.mta_wwn,
6224 0)) != NULL) {
6225 if (ndi_prop_update_string(DDI_DEV_T_NONE, dip,
6226 SCSI_ADDR_PROP_BRIDGE_PORT, uabuf) != DDI_PROP_SUCCESS) {
6227 mptsas_log(mpt, CE_WARN,
6228 "mptsas unable to create SCSI bridge port "
6229 "property for SATA device");
6230 return (B_FALSE);
6231 }
6232 return (B_TRUE);
6233 }
6234
6235 mptsas_log(mpt, CE_WARN, "mptsas failed to find dev_info_t or "
6236 "mdi_pathinfo_t for target with WWN %016" PRIx64,
6237 ptgt->m_addr.mta_wwn);
6238
6239 return (B_FALSE);
6240 }
6241
6242 static void
mptsas_update_phymask(mptsas_t * mpt)6243 mptsas_update_phymask(mptsas_t *mpt)
6244 {
6245 mptsas_phymask_t mask = 0, phy_mask;
6246 char *phy_mask_name;
6247 uint8_t current_port;
6248 int i, j;
6249
6250 NDBG20(("mptsas%d update phymask ", mpt->m_instance));
6251
6252 ASSERT(mutex_owned(&mpt->m_mutex));
6253
6254 (void) mptsas_get_sas_io_unit_page(mpt);
6255
6256 phy_mask_name = kmem_zalloc(MPTSAS_MAX_PHYS, KM_SLEEP);
6257
6258 for (i = 0; i < mpt->m_num_phys; i++) {
6259 phy_mask = 0x00;
6260
6261 if (mpt->m_phy_info[i].attached_devhdl == 0)
6262 continue;
6263
6264 bzero(phy_mask_name, sizeof (phy_mask_name));
6265
6266 current_port = mpt->m_phy_info[i].port_num;
6267
6268 if ((mask & (1 << i)) != 0)
6269 continue;
6270
6271 for (j = 0; j < mpt->m_num_phys; j++) {
6272 if (mpt->m_phy_info[j].attached_devhdl &&
6273 (mpt->m_phy_info[j].port_num == current_port)) {
6274 phy_mask |= (1 << j);
6275 }
6276 }
6277 mask = mask | phy_mask;
6278
6279 for (j = 0; j < mpt->m_num_phys; j++) {
6280 if ((phy_mask >> j) & 0x01) {
6281 mpt->m_phy_info[j].phy_mask = phy_mask;
6282 }
6283 }
6284
6285 (void) sprintf(phy_mask_name, "%x", phy_mask);
6286
6287 mutex_exit(&mpt->m_mutex);
6288 /*
6289 * register a iport, if the port has already been existed
6290 * SCSA will do nothing and just return.
6291 */
6292 (void) scsi_hba_iport_register(mpt->m_dip, phy_mask_name);
6293 mutex_enter(&mpt->m_mutex);
6294 }
6295 kmem_free(phy_mask_name, MPTSAS_MAX_PHYS);
6296 NDBG20(("mptsas%d update phymask return", mpt->m_instance));
6297 }
6298
6299 /*
6300 * mptsas_handle_dr is a task handler for DR, the DR action includes:
6301 * 1. Directly attched Device Added/Removed.
6302 * 2. Expander Device Added/Removed.
6303 * 3. Indirectly Attached Device Added/Expander.
6304 * 4. LUNs of a existing device status change.
6305 * 5. RAID volume created/deleted.
6306 * 6. Member of RAID volume is released because of RAID deletion.
6307 * 7. Physical disks are removed because of RAID creation.
6308 */
6309 static void
mptsas_handle_dr(void * args)6310 mptsas_handle_dr(void *args)
6311 {
6312 mptsas_topo_change_list_t *topo_node = NULL;
6313 mptsas_topo_change_list_t *save_node = NULL;
6314 mptsas_t *mpt;
6315 dev_info_t *parent = NULL;
6316 mptsas_phymask_t phymask = 0;
6317 char *phy_mask_name;
6318 uint8_t flags = 0, physport = 0xff;
6319 uint8_t port_update = 0;
6320 uint_t event;
6321
6322 topo_node = (mptsas_topo_change_list_t *)args;
6323
6324 mpt = topo_node->mpt;
6325 event = topo_node->event;
6326 flags = topo_node->flags;
6327
6328 phy_mask_name = kmem_zalloc(MPTSAS_MAX_PHYS, KM_SLEEP);
6329
6330 NDBG20(("mptsas%d handle_dr enter", mpt->m_instance));
6331
6332 switch (event) {
6333 case MPTSAS_DR_EVENT_RECONFIG_TARGET:
6334 if ((flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) ||
6335 (flags == MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE) ||
6336 (flags == MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED)) {
6337 /*
6338 * Direct attached or expander attached device added
6339 * into system or a Phys Disk that is being unhidden.
6340 */
6341 port_update = 1;
6342 }
6343 break;
6344 case MPTSAS_DR_EVENT_RECONFIG_SMP:
6345 /*
6346 * New expander added into system, it must be the head
6347 * of topo_change_list_t
6348 */
6349 port_update = 1;
6350 break;
6351 default:
6352 port_update = 0;
6353 break;
6354 }
6355 /*
6356 * All cases port_update == 1 may cause initiator port form change
6357 */
6358 mutex_enter(&mpt->m_mutex);
6359 if (mpt->m_port_chng && port_update) {
6360 /*
6361 * mpt->m_port_chng flag indicates some PHYs of initiator
6362 * port have changed to online. So when expander added or
6363 * directly attached device online event come, we force to
6364 * update port information by issueing SAS IO Unit Page and
6365 * update PHYMASKs.
6366 */
6367 (void) mptsas_update_phymask(mpt);
6368 mpt->m_port_chng = 0;
6369
6370 }
6371 mutex_exit(&mpt->m_mutex);
6372 while (topo_node) {
6373 phymask = 0;
6374 if (parent == NULL) {
6375 physport = topo_node->un.physport;
6376 event = topo_node->event;
6377 flags = topo_node->flags;
6378 if (event & (MPTSAS_DR_EVENT_OFFLINE_TARGET |
6379 MPTSAS_DR_EVENT_OFFLINE_SMP)) {
6380 /*
6381 * For all offline events, phymask is known
6382 */
6383 phymask = topo_node->un.phymask;
6384 goto find_parent;
6385 }
6386 if (event & MPTSAS_TOPO_FLAG_REMOVE_HANDLE) {
6387 goto handle_topo_change;
6388 }
6389 if (flags & MPTSAS_TOPO_FLAG_LUN_ASSOCIATED) {
6390 phymask = topo_node->un.phymask;
6391 goto find_parent;
6392 }
6393
6394 if ((flags ==
6395 MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED) &&
6396 (event == MPTSAS_DR_EVENT_RECONFIG_TARGET)) {
6397 /*
6398 * There is no any field in IR_CONFIG_CHANGE
6399 * event indicate physport/phynum, let's get
6400 * parent after SAS Device Page0 request.
6401 */
6402 goto handle_topo_change;
6403 }
6404
6405 mutex_enter(&mpt->m_mutex);
6406 if (flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) {
6407 /*
6408 * If the direct attached device added or a
6409 * phys disk is being unhidden, argument
6410 * physport actually is PHY#, so we have to get
6411 * phymask according PHY#.
6412 */
6413 physport = mpt->m_phy_info[physport].port_num;
6414 }
6415
6416 /*
6417 * Translate physport to phymask so that we can search
6418 * parent dip.
6419 */
6420 phymask = mptsas_physport_to_phymask(mpt,
6421 physport);
6422 mutex_exit(&mpt->m_mutex);
6423
6424 find_parent:
6425 bzero(phy_mask_name, MPTSAS_MAX_PHYS);
6426 /*
6427 * For RAID topology change node, write the iport name
6428 * as v0.
6429 */
6430 if (flags & MPTSAS_TOPO_FLAG_RAID_ASSOCIATED) {
6431 (void) sprintf(phy_mask_name, "v0");
6432 } else {
6433 /*
6434 * phymask can bo 0 if the drive has been
6435 * pulled by the time an add event is
6436 * processed. If phymask is 0, just skip this
6437 * event and continue.
6438 */
6439 if (phymask == 0) {
6440 mutex_enter(&mpt->m_mutex);
6441 save_node = topo_node;
6442 topo_node = topo_node->next;
6443 ASSERT(save_node);
6444 kmem_free(save_node,
6445 sizeof (mptsas_topo_change_list_t));
6446 mutex_exit(&mpt->m_mutex);
6447
6448 parent = NULL;
6449 continue;
6450 }
6451 (void) sprintf(phy_mask_name, "%x", phymask);
6452 }
6453 parent = scsi_hba_iport_find(mpt->m_dip,
6454 phy_mask_name);
6455 if (parent == NULL) {
6456 mptsas_log(mpt, CE_WARN, "Failed to find an "
6457 "iport, should not happen!");
6458 goto out;
6459 }
6460
6461 }
6462 ASSERT(parent);
6463 handle_topo_change:
6464
6465 mutex_enter(&mpt->m_mutex);
6466 /*
6467 * If HBA is being reset, don't perform operations depending
6468 * on the IOC. We must free the topo list, however.
6469 */
6470 if (!mpt->m_in_reset) {
6471 mptsas_handle_topo_change(topo_node, parent);
6472 } else {
6473 NDBG20(("skipping topo change received during reset"));
6474 }
6475 save_node = topo_node;
6476 topo_node = topo_node->next;
6477 ASSERT(save_node);
6478 kmem_free(save_node, sizeof (mptsas_topo_change_list_t));
6479 mutex_exit(&mpt->m_mutex);
6480
6481 if ((flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) ||
6482 (flags == MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED) ||
6483 (flags == MPTSAS_TOPO_FLAG_RAID_ASSOCIATED)) {
6484 /*
6485 * If direct attached device associated, make sure
6486 * reset the parent before start the next one. But
6487 * all devices associated with expander shares the
6488 * parent. Also, reset parent if this is for RAID.
6489 */
6490 parent = NULL;
6491 }
6492 }
6493 out:
6494 kmem_free(phy_mask_name, MPTSAS_MAX_PHYS);
6495 }
6496
6497 static void
mptsas_handle_topo_change(mptsas_topo_change_list_t * topo_node,dev_info_t * parent)6498 mptsas_handle_topo_change(mptsas_topo_change_list_t *topo_node,
6499 dev_info_t *parent)
6500 {
6501 mptsas_target_t *ptgt = NULL;
6502 mptsas_smp_t *psmp = NULL;
6503 mptsas_t *mpt = (void *)topo_node->mpt;
6504 uint16_t devhdl;
6505 uint16_t attached_devhdl;
6506 uint64_t sas_wwn = 0;
6507 int rval = 0;
6508 uint32_t page_address;
6509 uint8_t phy, flags;
6510 char *addr = NULL;
6511 dev_info_t *lundip;
6512 int circ = 0, circ1 = 0;
6513 char attached_wwnstr[MPTSAS_WWN_STRLEN];
6514
6515 NDBG20(("mptsas%d handle_topo_change enter, devhdl 0x%x,"
6516 "event 0x%x, flags 0x%x", mpt->m_instance, topo_node->devhdl,
6517 topo_node->event, topo_node->flags));
6518
6519 ASSERT(mutex_owned(&mpt->m_mutex));
6520
6521 switch (topo_node->event) {
6522 case MPTSAS_DR_EVENT_RECONFIG_TARGET:
6523 {
6524 char *phy_mask_name;
6525 mptsas_phymask_t phymask = 0;
6526
6527 if (topo_node->flags == MPTSAS_TOPO_FLAG_RAID_ASSOCIATED) {
6528 /*
6529 * Get latest RAID info.
6530 */
6531 (void) mptsas_get_raid_info(mpt);
6532 ptgt = refhash_linear_search(mpt->m_targets,
6533 mptsas_target_eval_devhdl, &topo_node->devhdl);
6534 if (ptgt == NULL)
6535 break;
6536 } else {
6537 ptgt = (void *)topo_node->object;
6538 }
6539
6540 if (ptgt == NULL) {
6541 /*
6542 * If a Phys Disk was deleted, RAID info needs to be
6543 * updated to reflect the new topology.
6544 */
6545 (void) mptsas_get_raid_info(mpt);
6546
6547 /*
6548 * Get sas device page 0 by DevHandle to make sure if
6549 * SSP/SATA end device exist.
6550 */
6551 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
6552 MPI2_SAS_DEVICE_PGAD_FORM_MASK) |
6553 topo_node->devhdl;
6554
6555 rval = mptsas_get_target_device_info(mpt, page_address,
6556 &devhdl, &ptgt);
6557 if (rval == DEV_INFO_WRONG_DEVICE_TYPE) {
6558 mptsas_log(mpt, CE_NOTE,
6559 "mptsas_handle_topo_change: target %d is "
6560 "not a SAS/SATA device. \n",
6561 topo_node->devhdl);
6562 } else if (rval == DEV_INFO_FAIL_ALLOC) {
6563 mptsas_log(mpt, CE_NOTE,
6564 "mptsas_handle_topo_change: could not "
6565 "allocate memory. \n");
6566 } else if (rval == DEV_INFO_FAIL_GUID) {
6567 mptsas_log(mpt, CE_NOTE,
6568 "mptsas_handle_topo_change: could not "
6569 "get SATA GUID for target %d. \n",
6570 topo_node->devhdl);
6571 }
6572 /*
6573 * If rval is DEV_INFO_PHYS_DISK or indicates failure
6574 * then there is nothing else to do, just leave.
6575 */
6576 if (rval != DEV_INFO_SUCCESS) {
6577 return;
6578 }
6579 }
6580
6581 ASSERT(ptgt->m_devhdl == topo_node->devhdl);
6582
6583 mutex_exit(&mpt->m_mutex);
6584 flags = topo_node->flags;
6585
6586 if (flags == MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED) {
6587 phymask = ptgt->m_addr.mta_phymask;
6588 phy_mask_name = kmem_zalloc(MPTSAS_MAX_PHYS, KM_SLEEP);
6589 (void) sprintf(phy_mask_name, "%x", phymask);
6590 parent = scsi_hba_iport_find(mpt->m_dip,
6591 phy_mask_name);
6592 kmem_free(phy_mask_name, MPTSAS_MAX_PHYS);
6593 if (parent == NULL) {
6594 mptsas_log(mpt, CE_WARN, "Failed to find a "
6595 "iport for PD, should not happen!");
6596 mutex_enter(&mpt->m_mutex);
6597 break;
6598 }
6599 }
6600
6601 if (flags == MPTSAS_TOPO_FLAG_RAID_ASSOCIATED) {
6602 ndi_devi_enter(parent, &circ1);
6603 (void) mptsas_config_raid(parent, topo_node->devhdl,
6604 &lundip);
6605 ndi_devi_exit(parent, circ1);
6606 } else {
6607 /*
6608 * hold nexus for bus configure
6609 */
6610 ndi_devi_enter(scsi_vhci_dip, &circ);
6611 ndi_devi_enter(parent, &circ1);
6612 rval = mptsas_config_target(parent, ptgt);
6613 /*
6614 * release nexus for bus configure
6615 */
6616 ndi_devi_exit(parent, circ1);
6617 ndi_devi_exit(scsi_vhci_dip, circ);
6618
6619 /*
6620 * If this is a SATA device, make sure that the
6621 * bridge-port (the SAS WWN that the SATA device is
6622 * plugged into) is updated. This may change if a SATA
6623 * device changes which bay, and therefore phy, it is
6624 * plugged into.
6625 */
6626 if (IS_SATA_DEVICE(ptgt->m_deviceinfo)) {
6627 if (!mptsas_update_sata_bridge(mpt, parent,
6628 ptgt)) {
6629 mutex_enter(&mpt->m_mutex);
6630 return;
6631 }
6632 }
6633
6634 /*
6635 * Add parent's props for SMHBA support
6636 */
6637 if (flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) {
6638 bzero(attached_wwnstr,
6639 sizeof (attached_wwnstr));
6640 (void) sprintf(attached_wwnstr, "w%016"PRIx64,
6641 ptgt->m_addr.mta_wwn);
6642 if (ddi_prop_update_string(DDI_DEV_T_NONE,
6643 parent,
6644 SCSI_ADDR_PROP_ATTACHED_PORT,
6645 attached_wwnstr)
6646 != DDI_PROP_SUCCESS) {
6647 (void) ddi_prop_remove(DDI_DEV_T_NONE,
6648 parent,
6649 SCSI_ADDR_PROP_ATTACHED_PORT);
6650 mptsas_log(mpt, CE_WARN, "Failed to"
6651 "attached-port props");
6652 mutex_enter(&mpt->m_mutex);
6653 return;
6654 }
6655 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent,
6656 MPTSAS_NUM_PHYS, 1) !=
6657 DDI_PROP_SUCCESS) {
6658 (void) ddi_prop_remove(DDI_DEV_T_NONE,
6659 parent, MPTSAS_NUM_PHYS);
6660 mptsas_log(mpt, CE_WARN, "Failed to"
6661 " create num-phys props");
6662 mutex_enter(&mpt->m_mutex);
6663 return;
6664 }
6665
6666 /*
6667 * Update PHY info for smhba
6668 */
6669 mutex_enter(&mpt->m_mutex);
6670 if (mptsas_smhba_phy_init(mpt)) {
6671 mptsas_log(mpt, CE_WARN, "mptsas phy"
6672 " update failed");
6673 return;
6674 }
6675 mutex_exit(&mpt->m_mutex);
6676
6677 /*
6678 * topo_node->un.physport is really the PHY#
6679 * for direct attached devices
6680 */
6681 mptsas_smhba_set_one_phy_props(mpt, parent,
6682 topo_node->un.physport, &attached_devhdl);
6683
6684 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent,
6685 MPTSAS_VIRTUAL_PORT, 0) !=
6686 DDI_PROP_SUCCESS) {
6687 (void) ddi_prop_remove(DDI_DEV_T_NONE,
6688 parent, MPTSAS_VIRTUAL_PORT);
6689 mptsas_log(mpt, CE_WARN,
6690 "mptsas virtual-port"
6691 "port prop update failed");
6692 mutex_enter(&mpt->m_mutex);
6693 return;
6694 }
6695 }
6696 }
6697 mutex_enter(&mpt->m_mutex);
6698
6699 NDBG20(("mptsas%d handle_topo_change to online devhdl:%x, "
6700 "phymask:%x.", mpt->m_instance, ptgt->m_devhdl,
6701 ptgt->m_addr.mta_phymask));
6702 break;
6703 }
6704 case MPTSAS_DR_EVENT_OFFLINE_TARGET:
6705 {
6706 devhdl = topo_node->devhdl;
6707 ptgt = refhash_linear_search(mpt->m_targets,
6708 mptsas_target_eval_devhdl, &devhdl);
6709 if (ptgt == NULL)
6710 break;
6711
6712 sas_wwn = ptgt->m_addr.mta_wwn;
6713 phy = ptgt->m_phynum;
6714
6715 addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
6716
6717 if (sas_wwn) {
6718 (void) sprintf(addr, "w%016"PRIx64, sas_wwn);
6719 } else {
6720 (void) sprintf(addr, "p%x", phy);
6721 }
6722 ASSERT(ptgt->m_devhdl == devhdl);
6723
6724 if ((topo_node->flags == MPTSAS_TOPO_FLAG_RAID_ASSOCIATED) ||
6725 (topo_node->flags ==
6726 MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED)) {
6727 /*
6728 * Get latest RAID info if RAID volume status changes
6729 * or Phys Disk status changes
6730 */
6731 (void) mptsas_get_raid_info(mpt);
6732 }
6733 /*
6734 * Abort all outstanding command on the device
6735 */
6736 rval = mptsas_do_scsi_reset(mpt, devhdl);
6737 if (rval) {
6738 NDBG20(("mptsas%d handle_topo_change to reset target "
6739 "before offline devhdl:%x, phymask:%x, rval:%x",
6740 mpt->m_instance, ptgt->m_devhdl,
6741 ptgt->m_addr.mta_phymask, rval));
6742 }
6743
6744 mutex_exit(&mpt->m_mutex);
6745
6746 ndi_devi_enter(scsi_vhci_dip, &circ);
6747 ndi_devi_enter(parent, &circ1);
6748 rval = mptsas_offline_target(parent, addr);
6749 ndi_devi_exit(parent, circ1);
6750 ndi_devi_exit(scsi_vhci_dip, circ);
6751 NDBG20(("mptsas%d handle_topo_change to offline devhdl:%x, "
6752 "phymask:%x, rval:%x", mpt->m_instance,
6753 ptgt->m_devhdl, ptgt->m_addr.mta_phymask, rval));
6754
6755 kmem_free(addr, SCSI_MAXNAMELEN);
6756
6757 /*
6758 * Clear parent's props for SMHBA support
6759 */
6760 flags = topo_node->flags;
6761 if (flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) {
6762 bzero(attached_wwnstr, sizeof (attached_wwnstr));
6763 if (ddi_prop_update_string(DDI_DEV_T_NONE, parent,
6764 SCSI_ADDR_PROP_ATTACHED_PORT, attached_wwnstr) !=
6765 DDI_PROP_SUCCESS) {
6766 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent,
6767 SCSI_ADDR_PROP_ATTACHED_PORT);
6768 mptsas_log(mpt, CE_WARN, "mptsas attached port "
6769 "prop update failed");
6770 mutex_enter(&mpt->m_mutex);
6771 break;
6772 }
6773 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent,
6774 MPTSAS_NUM_PHYS, 0) !=
6775 DDI_PROP_SUCCESS) {
6776 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent,
6777 MPTSAS_NUM_PHYS);
6778 mptsas_log(mpt, CE_WARN, "mptsas num phys "
6779 "prop update failed");
6780 mutex_enter(&mpt->m_mutex);
6781 break;
6782 }
6783 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent,
6784 MPTSAS_VIRTUAL_PORT, 1) !=
6785 DDI_PROP_SUCCESS) {
6786 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent,
6787 MPTSAS_VIRTUAL_PORT);
6788 mptsas_log(mpt, CE_WARN, "mptsas virtual port "
6789 "prop update failed");
6790 mutex_enter(&mpt->m_mutex);
6791 break;
6792 }
6793 }
6794
6795 mutex_enter(&mpt->m_mutex);
6796 if (rval == DDI_SUCCESS) {
6797 refhash_remove(mpt->m_targets, ptgt);
6798 ptgt = NULL;
6799 } else {
6800 /*
6801 * clean DR_INTRANSITION flag to allow I/O down to
6802 * PHCI driver since failover finished.
6803 * Invalidate the devhdl
6804 */
6805 ptgt->m_devhdl = MPTSAS_INVALID_DEVHDL;
6806 ptgt->m_tgt_unconfigured = 0;
6807 mutex_enter(&mpt->m_tx_waitq_mutex);
6808 ptgt->m_dr_flag = MPTSAS_DR_INACTIVE;
6809 mutex_exit(&mpt->m_tx_waitq_mutex);
6810 }
6811
6812 /*
6813 * Send SAS IO Unit Control to free the dev handle
6814 */
6815 if ((flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) ||
6816 (flags == MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE)) {
6817 rval = mptsas_free_devhdl(mpt, devhdl);
6818
6819 NDBG20(("mptsas%d handle_topo_change to remove "
6820 "devhdl:%x, rval:%x", mpt->m_instance, devhdl,
6821 rval));
6822 }
6823
6824 break;
6825 }
6826 case MPTSAS_TOPO_FLAG_REMOVE_HANDLE:
6827 {
6828 devhdl = topo_node->devhdl;
6829 /*
6830 * If this is the remove handle event, do a reset first.
6831 */
6832 if (topo_node->event == MPTSAS_TOPO_FLAG_REMOVE_HANDLE) {
6833 rval = mptsas_do_scsi_reset(mpt, devhdl);
6834 if (rval) {
6835 NDBG20(("mpt%d reset target before remove "
6836 "devhdl:%x, rval:%x", mpt->m_instance,
6837 devhdl, rval));
6838 }
6839 }
6840
6841 /*
6842 * Send SAS IO Unit Control to free the dev handle
6843 */
6844 rval = mptsas_free_devhdl(mpt, devhdl);
6845 NDBG20(("mptsas%d handle_topo_change to remove "
6846 "devhdl:%x, rval:%x", mpt->m_instance, devhdl,
6847 rval));
6848 break;
6849 }
6850 case MPTSAS_DR_EVENT_RECONFIG_SMP:
6851 {
6852 mptsas_smp_t smp;
6853 dev_info_t *smpdip;
6854
6855 devhdl = topo_node->devhdl;
6856
6857 page_address = (MPI2_SAS_EXPAND_PGAD_FORM_HNDL &
6858 MPI2_SAS_EXPAND_PGAD_FORM_MASK) | (uint32_t)devhdl;
6859 rval = mptsas_get_sas_expander_page0(mpt, page_address, &smp);
6860 if (rval != DDI_SUCCESS) {
6861 mptsas_log(mpt, CE_WARN, "failed to online smp, "
6862 "handle %x", devhdl);
6863 return;
6864 }
6865
6866 psmp = mptsas_smp_alloc(mpt, &smp);
6867 if (psmp == NULL) {
6868 return;
6869 }
6870
6871 mutex_exit(&mpt->m_mutex);
6872 ndi_devi_enter(parent, &circ1);
6873 (void) mptsas_online_smp(parent, psmp, &smpdip);
6874 ndi_devi_exit(parent, circ1);
6875
6876 mutex_enter(&mpt->m_mutex);
6877 break;
6878 }
6879 case MPTSAS_DR_EVENT_OFFLINE_SMP:
6880 {
6881 devhdl = topo_node->devhdl;
6882 uint32_t dev_info;
6883
6884 psmp = refhash_linear_search(mpt->m_smp_targets,
6885 mptsas_smp_eval_devhdl, &devhdl);
6886 if (psmp == NULL)
6887 break;
6888 /*
6889 * The mptsas_smp_t data is released only if the dip is offlined
6890 * successfully.
6891 */
6892 mutex_exit(&mpt->m_mutex);
6893
6894 ndi_devi_enter(parent, &circ1);
6895 rval = mptsas_offline_smp(parent, psmp, NDI_DEVI_REMOVE);
6896 ndi_devi_exit(parent, circ1);
6897
6898 dev_info = psmp->m_deviceinfo;
6899 if ((dev_info & DEVINFO_DIRECT_ATTACHED) ==
6900 DEVINFO_DIRECT_ATTACHED) {
6901 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent,
6902 MPTSAS_VIRTUAL_PORT, 1) !=
6903 DDI_PROP_SUCCESS) {
6904 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent,
6905 MPTSAS_VIRTUAL_PORT);
6906 mptsas_log(mpt, CE_WARN, "mptsas virtual port "
6907 "prop update failed");
6908 mutex_enter(&mpt->m_mutex);
6909 return;
6910 }
6911 /*
6912 * Check whether the smp connected to the iport,
6913 */
6914 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent,
6915 MPTSAS_NUM_PHYS, 0) !=
6916 DDI_PROP_SUCCESS) {
6917 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent,
6918 MPTSAS_NUM_PHYS);
6919 mptsas_log(mpt, CE_WARN, "mptsas num phys"
6920 "prop update failed");
6921 mutex_enter(&mpt->m_mutex);
6922 return;
6923 }
6924 /*
6925 * Clear parent's attached-port props
6926 */
6927 bzero(attached_wwnstr, sizeof (attached_wwnstr));
6928 if (ddi_prop_update_string(DDI_DEV_T_NONE, parent,
6929 SCSI_ADDR_PROP_ATTACHED_PORT, attached_wwnstr) !=
6930 DDI_PROP_SUCCESS) {
6931 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent,
6932 SCSI_ADDR_PROP_ATTACHED_PORT);
6933 mptsas_log(mpt, CE_WARN, "mptsas attached port "
6934 "prop update failed");
6935 mutex_enter(&mpt->m_mutex);
6936 return;
6937 }
6938 }
6939
6940 mutex_enter(&mpt->m_mutex);
6941 NDBG20(("mptsas%d handle_topo_change to remove devhdl:%x, "
6942 "rval:%x", mpt->m_instance, psmp->m_devhdl, rval));
6943 if (rval == DDI_SUCCESS) {
6944 refhash_remove(mpt->m_smp_targets, psmp);
6945 } else {
6946 psmp->m_devhdl = MPTSAS_INVALID_DEVHDL;
6947 }
6948
6949 bzero(attached_wwnstr, sizeof (attached_wwnstr));
6950
6951 break;
6952 }
6953 default:
6954 return;
6955 }
6956 }
6957
6958 /*
6959 * Record the event if its type is enabled in mpt instance by ioctl.
6960 */
6961 static void
mptsas_record_event(void * args)6962 mptsas_record_event(void *args)
6963 {
6964 m_replyh_arg_t *replyh_arg;
6965 pMpi2EventNotificationReply_t eventreply;
6966 uint32_t event, rfm;
6967 mptsas_t *mpt;
6968 int i, j;
6969 uint16_t event_data_len;
6970 boolean_t sendAEN = FALSE;
6971
6972 replyh_arg = (m_replyh_arg_t *)args;
6973 rfm = replyh_arg->rfm;
6974 mpt = replyh_arg->mpt;
6975
6976 eventreply = (pMpi2EventNotificationReply_t)
6977 (mpt->m_reply_frame + (rfm -
6978 (mpt->m_reply_frame_dma_addr & 0xffffffffu)));
6979 event = ddi_get16(mpt->m_acc_reply_frame_hdl, &eventreply->Event);
6980
6981
6982 /*
6983 * Generate a system event to let anyone who cares know that a
6984 * LOG_ENTRY_ADDED event has occurred. This is sent no matter what the
6985 * event mask is set to.
6986 */
6987 if (event == MPI2_EVENT_LOG_ENTRY_ADDED) {
6988 sendAEN = TRUE;
6989 }
6990
6991 /*
6992 * Record the event only if it is not masked. Determine which dword
6993 * and bit of event mask to test.
6994 */
6995 i = (uint8_t)(event / 32);
6996 j = (uint8_t)(event % 32);
6997 if ((i < 4) && ((1 << j) & mpt->m_event_mask[i])) {
6998 i = mpt->m_event_index;
6999 mpt->m_events[i].Type = event;
7000 mpt->m_events[i].Number = ++mpt->m_event_number;
7001 bzero(mpt->m_events[i].Data, MPTSAS_MAX_EVENT_DATA_LENGTH * 4);
7002 event_data_len = ddi_get16(mpt->m_acc_reply_frame_hdl,
7003 &eventreply->EventDataLength);
7004
7005 if (event_data_len > 0) {
7006 /*
7007 * Limit data to size in m_event entry
7008 */
7009 if (event_data_len > MPTSAS_MAX_EVENT_DATA_LENGTH) {
7010 event_data_len = MPTSAS_MAX_EVENT_DATA_LENGTH;
7011 }
7012 for (j = 0; j < event_data_len; j++) {
7013 mpt->m_events[i].Data[j] =
7014 ddi_get32(mpt->m_acc_reply_frame_hdl,
7015 &(eventreply->EventData[j]));
7016 }
7017
7018 /*
7019 * check for index wrap-around
7020 */
7021 if (++i == MPTSAS_EVENT_QUEUE_SIZE) {
7022 i = 0;
7023 }
7024 mpt->m_event_index = (uint8_t)i;
7025
7026 /*
7027 * Set flag to send the event.
7028 */
7029 sendAEN = TRUE;
7030 }
7031 }
7032
7033 /*
7034 * Generate a system event if flag is set to let anyone who cares know
7035 * that an event has occurred.
7036 */
7037 if (sendAEN) {
7038 (void) ddi_log_sysevent(mpt->m_dip, DDI_VENDOR_LSI, "MPT_SAS",
7039 "SAS", NULL, NULL, DDI_NOSLEEP);
7040 }
7041 }
7042
7043 #define SMP_RESET_IN_PROGRESS MPI2_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS
7044 /*
7045 * handle sync events from ioc in interrupt
7046 * return value:
7047 * DDI_SUCCESS: The event is handled by this func
7048 * DDI_FAILURE: Event is not handled
7049 */
7050 static int
mptsas_handle_event_sync(void * args)7051 mptsas_handle_event_sync(void *args)
7052 {
7053 m_replyh_arg_t *replyh_arg;
7054 pMpi2EventNotificationReply_t eventreply;
7055 uint32_t event, rfm;
7056 mptsas_t *mpt;
7057 uint_t iocstatus;
7058
7059 replyh_arg = (m_replyh_arg_t *)args;
7060 rfm = replyh_arg->rfm;
7061 mpt = replyh_arg->mpt;
7062
7063 ASSERT(mutex_owned(&mpt->m_mutex));
7064
7065 eventreply = (pMpi2EventNotificationReply_t)
7066 (mpt->m_reply_frame + (rfm -
7067 (mpt->m_reply_frame_dma_addr & 0xffffffffu)));
7068 event = ddi_get16(mpt->m_acc_reply_frame_hdl, &eventreply->Event);
7069
7070 if ((iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl,
7071 &eventreply->IOCStatus)) != 0) {
7072 if (iocstatus == MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) {
7073 mptsas_log(mpt, CE_WARN,
7074 "!mptsas_handle_event_sync: event 0x%x, "
7075 "IOCStatus=0x%x, "
7076 "IOCLogInfo=0x%x", event, iocstatus,
7077 ddi_get32(mpt->m_acc_reply_frame_hdl,
7078 &eventreply->IOCLogInfo));
7079 } else {
7080 mptsas_log(mpt, CE_WARN,
7081 "mptsas_handle_event_sync: event 0x%x, "
7082 "IOCStatus=0x%x, "
7083 "(IOCLogInfo=0x%x)", event, iocstatus,
7084 ddi_get32(mpt->m_acc_reply_frame_hdl,
7085 &eventreply->IOCLogInfo));
7086 }
7087 }
7088
7089 /*
7090 * figure out what kind of event we got and handle accordingly
7091 */
7092 switch (event) {
7093 case MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST:
7094 {
7095 pMpi2EventDataSasTopologyChangeList_t sas_topo_change_list;
7096 uint8_t num_entries, expstatus, phy;
7097 uint8_t phystatus, physport, state, i;
7098 uint8_t start_phy_num, link_rate;
7099 uint16_t dev_handle, reason_code;
7100 uint16_t enc_handle, expd_handle;
7101 char string[80], curr[80], prev[80];
7102 mptsas_topo_change_list_t *topo_head = NULL;
7103 mptsas_topo_change_list_t *topo_tail = NULL;
7104 mptsas_topo_change_list_t *topo_node = NULL;
7105 mptsas_target_t *ptgt;
7106 mptsas_smp_t *psmp;
7107 uint8_t flags = 0, exp_flag;
7108 smhba_info_t *pSmhba = NULL;
7109
7110 NDBG20(("mptsas_handle_event_sync: SAS topology change"));
7111
7112 sas_topo_change_list = (pMpi2EventDataSasTopologyChangeList_t)
7113 eventreply->EventData;
7114
7115 enc_handle = ddi_get16(mpt->m_acc_reply_frame_hdl,
7116 &sas_topo_change_list->EnclosureHandle);
7117 expd_handle = ddi_get16(mpt->m_acc_reply_frame_hdl,
7118 &sas_topo_change_list->ExpanderDevHandle);
7119 num_entries = ddi_get8(mpt->m_acc_reply_frame_hdl,
7120 &sas_topo_change_list->NumEntries);
7121 start_phy_num = ddi_get8(mpt->m_acc_reply_frame_hdl,
7122 &sas_topo_change_list->StartPhyNum);
7123 expstatus = ddi_get8(mpt->m_acc_reply_frame_hdl,
7124 &sas_topo_change_list->ExpStatus);
7125 physport = ddi_get8(mpt->m_acc_reply_frame_hdl,
7126 &sas_topo_change_list->PhysicalPort);
7127
7128 string[0] = 0;
7129 if (expd_handle) {
7130 flags = MPTSAS_TOPO_FLAG_EXPANDER_ASSOCIATED;
7131 switch (expstatus) {
7132 case MPI2_EVENT_SAS_TOPO_ES_ADDED:
7133 (void) sprintf(string, " added");
7134 /*
7135 * New expander device added
7136 */
7137 mpt->m_port_chng = 1;
7138 topo_node = kmem_zalloc(
7139 sizeof (mptsas_topo_change_list_t),
7140 KM_SLEEP);
7141 topo_node->mpt = mpt;
7142 topo_node->event = MPTSAS_DR_EVENT_RECONFIG_SMP;
7143 topo_node->un.physport = physport;
7144 topo_node->devhdl = expd_handle;
7145 topo_node->flags = flags;
7146 topo_node->object = NULL;
7147 if (topo_head == NULL) {
7148 topo_head = topo_tail = topo_node;
7149 } else {
7150 topo_tail->next = topo_node;
7151 topo_tail = topo_node;
7152 }
7153 break;
7154 case MPI2_EVENT_SAS_TOPO_ES_NOT_RESPONDING:
7155 (void) sprintf(string, " not responding, "
7156 "removed");
7157 psmp = refhash_linear_search(mpt->m_smp_targets,
7158 mptsas_smp_eval_devhdl, &expd_handle);
7159 if (psmp == NULL)
7160 break;
7161
7162 topo_node = kmem_zalloc(
7163 sizeof (mptsas_topo_change_list_t),
7164 KM_SLEEP);
7165 topo_node->mpt = mpt;
7166 topo_node->un.phymask =
7167 psmp->m_addr.mta_phymask;
7168 topo_node->event = MPTSAS_DR_EVENT_OFFLINE_SMP;
7169 topo_node->devhdl = expd_handle;
7170 topo_node->flags = flags;
7171 topo_node->object = NULL;
7172 if (topo_head == NULL) {
7173 topo_head = topo_tail = topo_node;
7174 } else {
7175 topo_tail->next = topo_node;
7176 topo_tail = topo_node;
7177 }
7178 break;
7179 case MPI2_EVENT_SAS_TOPO_ES_RESPONDING:
7180 break;
7181 case MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING:
7182 (void) sprintf(string, " not responding, "
7183 "delaying removal");
7184 break;
7185 default:
7186 break;
7187 }
7188 } else {
7189 flags = MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE;
7190 }
7191
7192 NDBG20(("SAS TOPOLOGY CHANGE for enclosure %x expander %x%s\n",
7193 enc_handle, expd_handle, string));
7194 for (i = 0; i < num_entries; i++) {
7195 phy = i + start_phy_num;
7196 phystatus = ddi_get8(mpt->m_acc_reply_frame_hdl,
7197 &sas_topo_change_list->PHY[i].PhyStatus);
7198 dev_handle = ddi_get16(mpt->m_acc_reply_frame_hdl,
7199 &sas_topo_change_list->PHY[i].AttachedDevHandle);
7200 reason_code = phystatus & MPI2_EVENT_SAS_TOPO_RC_MASK;
7201 /*
7202 * Filter out processing of Phy Vacant Status unless
7203 * the reason code is "Not Responding". Process all
7204 * other combinations of Phy Status and Reason Codes.
7205 */
7206 if ((phystatus &
7207 MPI2_EVENT_SAS_TOPO_PHYSTATUS_VACANT) &&
7208 (reason_code !=
7209 MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING)) {
7210 continue;
7211 }
7212 curr[0] = 0;
7213 prev[0] = 0;
7214 string[0] = 0;
7215 switch (reason_code) {
7216 case MPI2_EVENT_SAS_TOPO_RC_TARG_ADDED:
7217 {
7218 NDBG20(("mptsas%d phy %d physical_port %d "
7219 "dev_handle %d added", mpt->m_instance, phy,
7220 physport, dev_handle));
7221 link_rate = ddi_get8(mpt->m_acc_reply_frame_hdl,
7222 &sas_topo_change_list->PHY[i].LinkRate);
7223 state = (link_rate &
7224 MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK) >>
7225 MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT;
7226 switch (state) {
7227 case MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED:
7228 (void) sprintf(curr, "is disabled");
7229 break;
7230 case MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED:
7231 (void) sprintf(curr, "is offline, "
7232 "failed speed negotiation");
7233 break;
7234 case MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE:
7235 (void) sprintf(curr, "SATA OOB "
7236 "complete");
7237 break;
7238 case SMP_RESET_IN_PROGRESS:
7239 (void) sprintf(curr, "SMP reset in "
7240 "progress");
7241 break;
7242 case MPI2_EVENT_SAS_TOPO_LR_RATE_1_5:
7243 (void) sprintf(curr, "is online at "
7244 "1.5 Gbps");
7245 break;
7246 case MPI2_EVENT_SAS_TOPO_LR_RATE_3_0:
7247 (void) sprintf(curr, "is online at 3.0 "
7248 "Gbps");
7249 break;
7250 case MPI2_EVENT_SAS_TOPO_LR_RATE_6_0:
7251 (void) sprintf(curr, "is online at 6.0 "
7252 "Gbps");
7253 break;
7254 case MPI25_EVENT_SAS_TOPO_LR_RATE_12_0:
7255 (void) sprintf(curr,
7256 "is online at 12.0 Gbps");
7257 break;
7258 default:
7259 (void) sprintf(curr, "state is "
7260 "unknown");
7261 break;
7262 }
7263 /*
7264 * New target device added into the system.
7265 * Set association flag according to if an
7266 * expander is used or not.
7267 */
7268 exp_flag =
7269 MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE;
7270 if (flags ==
7271 MPTSAS_TOPO_FLAG_EXPANDER_ASSOCIATED) {
7272 flags = exp_flag;
7273 }
7274 topo_node = kmem_zalloc(
7275 sizeof (mptsas_topo_change_list_t),
7276 KM_SLEEP);
7277 topo_node->mpt = mpt;
7278 topo_node->event =
7279 MPTSAS_DR_EVENT_RECONFIG_TARGET;
7280 if (expd_handle == 0) {
7281 /*
7282 * Per MPI 2, if expander dev handle
7283 * is 0, it's a directly attached
7284 * device. So driver use PHY to decide
7285 * which iport is associated
7286 */
7287 physport = phy;
7288 mpt->m_port_chng = 1;
7289 }
7290 topo_node->un.physport = physport;
7291 topo_node->devhdl = dev_handle;
7292 topo_node->flags = flags;
7293 topo_node->object = NULL;
7294 if (topo_head == NULL) {
7295 topo_head = topo_tail = topo_node;
7296 } else {
7297 topo_tail->next = topo_node;
7298 topo_tail = topo_node;
7299 }
7300 break;
7301 }
7302 case MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING:
7303 {
7304 NDBG20(("mptsas%d phy %d physical_port %d "
7305 "dev_handle %d removed", mpt->m_instance,
7306 phy, physport, dev_handle));
7307 /*
7308 * Set association flag according to if an
7309 * expander is used or not.
7310 */
7311 exp_flag =
7312 MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE;
7313 if (flags ==
7314 MPTSAS_TOPO_FLAG_EXPANDER_ASSOCIATED) {
7315 flags = exp_flag;
7316 }
7317 /*
7318 * Target device is removed from the system
7319 * Before the device is really offline from
7320 * from system.
7321 */
7322 ptgt = refhash_linear_search(mpt->m_targets,
7323 mptsas_target_eval_devhdl, &dev_handle);
7324 /*
7325 * If ptgt is NULL here, it means that the
7326 * DevHandle is not in the hash table. This is
7327 * reasonable sometimes. For example, if a
7328 * disk was pulled, then added, then pulled
7329 * again, the disk will not have been put into
7330 * the hash table because the add event will
7331 * have an invalid phymask. BUT, this does not
7332 * mean that the DevHandle is invalid. The
7333 * controller will still have a valid DevHandle
7334 * that must be removed. To do this, use the
7335 * MPTSAS_TOPO_FLAG_REMOVE_HANDLE event.
7336 */
7337 if (ptgt == NULL) {
7338 topo_node = kmem_zalloc(
7339 sizeof (mptsas_topo_change_list_t),
7340 KM_SLEEP);
7341 topo_node->mpt = mpt;
7342 topo_node->un.phymask = 0;
7343 topo_node->event =
7344 MPTSAS_TOPO_FLAG_REMOVE_HANDLE;
7345 topo_node->devhdl = dev_handle;
7346 topo_node->flags = flags;
7347 topo_node->object = NULL;
7348 if (topo_head == NULL) {
7349 topo_head = topo_tail =
7350 topo_node;
7351 } else {
7352 topo_tail->next = topo_node;
7353 topo_tail = topo_node;
7354 }
7355 break;
7356 }
7357
7358 /*
7359 * Update DR flag immediately avoid I/O failure
7360 * before failover finish. Pay attention to the
7361 * mutex protect, we need grab m_tx_waitq_mutex
7362 * during set m_dr_flag because we won't add
7363 * the following command into waitq, instead,
7364 * we need return TRAN_BUSY in the tran_start
7365 * context.
7366 */
7367 mutex_enter(&mpt->m_tx_waitq_mutex);
7368 ptgt->m_dr_flag = MPTSAS_DR_INTRANSITION;
7369 mutex_exit(&mpt->m_tx_waitq_mutex);
7370
7371 topo_node = kmem_zalloc(
7372 sizeof (mptsas_topo_change_list_t),
7373 KM_SLEEP);
7374 topo_node->mpt = mpt;
7375 topo_node->un.phymask =
7376 ptgt->m_addr.mta_phymask;
7377 topo_node->event =
7378 MPTSAS_DR_EVENT_OFFLINE_TARGET;
7379 topo_node->devhdl = dev_handle;
7380 topo_node->flags = flags;
7381 topo_node->object = NULL;
7382 if (topo_head == NULL) {
7383 topo_head = topo_tail = topo_node;
7384 } else {
7385 topo_tail->next = topo_node;
7386 topo_tail = topo_node;
7387 }
7388 break;
7389 }
7390 case MPI2_EVENT_SAS_TOPO_RC_PHY_CHANGED:
7391 link_rate = ddi_get8(mpt->m_acc_reply_frame_hdl,
7392 &sas_topo_change_list->PHY[i].LinkRate);
7393 state = (link_rate &
7394 MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK) >>
7395 MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT;
7396 pSmhba = &mpt->m_phy_info[i].smhba_info;
7397 pSmhba->negotiated_link_rate = state;
7398 switch (state) {
7399 case MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED:
7400 (void) sprintf(curr, "is disabled");
7401 mptsas_smhba_log_sysevent(mpt,
7402 ESC_SAS_PHY_EVENT,
7403 SAS_PHY_REMOVE,
7404 &mpt->m_phy_info[i].smhba_info);
7405 mpt->m_phy_info[i].smhba_info.
7406 negotiated_link_rate
7407 = 0x1;
7408 break;
7409 case MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED:
7410 (void) sprintf(curr, "is offline, "
7411 "failed speed negotiation");
7412 mptsas_smhba_log_sysevent(mpt,
7413 ESC_SAS_PHY_EVENT,
7414 SAS_PHY_OFFLINE,
7415 &mpt->m_phy_info[i].smhba_info);
7416 break;
7417 case MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE:
7418 (void) sprintf(curr, "SATA OOB "
7419 "complete");
7420 break;
7421 case SMP_RESET_IN_PROGRESS:
7422 (void) sprintf(curr, "SMP reset in "
7423 "progress");
7424 break;
7425 case MPI2_EVENT_SAS_TOPO_LR_RATE_1_5:
7426 (void) sprintf(curr, "is online at "
7427 "1.5 Gbps");
7428 if ((expd_handle == 0) &&
7429 (enc_handle == 1)) {
7430 mpt->m_port_chng = 1;
7431 }
7432 mptsas_smhba_log_sysevent(mpt,
7433 ESC_SAS_PHY_EVENT,
7434 SAS_PHY_ONLINE,
7435 &mpt->m_phy_info[i].smhba_info);
7436 break;
7437 case MPI2_EVENT_SAS_TOPO_LR_RATE_3_0:
7438 (void) sprintf(curr, "is online at 3.0 "
7439 "Gbps");
7440 if ((expd_handle == 0) &&
7441 (enc_handle == 1)) {
7442 mpt->m_port_chng = 1;
7443 }
7444 mptsas_smhba_log_sysevent(mpt,
7445 ESC_SAS_PHY_EVENT,
7446 SAS_PHY_ONLINE,
7447 &mpt->m_phy_info[i].smhba_info);
7448 break;
7449 case MPI2_EVENT_SAS_TOPO_LR_RATE_6_0:
7450 (void) sprintf(curr, "is online at "
7451 "6.0 Gbps");
7452 if ((expd_handle == 0) &&
7453 (enc_handle == 1)) {
7454 mpt->m_port_chng = 1;
7455 }
7456 mptsas_smhba_log_sysevent(mpt,
7457 ESC_SAS_PHY_EVENT,
7458 SAS_PHY_ONLINE,
7459 &mpt->m_phy_info[i].smhba_info);
7460 break;
7461 case MPI25_EVENT_SAS_TOPO_LR_RATE_12_0:
7462 (void) sprintf(curr, "is online at "
7463 "12.0 Gbps");
7464 if ((expd_handle == 0) &&
7465 (enc_handle == 1)) {
7466 mpt->m_port_chng = 1;
7467 }
7468 mptsas_smhba_log_sysevent(mpt,
7469 ESC_SAS_PHY_EVENT,
7470 SAS_PHY_ONLINE,
7471 &mpt->m_phy_info[i].smhba_info);
7472 break;
7473 default:
7474 (void) sprintf(curr, "state is "
7475 "unknown");
7476 break;
7477 }
7478
7479 state = (link_rate &
7480 MPI2_EVENT_SAS_TOPO_LR_PREV_MASK) >>
7481 MPI2_EVENT_SAS_TOPO_LR_PREV_SHIFT;
7482 switch (state) {
7483 case MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED:
7484 (void) sprintf(prev, ", was disabled");
7485 break;
7486 case MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED:
7487 (void) sprintf(prev, ", was offline, "
7488 "failed speed negotiation");
7489 break;
7490 case MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE:
7491 (void) sprintf(prev, ", was SATA OOB "
7492 "complete");
7493 break;
7494 case SMP_RESET_IN_PROGRESS:
7495 (void) sprintf(prev, ", was SMP reset "
7496 "in progress");
7497 break;
7498 case MPI2_EVENT_SAS_TOPO_LR_RATE_1_5:
7499 (void) sprintf(prev, ", was online at "
7500 "1.5 Gbps");
7501 break;
7502 case MPI2_EVENT_SAS_TOPO_LR_RATE_3_0:
7503 (void) sprintf(prev, ", was online at "
7504 "3.0 Gbps");
7505 break;
7506 case MPI2_EVENT_SAS_TOPO_LR_RATE_6_0:
7507 (void) sprintf(prev, ", was online at "
7508 "6.0 Gbps");
7509 break;
7510 case MPI25_EVENT_SAS_TOPO_LR_RATE_12_0:
7511 (void) sprintf(prev, ", was online at "
7512 "12.0 Gbps");
7513 break;
7514 default:
7515 break;
7516 }
7517 (void) sprintf(&string[strlen(string)], "link "
7518 "changed, ");
7519 break;
7520 case MPI2_EVENT_SAS_TOPO_RC_NO_CHANGE:
7521 continue;
7522 case MPI2_EVENT_SAS_TOPO_RC_DELAY_NOT_RESPONDING:
7523 (void) sprintf(&string[strlen(string)],
7524 "target not responding, delaying "
7525 "removal");
7526 break;
7527 }
7528 NDBG20(("mptsas%d phy %d DevHandle %x, %s%s%s\n",
7529 mpt->m_instance, phy, dev_handle, string, curr,
7530 prev));
7531 }
7532 if (topo_head != NULL) {
7533 /*
7534 * Launch DR taskq to handle topology change
7535 */
7536 if ((ddi_taskq_dispatch(mpt->m_dr_taskq,
7537 mptsas_handle_dr, (void *)topo_head,
7538 DDI_NOSLEEP)) != DDI_SUCCESS) {
7539 while (topo_head != NULL) {
7540 topo_node = topo_head;
7541 topo_head = topo_head->next;
7542 kmem_free(topo_node,
7543 sizeof (mptsas_topo_change_list_t));
7544 }
7545 mptsas_log(mpt, CE_NOTE, "mptsas start taskq "
7546 "for handle SAS DR event failed. \n");
7547 }
7548 }
7549 break;
7550 }
7551 case MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST:
7552 {
7553 Mpi2EventDataIrConfigChangeList_t *irChangeList;
7554 mptsas_topo_change_list_t *topo_head = NULL;
7555 mptsas_topo_change_list_t *topo_tail = NULL;
7556 mptsas_topo_change_list_t *topo_node = NULL;
7557 mptsas_target_t *ptgt;
7558 uint8_t num_entries, i, reason;
7559 uint16_t volhandle, diskhandle;
7560
7561 irChangeList = (pMpi2EventDataIrConfigChangeList_t)
7562 eventreply->EventData;
7563 num_entries = ddi_get8(mpt->m_acc_reply_frame_hdl,
7564 &irChangeList->NumElements);
7565
7566 NDBG20(("mptsas%d IR_CONFIGURATION_CHANGE_LIST event received",
7567 mpt->m_instance));
7568
7569 for (i = 0; i < num_entries; i++) {
7570 reason = ddi_get8(mpt->m_acc_reply_frame_hdl,
7571 &irChangeList->ConfigElement[i].ReasonCode);
7572 volhandle = ddi_get16(mpt->m_acc_reply_frame_hdl,
7573 &irChangeList->ConfigElement[i].VolDevHandle);
7574 diskhandle = ddi_get16(mpt->m_acc_reply_frame_hdl,
7575 &irChangeList->ConfigElement[i].PhysDiskDevHandle);
7576
7577 switch (reason) {
7578 case MPI2_EVENT_IR_CHANGE_RC_ADDED:
7579 case MPI2_EVENT_IR_CHANGE_RC_VOLUME_CREATED:
7580 {
7581 NDBG20(("mptsas %d volume added\n",
7582 mpt->m_instance));
7583
7584 topo_node = kmem_zalloc(
7585 sizeof (mptsas_topo_change_list_t),
7586 KM_SLEEP);
7587
7588 topo_node->mpt = mpt;
7589 topo_node->event =
7590 MPTSAS_DR_EVENT_RECONFIG_TARGET;
7591 topo_node->un.physport = 0xff;
7592 topo_node->devhdl = volhandle;
7593 topo_node->flags =
7594 MPTSAS_TOPO_FLAG_RAID_ASSOCIATED;
7595 topo_node->object = NULL;
7596 if (topo_head == NULL) {
7597 topo_head = topo_tail = topo_node;
7598 } else {
7599 topo_tail->next = topo_node;
7600 topo_tail = topo_node;
7601 }
7602 break;
7603 }
7604 case MPI2_EVENT_IR_CHANGE_RC_REMOVED:
7605 case MPI2_EVENT_IR_CHANGE_RC_VOLUME_DELETED:
7606 {
7607 NDBG20(("mptsas %d volume deleted\n",
7608 mpt->m_instance));
7609 ptgt = refhash_linear_search(mpt->m_targets,
7610 mptsas_target_eval_devhdl, &volhandle);
7611 if (ptgt == NULL)
7612 break;
7613
7614 /*
7615 * Clear any flags related to volume
7616 */
7617 (void) mptsas_delete_volume(mpt, volhandle);
7618
7619 /*
7620 * Update DR flag immediately avoid I/O failure
7621 */
7622 mutex_enter(&mpt->m_tx_waitq_mutex);
7623 ptgt->m_dr_flag = MPTSAS_DR_INTRANSITION;
7624 mutex_exit(&mpt->m_tx_waitq_mutex);
7625
7626 topo_node = kmem_zalloc(
7627 sizeof (mptsas_topo_change_list_t),
7628 KM_SLEEP);
7629 topo_node->mpt = mpt;
7630 topo_node->un.phymask =
7631 ptgt->m_addr.mta_phymask;
7632 topo_node->event =
7633 MPTSAS_DR_EVENT_OFFLINE_TARGET;
7634 topo_node->devhdl = volhandle;
7635 topo_node->flags =
7636 MPTSAS_TOPO_FLAG_RAID_ASSOCIATED;
7637 topo_node->object = (void *)ptgt;
7638 if (topo_head == NULL) {
7639 topo_head = topo_tail = topo_node;
7640 } else {
7641 topo_tail->next = topo_node;
7642 topo_tail = topo_node;
7643 }
7644 break;
7645 }
7646 case MPI2_EVENT_IR_CHANGE_RC_PD_CREATED:
7647 case MPI2_EVENT_IR_CHANGE_RC_HIDE:
7648 {
7649 ptgt = refhash_linear_search(mpt->m_targets,
7650 mptsas_target_eval_devhdl, &diskhandle);
7651 if (ptgt == NULL)
7652 break;
7653
7654 /*
7655 * Update DR flag immediately avoid I/O failure
7656 */
7657 mutex_enter(&mpt->m_tx_waitq_mutex);
7658 ptgt->m_dr_flag = MPTSAS_DR_INTRANSITION;
7659 mutex_exit(&mpt->m_tx_waitq_mutex);
7660
7661 topo_node = kmem_zalloc(
7662 sizeof (mptsas_topo_change_list_t),
7663 KM_SLEEP);
7664 topo_node->mpt = mpt;
7665 topo_node->un.phymask =
7666 ptgt->m_addr.mta_phymask;
7667 topo_node->event =
7668 MPTSAS_DR_EVENT_OFFLINE_TARGET;
7669 topo_node->devhdl = diskhandle;
7670 topo_node->flags =
7671 MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED;
7672 topo_node->object = (void *)ptgt;
7673 if (topo_head == NULL) {
7674 topo_head = topo_tail = topo_node;
7675 } else {
7676 topo_tail->next = topo_node;
7677 topo_tail = topo_node;
7678 }
7679 break;
7680 }
7681 case MPI2_EVENT_IR_CHANGE_RC_UNHIDE:
7682 case MPI2_EVENT_IR_CHANGE_RC_PD_DELETED:
7683 {
7684 /*
7685 * The physical drive is released by a IR
7686 * volume. But we cannot get the the physport
7687 * or phynum from the event data, so we only
7688 * can get the physport/phynum after SAS
7689 * Device Page0 request for the devhdl.
7690 */
7691 topo_node = kmem_zalloc(
7692 sizeof (mptsas_topo_change_list_t),
7693 KM_SLEEP);
7694 topo_node->mpt = mpt;
7695 topo_node->un.phymask = 0;
7696 topo_node->event =
7697 MPTSAS_DR_EVENT_RECONFIG_TARGET;
7698 topo_node->devhdl = diskhandle;
7699 topo_node->flags =
7700 MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED;
7701 topo_node->object = NULL;
7702 mpt->m_port_chng = 1;
7703 if (topo_head == NULL) {
7704 topo_head = topo_tail = topo_node;
7705 } else {
7706 topo_tail->next = topo_node;
7707 topo_tail = topo_node;
7708 }
7709 break;
7710 }
7711 default:
7712 break;
7713 }
7714 }
7715
7716 if (topo_head != NULL) {
7717 /*
7718 * Launch DR taskq to handle topology change
7719 */
7720 if ((ddi_taskq_dispatch(mpt->m_dr_taskq,
7721 mptsas_handle_dr, (void *)topo_head,
7722 DDI_NOSLEEP)) != DDI_SUCCESS) {
7723 while (topo_head != NULL) {
7724 topo_node = topo_head;
7725 topo_head = topo_head->next;
7726 kmem_free(topo_node,
7727 sizeof (mptsas_topo_change_list_t));
7728 }
7729 mptsas_log(mpt, CE_NOTE, "mptsas start taskq "
7730 "for handle SAS DR event failed. \n");
7731 }
7732 }
7733 break;
7734 }
7735 default:
7736 return (DDI_FAILURE);
7737 }
7738
7739 return (DDI_SUCCESS);
7740 }
7741
7742 /*
7743 * handle events from ioc
7744 */
7745 static void
mptsas_handle_event(void * args)7746 mptsas_handle_event(void *args)
7747 {
7748 m_replyh_arg_t *replyh_arg;
7749 pMpi2EventNotificationReply_t eventreply;
7750 uint32_t event, iocloginfo, rfm;
7751 uint32_t status;
7752 uint8_t port;
7753 mptsas_t *mpt;
7754 uint_t iocstatus;
7755
7756 replyh_arg = (m_replyh_arg_t *)args;
7757 rfm = replyh_arg->rfm;
7758 mpt = replyh_arg->mpt;
7759
7760 mutex_enter(&mpt->m_mutex);
7761 /*
7762 * If HBA is being reset, drop incoming event.
7763 */
7764 if (mpt->m_in_reset) {
7765 NDBG20(("dropping event received prior to reset"));
7766 mutex_exit(&mpt->m_mutex);
7767 return;
7768 }
7769
7770 eventreply = (pMpi2EventNotificationReply_t)
7771 (mpt->m_reply_frame + (rfm -
7772 (mpt->m_reply_frame_dma_addr & 0xffffffffu)));
7773 event = ddi_get16(mpt->m_acc_reply_frame_hdl, &eventreply->Event);
7774
7775 if ((iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl,
7776 &eventreply->IOCStatus)) != 0) {
7777 if (iocstatus == MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) {
7778 mptsas_log(mpt, CE_WARN,
7779 "!mptsas_handle_event: IOCStatus=0x%x, "
7780 "IOCLogInfo=0x%x", iocstatus,
7781 ddi_get32(mpt->m_acc_reply_frame_hdl,
7782 &eventreply->IOCLogInfo));
7783 } else {
7784 mptsas_log(mpt, CE_WARN,
7785 "mptsas_handle_event: IOCStatus=0x%x, "
7786 "IOCLogInfo=0x%x", iocstatus,
7787 ddi_get32(mpt->m_acc_reply_frame_hdl,
7788 &eventreply->IOCLogInfo));
7789 }
7790 }
7791
7792 /*
7793 * figure out what kind of event we got and handle accordingly
7794 */
7795 switch (event) {
7796 case MPI2_EVENT_LOG_ENTRY_ADDED:
7797 break;
7798 case MPI2_EVENT_LOG_DATA:
7799 iocloginfo = ddi_get32(mpt->m_acc_reply_frame_hdl,
7800 &eventreply->IOCLogInfo);
7801 NDBG20(("mptsas %d log info %x received.\n", mpt->m_instance,
7802 iocloginfo));
7803 break;
7804 case MPI2_EVENT_STATE_CHANGE:
7805 NDBG20(("mptsas%d state change.", mpt->m_instance));
7806 break;
7807 case MPI2_EVENT_HARD_RESET_RECEIVED:
7808 NDBG20(("mptsas%d event change.", mpt->m_instance));
7809 break;
7810 case MPI2_EVENT_SAS_DISCOVERY:
7811 {
7812 MPI2_EVENT_DATA_SAS_DISCOVERY *sasdiscovery;
7813 char string[80];
7814 uint8_t rc;
7815
7816 sasdiscovery =
7817 (pMpi2EventDataSasDiscovery_t)eventreply->EventData;
7818
7819 rc = ddi_get8(mpt->m_acc_reply_frame_hdl,
7820 &sasdiscovery->ReasonCode);
7821 port = ddi_get8(mpt->m_acc_reply_frame_hdl,
7822 &sasdiscovery->PhysicalPort);
7823 status = ddi_get32(mpt->m_acc_reply_frame_hdl,
7824 &sasdiscovery->DiscoveryStatus);
7825
7826 string[0] = 0;
7827 switch (rc) {
7828 case MPI2_EVENT_SAS_DISC_RC_STARTED:
7829 (void) sprintf(string, "STARTING");
7830 break;
7831 case MPI2_EVENT_SAS_DISC_RC_COMPLETED:
7832 (void) sprintf(string, "COMPLETED");
7833 break;
7834 default:
7835 (void) sprintf(string, "UNKNOWN");
7836 break;
7837 }
7838
7839 NDBG20(("SAS DISCOVERY is %s for port %d, status %x", string,
7840 port, status));
7841
7842 break;
7843 }
7844 case MPI2_EVENT_EVENT_CHANGE:
7845 NDBG20(("mptsas%d event change.", mpt->m_instance));
7846 break;
7847 case MPI2_EVENT_TASK_SET_FULL:
7848 {
7849 pMpi2EventDataTaskSetFull_t taskfull;
7850
7851 taskfull = (pMpi2EventDataTaskSetFull_t)eventreply->EventData;
7852
7853 NDBG20(("TASK_SET_FULL received for mptsas%d, depth %d\n",
7854 mpt->m_instance, ddi_get16(mpt->m_acc_reply_frame_hdl,
7855 &taskfull->CurrentDepth)));
7856 break;
7857 }
7858 case MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST:
7859 {
7860 /*
7861 * SAS TOPOLOGY CHANGE LIST Event has already been handled
7862 * in mptsas_handle_event_sync() of interrupt context
7863 */
7864 break;
7865 }
7866 case MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE:
7867 {
7868 pMpi2EventDataSasEnclDevStatusChange_t encstatus;
7869 uint8_t rc;
7870 uint16_t enchdl;
7871 char string[80];
7872 mptsas_enclosure_t *mep;
7873
7874 encstatus = (pMpi2EventDataSasEnclDevStatusChange_t)
7875 eventreply->EventData;
7876
7877 rc = ddi_get8(mpt->m_acc_reply_frame_hdl,
7878 &encstatus->ReasonCode);
7879 enchdl = ddi_get16(mpt->m_acc_reply_frame_hdl,
7880 &encstatus->EnclosureHandle);
7881
7882 switch (rc) {
7883 case MPI2_EVENT_SAS_ENCL_RC_ADDED:
7884 (void) sprintf(string, "added");
7885 break;
7886 case MPI2_EVENT_SAS_ENCL_RC_NOT_RESPONDING:
7887 mep = mptsas_enc_lookup(mpt, enchdl);
7888 if (mep != NULL) {
7889 list_remove(&mpt->m_enclosures, mep);
7890 mptsas_enc_free(mep);
7891 mep = NULL;
7892 }
7893 (void) sprintf(string, ", not responding");
7894 break;
7895 default:
7896 break;
7897 }
7898 NDBG20(("mptsas%d ENCLOSURE STATUS CHANGE for enclosure "
7899 "%x%s\n", mpt->m_instance,
7900 ddi_get16(mpt->m_acc_reply_frame_hdl,
7901 &encstatus->EnclosureHandle), string));
7902
7903 /*
7904 * No matter what has happened, update all of our device state
7905 * for enclosures, by retriggering an evaluation.
7906 */
7907 mpt->m_done_traverse_enc = 0;
7908 mptsas_update_hashtab(mpt);
7909 break;
7910 }
7911
7912 /*
7913 * MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE is handled by
7914 * mptsas_handle_event_sync,in here just send ack message.
7915 */
7916 case MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE:
7917 {
7918 pMpi2EventDataSasDeviceStatusChange_t statuschange;
7919 uint8_t rc;
7920 uint16_t devhdl;
7921 uint64_t wwn = 0;
7922 uint32_t wwn_lo, wwn_hi;
7923
7924 statuschange = (pMpi2EventDataSasDeviceStatusChange_t)
7925 eventreply->EventData;
7926 rc = ddi_get8(mpt->m_acc_reply_frame_hdl,
7927 &statuschange->ReasonCode);
7928 wwn_lo = ddi_get32(mpt->m_acc_reply_frame_hdl,
7929 (uint32_t *)(void *)&statuschange->SASAddress);
7930 wwn_hi = ddi_get32(mpt->m_acc_reply_frame_hdl,
7931 (uint32_t *)(void *)&statuschange->SASAddress + 1);
7932 wwn = ((uint64_t)wwn_hi << 32) | wwn_lo;
7933 devhdl = ddi_get16(mpt->m_acc_reply_frame_hdl,
7934 &statuschange->DevHandle);
7935
7936 NDBG13(("MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE wwn is %"PRIx64,
7937 wwn));
7938
7939 switch (rc) {
7940 case MPI2_EVENT_SAS_DEV_STAT_RC_SMART_DATA:
7941 NDBG20(("SMART data received, ASC/ASCQ = %02x/%02x",
7942 ddi_get8(mpt->m_acc_reply_frame_hdl,
7943 &statuschange->ASC),
7944 ddi_get8(mpt->m_acc_reply_frame_hdl,
7945 &statuschange->ASCQ)));
7946 break;
7947
7948 case MPI2_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED:
7949 NDBG20(("Device not supported"));
7950 break;
7951
7952 case MPI2_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET:
7953 NDBG20(("IOC internally generated the Target Reset "
7954 "for devhdl:%x", devhdl));
7955 break;
7956
7957 case MPI2_EVENT_SAS_DEV_STAT_RC_CMP_INTERNAL_DEV_RESET:
7958 NDBG20(("IOC's internally generated Target Reset "
7959 "completed for devhdl:%x", devhdl));
7960 break;
7961
7962 case MPI2_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL:
7963 NDBG20(("IOC internally generated Abort Task"));
7964 break;
7965
7966 case MPI2_EVENT_SAS_DEV_STAT_RC_CMP_TASK_ABORT_INTERNAL:
7967 NDBG20(("IOC's internally generated Abort Task "
7968 "completed"));
7969 break;
7970
7971 case MPI2_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL:
7972 NDBG20(("IOC internally generated Abort Task Set"));
7973 break;
7974
7975 case MPI2_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL:
7976 NDBG20(("IOC internally generated Clear Task Set"));
7977 break;
7978
7979 case MPI2_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL:
7980 NDBG20(("IOC internally generated Query Task"));
7981 break;
7982
7983 case MPI2_EVENT_SAS_DEV_STAT_RC_ASYNC_NOTIFICATION:
7984 NDBG20(("Device sent an Asynchronous Notification"));
7985 break;
7986
7987 default:
7988 break;
7989 }
7990 break;
7991 }
7992 case MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST:
7993 {
7994 /*
7995 * IR TOPOLOGY CHANGE LIST Event has already been handled
7996 * in mpt_handle_event_sync() of interrupt context
7997 */
7998 break;
7999 }
8000 case MPI2_EVENT_IR_OPERATION_STATUS:
8001 {
8002 Mpi2EventDataIrOperationStatus_t *irOpStatus;
8003 char reason_str[80];
8004 uint8_t rc, percent;
8005 uint16_t handle;
8006
8007 irOpStatus = (pMpi2EventDataIrOperationStatus_t)
8008 eventreply->EventData;
8009 rc = ddi_get8(mpt->m_acc_reply_frame_hdl,
8010 &irOpStatus->RAIDOperation);
8011 percent = ddi_get8(mpt->m_acc_reply_frame_hdl,
8012 &irOpStatus->PercentComplete);
8013 handle = ddi_get16(mpt->m_acc_reply_frame_hdl,
8014 &irOpStatus->VolDevHandle);
8015
8016 switch (rc) {
8017 case MPI2_EVENT_IR_RAIDOP_RESYNC:
8018 (void) sprintf(reason_str, "resync");
8019 break;
8020 case MPI2_EVENT_IR_RAIDOP_ONLINE_CAP_EXPANSION:
8021 (void) sprintf(reason_str, "online capacity "
8022 "expansion");
8023 break;
8024 case MPI2_EVENT_IR_RAIDOP_CONSISTENCY_CHECK:
8025 (void) sprintf(reason_str, "consistency check");
8026 break;
8027 default:
8028 (void) sprintf(reason_str, "unknown reason %x",
8029 rc);
8030 }
8031
8032 NDBG20(("mptsas%d raid operational status: (%s)"
8033 "\thandle(0x%04x), percent complete(%d)\n",
8034 mpt->m_instance, reason_str, handle, percent));
8035 break;
8036 }
8037 case MPI2_EVENT_SAS_BROADCAST_PRIMITIVE:
8038 {
8039 pMpi2EventDataSasBroadcastPrimitive_t sas_broadcast;
8040 uint8_t phy_num;
8041 uint8_t primitive;
8042
8043 sas_broadcast = (pMpi2EventDataSasBroadcastPrimitive_t)
8044 eventreply->EventData;
8045
8046 phy_num = ddi_get8(mpt->m_acc_reply_frame_hdl,
8047 &sas_broadcast->PhyNum);
8048 primitive = ddi_get8(mpt->m_acc_reply_frame_hdl,
8049 &sas_broadcast->Primitive);
8050
8051 switch (primitive) {
8052 case MPI2_EVENT_PRIMITIVE_CHANGE:
8053 mptsas_smhba_log_sysevent(mpt,
8054 ESC_SAS_HBA_PORT_BROADCAST,
8055 SAS_PORT_BROADCAST_CHANGE,
8056 &mpt->m_phy_info[phy_num].smhba_info);
8057 break;
8058 case MPI2_EVENT_PRIMITIVE_SES:
8059 mptsas_smhba_log_sysevent(mpt,
8060 ESC_SAS_HBA_PORT_BROADCAST,
8061 SAS_PORT_BROADCAST_SES,
8062 &mpt->m_phy_info[phy_num].smhba_info);
8063 break;
8064 case MPI2_EVENT_PRIMITIVE_EXPANDER:
8065 mptsas_smhba_log_sysevent(mpt,
8066 ESC_SAS_HBA_PORT_BROADCAST,
8067 SAS_PORT_BROADCAST_D01_4,
8068 &mpt->m_phy_info[phy_num].smhba_info);
8069 break;
8070 case MPI2_EVENT_PRIMITIVE_ASYNCHRONOUS_EVENT:
8071 mptsas_smhba_log_sysevent(mpt,
8072 ESC_SAS_HBA_PORT_BROADCAST,
8073 SAS_PORT_BROADCAST_D04_7,
8074 &mpt->m_phy_info[phy_num].smhba_info);
8075 break;
8076 case MPI2_EVENT_PRIMITIVE_RESERVED3:
8077 mptsas_smhba_log_sysevent(mpt,
8078 ESC_SAS_HBA_PORT_BROADCAST,
8079 SAS_PORT_BROADCAST_D16_7,
8080 &mpt->m_phy_info[phy_num].smhba_info);
8081 break;
8082 case MPI2_EVENT_PRIMITIVE_RESERVED4:
8083 mptsas_smhba_log_sysevent(mpt,
8084 ESC_SAS_HBA_PORT_BROADCAST,
8085 SAS_PORT_BROADCAST_D29_7,
8086 &mpt->m_phy_info[phy_num].smhba_info);
8087 break;
8088 case MPI2_EVENT_PRIMITIVE_CHANGE0_RESERVED:
8089 mptsas_smhba_log_sysevent(mpt,
8090 ESC_SAS_HBA_PORT_BROADCAST,
8091 SAS_PORT_BROADCAST_D24_0,
8092 &mpt->m_phy_info[phy_num].smhba_info);
8093 break;
8094 case MPI2_EVENT_PRIMITIVE_CHANGE1_RESERVED:
8095 mptsas_smhba_log_sysevent(mpt,
8096 ESC_SAS_HBA_PORT_BROADCAST,
8097 SAS_PORT_BROADCAST_D27_4,
8098 &mpt->m_phy_info[phy_num].smhba_info);
8099 break;
8100 default:
8101 NDBG16(("mptsas%d: unknown BROADCAST PRIMITIVE"
8102 " %x received",
8103 mpt->m_instance, primitive));
8104 break;
8105 }
8106 NDBG16(("mptsas%d sas broadcast primitive: "
8107 "\tprimitive(0x%04x), phy(%d) complete\n",
8108 mpt->m_instance, primitive, phy_num));
8109 break;
8110 }
8111 case MPI2_EVENT_IR_VOLUME:
8112 {
8113 Mpi2EventDataIrVolume_t *irVolume;
8114 uint16_t devhandle;
8115 uint32_t state;
8116 int config, vol;
8117 uint8_t found = FALSE;
8118
8119 irVolume = (pMpi2EventDataIrVolume_t)eventreply->EventData;
8120 state = ddi_get32(mpt->m_acc_reply_frame_hdl,
8121 &irVolume->NewValue);
8122 devhandle = ddi_get16(mpt->m_acc_reply_frame_hdl,
8123 &irVolume->VolDevHandle);
8124
8125 NDBG20(("EVENT_IR_VOLUME event is received"));
8126
8127 /*
8128 * Get latest RAID info and then find the DevHandle for this
8129 * event in the configuration. If the DevHandle is not found
8130 * just exit the event.
8131 */
8132 (void) mptsas_get_raid_info(mpt);
8133 for (config = 0; (config < mpt->m_num_raid_configs) &&
8134 (!found); config++) {
8135 for (vol = 0; vol < MPTSAS_MAX_RAIDVOLS; vol++) {
8136 if (mpt->m_raidconfig[config].m_raidvol[vol].
8137 m_raidhandle == devhandle) {
8138 found = TRUE;
8139 break;
8140 }
8141 }
8142 }
8143 if (!found) {
8144 break;
8145 }
8146
8147 switch (irVolume->ReasonCode) {
8148 case MPI2_EVENT_IR_VOLUME_RC_SETTINGS_CHANGED:
8149 {
8150 uint32_t i;
8151 mpt->m_raidconfig[config].m_raidvol[vol].m_settings =
8152 state;
8153
8154 i = state & MPI2_RAIDVOL0_SETTING_MASK_WRITE_CACHING;
8155 mptsas_log(mpt, CE_NOTE, " Volume %d settings changed"
8156 ", auto-config of hot-swap drives is %s"
8157 ", write caching is %s"
8158 ", hot-spare pool mask is %02x\n",
8159 vol, state &
8160 MPI2_RAIDVOL0_SETTING_AUTO_CONFIG_HSWAP_DISABLE
8161 ? "disabled" : "enabled",
8162 i == MPI2_RAIDVOL0_SETTING_UNCHANGED
8163 ? "controlled by member disks" :
8164 i == MPI2_RAIDVOL0_SETTING_DISABLE_WRITE_CACHING
8165 ? "disabled" :
8166 i == MPI2_RAIDVOL0_SETTING_ENABLE_WRITE_CACHING
8167 ? "enabled" :
8168 "incorrectly set",
8169 (state >> 16) & 0xff);
8170 break;
8171 }
8172 case MPI2_EVENT_IR_VOLUME_RC_STATE_CHANGED:
8173 {
8174 mpt->m_raidconfig[config].m_raidvol[vol].m_state =
8175 (uint8_t)state;
8176
8177 mptsas_log(mpt, CE_NOTE,
8178 "Volume %d is now %s\n", vol,
8179 state == MPI2_RAID_VOL_STATE_OPTIMAL
8180 ? "optimal" :
8181 state == MPI2_RAID_VOL_STATE_DEGRADED
8182 ? "degraded" :
8183 state == MPI2_RAID_VOL_STATE_ONLINE
8184 ? "online" :
8185 state == MPI2_RAID_VOL_STATE_INITIALIZING
8186 ? "initializing" :
8187 state == MPI2_RAID_VOL_STATE_FAILED
8188 ? "failed" :
8189 state == MPI2_RAID_VOL_STATE_MISSING
8190 ? "missing" :
8191 "state unknown");
8192 break;
8193 }
8194 case MPI2_EVENT_IR_VOLUME_RC_STATUS_FLAGS_CHANGED:
8195 {
8196 mpt->m_raidconfig[config].m_raidvol[vol].
8197 m_statusflags = state;
8198
8199 mptsas_log(mpt, CE_NOTE,
8200 " Volume %d is now %s%s%s%s%s%s%s%s%s\n",
8201 vol,
8202 state & MPI2_RAIDVOL0_STATUS_FLAG_ENABLED
8203 ? ", enabled" : ", disabled",
8204 state & MPI2_RAIDVOL0_STATUS_FLAG_QUIESCED
8205 ? ", quiesced" : "",
8206 state & MPI2_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE
8207 ? ", inactive" : ", active",
8208 state &
8209 MPI2_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL
8210 ? ", bad block table is full" : "",
8211 state &
8212 MPI2_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS
8213 ? ", resync in progress" : "",
8214 state & MPI2_RAIDVOL0_STATUS_FLAG_BACKGROUND_INIT
8215 ? ", background initialization in progress" : "",
8216 state &
8217 MPI2_RAIDVOL0_STATUS_FLAG_CAPACITY_EXPANSION
8218 ? ", capacity expansion in progress" : "",
8219 state &
8220 MPI2_RAIDVOL0_STATUS_FLAG_CONSISTENCY_CHECK
8221 ? ", consistency check in progress" : "",
8222 state & MPI2_RAIDVOL0_STATUS_FLAG_DATA_SCRUB
8223 ? ", data scrub in progress" : "");
8224 break;
8225 }
8226 default:
8227 break;
8228 }
8229 break;
8230 }
8231 case MPI2_EVENT_IR_PHYSICAL_DISK:
8232 {
8233 Mpi2EventDataIrPhysicalDisk_t *irPhysDisk;
8234 uint16_t devhandle, enchandle, slot;
8235 uint32_t status, state;
8236 uint8_t physdisknum, reason;
8237
8238 irPhysDisk = (Mpi2EventDataIrPhysicalDisk_t *)
8239 eventreply->EventData;
8240 physdisknum = ddi_get8(mpt->m_acc_reply_frame_hdl,
8241 &irPhysDisk->PhysDiskNum);
8242 devhandle = ddi_get16(mpt->m_acc_reply_frame_hdl,
8243 &irPhysDisk->PhysDiskDevHandle);
8244 enchandle = ddi_get16(mpt->m_acc_reply_frame_hdl,
8245 &irPhysDisk->EnclosureHandle);
8246 slot = ddi_get16(mpt->m_acc_reply_frame_hdl,
8247 &irPhysDisk->Slot);
8248 state = ddi_get32(mpt->m_acc_reply_frame_hdl,
8249 &irPhysDisk->NewValue);
8250 reason = ddi_get8(mpt->m_acc_reply_frame_hdl,
8251 &irPhysDisk->ReasonCode);
8252
8253 NDBG20(("EVENT_IR_PHYSICAL_DISK event is received"));
8254
8255 switch (reason) {
8256 case MPI2_EVENT_IR_PHYSDISK_RC_SETTINGS_CHANGED:
8257 mptsas_log(mpt, CE_NOTE,
8258 " PhysDiskNum %d with DevHandle 0x%x in slot %d "
8259 "for enclosure with handle 0x%x is now in hot "
8260 "spare pool %d",
8261 physdisknum, devhandle, slot, enchandle,
8262 (state >> 16) & 0xff);
8263 break;
8264
8265 case MPI2_EVENT_IR_PHYSDISK_RC_STATUS_FLAGS_CHANGED:
8266 status = state;
8267 mptsas_log(mpt, CE_NOTE,
8268 " PhysDiskNum %d with DevHandle 0x%x in slot %d "
8269 "for enclosure with handle 0x%x is now "
8270 "%s%s%s%s%s\n", physdisknum, devhandle, slot,
8271 enchandle,
8272 status & MPI2_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME
8273 ? ", inactive" : ", active",
8274 status & MPI2_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC
8275 ? ", out of sync" : "",
8276 status & MPI2_PHYSDISK0_STATUS_FLAG_QUIESCED
8277 ? ", quiesced" : "",
8278 status &
8279 MPI2_PHYSDISK0_STATUS_FLAG_WRITE_CACHE_ENABLED
8280 ? ", write cache enabled" : "",
8281 status & MPI2_PHYSDISK0_STATUS_FLAG_OCE_TARGET
8282 ? ", capacity expansion target" : "");
8283 break;
8284
8285 case MPI2_EVENT_IR_PHYSDISK_RC_STATE_CHANGED:
8286 mptsas_log(mpt, CE_NOTE,
8287 " PhysDiskNum %d with DevHandle 0x%x in slot %d "
8288 "for enclosure with handle 0x%x is now %s\n",
8289 physdisknum, devhandle, slot, enchandle,
8290 state == MPI2_RAID_PD_STATE_OPTIMAL
8291 ? "optimal" :
8292 state == MPI2_RAID_PD_STATE_REBUILDING
8293 ? "rebuilding" :
8294 state == MPI2_RAID_PD_STATE_DEGRADED
8295 ? "degraded" :
8296 state == MPI2_RAID_PD_STATE_HOT_SPARE
8297 ? "a hot spare" :
8298 state == MPI2_RAID_PD_STATE_ONLINE
8299 ? "online" :
8300 state == MPI2_RAID_PD_STATE_OFFLINE
8301 ? "offline" :
8302 state == MPI2_RAID_PD_STATE_NOT_COMPATIBLE
8303 ? "not compatible" :
8304 state == MPI2_RAID_PD_STATE_NOT_CONFIGURED
8305 ? "not configured" :
8306 "state unknown");
8307 break;
8308 }
8309 break;
8310 }
8311 case MPI2_EVENT_ACTIVE_CABLE_EXCEPTION:
8312 {
8313 pMpi26EventDataActiveCableExcept_t actcable;
8314 uint32_t power;
8315 uint8_t reason, id;
8316
8317 actcable = (pMpi26EventDataActiveCableExcept_t)
8318 eventreply->EventData;
8319 power = ddi_get32(mpt->m_acc_reply_frame_hdl,
8320 &actcable->ActiveCablePowerRequirement);
8321 reason = ddi_get8(mpt->m_acc_reply_frame_hdl,
8322 &actcable->ReasonCode);
8323 id = ddi_get8(mpt->m_acc_reply_frame_hdl,
8324 &actcable->ReceptacleID);
8325
8326 /*
8327 * It'd be nice if this weren't just logging to the system but
8328 * were telling FMA about the active cable problem and FMA was
8329 * aware of the cable topology and state.
8330 */
8331 switch (reason) {
8332 case MPI26_EVENT_ACTIVE_CABLE_PRESENT:
8333 /* Don't log anything if it's fine */
8334 break;
8335 case MPI26_EVENT_ACTIVE_CABLE_INSUFFICIENT_POWER:
8336 mptsas_log(mpt, CE_WARN, "An active cable (id %u) does "
8337 "not have sufficient power to be enabled. "
8338 "Devices connected to this cable will not be "
8339 "visible to the system.", id);
8340 if (power == UINT32_MAX) {
8341 mptsas_log(mpt, CE_CONT, "The cable's power "
8342 "requirements are unknown.\n");
8343 } else {
8344 mptsas_log(mpt, CE_CONT, "The cable requires "
8345 "%u mW of power to function.\n", power);
8346 }
8347 break;
8348 case MPI26_EVENT_ACTIVE_CABLE_DEGRADED:
8349 mptsas_log(mpt, CE_WARN, "An active cable (id %u) is "
8350 "degraded and not running at its full speed. "
8351 "Some devices might not appear.", id);
8352 break;
8353 default:
8354 break;
8355 }
8356 break;
8357 }
8358 case MPI2_EVENT_PCIE_DEVICE_STATUS_CHANGE:
8359 case MPI2_EVENT_PCIE_ENUMERATION:
8360 case MPI2_EVENT_PCIE_TOPOLOGY_CHANGE_LIST:
8361 case MPI2_EVENT_PCIE_LINK_COUNTER:
8362 mptsas_log(mpt, CE_NOTE, "Unhandled mpt_sas PCIe device "
8363 "event received (0x%x)", event);
8364 break;
8365 default:
8366 NDBG20(("mptsas%d: unknown event %x received",
8367 mpt->m_instance, event));
8368 break;
8369 }
8370
8371 /*
8372 * Return the reply frame to the free queue.
8373 */
8374 ddi_put32(mpt->m_acc_free_queue_hdl,
8375 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index], rfm);
8376 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0,
8377 DDI_DMA_SYNC_FORDEV);
8378 if (++mpt->m_free_index == mpt->m_free_queue_depth) {
8379 mpt->m_free_index = 0;
8380 }
8381 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex,
8382 mpt->m_free_index);
8383 mutex_exit(&mpt->m_mutex);
8384 }
8385
8386 /*
8387 * invoked from timeout() to restart qfull cmds with throttle == 0
8388 */
8389 static void
mptsas_restart_cmd(void * arg)8390 mptsas_restart_cmd(void *arg)
8391 {
8392 mptsas_t *mpt = arg;
8393 mptsas_target_t *ptgt = NULL;
8394
8395 mutex_enter(&mpt->m_mutex);
8396
8397 mpt->m_restart_cmd_timeid = 0;
8398
8399 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
8400 ptgt = refhash_next(mpt->m_targets, ptgt)) {
8401 if (ptgt->m_reset_delay == 0) {
8402 if (ptgt->m_t_throttle == QFULL_THROTTLE) {
8403 mptsas_set_throttle(mpt, ptgt,
8404 MAX_THROTTLE);
8405 }
8406 }
8407 }
8408 mptsas_restart_hba(mpt);
8409 mutex_exit(&mpt->m_mutex);
8410 }
8411
8412 void
mptsas_remove_cmd(mptsas_t * mpt,mptsas_cmd_t * cmd)8413 mptsas_remove_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd)
8414 {
8415 int slot;
8416 mptsas_slots_t *slots = mpt->m_active;
8417 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
8418
8419 ASSERT(cmd != NULL);
8420 ASSERT(cmd->cmd_queued == FALSE);
8421
8422 /*
8423 * Task Management cmds are removed in their own routines. Also,
8424 * we don't want to modify timeout based on TM cmds.
8425 */
8426 if (cmd->cmd_flags & CFLAG_TM_CMD) {
8427 return;
8428 }
8429
8430 slot = cmd->cmd_slot;
8431
8432 /*
8433 * remove the cmd.
8434 */
8435 if (cmd == slots->m_slot[slot]) {
8436 NDBG31(("mptsas_remove_cmd: removing cmd=0x%p, flags "
8437 "0x%x", (void *)cmd, cmd->cmd_flags));
8438 slots->m_slot[slot] = NULL;
8439 mpt->m_ncmds--;
8440
8441 /*
8442 * only decrement per target ncmds if command
8443 * has a target associated with it.
8444 */
8445 if ((cmd->cmd_flags & CFLAG_CMDIOC) == 0) {
8446 ptgt->m_t_ncmds--;
8447 /*
8448 * reset throttle if we just ran an untagged command
8449 * to a tagged target
8450 */
8451 if ((ptgt->m_t_ncmds == 0) &&
8452 ((cmd->cmd_pkt_flags & FLAG_TAGMASK) == 0)) {
8453 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE);
8454 }
8455
8456 /*
8457 * Remove this command from the active queue.
8458 */
8459 if (cmd->cmd_active_expiration != 0) {
8460 TAILQ_REMOVE(&ptgt->m_active_cmdq, cmd,
8461 cmd_active_link);
8462 cmd->cmd_active_expiration = 0;
8463 }
8464 }
8465 }
8466
8467 /*
8468 * This is all we need to do for ioc commands.
8469 */
8470 if (cmd->cmd_flags & CFLAG_CMDIOC) {
8471 mptsas_return_to_pool(mpt, cmd);
8472 return;
8473 }
8474
8475 ASSERT(cmd != slots->m_slot[cmd->cmd_slot]);
8476 }
8477
8478 /*
8479 * accept all cmds on the tx_waitq if any and then
8480 * start a fresh request from the top of the device queue.
8481 *
8482 * since there are always cmds queued on the tx_waitq, and rare cmds on
8483 * the instance waitq, so this function should not be invoked in the ISR,
8484 * the mptsas_restart_waitq() is invoked in the ISR instead. otherwise, the
8485 * burden belongs to the IO dispatch CPUs is moved the interrupt CPU.
8486 */
8487 static void
mptsas_restart_hba(mptsas_t * mpt)8488 mptsas_restart_hba(mptsas_t *mpt)
8489 {
8490 ASSERT(mutex_owned(&mpt->m_mutex));
8491
8492 mutex_enter(&mpt->m_tx_waitq_mutex);
8493 if (mpt->m_tx_waitq) {
8494 mptsas_accept_tx_waitq(mpt);
8495 }
8496 mutex_exit(&mpt->m_tx_waitq_mutex);
8497 mptsas_restart_waitq(mpt);
8498 }
8499
8500 /*
8501 * start a fresh request from the top of the device queue
8502 */
8503 static void
mptsas_restart_waitq(mptsas_t * mpt)8504 mptsas_restart_waitq(mptsas_t *mpt)
8505 {
8506 mptsas_cmd_t *cmd, *next_cmd;
8507 mptsas_target_t *ptgt = NULL;
8508
8509 NDBG1(("mptsas_restart_waitq: mpt=0x%p", (void *)mpt));
8510
8511 ASSERT(mutex_owned(&mpt->m_mutex));
8512
8513 /*
8514 * If there is a reset delay, don't start any cmds. Otherwise, start
8515 * as many cmds as possible.
8516 * Since SMID 0 is reserved and the TM slot is reserved, the actual max
8517 * commands is m_max_requests - 2.
8518 */
8519 cmd = mpt->m_waitq;
8520
8521 while (cmd != NULL) {
8522 next_cmd = cmd->cmd_linkp;
8523 if (cmd->cmd_flags & CFLAG_PASSTHRU) {
8524 if (mptsas_save_cmd(mpt, cmd) == TRUE) {
8525 /*
8526 * passthru command get slot need
8527 * set CFLAG_PREPARED.
8528 */
8529 cmd->cmd_flags |= CFLAG_PREPARED;
8530 mptsas_waitq_delete(mpt, cmd);
8531 mptsas_start_passthru(mpt, cmd);
8532 }
8533 cmd = next_cmd;
8534 continue;
8535 }
8536 if (cmd->cmd_flags & CFLAG_CONFIG) {
8537 if (mptsas_save_cmd(mpt, cmd) == TRUE) {
8538 /*
8539 * Send the config page request and delete it
8540 * from the waitq.
8541 */
8542 cmd->cmd_flags |= CFLAG_PREPARED;
8543 mptsas_waitq_delete(mpt, cmd);
8544 mptsas_start_config_page_access(mpt, cmd);
8545 }
8546 cmd = next_cmd;
8547 continue;
8548 }
8549 if (cmd->cmd_flags & CFLAG_FW_DIAG) {
8550 if (mptsas_save_cmd(mpt, cmd) == TRUE) {
8551 /*
8552 * Send the FW Diag request and delete if from
8553 * the waitq.
8554 */
8555 cmd->cmd_flags |= CFLAG_PREPARED;
8556 mptsas_waitq_delete(mpt, cmd);
8557 mptsas_start_diag(mpt, cmd);
8558 }
8559 cmd = next_cmd;
8560 continue;
8561 }
8562
8563 ptgt = cmd->cmd_tgt_addr;
8564 if (ptgt && (ptgt->m_t_throttle == DRAIN_THROTTLE) &&
8565 (ptgt->m_t_ncmds == 0)) {
8566 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE);
8567 }
8568 if ((mpt->m_ncmds <= (mpt->m_max_requests - 2)) &&
8569 (ptgt && (ptgt->m_reset_delay == 0)) &&
8570 (ptgt && (ptgt->m_t_ncmds <
8571 ptgt->m_t_throttle))) {
8572 if (mptsas_save_cmd(mpt, cmd) == TRUE) {
8573 mptsas_waitq_delete(mpt, cmd);
8574 (void) mptsas_start_cmd(mpt, cmd);
8575 }
8576 }
8577 cmd = next_cmd;
8578 }
8579 }
8580 /*
8581 * Cmds are queued if tran_start() doesn't get the m_mutexlock(no wait).
8582 * Accept all those queued cmds before new cmd is accept so that the
8583 * cmds are sent in order.
8584 */
8585 static void
mptsas_accept_tx_waitq(mptsas_t * mpt)8586 mptsas_accept_tx_waitq(mptsas_t *mpt)
8587 {
8588 mptsas_cmd_t *cmd;
8589
8590 ASSERT(mutex_owned(&mpt->m_mutex));
8591 ASSERT(mutex_owned(&mpt->m_tx_waitq_mutex));
8592
8593 /*
8594 * A Bus Reset could occur at any time and flush the tx_waitq,
8595 * so we cannot count on the tx_waitq to contain even one cmd.
8596 * And when the m_tx_waitq_mutex is released and run
8597 * mptsas_accept_pkt(), the tx_waitq may be flushed.
8598 */
8599 cmd = mpt->m_tx_waitq;
8600 for (;;) {
8601 if ((cmd = mpt->m_tx_waitq) == NULL) {
8602 mpt->m_tx_draining = 0;
8603 break;
8604 }
8605 if ((mpt->m_tx_waitq = cmd->cmd_linkp) == NULL) {
8606 mpt->m_tx_waitqtail = &mpt->m_tx_waitq;
8607 }
8608 cmd->cmd_linkp = NULL;
8609 mutex_exit(&mpt->m_tx_waitq_mutex);
8610 if (mptsas_accept_pkt(mpt, cmd) != TRAN_ACCEPT)
8611 cmn_err(CE_WARN, "mpt: mptsas_accept_tx_waitq: failed "
8612 "to accept cmd on queue\n");
8613 mutex_enter(&mpt->m_tx_waitq_mutex);
8614 }
8615 }
8616
8617
8618 /*
8619 * mpt tag type lookup
8620 */
8621 static char mptsas_tag_lookup[] =
8622 {0, MSG_HEAD_QTAG, MSG_ORDERED_QTAG, 0, MSG_SIMPLE_QTAG};
8623
8624 static int
mptsas_start_cmd(mptsas_t * mpt,mptsas_cmd_t * cmd)8625 mptsas_start_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd)
8626 {
8627 struct scsi_pkt *pkt = CMD2PKT(cmd);
8628 uint32_t control = 0;
8629 caddr_t mem, arsbuf;
8630 pMpi2SCSIIORequest_t io_request;
8631 ddi_dma_handle_t dma_hdl = mpt->m_dma_req_frame_hdl;
8632 ddi_acc_handle_t acc_hdl = mpt->m_acc_req_frame_hdl;
8633 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
8634 uint16_t SMID, io_flags = 0;
8635 uint8_t ars_size;
8636 uint64_t request_desc;
8637 uint32_t ars_dmaaddrlow;
8638 mptsas_cmd_t *c;
8639
8640 NDBG1(("mptsas_start_cmd: cmd=0x%p, flags 0x%x", (void *)cmd,
8641 cmd->cmd_flags));
8642
8643 /*
8644 * Set SMID and increment index. Rollover to 1 instead of 0 if index
8645 * is at the max. 0 is an invalid SMID, so we call the first index 1.
8646 */
8647 SMID = cmd->cmd_slot;
8648
8649 /*
8650 * It is possible for back to back device reset to
8651 * happen before the reset delay has expired. That's
8652 * ok, just let the device reset go out on the bus.
8653 */
8654 if ((cmd->cmd_pkt_flags & FLAG_NOINTR) == 0) {
8655 ASSERT(ptgt->m_reset_delay == 0);
8656 }
8657
8658 /*
8659 * if a non-tagged cmd is submitted to an active tagged target
8660 * then drain before submitting this cmd; SCSI-2 allows RQSENSE
8661 * to be untagged
8662 */
8663 if (((cmd->cmd_pkt_flags & FLAG_TAGMASK) == 0) &&
8664 (ptgt->m_t_ncmds > 1) &&
8665 ((cmd->cmd_flags & CFLAG_TM_CMD) == 0) &&
8666 (*(cmd->cmd_pkt->pkt_cdbp) != SCMD_REQUEST_SENSE)) {
8667 if ((cmd->cmd_pkt_flags & FLAG_NOINTR) == 0) {
8668 NDBG23(("target=%d, untagged cmd, start draining\n",
8669 ptgt->m_devhdl));
8670
8671 if (ptgt->m_reset_delay == 0) {
8672 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE);
8673 }
8674
8675 mptsas_remove_cmd(mpt, cmd);
8676 cmd->cmd_pkt_flags |= FLAG_HEAD;
8677 mptsas_waitq_add(mpt, cmd);
8678 }
8679 return (DDI_FAILURE);
8680 }
8681
8682 /*
8683 * Set correct tag bits.
8684 */
8685 if (cmd->cmd_pkt_flags & FLAG_TAGMASK) {
8686 switch (mptsas_tag_lookup[((cmd->cmd_pkt_flags &
8687 FLAG_TAGMASK) >> 12)]) {
8688 case MSG_SIMPLE_QTAG:
8689 control |= MPI2_SCSIIO_CONTROL_SIMPLEQ;
8690 break;
8691 case MSG_HEAD_QTAG:
8692 control |= MPI2_SCSIIO_CONTROL_HEADOFQ;
8693 break;
8694 case MSG_ORDERED_QTAG:
8695 control |= MPI2_SCSIIO_CONTROL_ORDEREDQ;
8696 break;
8697 default:
8698 mptsas_log(mpt, CE_WARN, "mpt: Invalid tag type\n");
8699 break;
8700 }
8701 } else {
8702 if (*(cmd->cmd_pkt->pkt_cdbp) != SCMD_REQUEST_SENSE) {
8703 ptgt->m_t_throttle = 1;
8704 }
8705 control |= MPI2_SCSIIO_CONTROL_SIMPLEQ;
8706 }
8707
8708 if (cmd->cmd_pkt_flags & FLAG_TLR) {
8709 control |= MPI2_SCSIIO_CONTROL_TLR_ON;
8710 }
8711
8712 mem = mpt->m_req_frame + (mpt->m_req_frame_size * SMID);
8713 io_request = (pMpi2SCSIIORequest_t)mem;
8714 if (cmd->cmd_extrqslen != 0) {
8715 /*
8716 * Mapping of the buffer was done in mptsas_pkt_alloc_extern().
8717 * Calculate the DMA address with the same offset.
8718 */
8719 arsbuf = cmd->cmd_arq_buf;
8720 ars_size = cmd->cmd_extrqslen;
8721 ars_dmaaddrlow = (mpt->m_req_sense_dma_addr +
8722 ((uintptr_t)arsbuf - (uintptr_t)mpt->m_req_sense)) &
8723 0xffffffffu;
8724 } else {
8725 arsbuf = mpt->m_req_sense + (mpt->m_req_sense_size * (SMID-1));
8726 cmd->cmd_arq_buf = arsbuf;
8727 ars_size = mpt->m_req_sense_size;
8728 ars_dmaaddrlow = (mpt->m_req_sense_dma_addr +
8729 (mpt->m_req_sense_size * (SMID-1))) &
8730 0xffffffffu;
8731 }
8732 bzero(io_request, sizeof (Mpi2SCSIIORequest_t));
8733 bzero(arsbuf, ars_size);
8734
8735 ddi_put8(acc_hdl, &io_request->SGLOffset0, offsetof
8736 (MPI2_SCSI_IO_REQUEST, SGL) / 4);
8737 mptsas_init_std_hdr(acc_hdl, io_request, ptgt->m_devhdl, Lun(cmd), 0,
8738 MPI2_FUNCTION_SCSI_IO_REQUEST);
8739
8740 (void) ddi_rep_put8(acc_hdl, (uint8_t *)pkt->pkt_cdbp,
8741 io_request->CDB.CDB32, cmd->cmd_cdblen, DDI_DEV_AUTOINCR);
8742
8743 io_flags = cmd->cmd_cdblen;
8744 if (mptsas_use_fastpath &&
8745 ptgt->m_io_flags & MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH) {
8746 io_flags |= MPI25_SCSIIO_IOFLAGS_FAST_PATH;
8747 request_desc = MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO;
8748 } else {
8749 request_desc = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO;
8750 }
8751 ddi_put16(acc_hdl, &io_request->IoFlags, io_flags);
8752 /*
8753 * setup the Scatter/Gather DMA list for this request
8754 */
8755 if (cmd->cmd_cookiec > 0) {
8756 mptsas_sge_setup(mpt, cmd, &control, io_request, acc_hdl);
8757 } else {
8758 ddi_put32(acc_hdl, &io_request->SGL.MpiSimple.FlagsLength,
8759 ((uint32_t)MPI2_SGE_FLAGS_LAST_ELEMENT |
8760 MPI2_SGE_FLAGS_END_OF_BUFFER |
8761 MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
8762 MPI2_SGE_FLAGS_END_OF_LIST) << MPI2_SGE_FLAGS_SHIFT);
8763 }
8764
8765 /*
8766 * save ARQ information
8767 */
8768 ddi_put8(acc_hdl, &io_request->SenseBufferLength, ars_size);
8769 ddi_put32(acc_hdl, &io_request->SenseBufferLowAddress, ars_dmaaddrlow);
8770
8771 ddi_put32(acc_hdl, &io_request->Control, control);
8772
8773 NDBG31(("starting message=%d(0x%p), with cmd=0x%p",
8774 SMID, (void *)io_request, (void *)cmd));
8775
8776 (void) ddi_dma_sync(dma_hdl, 0, 0, DDI_DMA_SYNC_FORDEV);
8777 (void) ddi_dma_sync(mpt->m_dma_req_sense_hdl, 0, 0,
8778 DDI_DMA_SYNC_FORDEV);
8779
8780 /*
8781 * Build request descriptor and write it to the request desc post reg.
8782 */
8783 request_desc |= (SMID << 16);
8784 request_desc |= (uint64_t)ptgt->m_devhdl << 48;
8785 MPTSAS_START_CMD(mpt, request_desc);
8786
8787 /*
8788 * Start timeout.
8789 */
8790 cmd->cmd_active_expiration =
8791 gethrtime() + (hrtime_t)pkt->pkt_time * NANOSEC;
8792 #ifdef MPTSAS_TEST
8793 /*
8794 * Force timeouts to happen immediately.
8795 */
8796 if (mptsas_test_timeouts)
8797 cmd->cmd_active_expiration = gethrtime();
8798 #endif
8799 c = TAILQ_FIRST(&ptgt->m_active_cmdq);
8800 if (c == NULL ||
8801 c->cmd_active_expiration < cmd->cmd_active_expiration) {
8802 /*
8803 * Common case is that this is the last pending expiration
8804 * (or queue is empty). Insert at head of the queue.
8805 */
8806 TAILQ_INSERT_HEAD(&ptgt->m_active_cmdq, cmd, cmd_active_link);
8807 } else {
8808 /*
8809 * Queue is not empty and first element expires later than
8810 * this command. Search for element expiring sooner.
8811 */
8812 while ((c = TAILQ_NEXT(c, cmd_active_link)) != NULL) {
8813 if (c->cmd_active_expiration <
8814 cmd->cmd_active_expiration) {
8815 TAILQ_INSERT_BEFORE(c, cmd, cmd_active_link);
8816 break;
8817 }
8818 }
8819 if (c == NULL) {
8820 /*
8821 * No element found expiring sooner, append to
8822 * non-empty queue.
8823 */
8824 TAILQ_INSERT_TAIL(&ptgt->m_active_cmdq, cmd,
8825 cmd_active_link);
8826 }
8827 }
8828
8829 if ((mptsas_check_dma_handle(dma_hdl) != DDI_SUCCESS) ||
8830 (mptsas_check_acc_handle(acc_hdl) != DDI_SUCCESS)) {
8831 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
8832 return (DDI_FAILURE);
8833 }
8834 return (DDI_SUCCESS);
8835 }
8836
8837 /*
8838 * Select a helper thread to handle current doneq
8839 */
8840 static void
mptsas_deliver_doneq_thread(mptsas_t * mpt)8841 mptsas_deliver_doneq_thread(mptsas_t *mpt)
8842 {
8843 uint64_t t, i;
8844 uint32_t min = 0xffffffff;
8845 mptsas_doneq_thread_list_t *item;
8846
8847 for (i = 0; i < mpt->m_doneq_thread_n; i++) {
8848 item = &mpt->m_doneq_thread_id[i];
8849 /*
8850 * If the completed command on help thread[i] less than
8851 * doneq_thread_threshold, then pick the thread[i]. Otherwise
8852 * pick a thread which has least completed command.
8853 */
8854
8855 mutex_enter(&item->mutex);
8856 if (item->len < mpt->m_doneq_thread_threshold) {
8857 t = i;
8858 mutex_exit(&item->mutex);
8859 break;
8860 }
8861 if (item->len < min) {
8862 min = item->len;
8863 t = i;
8864 }
8865 mutex_exit(&item->mutex);
8866 }
8867 mutex_enter(&mpt->m_doneq_thread_id[t].mutex);
8868 mptsas_doneq_mv(mpt, t);
8869 cv_signal(&mpt->m_doneq_thread_id[t].cv);
8870 mutex_exit(&mpt->m_doneq_thread_id[t].mutex);
8871 }
8872
8873 /*
8874 * move the current global doneq to the doneq of thead[t]
8875 */
8876 static void
mptsas_doneq_mv(mptsas_t * mpt,uint64_t t)8877 mptsas_doneq_mv(mptsas_t *mpt, uint64_t t)
8878 {
8879 mptsas_cmd_t *cmd;
8880 mptsas_doneq_thread_list_t *item = &mpt->m_doneq_thread_id[t];
8881
8882 ASSERT(mutex_owned(&item->mutex));
8883 while ((cmd = mpt->m_doneq) != NULL) {
8884 if ((mpt->m_doneq = cmd->cmd_linkp) == NULL) {
8885 mpt->m_donetail = &mpt->m_doneq;
8886 }
8887 cmd->cmd_linkp = NULL;
8888 *item->donetail = cmd;
8889 item->donetail = &cmd->cmd_linkp;
8890 mpt->m_doneq_len--;
8891 item->len++;
8892 }
8893 }
8894
8895 void
mptsas_fma_check(mptsas_t * mpt,mptsas_cmd_t * cmd)8896 mptsas_fma_check(mptsas_t *mpt, mptsas_cmd_t *cmd)
8897 {
8898 struct scsi_pkt *pkt = CMD2PKT(cmd);
8899
8900 /* Check all acc and dma handles */
8901 if ((mptsas_check_acc_handle(mpt->m_datap) !=
8902 DDI_SUCCESS) ||
8903 (mptsas_check_acc_handle(mpt->m_acc_req_frame_hdl) !=
8904 DDI_SUCCESS) ||
8905 (mptsas_check_acc_handle(mpt->m_acc_req_sense_hdl) !=
8906 DDI_SUCCESS) ||
8907 (mptsas_check_acc_handle(mpt->m_acc_reply_frame_hdl) !=
8908 DDI_SUCCESS) ||
8909 (mptsas_check_acc_handle(mpt->m_acc_free_queue_hdl) !=
8910 DDI_SUCCESS) ||
8911 (mptsas_check_acc_handle(mpt->m_acc_post_queue_hdl) !=
8912 DDI_SUCCESS) ||
8913 (mptsas_check_acc_handle(mpt->m_hshk_acc_hdl) !=
8914 DDI_SUCCESS) ||
8915 (mptsas_check_acc_handle(mpt->m_config_handle) !=
8916 DDI_SUCCESS)) {
8917 ddi_fm_service_impact(mpt->m_dip,
8918 DDI_SERVICE_UNAFFECTED);
8919 ddi_fm_acc_err_clear(mpt->m_config_handle,
8920 DDI_FME_VER0);
8921 pkt->pkt_reason = CMD_TRAN_ERR;
8922 pkt->pkt_statistics = 0;
8923 }
8924 if ((mptsas_check_dma_handle(mpt->m_dma_req_frame_hdl) !=
8925 DDI_SUCCESS) ||
8926 (mptsas_check_dma_handle(mpt->m_dma_req_sense_hdl) !=
8927 DDI_SUCCESS) ||
8928 (mptsas_check_dma_handle(mpt->m_dma_reply_frame_hdl) !=
8929 DDI_SUCCESS) ||
8930 (mptsas_check_dma_handle(mpt->m_dma_free_queue_hdl) !=
8931 DDI_SUCCESS) ||
8932 (mptsas_check_dma_handle(mpt->m_dma_post_queue_hdl) !=
8933 DDI_SUCCESS) ||
8934 (mptsas_check_dma_handle(mpt->m_hshk_dma_hdl) !=
8935 DDI_SUCCESS)) {
8936 ddi_fm_service_impact(mpt->m_dip,
8937 DDI_SERVICE_UNAFFECTED);
8938 pkt->pkt_reason = CMD_TRAN_ERR;
8939 pkt->pkt_statistics = 0;
8940 }
8941 if (cmd->cmd_dmahandle &&
8942 (mptsas_check_dma_handle(cmd->cmd_dmahandle) != DDI_SUCCESS)) {
8943 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
8944 pkt->pkt_reason = CMD_TRAN_ERR;
8945 pkt->pkt_statistics = 0;
8946 }
8947 if ((cmd->cmd_extra_frames &&
8948 ((mptsas_check_dma_handle(cmd->cmd_extra_frames->m_dma_hdl) !=
8949 DDI_SUCCESS) ||
8950 (mptsas_check_acc_handle(cmd->cmd_extra_frames->m_acc_hdl) !=
8951 DDI_SUCCESS)))) {
8952 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
8953 pkt->pkt_reason = CMD_TRAN_ERR;
8954 pkt->pkt_statistics = 0;
8955 }
8956 }
8957
8958 /*
8959 * These routines manipulate the queue of commands that
8960 * are waiting for their completion routines to be called.
8961 * The queue is usually in FIFO order but on an MP system
8962 * it's possible for the completion routines to get out
8963 * of order. If that's a problem you need to add a global
8964 * mutex around the code that calls the completion routine
8965 * in the interrupt handler.
8966 */
8967 static void
mptsas_doneq_add(mptsas_t * mpt,mptsas_cmd_t * cmd)8968 mptsas_doneq_add(mptsas_t *mpt, mptsas_cmd_t *cmd)
8969 {
8970 struct scsi_pkt *pkt = CMD2PKT(cmd);
8971
8972 NDBG31(("mptsas_doneq_add: cmd=0x%p", (void *)cmd));
8973
8974 ASSERT((cmd->cmd_flags & CFLAG_COMPLETED) == 0);
8975 cmd->cmd_linkp = NULL;
8976 cmd->cmd_flags |= CFLAG_FINISHED;
8977 cmd->cmd_flags &= ~CFLAG_IN_TRANSPORT;
8978
8979 mptsas_fma_check(mpt, cmd);
8980
8981 /*
8982 * only add scsi pkts that have completion routines to
8983 * the doneq. no intr cmds do not have callbacks.
8984 */
8985 if (pkt && (pkt->pkt_comp)) {
8986 *mpt->m_donetail = cmd;
8987 mpt->m_donetail = &cmd->cmd_linkp;
8988 mpt->m_doneq_len++;
8989 }
8990 }
8991
8992 static mptsas_cmd_t *
mptsas_doneq_thread_rm(mptsas_t * mpt,uint64_t t)8993 mptsas_doneq_thread_rm(mptsas_t *mpt, uint64_t t)
8994 {
8995 mptsas_cmd_t *cmd;
8996 mptsas_doneq_thread_list_t *item = &mpt->m_doneq_thread_id[t];
8997
8998 /* pop one off the done queue */
8999 if ((cmd = item->doneq) != NULL) {
9000 /* if the queue is now empty fix the tail pointer */
9001 NDBG31(("mptsas_doneq_thread_rm: cmd=0x%p", (void *)cmd));
9002 if ((item->doneq = cmd->cmd_linkp) == NULL) {
9003 item->donetail = &item->doneq;
9004 }
9005 cmd->cmd_linkp = NULL;
9006 item->len--;
9007 }
9008 return (cmd);
9009 }
9010
9011 static void
mptsas_doneq_empty(mptsas_t * mpt)9012 mptsas_doneq_empty(mptsas_t *mpt)
9013 {
9014 if (mpt->m_doneq && !mpt->m_in_callback) {
9015 mptsas_cmd_t *cmd, *next;
9016 struct scsi_pkt *pkt;
9017
9018 mpt->m_in_callback = 1;
9019 cmd = mpt->m_doneq;
9020 mpt->m_doneq = NULL;
9021 mpt->m_donetail = &mpt->m_doneq;
9022 mpt->m_doneq_len = 0;
9023
9024 mutex_exit(&mpt->m_mutex);
9025 /*
9026 * run the completion routines of all the
9027 * completed commands
9028 */
9029 while (cmd != NULL) {
9030 next = cmd->cmd_linkp;
9031 cmd->cmd_linkp = NULL;
9032 /* run this command's completion routine */
9033 cmd->cmd_flags |= CFLAG_COMPLETED;
9034 pkt = CMD2PKT(cmd);
9035 mptsas_pkt_comp(pkt, cmd);
9036 cmd = next;
9037 }
9038 mutex_enter(&mpt->m_mutex);
9039 mpt->m_in_callback = 0;
9040 }
9041 }
9042
9043 /*
9044 * These routines manipulate the target's queue of pending requests
9045 */
9046 void
mptsas_waitq_add(mptsas_t * mpt,mptsas_cmd_t * cmd)9047 mptsas_waitq_add(mptsas_t *mpt, mptsas_cmd_t *cmd)
9048 {
9049 NDBG7(("mptsas_waitq_add: cmd=0x%p", (void *)cmd));
9050 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
9051 cmd->cmd_queued = TRUE;
9052 if (ptgt)
9053 ptgt->m_t_nwait++;
9054 if (cmd->cmd_pkt_flags & FLAG_HEAD) {
9055 if ((cmd->cmd_linkp = mpt->m_waitq) == NULL) {
9056 mpt->m_waitqtail = &cmd->cmd_linkp;
9057 }
9058 mpt->m_waitq = cmd;
9059 } else {
9060 cmd->cmd_linkp = NULL;
9061 *(mpt->m_waitqtail) = cmd;
9062 mpt->m_waitqtail = &cmd->cmd_linkp;
9063 }
9064 }
9065
9066 static mptsas_cmd_t *
mptsas_waitq_rm(mptsas_t * mpt)9067 mptsas_waitq_rm(mptsas_t *mpt)
9068 {
9069 mptsas_cmd_t *cmd;
9070 mptsas_target_t *ptgt;
9071 NDBG7(("mptsas_waitq_rm"));
9072
9073 MPTSAS_WAITQ_RM(mpt, cmd);
9074
9075 NDBG7(("mptsas_waitq_rm: cmd=0x%p", (void *)cmd));
9076 if (cmd) {
9077 ptgt = cmd->cmd_tgt_addr;
9078 if (ptgt) {
9079 ptgt->m_t_nwait--;
9080 ASSERT(ptgt->m_t_nwait >= 0);
9081 }
9082 }
9083 return (cmd);
9084 }
9085
9086 /*
9087 * remove specified cmd from the middle of the wait queue.
9088 */
9089 static void
mptsas_waitq_delete(mptsas_t * mpt,mptsas_cmd_t * cmd)9090 mptsas_waitq_delete(mptsas_t *mpt, mptsas_cmd_t *cmd)
9091 {
9092 mptsas_cmd_t *prevp = mpt->m_waitq;
9093 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
9094
9095 NDBG7(("mptsas_waitq_delete: mpt=0x%p cmd=0x%p",
9096 (void *)mpt, (void *)cmd));
9097 if (ptgt) {
9098 ptgt->m_t_nwait--;
9099 ASSERT(ptgt->m_t_nwait >= 0);
9100 }
9101
9102 if (prevp == cmd) {
9103 if ((mpt->m_waitq = cmd->cmd_linkp) == NULL)
9104 mpt->m_waitqtail = &mpt->m_waitq;
9105
9106 cmd->cmd_linkp = NULL;
9107 cmd->cmd_queued = FALSE;
9108 NDBG7(("mptsas_waitq_delete: mpt=0x%p cmd=0x%p",
9109 (void *)mpt, (void *)cmd));
9110 return;
9111 }
9112
9113 while (prevp != NULL) {
9114 if (prevp->cmd_linkp == cmd) {
9115 if ((prevp->cmd_linkp = cmd->cmd_linkp) == NULL)
9116 mpt->m_waitqtail = &prevp->cmd_linkp;
9117
9118 cmd->cmd_linkp = NULL;
9119 cmd->cmd_queued = FALSE;
9120 NDBG7(("mptsas_waitq_delete: mpt=0x%p cmd=0x%p",
9121 (void *)mpt, (void *)cmd));
9122 return;
9123 }
9124 prevp = prevp->cmd_linkp;
9125 }
9126 cmn_err(CE_PANIC, "mpt: mptsas_waitq_delete: queue botch");
9127 }
9128
9129 static mptsas_cmd_t *
mptsas_tx_waitq_rm(mptsas_t * mpt)9130 mptsas_tx_waitq_rm(mptsas_t *mpt)
9131 {
9132 mptsas_cmd_t *cmd;
9133 NDBG7(("mptsas_tx_waitq_rm"));
9134
9135 MPTSAS_TX_WAITQ_RM(mpt, cmd);
9136
9137 NDBG7(("mptsas_tx_waitq_rm: cmd=0x%p", (void *)cmd));
9138
9139 return (cmd);
9140 }
9141
9142 /*
9143 * remove specified cmd from the middle of the tx_waitq.
9144 */
9145 static void
mptsas_tx_waitq_delete(mptsas_t * mpt,mptsas_cmd_t * cmd)9146 mptsas_tx_waitq_delete(mptsas_t *mpt, mptsas_cmd_t *cmd)
9147 {
9148 mptsas_cmd_t *prevp = mpt->m_tx_waitq;
9149
9150 NDBG7(("mptsas_tx_waitq_delete: mpt=0x%p cmd=0x%p",
9151 (void *)mpt, (void *)cmd));
9152
9153 if (prevp == cmd) {
9154 if ((mpt->m_tx_waitq = cmd->cmd_linkp) == NULL)
9155 mpt->m_tx_waitqtail = &mpt->m_tx_waitq;
9156
9157 cmd->cmd_linkp = NULL;
9158 cmd->cmd_queued = FALSE;
9159 NDBG7(("mptsas_tx_waitq_delete: mpt=0x%p cmd=0x%p",
9160 (void *)mpt, (void *)cmd));
9161 return;
9162 }
9163
9164 while (prevp != NULL) {
9165 if (prevp->cmd_linkp == cmd) {
9166 if ((prevp->cmd_linkp = cmd->cmd_linkp) == NULL)
9167 mpt->m_tx_waitqtail = &prevp->cmd_linkp;
9168
9169 cmd->cmd_linkp = NULL;
9170 cmd->cmd_queued = FALSE;
9171 NDBG7(("mptsas_tx_waitq_delete: mpt=0x%p cmd=0x%p",
9172 (void *)mpt, (void *)cmd));
9173 return;
9174 }
9175 prevp = prevp->cmd_linkp;
9176 }
9177 cmn_err(CE_PANIC, "mpt: mptsas_tx_waitq_delete: queue botch");
9178 }
9179
9180 /*
9181 * device and bus reset handling
9182 *
9183 * Notes:
9184 * - RESET_ALL: reset the controller
9185 * - RESET_TARGET: reset the target specified in scsi_address
9186 */
9187 static int
mptsas_scsi_reset(struct scsi_address * ap,int level)9188 mptsas_scsi_reset(struct scsi_address *ap, int level)
9189 {
9190 mptsas_t *mpt = ADDR2MPT(ap);
9191 int rval;
9192 mptsas_tgt_private_t *tgt_private;
9193 mptsas_target_t *ptgt = NULL;
9194
9195 tgt_private = (mptsas_tgt_private_t *)ap->a_hba_tran->tran_tgt_private;
9196 ptgt = tgt_private->t_private;
9197 if (ptgt == NULL) {
9198 return (FALSE);
9199 }
9200 NDBG22(("mptsas_scsi_reset: target=%d level=%d", ptgt->m_devhdl,
9201 level));
9202
9203 mutex_enter(&mpt->m_mutex);
9204 /*
9205 * if we are not in panic set up a reset delay for this target
9206 */
9207 if (!ddi_in_panic()) {
9208 mptsas_setup_bus_reset_delay(mpt);
9209 } else {
9210 drv_usecwait(mpt->m_scsi_reset_delay * 1000);
9211 }
9212 rval = mptsas_do_scsi_reset(mpt, ptgt->m_devhdl);
9213 mutex_exit(&mpt->m_mutex);
9214
9215 /*
9216 * The transport layer expect to only see TRUE and
9217 * FALSE. Therefore, we will adjust the return value
9218 * if mptsas_do_scsi_reset returns FAILED.
9219 */
9220 if (rval == FAILED)
9221 rval = FALSE;
9222 return (rval);
9223 }
9224
9225 static int
mptsas_do_scsi_reset(mptsas_t * mpt,uint16_t devhdl)9226 mptsas_do_scsi_reset(mptsas_t *mpt, uint16_t devhdl)
9227 {
9228 int rval = FALSE;
9229 uint8_t config, disk;
9230
9231 ASSERT(mutex_owned(&mpt->m_mutex));
9232
9233 if (mptsas_debug_resets) {
9234 mptsas_log(mpt, CE_WARN, "mptsas_do_scsi_reset: target=%d",
9235 devhdl);
9236 }
9237
9238 /*
9239 * Issue a Target Reset message to the target specified but not to a
9240 * disk making up a raid volume. Just look through the RAID config
9241 * Phys Disk list of DevHandles. If the target's DevHandle is in this
9242 * list, then don't reset this target.
9243 */
9244 for (config = 0; config < mpt->m_num_raid_configs; config++) {
9245 for (disk = 0; disk < MPTSAS_MAX_DISKS_IN_CONFIG; disk++) {
9246 if (devhdl == mpt->m_raidconfig[config].
9247 m_physdisk_devhdl[disk]) {
9248 return (TRUE);
9249 }
9250 }
9251 }
9252
9253 rval = mptsas_ioc_task_management(mpt,
9254 MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET, devhdl, 0, NULL, 0, 0);
9255
9256 mptsas_doneq_empty(mpt);
9257 return (rval);
9258 }
9259
9260 static int
mptsas_scsi_reset_notify(struct scsi_address * ap,int flag,void (* callback)(caddr_t),caddr_t arg)9261 mptsas_scsi_reset_notify(struct scsi_address *ap, int flag,
9262 void (*callback)(caddr_t), caddr_t arg)
9263 {
9264 mptsas_t *mpt = ADDR2MPT(ap);
9265
9266 NDBG22(("mptsas_scsi_reset_notify: tgt=%d", ap->a_target));
9267
9268 return (scsi_hba_reset_notify_setup(ap, flag, callback, arg,
9269 &mpt->m_mutex, &mpt->m_reset_notify_listf));
9270 }
9271
9272 static int
mptsas_get_name(struct scsi_device * sd,char * name,int len)9273 mptsas_get_name(struct scsi_device *sd, char *name, int len)
9274 {
9275 dev_info_t *lun_dip = NULL;
9276
9277 ASSERT(sd != NULL);
9278 ASSERT(name != NULL);
9279 lun_dip = sd->sd_dev;
9280 ASSERT(lun_dip != NULL);
9281
9282 if (mptsas_name_child(lun_dip, name, len) == DDI_SUCCESS) {
9283 return (1);
9284 } else {
9285 return (0);
9286 }
9287 }
9288
9289 static int
mptsas_get_bus_addr(struct scsi_device * sd,char * name,int len)9290 mptsas_get_bus_addr(struct scsi_device *sd, char *name, int len)
9291 {
9292 return (mptsas_get_name(sd, name, len));
9293 }
9294
9295 void
mptsas_set_throttle(mptsas_t * mpt,mptsas_target_t * ptgt,int what)9296 mptsas_set_throttle(mptsas_t *mpt, mptsas_target_t *ptgt, int what)
9297 {
9298
9299 NDBG25(("mptsas_set_throttle: throttle=%x", what));
9300
9301 /*
9302 * if the bus is draining/quiesced, no changes to the throttles
9303 * are allowed. Not allowing change of throttles during draining
9304 * limits error recovery but will reduce draining time
9305 *
9306 * all throttles should have been set to HOLD_THROTTLE
9307 */
9308 if (mpt->m_softstate & (MPTSAS_SS_QUIESCED | MPTSAS_SS_DRAINING)) {
9309 return;
9310 }
9311
9312 if (what == HOLD_THROTTLE) {
9313 ptgt->m_t_throttle = HOLD_THROTTLE;
9314 } else if (ptgt->m_reset_delay == 0) {
9315 ptgt->m_t_throttle = what;
9316 }
9317 }
9318
9319 /*
9320 * Clean up from a device reset.
9321 * For the case of target reset, this function clears the waitq of all
9322 * commands for a particular target. For the case of abort task set, this
9323 * function clears the waitq of all commonds for a particular target/lun.
9324 */
9325 static void
mptsas_flush_target(mptsas_t * mpt,ushort_t target,int lun,uint8_t tasktype)9326 mptsas_flush_target(mptsas_t *mpt, ushort_t target, int lun, uint8_t tasktype)
9327 {
9328 mptsas_slots_t *slots = mpt->m_active;
9329 mptsas_cmd_t *cmd, *next_cmd;
9330 int slot;
9331 uchar_t reason;
9332 uint_t stat;
9333 hrtime_t timestamp;
9334
9335 NDBG25(("mptsas_flush_target: target=%d lun=%d", target, lun));
9336
9337 timestamp = gethrtime();
9338
9339 /*
9340 * Make sure the I/O Controller has flushed all cmds
9341 * that are associated with this target for a target reset
9342 * and target/lun for abort task set.
9343 * Account for TM requests, which use the last SMID.
9344 */
9345 for (slot = 0; slot <= mpt->m_active->m_n_normal; slot++) {
9346 if ((cmd = slots->m_slot[slot]) == NULL)
9347 continue;
9348 reason = CMD_RESET;
9349 stat = STAT_DEV_RESET;
9350 switch (tasktype) {
9351 case MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET:
9352 if (Tgt(cmd) == target) {
9353 if (cmd->cmd_active_expiration <= timestamp) {
9354 /*
9355 * When timeout requested, propagate
9356 * proper reason and statistics to
9357 * target drivers.
9358 */
9359 reason = CMD_TIMEOUT;
9360 stat |= STAT_TIMEOUT;
9361 }
9362 NDBG25(("mptsas_flush_target discovered non-"
9363 "NULL cmd in slot %d, tasktype 0x%x", slot,
9364 tasktype));
9365 mptsas_dump_cmd(mpt, cmd);
9366 mptsas_remove_cmd(mpt, cmd);
9367 mptsas_set_pkt_reason(mpt, cmd, reason, stat);
9368 mptsas_doneq_add(mpt, cmd);
9369 }
9370 break;
9371 case MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET:
9372 reason = CMD_ABORTED;
9373 stat = STAT_ABORTED;
9374 /*FALLTHROUGH*/
9375 case MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET:
9376 if ((Tgt(cmd) == target) && (Lun(cmd) == lun)) {
9377
9378 NDBG25(("mptsas_flush_target discovered non-"
9379 "NULL cmd in slot %d, tasktype 0x%x", slot,
9380 tasktype));
9381 mptsas_dump_cmd(mpt, cmd);
9382 mptsas_remove_cmd(mpt, cmd);
9383 mptsas_set_pkt_reason(mpt, cmd, reason,
9384 stat);
9385 mptsas_doneq_add(mpt, cmd);
9386 }
9387 break;
9388 default:
9389 break;
9390 }
9391 }
9392
9393 /*
9394 * Flush the waitq and tx_waitq of this target's cmds
9395 */
9396 cmd = mpt->m_waitq;
9397
9398 reason = CMD_RESET;
9399 stat = STAT_DEV_RESET;
9400
9401 switch (tasktype) {
9402 case MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET:
9403 while (cmd != NULL) {
9404 next_cmd = cmd->cmd_linkp;
9405 if (Tgt(cmd) == target) {
9406 mptsas_waitq_delete(mpt, cmd);
9407 mptsas_set_pkt_reason(mpt, cmd,
9408 reason, stat);
9409 mptsas_doneq_add(mpt, cmd);
9410 }
9411 cmd = next_cmd;
9412 }
9413 mutex_enter(&mpt->m_tx_waitq_mutex);
9414 cmd = mpt->m_tx_waitq;
9415 while (cmd != NULL) {
9416 next_cmd = cmd->cmd_linkp;
9417 if (Tgt(cmd) == target) {
9418 mptsas_tx_waitq_delete(mpt, cmd);
9419 mutex_exit(&mpt->m_tx_waitq_mutex);
9420 mptsas_set_pkt_reason(mpt, cmd,
9421 reason, stat);
9422 mptsas_doneq_add(mpt, cmd);
9423 mutex_enter(&mpt->m_tx_waitq_mutex);
9424 }
9425 cmd = next_cmd;
9426 }
9427 mutex_exit(&mpt->m_tx_waitq_mutex);
9428 break;
9429 case MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET:
9430 reason = CMD_ABORTED;
9431 stat = STAT_ABORTED;
9432 /*FALLTHROUGH*/
9433 case MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET:
9434 while (cmd != NULL) {
9435 next_cmd = cmd->cmd_linkp;
9436 if ((Tgt(cmd) == target) && (Lun(cmd) == lun)) {
9437 mptsas_waitq_delete(mpt, cmd);
9438 mptsas_set_pkt_reason(mpt, cmd,
9439 reason, stat);
9440 mptsas_doneq_add(mpt, cmd);
9441 }
9442 cmd = next_cmd;
9443 }
9444 mutex_enter(&mpt->m_tx_waitq_mutex);
9445 cmd = mpt->m_tx_waitq;
9446 while (cmd != NULL) {
9447 next_cmd = cmd->cmd_linkp;
9448 if ((Tgt(cmd) == target) && (Lun(cmd) == lun)) {
9449 mptsas_tx_waitq_delete(mpt, cmd);
9450 mutex_exit(&mpt->m_tx_waitq_mutex);
9451 mptsas_set_pkt_reason(mpt, cmd,
9452 reason, stat);
9453 mptsas_doneq_add(mpt, cmd);
9454 mutex_enter(&mpt->m_tx_waitq_mutex);
9455 }
9456 cmd = next_cmd;
9457 }
9458 mutex_exit(&mpt->m_tx_waitq_mutex);
9459 break;
9460 default:
9461 mptsas_log(mpt, CE_WARN, "Unknown task management type %d.",
9462 tasktype);
9463 break;
9464 }
9465 }
9466
9467 /*
9468 * Clean up hba state, abort all outstanding command and commands in waitq
9469 * reset timeout of all targets.
9470 */
9471 static void
mptsas_flush_hba(mptsas_t * mpt)9472 mptsas_flush_hba(mptsas_t *mpt)
9473 {
9474 mptsas_slots_t *slots = mpt->m_active;
9475 mptsas_cmd_t *cmd;
9476 int slot;
9477
9478 NDBG25(("mptsas_flush_hba"));
9479
9480 /*
9481 * The I/O Controller should have already sent back
9482 * all commands via the scsi I/O reply frame. Make
9483 * sure all commands have been flushed.
9484 * Account for TM request, which use the last SMID.
9485 */
9486 for (slot = 0; slot <= mpt->m_active->m_n_normal; slot++) {
9487 if ((cmd = slots->m_slot[slot]) == NULL)
9488 continue;
9489
9490 if (cmd->cmd_flags & CFLAG_CMDIOC) {
9491 /*
9492 * Need to make sure to tell everyone that might be
9493 * waiting on this command that it's going to fail. If
9494 * we get here, this command will never timeout because
9495 * the active command table is going to be re-allocated,
9496 * so there will be nothing to check against a time out.
9497 * Instead, mark the command as failed due to reset.
9498 */
9499 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET,
9500 STAT_BUS_RESET);
9501 if ((cmd->cmd_flags &
9502 (CFLAG_PASSTHRU | CFLAG_CONFIG | CFLAG_FW_DIAG))) {
9503 cmd->cmd_flags |= CFLAG_FINISHED;
9504 cv_broadcast(&mpt->m_passthru_cv);
9505 cv_broadcast(&mpt->m_config_cv);
9506 cv_broadcast(&mpt->m_fw_diag_cv);
9507 }
9508 continue;
9509 }
9510
9511 NDBG25(("mptsas_flush_hba discovered non-NULL cmd in slot %d",
9512 slot));
9513 mptsas_dump_cmd(mpt, cmd);
9514
9515 mptsas_remove_cmd(mpt, cmd);
9516 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET, STAT_BUS_RESET);
9517 mptsas_doneq_add(mpt, cmd);
9518 }
9519
9520 /*
9521 * Flush the waitq.
9522 */
9523 while ((cmd = mptsas_waitq_rm(mpt)) != NULL) {
9524 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET, STAT_BUS_RESET);
9525 if ((cmd->cmd_flags & CFLAG_PASSTHRU) ||
9526 (cmd->cmd_flags & CFLAG_CONFIG) ||
9527 (cmd->cmd_flags & CFLAG_FW_DIAG)) {
9528 cmd->cmd_flags |= CFLAG_FINISHED;
9529 cv_broadcast(&mpt->m_passthru_cv);
9530 cv_broadcast(&mpt->m_config_cv);
9531 cv_broadcast(&mpt->m_fw_diag_cv);
9532 } else {
9533 mptsas_doneq_add(mpt, cmd);
9534 }
9535 }
9536
9537 /*
9538 * Flush the tx_waitq
9539 */
9540 mutex_enter(&mpt->m_tx_waitq_mutex);
9541 while ((cmd = mptsas_tx_waitq_rm(mpt)) != NULL) {
9542 mutex_exit(&mpt->m_tx_waitq_mutex);
9543 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET, STAT_BUS_RESET);
9544 mptsas_doneq_add(mpt, cmd);
9545 mutex_enter(&mpt->m_tx_waitq_mutex);
9546 }
9547 mutex_exit(&mpt->m_tx_waitq_mutex);
9548
9549 /*
9550 * Drain the taskqs prior to reallocating resources. The thread
9551 * passing through here could be launched from either (dr)
9552 * or (event) taskqs so only wait on the 'other' queue since
9553 * waiting on 'this' queue is a deadlock condition.
9554 */
9555 mutex_exit(&mpt->m_mutex);
9556 if (!taskq_member((taskq_t *)mpt->m_event_taskq, curthread))
9557 ddi_taskq_wait(mpt->m_event_taskq);
9558 if (!taskq_member((taskq_t *)mpt->m_dr_taskq, curthread))
9559 ddi_taskq_wait(mpt->m_dr_taskq);
9560
9561 mutex_enter(&mpt->m_mutex);
9562 }
9563
9564 /*
9565 * set pkt_reason and OR in pkt_statistics flag
9566 */
9567 static void
mptsas_set_pkt_reason(mptsas_t * mpt,mptsas_cmd_t * cmd,uchar_t reason,uint_t stat)9568 mptsas_set_pkt_reason(mptsas_t *mpt, mptsas_cmd_t *cmd, uchar_t reason,
9569 uint_t stat)
9570 {
9571 #ifndef __lock_lint
9572 _NOTE(ARGUNUSED(mpt))
9573 #endif
9574
9575 NDBG25(("mptsas_set_pkt_reason: cmd=0x%p reason=%x stat=%x",
9576 (void *)cmd, reason, stat));
9577
9578 if (cmd) {
9579 if (cmd->cmd_pkt->pkt_reason == CMD_CMPLT) {
9580 cmd->cmd_pkt->pkt_reason = reason;
9581 }
9582 cmd->cmd_pkt->pkt_statistics |= stat;
9583 }
9584 }
9585
9586 static void
mptsas_start_watch_reset_delay()9587 mptsas_start_watch_reset_delay()
9588 {
9589 NDBG22(("mptsas_start_watch_reset_delay"));
9590
9591 mutex_enter(&mptsas_global_mutex);
9592 if (mptsas_reset_watch == NULL && mptsas_timeouts_enabled) {
9593 mptsas_reset_watch = timeout(mptsas_watch_reset_delay, NULL,
9594 drv_usectohz((clock_t)
9595 MPTSAS_WATCH_RESET_DELAY_TICK * 1000));
9596 ASSERT(mptsas_reset_watch != NULL);
9597 }
9598 mutex_exit(&mptsas_global_mutex);
9599 }
9600
9601 static void
mptsas_setup_bus_reset_delay(mptsas_t * mpt)9602 mptsas_setup_bus_reset_delay(mptsas_t *mpt)
9603 {
9604 mptsas_target_t *ptgt = NULL;
9605
9606 ASSERT(MUTEX_HELD(&mpt->m_mutex));
9607
9608 NDBG22(("mptsas_setup_bus_reset_delay"));
9609 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
9610 ptgt = refhash_next(mpt->m_targets, ptgt)) {
9611 mptsas_set_throttle(mpt, ptgt, HOLD_THROTTLE);
9612 ptgt->m_reset_delay = mpt->m_scsi_reset_delay;
9613 }
9614
9615 mptsas_start_watch_reset_delay();
9616 }
9617
9618 /*
9619 * mptsas_watch_reset_delay(_subr) is invoked by timeout() and checks every
9620 * mpt instance for active reset delays
9621 */
9622 static void
mptsas_watch_reset_delay(void * arg)9623 mptsas_watch_reset_delay(void *arg)
9624 {
9625 #ifndef __lock_lint
9626 _NOTE(ARGUNUSED(arg))
9627 #endif
9628
9629 mptsas_t *mpt;
9630 int not_done = 0;
9631
9632 NDBG22(("mptsas_watch_reset_delay"));
9633
9634 mutex_enter(&mptsas_global_mutex);
9635 mptsas_reset_watch = 0;
9636 mutex_exit(&mptsas_global_mutex);
9637 rw_enter(&mptsas_global_rwlock, RW_READER);
9638 for (mpt = mptsas_head; mpt != NULL; mpt = mpt->m_next) {
9639 if (mpt->m_tran == 0) {
9640 continue;
9641 }
9642 mutex_enter(&mpt->m_mutex);
9643 not_done += mptsas_watch_reset_delay_subr(mpt);
9644 mutex_exit(&mpt->m_mutex);
9645 }
9646 rw_exit(&mptsas_global_rwlock);
9647
9648 if (not_done) {
9649 mptsas_start_watch_reset_delay();
9650 }
9651 }
9652
9653 static int
mptsas_watch_reset_delay_subr(mptsas_t * mpt)9654 mptsas_watch_reset_delay_subr(mptsas_t *mpt)
9655 {
9656 int done = 0;
9657 int restart = 0;
9658 mptsas_target_t *ptgt = NULL;
9659
9660 NDBG22(("mptsas_watch_reset_delay_subr: mpt=0x%p", (void *)mpt));
9661
9662 ASSERT(mutex_owned(&mpt->m_mutex));
9663
9664 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
9665 ptgt = refhash_next(mpt->m_targets, ptgt)) {
9666 if (ptgt->m_reset_delay != 0) {
9667 ptgt->m_reset_delay -=
9668 MPTSAS_WATCH_RESET_DELAY_TICK;
9669 if (ptgt->m_reset_delay <= 0) {
9670 ptgt->m_reset_delay = 0;
9671 mptsas_set_throttle(mpt, ptgt,
9672 MAX_THROTTLE);
9673 restart++;
9674 } else {
9675 done = -1;
9676 }
9677 }
9678 }
9679
9680 if (restart > 0) {
9681 mptsas_restart_hba(mpt);
9682 }
9683 return (done);
9684 }
9685
9686 #ifdef MPTSAS_TEST
9687 static void
mptsas_test_reset(mptsas_t * mpt,int target)9688 mptsas_test_reset(mptsas_t *mpt, int target)
9689 {
9690 mptsas_target_t *ptgt = NULL;
9691
9692 if (mptsas_rtest == target) {
9693 if (mptsas_do_scsi_reset(mpt, target) == TRUE) {
9694 mptsas_rtest = -1;
9695 }
9696 if (mptsas_rtest == -1) {
9697 NDBG22(("mptsas_test_reset success"));
9698 }
9699 }
9700 }
9701 #endif
9702
9703 /*
9704 * abort handling:
9705 *
9706 * Notes:
9707 * - if pkt is not NULL, abort just that command
9708 * - if pkt is NULL, abort all outstanding commands for target
9709 */
9710 static int
mptsas_scsi_abort(struct scsi_address * ap,struct scsi_pkt * pkt)9711 mptsas_scsi_abort(struct scsi_address *ap, struct scsi_pkt *pkt)
9712 {
9713 mptsas_t *mpt = ADDR2MPT(ap);
9714 int rval;
9715 mptsas_tgt_private_t *tgt_private;
9716 int target, lun;
9717
9718 tgt_private = (mptsas_tgt_private_t *)ap->a_hba_tran->
9719 tran_tgt_private;
9720 ASSERT(tgt_private != NULL);
9721 target = tgt_private->t_private->m_devhdl;
9722 lun = tgt_private->t_lun;
9723
9724 NDBG23(("mptsas_scsi_abort: target=%d.%d", target, lun));
9725
9726 mutex_enter(&mpt->m_mutex);
9727 rval = mptsas_do_scsi_abort(mpt, target, lun, pkt);
9728 mutex_exit(&mpt->m_mutex);
9729 return (rval);
9730 }
9731
9732 static int
mptsas_do_scsi_abort(mptsas_t * mpt,int target,int lun,struct scsi_pkt * pkt)9733 mptsas_do_scsi_abort(mptsas_t *mpt, int target, int lun, struct scsi_pkt *pkt)
9734 {
9735 mptsas_cmd_t *sp = NULL;
9736 mptsas_slots_t *slots = mpt->m_active;
9737 int rval = FALSE;
9738
9739 ASSERT(mutex_owned(&mpt->m_mutex));
9740
9741 /*
9742 * Abort the command pkt on the target/lun in ap. If pkt is
9743 * NULL, abort all outstanding commands on that target/lun.
9744 * If you can abort them, return 1, else return 0.
9745 * Each packet that's aborted should be sent back to the target
9746 * driver through the callback routine, with pkt_reason set to
9747 * CMD_ABORTED.
9748 *
9749 * abort cmd pkt on HBA hardware; clean out of outstanding
9750 * command lists, etc.
9751 */
9752 if (pkt != NULL) {
9753 /* abort the specified packet */
9754 sp = PKT2CMD(pkt);
9755
9756 if (sp->cmd_queued) {
9757 NDBG23(("mptsas_do_scsi_abort: queued sp=0x%p aborted",
9758 (void *)sp));
9759 mptsas_waitq_delete(mpt, sp);
9760 mptsas_set_pkt_reason(mpt, sp, CMD_ABORTED,
9761 STAT_ABORTED);
9762 mptsas_doneq_add(mpt, sp);
9763 rval = TRUE;
9764 goto done;
9765 }
9766
9767 /*
9768 * Have mpt firmware abort this command
9769 */
9770
9771 if (slots->m_slot[sp->cmd_slot] != NULL) {
9772 rval = mptsas_ioc_task_management(mpt,
9773 MPI2_SCSITASKMGMT_TASKTYPE_ABORT_TASK, target,
9774 lun, NULL, 0, 0);
9775
9776 /*
9777 * The transport layer expects only TRUE and FALSE.
9778 * Therefore, if mptsas_ioc_task_management returns
9779 * FAILED we will return FALSE.
9780 */
9781 if (rval == FAILED)
9782 rval = FALSE;
9783 goto done;
9784 }
9785 }
9786
9787 /*
9788 * If pkt is NULL then abort task set
9789 */
9790 rval = mptsas_ioc_task_management(mpt,
9791 MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET, target, lun, NULL, 0, 0);
9792
9793 /*
9794 * The transport layer expects only TRUE and FALSE.
9795 * Therefore, if mptsas_ioc_task_management returns
9796 * FAILED we will return FALSE.
9797 */
9798 if (rval == FAILED)
9799 rval = FALSE;
9800
9801 #ifdef MPTSAS_TEST
9802 if (rval && mptsas_test_stop) {
9803 debug_enter("mptsas_do_scsi_abort");
9804 }
9805 #endif
9806
9807 done:
9808 mptsas_doneq_empty(mpt);
9809 return (rval);
9810 }
9811
9812 /*
9813 * capability handling:
9814 * (*tran_getcap). Get the capability named, and return its value.
9815 */
9816 static int
mptsas_scsi_getcap(struct scsi_address * ap,char * cap,int tgtonly)9817 mptsas_scsi_getcap(struct scsi_address *ap, char *cap, int tgtonly)
9818 {
9819 mptsas_t *mpt = ADDR2MPT(ap);
9820 int ckey;
9821 int rval = FALSE;
9822
9823 NDBG24(("mptsas_scsi_getcap: target=%d, cap=%s tgtonly=%x",
9824 ap->a_target, cap, tgtonly));
9825
9826 mutex_enter(&mpt->m_mutex);
9827
9828 if ((mptsas_scsi_capchk(cap, tgtonly, &ckey)) != TRUE) {
9829 mutex_exit(&mpt->m_mutex);
9830 return (UNDEFINED);
9831 }
9832
9833 switch (ckey) {
9834 case SCSI_CAP_DMA_MAX:
9835 rval = (int)mpt->m_msg_dma_attr.dma_attr_maxxfer;
9836 break;
9837 case SCSI_CAP_ARQ:
9838 rval = TRUE;
9839 break;
9840 case SCSI_CAP_MSG_OUT:
9841 case SCSI_CAP_PARITY:
9842 case SCSI_CAP_UNTAGGED_QING:
9843 rval = TRUE;
9844 break;
9845 case SCSI_CAP_TAGGED_QING:
9846 rval = TRUE;
9847 break;
9848 case SCSI_CAP_RESET_NOTIFICATION:
9849 rval = TRUE;
9850 break;
9851 case SCSI_CAP_LINKED_CMDS:
9852 rval = FALSE;
9853 break;
9854 case SCSI_CAP_QFULL_RETRIES:
9855 rval = ((mptsas_tgt_private_t *)(ap->a_hba_tran->
9856 tran_tgt_private))->t_private->m_qfull_retries;
9857 break;
9858 case SCSI_CAP_QFULL_RETRY_INTERVAL:
9859 rval = drv_hztousec(((mptsas_tgt_private_t *)
9860 (ap->a_hba_tran->tran_tgt_private))->
9861 t_private->m_qfull_retry_interval) / 1000;
9862 break;
9863 case SCSI_CAP_CDB_LEN:
9864 rval = CDB_GROUP4;
9865 break;
9866 case SCSI_CAP_INTERCONNECT_TYPE:
9867 rval = INTERCONNECT_SAS;
9868 break;
9869 case SCSI_CAP_TRAN_LAYER_RETRIES:
9870 if (mpt->m_ioc_capabilities &
9871 MPI2_IOCFACTS_CAPABILITY_TLR)
9872 rval = TRUE;
9873 else
9874 rval = FALSE;
9875 break;
9876 default:
9877 rval = UNDEFINED;
9878 break;
9879 }
9880
9881 NDBG24(("mptsas_scsi_getcap: %s, rval=%x", cap, rval));
9882
9883 mutex_exit(&mpt->m_mutex);
9884 return (rval);
9885 }
9886
9887 /*
9888 * (*tran_setcap). Set the capability named to the value given.
9889 */
9890 static int
mptsas_scsi_setcap(struct scsi_address * ap,char * cap,int value,int tgtonly)9891 mptsas_scsi_setcap(struct scsi_address *ap, char *cap, int value, int tgtonly)
9892 {
9893 mptsas_t *mpt = ADDR2MPT(ap);
9894 int ckey;
9895 int rval = FALSE;
9896
9897 NDBG24(("mptsas_scsi_setcap: target=%d, cap=%s value=%x tgtonly=%x",
9898 ap->a_target, cap, value, tgtonly));
9899
9900 if (!tgtonly) {
9901 return (rval);
9902 }
9903
9904 mutex_enter(&mpt->m_mutex);
9905
9906 if ((mptsas_scsi_capchk(cap, tgtonly, &ckey)) != TRUE) {
9907 mutex_exit(&mpt->m_mutex);
9908 return (UNDEFINED);
9909 }
9910
9911 switch (ckey) {
9912 case SCSI_CAP_DMA_MAX:
9913 case SCSI_CAP_MSG_OUT:
9914 case SCSI_CAP_PARITY:
9915 case SCSI_CAP_INITIATOR_ID:
9916 case SCSI_CAP_LINKED_CMDS:
9917 case SCSI_CAP_UNTAGGED_QING:
9918 case SCSI_CAP_RESET_NOTIFICATION:
9919 /*
9920 * None of these are settable via
9921 * the capability interface.
9922 */
9923 break;
9924 case SCSI_CAP_ARQ:
9925 /*
9926 * We cannot turn off arq so return false if asked to
9927 */
9928 if (value) {
9929 rval = TRUE;
9930 } else {
9931 rval = FALSE;
9932 }
9933 break;
9934 case SCSI_CAP_TAGGED_QING:
9935 mptsas_set_throttle(mpt, ((mptsas_tgt_private_t *)
9936 (ap->a_hba_tran->tran_tgt_private))->t_private,
9937 MAX_THROTTLE);
9938 rval = TRUE;
9939 break;
9940 case SCSI_CAP_QFULL_RETRIES:
9941 ((mptsas_tgt_private_t *)(ap->a_hba_tran->tran_tgt_private))->
9942 t_private->m_qfull_retries = (uchar_t)value;
9943 rval = TRUE;
9944 break;
9945 case SCSI_CAP_QFULL_RETRY_INTERVAL:
9946 ((mptsas_tgt_private_t *)(ap->a_hba_tran->tran_tgt_private))->
9947 t_private->m_qfull_retry_interval =
9948 drv_usectohz(value * 1000);
9949 rval = TRUE;
9950 break;
9951 default:
9952 rval = UNDEFINED;
9953 break;
9954 }
9955 mutex_exit(&mpt->m_mutex);
9956 return (rval);
9957 }
9958
9959 /*
9960 * Utility routine for mptsas_ifsetcap/ifgetcap
9961 */
9962 /*ARGSUSED*/
9963 static int
mptsas_scsi_capchk(char * cap,int tgtonly,int * cidxp)9964 mptsas_scsi_capchk(char *cap, int tgtonly, int *cidxp)
9965 {
9966 NDBG24(("mptsas_scsi_capchk: cap=%s", cap));
9967
9968 if (!cap)
9969 return (FALSE);
9970
9971 *cidxp = scsi_hba_lookup_capstr(cap);
9972 return (TRUE);
9973 }
9974
9975 static int
mptsas_alloc_active_slots(mptsas_t * mpt,int flag)9976 mptsas_alloc_active_slots(mptsas_t *mpt, int flag)
9977 {
9978 mptsas_slots_t *old_active = mpt->m_active;
9979 mptsas_slots_t *new_active;
9980 size_t size;
9981
9982 /*
9983 * if there are active commands, then we cannot
9984 * change size of active slots array.
9985 */
9986 ASSERT(mpt->m_ncmds == 0);
9987
9988 size = MPTSAS_SLOTS_SIZE(mpt);
9989 new_active = kmem_zalloc(size, flag);
9990 if (new_active == NULL) {
9991 NDBG1(("new active alloc failed"));
9992 return (-1);
9993 }
9994 /*
9995 * Since SMID 0 is reserved and the TM slot is reserved, the
9996 * number of slots that can be used at any one time is
9997 * m_max_requests - 2.
9998 */
9999 new_active->m_n_normal = (mpt->m_max_requests - 2);
10000 new_active->m_size = size;
10001 new_active->m_rotor = 1;
10002 if (old_active)
10003 mptsas_free_active_slots(mpt);
10004 mpt->m_active = new_active;
10005
10006 return (0);
10007 }
10008
10009 static void
mptsas_free_active_slots(mptsas_t * mpt)10010 mptsas_free_active_slots(mptsas_t *mpt)
10011 {
10012 mptsas_slots_t *active = mpt->m_active;
10013 size_t size;
10014
10015 if (active == NULL)
10016 return;
10017 size = active->m_size;
10018 kmem_free(active, size);
10019 mpt->m_active = NULL;
10020 }
10021
10022 /*
10023 * Error logging, printing, and debug print routines.
10024 */
10025 static char *mptsas_label = "mpt_sas";
10026
10027 /*PRINTFLIKE3*/
10028 void
mptsas_log(mptsas_t * mpt,int level,char * fmt,...)10029 mptsas_log(mptsas_t *mpt, int level, char *fmt, ...)
10030 {
10031 dev_info_t *dev;
10032 va_list ap;
10033
10034 if (mpt) {
10035 dev = mpt->m_dip;
10036 } else {
10037 dev = 0;
10038 }
10039
10040 mutex_enter(&mptsas_log_mutex);
10041
10042 va_start(ap, fmt);
10043 (void) vsprintf(mptsas_log_buf, fmt, ap);
10044 va_end(ap);
10045
10046 if (level == CE_CONT) {
10047 scsi_log(dev, mptsas_label, level, "%s\n", mptsas_log_buf);
10048 } else {
10049 scsi_log(dev, mptsas_label, level, "%s", mptsas_log_buf);
10050 }
10051
10052 mutex_exit(&mptsas_log_mutex);
10053 }
10054
10055 #ifdef MPTSAS_DEBUG
10056 /*
10057 * Use a circular buffer to log messages to private memory.
10058 * Increment idx atomically to minimize risk to miss lines.
10059 * It's fast and does not hold up the proceedings too much.
10060 */
10061 static const size_t mptsas_dbglog_linecnt = MPTSAS_DBGLOG_LINECNT;
10062 static const size_t mptsas_dbglog_linelen = MPTSAS_DBGLOG_LINELEN;
10063 static char mptsas_dbglog_bufs[MPTSAS_DBGLOG_LINECNT][MPTSAS_DBGLOG_LINELEN];
10064 static uint32_t mptsas_dbglog_idx = 0;
10065
10066 /*PRINTFLIKE1*/
10067 void
mptsas_debug_log(char * fmt,...)10068 mptsas_debug_log(char *fmt, ...)
10069 {
10070 va_list ap;
10071 uint32_t idx;
10072
10073 idx = atomic_inc_32_nv(&mptsas_dbglog_idx) &
10074 (mptsas_dbglog_linecnt - 1);
10075
10076 va_start(ap, fmt);
10077 (void) vsnprintf(mptsas_dbglog_bufs[idx],
10078 mptsas_dbglog_linelen, fmt, ap);
10079 va_end(ap);
10080 }
10081
10082 /*PRINTFLIKE1*/
10083 void
mptsas_printf(char * fmt,...)10084 mptsas_printf(char *fmt, ...)
10085 {
10086 dev_info_t *dev = 0;
10087 va_list ap;
10088
10089 mutex_enter(&mptsas_log_mutex);
10090
10091 va_start(ap, fmt);
10092 (void) vsprintf(mptsas_log_buf, fmt, ap);
10093 va_end(ap);
10094
10095 #ifdef PROM_PRINTF
10096 prom_printf("%s:\t%s\n", mptsas_label, mptsas_log_buf);
10097 #else
10098 scsi_log(dev, mptsas_label, CE_CONT, "!%s\n", mptsas_log_buf);
10099 #endif
10100 mutex_exit(&mptsas_log_mutex);
10101 }
10102 #endif
10103
10104 /*
10105 * timeout handling
10106 */
10107 static void
mptsas_watch(void * arg)10108 mptsas_watch(void *arg)
10109 {
10110 #ifndef __lock_lint
10111 _NOTE(ARGUNUSED(arg))
10112 #endif
10113
10114 mptsas_t *mpt;
10115 uint32_t doorbell;
10116
10117 NDBG30(("mptsas_watch"));
10118
10119 rw_enter(&mptsas_global_rwlock, RW_READER);
10120 for (mpt = mptsas_head; mpt != (mptsas_t *)NULL; mpt = mpt->m_next) {
10121
10122 mutex_enter(&mpt->m_mutex);
10123
10124 /* Skip device if not powered on */
10125 if (mpt->m_options & MPTSAS_OPT_PM) {
10126 if (mpt->m_power_level == PM_LEVEL_D0) {
10127 (void) pm_busy_component(mpt->m_dip, 0);
10128 mpt->m_busy = 1;
10129 } else {
10130 mutex_exit(&mpt->m_mutex);
10131 continue;
10132 }
10133 }
10134
10135 /*
10136 * Check if controller is in a FAULT state. If so, reset it.
10137 */
10138 doorbell = ddi_get32(mpt->m_datap, &mpt->m_reg->Doorbell);
10139 if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
10140 doorbell &= MPI2_DOORBELL_DATA_MASK;
10141 mptsas_log(mpt, CE_WARN, "MPT Firmware Fault, "
10142 "code: %04x", doorbell);
10143 mpt->m_softstate &= ~MPTSAS_SS_MSG_UNIT_RESET;
10144 if ((mptsas_restart_ioc(mpt)) == DDI_FAILURE) {
10145 mptsas_log(mpt, CE_WARN, "Reset failed"
10146 "after fault was detected");
10147 }
10148 }
10149
10150 /*
10151 * For now, always call mptsas_watchsubr.
10152 */
10153 mptsas_watchsubr(mpt);
10154
10155 if (mpt->m_options & MPTSAS_OPT_PM) {
10156 mpt->m_busy = 0;
10157 (void) pm_idle_component(mpt->m_dip, 0);
10158 }
10159
10160 mutex_exit(&mpt->m_mutex);
10161 }
10162 rw_exit(&mptsas_global_rwlock);
10163
10164 mutex_enter(&mptsas_global_mutex);
10165 if (mptsas_timeouts_enabled)
10166 mptsas_timeout_id = timeout(mptsas_watch, NULL, mptsas_tick);
10167 mutex_exit(&mptsas_global_mutex);
10168 }
10169
10170 static void
mptsas_watchsubr_tgt(mptsas_t * mpt,mptsas_target_t * ptgt,hrtime_t timestamp)10171 mptsas_watchsubr_tgt(mptsas_t *mpt, mptsas_target_t *ptgt, hrtime_t timestamp)
10172 {
10173 mptsas_cmd_t *cmd;
10174
10175 /*
10176 * If we were draining due to a qfull condition,
10177 * go back to full throttle.
10178 */
10179 if ((ptgt->m_t_throttle < MAX_THROTTLE) &&
10180 (ptgt->m_t_throttle > HOLD_THROTTLE) &&
10181 (ptgt->m_t_ncmds < ptgt->m_t_throttle)) {
10182 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE);
10183 mptsas_restart_hba(mpt);
10184 }
10185
10186 cmd = TAILQ_LAST(&ptgt->m_active_cmdq, mptsas_active_cmdq);
10187 if (cmd == NULL)
10188 return;
10189
10190 if (cmd->cmd_active_expiration <= timestamp) {
10191 /*
10192 * Earliest command timeout expired. Drain throttle.
10193 */
10194 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE);
10195
10196 /*
10197 * Check for remaining commands.
10198 */
10199 cmd = TAILQ_FIRST(&ptgt->m_active_cmdq);
10200 if (cmd->cmd_active_expiration > timestamp) {
10201 /*
10202 * Wait for remaining commands to complete or
10203 * time out.
10204 */
10205 NDBG23(("command timed out, pending drain"));
10206 return;
10207 }
10208
10209 /*
10210 * All command timeouts expired.
10211 */
10212 mptsas_log(mpt, CE_NOTE, "Timeout of %d seconds "
10213 "expired with %d commands on target %d lun %d.",
10214 cmd->cmd_pkt->pkt_time, ptgt->m_t_ncmds,
10215 ptgt->m_devhdl, Lun(cmd));
10216
10217 mptsas_cmd_timeout(mpt, ptgt);
10218 } else if (cmd->cmd_active_expiration <=
10219 timestamp + (hrtime_t)mptsas_scsi_watchdog_tick * NANOSEC) {
10220 NDBG23(("pending timeout"));
10221 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE);
10222 }
10223 }
10224
10225 static void
mptsas_watchsubr(mptsas_t * mpt)10226 mptsas_watchsubr(mptsas_t *mpt)
10227 {
10228 int i;
10229 mptsas_cmd_t *cmd;
10230 mptsas_target_t *ptgt = NULL;
10231 hrtime_t timestamp = gethrtime();
10232
10233 ASSERT(MUTEX_HELD(&mpt->m_mutex));
10234
10235 NDBG30(("mptsas_watchsubr: mpt=0x%p", (void *)mpt));
10236
10237 #ifdef MPTSAS_TEST
10238 if (mptsas_enable_untagged) {
10239 mptsas_test_untagged++;
10240 }
10241 #endif
10242
10243 /*
10244 * Check for commands stuck in active slot
10245 * Account for TM requests, which use the last SMID.
10246 */
10247 for (i = 0; i <= mpt->m_active->m_n_normal; i++) {
10248 if ((cmd = mpt->m_active->m_slot[i]) != NULL) {
10249 if (cmd->cmd_active_expiration <= timestamp) {
10250 if ((cmd->cmd_flags & CFLAG_CMDIOC) == 0) {
10251 /*
10252 * There seems to be a command stuck
10253 * in the active slot. Drain throttle.
10254 */
10255 mptsas_set_throttle(mpt,
10256 cmd->cmd_tgt_addr,
10257 DRAIN_THROTTLE);
10258 } else if (cmd->cmd_flags &
10259 (CFLAG_PASSTHRU | CFLAG_CONFIG |
10260 CFLAG_FW_DIAG)) {
10261 /*
10262 * passthrough command timeout
10263 */
10264 cmd->cmd_flags |= (CFLAG_FINISHED |
10265 CFLAG_TIMEOUT);
10266 cv_broadcast(&mpt->m_passthru_cv);
10267 cv_broadcast(&mpt->m_config_cv);
10268 cv_broadcast(&mpt->m_fw_diag_cv);
10269 }
10270 }
10271 }
10272 }
10273
10274 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
10275 ptgt = refhash_next(mpt->m_targets, ptgt)) {
10276 mptsas_watchsubr_tgt(mpt, ptgt, timestamp);
10277 }
10278
10279 for (ptgt = refhash_first(mpt->m_tmp_targets); ptgt != NULL;
10280 ptgt = refhash_next(mpt->m_tmp_targets, ptgt)) {
10281 mptsas_watchsubr_tgt(mpt, ptgt, timestamp);
10282 }
10283 }
10284
10285 /*
10286 * timeout recovery
10287 */
10288 static void
mptsas_cmd_timeout(mptsas_t * mpt,mptsas_target_t * ptgt)10289 mptsas_cmd_timeout(mptsas_t *mpt, mptsas_target_t *ptgt)
10290 {
10291 uint16_t devhdl;
10292 uint64_t sas_wwn;
10293 uint8_t phy;
10294 char wwn_str[MPTSAS_WWN_STRLEN];
10295
10296 devhdl = ptgt->m_devhdl;
10297 sas_wwn = ptgt->m_addr.mta_wwn;
10298 phy = ptgt->m_phynum;
10299 if (sas_wwn == 0) {
10300 (void) sprintf(wwn_str, "p%x", phy);
10301 } else {
10302 (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn);
10303 }
10304
10305 NDBG29(("mptsas_cmd_timeout: target=%d", devhdl));
10306 mptsas_log(mpt, CE_WARN, "Disconnected command timeout for "
10307 "target %d %s, enclosure %u", devhdl, wwn_str,
10308 ptgt->m_enclosure);
10309
10310 /*
10311 * Abort all outstanding commands on the device.
10312 */
10313 NDBG29(("mptsas_cmd_timeout: device reset"));
10314 if (mptsas_do_scsi_reset(mpt, devhdl) != TRUE) {
10315 mptsas_log(mpt, CE_WARN, "Target %d reset for command timeout "
10316 "recovery failed!", devhdl);
10317 }
10318 }
10319
10320 /*
10321 * Device / Hotplug control
10322 */
10323 static int
mptsas_scsi_quiesce(dev_info_t * dip)10324 mptsas_scsi_quiesce(dev_info_t *dip)
10325 {
10326 mptsas_t *mpt;
10327 scsi_hba_tran_t *tran;
10328
10329 tran = ddi_get_driver_private(dip);
10330 if (tran == NULL || (mpt = TRAN2MPT(tran)) == NULL)
10331 return (-1);
10332
10333 return (mptsas_quiesce_bus(mpt));
10334 }
10335
10336 static int
mptsas_scsi_unquiesce(dev_info_t * dip)10337 mptsas_scsi_unquiesce(dev_info_t *dip)
10338 {
10339 mptsas_t *mpt;
10340 scsi_hba_tran_t *tran;
10341
10342 tran = ddi_get_driver_private(dip);
10343 if (tran == NULL || (mpt = TRAN2MPT(tran)) == NULL)
10344 return (-1);
10345
10346 return (mptsas_unquiesce_bus(mpt));
10347 }
10348
10349 static int
mptsas_quiesce_bus(mptsas_t * mpt)10350 mptsas_quiesce_bus(mptsas_t *mpt)
10351 {
10352 mptsas_target_t *ptgt = NULL;
10353
10354 NDBG28(("mptsas_quiesce_bus"));
10355 mutex_enter(&mpt->m_mutex);
10356
10357 /* Set all the throttles to zero */
10358 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
10359 ptgt = refhash_next(mpt->m_targets, ptgt)) {
10360 mptsas_set_throttle(mpt, ptgt, HOLD_THROTTLE);
10361 }
10362
10363 /* If there are any outstanding commands in the queue */
10364 if (mpt->m_ncmds) {
10365 mpt->m_softstate |= MPTSAS_SS_DRAINING;
10366 mpt->m_quiesce_timeid = timeout(mptsas_ncmds_checkdrain,
10367 mpt, (MPTSAS_QUIESCE_TIMEOUT * drv_usectohz(1000000)));
10368 if (cv_wait_sig(&mpt->m_cv, &mpt->m_mutex) == 0) {
10369 /*
10370 * Quiesce has been interrupted
10371 */
10372 mpt->m_softstate &= ~MPTSAS_SS_DRAINING;
10373 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
10374 ptgt = refhash_next(mpt->m_targets, ptgt)) {
10375 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE);
10376 }
10377 mptsas_restart_hba(mpt);
10378 if (mpt->m_quiesce_timeid != 0) {
10379 timeout_id_t tid = mpt->m_quiesce_timeid;
10380 mpt->m_quiesce_timeid = 0;
10381 mutex_exit(&mpt->m_mutex);
10382 (void) untimeout(tid);
10383 return (-1);
10384 }
10385 mutex_exit(&mpt->m_mutex);
10386 return (-1);
10387 } else {
10388 /* Bus has been quiesced */
10389 ASSERT(mpt->m_quiesce_timeid == 0);
10390 mpt->m_softstate &= ~MPTSAS_SS_DRAINING;
10391 mpt->m_softstate |= MPTSAS_SS_QUIESCED;
10392 mutex_exit(&mpt->m_mutex);
10393 return (0);
10394 }
10395 }
10396 /* Bus was not busy - QUIESCED */
10397 mutex_exit(&mpt->m_mutex);
10398
10399 return (0);
10400 }
10401
10402 static int
mptsas_unquiesce_bus(mptsas_t * mpt)10403 mptsas_unquiesce_bus(mptsas_t *mpt)
10404 {
10405 mptsas_target_t *ptgt = NULL;
10406
10407 NDBG28(("mptsas_unquiesce_bus"));
10408 mutex_enter(&mpt->m_mutex);
10409 mpt->m_softstate &= ~MPTSAS_SS_QUIESCED;
10410 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
10411 ptgt = refhash_next(mpt->m_targets, ptgt)) {
10412 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE);
10413 }
10414 mptsas_restart_hba(mpt);
10415 mutex_exit(&mpt->m_mutex);
10416 return (0);
10417 }
10418
10419 static void
mptsas_ncmds_checkdrain(void * arg)10420 mptsas_ncmds_checkdrain(void *arg)
10421 {
10422 mptsas_t *mpt = arg;
10423 mptsas_target_t *ptgt = NULL;
10424
10425 mutex_enter(&mpt->m_mutex);
10426 if (mpt->m_softstate & MPTSAS_SS_DRAINING) {
10427 mpt->m_quiesce_timeid = 0;
10428 if (mpt->m_ncmds == 0) {
10429 /* Command queue has been drained */
10430 cv_signal(&mpt->m_cv);
10431 } else {
10432 /*
10433 * The throttle may have been reset because
10434 * of a SCSI bus reset
10435 */
10436 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
10437 ptgt = refhash_next(mpt->m_targets, ptgt)) {
10438 mptsas_set_throttle(mpt, ptgt, HOLD_THROTTLE);
10439 }
10440
10441 mpt->m_quiesce_timeid = timeout(mptsas_ncmds_checkdrain,
10442 mpt, (MPTSAS_QUIESCE_TIMEOUT *
10443 drv_usectohz(1000000)));
10444 }
10445 }
10446 mutex_exit(&mpt->m_mutex);
10447 }
10448
10449 /*ARGSUSED*/
10450 static void
mptsas_dump_cmd(mptsas_t * mpt,mptsas_cmd_t * cmd)10451 mptsas_dump_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd)
10452 {
10453 int i;
10454 uint8_t *cp = (uchar_t *)cmd->cmd_pkt->pkt_cdbp;
10455 char buf[128];
10456
10457 buf[0] = '\0';
10458 NDBG25(("?Cmd (0x%p) dump for Target %d Lun %d:\n", (void *)cmd,
10459 Tgt(cmd), Lun(cmd)));
10460 (void) sprintf(&buf[0], "\tcdb=[");
10461 for (i = 0; i < (int)cmd->cmd_cdblen; i++) {
10462 (void) sprintf(&buf[strlen(buf)], " 0x%x", *cp++);
10463 }
10464 (void) sprintf(&buf[strlen(buf)], " ]");
10465 NDBG25(("?%s\n", buf));
10466 NDBG25(("?pkt_flags=0x%x pkt_statistics=0x%x pkt_state=0x%x\n",
10467 cmd->cmd_pkt->pkt_flags, cmd->cmd_pkt->pkt_statistics,
10468 cmd->cmd_pkt->pkt_state));
10469 NDBG25(("?pkt_scbp=0x%x cmd_flags=0x%x\n", cmd->cmd_pkt->pkt_scbp ?
10470 *(cmd->cmd_pkt->pkt_scbp) : 0, cmd->cmd_flags));
10471 }
10472
10473 static void
mptsas_passthru_sge(ddi_acc_handle_t acc_hdl,mptsas_pt_request_t * pt,pMpi2SGESimple64_t sgep)10474 mptsas_passthru_sge(ddi_acc_handle_t acc_hdl, mptsas_pt_request_t *pt,
10475 pMpi2SGESimple64_t sgep)
10476 {
10477 uint32_t sge_flags;
10478 uint32_t data_size, dataout_size;
10479 ddi_dma_cookie_t data_cookie;
10480 ddi_dma_cookie_t dataout_cookie;
10481
10482 data_size = pt->data_size;
10483 dataout_size = pt->dataout_size;
10484 data_cookie = pt->data_cookie;
10485 dataout_cookie = pt->dataout_cookie;
10486
10487 if (dataout_size) {
10488 sge_flags = dataout_size |
10489 ((uint32_t)(MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
10490 MPI2_SGE_FLAGS_END_OF_BUFFER |
10491 MPI2_SGE_FLAGS_HOST_TO_IOC |
10492 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) <<
10493 MPI2_SGE_FLAGS_SHIFT);
10494 ddi_put32(acc_hdl, &sgep->FlagsLength, sge_flags);
10495 ddi_put32(acc_hdl, &sgep->Address.Low,
10496 (uint32_t)(dataout_cookie.dmac_laddress &
10497 0xffffffffull));
10498 ddi_put32(acc_hdl, &sgep->Address.High,
10499 (uint32_t)(dataout_cookie.dmac_laddress
10500 >> 32));
10501 sgep++;
10502 }
10503 sge_flags = data_size;
10504 sge_flags |= ((uint32_t)(MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
10505 MPI2_SGE_FLAGS_LAST_ELEMENT |
10506 MPI2_SGE_FLAGS_END_OF_BUFFER |
10507 MPI2_SGE_FLAGS_END_OF_LIST |
10508 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) <<
10509 MPI2_SGE_FLAGS_SHIFT);
10510 if (pt->direction == MPTSAS_PASS_THRU_DIRECTION_WRITE) {
10511 sge_flags |= ((uint32_t)(MPI2_SGE_FLAGS_HOST_TO_IOC) <<
10512 MPI2_SGE_FLAGS_SHIFT);
10513 } else {
10514 sge_flags |= ((uint32_t)(MPI2_SGE_FLAGS_IOC_TO_HOST) <<
10515 MPI2_SGE_FLAGS_SHIFT);
10516 }
10517 ddi_put32(acc_hdl, &sgep->FlagsLength,
10518 sge_flags);
10519 ddi_put32(acc_hdl, &sgep->Address.Low,
10520 (uint32_t)(data_cookie.dmac_laddress &
10521 0xffffffffull));
10522 ddi_put32(acc_hdl, &sgep->Address.High,
10523 (uint32_t)(data_cookie.dmac_laddress >> 32));
10524 }
10525
10526 static void
mptsas_passthru_ieee_sge(ddi_acc_handle_t acc_hdl,mptsas_pt_request_t * pt,pMpi2IeeeSgeSimple64_t ieeesgep)10527 mptsas_passthru_ieee_sge(ddi_acc_handle_t acc_hdl, mptsas_pt_request_t *pt,
10528 pMpi2IeeeSgeSimple64_t ieeesgep)
10529 {
10530 uint8_t sge_flags;
10531 uint32_t data_size, dataout_size;
10532 ddi_dma_cookie_t data_cookie;
10533 ddi_dma_cookie_t dataout_cookie;
10534
10535 data_size = pt->data_size;
10536 dataout_size = pt->dataout_size;
10537 data_cookie = pt->data_cookie;
10538 dataout_cookie = pt->dataout_cookie;
10539
10540 sge_flags = (MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
10541 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR);
10542 if (dataout_size) {
10543 ddi_put32(acc_hdl, &ieeesgep->Length, dataout_size);
10544 ddi_put32(acc_hdl, &ieeesgep->Address.Low,
10545 (uint32_t)(dataout_cookie.dmac_laddress &
10546 0xffffffffull));
10547 ddi_put32(acc_hdl, &ieeesgep->Address.High,
10548 (uint32_t)(dataout_cookie.dmac_laddress >> 32));
10549 ddi_put8(acc_hdl, &ieeesgep->Flags, sge_flags);
10550 ieeesgep++;
10551 }
10552 sge_flags |= MPI25_IEEE_SGE_FLAGS_END_OF_LIST;
10553 ddi_put32(acc_hdl, &ieeesgep->Length, data_size);
10554 ddi_put32(acc_hdl, &ieeesgep->Address.Low,
10555 (uint32_t)(data_cookie.dmac_laddress & 0xffffffffull));
10556 ddi_put32(acc_hdl, &ieeesgep->Address.High,
10557 (uint32_t)(data_cookie.dmac_laddress >> 32));
10558 ddi_put8(acc_hdl, &ieeesgep->Flags, sge_flags);
10559 }
10560
10561 static void
mptsas_start_passthru(mptsas_t * mpt,mptsas_cmd_t * cmd)10562 mptsas_start_passthru(mptsas_t *mpt, mptsas_cmd_t *cmd)
10563 {
10564 caddr_t memp;
10565 pMPI2RequestHeader_t request_hdrp;
10566 struct scsi_pkt *pkt = cmd->cmd_pkt;
10567 mptsas_pt_request_t *pt = pkt->pkt_ha_private;
10568 uint32_t request_size;
10569 uint32_t i;
10570 uint64_t request_desc = 0;
10571 uint8_t desc_type;
10572 uint16_t SMID;
10573 uint8_t *request, function;
10574 ddi_dma_handle_t dma_hdl = mpt->m_dma_req_frame_hdl;
10575 ddi_acc_handle_t acc_hdl = mpt->m_acc_req_frame_hdl;
10576
10577 desc_type = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE;
10578
10579 request = pt->request;
10580 request_size = pt->request_size;
10581
10582 SMID = cmd->cmd_slot;
10583
10584 /*
10585 * Store the passthrough message in memory location
10586 * corresponding to our slot number
10587 */
10588 memp = mpt->m_req_frame + (mpt->m_req_frame_size * SMID);
10589 request_hdrp = (pMPI2RequestHeader_t)memp;
10590 bzero(memp, mpt->m_req_frame_size);
10591
10592 for (i = 0; i < request_size; i++) {
10593 bcopy(request + i, memp + i, 1);
10594 }
10595
10596 NDBG15(("mptsas_start_passthru: Func 0x%x, MsgFlags 0x%x, "
10597 "size=%d, in %d, out %d, SMID %d", request_hdrp->Function,
10598 request_hdrp->MsgFlags, request_size,
10599 pt->data_size, pt->dataout_size, SMID));
10600
10601 /*
10602 * Add an SGE, even if the length is zero.
10603 */
10604 if (mpt->m_MPI25 && pt->simple == 0) {
10605 mptsas_passthru_ieee_sge(acc_hdl, pt,
10606 (pMpi2IeeeSgeSimple64_t)
10607 ((uint8_t *)request_hdrp + pt->sgl_offset));
10608 } else {
10609 mptsas_passthru_sge(acc_hdl, pt,
10610 (pMpi2SGESimple64_t)
10611 ((uint8_t *)request_hdrp + pt->sgl_offset));
10612 }
10613
10614 function = request_hdrp->Function;
10615 if ((function == MPI2_FUNCTION_SCSI_IO_REQUEST) ||
10616 (function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH)) {
10617 pMpi2SCSIIORequest_t scsi_io_req;
10618 caddr_t arsbuf;
10619 uint8_t ars_size;
10620 uint32_t ars_dmaaddrlow;
10621
10622 NDBG15(("mptsas_start_passthru: Is SCSI IO Req"));
10623 scsi_io_req = (pMpi2SCSIIORequest_t)request_hdrp;
10624
10625 if (cmd->cmd_extrqslen != 0) {
10626 /*
10627 * Mapping of the buffer was done in
10628 * mptsas_do_passthru().
10629 * Calculate the DMA address with the same offset.
10630 */
10631 arsbuf = cmd->cmd_arq_buf;
10632 ars_size = cmd->cmd_extrqslen;
10633 ars_dmaaddrlow = (mpt->m_req_sense_dma_addr +
10634 ((uintptr_t)arsbuf - (uintptr_t)mpt->m_req_sense)) &
10635 0xffffffffu;
10636 } else {
10637 arsbuf = mpt->m_req_sense +
10638 (mpt->m_req_sense_size * (SMID-1));
10639 cmd->cmd_arq_buf = arsbuf;
10640 ars_size = mpt->m_req_sense_size;
10641 ars_dmaaddrlow = (mpt->m_req_sense_dma_addr +
10642 (mpt->m_req_sense_size * (SMID-1))) &
10643 0xffffffffu;
10644 }
10645 bzero(arsbuf, ars_size);
10646
10647 ddi_put8(acc_hdl, &scsi_io_req->SenseBufferLength, ars_size);
10648 ddi_put32(acc_hdl, &scsi_io_req->SenseBufferLowAddress,
10649 ars_dmaaddrlow);
10650
10651 /*
10652 * Put SGE for data and data_out buffer at the end of
10653 * scsi_io_request message header.(64 bytes in total)
10654 * Set SGLOffset0 value
10655 */
10656 ddi_put8(acc_hdl, &scsi_io_req->SGLOffset0,
10657 offsetof(MPI2_SCSI_IO_REQUEST, SGL) / 4);
10658
10659 /*
10660 * Setup descriptor info. RAID passthrough must use the
10661 * default request descriptor which is already set, so if this
10662 * is a SCSI IO request, change the descriptor to SCSI IO.
10663 */
10664 if (function == MPI2_FUNCTION_SCSI_IO_REQUEST) {
10665 desc_type = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO;
10666 request_desc = ((uint64_t)ddi_get16(acc_hdl,
10667 &scsi_io_req->DevHandle) << 48);
10668 }
10669 (void) ddi_dma_sync(mpt->m_dma_req_sense_hdl, 0, 0,
10670 DDI_DMA_SYNC_FORDEV);
10671 }
10672
10673 /*
10674 * We must wait till the message has been completed before
10675 * beginning the next message so we wait for this one to
10676 * finish.
10677 */
10678 (void) ddi_dma_sync(dma_hdl, 0, 0, DDI_DMA_SYNC_FORDEV);
10679 request_desc |= (SMID << 16) + desc_type;
10680 cmd->cmd_rfm = 0;
10681 MPTSAS_START_CMD(mpt, request_desc);
10682 if ((mptsas_check_dma_handle(dma_hdl) != DDI_SUCCESS) ||
10683 (mptsas_check_acc_handle(acc_hdl) != DDI_SUCCESS)) {
10684 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
10685 }
10686 }
10687
10688 typedef void (mptsas_pre_f)(mptsas_t *, mptsas_pt_request_t *);
10689 static mptsas_pre_f mpi_pre_ioc_facts;
10690 static mptsas_pre_f mpi_pre_port_facts;
10691 static mptsas_pre_f mpi_pre_fw_download;
10692 static mptsas_pre_f mpi_pre_fw_25_download;
10693 static mptsas_pre_f mpi_pre_fw_upload;
10694 static mptsas_pre_f mpi_pre_fw_25_upload;
10695 static mptsas_pre_f mpi_pre_sata_passthrough;
10696 static mptsas_pre_f mpi_pre_smp_passthrough;
10697 static mptsas_pre_f mpi_pre_config;
10698 static mptsas_pre_f mpi_pre_sas_io_unit_control;
10699 static mptsas_pre_f mpi_pre_scsi_io_req;
10700
10701 /*
10702 * Prepare the pt for a SAS2 FW_DOWNLOAD request.
10703 */
10704 static void
mpi_pre_fw_download(mptsas_t * mpt,mptsas_pt_request_t * pt)10705 mpi_pre_fw_download(mptsas_t *mpt, mptsas_pt_request_t *pt)
10706 {
10707 pMpi2FWDownloadTCSGE_t tcsge;
10708 pMpi2FWDownloadRequest req;
10709
10710 /*
10711 * If SAS3, call separate function.
10712 */
10713 if (mpt->m_MPI25) {
10714 mpi_pre_fw_25_download(mpt, pt);
10715 return;
10716 }
10717
10718 /*
10719 * User requests should come in with the Transaction
10720 * context element where the SGL will go. Putting the
10721 * SGL after that seems to work, but don't really know
10722 * why. Other drivers tend to create an extra SGL and
10723 * refer to the TCE through that.
10724 */
10725 req = (pMpi2FWDownloadRequest)pt->request;
10726 tcsge = (pMpi2FWDownloadTCSGE_t)&req->SGL;
10727 if (tcsge->ContextSize != 0 || tcsge->DetailsLength != 12 ||
10728 tcsge->Flags != MPI2_SGE_FLAGS_TRANSACTION_ELEMENT) {
10729 mptsas_log(mpt, CE_WARN, "FW Download tce invalid!");
10730 }
10731
10732 pt->sgl_offset = offsetof(MPI2_FW_DOWNLOAD_REQUEST, SGL) +
10733 sizeof (*tcsge);
10734 if (pt->request_size != pt->sgl_offset) {
10735 NDBG15(("mpi_pre_fw_download(): Incorrect req size, "
10736 "0x%x, should be 0x%x, dataoutsz 0x%x",
10737 (int)pt->request_size, (int)pt->sgl_offset,
10738 (int)pt->dataout_size));
10739 }
10740 if (pt->data_size < sizeof (MPI2_FW_DOWNLOAD_REPLY)) {
10741 NDBG15(("mpi_pre_fw_download(): Incorrect rep size, "
10742 "0x%x, should be 0x%x", pt->data_size,
10743 (int)sizeof (MPI2_FW_DOWNLOAD_REPLY)));
10744 }
10745 }
10746
10747 /*
10748 * Prepare the pt for a SAS3 FW_DOWNLOAD request.
10749 */
10750 static void
mpi_pre_fw_25_download(mptsas_t * mpt,mptsas_pt_request_t * pt)10751 mpi_pre_fw_25_download(mptsas_t *mpt, mptsas_pt_request_t *pt)
10752 {
10753 pMpi2FWDownloadTCSGE_t tcsge;
10754 pMpi2FWDownloadRequest req2;
10755 pMpi25FWDownloadRequest req25;
10756
10757 /*
10758 * User requests should come in with the Transaction
10759 * context element where the SGL will go. The new firmware
10760 * Doesn't use TCE and has space in the main request for
10761 * this information. So move to the right place.
10762 */
10763 req2 = (pMpi2FWDownloadRequest)pt->request;
10764 req25 = (pMpi25FWDownloadRequest)pt->request;
10765 tcsge = (pMpi2FWDownloadTCSGE_t)&req2->SGL;
10766 if (tcsge->ContextSize != 0 || tcsge->DetailsLength != 12 ||
10767 tcsge->Flags != MPI2_SGE_FLAGS_TRANSACTION_ELEMENT) {
10768 mptsas_log(mpt, CE_WARN, "FW Download tce invalid!");
10769 }
10770 req25->ImageOffset = tcsge->ImageOffset;
10771 req25->ImageSize = tcsge->ImageSize;
10772
10773 pt->sgl_offset = offsetof(MPI25_FW_DOWNLOAD_REQUEST, SGL);
10774 if (pt->request_size != pt->sgl_offset) {
10775 NDBG15(("mpi_pre_fw_25_download(): Incorrect req size, "
10776 "0x%x, should be 0x%x, dataoutsz 0x%x",
10777 pt->request_size, pt->sgl_offset,
10778 pt->dataout_size));
10779 }
10780 if (pt->data_size < sizeof (MPI2_FW_DOWNLOAD_REPLY)) {
10781 NDBG15(("mpi_pre_fw_25_download(): Incorrect rep size, "
10782 "0x%x, should be 0x%x", pt->data_size,
10783 (int)sizeof (MPI2_FW_UPLOAD_REPLY)));
10784 }
10785 }
10786
10787 /*
10788 * Prepare the pt for a SAS2 FW_UPLOAD request.
10789 */
10790 static void
mpi_pre_fw_upload(mptsas_t * mpt,mptsas_pt_request_t * pt)10791 mpi_pre_fw_upload(mptsas_t *mpt, mptsas_pt_request_t *pt)
10792 {
10793 pMpi2FWUploadTCSGE_t tcsge;
10794 pMpi2FWUploadRequest_t req;
10795
10796 /*
10797 * If SAS3, call separate function.
10798 */
10799 if (mpt->m_MPI25) {
10800 mpi_pre_fw_25_upload(mpt, pt);
10801 return;
10802 }
10803
10804 /*
10805 * User requests should come in with the Transaction
10806 * context element where the SGL will go. Putting the
10807 * SGL after that seems to work, but don't really know
10808 * why. Other drivers tend to create an extra SGL and
10809 * refer to the TCE through that.
10810 */
10811 req = (pMpi2FWUploadRequest_t)pt->request;
10812 tcsge = (pMpi2FWUploadTCSGE_t)&req->SGL;
10813 if (tcsge->ContextSize != 0 || tcsge->DetailsLength != 12 ||
10814 tcsge->Flags != MPI2_SGE_FLAGS_TRANSACTION_ELEMENT) {
10815 mptsas_log(mpt, CE_WARN, "FW Upload tce invalid!");
10816 }
10817
10818 pt->sgl_offset = offsetof(MPI2_FW_UPLOAD_REQUEST, SGL) +
10819 sizeof (*tcsge);
10820 if (pt->request_size != pt->sgl_offset) {
10821 NDBG15(("mpi_pre_fw_upload(): Incorrect req size, "
10822 "0x%x, should be 0x%x, dataoutsz 0x%x",
10823 pt->request_size, pt->sgl_offset,
10824 pt->dataout_size));
10825 }
10826 if (pt->data_size < sizeof (MPI2_FW_UPLOAD_REPLY)) {
10827 NDBG15(("mpi_pre_fw_upload(): Incorrect rep size, "
10828 "0x%x, should be 0x%x", pt->data_size,
10829 (int)sizeof (MPI2_FW_UPLOAD_REPLY)));
10830 }
10831 }
10832
10833 /*
10834 * Prepare the pt a SAS3 FW_UPLOAD request.
10835 */
10836 static void
mpi_pre_fw_25_upload(mptsas_t * mpt,mptsas_pt_request_t * pt)10837 mpi_pre_fw_25_upload(mptsas_t *mpt, mptsas_pt_request_t *pt)
10838 {
10839 pMpi2FWUploadTCSGE_t tcsge;
10840 pMpi2FWUploadRequest_t req2;
10841 pMpi25FWUploadRequest_t req25;
10842
10843 /*
10844 * User requests should come in with the Transaction
10845 * context element where the SGL will go. The new firmware
10846 * Doesn't use TCE and has space in the main request for
10847 * this information. So move to the right place.
10848 */
10849 req2 = (pMpi2FWUploadRequest_t)pt->request;
10850 req25 = (pMpi25FWUploadRequest_t)pt->request;
10851 tcsge = (pMpi2FWUploadTCSGE_t)&req2->SGL;
10852 if (tcsge->ContextSize != 0 || tcsge->DetailsLength != 12 ||
10853 tcsge->Flags != MPI2_SGE_FLAGS_TRANSACTION_ELEMENT) {
10854 mptsas_log(mpt, CE_WARN, "FW Upload tce invalid!");
10855 }
10856 req25->ImageOffset = tcsge->ImageOffset;
10857 req25->ImageSize = tcsge->ImageSize;
10858
10859 pt->sgl_offset = offsetof(MPI25_FW_UPLOAD_REQUEST, SGL);
10860 if (pt->request_size != pt->sgl_offset) {
10861 NDBG15(("mpi_pre_fw_25_upload(): Incorrect req size, "
10862 "0x%x, should be 0x%x, dataoutsz 0x%x",
10863 pt->request_size, pt->sgl_offset,
10864 pt->dataout_size));
10865 }
10866 if (pt->data_size < sizeof (MPI2_FW_UPLOAD_REPLY)) {
10867 NDBG15(("mpi_pre_fw_25_upload(): Incorrect rep size, "
10868 "0x%x, should be 0x%x", pt->data_size,
10869 (int)sizeof (MPI2_FW_UPLOAD_REPLY)));
10870 }
10871 }
10872
10873 /*
10874 * Prepare the pt for an IOC_FACTS request.
10875 */
10876 static void
mpi_pre_ioc_facts(mptsas_t * mpt,mptsas_pt_request_t * pt)10877 mpi_pre_ioc_facts(mptsas_t *mpt, mptsas_pt_request_t *pt)
10878 {
10879 #ifndef __lock_lint
10880 _NOTE(ARGUNUSED(mpt))
10881 #endif
10882 if (pt->request_size != sizeof (MPI2_IOC_FACTS_REQUEST)) {
10883 NDBG15(("mpi_pre_ioc_facts(): Incorrect req size, "
10884 "0x%x, should be 0x%x, dataoutsz 0x%x",
10885 pt->request_size,
10886 (int)sizeof (MPI2_IOC_FACTS_REQUEST),
10887 pt->dataout_size));
10888 }
10889 if (pt->data_size != sizeof (MPI2_IOC_FACTS_REPLY)) {
10890 NDBG15(("mpi_pre_ioc_facts(): Incorrect rep size, "
10891 "0x%x, should be 0x%x", pt->data_size,
10892 (int)sizeof (MPI2_IOC_FACTS_REPLY)));
10893 }
10894 pt->sgl_offset = (uint16_t)pt->request_size;
10895 }
10896
10897 /*
10898 * Prepare the pt for a PORT_FACTS request.
10899 */
10900 static void
mpi_pre_port_facts(mptsas_t * mpt,mptsas_pt_request_t * pt)10901 mpi_pre_port_facts(mptsas_t *mpt, mptsas_pt_request_t *pt)
10902 {
10903 #ifndef __lock_lint
10904 _NOTE(ARGUNUSED(mpt))
10905 #endif
10906 if (pt->request_size != sizeof (MPI2_PORT_FACTS_REQUEST)) {
10907 NDBG15(("mpi_pre_port_facts(): Incorrect req size, "
10908 "0x%x, should be 0x%x, dataoutsz 0x%x",
10909 pt->request_size,
10910 (int)sizeof (MPI2_PORT_FACTS_REQUEST),
10911 pt->dataout_size));
10912 }
10913 if (pt->data_size != sizeof (MPI2_PORT_FACTS_REPLY)) {
10914 NDBG15(("mpi_pre_port_facts(): Incorrect rep size, "
10915 "0x%x, should be 0x%x", pt->data_size,
10916 (int)sizeof (MPI2_PORT_FACTS_REPLY)));
10917 }
10918 pt->sgl_offset = (uint16_t)pt->request_size;
10919 }
10920
10921 /*
10922 * Prepare pt for a SATA_PASSTHROUGH request.
10923 */
10924 static void
mpi_pre_sata_passthrough(mptsas_t * mpt,mptsas_pt_request_t * pt)10925 mpi_pre_sata_passthrough(mptsas_t *mpt, mptsas_pt_request_t *pt)
10926 {
10927 #ifndef __lock_lint
10928 _NOTE(ARGUNUSED(mpt))
10929 #endif
10930 pt->sgl_offset = offsetof(MPI2_SATA_PASSTHROUGH_REQUEST, SGL);
10931 if (pt->request_size != pt->sgl_offset) {
10932 NDBG15(("mpi_pre_sata_passthrough(): Incorrect req size, "
10933 "0x%x, should be 0x%x, dataoutsz 0x%x",
10934 pt->request_size, pt->sgl_offset,
10935 pt->dataout_size));
10936 }
10937 if (pt->data_size != sizeof (MPI2_SATA_PASSTHROUGH_REPLY)) {
10938 NDBG15(("mpi_pre_sata_passthrough(): Incorrect rep size, "
10939 "0x%x, should be 0x%x", pt->data_size,
10940 (int)sizeof (MPI2_SATA_PASSTHROUGH_REPLY)));
10941 }
10942 }
10943
10944 static void
mpi_pre_smp_passthrough(mptsas_t * mpt,mptsas_pt_request_t * pt)10945 mpi_pre_smp_passthrough(mptsas_t *mpt, mptsas_pt_request_t *pt)
10946 {
10947 #ifndef __lock_lint
10948 _NOTE(ARGUNUSED(mpt))
10949 #endif
10950 pt->sgl_offset = offsetof(MPI2_SMP_PASSTHROUGH_REQUEST, SGL);
10951 if (pt->request_size != pt->sgl_offset) {
10952 NDBG15(("mpi_pre_smp_passthrough(): Incorrect req size, "
10953 "0x%x, should be 0x%x, dataoutsz 0x%x",
10954 pt->request_size, pt->sgl_offset,
10955 pt->dataout_size));
10956 }
10957 if (pt->data_size != sizeof (MPI2_SMP_PASSTHROUGH_REPLY)) {
10958 NDBG15(("mpi_pre_smp_passthrough(): Incorrect rep size, "
10959 "0x%x, should be 0x%x", pt->data_size,
10960 (int)sizeof (MPI2_SMP_PASSTHROUGH_REPLY)));
10961 }
10962 }
10963
10964 /*
10965 * Prepare pt for a CONFIG request.
10966 */
10967 static void
mpi_pre_config(mptsas_t * mpt,mptsas_pt_request_t * pt)10968 mpi_pre_config(mptsas_t *mpt, mptsas_pt_request_t *pt)
10969 {
10970 #ifndef __lock_lint
10971 _NOTE(ARGUNUSED(mpt))
10972 #endif
10973 pt->sgl_offset = offsetof(MPI2_CONFIG_REQUEST, PageBufferSGE);
10974 if (pt->request_size != pt->sgl_offset) {
10975 NDBG15(("mpi_pre_config(): Incorrect req size, 0x%x, "
10976 "should be 0x%x, dataoutsz 0x%x", pt->request_size,
10977 pt->sgl_offset, pt->dataout_size));
10978 }
10979 if (pt->data_size != sizeof (MPI2_CONFIG_REPLY)) {
10980 NDBG15(("mpi_pre_config(): Incorrect rep size, 0x%x, "
10981 "should be 0x%x", pt->data_size,
10982 (int)sizeof (MPI2_CONFIG_REPLY)));
10983 }
10984 pt->simple = 1;
10985 }
10986
10987 /*
10988 * Prepare pt for a SCSI_IO_REQ request.
10989 */
10990 static void
mpi_pre_scsi_io_req(mptsas_t * mpt,mptsas_pt_request_t * pt)10991 mpi_pre_scsi_io_req(mptsas_t *mpt, mptsas_pt_request_t *pt)
10992 {
10993 #ifndef __lock_lint
10994 _NOTE(ARGUNUSED(mpt))
10995 #endif
10996 pt->sgl_offset = offsetof(MPI2_SCSI_IO_REQUEST, SGL);
10997 if (pt->request_size != pt->sgl_offset) {
10998 NDBG15(("mpi_pre_config(): Incorrect req size, 0x%x, "
10999 "should be 0x%x, dataoutsz 0x%x", pt->request_size,
11000 pt->sgl_offset,
11001 pt->dataout_size));
11002 }
11003 if (pt->data_size != sizeof (MPI2_SCSI_IO_REPLY)) {
11004 NDBG15(("mpi_pre_config(): Incorrect rep size, 0x%x, "
11005 "should be 0x%x", pt->data_size,
11006 (int)sizeof (MPI2_SCSI_IO_REPLY)));
11007 }
11008 }
11009
11010 /*
11011 * Prepare the mptsas_cmd for a SAS_IO_UNIT_CONTROL request.
11012 */
11013 static void
mpi_pre_sas_io_unit_control(mptsas_t * mpt,mptsas_pt_request_t * pt)11014 mpi_pre_sas_io_unit_control(mptsas_t *mpt, mptsas_pt_request_t *pt)
11015 {
11016 #ifndef __lock_lint
11017 _NOTE(ARGUNUSED(mpt))
11018 #endif
11019 pt->sgl_offset = (uint16_t)pt->request_size;
11020 }
11021
11022 /*
11023 * A set of functions to prepare an mptsas_cmd for the various
11024 * supported requests.
11025 */
11026 static struct mptsas_func {
11027 U8 Function;
11028 char *Name;
11029 mptsas_pre_f *f_pre;
11030 } mptsas_func_list[] = {
11031 { MPI2_FUNCTION_IOC_FACTS, "IOC_FACTS", mpi_pre_ioc_facts },
11032 { MPI2_FUNCTION_PORT_FACTS, "PORT_FACTS", mpi_pre_port_facts },
11033 { MPI2_FUNCTION_FW_DOWNLOAD, "FW_DOWNLOAD", mpi_pre_fw_download },
11034 { MPI2_FUNCTION_FW_UPLOAD, "FW_UPLOAD", mpi_pre_fw_upload },
11035 { MPI2_FUNCTION_SATA_PASSTHROUGH, "SATA_PASSTHROUGH",
11036 mpi_pre_sata_passthrough },
11037 { MPI2_FUNCTION_SMP_PASSTHROUGH, "SMP_PASSTHROUGH",
11038 mpi_pre_smp_passthrough},
11039 { MPI2_FUNCTION_SCSI_IO_REQUEST, "SCSI_IO_REQUEST",
11040 mpi_pre_scsi_io_req},
11041 { MPI2_FUNCTION_CONFIG, "CONFIG", mpi_pre_config},
11042 { MPI2_FUNCTION_SAS_IO_UNIT_CONTROL, "SAS_IO_UNIT_CONTROL",
11043 mpi_pre_sas_io_unit_control },
11044 { 0xFF, NULL, NULL } /* list end */
11045 };
11046
11047 static void
mptsas_prep_sgl_offset(mptsas_t * mpt,mptsas_pt_request_t * pt)11048 mptsas_prep_sgl_offset(mptsas_t *mpt, mptsas_pt_request_t *pt)
11049 {
11050 pMPI2RequestHeader_t hdr;
11051 struct mptsas_func *f;
11052
11053 hdr = (pMPI2RequestHeader_t)pt->request;
11054
11055 for (f = mptsas_func_list; f->f_pre != NULL; f++) {
11056 if (hdr->Function == f->Function) {
11057 f->f_pre(mpt, pt);
11058 NDBG15(("mptsas_prep_sgl_offset: Function %s,"
11059 " sgl_offset 0x%x", f->Name,
11060 pt->sgl_offset));
11061 return;
11062 }
11063 }
11064 NDBG15(("mptsas_prep_sgl_offset: Unknown Function 0x%02x,"
11065 " returning req_size 0x%x for sgl_offset",
11066 hdr->Function, pt->request_size));
11067 pt->sgl_offset = (uint16_t)pt->request_size;
11068 }
11069
11070
11071 static int
mptsas_do_passthru(mptsas_t * mpt,uint8_t * request,uint8_t * reply,uint8_t * data,uint32_t request_size,uint32_t reply_size,uint32_t data_size,uint32_t direction,uint8_t * dataout,uint32_t dataout_size,short timeout,int mode)11072 mptsas_do_passthru(mptsas_t *mpt, uint8_t *request, uint8_t *reply,
11073 uint8_t *data, uint32_t request_size, uint32_t reply_size,
11074 uint32_t data_size, uint32_t direction, uint8_t *dataout,
11075 uint32_t dataout_size, short timeout, int mode)
11076 {
11077 mptsas_pt_request_t pt;
11078 mptsas_dma_alloc_state_t data_dma_state;
11079 mptsas_dma_alloc_state_t dataout_dma_state;
11080 caddr_t memp;
11081 mptsas_cmd_t *cmd = NULL;
11082 struct scsi_pkt *pkt;
11083 uint32_t reply_len = 0, sense_len = 0;
11084 pMPI2RequestHeader_t request_hdrp;
11085 pMPI2RequestHeader_t request_msg;
11086 pMPI2DefaultReply_t reply_msg;
11087 Mpi2SCSIIOReply_t rep_msg;
11088 int rvalue;
11089 int i, status = 0, pt_flags = 0, rv = 0;
11090 uint8_t function;
11091
11092 ASSERT(mutex_owned(&mpt->m_mutex));
11093
11094 reply_msg = (pMPI2DefaultReply_t)(&rep_msg);
11095 bzero(reply_msg, sizeof (MPI2_DEFAULT_REPLY));
11096 request_msg = kmem_zalloc(request_size, KM_SLEEP);
11097
11098 mutex_exit(&mpt->m_mutex);
11099 /*
11100 * copy in the request buffer since it could be used by
11101 * another thread when the pt request into waitq
11102 */
11103 if (ddi_copyin(request, request_msg, request_size, mode)) {
11104 mutex_enter(&mpt->m_mutex);
11105 status = EFAULT;
11106 mptsas_log(mpt, CE_WARN, "failed to copy request data");
11107 goto out;
11108 }
11109 NDBG27(("mptsas_do_passthru: mode 0x%x, size 0x%x, Func 0x%x",
11110 mode, request_size, request_msg->Function));
11111 mutex_enter(&mpt->m_mutex);
11112
11113 function = request_msg->Function;
11114 if (function == MPI2_FUNCTION_SCSI_TASK_MGMT) {
11115 pMpi2SCSITaskManagementRequest_t task;
11116 task = (pMpi2SCSITaskManagementRequest_t)request_msg;
11117 mptsas_setup_bus_reset_delay(mpt);
11118 rv = mptsas_ioc_task_management(mpt, task->TaskType,
11119 task->DevHandle, (int)task->LUN[1], reply, reply_size,
11120 mode);
11121
11122 if (rv != TRUE) {
11123 status = EIO;
11124 mptsas_log(mpt, CE_WARN, "task management failed");
11125 }
11126 goto out;
11127 }
11128
11129 if (data_size != 0) {
11130 data_dma_state.size = data_size;
11131 if (mptsas_dma_alloc(mpt, &data_dma_state) != DDI_SUCCESS) {
11132 status = ENOMEM;
11133 mptsas_log(mpt, CE_WARN, "failed to alloc DMA "
11134 "resource");
11135 goto out;
11136 }
11137 pt_flags |= MPTSAS_DATA_ALLOCATED;
11138 if (direction == MPTSAS_PASS_THRU_DIRECTION_WRITE) {
11139 mutex_exit(&mpt->m_mutex);
11140 for (i = 0; i < data_size; i++) {
11141 if (ddi_copyin(data + i, (uint8_t *)
11142 data_dma_state.memp + i, 1, mode)) {
11143 mutex_enter(&mpt->m_mutex);
11144 status = EFAULT;
11145 mptsas_log(mpt, CE_WARN, "failed to "
11146 "copy read data");
11147 goto out;
11148 }
11149 }
11150 mutex_enter(&mpt->m_mutex);
11151 }
11152 } else {
11153 bzero(&data_dma_state, sizeof (data_dma_state));
11154 }
11155
11156 if (dataout_size != 0) {
11157 dataout_dma_state.size = dataout_size;
11158 if (mptsas_dma_alloc(mpt, &dataout_dma_state) != DDI_SUCCESS) {
11159 status = ENOMEM;
11160 mptsas_log(mpt, CE_WARN, "failed to alloc DMA "
11161 "resource");
11162 goto out;
11163 }
11164 pt_flags |= MPTSAS_DATAOUT_ALLOCATED;
11165 mutex_exit(&mpt->m_mutex);
11166 for (i = 0; i < dataout_size; i++) {
11167 if (ddi_copyin(dataout + i, (uint8_t *)
11168 dataout_dma_state.memp + i, 1, mode)) {
11169 mutex_enter(&mpt->m_mutex);
11170 mptsas_log(mpt, CE_WARN, "failed to copy out"
11171 " data");
11172 status = EFAULT;
11173 goto out;
11174 }
11175 }
11176 mutex_enter(&mpt->m_mutex);
11177 } else {
11178 bzero(&dataout_dma_state, sizeof (dataout_dma_state));
11179 }
11180
11181 if ((rvalue = (mptsas_request_from_pool(mpt, &cmd, &pkt))) == -1) {
11182 status = EAGAIN;
11183 mptsas_log(mpt, CE_NOTE, "event ack command pool is full");
11184 goto out;
11185 }
11186 pt_flags |= MPTSAS_REQUEST_POOL_CMD;
11187
11188 bzero((caddr_t)cmd, sizeof (*cmd));
11189 bzero((caddr_t)pkt, scsi_pkt_size());
11190 bzero((caddr_t)&pt, sizeof (pt));
11191
11192 cmd->ioc_cmd_slot = (uint32_t)(rvalue);
11193
11194 pt.request = (uint8_t *)request_msg;
11195 pt.direction = direction;
11196 pt.simple = 0;
11197 pt.request_size = request_size;
11198 pt.data_size = data_size;
11199 pt.dataout_size = dataout_size;
11200 pt.data_cookie = data_dma_state.cookie;
11201 pt.dataout_cookie = dataout_dma_state.cookie;
11202 mptsas_prep_sgl_offset(mpt, &pt);
11203
11204 /*
11205 * Form a blank cmd/pkt to store the acknowledgement message
11206 */
11207 pkt->pkt_cdbp = (opaque_t)&cmd->cmd_cdb[0];
11208 pkt->pkt_scbp = (opaque_t)&cmd->cmd_scb;
11209 pkt->pkt_ha_private = (opaque_t)&pt;
11210 pkt->pkt_flags = FLAG_HEAD;
11211 pkt->pkt_time = timeout;
11212 cmd->cmd_pkt = pkt;
11213 cmd->cmd_flags = CFLAG_CMDIOC | CFLAG_PASSTHRU;
11214
11215 if ((function == MPI2_FUNCTION_SCSI_IO_REQUEST) ||
11216 (function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH)) {
11217 uint8_t com, cdb_group_id;
11218 boolean_t ret;
11219
11220 pkt->pkt_cdbp = ((pMpi2SCSIIORequest_t)request_msg)->CDB.CDB32;
11221 com = pkt->pkt_cdbp[0];
11222 cdb_group_id = CDB_GROUPID(com);
11223 switch (cdb_group_id) {
11224 case CDB_GROUPID_0: cmd->cmd_cdblen = CDB_GROUP0; break;
11225 case CDB_GROUPID_1: cmd->cmd_cdblen = CDB_GROUP1; break;
11226 case CDB_GROUPID_2: cmd->cmd_cdblen = CDB_GROUP2; break;
11227 case CDB_GROUPID_4: cmd->cmd_cdblen = CDB_GROUP4; break;
11228 case CDB_GROUPID_5: cmd->cmd_cdblen = CDB_GROUP5; break;
11229 default:
11230 NDBG27(("mptsas_do_passthru: SCSI_IO, reserved "
11231 "CDBGROUP 0x%x requested!", cdb_group_id));
11232 break;
11233 }
11234
11235 reply_len = sizeof (MPI2_SCSI_IO_REPLY);
11236 sense_len = reply_size - reply_len;
11237 ret = mptsas_cmdarqsize(mpt, cmd, sense_len, KM_SLEEP);
11238 VERIFY(ret == B_TRUE);
11239 } else {
11240 reply_len = reply_size;
11241 sense_len = 0;
11242 }
11243
11244 NDBG27(("mptsas_do_passthru: %s, dsz 0x%x, dosz 0x%x, replen 0x%x, "
11245 "snslen 0x%x",
11246 (direction == MPTSAS_PASS_THRU_DIRECTION_WRITE)?"Write":"Read",
11247 data_size, dataout_size, reply_len, sense_len));
11248
11249 /*
11250 * Save the command in a slot
11251 */
11252 if (mptsas_save_cmd(mpt, cmd) == TRUE) {
11253 /*
11254 * Once passthru command get slot, set cmd_flags
11255 * CFLAG_PREPARED.
11256 */
11257 cmd->cmd_flags |= CFLAG_PREPARED;
11258 mptsas_start_passthru(mpt, cmd);
11259 } else {
11260 mptsas_waitq_add(mpt, cmd);
11261 }
11262
11263 while ((cmd->cmd_flags & CFLAG_FINISHED) == 0) {
11264 cv_wait(&mpt->m_passthru_cv, &mpt->m_mutex);
11265 }
11266
11267 NDBG27(("mptsas_do_passthru: Cmd complete, flags 0x%x, rfm 0x%x "
11268 "pktreason 0x%x", cmd->cmd_flags, cmd->cmd_rfm,
11269 pkt->pkt_reason));
11270
11271 if (cmd->cmd_flags & CFLAG_PREPARED) {
11272 memp = mpt->m_req_frame + (mpt->m_req_frame_size *
11273 cmd->cmd_slot);
11274 request_hdrp = (pMPI2RequestHeader_t)memp;
11275 }
11276
11277 if (cmd->cmd_flags & CFLAG_TIMEOUT) {
11278 status = ETIMEDOUT;
11279 mptsas_log(mpt, CE_WARN, "passthrough command timeout");
11280 pt_flags |= MPTSAS_CMD_TIMEOUT;
11281 goto out;
11282 }
11283
11284 if (cmd->cmd_rfm) {
11285 /*
11286 * cmd_rfm is zero means the command reply is a CONTEXT
11287 * reply and no PCI Write to post the free reply SMFA
11288 * because no reply message frame is used.
11289 * cmd_rfm is non-zero means the reply is a ADDRESS
11290 * reply and reply message frame is used.
11291 */
11292 pt_flags |= MPTSAS_ADDRESS_REPLY;
11293 (void) ddi_dma_sync(mpt->m_dma_reply_frame_hdl, 0, 0,
11294 DDI_DMA_SYNC_FORCPU);
11295 reply_msg = (pMPI2DefaultReply_t)
11296 (mpt->m_reply_frame + (cmd->cmd_rfm -
11297 (mpt->m_reply_frame_dma_addr & 0xffffffffu)));
11298 }
11299
11300 mptsas_fma_check(mpt, cmd);
11301 if (pkt->pkt_reason == CMD_TRAN_ERR) {
11302 status = EAGAIN;
11303 mptsas_log(mpt, CE_WARN, "passthru fma error");
11304 goto out;
11305 }
11306 if (pkt->pkt_reason == CMD_RESET) {
11307 status = EAGAIN;
11308 mptsas_log(mpt, CE_WARN, "ioc reset abort passthru");
11309 goto out;
11310 }
11311
11312 if (pkt->pkt_reason == CMD_INCOMPLETE) {
11313 status = EIO;
11314 mptsas_log(mpt, CE_WARN, "passthrough command incomplete");
11315 goto out;
11316 }
11317
11318 mutex_exit(&mpt->m_mutex);
11319 if (cmd->cmd_flags & CFLAG_PREPARED) {
11320 function = request_hdrp->Function;
11321 if ((function == MPI2_FUNCTION_SCSI_IO_REQUEST) ||
11322 (function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH)) {
11323 reply_len = sizeof (MPI2_SCSI_IO_REPLY);
11324 sense_len = cmd->cmd_extrqslen ?
11325 min(sense_len, cmd->cmd_extrqslen) :
11326 min(sense_len, cmd->cmd_rqslen);
11327 } else {
11328 reply_len = reply_size;
11329 sense_len = 0;
11330 }
11331
11332 for (i = 0; i < reply_len; i++) {
11333 if (ddi_copyout((uint8_t *)reply_msg + i, reply + i, 1,
11334 mode)) {
11335 mutex_enter(&mpt->m_mutex);
11336 status = EFAULT;
11337 mptsas_log(mpt, CE_WARN, "failed to copy out "
11338 "reply data");
11339 goto out;
11340 }
11341 }
11342 for (i = 0; i < sense_len; i++) {
11343 if (ddi_copyout((uint8_t *)request_hdrp + 64 + i,
11344 reply + reply_len + i, 1, mode)) {
11345 mutex_enter(&mpt->m_mutex);
11346 status = EFAULT;
11347 mptsas_log(mpt, CE_WARN, "failed to copy out "
11348 "sense data");
11349 goto out;
11350 }
11351 }
11352 }
11353
11354 if (data_size) {
11355 if (direction != MPTSAS_PASS_THRU_DIRECTION_WRITE) {
11356 (void) ddi_dma_sync(data_dma_state.handle, 0, 0,
11357 DDI_DMA_SYNC_FORCPU);
11358 for (i = 0; i < data_size; i++) {
11359 if (ddi_copyout((uint8_t *)(
11360 data_dma_state.memp + i), data + i, 1,
11361 mode)) {
11362 mutex_enter(&mpt->m_mutex);
11363 status = EFAULT;
11364 mptsas_log(mpt, CE_WARN, "failed to "
11365 "copy out the reply data");
11366 goto out;
11367 }
11368 }
11369 }
11370 }
11371 mutex_enter(&mpt->m_mutex);
11372 out:
11373 /*
11374 * Put the reply frame back on the free queue, increment the free
11375 * index, and write the new index to the free index register. But only
11376 * if this reply is an ADDRESS reply.
11377 */
11378 if (pt_flags & MPTSAS_ADDRESS_REPLY) {
11379 ddi_put32(mpt->m_acc_free_queue_hdl,
11380 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index],
11381 cmd->cmd_rfm);
11382 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0,
11383 DDI_DMA_SYNC_FORDEV);
11384 if (++mpt->m_free_index == mpt->m_free_queue_depth) {
11385 mpt->m_free_index = 0;
11386 }
11387 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex,
11388 mpt->m_free_index);
11389 }
11390 if (cmd) {
11391 if (cmd->cmd_extrqslen != 0) {
11392 rmfree(mpt->m_erqsense_map, cmd->cmd_extrqschunks,
11393 cmd->cmd_extrqsidx + 1);
11394 }
11395 if (cmd->cmd_flags & CFLAG_PREPARED) {
11396 mptsas_remove_cmd(mpt, cmd);
11397 pt_flags &= (~MPTSAS_REQUEST_POOL_CMD);
11398 }
11399 }
11400 if (pt_flags & MPTSAS_REQUEST_POOL_CMD)
11401 mptsas_return_to_pool(mpt, cmd);
11402 if (pt_flags & MPTSAS_DATA_ALLOCATED) {
11403 if (mptsas_check_dma_handle(data_dma_state.handle) !=
11404 DDI_SUCCESS) {
11405 ddi_fm_service_impact(mpt->m_dip,
11406 DDI_SERVICE_UNAFFECTED);
11407 status = EFAULT;
11408 }
11409 mptsas_dma_free(&data_dma_state);
11410 }
11411 if (pt_flags & MPTSAS_DATAOUT_ALLOCATED) {
11412 if (mptsas_check_dma_handle(dataout_dma_state.handle) !=
11413 DDI_SUCCESS) {
11414 ddi_fm_service_impact(mpt->m_dip,
11415 DDI_SERVICE_UNAFFECTED);
11416 status = EFAULT;
11417 }
11418 mptsas_dma_free(&dataout_dma_state);
11419 }
11420 if (pt_flags & MPTSAS_CMD_TIMEOUT) {
11421 if ((mptsas_restart_ioc(mpt)) == DDI_FAILURE) {
11422 mptsas_log(mpt, CE_WARN, "mptsas_restart_ioc failed");
11423 }
11424 }
11425 if (request_msg)
11426 kmem_free(request_msg, request_size);
11427 NDBG27(("mptsas_do_passthru: Done status 0x%x", status));
11428
11429 return (status);
11430 }
11431
11432 static int
mptsas_pass_thru(mptsas_t * mpt,mptsas_pass_thru_t * data,int mode)11433 mptsas_pass_thru(mptsas_t *mpt, mptsas_pass_thru_t *data, int mode)
11434 {
11435 /*
11436 * If timeout is 0, set timeout to default of 60 seconds.
11437 */
11438 if (data->Timeout == 0) {
11439 data->Timeout = MPTSAS_PASS_THRU_TIME_DEFAULT;
11440 }
11441
11442 if (((data->DataSize == 0) &&
11443 (data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_NONE)) ||
11444 ((data->DataSize != 0) &&
11445 ((data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_READ) ||
11446 (data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_WRITE) ||
11447 ((data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_BOTH) &&
11448 (data->DataOutSize != 0))))) {
11449 if (data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_BOTH) {
11450 data->DataDirection = MPTSAS_PASS_THRU_DIRECTION_READ;
11451 } else {
11452 data->DataOutSize = 0;
11453 }
11454 /*
11455 * Send passthru request messages
11456 */
11457 return (mptsas_do_passthru(mpt,
11458 (uint8_t *)((uintptr_t)data->PtrRequest),
11459 (uint8_t *)((uintptr_t)data->PtrReply),
11460 (uint8_t *)((uintptr_t)data->PtrData),
11461 data->RequestSize, data->ReplySize,
11462 data->DataSize, data->DataDirection,
11463 (uint8_t *)((uintptr_t)data->PtrDataOut),
11464 data->DataOutSize, data->Timeout, mode));
11465 } else {
11466 return (EINVAL);
11467 }
11468 }
11469
11470 static uint8_t
mptsas_get_fw_diag_buffer_number(mptsas_t * mpt,uint32_t unique_id)11471 mptsas_get_fw_diag_buffer_number(mptsas_t *mpt, uint32_t unique_id)
11472 {
11473 uint8_t index;
11474
11475 for (index = 0; index < MPI2_DIAG_BUF_TYPE_COUNT; index++) {
11476 if (mpt->m_fw_diag_buffer_list[index].unique_id == unique_id) {
11477 return (index);
11478 }
11479 }
11480
11481 return (MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND);
11482 }
11483
11484 static void
mptsas_start_diag(mptsas_t * mpt,mptsas_cmd_t * cmd)11485 mptsas_start_diag(mptsas_t *mpt, mptsas_cmd_t *cmd)
11486 {
11487 pMpi2DiagBufferPostRequest_t pDiag_post_msg;
11488 pMpi2DiagReleaseRequest_t pDiag_release_msg;
11489 struct scsi_pkt *pkt = cmd->cmd_pkt;
11490 mptsas_diag_request_t *diag = pkt->pkt_ha_private;
11491 uint32_t i;
11492 uint64_t request_desc;
11493
11494 ASSERT(mutex_owned(&mpt->m_mutex));
11495
11496 /*
11497 * Form the diag message depending on the post or release function.
11498 */
11499 if (diag->function == MPI2_FUNCTION_DIAG_BUFFER_POST) {
11500 pDiag_post_msg = (pMpi2DiagBufferPostRequest_t)
11501 (mpt->m_req_frame + (mpt->m_req_frame_size *
11502 cmd->cmd_slot));
11503 bzero(pDiag_post_msg, mpt->m_req_frame_size);
11504 ddi_put8(mpt->m_acc_req_frame_hdl, &pDiag_post_msg->Function,
11505 diag->function);
11506 ddi_put8(mpt->m_acc_req_frame_hdl, &pDiag_post_msg->BufferType,
11507 diag->pBuffer->buffer_type);
11508 ddi_put8(mpt->m_acc_req_frame_hdl,
11509 &pDiag_post_msg->ExtendedType,
11510 diag->pBuffer->extended_type);
11511 ddi_put32(mpt->m_acc_req_frame_hdl,
11512 &pDiag_post_msg->BufferLength,
11513 diag->pBuffer->buffer_data.size);
11514 for (i = 0; i < (sizeof (pDiag_post_msg->ProductSpecific) / 4);
11515 i++) {
11516 ddi_put32(mpt->m_acc_req_frame_hdl,
11517 &pDiag_post_msg->ProductSpecific[i],
11518 diag->pBuffer->product_specific[i]);
11519 }
11520 ddi_put32(mpt->m_acc_req_frame_hdl,
11521 &pDiag_post_msg->BufferAddress.Low,
11522 (uint32_t)(diag->pBuffer->buffer_data.cookie.dmac_laddress
11523 & 0xffffffffull));
11524 ddi_put32(mpt->m_acc_req_frame_hdl,
11525 &pDiag_post_msg->BufferAddress.High,
11526 (uint32_t)(diag->pBuffer->buffer_data.cookie.dmac_laddress
11527 >> 32));
11528 } else {
11529 pDiag_release_msg = (pMpi2DiagReleaseRequest_t)
11530 (mpt->m_req_frame + (mpt->m_req_frame_size *
11531 cmd->cmd_slot));
11532 bzero(pDiag_release_msg, mpt->m_req_frame_size);
11533 ddi_put8(mpt->m_acc_req_frame_hdl,
11534 &pDiag_release_msg->Function, diag->function);
11535 ddi_put8(mpt->m_acc_req_frame_hdl,
11536 &pDiag_release_msg->BufferType,
11537 diag->pBuffer->buffer_type);
11538 }
11539
11540 /*
11541 * Send the message
11542 */
11543 (void) ddi_dma_sync(mpt->m_dma_req_frame_hdl, 0, 0,
11544 DDI_DMA_SYNC_FORDEV);
11545 request_desc = (cmd->cmd_slot << 16) +
11546 MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE;
11547 cmd->cmd_rfm = 0;
11548 MPTSAS_START_CMD(mpt, request_desc);
11549 if ((mptsas_check_dma_handle(mpt->m_dma_req_frame_hdl) !=
11550 DDI_SUCCESS) ||
11551 (mptsas_check_acc_handle(mpt->m_acc_req_frame_hdl) !=
11552 DDI_SUCCESS)) {
11553 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
11554 }
11555 }
11556
11557 static int
mptsas_post_fw_diag_buffer(mptsas_t * mpt,mptsas_fw_diagnostic_buffer_t * pBuffer,uint32_t * return_code)11558 mptsas_post_fw_diag_buffer(mptsas_t *mpt,
11559 mptsas_fw_diagnostic_buffer_t *pBuffer, uint32_t *return_code)
11560 {
11561 mptsas_diag_request_t diag;
11562 int status, slot_num, post_flags = 0;
11563 mptsas_cmd_t *cmd = NULL;
11564 struct scsi_pkt *pkt;
11565 pMpi2DiagBufferPostReply_t reply;
11566 uint16_t iocstatus;
11567 uint32_t iocloginfo, transfer_length;
11568
11569 /*
11570 * If buffer is not enabled, just leave.
11571 */
11572 *return_code = MPTSAS_FW_DIAG_ERROR_POST_FAILED;
11573 if (!pBuffer->enabled) {
11574 status = DDI_FAILURE;
11575 goto out;
11576 }
11577
11578 /*
11579 * Clear some flags initially.
11580 */
11581 pBuffer->force_release = FALSE;
11582 pBuffer->valid_data = FALSE;
11583 pBuffer->owned_by_firmware = FALSE;
11584
11585 /*
11586 * Get a cmd buffer from the cmd buffer pool
11587 */
11588 if ((slot_num = (mptsas_request_from_pool(mpt, &cmd, &pkt))) == -1) {
11589 status = DDI_FAILURE;
11590 mptsas_log(mpt, CE_NOTE, "command pool is full: Post FW Diag");
11591 goto out;
11592 }
11593 post_flags |= MPTSAS_REQUEST_POOL_CMD;
11594
11595 bzero((caddr_t)cmd, sizeof (*cmd));
11596 bzero((caddr_t)pkt, scsi_pkt_size());
11597
11598 cmd->ioc_cmd_slot = (uint32_t)(slot_num);
11599
11600 diag.pBuffer = pBuffer;
11601 diag.function = MPI2_FUNCTION_DIAG_BUFFER_POST;
11602
11603 /*
11604 * Form a blank cmd/pkt to store the acknowledgement message
11605 */
11606 pkt->pkt_ha_private = (opaque_t)&diag;
11607 pkt->pkt_flags = FLAG_HEAD;
11608 pkt->pkt_time = 60;
11609 cmd->cmd_pkt = pkt;
11610 cmd->cmd_flags = CFLAG_CMDIOC | CFLAG_FW_DIAG;
11611
11612 /*
11613 * Save the command in a slot
11614 */
11615 if (mptsas_save_cmd(mpt, cmd) == TRUE) {
11616 /*
11617 * Once passthru command get slot, set cmd_flags
11618 * CFLAG_PREPARED.
11619 */
11620 cmd->cmd_flags |= CFLAG_PREPARED;
11621 mptsas_start_diag(mpt, cmd);
11622 } else {
11623 mptsas_waitq_add(mpt, cmd);
11624 }
11625
11626 while ((cmd->cmd_flags & CFLAG_FINISHED) == 0) {
11627 cv_wait(&mpt->m_fw_diag_cv, &mpt->m_mutex);
11628 }
11629
11630 if (cmd->cmd_flags & CFLAG_TIMEOUT) {
11631 status = DDI_FAILURE;
11632 mptsas_log(mpt, CE_WARN, "Post FW Diag command timeout");
11633 goto out;
11634 }
11635
11636 /*
11637 * cmd_rfm points to the reply message if a reply was given. Check the
11638 * IOCStatus to make sure everything went OK with the FW diag request
11639 * and set buffer flags.
11640 */
11641 if (cmd->cmd_rfm) {
11642 post_flags |= MPTSAS_ADDRESS_REPLY;
11643 (void) ddi_dma_sync(mpt->m_dma_reply_frame_hdl, 0, 0,
11644 DDI_DMA_SYNC_FORCPU);
11645 reply = (pMpi2DiagBufferPostReply_t)(mpt->m_reply_frame +
11646 (cmd->cmd_rfm -
11647 (mpt->m_reply_frame_dma_addr & 0xffffffffu)));
11648
11649 /*
11650 * Get the reply message data
11651 */
11652 iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl,
11653 &reply->IOCStatus);
11654 iocloginfo = ddi_get32(mpt->m_acc_reply_frame_hdl,
11655 &reply->IOCLogInfo);
11656 transfer_length = ddi_get32(mpt->m_acc_reply_frame_hdl,
11657 &reply->TransferLength);
11658
11659 /*
11660 * If post failed quit.
11661 */
11662 if (iocstatus != MPI2_IOCSTATUS_SUCCESS) {
11663 status = DDI_FAILURE;
11664 NDBG13(("post FW Diag Buffer failed: IOCStatus=0x%x, "
11665 "IOCLogInfo=0x%x, TransferLength=0x%x", iocstatus,
11666 iocloginfo, transfer_length));
11667 goto out;
11668 }
11669
11670 /*
11671 * Post was successful.
11672 */
11673 pBuffer->valid_data = TRUE;
11674 pBuffer->owned_by_firmware = TRUE;
11675 *return_code = MPTSAS_FW_DIAG_ERROR_SUCCESS;
11676 status = DDI_SUCCESS;
11677 }
11678
11679 out:
11680 /*
11681 * Put the reply frame back on the free queue, increment the free
11682 * index, and write the new index to the free index register. But only
11683 * if this reply is an ADDRESS reply.
11684 */
11685 if (post_flags & MPTSAS_ADDRESS_REPLY) {
11686 ddi_put32(mpt->m_acc_free_queue_hdl,
11687 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index],
11688 cmd->cmd_rfm);
11689 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0,
11690 DDI_DMA_SYNC_FORDEV);
11691 if (++mpt->m_free_index == mpt->m_free_queue_depth) {
11692 mpt->m_free_index = 0;
11693 }
11694 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex,
11695 mpt->m_free_index);
11696 }
11697 if (cmd && (cmd->cmd_flags & CFLAG_PREPARED)) {
11698 mptsas_remove_cmd(mpt, cmd);
11699 post_flags &= (~MPTSAS_REQUEST_POOL_CMD);
11700 }
11701 if (post_flags & MPTSAS_REQUEST_POOL_CMD) {
11702 mptsas_return_to_pool(mpt, cmd);
11703 }
11704
11705 return (status);
11706 }
11707
11708 static int
mptsas_release_fw_diag_buffer(mptsas_t * mpt,mptsas_fw_diagnostic_buffer_t * pBuffer,uint32_t * return_code,uint32_t diag_type)11709 mptsas_release_fw_diag_buffer(mptsas_t *mpt,
11710 mptsas_fw_diagnostic_buffer_t *pBuffer, uint32_t *return_code,
11711 uint32_t diag_type)
11712 {
11713 mptsas_diag_request_t diag;
11714 int status, slot_num, rel_flags = 0;
11715 mptsas_cmd_t *cmd = NULL;
11716 struct scsi_pkt *pkt;
11717 pMpi2DiagReleaseReply_t reply;
11718 uint16_t iocstatus;
11719 uint32_t iocloginfo;
11720
11721 /*
11722 * If buffer is not enabled, just leave.
11723 */
11724 *return_code = MPTSAS_FW_DIAG_ERROR_RELEASE_FAILED;
11725 if (!pBuffer->enabled) {
11726 mptsas_log(mpt, CE_NOTE, "This buffer type is not supported "
11727 "by the IOC");
11728 status = DDI_FAILURE;
11729 goto out;
11730 }
11731
11732 /*
11733 * Clear some flags initially.
11734 */
11735 pBuffer->force_release = FALSE;
11736 pBuffer->valid_data = FALSE;
11737 pBuffer->owned_by_firmware = FALSE;
11738
11739 /*
11740 * Get a cmd buffer from the cmd buffer pool
11741 */
11742 if ((slot_num = (mptsas_request_from_pool(mpt, &cmd, &pkt))) == -1) {
11743 status = DDI_FAILURE;
11744 mptsas_log(mpt, CE_NOTE, "command pool is full: Release FW "
11745 "Diag");
11746 goto out;
11747 }
11748 rel_flags |= MPTSAS_REQUEST_POOL_CMD;
11749
11750 bzero((caddr_t)cmd, sizeof (*cmd));
11751 bzero((caddr_t)pkt, scsi_pkt_size());
11752
11753 cmd->ioc_cmd_slot = (uint32_t)(slot_num);
11754
11755 diag.pBuffer = pBuffer;
11756 diag.function = MPI2_FUNCTION_DIAG_RELEASE;
11757
11758 /*
11759 * Form a blank cmd/pkt to store the acknowledgement message
11760 */
11761 pkt->pkt_ha_private = (opaque_t)&diag;
11762 pkt->pkt_flags = FLAG_HEAD;
11763 pkt->pkt_time = 60;
11764 cmd->cmd_pkt = pkt;
11765 cmd->cmd_flags = CFLAG_CMDIOC | CFLAG_FW_DIAG;
11766
11767 /*
11768 * Save the command in a slot
11769 */
11770 if (mptsas_save_cmd(mpt, cmd) == TRUE) {
11771 /*
11772 * Once passthru command get slot, set cmd_flags
11773 * CFLAG_PREPARED.
11774 */
11775 cmd->cmd_flags |= CFLAG_PREPARED;
11776 mptsas_start_diag(mpt, cmd);
11777 } else {
11778 mptsas_waitq_add(mpt, cmd);
11779 }
11780
11781 while ((cmd->cmd_flags & CFLAG_FINISHED) == 0) {
11782 cv_wait(&mpt->m_fw_diag_cv, &mpt->m_mutex);
11783 }
11784
11785 if (cmd->cmd_flags & CFLAG_TIMEOUT) {
11786 status = DDI_FAILURE;
11787 mptsas_log(mpt, CE_WARN, "Release FW Diag command timeout");
11788 goto out;
11789 }
11790
11791 /*
11792 * cmd_rfm points to the reply message if a reply was given. Check the
11793 * IOCStatus to make sure everything went OK with the FW diag request
11794 * and set buffer flags.
11795 */
11796 if (cmd->cmd_rfm) {
11797 rel_flags |= MPTSAS_ADDRESS_REPLY;
11798 (void) ddi_dma_sync(mpt->m_dma_reply_frame_hdl, 0, 0,
11799 DDI_DMA_SYNC_FORCPU);
11800 reply = (pMpi2DiagReleaseReply_t)(mpt->m_reply_frame +
11801 (cmd->cmd_rfm -
11802 (mpt->m_reply_frame_dma_addr & 0xffffffffu)));
11803
11804 /*
11805 * Get the reply message data
11806 */
11807 iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl,
11808 &reply->IOCStatus);
11809 iocloginfo = ddi_get32(mpt->m_acc_reply_frame_hdl,
11810 &reply->IOCLogInfo);
11811
11812 /*
11813 * If release failed quit.
11814 */
11815 if ((iocstatus != MPI2_IOCSTATUS_SUCCESS) ||
11816 pBuffer->owned_by_firmware) {
11817 status = DDI_FAILURE;
11818 NDBG13(("release FW Diag Buffer failed: "
11819 "IOCStatus=0x%x, IOCLogInfo=0x%x", iocstatus,
11820 iocloginfo));
11821 goto out;
11822 }
11823
11824 /*
11825 * Release was successful.
11826 */
11827 *return_code = MPTSAS_FW_DIAG_ERROR_SUCCESS;
11828 status = DDI_SUCCESS;
11829
11830 /*
11831 * If this was for an UNREGISTER diag type command, clear the
11832 * unique ID.
11833 */
11834 if (diag_type == MPTSAS_FW_DIAG_TYPE_UNREGISTER) {
11835 pBuffer->unique_id = MPTSAS_FW_DIAG_INVALID_UID;
11836 }
11837 }
11838
11839 out:
11840 /*
11841 * Put the reply frame back on the free queue, increment the free
11842 * index, and write the new index to the free index register. But only
11843 * if this reply is an ADDRESS reply.
11844 */
11845 if (rel_flags & MPTSAS_ADDRESS_REPLY) {
11846 ddi_put32(mpt->m_acc_free_queue_hdl,
11847 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index],
11848 cmd->cmd_rfm);
11849 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0,
11850 DDI_DMA_SYNC_FORDEV);
11851 if (++mpt->m_free_index == mpt->m_free_queue_depth) {
11852 mpt->m_free_index = 0;
11853 }
11854 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex,
11855 mpt->m_free_index);
11856 }
11857 if (cmd && (cmd->cmd_flags & CFLAG_PREPARED)) {
11858 mptsas_remove_cmd(mpt, cmd);
11859 rel_flags &= (~MPTSAS_REQUEST_POOL_CMD);
11860 }
11861 if (rel_flags & MPTSAS_REQUEST_POOL_CMD) {
11862 mptsas_return_to_pool(mpt, cmd);
11863 }
11864
11865 return (status);
11866 }
11867
11868 static int
mptsas_diag_register(mptsas_t * mpt,mptsas_fw_diag_register_t * diag_register,uint32_t * return_code)11869 mptsas_diag_register(mptsas_t *mpt, mptsas_fw_diag_register_t *diag_register,
11870 uint32_t *return_code)
11871 {
11872 mptsas_fw_diagnostic_buffer_t *pBuffer;
11873 uint8_t extended_type, buffer_type, i;
11874 uint32_t buffer_size;
11875 uint32_t unique_id;
11876 int status;
11877
11878 ASSERT(mutex_owned(&mpt->m_mutex));
11879
11880 extended_type = diag_register->ExtendedType;
11881 buffer_type = diag_register->BufferType;
11882 buffer_size = diag_register->RequestedBufferSize;
11883 unique_id = diag_register->UniqueId;
11884
11885 /*
11886 * Check for valid buffer type
11887 */
11888 if (buffer_type >= MPI2_DIAG_BUF_TYPE_COUNT) {
11889 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
11890 return (DDI_FAILURE);
11891 }
11892
11893 /*
11894 * Get the current buffer and look up the unique ID. The unique ID
11895 * should not be found. If it is, the ID is already in use.
11896 */
11897 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id);
11898 pBuffer = &mpt->m_fw_diag_buffer_list[buffer_type];
11899 if (i != MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) {
11900 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID;
11901 return (DDI_FAILURE);
11902 }
11903
11904 /*
11905 * The buffer's unique ID should not be registered yet, and the given
11906 * unique ID cannot be 0.
11907 */
11908 if ((pBuffer->unique_id != MPTSAS_FW_DIAG_INVALID_UID) ||
11909 (unique_id == MPTSAS_FW_DIAG_INVALID_UID)) {
11910 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID;
11911 return (DDI_FAILURE);
11912 }
11913
11914 /*
11915 * If this buffer is already posted as immediate, just change owner.
11916 */
11917 if (pBuffer->immediate && pBuffer->owned_by_firmware &&
11918 (pBuffer->unique_id == MPTSAS_FW_DIAG_INVALID_UID)) {
11919 pBuffer->immediate = FALSE;
11920 pBuffer->unique_id = unique_id;
11921 return (DDI_SUCCESS);
11922 }
11923
11924 /*
11925 * Post a new buffer after checking if it's enabled. The DMA buffer
11926 * that is allocated will be contiguous (sgl_len = 1).
11927 */
11928 if (!pBuffer->enabled) {
11929 *return_code = MPTSAS_FW_DIAG_ERROR_NO_BUFFER;
11930 return (DDI_FAILURE);
11931 }
11932 bzero(&pBuffer->buffer_data, sizeof (mptsas_dma_alloc_state_t));
11933 pBuffer->buffer_data.size = buffer_size;
11934 if (mptsas_dma_alloc(mpt, &pBuffer->buffer_data) != DDI_SUCCESS) {
11935 mptsas_log(mpt, CE_WARN, "failed to alloc DMA resource for "
11936 "diag buffer: size = %d bytes", buffer_size);
11937 *return_code = MPTSAS_FW_DIAG_ERROR_NO_BUFFER;
11938 return (DDI_FAILURE);
11939 }
11940
11941 /*
11942 * Copy the given info to the diag buffer and post the buffer.
11943 */
11944 pBuffer->buffer_type = buffer_type;
11945 pBuffer->immediate = FALSE;
11946 if (buffer_type == MPI2_DIAG_BUF_TYPE_TRACE) {
11947 for (i = 0; i < (sizeof (pBuffer->product_specific) / 4);
11948 i++) {
11949 pBuffer->product_specific[i] =
11950 diag_register->ProductSpecific[i];
11951 }
11952 }
11953 pBuffer->extended_type = extended_type;
11954 pBuffer->unique_id = unique_id;
11955 status = mptsas_post_fw_diag_buffer(mpt, pBuffer, return_code);
11956
11957 if (mptsas_check_dma_handle(pBuffer->buffer_data.handle) !=
11958 DDI_SUCCESS) {
11959 mptsas_log(mpt, CE_WARN, "Check of DMA handle failed in "
11960 "mptsas_diag_register.");
11961 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
11962 status = DDI_FAILURE;
11963 }
11964
11965 /*
11966 * In case there was a failure, free the DMA buffer.
11967 */
11968 if (status == DDI_FAILURE) {
11969 mptsas_dma_free(&pBuffer->buffer_data);
11970 }
11971
11972 return (status);
11973 }
11974
11975 static int
mptsas_diag_unregister(mptsas_t * mpt,mptsas_fw_diag_unregister_t * diag_unregister,uint32_t * return_code)11976 mptsas_diag_unregister(mptsas_t *mpt,
11977 mptsas_fw_diag_unregister_t *diag_unregister, uint32_t *return_code)
11978 {
11979 mptsas_fw_diagnostic_buffer_t *pBuffer;
11980 uint8_t i;
11981 uint32_t unique_id;
11982 int status;
11983
11984 ASSERT(mutex_owned(&mpt->m_mutex));
11985
11986 unique_id = diag_unregister->UniqueId;
11987
11988 /*
11989 * Get the current buffer and look up the unique ID. The unique ID
11990 * should be there.
11991 */
11992 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id);
11993 if (i == MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) {
11994 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID;
11995 return (DDI_FAILURE);
11996 }
11997
11998 pBuffer = &mpt->m_fw_diag_buffer_list[i];
11999
12000 /*
12001 * Try to release the buffer from FW before freeing it. If release
12002 * fails, don't free the DMA buffer in case FW tries to access it
12003 * later. If buffer is not owned by firmware, can't release it.
12004 */
12005 if (!pBuffer->owned_by_firmware) {
12006 status = DDI_SUCCESS;
12007 } else {
12008 status = mptsas_release_fw_diag_buffer(mpt, pBuffer,
12009 return_code, MPTSAS_FW_DIAG_TYPE_UNREGISTER);
12010 }
12011
12012 /*
12013 * At this point, return the current status no matter what happens with
12014 * the DMA buffer.
12015 */
12016 pBuffer->unique_id = MPTSAS_FW_DIAG_INVALID_UID;
12017 if (status == DDI_SUCCESS) {
12018 if (mptsas_check_dma_handle(pBuffer->buffer_data.handle) !=
12019 DDI_SUCCESS) {
12020 mptsas_log(mpt, CE_WARN, "Check of DMA handle failed "
12021 "in mptsas_diag_unregister.");
12022 ddi_fm_service_impact(mpt->m_dip,
12023 DDI_SERVICE_UNAFFECTED);
12024 }
12025 mptsas_dma_free(&pBuffer->buffer_data);
12026 }
12027
12028 return (status);
12029 }
12030
12031 static int
mptsas_diag_query(mptsas_t * mpt,mptsas_fw_diag_query_t * diag_query,uint32_t * return_code)12032 mptsas_diag_query(mptsas_t *mpt, mptsas_fw_diag_query_t *diag_query,
12033 uint32_t *return_code)
12034 {
12035 mptsas_fw_diagnostic_buffer_t *pBuffer;
12036 uint8_t i;
12037 uint32_t unique_id;
12038
12039 ASSERT(mutex_owned(&mpt->m_mutex));
12040
12041 unique_id = diag_query->UniqueId;
12042
12043 /*
12044 * If ID is valid, query on ID.
12045 * If ID is invalid, query on buffer type.
12046 */
12047 if (unique_id == MPTSAS_FW_DIAG_INVALID_UID) {
12048 i = diag_query->BufferType;
12049 if (i >= MPI2_DIAG_BUF_TYPE_COUNT) {
12050 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID;
12051 return (DDI_FAILURE);
12052 }
12053 } else {
12054 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id);
12055 if (i == MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) {
12056 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID;
12057 return (DDI_FAILURE);
12058 }
12059 }
12060
12061 /*
12062 * Fill query structure with the diag buffer info.
12063 */
12064 pBuffer = &mpt->m_fw_diag_buffer_list[i];
12065 diag_query->BufferType = pBuffer->buffer_type;
12066 diag_query->ExtendedType = pBuffer->extended_type;
12067 if (diag_query->BufferType == MPI2_DIAG_BUF_TYPE_TRACE) {
12068 for (i = 0; i < (sizeof (diag_query->ProductSpecific) / 4);
12069 i++) {
12070 diag_query->ProductSpecific[i] =
12071 pBuffer->product_specific[i];
12072 }
12073 }
12074 diag_query->TotalBufferSize = pBuffer->buffer_data.size;
12075 diag_query->DriverAddedBufferSize = 0;
12076 diag_query->UniqueId = pBuffer->unique_id;
12077 diag_query->ApplicationFlags = 0;
12078 diag_query->DiagnosticFlags = 0;
12079
12080 /*
12081 * Set/Clear application flags
12082 */
12083 if (pBuffer->immediate) {
12084 diag_query->ApplicationFlags &= ~MPTSAS_FW_DIAG_FLAG_APP_OWNED;
12085 } else {
12086 diag_query->ApplicationFlags |= MPTSAS_FW_DIAG_FLAG_APP_OWNED;
12087 }
12088 if (pBuffer->valid_data || pBuffer->owned_by_firmware) {
12089 diag_query->ApplicationFlags |=
12090 MPTSAS_FW_DIAG_FLAG_BUFFER_VALID;
12091 } else {
12092 diag_query->ApplicationFlags &=
12093 ~MPTSAS_FW_DIAG_FLAG_BUFFER_VALID;
12094 }
12095 if (pBuffer->owned_by_firmware) {
12096 diag_query->ApplicationFlags |=
12097 MPTSAS_FW_DIAG_FLAG_FW_BUFFER_ACCESS;
12098 } else {
12099 diag_query->ApplicationFlags &=
12100 ~MPTSAS_FW_DIAG_FLAG_FW_BUFFER_ACCESS;
12101 }
12102
12103 return (DDI_SUCCESS);
12104 }
12105
12106 static int
mptsas_diag_read_buffer(mptsas_t * mpt,mptsas_diag_read_buffer_t * diag_read_buffer,uint8_t * ioctl_buf,uint32_t * return_code,int ioctl_mode)12107 mptsas_diag_read_buffer(mptsas_t *mpt,
12108 mptsas_diag_read_buffer_t *diag_read_buffer, uint8_t *ioctl_buf,
12109 uint32_t *return_code, int ioctl_mode)
12110 {
12111 mptsas_fw_diagnostic_buffer_t *pBuffer;
12112 uint8_t i, *pData;
12113 uint32_t unique_id, byte;
12114 int status;
12115
12116 ASSERT(mutex_owned(&mpt->m_mutex));
12117
12118 unique_id = diag_read_buffer->UniqueId;
12119
12120 /*
12121 * Get the current buffer and look up the unique ID. The unique ID
12122 * should be there.
12123 */
12124 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id);
12125 if (i == MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) {
12126 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID;
12127 return (DDI_FAILURE);
12128 }
12129
12130 pBuffer = &mpt->m_fw_diag_buffer_list[i];
12131
12132 /*
12133 * Make sure requested read is within limits
12134 */
12135 if (diag_read_buffer->StartingOffset + diag_read_buffer->BytesToRead >
12136 pBuffer->buffer_data.size) {
12137 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
12138 return (DDI_FAILURE);
12139 }
12140
12141 /*
12142 * Copy the requested data from DMA to the diag_read_buffer. The DMA
12143 * buffer that was allocated is one contiguous buffer.
12144 */
12145 pData = (uint8_t *)(pBuffer->buffer_data.memp +
12146 diag_read_buffer->StartingOffset);
12147 (void) ddi_dma_sync(pBuffer->buffer_data.handle, 0, 0,
12148 DDI_DMA_SYNC_FORCPU);
12149 for (byte = 0; byte < diag_read_buffer->BytesToRead; byte++) {
12150 if (ddi_copyout(pData + byte, ioctl_buf + byte, 1, ioctl_mode)
12151 != 0) {
12152 return (DDI_FAILURE);
12153 }
12154 }
12155 diag_read_buffer->Status = 0;
12156
12157 /*
12158 * Set or clear the Force Release flag.
12159 */
12160 if (pBuffer->force_release) {
12161 diag_read_buffer->Flags |= MPTSAS_FW_DIAG_FLAG_FORCE_RELEASE;
12162 } else {
12163 diag_read_buffer->Flags &= ~MPTSAS_FW_DIAG_FLAG_FORCE_RELEASE;
12164 }
12165
12166 /*
12167 * If buffer is to be reregistered, make sure it's not already owned by
12168 * firmware first.
12169 */
12170 status = DDI_SUCCESS;
12171 if (!pBuffer->owned_by_firmware) {
12172 if (diag_read_buffer->Flags & MPTSAS_FW_DIAG_FLAG_REREGISTER) {
12173 status = mptsas_post_fw_diag_buffer(mpt, pBuffer,
12174 return_code);
12175 }
12176 }
12177
12178 return (status);
12179 }
12180
12181 static int
mptsas_diag_release(mptsas_t * mpt,mptsas_fw_diag_release_t * diag_release,uint32_t * return_code)12182 mptsas_diag_release(mptsas_t *mpt, mptsas_fw_diag_release_t *diag_release,
12183 uint32_t *return_code)
12184 {
12185 mptsas_fw_diagnostic_buffer_t *pBuffer;
12186 uint8_t i;
12187 uint32_t unique_id;
12188 int status;
12189
12190 ASSERT(mutex_owned(&mpt->m_mutex));
12191
12192 unique_id = diag_release->UniqueId;
12193
12194 /*
12195 * Get the current buffer and look up the unique ID. The unique ID
12196 * should be there.
12197 */
12198 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id);
12199 if (i == MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) {
12200 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID;
12201 return (DDI_FAILURE);
12202 }
12203
12204 pBuffer = &mpt->m_fw_diag_buffer_list[i];
12205
12206 /*
12207 * If buffer is not owned by firmware, it's already been released.
12208 */
12209 if (!pBuffer->owned_by_firmware) {
12210 *return_code = MPTSAS_FW_DIAG_ERROR_ALREADY_RELEASED;
12211 return (DDI_FAILURE);
12212 }
12213
12214 /*
12215 * Release the buffer.
12216 */
12217 status = mptsas_release_fw_diag_buffer(mpt, pBuffer, return_code,
12218 MPTSAS_FW_DIAG_TYPE_RELEASE);
12219 return (status);
12220 }
12221
12222 static int
mptsas_do_diag_action(mptsas_t * mpt,uint32_t action,uint8_t * diag_action,uint32_t length,uint32_t * return_code,int ioctl_mode)12223 mptsas_do_diag_action(mptsas_t *mpt, uint32_t action, uint8_t *diag_action,
12224 uint32_t length, uint32_t *return_code, int ioctl_mode)
12225 {
12226 mptsas_fw_diag_register_t diag_register;
12227 mptsas_fw_diag_unregister_t diag_unregister;
12228 mptsas_fw_diag_query_t diag_query;
12229 mptsas_diag_read_buffer_t diag_read_buffer;
12230 mptsas_fw_diag_release_t diag_release;
12231 int status = DDI_SUCCESS;
12232 uint32_t original_return_code, read_buf_len;
12233
12234 ASSERT(mutex_owned(&mpt->m_mutex));
12235
12236 original_return_code = *return_code;
12237 *return_code = MPTSAS_FW_DIAG_ERROR_SUCCESS;
12238
12239 switch (action) {
12240 case MPTSAS_FW_DIAG_TYPE_REGISTER:
12241 if (!length) {
12242 *return_code =
12243 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
12244 status = DDI_FAILURE;
12245 break;
12246 }
12247 if (ddi_copyin(diag_action, &diag_register,
12248 sizeof (diag_register), ioctl_mode) != 0) {
12249 return (DDI_FAILURE);
12250 }
12251 status = mptsas_diag_register(mpt, &diag_register,
12252 return_code);
12253 break;
12254
12255 case MPTSAS_FW_DIAG_TYPE_UNREGISTER:
12256 if (length < sizeof (diag_unregister)) {
12257 *return_code =
12258 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
12259 status = DDI_FAILURE;
12260 break;
12261 }
12262 if (ddi_copyin(diag_action, &diag_unregister,
12263 sizeof (diag_unregister), ioctl_mode) != 0) {
12264 return (DDI_FAILURE);
12265 }
12266 status = mptsas_diag_unregister(mpt, &diag_unregister,
12267 return_code);
12268 break;
12269
12270 case MPTSAS_FW_DIAG_TYPE_QUERY:
12271 if (length < sizeof (diag_query)) {
12272 *return_code =
12273 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
12274 status = DDI_FAILURE;
12275 break;
12276 }
12277 if (ddi_copyin(diag_action, &diag_query,
12278 sizeof (diag_query), ioctl_mode) != 0) {
12279 return (DDI_FAILURE);
12280 }
12281 status = mptsas_diag_query(mpt, &diag_query,
12282 return_code);
12283 if (status == DDI_SUCCESS) {
12284 if (ddi_copyout(&diag_query, diag_action,
12285 sizeof (diag_query), ioctl_mode) != 0) {
12286 return (DDI_FAILURE);
12287 }
12288 }
12289 break;
12290
12291 case MPTSAS_FW_DIAG_TYPE_READ_BUFFER:
12292 if (ddi_copyin(diag_action, &diag_read_buffer,
12293 sizeof (diag_read_buffer) - 4, ioctl_mode) != 0) {
12294 return (DDI_FAILURE);
12295 }
12296 read_buf_len = sizeof (diag_read_buffer) -
12297 sizeof (diag_read_buffer.DataBuffer) +
12298 diag_read_buffer.BytesToRead;
12299 if (length < read_buf_len) {
12300 *return_code =
12301 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
12302 status = DDI_FAILURE;
12303 break;
12304 }
12305 status = mptsas_diag_read_buffer(mpt,
12306 &diag_read_buffer, diag_action +
12307 sizeof (diag_read_buffer) - 4, return_code,
12308 ioctl_mode);
12309 if (status == DDI_SUCCESS) {
12310 if (ddi_copyout(&diag_read_buffer, diag_action,
12311 sizeof (diag_read_buffer) - 4, ioctl_mode)
12312 != 0) {
12313 return (DDI_FAILURE);
12314 }
12315 }
12316 break;
12317
12318 case MPTSAS_FW_DIAG_TYPE_RELEASE:
12319 if (length < sizeof (diag_release)) {
12320 *return_code =
12321 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
12322 status = DDI_FAILURE;
12323 break;
12324 }
12325 if (ddi_copyin(diag_action, &diag_release,
12326 sizeof (diag_release), ioctl_mode) != 0) {
12327 return (DDI_FAILURE);
12328 }
12329 status = mptsas_diag_release(mpt, &diag_release,
12330 return_code);
12331 break;
12332
12333 default:
12334 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
12335 status = DDI_FAILURE;
12336 break;
12337 }
12338
12339 if ((status == DDI_FAILURE) &&
12340 (original_return_code == MPTSAS_FW_DIAG_NEW) &&
12341 (*return_code != MPTSAS_FW_DIAG_ERROR_SUCCESS)) {
12342 status = DDI_SUCCESS;
12343 }
12344
12345 return (status);
12346 }
12347
12348 static int
mptsas_diag_action(mptsas_t * mpt,mptsas_diag_action_t * user_data,int mode)12349 mptsas_diag_action(mptsas_t *mpt, mptsas_diag_action_t *user_data, int mode)
12350 {
12351 int status;
12352 mptsas_diag_action_t driver_data;
12353
12354 ASSERT(mutex_owned(&mpt->m_mutex));
12355
12356 /*
12357 * Copy the user data to a driver data buffer.
12358 */
12359 if (ddi_copyin(user_data, &driver_data, sizeof (mptsas_diag_action_t),
12360 mode) == 0) {
12361 /*
12362 * Send diag action request if Action is valid
12363 */
12364 if (driver_data.Action == MPTSAS_FW_DIAG_TYPE_REGISTER ||
12365 driver_data.Action == MPTSAS_FW_DIAG_TYPE_UNREGISTER ||
12366 driver_data.Action == MPTSAS_FW_DIAG_TYPE_QUERY ||
12367 driver_data.Action == MPTSAS_FW_DIAG_TYPE_READ_BUFFER ||
12368 driver_data.Action == MPTSAS_FW_DIAG_TYPE_RELEASE) {
12369 status = mptsas_do_diag_action(mpt, driver_data.Action,
12370 (void *)(uintptr_t)driver_data.PtrDiagAction,
12371 driver_data.Length, &driver_data.ReturnCode,
12372 mode);
12373 if (status == DDI_SUCCESS) {
12374 if (ddi_copyout(&driver_data.ReturnCode,
12375 &user_data->ReturnCode,
12376 sizeof (user_data->ReturnCode), mode)
12377 != 0) {
12378 status = EFAULT;
12379 } else {
12380 status = 0;
12381 }
12382 } else {
12383 status = EIO;
12384 }
12385 } else {
12386 status = EINVAL;
12387 }
12388 } else {
12389 status = EFAULT;
12390 }
12391
12392 return (status);
12393 }
12394
12395 /*
12396 * This routine handles the "event query" ioctl.
12397 */
12398 static int
mptsas_event_query(mptsas_t * mpt,mptsas_event_query_t * data,int mode,int * rval)12399 mptsas_event_query(mptsas_t *mpt, mptsas_event_query_t *data, int mode,
12400 int *rval)
12401 {
12402 int status;
12403 mptsas_event_query_t driverdata;
12404 uint8_t i;
12405
12406 driverdata.Entries = MPTSAS_EVENT_QUEUE_SIZE;
12407
12408 mutex_enter(&mpt->m_mutex);
12409 for (i = 0; i < 4; i++) {
12410 driverdata.Types[i] = mpt->m_event_mask[i];
12411 }
12412 mutex_exit(&mpt->m_mutex);
12413
12414 if (ddi_copyout(&driverdata, data, sizeof (driverdata), mode) != 0) {
12415 status = EFAULT;
12416 } else {
12417 *rval = MPTIOCTL_STATUS_GOOD;
12418 status = 0;
12419 }
12420
12421 return (status);
12422 }
12423
12424 /*
12425 * This routine handles the "event enable" ioctl.
12426 */
12427 static int
mptsas_event_enable(mptsas_t * mpt,mptsas_event_enable_t * data,int mode,int * rval)12428 mptsas_event_enable(mptsas_t *mpt, mptsas_event_enable_t *data, int mode,
12429 int *rval)
12430 {
12431 int status;
12432 mptsas_event_enable_t driverdata;
12433 uint8_t i;
12434
12435 if (ddi_copyin(data, &driverdata, sizeof (driverdata), mode) == 0) {
12436 mutex_enter(&mpt->m_mutex);
12437 for (i = 0; i < 4; i++) {
12438 mpt->m_event_mask[i] = driverdata.Types[i];
12439 }
12440 mutex_exit(&mpt->m_mutex);
12441
12442 *rval = MPTIOCTL_STATUS_GOOD;
12443 status = 0;
12444 } else {
12445 status = EFAULT;
12446 }
12447 return (status);
12448 }
12449
12450 /*
12451 * This routine handles the "event report" ioctl.
12452 */
12453 static int
mptsas_event_report(mptsas_t * mpt,mptsas_event_report_t * data,int mode,int * rval)12454 mptsas_event_report(mptsas_t *mpt, mptsas_event_report_t *data, int mode,
12455 int *rval)
12456 {
12457 int status;
12458 mptsas_event_report_t driverdata;
12459
12460 mutex_enter(&mpt->m_mutex);
12461
12462 if (ddi_copyin(&data->Size, &driverdata.Size, sizeof (driverdata.Size),
12463 mode) == 0) {
12464 if (driverdata.Size >= sizeof (mpt->m_events)) {
12465 if (ddi_copyout(mpt->m_events, data->Events,
12466 sizeof (mpt->m_events), mode) != 0) {
12467 status = EFAULT;
12468 } else {
12469 if (driverdata.Size > sizeof (mpt->m_events)) {
12470 driverdata.Size =
12471 sizeof (mpt->m_events);
12472 if (ddi_copyout(&driverdata.Size,
12473 &data->Size,
12474 sizeof (driverdata.Size),
12475 mode) != 0) {
12476 status = EFAULT;
12477 } else {
12478 *rval = MPTIOCTL_STATUS_GOOD;
12479 status = 0;
12480 }
12481 } else {
12482 *rval = MPTIOCTL_STATUS_GOOD;
12483 status = 0;
12484 }
12485 }
12486 } else {
12487 *rval = MPTIOCTL_STATUS_LEN_TOO_SHORT;
12488 status = 0;
12489 }
12490 } else {
12491 status = EFAULT;
12492 }
12493
12494 mutex_exit(&mpt->m_mutex);
12495 return (status);
12496 }
12497
12498 static void
mptsas_lookup_pci_data(mptsas_t * mpt,mptsas_adapter_data_t * adapter_data)12499 mptsas_lookup_pci_data(mptsas_t *mpt, mptsas_adapter_data_t *adapter_data)
12500 {
12501 int *reg_data;
12502 uint_t reglen;
12503
12504 /*
12505 * Lookup the 'reg' property and extract the other data
12506 */
12507 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, mpt->m_dip,
12508 DDI_PROP_DONTPASS, "reg", ®_data, ®len) ==
12509 DDI_PROP_SUCCESS) {
12510 /*
12511 * Extract the PCI data from the 'reg' property first DWORD.
12512 * The entry looks like the following:
12513 * First DWORD:
12514 * Bits 0 - 7 8-bit Register number
12515 * Bits 8 - 10 3-bit Function number
12516 * Bits 11 - 15 5-bit Device number
12517 * Bits 16 - 23 8-bit Bus number
12518 * Bits 24 - 25 2-bit Address Space type identifier
12519 *
12520 */
12521 adapter_data->PciInformation.u.bits.BusNumber =
12522 (reg_data[0] & 0x00FF0000) >> 16;
12523 adapter_data->PciInformation.u.bits.DeviceNumber =
12524 (reg_data[0] & 0x0000F800) >> 11;
12525 adapter_data->PciInformation.u.bits.FunctionNumber =
12526 (reg_data[0] & 0x00000700) >> 8;
12527 ddi_prop_free((void *)reg_data);
12528 } else {
12529 /*
12530 * If we can't determine the PCI data then we fill in FF's for
12531 * the data to indicate this.
12532 */
12533 adapter_data->PCIDeviceHwId = 0xFFFFFFFF;
12534 adapter_data->MpiPortNumber = 0xFFFFFFFF;
12535 adapter_data->PciInformation.u.AsDWORD = 0xFFFFFFFF;
12536 }
12537
12538 /*
12539 * Saved in the mpt->m_fwversion
12540 */
12541 adapter_data->MpiFirmwareVersion = mpt->m_fwversion;
12542 }
12543
12544 static void
mptsas_read_adapter_data(mptsas_t * mpt,mptsas_adapter_data_t * adapter_data)12545 mptsas_read_adapter_data(mptsas_t *mpt, mptsas_adapter_data_t *adapter_data)
12546 {
12547 char *driver_verstr = MPTSAS_MOD_STRING;
12548
12549 mptsas_lookup_pci_data(mpt, adapter_data);
12550 adapter_data->AdapterType = mpt->m_MPI25 ?
12551 MPTIOCTL_ADAPTER_TYPE_SAS3 :
12552 MPTIOCTL_ADAPTER_TYPE_SAS2;
12553 adapter_data->PCIDeviceHwId = (uint32_t)mpt->m_devid;
12554 adapter_data->PCIDeviceHwRev = (uint32_t)mpt->m_revid;
12555 adapter_data->SubSystemId = (uint32_t)mpt->m_ssid;
12556 adapter_data->SubsystemVendorId = (uint32_t)mpt->m_svid;
12557 (void) strcpy((char *)&adapter_data->DriverVersion[0], driver_verstr);
12558 adapter_data->BiosVersion = 0;
12559 (void) mptsas_get_bios_page3(mpt, &adapter_data->BiosVersion);
12560 }
12561
12562 static void
mptsas_read_pci_info(mptsas_t * mpt,mptsas_pci_info_t * pci_info)12563 mptsas_read_pci_info(mptsas_t *mpt, mptsas_pci_info_t *pci_info)
12564 {
12565 int *reg_data, i;
12566 uint_t reglen;
12567
12568 /*
12569 * Lookup the 'reg' property and extract the other data
12570 */
12571 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, mpt->m_dip,
12572 DDI_PROP_DONTPASS, "reg", ®_data, ®len) ==
12573 DDI_PROP_SUCCESS) {
12574 /*
12575 * Extract the PCI data from the 'reg' property first DWORD.
12576 * The entry looks like the following:
12577 * First DWORD:
12578 * Bits 8 - 10 3-bit Function number
12579 * Bits 11 - 15 5-bit Device number
12580 * Bits 16 - 23 8-bit Bus number
12581 */
12582 pci_info->BusNumber = (reg_data[0] & 0x00FF0000) >> 16;
12583 pci_info->DeviceNumber = (reg_data[0] & 0x0000F800) >> 11;
12584 pci_info->FunctionNumber = (reg_data[0] & 0x00000700) >> 8;
12585 ddi_prop_free((void *)reg_data);
12586 } else {
12587 /*
12588 * If we can't determine the PCI info then we fill in FF's for
12589 * the data to indicate this.
12590 */
12591 pci_info->BusNumber = 0xFFFFFFFF;
12592 pci_info->DeviceNumber = 0xFF;
12593 pci_info->FunctionNumber = 0xFF;
12594 }
12595
12596 /*
12597 * Now get the interrupt vector and the pci header. The vector can
12598 * only be 0 right now. The header is the first 256 bytes of config
12599 * space.
12600 */
12601 pci_info->InterruptVector = 0;
12602 for (i = 0; i < sizeof (pci_info->PciHeader); i++) {
12603 pci_info->PciHeader[i] = pci_config_get8(mpt->m_config_handle,
12604 i);
12605 }
12606 }
12607
12608 static int
mptsas_reg_access(mptsas_t * mpt,mptsas_reg_access_t * data,int mode)12609 mptsas_reg_access(mptsas_t *mpt, mptsas_reg_access_t *data, int mode)
12610 {
12611 int status = 0;
12612 mptsas_reg_access_t driverdata;
12613
12614 mutex_enter(&mpt->m_mutex);
12615 if (ddi_copyin(data, &driverdata, sizeof (driverdata), mode) == 0) {
12616 switch (driverdata.Command) {
12617 /*
12618 * IO access is not supported.
12619 */
12620 case REG_IO_READ:
12621 case REG_IO_WRITE:
12622 mptsas_log(mpt, CE_WARN, "IO access is not "
12623 "supported. Use memory access.");
12624 status = EINVAL;
12625 break;
12626
12627 case REG_MEM_READ:
12628 driverdata.RegData = ddi_get32(mpt->m_datap,
12629 (uint32_t *)(void *)mpt->m_reg +
12630 driverdata.RegOffset);
12631 if (ddi_copyout(&driverdata.RegData,
12632 &data->RegData,
12633 sizeof (driverdata.RegData), mode) != 0) {
12634 mptsas_log(mpt, CE_WARN, "Register "
12635 "Read Failed");
12636 status = EFAULT;
12637 }
12638 break;
12639
12640 case REG_MEM_WRITE:
12641 ddi_put32(mpt->m_datap,
12642 (uint32_t *)(void *)mpt->m_reg +
12643 driverdata.RegOffset,
12644 driverdata.RegData);
12645 break;
12646
12647 default:
12648 status = EINVAL;
12649 break;
12650 }
12651 } else {
12652 status = EFAULT;
12653 }
12654
12655 mutex_exit(&mpt->m_mutex);
12656 return (status);
12657 }
12658
12659 static int
led_control(mptsas_t * mpt,intptr_t data,int mode)12660 led_control(mptsas_t *mpt, intptr_t data, int mode)
12661 {
12662 int ret = 0;
12663 mptsas_led_control_t lc;
12664 mptsas_enclosure_t *mep;
12665 uint16_t slotidx;
12666
12667 if (ddi_copyin((void *)data, &lc, sizeof (lc), mode) != 0) {
12668 return (EFAULT);
12669 }
12670
12671 if ((lc.Command != MPTSAS_LEDCTL_FLAG_SET &&
12672 lc.Command != MPTSAS_LEDCTL_FLAG_GET) ||
12673 lc.Led < MPTSAS_LEDCTL_LED_MIN ||
12674 lc.Led > MPTSAS_LEDCTL_LED_MAX ||
12675 (lc.Command == MPTSAS_LEDCTL_FLAG_SET && lc.LedStatus != 0 &&
12676 lc.LedStatus != 1)) {
12677 return (EINVAL);
12678 }
12679
12680 if ((lc.Command == MPTSAS_LEDCTL_FLAG_SET && (mode & FWRITE) == 0) ||
12681 (lc.Command == MPTSAS_LEDCTL_FLAG_GET && (mode & FREAD) == 0))
12682 return (EACCES);
12683
12684 /* Locate the required enclosure */
12685 mutex_enter(&mpt->m_mutex);
12686 mep = mptsas_enc_lookup(mpt, lc.Enclosure);
12687 if (mep == NULL) {
12688 mutex_exit(&mpt->m_mutex);
12689 return (ENOENT);
12690 }
12691
12692 if (lc.Slot < mep->me_fslot) {
12693 mutex_exit(&mpt->m_mutex);
12694 return (ENOENT);
12695 }
12696
12697 /*
12698 * Slots on the enclosure are maintained in array where me_fslot is
12699 * entry zero. We normalize the requested slot.
12700 */
12701 slotidx = lc.Slot - mep->me_fslot;
12702 if (slotidx >= mep->me_nslots) {
12703 mutex_exit(&mpt->m_mutex);
12704 return (ENOENT);
12705 }
12706
12707 if (lc.Command == MPTSAS_LEDCTL_FLAG_SET) {
12708 /* Update our internal LED state. */
12709 mep->me_slotleds[slotidx] &= ~(1 << (lc.Led - 1));
12710 mep->me_slotleds[slotidx] |= lc.LedStatus << (lc.Led - 1);
12711
12712 /* Flush it to the controller. */
12713 ret = mptsas_flush_led_status(mpt, mep, slotidx);
12714 mutex_exit(&mpt->m_mutex);
12715 return (ret);
12716 }
12717
12718 /* Return our internal LED state. */
12719 lc.LedStatus = (mep->me_slotleds[slotidx] >> (lc.Led - 1)) & 1;
12720 mutex_exit(&mpt->m_mutex);
12721
12722 if (ddi_copyout(&lc, (void *)data, sizeof (lc), mode) != 0) {
12723 return (EFAULT);
12724 }
12725
12726 return (0);
12727 }
12728
12729 static int
get_disk_info(mptsas_t * mpt,intptr_t data,int mode)12730 get_disk_info(mptsas_t *mpt, intptr_t data, int mode)
12731 {
12732 uint16_t i = 0;
12733 uint16_t count = 0;
12734 int ret = 0;
12735 mptsas_target_t *ptgt;
12736 mptsas_disk_info_t *di;
12737 STRUCT_DECL(mptsas_get_disk_info, gdi);
12738
12739 if ((mode & FREAD) == 0)
12740 return (EACCES);
12741
12742 STRUCT_INIT(gdi, get_udatamodel());
12743
12744 if (ddi_copyin((void *)data, STRUCT_BUF(gdi), STRUCT_SIZE(gdi),
12745 mode) != 0) {
12746 return (EFAULT);
12747 }
12748
12749 /* Find out how many targets there are. */
12750 mutex_enter(&mpt->m_mutex);
12751 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
12752 ptgt = refhash_next(mpt->m_targets, ptgt)) {
12753 count++;
12754 }
12755 mutex_exit(&mpt->m_mutex);
12756
12757 /*
12758 * If we haven't been asked to copy out information on each target,
12759 * then just return the count.
12760 */
12761 STRUCT_FSET(gdi, DiskCount, count);
12762 if (STRUCT_FGETP(gdi, PtrDiskInfoArray) == NULL)
12763 goto copy_out;
12764
12765 /*
12766 * If we haven't been given a large enough buffer to copy out into,
12767 * let the caller know.
12768 */
12769 if (STRUCT_FGET(gdi, DiskInfoArraySize) <
12770 count * sizeof (mptsas_disk_info_t)) {
12771 ret = ENOSPC;
12772 goto copy_out;
12773 }
12774
12775 di = kmem_zalloc(count * sizeof (mptsas_disk_info_t), KM_SLEEP);
12776
12777 mutex_enter(&mpt->m_mutex);
12778 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
12779 ptgt = refhash_next(mpt->m_targets, ptgt)) {
12780 if (i >= count) {
12781 /*
12782 * The number of targets changed while we weren't
12783 * looking, so give up.
12784 */
12785 refhash_rele(mpt->m_targets, ptgt);
12786 mutex_exit(&mpt->m_mutex);
12787 kmem_free(di, count * sizeof (mptsas_disk_info_t));
12788 return (EAGAIN);
12789 }
12790 di[i].Instance = mpt->m_instance;
12791 di[i].Enclosure = ptgt->m_enclosure;
12792 di[i].Slot = ptgt->m_slot_num;
12793 di[i].SasAddress = ptgt->m_addr.mta_wwn;
12794 i++;
12795 }
12796 mutex_exit(&mpt->m_mutex);
12797 STRUCT_FSET(gdi, DiskCount, i);
12798
12799 /* Copy out the disk information to the caller. */
12800 if (ddi_copyout((void *)di, STRUCT_FGETP(gdi, PtrDiskInfoArray),
12801 i * sizeof (mptsas_disk_info_t), mode) != 0) {
12802 ret = EFAULT;
12803 }
12804
12805 kmem_free(di, count * sizeof (mptsas_disk_info_t));
12806
12807 copy_out:
12808 if (ddi_copyout(STRUCT_BUF(gdi), (void *)data, STRUCT_SIZE(gdi),
12809 mode) != 0) {
12810 ret = EFAULT;
12811 }
12812
12813 return (ret);
12814 }
12815
12816 static int
mptsas_ioctl(dev_t dev,int cmd,intptr_t data,int mode,cred_t * credp,int * rval)12817 mptsas_ioctl(dev_t dev, int cmd, intptr_t data, int mode, cred_t *credp,
12818 int *rval)
12819 {
12820 int status = 0;
12821 mptsas_t *mpt;
12822 mptsas_update_flash_t flashdata;
12823 mptsas_pass_thru_t passthru_data;
12824 mptsas_adapter_data_t adapter_data;
12825 mptsas_pci_info_t pci_info;
12826 int copylen;
12827
12828 int iport_flag = 0;
12829 dev_info_t *dip = NULL;
12830 mptsas_phymask_t phymask = 0;
12831 struct devctl_iocdata *dcp = NULL;
12832 char *addr = NULL;
12833 mptsas_target_t *ptgt = NULL;
12834
12835 *rval = MPTIOCTL_STATUS_GOOD;
12836 if (secpolicy_sys_config(credp, B_FALSE) != 0) {
12837 return (EPERM);
12838 }
12839
12840 mpt = ddi_get_soft_state(mptsas_state, MINOR2INST(getminor(dev)));
12841 if (mpt == NULL) {
12842 /*
12843 * Called from iport node, get the states
12844 */
12845 iport_flag = 1;
12846 dip = mptsas_get_dip_from_dev(dev, &phymask);
12847 if (dip == NULL) {
12848 return (ENXIO);
12849 }
12850 mpt = DIP2MPT(dip);
12851 }
12852 /* Make sure power level is D0 before accessing registers */
12853 mutex_enter(&mpt->m_mutex);
12854 if (mpt->m_options & MPTSAS_OPT_PM) {
12855 (void) pm_busy_component(mpt->m_dip, 0);
12856 if (mpt->m_power_level != PM_LEVEL_D0) {
12857 mutex_exit(&mpt->m_mutex);
12858 if (pm_raise_power(mpt->m_dip, 0, PM_LEVEL_D0) !=
12859 DDI_SUCCESS) {
12860 mptsas_log(mpt, CE_WARN,
12861 "mptsas%d: mptsas_ioctl: Raise power "
12862 "request failed.", mpt->m_instance);
12863 (void) pm_idle_component(mpt->m_dip, 0);
12864 return (ENXIO);
12865 }
12866 } else {
12867 mutex_exit(&mpt->m_mutex);
12868 }
12869 } else {
12870 mutex_exit(&mpt->m_mutex);
12871 }
12872
12873 if (iport_flag) {
12874 status = scsi_hba_ioctl(dev, cmd, data, mode, credp, rval);
12875 if (status != 0) {
12876 goto out;
12877 }
12878 /*
12879 * The following code control the OK2RM LED, it doesn't affect
12880 * the ioctl return status.
12881 */
12882 if ((cmd == DEVCTL_DEVICE_ONLINE) ||
12883 (cmd == DEVCTL_DEVICE_OFFLINE)) {
12884 if (ndi_dc_allochdl((void *)data, &dcp) !=
12885 NDI_SUCCESS) {
12886 goto out;
12887 }
12888 addr = ndi_dc_getaddr(dcp);
12889 ptgt = mptsas_addr_to_ptgt(mpt, addr, phymask);
12890 if (ptgt == NULL) {
12891 NDBG14(("mptsas_ioctl led control: tgt %s not "
12892 "found", addr));
12893 ndi_dc_freehdl(dcp);
12894 goto out;
12895 }
12896 ndi_dc_freehdl(dcp);
12897 }
12898 goto out;
12899 }
12900 switch (cmd) {
12901 case MPTIOCTL_GET_DISK_INFO:
12902 status = get_disk_info(mpt, data, mode);
12903 break;
12904 case MPTIOCTL_LED_CONTROL:
12905 status = led_control(mpt, data, mode);
12906 break;
12907 case MPTIOCTL_UPDATE_FLASH:
12908 if (ddi_copyin((void *)data, &flashdata,
12909 sizeof (struct mptsas_update_flash), mode)) {
12910 status = EFAULT;
12911 break;
12912 }
12913
12914 mutex_enter(&mpt->m_mutex);
12915 if (mptsas_update_flash(mpt,
12916 (caddr_t)(long)flashdata.PtrBuffer,
12917 flashdata.ImageSize, flashdata.ImageType, mode)) {
12918 status = EFAULT;
12919 }
12920
12921 /*
12922 * Reset the chip to start using the new
12923 * firmware. Reset if failed also.
12924 */
12925 mpt->m_softstate &= ~MPTSAS_SS_MSG_UNIT_RESET;
12926 if (mptsas_restart_ioc(mpt) == DDI_FAILURE) {
12927 status = EFAULT;
12928 }
12929 mutex_exit(&mpt->m_mutex);
12930 break;
12931 case MPTIOCTL_PASS_THRU:
12932 /*
12933 * The user has requested to pass through a command to
12934 * be executed by the MPT firmware. Call our routine
12935 * which does this. Only allow one passthru IOCTL at
12936 * one time. Other threads will block on
12937 * m_passthru_mutex, which is of adaptive variant.
12938 */
12939 if (ddi_copyin((void *)data, &passthru_data,
12940 sizeof (mptsas_pass_thru_t), mode)) {
12941 status = EFAULT;
12942 break;
12943 }
12944 mutex_enter(&mpt->m_passthru_mutex);
12945 mutex_enter(&mpt->m_mutex);
12946 status = mptsas_pass_thru(mpt, &passthru_data, mode);
12947 mutex_exit(&mpt->m_mutex);
12948 mutex_exit(&mpt->m_passthru_mutex);
12949
12950 break;
12951 case MPTIOCTL_GET_ADAPTER_DATA:
12952 /*
12953 * The user has requested to read adapter data. Call
12954 * our routine which does this.
12955 */
12956 bzero(&adapter_data, sizeof (mptsas_adapter_data_t));
12957 if (ddi_copyin((void *)data, (void *)&adapter_data,
12958 sizeof (mptsas_adapter_data_t), mode)) {
12959 status = EFAULT;
12960 break;
12961 }
12962 if (adapter_data.StructureLength >=
12963 sizeof (mptsas_adapter_data_t)) {
12964 adapter_data.StructureLength = (uint32_t)
12965 sizeof (mptsas_adapter_data_t);
12966 copylen = sizeof (mptsas_adapter_data_t);
12967 mutex_enter(&mpt->m_mutex);
12968 mptsas_read_adapter_data(mpt, &adapter_data);
12969 mutex_exit(&mpt->m_mutex);
12970 } else {
12971 adapter_data.StructureLength = (uint32_t)
12972 sizeof (mptsas_adapter_data_t);
12973 copylen = sizeof (adapter_data.StructureLength);
12974 *rval = MPTIOCTL_STATUS_LEN_TOO_SHORT;
12975 }
12976 if (ddi_copyout((void *)(&adapter_data), (void *)data,
12977 copylen, mode) != 0) {
12978 status = EFAULT;
12979 }
12980 break;
12981 case MPTIOCTL_GET_PCI_INFO:
12982 /*
12983 * The user has requested to read pci info. Call
12984 * our routine which does this.
12985 */
12986 bzero(&pci_info, sizeof (mptsas_pci_info_t));
12987 mutex_enter(&mpt->m_mutex);
12988 mptsas_read_pci_info(mpt, &pci_info);
12989 mutex_exit(&mpt->m_mutex);
12990 if (ddi_copyout((void *)(&pci_info), (void *)data,
12991 sizeof (mptsas_pci_info_t), mode) != 0) {
12992 status = EFAULT;
12993 }
12994 break;
12995 case MPTIOCTL_RESET_ADAPTER:
12996 mutex_enter(&mpt->m_mutex);
12997 mpt->m_softstate &= ~MPTSAS_SS_MSG_UNIT_RESET;
12998 if ((mptsas_restart_ioc(mpt)) == DDI_FAILURE) {
12999 mptsas_log(mpt, CE_WARN, "reset adapter IOCTL "
13000 "failed");
13001 status = EFAULT;
13002 }
13003 mutex_exit(&mpt->m_mutex);
13004 break;
13005 case MPTIOCTL_DIAG_ACTION:
13006 /*
13007 * The user has done a diag buffer action. Call our
13008 * routine which does this. Only allow one diag action
13009 * at one time.
13010 */
13011 mutex_enter(&mpt->m_mutex);
13012 if (mpt->m_diag_action_in_progress) {
13013 mutex_exit(&mpt->m_mutex);
13014 return (EBUSY);
13015 }
13016 mpt->m_diag_action_in_progress = 1;
13017 status = mptsas_diag_action(mpt,
13018 (mptsas_diag_action_t *)data, mode);
13019 mpt->m_diag_action_in_progress = 0;
13020 mutex_exit(&mpt->m_mutex);
13021 break;
13022 case MPTIOCTL_EVENT_QUERY:
13023 /*
13024 * The user has done an event query. Call our routine
13025 * which does this.
13026 */
13027 status = mptsas_event_query(mpt,
13028 (mptsas_event_query_t *)data, mode, rval);
13029 break;
13030 case MPTIOCTL_EVENT_ENABLE:
13031 /*
13032 * The user has done an event enable. Call our routine
13033 * which does this.
13034 */
13035 status = mptsas_event_enable(mpt,
13036 (mptsas_event_enable_t *)data, mode, rval);
13037 break;
13038 case MPTIOCTL_EVENT_REPORT:
13039 /*
13040 * The user has done an event report. Call our routine
13041 * which does this.
13042 */
13043 status = mptsas_event_report(mpt,
13044 (mptsas_event_report_t *)data, mode, rval);
13045 break;
13046 case MPTIOCTL_REG_ACCESS:
13047 /*
13048 * The user has requested register access. Call our
13049 * routine which does this.
13050 */
13051 status = mptsas_reg_access(mpt,
13052 (mptsas_reg_access_t *)data, mode);
13053 break;
13054 default:
13055 status = scsi_hba_ioctl(dev, cmd, data, mode, credp,
13056 rval);
13057 break;
13058 }
13059
13060 out:
13061 return (status);
13062 }
13063
13064 int
mptsas_restart_ioc(mptsas_t * mpt)13065 mptsas_restart_ioc(mptsas_t *mpt)
13066 {
13067 int rval = DDI_SUCCESS;
13068 mptsas_target_t *ptgt = NULL;
13069
13070 ASSERT(mutex_owned(&mpt->m_mutex));
13071
13072 /*
13073 * Set a flag telling I/O path that we're processing a reset. This is
13074 * needed because after the reset is complete, the hash table still
13075 * needs to be rebuilt. If I/Os are started before the hash table is
13076 * rebuilt, I/O errors will occur. This flag allows I/Os to be marked
13077 * so that they can be retried.
13078 */
13079 mpt->m_in_reset = TRUE;
13080
13081 /*
13082 * Wait until all the allocated sense data buffers for DMA are freed.
13083 */
13084 while (mpt->m_extreq_sense_refcount > 0)
13085 cv_wait(&mpt->m_extreq_sense_refcount_cv, &mpt->m_mutex);
13086
13087 /*
13088 * Set all throttles to HOLD
13089 */
13090 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
13091 ptgt = refhash_next(mpt->m_targets, ptgt)) {
13092 mptsas_set_throttle(mpt, ptgt, HOLD_THROTTLE);
13093 }
13094
13095 /*
13096 * Disable interrupts
13097 */
13098 MPTSAS_DISABLE_INTR(mpt);
13099
13100 /*
13101 * Abort all commands: outstanding commands, commands in waitq and
13102 * tx_waitq.
13103 */
13104 mptsas_flush_hba(mpt);
13105
13106 /*
13107 * Reinitialize the chip.
13108 */
13109 if (mptsas_init_chip(mpt, FALSE) == DDI_FAILURE) {
13110 rval = DDI_FAILURE;
13111 }
13112
13113 /*
13114 * Enable interrupts again
13115 */
13116 MPTSAS_ENABLE_INTR(mpt);
13117
13118 /*
13119 * If mptsas_init_chip was successful, update the driver data.
13120 */
13121 if (rval == DDI_SUCCESS) {
13122 mptsas_update_driver_data(mpt);
13123 }
13124
13125 /*
13126 * Reset the throttles
13127 */
13128 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
13129 ptgt = refhash_next(mpt->m_targets, ptgt)) {
13130 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE);
13131 }
13132
13133 mptsas_doneq_empty(mpt);
13134 mptsas_restart_hba(mpt);
13135
13136 if (rval != DDI_SUCCESS) {
13137 mptsas_fm_ereport(mpt, DDI_FM_DEVICE_NO_RESPONSE);
13138 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_LOST);
13139 }
13140
13141 /*
13142 * Clear the reset flag so that I/Os can continue.
13143 */
13144 mpt->m_in_reset = FALSE;
13145
13146 return (rval);
13147 }
13148
13149 static int
mptsas_init_chip(mptsas_t * mpt,int first_time)13150 mptsas_init_chip(mptsas_t *mpt, int first_time)
13151 {
13152 ddi_dma_cookie_t cookie;
13153 uint32_t i;
13154 int rval;
13155
13156 /*
13157 * Check to see if the firmware image is valid
13158 */
13159 if (ddi_get32(mpt->m_datap, &mpt->m_reg->HostDiagnostic) &
13160 MPI2_DIAG_FLASH_BAD_SIG) {
13161 mptsas_log(mpt, CE_WARN, "mptsas bad flash signature!");
13162 goto fail;
13163 }
13164
13165 /*
13166 * Reset the chip
13167 */
13168 rval = mptsas_ioc_reset(mpt, first_time);
13169 if (rval == MPTSAS_RESET_FAIL) {
13170 mptsas_log(mpt, CE_WARN, "hard reset failed!");
13171 goto fail;
13172 }
13173
13174 if ((rval == MPTSAS_SUCCESS_MUR) && (!first_time)) {
13175 goto mur;
13176 }
13177 /*
13178 * Setup configuration space
13179 */
13180 if (mptsas_config_space_init(mpt) == FALSE) {
13181 mptsas_log(mpt, CE_WARN, "mptsas_config_space_init "
13182 "failed!");
13183 goto fail;
13184 }
13185
13186 /*
13187 * IOC facts can change after a diag reset so all buffers that are
13188 * based on these numbers must be de-allocated and re-allocated. Get
13189 * new IOC facts each time chip is initialized.
13190 */
13191 if (mptsas_ioc_get_facts(mpt) == DDI_FAILURE) {
13192 mptsas_log(mpt, CE_WARN, "mptsas_ioc_get_facts failed");
13193 goto fail;
13194 }
13195
13196 if (mptsas_alloc_active_slots(mpt, KM_SLEEP)) {
13197 goto fail;
13198 }
13199 /*
13200 * Allocate request message frames, reply free queue, reply descriptor
13201 * post queue, and reply message frames using latest IOC facts.
13202 */
13203 if (mptsas_alloc_request_frames(mpt) == DDI_FAILURE) {
13204 mptsas_log(mpt, CE_WARN, "mptsas_alloc_request_frames failed");
13205 goto fail;
13206 }
13207 if (mptsas_alloc_sense_bufs(mpt) == DDI_FAILURE) {
13208 mptsas_log(mpt, CE_WARN, "mptsas_alloc_sense_bufs failed");
13209 goto fail;
13210 }
13211 if (mptsas_alloc_free_queue(mpt) == DDI_FAILURE) {
13212 mptsas_log(mpt, CE_WARN, "mptsas_alloc_free_queue failed!");
13213 goto fail;
13214 }
13215 if (mptsas_alloc_post_queue(mpt) == DDI_FAILURE) {
13216 mptsas_log(mpt, CE_WARN, "mptsas_alloc_post_queue failed!");
13217 goto fail;
13218 }
13219 if (mptsas_alloc_reply_frames(mpt) == DDI_FAILURE) {
13220 mptsas_log(mpt, CE_WARN, "mptsas_alloc_reply_frames failed!");
13221 goto fail;
13222 }
13223
13224 mur:
13225 /*
13226 * Re-Initialize ioc to operational state
13227 */
13228 if (mptsas_ioc_init(mpt) == DDI_FAILURE) {
13229 mptsas_log(mpt, CE_WARN, "mptsas_ioc_init failed");
13230 goto fail;
13231 }
13232
13233 mptsas_alloc_reply_args(mpt);
13234
13235 /*
13236 * Initialize reply post index. Reply free index is initialized after
13237 * the next loop.
13238 */
13239 mpt->m_post_index = 0;
13240
13241 /*
13242 * Initialize the Reply Free Queue with the physical addresses of our
13243 * reply frames.
13244 */
13245 cookie.dmac_address = mpt->m_reply_frame_dma_addr & 0xffffffffu;
13246 for (i = 0; i < mpt->m_max_replies; i++) {
13247 ddi_put32(mpt->m_acc_free_queue_hdl,
13248 &((uint32_t *)(void *)mpt->m_free_queue)[i],
13249 cookie.dmac_address);
13250 cookie.dmac_address += mpt->m_reply_frame_size;
13251 }
13252 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0,
13253 DDI_DMA_SYNC_FORDEV);
13254
13255 /*
13256 * Initialize the reply free index to one past the last frame on the
13257 * queue. This will signify that the queue is empty to start with.
13258 */
13259 mpt->m_free_index = i;
13260 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex, i);
13261
13262 /*
13263 * Initialize the reply post queue to 0xFFFFFFFF,0xFFFFFFFF's.
13264 */
13265 for (i = 0; i < mpt->m_post_queue_depth; i++) {
13266 ddi_put64(mpt->m_acc_post_queue_hdl,
13267 &((uint64_t *)(void *)mpt->m_post_queue)[i],
13268 0xFFFFFFFFFFFFFFFF);
13269 }
13270 (void) ddi_dma_sync(mpt->m_dma_post_queue_hdl, 0, 0,
13271 DDI_DMA_SYNC_FORDEV);
13272
13273 /*
13274 * Enable ports
13275 */
13276 if (mptsas_ioc_enable_port(mpt) == DDI_FAILURE) {
13277 mptsas_log(mpt, CE_WARN, "mptsas_ioc_enable_port failed");
13278 goto fail;
13279 }
13280
13281 /*
13282 * enable events
13283 */
13284 if (mptsas_ioc_enable_event_notification(mpt)) {
13285 mptsas_log(mpt, CE_WARN,
13286 "mptsas_ioc_enable_event_notification failed");
13287 goto fail;
13288 }
13289
13290 /*
13291 * We need checks in attach and these.
13292 * chip_init is called in mult. places
13293 */
13294
13295 if ((mptsas_check_dma_handle(mpt->m_dma_req_frame_hdl) !=
13296 DDI_SUCCESS) ||
13297 (mptsas_check_dma_handle(mpt->m_dma_req_sense_hdl) !=
13298 DDI_SUCCESS) ||
13299 (mptsas_check_dma_handle(mpt->m_dma_reply_frame_hdl) !=
13300 DDI_SUCCESS) ||
13301 (mptsas_check_dma_handle(mpt->m_dma_free_queue_hdl) !=
13302 DDI_SUCCESS) ||
13303 (mptsas_check_dma_handle(mpt->m_dma_post_queue_hdl) !=
13304 DDI_SUCCESS) ||
13305 (mptsas_check_dma_handle(mpt->m_hshk_dma_hdl) !=
13306 DDI_SUCCESS)) {
13307 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
13308 goto fail;
13309 }
13310
13311 /* Check all acc handles */
13312 if ((mptsas_check_acc_handle(mpt->m_datap) != DDI_SUCCESS) ||
13313 (mptsas_check_acc_handle(mpt->m_acc_req_frame_hdl) !=
13314 DDI_SUCCESS) ||
13315 (mptsas_check_acc_handle(mpt->m_acc_req_sense_hdl) !=
13316 DDI_SUCCESS) ||
13317 (mptsas_check_acc_handle(mpt->m_acc_reply_frame_hdl) !=
13318 DDI_SUCCESS) ||
13319 (mptsas_check_acc_handle(mpt->m_acc_free_queue_hdl) !=
13320 DDI_SUCCESS) ||
13321 (mptsas_check_acc_handle(mpt->m_acc_post_queue_hdl) !=
13322 DDI_SUCCESS) ||
13323 (mptsas_check_acc_handle(mpt->m_hshk_acc_hdl) !=
13324 DDI_SUCCESS) ||
13325 (mptsas_check_acc_handle(mpt->m_config_handle) !=
13326 DDI_SUCCESS)) {
13327 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
13328 goto fail;
13329 }
13330
13331 return (DDI_SUCCESS);
13332
13333 fail:
13334 return (DDI_FAILURE);
13335 }
13336
13337 static int
mptsas_get_pci_cap(mptsas_t * mpt)13338 mptsas_get_pci_cap(mptsas_t *mpt)
13339 {
13340 ushort_t caps_ptr, cap, cap_count;
13341
13342 if (mpt->m_config_handle == NULL)
13343 return (FALSE);
13344 /*
13345 * Check if capabilities list is supported and if so,
13346 * get initial capabilities pointer and clear bits 0,1.
13347 */
13348 if (pci_config_get16(mpt->m_config_handle, PCI_CONF_STAT)
13349 & PCI_STAT_CAP) {
13350 caps_ptr = P2ALIGN(pci_config_get8(mpt->m_config_handle,
13351 PCI_CONF_CAP_PTR), 4);
13352 } else {
13353 caps_ptr = PCI_CAP_NEXT_PTR_NULL;
13354 }
13355
13356 /*
13357 * Walk capabilities if supported.
13358 */
13359 for (cap_count = 0; caps_ptr != PCI_CAP_NEXT_PTR_NULL; ) {
13360
13361 /*
13362 * Check that we haven't exceeded the maximum number of
13363 * capabilities and that the pointer is in a valid range.
13364 */
13365 if (++cap_count > 48) {
13366 mptsas_log(mpt, CE_WARN,
13367 "too many device capabilities.\n");
13368 break;
13369 }
13370 if (caps_ptr < 64) {
13371 mptsas_log(mpt, CE_WARN,
13372 "capabilities pointer 0x%x out of range.\n",
13373 caps_ptr);
13374 break;
13375 }
13376
13377 /*
13378 * Get next capability and check that it is valid.
13379 * For now, we only support power management.
13380 */
13381 cap = pci_config_get8(mpt->m_config_handle, caps_ptr);
13382 switch (cap) {
13383 case PCI_CAP_ID_PM:
13384 mptsas_log(mpt, CE_NOTE,
13385 "?mptsas%d supports power management.\n",
13386 mpt->m_instance);
13387 mpt->m_options |= MPTSAS_OPT_PM;
13388
13389 /* Save PMCSR offset */
13390 mpt->m_pmcsr_offset = caps_ptr + PCI_PMCSR;
13391 break;
13392 /*
13393 * The following capabilities are valid. Any others
13394 * will cause a message to be logged.
13395 */
13396 case PCI_CAP_ID_VPD:
13397 case PCI_CAP_ID_MSI:
13398 case PCI_CAP_ID_PCIX:
13399 case PCI_CAP_ID_PCI_E:
13400 case PCI_CAP_ID_MSI_X:
13401 break;
13402 default:
13403 mptsas_log(mpt, CE_NOTE,
13404 "?mptsas%d unrecognized capability "
13405 "0x%x.\n", mpt->m_instance, cap);
13406 break;
13407 }
13408
13409 /*
13410 * Get next capabilities pointer and clear bits 0,1.
13411 */
13412 caps_ptr = P2ALIGN(pci_config_get8(mpt->m_config_handle,
13413 (caps_ptr + PCI_CAP_NEXT_PTR)), 4);
13414 }
13415 return (TRUE);
13416 }
13417
13418 static int
mptsas_init_pm(mptsas_t * mpt)13419 mptsas_init_pm(mptsas_t *mpt)
13420 {
13421 char pmc_name[16];
13422 char *pmc[] = {
13423 NULL,
13424 "0=Off (PCI D3 State)",
13425 "3=On (PCI D0 State)",
13426 NULL
13427 };
13428 uint16_t pmcsr_stat;
13429
13430 if (mptsas_get_pci_cap(mpt) == FALSE) {
13431 return (DDI_FAILURE);
13432 }
13433 /*
13434 * If PCI's capability does not support PM, then don't need
13435 * to registe the pm-components
13436 */
13437 if (!(mpt->m_options & MPTSAS_OPT_PM))
13438 return (DDI_SUCCESS);
13439 /*
13440 * If power management is supported by this chip, create
13441 * pm-components property for the power management framework
13442 */
13443 (void) sprintf(pmc_name, "NAME=mptsas%d", mpt->m_instance);
13444 pmc[0] = pmc_name;
13445 if (ddi_prop_update_string_array(DDI_DEV_T_NONE, mpt->m_dip,
13446 "pm-components", pmc, 3) != DDI_PROP_SUCCESS) {
13447 mpt->m_options &= ~MPTSAS_OPT_PM;
13448 mptsas_log(mpt, CE_WARN,
13449 "mptsas%d: pm-component property creation failed.",
13450 mpt->m_instance);
13451 return (DDI_FAILURE);
13452 }
13453
13454 /*
13455 * Power on device.
13456 */
13457 (void) pm_busy_component(mpt->m_dip, 0);
13458 pmcsr_stat = pci_config_get16(mpt->m_config_handle,
13459 mpt->m_pmcsr_offset);
13460 if ((pmcsr_stat & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_D0) {
13461 mptsas_log(mpt, CE_WARN, "mptsas%d: Power up the device",
13462 mpt->m_instance);
13463 pci_config_put16(mpt->m_config_handle, mpt->m_pmcsr_offset,
13464 PCI_PMCSR_D0);
13465 }
13466 if (pm_power_has_changed(mpt->m_dip, 0, PM_LEVEL_D0) != DDI_SUCCESS) {
13467 mptsas_log(mpt, CE_WARN, "pm_power_has_changed failed");
13468 return (DDI_FAILURE);
13469 }
13470 mpt->m_power_level = PM_LEVEL_D0;
13471 /*
13472 * Set pm idle delay.
13473 */
13474 mpt->m_pm_idle_delay = ddi_prop_get_int(DDI_DEV_T_ANY,
13475 mpt->m_dip, 0, "mptsas-pm-idle-delay", MPTSAS_PM_IDLE_TIMEOUT);
13476
13477 return (DDI_SUCCESS);
13478 }
13479
13480 static int
mptsas_register_intrs(mptsas_t * mpt)13481 mptsas_register_intrs(mptsas_t *mpt)
13482 {
13483 dev_info_t *dip;
13484 int intr_types;
13485
13486 dip = mpt->m_dip;
13487
13488 /* Get supported interrupt types */
13489 if (ddi_intr_get_supported_types(dip, &intr_types) != DDI_SUCCESS) {
13490 mptsas_log(mpt, CE_WARN, "ddi_intr_get_supported_types "
13491 "failed\n");
13492 return (FALSE);
13493 }
13494
13495 NDBG6(("ddi_intr_get_supported_types() returned: 0x%x", intr_types));
13496
13497 /*
13498 * Try MSI, but fall back to FIXED
13499 */
13500 if (mptsas_enable_msi && (intr_types & DDI_INTR_TYPE_MSI)) {
13501 if (mptsas_add_intrs(mpt, DDI_INTR_TYPE_MSI) == DDI_SUCCESS) {
13502 NDBG0(("Using MSI interrupt type"));
13503 mpt->m_intr_type = DDI_INTR_TYPE_MSI;
13504 return (TRUE);
13505 }
13506 }
13507 if (intr_types & DDI_INTR_TYPE_FIXED) {
13508 if (mptsas_add_intrs(mpt, DDI_INTR_TYPE_FIXED) == DDI_SUCCESS) {
13509 NDBG0(("Using FIXED interrupt type"));
13510 mpt->m_intr_type = DDI_INTR_TYPE_FIXED;
13511 return (TRUE);
13512 } else {
13513 NDBG0(("FIXED interrupt registration failed"));
13514 return (FALSE);
13515 }
13516 }
13517
13518 return (FALSE);
13519 }
13520
13521 static void
mptsas_unregister_intrs(mptsas_t * mpt)13522 mptsas_unregister_intrs(mptsas_t *mpt)
13523 {
13524 mptsas_rem_intrs(mpt);
13525 }
13526
13527 /*
13528 * mptsas_add_intrs:
13529 *
13530 * Register FIXED or MSI interrupts.
13531 */
13532 static int
mptsas_add_intrs(mptsas_t * mpt,int intr_type)13533 mptsas_add_intrs(mptsas_t *mpt, int intr_type)
13534 {
13535 dev_info_t *dip = mpt->m_dip;
13536 int avail, actual, count = 0;
13537 int i, flag, ret;
13538
13539 NDBG6(("mptsas_add_intrs:interrupt type 0x%x", intr_type));
13540
13541 /* Get number of interrupts */
13542 ret = ddi_intr_get_nintrs(dip, intr_type, &count);
13543 if ((ret != DDI_SUCCESS) || (count <= 0)) {
13544 mptsas_log(mpt, CE_WARN, "ddi_intr_get_nintrs() failed, "
13545 "ret %d count %d\n", ret, count);
13546
13547 return (DDI_FAILURE);
13548 }
13549
13550 /* Get number of available interrupts */
13551 ret = ddi_intr_get_navail(dip, intr_type, &avail);
13552 if ((ret != DDI_SUCCESS) || (avail == 0)) {
13553 mptsas_log(mpt, CE_WARN, "ddi_intr_get_navail() failed, "
13554 "ret %d avail %d\n", ret, avail);
13555
13556 return (DDI_FAILURE);
13557 }
13558
13559 if (avail < count) {
13560 mptsas_log(mpt, CE_NOTE, "ddi_intr_get_nvail returned %d, "
13561 "navail() returned %d", count, avail);
13562 }
13563
13564 /* Mpt only have one interrupt routine */
13565 if ((intr_type == DDI_INTR_TYPE_MSI) && (count > 1)) {
13566 count = 1;
13567 }
13568
13569 /* Allocate an array of interrupt handles */
13570 mpt->m_intr_size = count * sizeof (ddi_intr_handle_t);
13571 mpt->m_htable = kmem_alloc(mpt->m_intr_size, KM_SLEEP);
13572
13573 flag = DDI_INTR_ALLOC_NORMAL;
13574
13575 /* call ddi_intr_alloc() */
13576 ret = ddi_intr_alloc(dip, mpt->m_htable, intr_type, 0,
13577 count, &actual, flag);
13578
13579 if ((ret != DDI_SUCCESS) || (actual == 0)) {
13580 mptsas_log(mpt, CE_WARN, "ddi_intr_alloc() failed, ret %d\n",
13581 ret);
13582 kmem_free(mpt->m_htable, mpt->m_intr_size);
13583 return (DDI_FAILURE);
13584 }
13585
13586 /* use interrupt count returned or abort? */
13587 if (actual < count) {
13588 mptsas_log(mpt, CE_NOTE, "Requested: %d, Received: %d\n",
13589 count, actual);
13590 }
13591
13592 mpt->m_intr_cnt = actual;
13593
13594 /*
13595 * Get priority for first msi, assume remaining are all the same
13596 */
13597 if ((ret = ddi_intr_get_pri(mpt->m_htable[0],
13598 &mpt->m_intr_pri)) != DDI_SUCCESS) {
13599 mptsas_log(mpt, CE_WARN, "ddi_intr_get_pri() failed %d\n", ret);
13600
13601 /* Free already allocated intr */
13602 for (i = 0; i < actual; i++) {
13603 (void) ddi_intr_free(mpt->m_htable[i]);
13604 }
13605
13606 kmem_free(mpt->m_htable, mpt->m_intr_size);
13607 return (DDI_FAILURE);
13608 }
13609
13610 /* Test for high level mutex */
13611 if (mpt->m_intr_pri >= ddi_intr_get_hilevel_pri()) {
13612 mptsas_log(mpt, CE_WARN, "mptsas_add_intrs: "
13613 "Hi level interrupt not supported\n");
13614
13615 /* Free already allocated intr */
13616 for (i = 0; i < actual; i++) {
13617 (void) ddi_intr_free(mpt->m_htable[i]);
13618 }
13619
13620 kmem_free(mpt->m_htable, mpt->m_intr_size);
13621 return (DDI_FAILURE);
13622 }
13623
13624 /* Call ddi_intr_add_handler() */
13625 for (i = 0; i < actual; i++) {
13626 if ((ret = ddi_intr_add_handler(mpt->m_htable[i], mptsas_intr,
13627 (caddr_t)mpt, (caddr_t)(uintptr_t)i)) != DDI_SUCCESS) {
13628 mptsas_log(mpt, CE_WARN, "ddi_intr_add_handler() "
13629 "failed %d\n", ret);
13630
13631 /* Free already allocated intr */
13632 for (i = 0; i < actual; i++) {
13633 (void) ddi_intr_free(mpt->m_htable[i]);
13634 }
13635
13636 kmem_free(mpt->m_htable, mpt->m_intr_size);
13637 return (DDI_FAILURE);
13638 }
13639 }
13640
13641 if ((ret = ddi_intr_get_cap(mpt->m_htable[0], &mpt->m_intr_cap))
13642 != DDI_SUCCESS) {
13643 mptsas_log(mpt, CE_WARN, "ddi_intr_get_cap() failed %d\n", ret);
13644
13645 /* Free already allocated intr */
13646 for (i = 0; i < actual; i++) {
13647 (void) ddi_intr_free(mpt->m_htable[i]);
13648 }
13649
13650 kmem_free(mpt->m_htable, mpt->m_intr_size);
13651 return (DDI_FAILURE);
13652 }
13653
13654 /*
13655 * Enable interrupts
13656 */
13657 if (mpt->m_intr_cap & DDI_INTR_FLAG_BLOCK) {
13658 /* Call ddi_intr_block_enable() for MSI interrupts */
13659 (void) ddi_intr_block_enable(mpt->m_htable, mpt->m_intr_cnt);
13660 } else {
13661 /* Call ddi_intr_enable for MSI or FIXED interrupts */
13662 for (i = 0; i < mpt->m_intr_cnt; i++) {
13663 (void) ddi_intr_enable(mpt->m_htable[i]);
13664 }
13665 }
13666 return (DDI_SUCCESS);
13667 }
13668
13669 /*
13670 * mptsas_rem_intrs:
13671 *
13672 * Unregister FIXED or MSI interrupts
13673 */
13674 static void
mptsas_rem_intrs(mptsas_t * mpt)13675 mptsas_rem_intrs(mptsas_t *mpt)
13676 {
13677 int i;
13678
13679 NDBG6(("mptsas_rem_intrs"));
13680
13681 /* Disable all interrupts */
13682 if (mpt->m_intr_cap & DDI_INTR_FLAG_BLOCK) {
13683 /* Call ddi_intr_block_disable() */
13684 (void) ddi_intr_block_disable(mpt->m_htable, mpt->m_intr_cnt);
13685 } else {
13686 for (i = 0; i < mpt->m_intr_cnt; i++) {
13687 (void) ddi_intr_disable(mpt->m_htable[i]);
13688 }
13689 }
13690
13691 /* Call ddi_intr_remove_handler() */
13692 for (i = 0; i < mpt->m_intr_cnt; i++) {
13693 (void) ddi_intr_remove_handler(mpt->m_htable[i]);
13694 (void) ddi_intr_free(mpt->m_htable[i]);
13695 }
13696
13697 kmem_free(mpt->m_htable, mpt->m_intr_size);
13698 }
13699
13700 /*
13701 * The IO fault service error handling callback function
13702 */
13703 /*ARGSUSED*/
13704 static int
mptsas_fm_error_cb(dev_info_t * dip,ddi_fm_error_t * err,const void * impl_data)13705 mptsas_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data)
13706 {
13707 /*
13708 * as the driver can always deal with an error in any dma or
13709 * access handle, we can just return the fme_status value.
13710 */
13711 pci_ereport_post(dip, err, NULL);
13712 return (err->fme_status);
13713 }
13714
13715 /*
13716 * mptsas_fm_init - initialize fma capabilities and register with IO
13717 * fault services.
13718 */
13719 static void
mptsas_fm_init(mptsas_t * mpt)13720 mptsas_fm_init(mptsas_t *mpt)
13721 {
13722 /*
13723 * Need to change iblock to priority for new MSI intr
13724 */
13725 ddi_iblock_cookie_t fm_ibc;
13726
13727 /* Only register with IO Fault Services if we have some capability */
13728 if (mpt->m_fm_capabilities) {
13729 /* Adjust access and dma attributes for FMA */
13730 mpt->m_reg_acc_attr.devacc_attr_access = DDI_FLAGERR_ACC;
13731 mpt->m_msg_dma_attr.dma_attr_flags |= DDI_DMA_FLAGERR;
13732 mpt->m_io_dma_attr.dma_attr_flags |= DDI_DMA_FLAGERR;
13733
13734 /*
13735 * Register capabilities with IO Fault Services.
13736 * mpt->m_fm_capabilities will be updated to indicate
13737 * capabilities actually supported (not requested.)
13738 */
13739 ddi_fm_init(mpt->m_dip, &mpt->m_fm_capabilities, &fm_ibc);
13740
13741 /*
13742 * Initialize pci ereport capabilities if ereport
13743 * capable (should always be.)
13744 */
13745 if (DDI_FM_EREPORT_CAP(mpt->m_fm_capabilities) ||
13746 DDI_FM_ERRCB_CAP(mpt->m_fm_capabilities)) {
13747 pci_ereport_setup(mpt->m_dip);
13748 }
13749
13750 /*
13751 * Register error callback if error callback capable.
13752 */
13753 if (DDI_FM_ERRCB_CAP(mpt->m_fm_capabilities)) {
13754 ddi_fm_handler_register(mpt->m_dip,
13755 mptsas_fm_error_cb, (void *) mpt);
13756 }
13757 }
13758 }
13759
13760 /*
13761 * mptsas_fm_fini - Releases fma capabilities and un-registers with IO
13762 * fault services.
13763 *
13764 */
13765 static void
mptsas_fm_fini(mptsas_t * mpt)13766 mptsas_fm_fini(mptsas_t *mpt)
13767 {
13768 /* Only unregister FMA capabilities if registered */
13769 if (mpt->m_fm_capabilities) {
13770
13771 /*
13772 * Un-register error callback if error callback capable.
13773 */
13774
13775 if (DDI_FM_ERRCB_CAP(mpt->m_fm_capabilities)) {
13776 ddi_fm_handler_unregister(mpt->m_dip);
13777 }
13778
13779 /*
13780 * Release any resources allocated by pci_ereport_setup()
13781 */
13782
13783 if (DDI_FM_EREPORT_CAP(mpt->m_fm_capabilities) ||
13784 DDI_FM_ERRCB_CAP(mpt->m_fm_capabilities)) {
13785 pci_ereport_teardown(mpt->m_dip);
13786 }
13787
13788 /* Unregister from IO Fault Services */
13789 ddi_fm_fini(mpt->m_dip);
13790
13791 /* Adjust access and dma attributes for FMA */
13792 mpt->m_reg_acc_attr.devacc_attr_access = DDI_DEFAULT_ACC;
13793 mpt->m_msg_dma_attr.dma_attr_flags &= ~DDI_DMA_FLAGERR;
13794 mpt->m_io_dma_attr.dma_attr_flags &= ~DDI_DMA_FLAGERR;
13795
13796 }
13797 }
13798
13799 int
mptsas_check_acc_handle(ddi_acc_handle_t handle)13800 mptsas_check_acc_handle(ddi_acc_handle_t handle)
13801 {
13802 ddi_fm_error_t de;
13803
13804 if (handle == NULL)
13805 return (DDI_FAILURE);
13806 ddi_fm_acc_err_get(handle, &de, DDI_FME_VER0);
13807 return (de.fme_status);
13808 }
13809
13810 int
mptsas_check_dma_handle(ddi_dma_handle_t handle)13811 mptsas_check_dma_handle(ddi_dma_handle_t handle)
13812 {
13813 ddi_fm_error_t de;
13814
13815 if (handle == NULL)
13816 return (DDI_FAILURE);
13817 ddi_fm_dma_err_get(handle, &de, DDI_FME_VER0);
13818 return (de.fme_status);
13819 }
13820
13821 void
mptsas_fm_ereport(mptsas_t * mpt,char * detail)13822 mptsas_fm_ereport(mptsas_t *mpt, char *detail)
13823 {
13824 uint64_t ena;
13825 char buf[FM_MAX_CLASS];
13826
13827 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", DDI_FM_DEVICE, detail);
13828 ena = fm_ena_generate(0, FM_ENA_FMT1);
13829 if (DDI_FM_EREPORT_CAP(mpt->m_fm_capabilities)) {
13830 ddi_fm_ereport_post(mpt->m_dip, buf, ena, DDI_NOSLEEP,
13831 FM_VERSION, DATA_TYPE_UINT8, FM_EREPORT_VERS0, NULL);
13832 }
13833 }
13834
13835 static int
mptsas_get_target_device_info(mptsas_t * mpt,uint32_t page_address,uint16_t * dev_handle,mptsas_target_t ** pptgt)13836 mptsas_get_target_device_info(mptsas_t *mpt, uint32_t page_address,
13837 uint16_t *dev_handle, mptsas_target_t **pptgt)
13838 {
13839 int rval;
13840 uint32_t dev_info;
13841 uint64_t sas_wwn;
13842 mptsas_phymask_t phymask;
13843 uint8_t physport, phynum, config, disk;
13844 uint64_t devicename;
13845 uint16_t pdev_hdl;
13846 mptsas_target_t *tmp_tgt = NULL;
13847 uint16_t bay_num, enclosure, io_flags;
13848
13849 ASSERT(*pptgt == NULL);
13850
13851 rval = mptsas_get_sas_device_page0(mpt, page_address, dev_handle,
13852 &sas_wwn, &dev_info, &physport, &phynum, &pdev_hdl,
13853 &bay_num, &enclosure, &io_flags);
13854 if (rval != DDI_SUCCESS) {
13855 rval = DEV_INFO_FAIL_PAGE0;
13856 return (rval);
13857 }
13858
13859 if ((dev_info & (MPI2_SAS_DEVICE_INFO_SSP_TARGET |
13860 MPI2_SAS_DEVICE_INFO_SATA_DEVICE |
13861 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) == 0) {
13862 rval = DEV_INFO_WRONG_DEVICE_TYPE;
13863 return (rval);
13864 }
13865
13866 /*
13867 * Check if the dev handle is for a Phys Disk. If so, set return value
13868 * and exit. Don't add Phys Disks to hash.
13869 */
13870 for (config = 0; config < mpt->m_num_raid_configs; config++) {
13871 for (disk = 0; disk < MPTSAS_MAX_DISKS_IN_CONFIG; disk++) {
13872 if (*dev_handle == mpt->m_raidconfig[config].
13873 m_physdisk_devhdl[disk]) {
13874 rval = DEV_INFO_PHYS_DISK;
13875 return (rval);
13876 }
13877 }
13878 }
13879
13880 /*
13881 * Get SATA Device Name from SAS device page0 for
13882 * sata device, if device name doesn't exist, set mta_wwn to
13883 * 0 for direct attached SATA. For the device behind the expander
13884 * we still can use STP address assigned by expander.
13885 */
13886 if (dev_info & (MPI2_SAS_DEVICE_INFO_SATA_DEVICE |
13887 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) {
13888 /* alloc a temporary target to send the cmd to */
13889 tmp_tgt = mptsas_tgt_alloc(mpt->m_tmp_targets, *dev_handle,
13890 0, dev_info, 0, 0);
13891 mutex_exit(&mpt->m_mutex);
13892
13893 devicename = mptsas_get_sata_guid(mpt, tmp_tgt, 0);
13894
13895 if (devicename == -1) {
13896 mutex_enter(&mpt->m_mutex);
13897 refhash_remove(mpt->m_tmp_targets, tmp_tgt);
13898 rval = DEV_INFO_FAIL_GUID;
13899 return (rval);
13900 }
13901
13902 if (devicename != 0 && (((devicename >> 56) & 0xf0) == 0x50)) {
13903 sas_wwn = devicename;
13904 } else if (dev_info & MPI2_SAS_DEVICE_INFO_DIRECT_ATTACH) {
13905 sas_wwn = 0;
13906 }
13907
13908 mutex_enter(&mpt->m_mutex);
13909 refhash_remove(mpt->m_tmp_targets, tmp_tgt);
13910 }
13911
13912 phymask = mptsas_physport_to_phymask(mpt, physport);
13913 *pptgt = mptsas_tgt_alloc(mpt->m_targets, *dev_handle, sas_wwn,
13914 dev_info, phymask, phynum);
13915 if (*pptgt == NULL) {
13916 mptsas_log(mpt, CE_WARN, "Failed to allocated target"
13917 "structure!");
13918 rval = DEV_INFO_FAIL_ALLOC;
13919 return (rval);
13920 }
13921 (*pptgt)->m_io_flags = io_flags;
13922 (*pptgt)->m_enclosure = enclosure;
13923 (*pptgt)->m_slot_num = bay_num;
13924 return (DEV_INFO_SUCCESS);
13925 }
13926
13927 uint64_t
mptsas_get_sata_guid(mptsas_t * mpt,mptsas_target_t * ptgt,int lun)13928 mptsas_get_sata_guid(mptsas_t *mpt, mptsas_target_t *ptgt, int lun)
13929 {
13930 uint64_t sata_guid = 0, *pwwn = NULL;
13931 int target = ptgt->m_devhdl;
13932 uchar_t *inq83 = NULL;
13933 int inq83_len = 0xFF;
13934 uchar_t *dblk = NULL;
13935 int inq83_retry = 3;
13936 int rval = DDI_FAILURE;
13937
13938 inq83 = kmem_zalloc(inq83_len, KM_SLEEP);
13939
13940 inq83_retry:
13941 rval = mptsas_inquiry(mpt, ptgt, lun, 0x83, inq83,
13942 inq83_len, NULL, 1);
13943 if (rval != DDI_SUCCESS) {
13944 mptsas_log(mpt, CE_WARN, "!mptsas request inquiry page "
13945 "0x83 for target:%x, lun:%x failed!", target, lun);
13946 sata_guid = -1;
13947 goto out;
13948 }
13949 /* According to SAT2, the first descriptor is logic unit name */
13950 dblk = &inq83[4];
13951 if ((dblk[1] & 0x30) != 0) {
13952 mptsas_log(mpt, CE_WARN, "!Descriptor is not lun associated.");
13953 goto out;
13954 }
13955 pwwn = (uint64_t *)(void *)(&dblk[4]);
13956 if ((dblk[4] & 0xf0) == 0x50) {
13957 sata_guid = BE_64(*pwwn);
13958 goto out;
13959 } else if (dblk[4] == 'A') {
13960 NDBG20(("SATA drive has no NAA format GUID."));
13961 goto out;
13962 } else {
13963 /* The data is not ready, wait and retry */
13964 inq83_retry--;
13965 if (inq83_retry <= 0) {
13966 goto out;
13967 }
13968 NDBG20(("The GUID is not ready, retry..."));
13969 delay(1 * drv_usectohz(1000000));
13970 goto inq83_retry;
13971 }
13972 out:
13973 kmem_free(inq83, inq83_len);
13974 return (sata_guid);
13975 }
13976
13977 static int
mptsas_inquiry(mptsas_t * mpt,mptsas_target_t * ptgt,int lun,uchar_t page,unsigned char * buf,int len,int * reallen,uchar_t evpd)13978 mptsas_inquiry(mptsas_t *mpt, mptsas_target_t *ptgt, int lun, uchar_t page,
13979 unsigned char *buf, int len, int *reallen, uchar_t evpd)
13980 {
13981 uchar_t cdb[CDB_GROUP0];
13982 struct scsi_address ap;
13983 struct buf *data_bp = NULL;
13984 int resid = 0;
13985 int ret = DDI_FAILURE;
13986
13987 ASSERT(len <= 0xffff);
13988
13989 ap.a_target = MPTSAS_INVALID_DEVHDL;
13990 ap.a_lun = (uchar_t)(lun);
13991 ap.a_hba_tran = mpt->m_tran;
13992
13993 data_bp = scsi_alloc_consistent_buf(&ap,
13994 (struct buf *)NULL, len, B_READ, NULL_FUNC, NULL);
13995 if (data_bp == NULL) {
13996 return (ret);
13997 }
13998 bzero(cdb, CDB_GROUP0);
13999 cdb[0] = SCMD_INQUIRY;
14000 cdb[1] = evpd;
14001 cdb[2] = page;
14002 cdb[3] = (len & 0xff00) >> 8;
14003 cdb[4] = (len & 0x00ff);
14004 cdb[5] = 0;
14005
14006 ret = mptsas_send_scsi_cmd(mpt, &ap, ptgt, &cdb[0], CDB_GROUP0, data_bp,
14007 &resid);
14008 if (ret == DDI_SUCCESS) {
14009 if (reallen) {
14010 *reallen = len - resid;
14011 }
14012 bcopy((caddr_t)data_bp->b_un.b_addr, buf, len);
14013 }
14014 if (data_bp) {
14015 scsi_free_consistent_buf(data_bp);
14016 }
14017 return (ret);
14018 }
14019
14020 static int
mptsas_send_scsi_cmd(mptsas_t * mpt,struct scsi_address * ap,mptsas_target_t * ptgt,uchar_t * cdb,int cdblen,struct buf * data_bp,int * resid)14021 mptsas_send_scsi_cmd(mptsas_t *mpt, struct scsi_address *ap,
14022 mptsas_target_t *ptgt, uchar_t *cdb, int cdblen, struct buf *data_bp,
14023 int *resid)
14024 {
14025 struct scsi_pkt *pktp = NULL;
14026 scsi_hba_tran_t *tran_clone = NULL;
14027 mptsas_tgt_private_t *tgt_private = NULL;
14028 int ret = DDI_FAILURE;
14029
14030 /*
14031 * scsi_hba_tran_t->tran_tgt_private is used to pass the address
14032 * information to scsi_init_pkt, allocate a scsi_hba_tran structure
14033 * to simulate the cmds from sd
14034 */
14035 tran_clone = kmem_alloc(
14036 sizeof (scsi_hba_tran_t), KM_SLEEP);
14037 if (tran_clone == NULL) {
14038 goto out;
14039 }
14040 bcopy((caddr_t)mpt->m_tran,
14041 (caddr_t)tran_clone, sizeof (scsi_hba_tran_t));
14042 tgt_private = kmem_alloc(
14043 sizeof (mptsas_tgt_private_t), KM_SLEEP);
14044 if (tgt_private == NULL) {
14045 goto out;
14046 }
14047 tgt_private->t_lun = ap->a_lun;
14048 tgt_private->t_private = ptgt;
14049 tran_clone->tran_tgt_private = tgt_private;
14050 ap->a_hba_tran = tran_clone;
14051
14052 pktp = scsi_init_pkt(ap, (struct scsi_pkt *)NULL,
14053 data_bp, cdblen, sizeof (struct scsi_arq_status),
14054 0, PKT_CONSISTENT, NULL, NULL);
14055 if (pktp == NULL) {
14056 goto out;
14057 }
14058 bcopy(cdb, pktp->pkt_cdbp, cdblen);
14059 pktp->pkt_flags = FLAG_NOPARITY;
14060 if (scsi_poll(pktp) < 0) {
14061 goto out;
14062 }
14063 if (((struct scsi_status *)pktp->pkt_scbp)->sts_chk) {
14064 goto out;
14065 }
14066 if (resid != NULL) {
14067 *resid = pktp->pkt_resid;
14068 }
14069
14070 ret = DDI_SUCCESS;
14071 out:
14072 if (pktp) {
14073 scsi_destroy_pkt(pktp);
14074 }
14075 if (tran_clone) {
14076 kmem_free(tran_clone, sizeof (scsi_hba_tran_t));
14077 }
14078 if (tgt_private) {
14079 kmem_free(tgt_private, sizeof (mptsas_tgt_private_t));
14080 }
14081 return (ret);
14082 }
14083 static int
mptsas_parse_address(char * name,uint64_t * wwid,uint8_t * phy,int * lun)14084 mptsas_parse_address(char *name, uint64_t *wwid, uint8_t *phy, int *lun)
14085 {
14086 char *cp = NULL;
14087 char *ptr = NULL;
14088 size_t s = 0;
14089 char *wwid_str = NULL;
14090 char *lun_str = NULL;
14091 long lunnum;
14092 long phyid = -1;
14093 int rc = DDI_FAILURE;
14094
14095 ptr = name;
14096 ASSERT(ptr[0] == 'w' || ptr[0] == 'p');
14097 ptr++;
14098 if ((cp = strchr(ptr, ',')) == NULL) {
14099 return (DDI_FAILURE);
14100 }
14101
14102 wwid_str = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
14103 s = (uintptr_t)cp - (uintptr_t)ptr;
14104
14105 bcopy(ptr, wwid_str, s);
14106 wwid_str[s] = '\0';
14107
14108 ptr = ++cp;
14109
14110 if ((cp = strchr(ptr, '\0')) == NULL) {
14111 goto out;
14112 }
14113 lun_str = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
14114 s = (uintptr_t)cp - (uintptr_t)ptr;
14115
14116 bcopy(ptr, lun_str, s);
14117 lun_str[s] = '\0';
14118
14119 if (name[0] == 'p') {
14120 rc = ddi_strtol(wwid_str, NULL, 0x10, &phyid);
14121 } else {
14122 rc = scsi_wwnstr_to_wwn(wwid_str, wwid);
14123 }
14124 if (rc != DDI_SUCCESS)
14125 goto out;
14126
14127 if (phyid != -1) {
14128 ASSERT(phyid < MPTSAS_MAX_PHYS);
14129 *phy = (uint8_t)phyid;
14130 }
14131 rc = ddi_strtol(lun_str, NULL, 0x10, &lunnum);
14132 if (rc != 0)
14133 goto out;
14134
14135 *lun = (int)lunnum;
14136 rc = DDI_SUCCESS;
14137 out:
14138 if (wwid_str)
14139 kmem_free(wwid_str, SCSI_MAXNAMELEN);
14140 if (lun_str)
14141 kmem_free(lun_str, SCSI_MAXNAMELEN);
14142
14143 return (rc);
14144 }
14145
14146 /*
14147 * mptsas_parse_smp_name() is to parse sas wwn string
14148 * which format is "wWWN"
14149 */
14150 static int
mptsas_parse_smp_name(char * name,uint64_t * wwn)14151 mptsas_parse_smp_name(char *name, uint64_t *wwn)
14152 {
14153 char *ptr = name;
14154
14155 if (*ptr != 'w') {
14156 return (DDI_FAILURE);
14157 }
14158
14159 ptr++;
14160 if (scsi_wwnstr_to_wwn(ptr, wwn)) {
14161 return (DDI_FAILURE);
14162 }
14163 return (DDI_SUCCESS);
14164 }
14165
14166 static int
mptsas_bus_config(dev_info_t * pdip,uint_t flag,ddi_bus_config_op_t op,void * arg,dev_info_t ** childp)14167 mptsas_bus_config(dev_info_t *pdip, uint_t flag,
14168 ddi_bus_config_op_t op, void *arg, dev_info_t **childp)
14169 {
14170 int ret = NDI_FAILURE;
14171 int circ = 0;
14172 int circ1 = 0;
14173 mptsas_t *mpt;
14174 char *ptr = NULL;
14175 char *devnm = NULL;
14176 uint64_t wwid = 0;
14177 uint8_t phy = 0xFF;
14178 int lun = 0;
14179 uint_t mflags = flag;
14180 int bconfig = TRUE;
14181
14182 if (scsi_hba_iport_unit_address(pdip) == 0) {
14183 return (DDI_FAILURE);
14184 }
14185
14186 mpt = DIP2MPT(pdip);
14187 if (!mpt) {
14188 return (DDI_FAILURE);
14189 }
14190 /*
14191 * Hold the nexus across the bus_config
14192 */
14193 ndi_devi_enter(scsi_vhci_dip, &circ);
14194 ndi_devi_enter(pdip, &circ1);
14195 switch (op) {
14196 case BUS_CONFIG_ONE:
14197 /* parse wwid/target name out of name given */
14198 if ((ptr = strchr((char *)arg, '@')) == NULL) {
14199 ret = NDI_FAILURE;
14200 break;
14201 }
14202 ptr++;
14203 if (strncmp((char *)arg, "smp", 3) == 0) {
14204 /*
14205 * This is a SMP target device
14206 */
14207 ret = mptsas_parse_smp_name(ptr, &wwid);
14208 if (ret != DDI_SUCCESS) {
14209 ret = NDI_FAILURE;
14210 break;
14211 }
14212 ret = mptsas_config_smp(pdip, wwid, childp);
14213 } else if ((ptr[0] == 'w') || (ptr[0] == 'p')) {
14214 /*
14215 * OBP could pass down a non-canonical form
14216 * bootpath without LUN part when LUN is 0.
14217 * So driver need adjust the string.
14218 */
14219 if (strchr(ptr, ',') == NULL) {
14220 devnm = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
14221 (void) sprintf(devnm, "%s,0", (char *)arg);
14222 ptr = strchr(devnm, '@');
14223 ptr++;
14224 }
14225
14226 /*
14227 * The device path is wWWID format and the device
14228 * is not SMP target device.
14229 */
14230 ret = mptsas_parse_address(ptr, &wwid, &phy, &lun);
14231 if (ret != DDI_SUCCESS) {
14232 ret = NDI_FAILURE;
14233 break;
14234 }
14235 *childp = NULL;
14236 if (ptr[0] == 'w') {
14237 ret = mptsas_config_one_addr(pdip, wwid,
14238 lun, childp);
14239 } else if (ptr[0] == 'p') {
14240 ret = mptsas_config_one_phy(pdip, phy, lun,
14241 childp);
14242 }
14243
14244 /*
14245 * If this is CD/DVD device in OBP path, the
14246 * ndi_busop_bus_config can be skipped as config one
14247 * operation is done above.
14248 */
14249 if ((ret == NDI_SUCCESS) && (*childp != NULL) &&
14250 (strcmp(ddi_node_name(*childp), "cdrom") == 0) &&
14251 (strncmp((char *)arg, "disk", 4) == 0)) {
14252 bconfig = FALSE;
14253 ndi_hold_devi(*childp);
14254 }
14255 } else {
14256 ret = NDI_FAILURE;
14257 break;
14258 }
14259
14260 /*
14261 * DDI group instructed us to use this flag.
14262 */
14263 mflags |= NDI_MDI_FALLBACK;
14264 break;
14265 case BUS_CONFIG_DRIVER:
14266 case BUS_CONFIG_ALL:
14267 mptsas_config_all(pdip);
14268 ret = NDI_SUCCESS;
14269 break;
14270 default:
14271 ret = NDI_FAILURE;
14272 break;
14273 }
14274
14275 if ((ret == NDI_SUCCESS) && bconfig) {
14276 ret = ndi_busop_bus_config(pdip, mflags, op,
14277 (devnm == NULL) ? arg : devnm, childp, 0);
14278 }
14279
14280 ndi_devi_exit(pdip, circ1);
14281 ndi_devi_exit(scsi_vhci_dip, circ);
14282 if (devnm != NULL)
14283 kmem_free(devnm, SCSI_MAXNAMELEN);
14284 return (ret);
14285 }
14286
14287 static int
mptsas_probe_lun(dev_info_t * pdip,int lun,dev_info_t ** dip,mptsas_target_t * ptgt)14288 mptsas_probe_lun(dev_info_t *pdip, int lun, dev_info_t **dip,
14289 mptsas_target_t *ptgt)
14290 {
14291 int rval = DDI_FAILURE;
14292 struct scsi_inquiry *sd_inq = NULL;
14293 mptsas_t *mpt = DIP2MPT(pdip);
14294
14295 sd_inq = (struct scsi_inquiry *)kmem_alloc(SUN_INQSIZE, KM_SLEEP);
14296
14297 rval = mptsas_inquiry(mpt, ptgt, lun, 0, (uchar_t *)sd_inq,
14298 SUN_INQSIZE, 0, (uchar_t)0);
14299
14300 if ((rval == DDI_SUCCESS) && MPTSAS_VALID_LUN(sd_inq)) {
14301 rval = mptsas_create_lun(pdip, sd_inq, dip, ptgt, lun);
14302 } else {
14303 rval = DDI_FAILURE;
14304 }
14305
14306 kmem_free(sd_inq, SUN_INQSIZE);
14307 return (rval);
14308 }
14309
14310 static int
mptsas_config_one_addr(dev_info_t * pdip,uint64_t sasaddr,int lun,dev_info_t ** lundip)14311 mptsas_config_one_addr(dev_info_t *pdip, uint64_t sasaddr, int lun,
14312 dev_info_t **lundip)
14313 {
14314 int rval;
14315 mptsas_t *mpt = DIP2MPT(pdip);
14316 int phymask;
14317 mptsas_target_t *ptgt = NULL;
14318
14319 /*
14320 * Get the physical port associated to the iport
14321 */
14322 phymask = ddi_prop_get_int(DDI_DEV_T_ANY, pdip, 0,
14323 "phymask", 0);
14324
14325 ptgt = mptsas_wwid_to_ptgt(mpt, phymask, sasaddr);
14326 if (ptgt == NULL) {
14327 /*
14328 * didn't match any device by searching
14329 */
14330 return (DDI_FAILURE);
14331 }
14332 /*
14333 * If the LUN already exists and the status is online,
14334 * we just return the pointer to dev_info_t directly.
14335 * For the mdi_pathinfo node, we'll handle it in
14336 * mptsas_create_virt_lun()
14337 * TODO should be also in mptsas_handle_dr
14338 */
14339
14340 *lundip = mptsas_find_child_addr(pdip, sasaddr, lun);
14341 if (*lundip != NULL) {
14342 /*
14343 * TODO Another senario is, we hotplug the same disk
14344 * on the same slot, the devhdl changed, is this
14345 * possible?
14346 * tgt_private->t_private != ptgt
14347 */
14348 if (sasaddr != ptgt->m_addr.mta_wwn) {
14349 /*
14350 * The device has changed although the devhdl is the
14351 * same (Enclosure mapping mode, change drive on the
14352 * same slot)
14353 */
14354 return (DDI_FAILURE);
14355 }
14356 return (DDI_SUCCESS);
14357 }
14358
14359 if (phymask == 0) {
14360 /*
14361 * Configure IR volume
14362 */
14363 rval = mptsas_config_raid(pdip, ptgt->m_devhdl, lundip);
14364 return (rval);
14365 }
14366 rval = mptsas_probe_lun(pdip, lun, lundip, ptgt);
14367
14368 return (rval);
14369 }
14370
14371 static int
mptsas_config_one_phy(dev_info_t * pdip,uint8_t phy,int lun,dev_info_t ** lundip)14372 mptsas_config_one_phy(dev_info_t *pdip, uint8_t phy, int lun,
14373 dev_info_t **lundip)
14374 {
14375 int rval;
14376 mptsas_t *mpt = DIP2MPT(pdip);
14377 mptsas_phymask_t phymask;
14378 mptsas_target_t *ptgt = NULL;
14379
14380 /*
14381 * Get the physical port associated to the iport
14382 */
14383 phymask = (mptsas_phymask_t)ddi_prop_get_int(DDI_DEV_T_ANY, pdip, 0,
14384 "phymask", 0);
14385
14386 ptgt = mptsas_phy_to_tgt(mpt, phymask, phy);
14387 if (ptgt == NULL) {
14388 /*
14389 * didn't match any device by searching
14390 */
14391 return (DDI_FAILURE);
14392 }
14393
14394 /*
14395 * If the LUN already exists and the status is online,
14396 * we just return the pointer to dev_info_t directly.
14397 * For the mdi_pathinfo node, we'll handle it in
14398 * mptsas_create_virt_lun().
14399 */
14400
14401 *lundip = mptsas_find_child_phy(pdip, phy);
14402 if (*lundip != NULL) {
14403 return (DDI_SUCCESS);
14404 }
14405
14406 rval = mptsas_probe_lun(pdip, lun, lundip, ptgt);
14407
14408 return (rval);
14409 }
14410
14411 static int
mptsas_retrieve_lundata(int lun_cnt,uint8_t * buf,uint16_t * lun_num,uint8_t * lun_addr_type)14412 mptsas_retrieve_lundata(int lun_cnt, uint8_t *buf, uint16_t *lun_num,
14413 uint8_t *lun_addr_type)
14414 {
14415 uint32_t lun_idx = 0;
14416
14417 ASSERT(lun_num != NULL);
14418 ASSERT(lun_addr_type != NULL);
14419
14420 lun_idx = (lun_cnt + 1) * MPTSAS_SCSI_REPORTLUNS_ADDRESS_SIZE;
14421 /* determine report luns addressing type */
14422 switch (buf[lun_idx] & MPTSAS_SCSI_REPORTLUNS_ADDRESS_MASK) {
14423 /*
14424 * Vendors in the field have been found to be concatenating
14425 * bus/target/lun to equal the complete lun value instead
14426 * of switching to flat space addressing
14427 */
14428 /* 00b - peripheral device addressing method */
14429 case MPTSAS_SCSI_REPORTLUNS_ADDRESS_PERIPHERAL:
14430 /* FALLTHRU */
14431 /* 10b - logical unit addressing method */
14432 case MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT:
14433 /* FALLTHRU */
14434 /* 01b - flat space addressing method */
14435 case MPTSAS_SCSI_REPORTLUNS_ADDRESS_FLAT_SPACE:
14436 /* byte0 bit0-5=msb lun byte1 bit0-7=lsb lun */
14437 *lun_addr_type = (buf[lun_idx] &
14438 MPTSAS_SCSI_REPORTLUNS_ADDRESS_MASK) >> 6;
14439 *lun_num = (buf[lun_idx] & 0x3F) << 8;
14440 *lun_num |= buf[lun_idx + 1];
14441 return (DDI_SUCCESS);
14442 default:
14443 return (DDI_FAILURE);
14444 }
14445 }
14446
14447 static int
mptsas_config_luns(dev_info_t * pdip,mptsas_target_t * ptgt)14448 mptsas_config_luns(dev_info_t *pdip, mptsas_target_t *ptgt)
14449 {
14450 struct buf *repluns_bp = NULL;
14451 struct scsi_address ap;
14452 uchar_t cdb[CDB_GROUP5];
14453 int ret = DDI_FAILURE;
14454 int retry = 0;
14455 int lun_list_len = 0;
14456 uint16_t lun_num = 0;
14457 uint8_t lun_addr_type = 0;
14458 uint32_t lun_cnt = 0;
14459 uint32_t lun_total = 0;
14460 dev_info_t *cdip = NULL;
14461 uint16_t *saved_repluns = NULL;
14462 char *buffer = NULL;
14463 int buf_len = 128;
14464 mptsas_t *mpt = DIP2MPT(pdip);
14465 uint64_t sas_wwn = 0;
14466 uint8_t phy = 0xFF;
14467 uint32_t dev_info = 0;
14468
14469 mutex_enter(&mpt->m_mutex);
14470 sas_wwn = ptgt->m_addr.mta_wwn;
14471 phy = ptgt->m_phynum;
14472 dev_info = ptgt->m_deviceinfo;
14473 mutex_exit(&mpt->m_mutex);
14474
14475 if (sas_wwn == 0) {
14476 /*
14477 * It's a SATA without Device Name
14478 * So don't try multi-LUNs
14479 */
14480 if (mptsas_find_child_phy(pdip, phy)) {
14481 return (DDI_SUCCESS);
14482 } else {
14483 /*
14484 * need configure and create node
14485 */
14486 return (DDI_FAILURE);
14487 }
14488 }
14489
14490 /*
14491 * WWN (SAS address or Device Name exist)
14492 */
14493 if (dev_info & (MPI2_SAS_DEVICE_INFO_SATA_DEVICE |
14494 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) {
14495 /*
14496 * SATA device with Device Name
14497 * So don't try multi-LUNs
14498 */
14499 if (mptsas_find_child_addr(pdip, sas_wwn, 0)) {
14500 return (DDI_SUCCESS);
14501 } else {
14502 return (DDI_FAILURE);
14503 }
14504 }
14505
14506 do {
14507 ap.a_target = MPTSAS_INVALID_DEVHDL;
14508 ap.a_lun = 0;
14509 ap.a_hba_tran = mpt->m_tran;
14510 repluns_bp = scsi_alloc_consistent_buf(&ap,
14511 (struct buf *)NULL, buf_len, B_READ, NULL_FUNC, NULL);
14512 if (repluns_bp == NULL) {
14513 retry++;
14514 continue;
14515 }
14516 bzero(cdb, CDB_GROUP5);
14517 cdb[0] = SCMD_REPORT_LUNS;
14518 cdb[6] = (buf_len & 0xff000000) >> 24;
14519 cdb[7] = (buf_len & 0x00ff0000) >> 16;
14520 cdb[8] = (buf_len & 0x0000ff00) >> 8;
14521 cdb[9] = (buf_len & 0x000000ff);
14522
14523 ret = mptsas_send_scsi_cmd(mpt, &ap, ptgt, &cdb[0], CDB_GROUP5,
14524 repluns_bp, NULL);
14525 if (ret != DDI_SUCCESS) {
14526 scsi_free_consistent_buf(repluns_bp);
14527 retry++;
14528 continue;
14529 }
14530 lun_list_len = BE_32(*(int *)((void *)(
14531 repluns_bp->b_un.b_addr)));
14532 if (buf_len >= lun_list_len + 8) {
14533 ret = DDI_SUCCESS;
14534 break;
14535 }
14536 scsi_free_consistent_buf(repluns_bp);
14537 buf_len = lun_list_len + 8;
14538
14539 } while (retry < 3);
14540
14541 if (ret != DDI_SUCCESS)
14542 return (ret);
14543 buffer = (char *)repluns_bp->b_un.b_addr;
14544 /*
14545 * find out the number of luns returned by the SCSI ReportLun call
14546 * and allocate buffer space
14547 */
14548 lun_total = lun_list_len / MPTSAS_SCSI_REPORTLUNS_ADDRESS_SIZE;
14549 saved_repluns = kmem_zalloc(sizeof (uint16_t) * lun_total, KM_SLEEP);
14550 if (saved_repluns == NULL) {
14551 scsi_free_consistent_buf(repluns_bp);
14552 return (DDI_FAILURE);
14553 }
14554 for (lun_cnt = 0; lun_cnt < lun_total; lun_cnt++) {
14555 if (mptsas_retrieve_lundata(lun_cnt, (uint8_t *)(buffer),
14556 &lun_num, &lun_addr_type) != DDI_SUCCESS) {
14557 continue;
14558 }
14559 saved_repluns[lun_cnt] = lun_num;
14560 if ((cdip = mptsas_find_child_addr(pdip, sas_wwn, lun_num)) !=
14561 NULL) {
14562 ret = DDI_SUCCESS;
14563 } else {
14564 ret = mptsas_probe_lun(pdip, lun_num, &cdip,
14565 ptgt);
14566 }
14567 if ((ret == DDI_SUCCESS) && (cdip != NULL)) {
14568 (void) ndi_prop_remove(DDI_DEV_T_NONE, cdip,
14569 MPTSAS_DEV_GONE);
14570 }
14571 }
14572 mptsas_offline_missed_luns(pdip, saved_repluns, lun_total, ptgt);
14573 kmem_free(saved_repluns, sizeof (uint16_t) * lun_total);
14574 scsi_free_consistent_buf(repluns_bp);
14575 return (DDI_SUCCESS);
14576 }
14577
14578 static int
mptsas_config_raid(dev_info_t * pdip,uint16_t target,dev_info_t ** dip)14579 mptsas_config_raid(dev_info_t *pdip, uint16_t target, dev_info_t **dip)
14580 {
14581 int rval = DDI_FAILURE;
14582 struct scsi_inquiry *sd_inq = NULL;
14583 mptsas_t *mpt = DIP2MPT(pdip);
14584 mptsas_target_t *ptgt = NULL;
14585
14586 mutex_enter(&mpt->m_mutex);
14587 ptgt = refhash_linear_search(mpt->m_targets,
14588 mptsas_target_eval_devhdl, &target);
14589 mutex_exit(&mpt->m_mutex);
14590 if (ptgt == NULL) {
14591 mptsas_log(mpt, CE_WARN, "Volume with VolDevHandle of 0x%x "
14592 "not found.", target);
14593 return (rval);
14594 }
14595
14596 sd_inq = (struct scsi_inquiry *)kmem_alloc(SUN_INQSIZE, KM_SLEEP);
14597 rval = mptsas_inquiry(mpt, ptgt, 0, 0, (uchar_t *)sd_inq,
14598 SUN_INQSIZE, 0, (uchar_t)0);
14599
14600 if ((rval == DDI_SUCCESS) && MPTSAS_VALID_LUN(sd_inq)) {
14601 rval = mptsas_create_phys_lun(pdip, sd_inq, NULL, dip, ptgt,
14602 0);
14603 } else {
14604 rval = DDI_FAILURE;
14605 }
14606
14607 kmem_free(sd_inq, SUN_INQSIZE);
14608 return (rval);
14609 }
14610
14611 /*
14612 * configure all RAID volumes for virtual iport
14613 */
14614 static void
mptsas_config_all_viport(dev_info_t * pdip)14615 mptsas_config_all_viport(dev_info_t *pdip)
14616 {
14617 mptsas_t *mpt = DIP2MPT(pdip);
14618 int config, vol;
14619 int target;
14620 dev_info_t *lundip = NULL;
14621
14622 /*
14623 * Get latest RAID info and search for any Volume DevHandles. If any
14624 * are found, configure the volume.
14625 */
14626 mutex_enter(&mpt->m_mutex);
14627 for (config = 0; config < mpt->m_num_raid_configs; config++) {
14628 for (vol = 0; vol < MPTSAS_MAX_RAIDVOLS; vol++) {
14629 if (mpt->m_raidconfig[config].m_raidvol[vol].m_israid
14630 == 1) {
14631 target = mpt->m_raidconfig[config].
14632 m_raidvol[vol].m_raidhandle;
14633 mutex_exit(&mpt->m_mutex);
14634 (void) mptsas_config_raid(pdip, target,
14635 &lundip);
14636 mutex_enter(&mpt->m_mutex);
14637 }
14638 }
14639 }
14640 mutex_exit(&mpt->m_mutex);
14641 }
14642
14643 static void
mptsas_offline_missed_luns(dev_info_t * pdip,uint16_t * repluns,int lun_cnt,mptsas_target_t * ptgt)14644 mptsas_offline_missed_luns(dev_info_t *pdip, uint16_t *repluns,
14645 int lun_cnt, mptsas_target_t *ptgt)
14646 {
14647 dev_info_t *child = NULL, *savechild = NULL;
14648 mdi_pathinfo_t *pip = NULL, *savepip = NULL;
14649 uint64_t sas_wwn, wwid;
14650 uint8_t phy;
14651 int lun;
14652 int i;
14653 int find;
14654 char *addr;
14655 char *nodename;
14656 mptsas_t *mpt = DIP2MPT(pdip);
14657
14658 mutex_enter(&mpt->m_mutex);
14659 wwid = ptgt->m_addr.mta_wwn;
14660 mutex_exit(&mpt->m_mutex);
14661
14662 child = ddi_get_child(pdip);
14663 while (child) {
14664 find = 0;
14665 savechild = child;
14666 child = ddi_get_next_sibling(child);
14667
14668 nodename = ddi_node_name(savechild);
14669 if (strcmp(nodename, "smp") == 0) {
14670 continue;
14671 }
14672
14673 addr = ddi_get_name_addr(savechild);
14674 if (addr == NULL) {
14675 continue;
14676 }
14677
14678 if (mptsas_parse_address(addr, &sas_wwn, &phy, &lun) !=
14679 DDI_SUCCESS) {
14680 continue;
14681 }
14682
14683 if (wwid == sas_wwn) {
14684 for (i = 0; i < lun_cnt; i++) {
14685 if (repluns[i] == lun) {
14686 find = 1;
14687 break;
14688 }
14689 }
14690 } else {
14691 continue;
14692 }
14693 if (find == 0) {
14694 /*
14695 * The lun has not been there already
14696 */
14697 (void) mptsas_offline_lun(pdip, savechild, NULL,
14698 NDI_DEVI_REMOVE);
14699 }
14700 }
14701
14702 pip = mdi_get_next_client_path(pdip, NULL);
14703 while (pip) {
14704 find = 0;
14705 savepip = pip;
14706 addr = MDI_PI(pip)->pi_addr;
14707
14708 pip = mdi_get_next_client_path(pdip, pip);
14709
14710 if (addr == NULL) {
14711 continue;
14712 }
14713
14714 if (mptsas_parse_address(addr, &sas_wwn, &phy,
14715 &lun) != DDI_SUCCESS) {
14716 continue;
14717 }
14718
14719 if (sas_wwn == wwid) {
14720 for (i = 0; i < lun_cnt; i++) {
14721 if (repluns[i] == lun) {
14722 find = 1;
14723 break;
14724 }
14725 }
14726 } else {
14727 continue;
14728 }
14729
14730 if (find == 0) {
14731 /*
14732 * The lun has not been there already
14733 */
14734 (void) mptsas_offline_lun(pdip, NULL, savepip,
14735 NDI_DEVI_REMOVE);
14736 }
14737 }
14738 }
14739
14740 /*
14741 * If this enclosure doesn't exist in the enclosure list, add it. If it does,
14742 * update it.
14743 */
14744 static void
mptsas_enclosure_update(mptsas_t * mpt,mptsas_enclosure_t * mep)14745 mptsas_enclosure_update(mptsas_t *mpt, mptsas_enclosure_t *mep)
14746 {
14747 mptsas_enclosure_t *m;
14748
14749 ASSERT(MUTEX_HELD(&mpt->m_mutex));
14750 m = mptsas_enc_lookup(mpt, mep->me_enchdl);
14751 if (m != NULL) {
14752 uint8_t *ledp;
14753 m->me_flags = mep->me_flags;
14754
14755
14756 /*
14757 * If the number of slots and the first slot entry in the
14758 * enclosure has not changed, then we don't need to do anything
14759 * here. Otherwise, we need to allocate a new array for the LED
14760 * status of the slot.
14761 */
14762 if (m->me_fslot == mep->me_fslot &&
14763 m->me_nslots == mep->me_nslots)
14764 return;
14765
14766 /*
14767 * If the number of slots or the first slot has changed, it's
14768 * not clear that we're really in a place that we can continue
14769 * to honor the existing flags.
14770 */
14771 if (mep->me_nslots > 0) {
14772 ledp = kmem_zalloc(sizeof (uint8_t) * mep->me_nslots,
14773 KM_SLEEP);
14774 } else {
14775 ledp = NULL;
14776 }
14777
14778 if (m->me_slotleds != NULL) {
14779 kmem_free(m->me_slotleds, sizeof (uint8_t) *
14780 m->me_nslots);
14781 }
14782 m->me_slotleds = ledp;
14783 m->me_fslot = mep->me_fslot;
14784 m->me_nslots = mep->me_nslots;
14785 return;
14786 }
14787
14788 m = kmem_zalloc(sizeof (*m), KM_SLEEP);
14789 m->me_enchdl = mep->me_enchdl;
14790 m->me_flags = mep->me_flags;
14791 m->me_nslots = mep->me_nslots;
14792 m->me_fslot = mep->me_fslot;
14793 if (m->me_nslots > 0) {
14794 m->me_slotleds = kmem_zalloc(sizeof (uint8_t) * mep->me_nslots,
14795 KM_SLEEP);
14796 /*
14797 * It may make sense to optionally flush all of the slots and/or
14798 * read the slot status flag here to synchronize between
14799 * ourselves and the card. So far, that hasn't been needed
14800 * annecdotally when enumerating something new. If we do, we
14801 * should kick that off in a taskq potentially.
14802 */
14803 }
14804 list_insert_tail(&mpt->m_enclosures, m);
14805 }
14806
14807 static void
mptsas_update_hashtab(struct mptsas * mpt)14808 mptsas_update_hashtab(struct mptsas *mpt)
14809 {
14810 uint32_t page_address;
14811 int rval = 0;
14812 uint16_t dev_handle;
14813 mptsas_target_t *ptgt = NULL;
14814 mptsas_smp_t smp_node;
14815
14816 /*
14817 * Get latest RAID info.
14818 */
14819 (void) mptsas_get_raid_info(mpt);
14820
14821 dev_handle = mpt->m_smp_devhdl;
14822 while (mpt->m_done_traverse_smp == 0) {
14823 page_address = (MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL &
14824 MPI2_SAS_EXPAND_PGAD_FORM_MASK) | (uint32_t)dev_handle;
14825 if (mptsas_get_sas_expander_page0(mpt, page_address, &smp_node)
14826 != DDI_SUCCESS) {
14827 break;
14828 }
14829 mpt->m_smp_devhdl = dev_handle = smp_node.m_devhdl;
14830 (void) mptsas_smp_alloc(mpt, &smp_node);
14831 }
14832
14833 /*
14834 * Loop over enclosures so we can understand what's there.
14835 */
14836 dev_handle = MPTSAS_INVALID_DEVHDL;
14837 while (mpt->m_done_traverse_enc == 0) {
14838 mptsas_enclosure_t me;
14839
14840 page_address = (MPI2_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE &
14841 MPI2_SAS_ENCLOS_PGAD_FORM_MASK) | (uint32_t)dev_handle;
14842
14843 if (mptsas_get_enclosure_page0(mpt, page_address, &me) !=
14844 DDI_SUCCESS) {
14845 break;
14846 }
14847 dev_handle = me.me_enchdl;
14848 mptsas_enclosure_update(mpt, &me);
14849 }
14850
14851 /*
14852 * Config target devices
14853 */
14854 dev_handle = mpt->m_dev_handle;
14855
14856 /*
14857 * Loop to get sas device page 0 by GetNextHandle till the
14858 * the last handle. If the sas device is a SATA/SSP target,
14859 * we try to config it.
14860 */
14861 while (mpt->m_done_traverse_dev == 0) {
14862 ptgt = NULL;
14863 page_address =
14864 (MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE &
14865 MPI2_SAS_DEVICE_PGAD_FORM_MASK) |
14866 (uint32_t)dev_handle;
14867 rval = mptsas_get_target_device_info(mpt, page_address,
14868 &dev_handle, &ptgt);
14869 if ((rval == DEV_INFO_FAIL_PAGE0) ||
14870 (rval == DEV_INFO_FAIL_ALLOC)) {
14871 break;
14872 }
14873 if (rval == DEV_INFO_FAIL_GUID) {
14874 continue;
14875 }
14876
14877 mpt->m_dev_handle = dev_handle;
14878 }
14879
14880 }
14881
14882 void
mptsas_update_driver_data(struct mptsas * mpt)14883 mptsas_update_driver_data(struct mptsas *mpt)
14884 {
14885 mptsas_target_t *tp;
14886 mptsas_smp_t *sp;
14887
14888 ASSERT(MUTEX_HELD(&mpt->m_mutex));
14889
14890 /*
14891 * TODO after hard reset, update the driver data structures
14892 * 1. update port/phymask mapping table mpt->m_phy_info
14893 * 2. invalid all the entries in hash table
14894 * m_devhdl = 0xffff and m_deviceinfo = 0
14895 * 3. call sas_device_page/expander_page to update hash table
14896 */
14897 mptsas_update_phymask(mpt);
14898
14899 /*
14900 * Remove all the devhdls for existing entries but leave their
14901 * addresses alone. In update_hashtab() below, we'll find all
14902 * targets that are still present and reassociate them with
14903 * their potentially new devhdls. Leaving the targets around in
14904 * this fashion allows them to be used on the tx waitq even
14905 * while IOC reset is occurring.
14906 */
14907 for (tp = refhash_first(mpt->m_targets); tp != NULL;
14908 tp = refhash_next(mpt->m_targets, tp)) {
14909 tp->m_devhdl = MPTSAS_INVALID_DEVHDL;
14910 tp->m_deviceinfo = 0;
14911 tp->m_dr_flag = MPTSAS_DR_INACTIVE;
14912 }
14913 for (sp = refhash_first(mpt->m_smp_targets); sp != NULL;
14914 sp = refhash_next(mpt->m_smp_targets, sp)) {
14915 sp->m_devhdl = MPTSAS_INVALID_DEVHDL;
14916 sp->m_deviceinfo = 0;
14917 }
14918 mpt->m_done_traverse_dev = 0;
14919 mpt->m_done_traverse_smp = 0;
14920 mpt->m_done_traverse_enc = 0;
14921 mpt->m_dev_handle = mpt->m_smp_devhdl = MPTSAS_INVALID_DEVHDL;
14922 mptsas_update_hashtab(mpt);
14923 }
14924
14925 static void
mptsas_config_all(dev_info_t * pdip)14926 mptsas_config_all(dev_info_t *pdip)
14927 {
14928 dev_info_t *smpdip = NULL;
14929 mptsas_t *mpt = DIP2MPT(pdip);
14930 int phymask = 0;
14931 mptsas_phymask_t phy_mask;
14932 mptsas_target_t *ptgt = NULL;
14933 mptsas_smp_t *psmp;
14934
14935 /*
14936 * Get the phymask associated to the iport
14937 */
14938 phymask = ddi_prop_get_int(DDI_DEV_T_ANY, pdip, 0,
14939 "phymask", 0);
14940
14941 /*
14942 * Enumerate RAID volumes here (phymask == 0).
14943 */
14944 if (phymask == 0) {
14945 mptsas_config_all_viport(pdip);
14946 return;
14947 }
14948
14949 mutex_enter(&mpt->m_mutex);
14950
14951 if (!mpt->m_done_traverse_dev || !mpt->m_done_traverse_smp ||
14952 !mpt->m_done_traverse_enc) {
14953 mptsas_update_hashtab(mpt);
14954 }
14955
14956 for (psmp = refhash_first(mpt->m_smp_targets); psmp != NULL;
14957 psmp = refhash_next(mpt->m_smp_targets, psmp)) {
14958 phy_mask = psmp->m_addr.mta_phymask;
14959 if (phy_mask == phymask) {
14960 smpdip = NULL;
14961 mutex_exit(&mpt->m_mutex);
14962 (void) mptsas_online_smp(pdip, psmp, &smpdip);
14963 mutex_enter(&mpt->m_mutex);
14964 }
14965 }
14966
14967 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
14968 ptgt = refhash_next(mpt->m_targets, ptgt)) {
14969 phy_mask = ptgt->m_addr.mta_phymask;
14970 if (phy_mask == phymask) {
14971 mutex_exit(&mpt->m_mutex);
14972 (void) mptsas_config_target(pdip, ptgt);
14973 mutex_enter(&mpt->m_mutex);
14974 }
14975 }
14976 mutex_exit(&mpt->m_mutex);
14977 }
14978
14979 static int
mptsas_config_target(dev_info_t * pdip,mptsas_target_t * ptgt)14980 mptsas_config_target(dev_info_t *pdip, mptsas_target_t *ptgt)
14981 {
14982 int rval = DDI_FAILURE;
14983 dev_info_t *tdip;
14984
14985 rval = mptsas_config_luns(pdip, ptgt);
14986 if (rval != DDI_SUCCESS) {
14987 /*
14988 * The return value means the SCMD_REPORT_LUNS
14989 * did not execute successfully. The target maybe
14990 * doesn't support such command.
14991 */
14992 rval = mptsas_probe_lun(pdip, 0, &tdip, ptgt);
14993 }
14994 return (rval);
14995 }
14996
14997 /*
14998 * Return fail if not all the childs/paths are freed.
14999 * if there is any path under the HBA, the return value will be always fail
15000 * because we didn't call mdi_pi_free for path
15001 */
15002 static int
mptsas_offline_target(dev_info_t * pdip,char * name)15003 mptsas_offline_target(dev_info_t *pdip, char *name)
15004 {
15005 dev_info_t *child = NULL, *prechild = NULL;
15006 mdi_pathinfo_t *pip = NULL, *savepip = NULL;
15007 int tmp_rval, rval = DDI_SUCCESS;
15008 char *addr, *cp;
15009 size_t s;
15010 mptsas_t *mpt = DIP2MPT(pdip);
15011
15012 child = ddi_get_child(pdip);
15013 while (child) {
15014 addr = ddi_get_name_addr(child);
15015 prechild = child;
15016 child = ddi_get_next_sibling(child);
15017
15018 if (addr == NULL) {
15019 continue;
15020 }
15021 if ((cp = strchr(addr, ',')) == NULL) {
15022 continue;
15023 }
15024
15025 s = (uintptr_t)cp - (uintptr_t)addr;
15026
15027 if (strncmp(addr, name, s) != 0) {
15028 continue;
15029 }
15030
15031 tmp_rval = mptsas_offline_lun(pdip, prechild, NULL,
15032 NDI_DEVI_REMOVE);
15033 if (tmp_rval != DDI_SUCCESS) {
15034 rval = DDI_FAILURE;
15035 if (ndi_prop_create_boolean(DDI_DEV_T_NONE,
15036 prechild, MPTSAS_DEV_GONE) !=
15037 DDI_PROP_SUCCESS) {
15038 mptsas_log(mpt, CE_WARN, "mptsas driver "
15039 "unable to create property for "
15040 "SAS %s (MPTSAS_DEV_GONE)", addr);
15041 }
15042 }
15043 }
15044
15045 pip = mdi_get_next_client_path(pdip, NULL);
15046 while (pip) {
15047 addr = MDI_PI(pip)->pi_addr;
15048 savepip = pip;
15049 pip = mdi_get_next_client_path(pdip, pip);
15050 if (addr == NULL) {
15051 continue;
15052 }
15053
15054 if ((cp = strchr(addr, ',')) == NULL) {
15055 continue;
15056 }
15057
15058 s = (uintptr_t)cp - (uintptr_t)addr;
15059
15060 if (strncmp(addr, name, s) != 0) {
15061 continue;
15062 }
15063
15064 (void) mptsas_offline_lun(pdip, NULL, savepip,
15065 NDI_DEVI_REMOVE);
15066 /*
15067 * driver will not invoke mdi_pi_free, so path will not
15068 * be freed forever, return DDI_FAILURE.
15069 */
15070 rval = DDI_FAILURE;
15071 }
15072 return (rval);
15073 }
15074
15075 static int
mptsas_offline_lun(dev_info_t * pdip,dev_info_t * rdip,mdi_pathinfo_t * rpip,uint_t flags)15076 mptsas_offline_lun(dev_info_t *pdip, dev_info_t *rdip,
15077 mdi_pathinfo_t *rpip, uint_t flags)
15078 {
15079 int rval = DDI_FAILURE;
15080 char *devname;
15081 dev_info_t *cdip, *parent;
15082
15083 if (rpip != NULL) {
15084 parent = scsi_vhci_dip;
15085 cdip = mdi_pi_get_client(rpip);
15086 } else if (rdip != NULL) {
15087 parent = pdip;
15088 cdip = rdip;
15089 } else {
15090 return (DDI_FAILURE);
15091 }
15092
15093 /*
15094 * Make sure node is attached otherwise
15095 * it won't have related cache nodes to
15096 * clean up. i_ddi_devi_attached is
15097 * similiar to i_ddi_node_state(cdip) >=
15098 * DS_ATTACHED.
15099 */
15100 if (i_ddi_devi_attached(cdip)) {
15101
15102 /* Get full devname */
15103 devname = kmem_alloc(MAXNAMELEN + 1, KM_SLEEP);
15104 (void) ddi_deviname(cdip, devname);
15105 /* Clean cache */
15106 (void) devfs_clean(parent, devname + 1,
15107 DV_CLEAN_FORCE);
15108 kmem_free(devname, MAXNAMELEN + 1);
15109 }
15110 if (rpip != NULL) {
15111 if (MDI_PI_IS_OFFLINE(rpip)) {
15112 rval = DDI_SUCCESS;
15113 } else {
15114 rval = mdi_pi_offline(rpip, 0);
15115 }
15116 } else {
15117 rval = ndi_devi_offline(cdip, flags);
15118 }
15119
15120 return (rval);
15121 }
15122
15123 static dev_info_t *
mptsas_find_smp_child(dev_info_t * parent,char * str_wwn)15124 mptsas_find_smp_child(dev_info_t *parent, char *str_wwn)
15125 {
15126 dev_info_t *child = NULL;
15127 char *smp_wwn = NULL;
15128
15129 child = ddi_get_child(parent);
15130 while (child) {
15131 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, child,
15132 DDI_PROP_DONTPASS, SMP_WWN, &smp_wwn)
15133 != DDI_SUCCESS) {
15134 child = ddi_get_next_sibling(child);
15135 continue;
15136 }
15137
15138 if (strcmp(smp_wwn, str_wwn) == 0) {
15139 ddi_prop_free(smp_wwn);
15140 break;
15141 }
15142 child = ddi_get_next_sibling(child);
15143 ddi_prop_free(smp_wwn);
15144 }
15145 return (child);
15146 }
15147
15148 static int
mptsas_offline_smp(dev_info_t * pdip,mptsas_smp_t * smp_node,uint_t flags)15149 mptsas_offline_smp(dev_info_t *pdip, mptsas_smp_t *smp_node, uint_t flags)
15150 {
15151 int rval = DDI_FAILURE;
15152 char *devname;
15153 char wwn_str[MPTSAS_WWN_STRLEN];
15154 dev_info_t *cdip;
15155
15156 (void) sprintf(wwn_str, "%"PRIx64, smp_node->m_addr.mta_wwn);
15157
15158 cdip = mptsas_find_smp_child(pdip, wwn_str);
15159
15160 if (cdip == NULL)
15161 return (DDI_SUCCESS);
15162
15163 /*
15164 * Make sure node is attached otherwise
15165 * it won't have related cache nodes to
15166 * clean up. i_ddi_devi_attached is
15167 * similiar to i_ddi_node_state(cdip) >=
15168 * DS_ATTACHED.
15169 */
15170 if (i_ddi_devi_attached(cdip)) {
15171
15172 /* Get full devname */
15173 devname = kmem_alloc(MAXNAMELEN + 1, KM_SLEEP);
15174 (void) ddi_deviname(cdip, devname);
15175 /* Clean cache */
15176 (void) devfs_clean(pdip, devname + 1,
15177 DV_CLEAN_FORCE);
15178 kmem_free(devname, MAXNAMELEN + 1);
15179 }
15180
15181 rval = ndi_devi_offline(cdip, flags);
15182
15183 return (rval);
15184 }
15185
15186 static dev_info_t *
mptsas_find_child(dev_info_t * pdip,char * name)15187 mptsas_find_child(dev_info_t *pdip, char *name)
15188 {
15189 dev_info_t *child = NULL;
15190 char *rname = NULL;
15191 int rval = DDI_FAILURE;
15192
15193 rname = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
15194
15195 child = ddi_get_child(pdip);
15196 while (child) {
15197 rval = mptsas_name_child(child, rname, SCSI_MAXNAMELEN);
15198 if (rval != DDI_SUCCESS) {
15199 child = ddi_get_next_sibling(child);
15200 bzero(rname, SCSI_MAXNAMELEN);
15201 continue;
15202 }
15203
15204 if (strcmp(rname, name) == 0) {
15205 break;
15206 }
15207 child = ddi_get_next_sibling(child);
15208 bzero(rname, SCSI_MAXNAMELEN);
15209 }
15210
15211 kmem_free(rname, SCSI_MAXNAMELEN);
15212
15213 return (child);
15214 }
15215
15216
15217 static dev_info_t *
mptsas_find_child_addr(dev_info_t * pdip,uint64_t sasaddr,int lun)15218 mptsas_find_child_addr(dev_info_t *pdip, uint64_t sasaddr, int lun)
15219 {
15220 dev_info_t *child = NULL;
15221 char *name = NULL;
15222 char *addr = NULL;
15223
15224 name = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
15225 addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
15226 (void) sprintf(name, "%016"PRIx64, sasaddr);
15227 (void) sprintf(addr, "w%s,%x", name, lun);
15228 child = mptsas_find_child(pdip, addr);
15229 kmem_free(name, SCSI_MAXNAMELEN);
15230 kmem_free(addr, SCSI_MAXNAMELEN);
15231 return (child);
15232 }
15233
15234 static dev_info_t *
mptsas_find_child_phy(dev_info_t * pdip,uint8_t phy)15235 mptsas_find_child_phy(dev_info_t *pdip, uint8_t phy)
15236 {
15237 dev_info_t *child;
15238 char *addr;
15239
15240 addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
15241 (void) sprintf(addr, "p%x,0", phy);
15242 child = mptsas_find_child(pdip, addr);
15243 kmem_free(addr, SCSI_MAXNAMELEN);
15244 return (child);
15245 }
15246
15247 static mdi_pathinfo_t *
mptsas_find_path_phy(dev_info_t * pdip,uint8_t phy)15248 mptsas_find_path_phy(dev_info_t *pdip, uint8_t phy)
15249 {
15250 mdi_pathinfo_t *path;
15251 char *addr = NULL;
15252
15253 addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
15254 (void) sprintf(addr, "p%x,0", phy);
15255 path = mdi_pi_find(pdip, NULL, addr);
15256 kmem_free(addr, SCSI_MAXNAMELEN);
15257 return (path);
15258 }
15259
15260 static mdi_pathinfo_t *
mptsas_find_path_addr(dev_info_t * parent,uint64_t sasaddr,int lun)15261 mptsas_find_path_addr(dev_info_t *parent, uint64_t sasaddr, int lun)
15262 {
15263 mdi_pathinfo_t *path;
15264 char *name = NULL;
15265 char *addr = NULL;
15266
15267 name = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
15268 addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
15269 (void) sprintf(name, "%016"PRIx64, sasaddr);
15270 (void) sprintf(addr, "w%s,%x", name, lun);
15271 path = mdi_pi_find(parent, NULL, addr);
15272 kmem_free(name, SCSI_MAXNAMELEN);
15273 kmem_free(addr, SCSI_MAXNAMELEN);
15274
15275 return (path);
15276 }
15277
15278 static int
mptsas_create_lun(dev_info_t * pdip,struct scsi_inquiry * sd_inq,dev_info_t ** lun_dip,mptsas_target_t * ptgt,int lun)15279 mptsas_create_lun(dev_info_t *pdip, struct scsi_inquiry *sd_inq,
15280 dev_info_t **lun_dip, mptsas_target_t *ptgt, int lun)
15281 {
15282 int i = 0;
15283 uchar_t *inq83 = NULL;
15284 int inq83_len1 = 0xFF;
15285 int inq83_len = 0;
15286 int rval = DDI_FAILURE;
15287 ddi_devid_t devid;
15288 char *guid = NULL;
15289 int target = ptgt->m_devhdl;
15290 mdi_pathinfo_t *pip = NULL;
15291 mptsas_t *mpt = DIP2MPT(pdip);
15292
15293 /*
15294 * For DVD/CD ROM and tape devices and optical
15295 * devices, we won't try to enumerate them under
15296 * scsi_vhci, so no need to try page83
15297 */
15298 if (sd_inq && (sd_inq->inq_dtype == DTYPE_RODIRECT ||
15299 sd_inq->inq_dtype == DTYPE_OPTICAL ||
15300 sd_inq->inq_dtype == DTYPE_ESI))
15301 goto create_lun;
15302
15303 /*
15304 * The LCA returns good SCSI status, but corrupt page 83 data the first
15305 * time it is queried. The solution is to keep trying to request page83
15306 * and verify the GUID is not (DDI_NOT_WELL_FORMED) in
15307 * mptsas_inq83_retry_timeout seconds. If the timeout expires, driver
15308 * give up to get VPD page at this stage and fail the enumeration.
15309 */
15310
15311 inq83 = kmem_zalloc(inq83_len1, KM_SLEEP);
15312
15313 for (i = 0; i < mptsas_inq83_retry_timeout; i++) {
15314 rval = mptsas_inquiry(mpt, ptgt, lun, 0x83, inq83,
15315 inq83_len1, &inq83_len, 1);
15316 if (rval != 0) {
15317 mptsas_log(mpt, CE_WARN, "!mptsas request inquiry page "
15318 "0x83 for target:%x, lun:%x failed!", target, lun);
15319 if (mptsas_physical_bind_failed_page_83 != B_FALSE)
15320 goto create_lun;
15321 goto out;
15322 }
15323 /*
15324 * create DEVID from inquiry data
15325 */
15326 if ((rval = ddi_devid_scsi_encode(
15327 DEVID_SCSI_ENCODE_VERSION_LATEST, NULL, (uchar_t *)sd_inq,
15328 sizeof (struct scsi_inquiry), NULL, 0, inq83,
15329 (size_t)inq83_len, &devid)) == DDI_SUCCESS) {
15330 /*
15331 * extract GUID from DEVID
15332 */
15333 guid = ddi_devid_to_guid(devid);
15334
15335 /*
15336 * Do not enable MPXIO if the strlen(guid) is greater
15337 * than MPTSAS_MAX_GUID_LEN, this constrain would be
15338 * handled by framework later.
15339 */
15340 if (guid && (strlen(guid) > MPTSAS_MAX_GUID_LEN)) {
15341 ddi_devid_free_guid(guid);
15342 guid = NULL;
15343 if (mpt->m_mpxio_enable == TRUE) {
15344 mptsas_log(mpt, CE_NOTE, "!Target:%x, "
15345 "lun:%x doesn't have a valid GUID, "
15346 "multipathing for this drive is "
15347 "not enabled", target, lun);
15348 }
15349 }
15350
15351 /*
15352 * devid no longer needed
15353 */
15354 ddi_devid_free(devid);
15355 break;
15356 } else if (rval == DDI_NOT_WELL_FORMED) {
15357 /*
15358 * return value of ddi_devid_scsi_encode equal to
15359 * DDI_NOT_WELL_FORMED means DEVID_RETRY, it worth
15360 * to retry inquiry page 0x83 and get GUID.
15361 */
15362 NDBG20(("Not well formed devid, retry..."));
15363 delay(1 * drv_usectohz(1000000));
15364 continue;
15365 } else {
15366 mptsas_log(mpt, CE_WARN, "!Encode devid failed for "
15367 "path target:%x, lun:%x", target, lun);
15368 rval = DDI_FAILURE;
15369 goto create_lun;
15370 }
15371 }
15372
15373 if (i == mptsas_inq83_retry_timeout) {
15374 mptsas_log(mpt, CE_WARN, "!Repeated page83 requests timeout "
15375 "for path target:%x, lun:%x", target, lun);
15376 }
15377
15378 rval = DDI_FAILURE;
15379
15380 create_lun:
15381 if ((guid != NULL) && (mpt->m_mpxio_enable == TRUE)) {
15382 rval = mptsas_create_virt_lun(pdip, sd_inq, guid, lun_dip, &pip,
15383 ptgt, lun);
15384 }
15385 if (rval != DDI_SUCCESS) {
15386 rval = mptsas_create_phys_lun(pdip, sd_inq, guid, lun_dip,
15387 ptgt, lun);
15388
15389 }
15390 out:
15391 if (guid != NULL) {
15392 /*
15393 * guid no longer needed
15394 */
15395 ddi_devid_free_guid(guid);
15396 }
15397 if (inq83 != NULL)
15398 kmem_free(inq83, inq83_len1);
15399 return (rval);
15400 }
15401
15402 static int
mptsas_create_virt_lun(dev_info_t * pdip,struct scsi_inquiry * inq,char * guid,dev_info_t ** lun_dip,mdi_pathinfo_t ** pip,mptsas_target_t * ptgt,int lun)15403 mptsas_create_virt_lun(dev_info_t *pdip, struct scsi_inquiry *inq, char *guid,
15404 dev_info_t **lun_dip, mdi_pathinfo_t **pip, mptsas_target_t *ptgt, int lun)
15405 {
15406 int target;
15407 char *nodename = NULL;
15408 char **compatible = NULL;
15409 int ncompatible = 0;
15410 int mdi_rtn = MDI_FAILURE;
15411 int rval = DDI_FAILURE;
15412 char *old_guid = NULL;
15413 mptsas_t *mpt = DIP2MPT(pdip);
15414 char *lun_addr = NULL;
15415 char *wwn_str = NULL;
15416 char *attached_wwn_str = NULL;
15417 char *component = NULL;
15418 uint8_t phy = 0xFF;
15419 uint64_t sas_wwn;
15420 int64_t lun64 = 0;
15421 uint32_t devinfo;
15422 uint16_t dev_hdl;
15423 uint16_t pdev_hdl;
15424 uint64_t dev_sas_wwn;
15425 uint64_t pdev_sas_wwn;
15426 uint32_t pdev_info;
15427 uint8_t physport;
15428 uint8_t phy_id;
15429 uint32_t page_address;
15430 uint16_t bay_num, enclosure, io_flags;
15431 char pdev_wwn_str[MPTSAS_WWN_STRLEN];
15432 uint32_t dev_info;
15433
15434 mutex_enter(&mpt->m_mutex);
15435 target = ptgt->m_devhdl;
15436 sas_wwn = ptgt->m_addr.mta_wwn;
15437 devinfo = ptgt->m_deviceinfo;
15438 phy = ptgt->m_phynum;
15439 mutex_exit(&mpt->m_mutex);
15440
15441 if (sas_wwn) {
15442 *pip = mptsas_find_path_addr(pdip, sas_wwn, lun);
15443 } else {
15444 *pip = mptsas_find_path_phy(pdip, phy);
15445 }
15446
15447 if (*pip != NULL) {
15448 *lun_dip = MDI_PI(*pip)->pi_client->ct_dip;
15449 ASSERT(*lun_dip != NULL);
15450 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, *lun_dip,
15451 (DDI_PROP_DONTPASS | DDI_PROP_NOTPROM),
15452 MDI_CLIENT_GUID_PROP, &old_guid) == DDI_SUCCESS) {
15453 if (strncmp(guid, old_guid, strlen(guid)) == 0) {
15454 /*
15455 * Same path back online again.
15456 */
15457 (void) ddi_prop_free(old_guid);
15458 if ((!MDI_PI_IS_ONLINE(*pip)) &&
15459 (!MDI_PI_IS_STANDBY(*pip)) &&
15460 (ptgt->m_tgt_unconfigured == 0)) {
15461 rval = mdi_pi_online(*pip, 0);
15462 } else {
15463 rval = DDI_SUCCESS;
15464 }
15465 if (rval != DDI_SUCCESS) {
15466 mptsas_log(mpt, CE_WARN, "path:target: "
15467 "%x, lun:%x online failed!", target,
15468 lun);
15469 *pip = NULL;
15470 *lun_dip = NULL;
15471 }
15472 return (rval);
15473 } else {
15474 /*
15475 * The GUID of the LUN has changed which maybe
15476 * because customer mapped another volume to the
15477 * same LUN.
15478 */
15479 mptsas_log(mpt, CE_WARN, "The GUID of the "
15480 "target:%x, lun:%x was changed, maybe "
15481 "because someone mapped another volume "
15482 "to the same LUN", target, lun);
15483 (void) ddi_prop_free(old_guid);
15484 if (!MDI_PI_IS_OFFLINE(*pip)) {
15485 rval = mdi_pi_offline(*pip, 0);
15486 if (rval != MDI_SUCCESS) {
15487 mptsas_log(mpt, CE_WARN, "path:"
15488 "target:%x, lun:%x offline "
15489 "failed!", target, lun);
15490 *pip = NULL;
15491 *lun_dip = NULL;
15492 return (DDI_FAILURE);
15493 }
15494 }
15495 if (mdi_pi_free(*pip, 0) != MDI_SUCCESS) {
15496 mptsas_log(mpt, CE_WARN, "path:target:"
15497 "%x, lun:%x free failed!", target,
15498 lun);
15499 *pip = NULL;
15500 *lun_dip = NULL;
15501 return (DDI_FAILURE);
15502 }
15503 }
15504 } else {
15505 mptsas_log(mpt, CE_WARN, "Can't get client-guid "
15506 "property for path:target:%x, lun:%x", target, lun);
15507 *pip = NULL;
15508 *lun_dip = NULL;
15509 return (DDI_FAILURE);
15510 }
15511 }
15512 scsi_hba_nodename_compatible_get(inq, NULL,
15513 inq->inq_dtype, NULL, &nodename, &compatible, &ncompatible);
15514
15515 /*
15516 * if nodename can't be determined then print a message and skip it
15517 */
15518 if (nodename == NULL) {
15519 mptsas_log(mpt, CE_WARN, "mptsas driver found no compatible "
15520 "driver for target%d lun %d dtype:0x%02x", target, lun,
15521 inq->inq_dtype);
15522 return (DDI_FAILURE);
15523 }
15524
15525 wwn_str = kmem_zalloc(MPTSAS_WWN_STRLEN, KM_SLEEP);
15526 /* The property is needed by MPAPI */
15527 (void) sprintf(wwn_str, "%016"PRIx64, sas_wwn);
15528
15529 lun_addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
15530 if (guid) {
15531 (void) sprintf(lun_addr, "w%s,%x", wwn_str, lun);
15532 (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn);
15533 } else {
15534 (void) sprintf(lun_addr, "p%x,%x", phy, lun);
15535 (void) sprintf(wwn_str, "p%x", phy);
15536 }
15537
15538 mdi_rtn = mdi_pi_alloc_compatible(pdip, nodename,
15539 guid, lun_addr, compatible, ncompatible,
15540 0, pip);
15541 if (mdi_rtn == MDI_SUCCESS) {
15542
15543 if (mdi_prop_update_string(*pip, MDI_GUID,
15544 guid) != DDI_SUCCESS) {
15545 mptsas_log(mpt, CE_WARN, "mptsas driver unable to "
15546 "create prop for target %d lun %d (MDI_GUID)",
15547 target, lun);
15548 mdi_rtn = MDI_FAILURE;
15549 goto virt_create_done;
15550 }
15551
15552 if (mdi_prop_update_int(*pip, LUN_PROP,
15553 lun) != DDI_SUCCESS) {
15554 mptsas_log(mpt, CE_WARN, "mptsas driver unable to "
15555 "create prop for target %d lun %d (LUN_PROP)",
15556 target, lun);
15557 mdi_rtn = MDI_FAILURE;
15558 goto virt_create_done;
15559 }
15560 lun64 = (int64_t)lun;
15561 if (mdi_prop_update_int64(*pip, LUN64_PROP,
15562 lun64) != DDI_SUCCESS) {
15563 mptsas_log(mpt, CE_WARN, "mptsas driver unable to "
15564 "create prop for target %d (LUN64_PROP)",
15565 target);
15566 mdi_rtn = MDI_FAILURE;
15567 goto virt_create_done;
15568 }
15569 if (mdi_prop_update_string_array(*pip, "compatible",
15570 compatible, ncompatible) !=
15571 DDI_PROP_SUCCESS) {
15572 mptsas_log(mpt, CE_WARN, "mptsas driver unable to "
15573 "create prop for target %d lun %d (COMPATIBLE)",
15574 target, lun);
15575 mdi_rtn = MDI_FAILURE;
15576 goto virt_create_done;
15577 }
15578 if (sas_wwn && (mdi_prop_update_string(*pip,
15579 SCSI_ADDR_PROP_TARGET_PORT, wwn_str) != DDI_PROP_SUCCESS)) {
15580 mptsas_log(mpt, CE_WARN, "mptsas driver unable to "
15581 "create prop for target %d lun %d "
15582 "(target-port)", target, lun);
15583 mdi_rtn = MDI_FAILURE;
15584 goto virt_create_done;
15585 } else if ((sas_wwn == 0) && (mdi_prop_update_int(*pip,
15586 "sata-phy", phy) != DDI_PROP_SUCCESS)) {
15587 /*
15588 * Direct attached SATA device without DeviceName
15589 */
15590 mptsas_log(mpt, CE_WARN, "mptsas driver unable to "
15591 "create prop for SAS target %d lun %d "
15592 "(sata-phy)", target, lun);
15593 mdi_rtn = MDI_FAILURE;
15594 goto virt_create_done;
15595 }
15596 mutex_enter(&mpt->m_mutex);
15597
15598 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
15599 MPI2_SAS_DEVICE_PGAD_FORM_MASK) |
15600 (uint32_t)ptgt->m_devhdl;
15601 rval = mptsas_get_sas_device_page0(mpt, page_address,
15602 &dev_hdl, &dev_sas_wwn, &dev_info, &physport,
15603 &phy_id, &pdev_hdl, &bay_num, &enclosure, &io_flags);
15604 if (rval != DDI_SUCCESS) {
15605 mutex_exit(&mpt->m_mutex);
15606 mptsas_log(mpt, CE_WARN, "mptsas unable to get "
15607 "parent device for handle %d", page_address);
15608 mdi_rtn = MDI_FAILURE;
15609 goto virt_create_done;
15610 }
15611
15612 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
15613 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | (uint32_t)pdev_hdl;
15614 rval = mptsas_get_sas_device_page0(mpt, page_address,
15615 &dev_hdl, &pdev_sas_wwn, &pdev_info, &physport,
15616 &phy_id, &pdev_hdl, &bay_num, &enclosure, &io_flags);
15617 if (rval != DDI_SUCCESS) {
15618 mutex_exit(&mpt->m_mutex);
15619 mptsas_log(mpt, CE_WARN, "mptsas unable to get"
15620 "device info for handle %d", page_address);
15621 mdi_rtn = MDI_FAILURE;
15622 goto virt_create_done;
15623 }
15624
15625 mutex_exit(&mpt->m_mutex);
15626
15627 /*
15628 * If this device direct attached to the controller
15629 * set the attached-port to the base wwid
15630 */
15631 if ((ptgt->m_deviceinfo & DEVINFO_DIRECT_ATTACHED)
15632 != DEVINFO_DIRECT_ATTACHED) {
15633 (void) sprintf(pdev_wwn_str, "w%016"PRIx64,
15634 pdev_sas_wwn);
15635 } else {
15636 /*
15637 * Update the iport's attached-port to guid
15638 */
15639 if (sas_wwn == 0) {
15640 (void) sprintf(wwn_str, "p%x", phy);
15641 } else {
15642 (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn);
15643 }
15644 if (ddi_prop_update_string(DDI_DEV_T_NONE,
15645 pdip, SCSI_ADDR_PROP_ATTACHED_PORT, wwn_str) !=
15646 DDI_PROP_SUCCESS) {
15647 mptsas_log(mpt, CE_WARN,
15648 "mptsas unable to create "
15649 "property for iport target-port"
15650 " %s (sas_wwn)",
15651 wwn_str);
15652 mdi_rtn = MDI_FAILURE;
15653 goto virt_create_done;
15654 }
15655
15656 (void) sprintf(pdev_wwn_str, "w%016"PRIx64,
15657 mpt->un.m_base_wwid);
15658 }
15659
15660 if (IS_SATA_DEVICE(ptgt->m_deviceinfo)) {
15661 char uabuf[SCSI_WWN_BUFLEN];
15662
15663 if (scsi_wwn_to_wwnstr(dev_sas_wwn, 1, uabuf) == NULL) {
15664 mptsas_log(mpt, CE_WARN,
15665 "mptsas unable to format SATA bridge WWN");
15666 mdi_rtn = MDI_FAILURE;
15667 goto virt_create_done;
15668 }
15669
15670 if (mdi_prop_update_string(*pip,
15671 SCSI_ADDR_PROP_BRIDGE_PORT, uabuf) !=
15672 DDI_SUCCESS) {
15673 mptsas_log(mpt, CE_WARN,
15674 "mptsas unable to create SCSI bridge port "
15675 "property for SATA device");
15676 mdi_rtn = MDI_FAILURE;
15677 goto virt_create_done;
15678 }
15679 }
15680
15681 if (mdi_prop_update_string(*pip,
15682 SCSI_ADDR_PROP_ATTACHED_PORT, pdev_wwn_str) !=
15683 DDI_PROP_SUCCESS) {
15684 mptsas_log(mpt, CE_WARN, "mptsas unable to create "
15685 "property for iport attached-port %s (sas_wwn)",
15686 attached_wwn_str);
15687 mdi_rtn = MDI_FAILURE;
15688 goto virt_create_done;
15689 }
15690
15691
15692 if (inq->inq_dtype == 0) {
15693 component = kmem_zalloc(MAXPATHLEN, KM_SLEEP);
15694 /*
15695 * set obp path for pathinfo
15696 */
15697 (void) snprintf(component, MAXPATHLEN,
15698 "disk@%s", lun_addr);
15699
15700 if (mdi_pi_pathname_obp_set(*pip, component) !=
15701 DDI_SUCCESS) {
15702 mptsas_log(mpt, CE_WARN, "mpt_sas driver "
15703 "unable to set obp-path for object %s",
15704 component);
15705 mdi_rtn = MDI_FAILURE;
15706 goto virt_create_done;
15707 }
15708 }
15709
15710 *lun_dip = MDI_PI(*pip)->pi_client->ct_dip;
15711 if (devinfo & (MPI2_SAS_DEVICE_INFO_SATA_DEVICE |
15712 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) {
15713 if ((ndi_prop_update_int(DDI_DEV_T_NONE, *lun_dip,
15714 "pm-capable", 1)) !=
15715 DDI_PROP_SUCCESS) {
15716 mptsas_log(mpt, CE_WARN, "mptsas driver"
15717 "failed to create pm-capable "
15718 "property, target %d", target);
15719 mdi_rtn = MDI_FAILURE;
15720 goto virt_create_done;
15721 }
15722 }
15723 /*
15724 * Create the phy-num property
15725 */
15726 if (mdi_prop_update_int(*pip, "phy-num",
15727 ptgt->m_phynum) != DDI_SUCCESS) {
15728 mptsas_log(mpt, CE_WARN, "mptsas driver unable to "
15729 "create phy-num property for target %d lun %d",
15730 target, lun);
15731 mdi_rtn = MDI_FAILURE;
15732 goto virt_create_done;
15733 }
15734 NDBG20(("new path:%s onlining,", MDI_PI(*pip)->pi_addr));
15735 mdi_rtn = mdi_pi_online(*pip, 0);
15736 if (mdi_rtn == MDI_NOT_SUPPORTED) {
15737 mdi_rtn = MDI_FAILURE;
15738 }
15739 virt_create_done:
15740 if (*pip && mdi_rtn != MDI_SUCCESS) {
15741 (void) mdi_pi_free(*pip, 0);
15742 *pip = NULL;
15743 *lun_dip = NULL;
15744 }
15745 }
15746
15747 scsi_hba_nodename_compatible_free(nodename, compatible);
15748 if (lun_addr != NULL) {
15749 kmem_free(lun_addr, SCSI_MAXNAMELEN);
15750 }
15751 if (wwn_str != NULL) {
15752 kmem_free(wwn_str, MPTSAS_WWN_STRLEN);
15753 }
15754 if (component != NULL) {
15755 kmem_free(component, MAXPATHLEN);
15756 }
15757
15758 return ((mdi_rtn == MDI_SUCCESS) ? DDI_SUCCESS : DDI_FAILURE);
15759 }
15760
15761 static int
mptsas_create_phys_lun(dev_info_t * pdip,struct scsi_inquiry * inq,char * guid,dev_info_t ** lun_dip,mptsas_target_t * ptgt,int lun)15762 mptsas_create_phys_lun(dev_info_t *pdip, struct scsi_inquiry *inq,
15763 char *guid, dev_info_t **lun_dip, mptsas_target_t *ptgt, int lun)
15764 {
15765 int target;
15766 int rval;
15767 int ndi_rtn = NDI_FAILURE;
15768 uint64_t be_sas_wwn;
15769 char *nodename = NULL;
15770 char **compatible = NULL;
15771 int ncompatible = 0;
15772 int instance = 0;
15773 mptsas_t *mpt = DIP2MPT(pdip);
15774 char *wwn_str = NULL;
15775 char *component = NULL;
15776 char *attached_wwn_str = NULL;
15777 uint8_t phy = 0xFF;
15778 uint64_t sas_wwn;
15779 uint32_t devinfo;
15780 uint16_t dev_hdl;
15781 uint16_t pdev_hdl;
15782 uint64_t pdev_sas_wwn;
15783 uint64_t dev_sas_wwn;
15784 uint32_t pdev_info;
15785 uint8_t physport;
15786 uint8_t phy_id;
15787 uint32_t page_address;
15788 uint16_t bay_num, enclosure, io_flags;
15789 char pdev_wwn_str[MPTSAS_WWN_STRLEN];
15790 uint32_t dev_info;
15791 int64_t lun64 = 0;
15792
15793 mutex_enter(&mpt->m_mutex);
15794 target = ptgt->m_devhdl;
15795 sas_wwn = ptgt->m_addr.mta_wwn;
15796 devinfo = ptgt->m_deviceinfo;
15797 phy = ptgt->m_phynum;
15798 mutex_exit(&mpt->m_mutex);
15799
15800 /*
15801 * generate compatible property with binding-set "mpt"
15802 */
15803 scsi_hba_nodename_compatible_get(inq, NULL, inq->inq_dtype, NULL,
15804 &nodename, &compatible, &ncompatible);
15805
15806 /*
15807 * if nodename can't be determined then print a message and skip it
15808 */
15809 if (nodename == NULL) {
15810 mptsas_log(mpt, CE_WARN, "mptsas found no compatible driver "
15811 "for target %d lun %d", target, lun);
15812 return (DDI_FAILURE);
15813 }
15814
15815 ndi_rtn = ndi_devi_alloc(pdip, nodename,
15816 DEVI_SID_NODEID, lun_dip);
15817
15818 /*
15819 * if lun alloc success, set props
15820 */
15821 if (ndi_rtn == NDI_SUCCESS) {
15822
15823 if (ndi_prop_update_int(DDI_DEV_T_NONE,
15824 *lun_dip, LUN_PROP, lun) !=
15825 DDI_PROP_SUCCESS) {
15826 mptsas_log(mpt, CE_WARN, "mptsas unable to create "
15827 "property for target %d lun %d (LUN_PROP)",
15828 target, lun);
15829 ndi_rtn = NDI_FAILURE;
15830 goto phys_create_done;
15831 }
15832
15833 lun64 = (int64_t)lun;
15834 if (ndi_prop_update_int64(DDI_DEV_T_NONE,
15835 *lun_dip, LUN64_PROP, lun64) !=
15836 DDI_PROP_SUCCESS) {
15837 mptsas_log(mpt, CE_WARN, "mptsas unable to create "
15838 "property for target %d lun64 %d (LUN64_PROP)",
15839 target, lun);
15840 ndi_rtn = NDI_FAILURE;
15841 goto phys_create_done;
15842 }
15843 if (ndi_prop_update_string_array(DDI_DEV_T_NONE,
15844 *lun_dip, "compatible", compatible, ncompatible)
15845 != DDI_PROP_SUCCESS) {
15846 mptsas_log(mpt, CE_WARN, "mptsas unable to create "
15847 "property for target %d lun %d (COMPATIBLE)",
15848 target, lun);
15849 ndi_rtn = NDI_FAILURE;
15850 goto phys_create_done;
15851 }
15852
15853 /*
15854 * We need the SAS WWN for non-multipath devices, so
15855 * we'll use the same property as that multipathing
15856 * devices need to present for MPAPI. If we don't have
15857 * a WWN (e.g. parallel SCSI), don't create the prop.
15858 */
15859 wwn_str = kmem_zalloc(MPTSAS_WWN_STRLEN, KM_SLEEP);
15860 (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn);
15861 if (sas_wwn && ndi_prop_update_string(DDI_DEV_T_NONE,
15862 *lun_dip, SCSI_ADDR_PROP_TARGET_PORT, wwn_str)
15863 != DDI_PROP_SUCCESS) {
15864 mptsas_log(mpt, CE_WARN, "mptsas unable to "
15865 "create property for SAS target %d lun %d "
15866 "(target-port)", target, lun);
15867 ndi_rtn = NDI_FAILURE;
15868 goto phys_create_done;
15869 }
15870
15871 be_sas_wwn = BE_64(sas_wwn);
15872 if (sas_wwn && ndi_prop_update_byte_array(
15873 DDI_DEV_T_NONE, *lun_dip, "port-wwn",
15874 (uchar_t *)&be_sas_wwn, 8) != DDI_PROP_SUCCESS) {
15875 mptsas_log(mpt, CE_WARN, "mptsas unable to "
15876 "create property for SAS target %d lun %d "
15877 "(port-wwn)", target, lun);
15878 ndi_rtn = NDI_FAILURE;
15879 goto phys_create_done;
15880 } else if ((sas_wwn == 0) && (ndi_prop_update_int(
15881 DDI_DEV_T_NONE, *lun_dip, "sata-phy", phy) !=
15882 DDI_PROP_SUCCESS)) {
15883 /*
15884 * Direct attached SATA device without DeviceName
15885 */
15886 mptsas_log(mpt, CE_WARN, "mptsas unable to "
15887 "create property for SAS target %d lun %d "
15888 "(sata-phy)", target, lun);
15889 ndi_rtn = NDI_FAILURE;
15890 goto phys_create_done;
15891 }
15892
15893 if (ndi_prop_create_boolean(DDI_DEV_T_NONE,
15894 *lun_dip, SAS_PROP) != DDI_PROP_SUCCESS) {
15895 mptsas_log(mpt, CE_WARN, "mptsas unable to"
15896 "create property for SAS target %d lun %d"
15897 " (SAS_PROP)", target, lun);
15898 ndi_rtn = NDI_FAILURE;
15899 goto phys_create_done;
15900 }
15901 if (guid && (ndi_prop_update_string(DDI_DEV_T_NONE,
15902 *lun_dip, NDI_GUID, guid) != DDI_SUCCESS)) {
15903 mptsas_log(mpt, CE_WARN, "mptsas unable "
15904 "to create guid property for target %d "
15905 "lun %d", target, lun);
15906 ndi_rtn = NDI_FAILURE;
15907 goto phys_create_done;
15908 }
15909
15910 /*
15911 * The following code is to set properties for SM-HBA support,
15912 * it doesn't apply to RAID volumes
15913 */
15914 if (ptgt->m_addr.mta_phymask == 0)
15915 goto phys_raid_lun;
15916
15917 mutex_enter(&mpt->m_mutex);
15918
15919 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
15920 MPI2_SAS_DEVICE_PGAD_FORM_MASK) |
15921 (uint32_t)ptgt->m_devhdl;
15922 rval = mptsas_get_sas_device_page0(mpt, page_address,
15923 &dev_hdl, &dev_sas_wwn, &dev_info,
15924 &physport, &phy_id, &pdev_hdl,
15925 &bay_num, &enclosure, &io_flags);
15926 if (rval != DDI_SUCCESS) {
15927 mutex_exit(&mpt->m_mutex);
15928 mptsas_log(mpt, CE_WARN, "mptsas unable to get"
15929 "parent device for handle %d.", page_address);
15930 ndi_rtn = NDI_FAILURE;
15931 goto phys_create_done;
15932 }
15933
15934 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
15935 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | (uint32_t)pdev_hdl;
15936 rval = mptsas_get_sas_device_page0(mpt, page_address,
15937 &dev_hdl, &pdev_sas_wwn, &pdev_info, &physport,
15938 &phy_id, &pdev_hdl, &bay_num, &enclosure, &io_flags);
15939 if (rval != DDI_SUCCESS) {
15940 mutex_exit(&mpt->m_mutex);
15941 mptsas_log(mpt, CE_WARN, "mptsas unable to create "
15942 "device for handle %d.", page_address);
15943 ndi_rtn = NDI_FAILURE;
15944 goto phys_create_done;
15945 }
15946
15947 mutex_exit(&mpt->m_mutex);
15948
15949 /*
15950 * If this device direct attached to the controller
15951 * set the attached-port to the base wwid
15952 */
15953 if ((ptgt->m_deviceinfo & DEVINFO_DIRECT_ATTACHED)
15954 != DEVINFO_DIRECT_ATTACHED) {
15955 (void) sprintf(pdev_wwn_str, "w%016"PRIx64,
15956 pdev_sas_wwn);
15957 } else {
15958 /*
15959 * Update the iport's attached-port to guid
15960 */
15961 if (sas_wwn == 0) {
15962 (void) sprintf(wwn_str, "p%x", phy);
15963 } else {
15964 (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn);
15965 }
15966 if (ddi_prop_update_string(DDI_DEV_T_NONE,
15967 pdip, SCSI_ADDR_PROP_ATTACHED_PORT, wwn_str) !=
15968 DDI_PROP_SUCCESS) {
15969 mptsas_log(mpt, CE_WARN,
15970 "mptsas unable to create "
15971 "property for iport target-port"
15972 " %s (sas_wwn)",
15973 wwn_str);
15974 ndi_rtn = NDI_FAILURE;
15975 goto phys_create_done;
15976 }
15977
15978 (void) sprintf(pdev_wwn_str, "w%016"PRIx64,
15979 mpt->un.m_base_wwid);
15980 }
15981
15982 if (ndi_prop_update_string(DDI_DEV_T_NONE,
15983 *lun_dip, SCSI_ADDR_PROP_ATTACHED_PORT, pdev_wwn_str) !=
15984 DDI_PROP_SUCCESS) {
15985 mptsas_log(mpt, CE_WARN,
15986 "mptsas unable to create "
15987 "property for iport attached-port %s (sas_wwn)",
15988 attached_wwn_str);
15989 ndi_rtn = NDI_FAILURE;
15990 goto phys_create_done;
15991 }
15992
15993 if (IS_SATA_DEVICE(dev_info)) {
15994 char uabuf[SCSI_WWN_BUFLEN];
15995
15996 if (ndi_prop_update_string(DDI_DEV_T_NONE,
15997 *lun_dip, MPTSAS_VARIANT, "sata") !=
15998 DDI_PROP_SUCCESS) {
15999 mptsas_log(mpt, CE_WARN,
16000 "mptsas unable to create "
16001 "property for device variant ");
16002 ndi_rtn = NDI_FAILURE;
16003 goto phys_create_done;
16004 }
16005
16006 if (scsi_wwn_to_wwnstr(dev_sas_wwn, 1, uabuf) == NULL) {
16007 mptsas_log(mpt, CE_WARN,
16008 "mptsas unable to format SATA bridge WWN");
16009 ndi_rtn = NDI_FAILURE;
16010 goto phys_create_done;
16011 }
16012
16013 if (ndi_prop_update_string(DDI_DEV_T_NONE, *lun_dip,
16014 SCSI_ADDR_PROP_BRIDGE_PORT, uabuf) !=
16015 DDI_PROP_SUCCESS) {
16016 mptsas_log(mpt, CE_WARN,
16017 "mptsas unable to create SCSI bridge port "
16018 "property for SATA device");
16019 ndi_rtn = NDI_FAILURE;
16020 goto phys_create_done;
16021 }
16022 }
16023
16024 if (IS_ATAPI_DEVICE(dev_info)) {
16025 if (ndi_prop_update_string(DDI_DEV_T_NONE,
16026 *lun_dip, MPTSAS_VARIANT, "atapi") !=
16027 DDI_PROP_SUCCESS) {
16028 mptsas_log(mpt, CE_WARN,
16029 "mptsas unable to create "
16030 "property for device variant ");
16031 ndi_rtn = NDI_FAILURE;
16032 goto phys_create_done;
16033 }
16034 }
16035
16036 phys_raid_lun:
16037 /*
16038 * if this is a SAS controller, and the target is a SATA
16039 * drive, set the 'pm-capable' property for sd and if on
16040 * an OPL platform, also check if this is an ATAPI
16041 * device.
16042 */
16043 instance = ddi_get_instance(mpt->m_dip);
16044 if (devinfo & (MPI2_SAS_DEVICE_INFO_SATA_DEVICE |
16045 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) {
16046 NDBG2(("mptsas%d: creating pm-capable property, "
16047 "target %d", instance, target));
16048
16049 if ((ndi_prop_update_int(DDI_DEV_T_NONE,
16050 *lun_dip, "pm-capable", 1)) !=
16051 DDI_PROP_SUCCESS) {
16052 mptsas_log(mpt, CE_WARN, "mptsas "
16053 "failed to create pm-capable "
16054 "property, target %d", target);
16055 ndi_rtn = NDI_FAILURE;
16056 goto phys_create_done;
16057 }
16058
16059 }
16060
16061 if ((inq->inq_dtype == 0) || (inq->inq_dtype == 5)) {
16062 /*
16063 * add 'obp-path' properties for devinfo
16064 */
16065 bzero(wwn_str, sizeof (wwn_str));
16066 (void) sprintf(wwn_str, "%016"PRIx64, sas_wwn);
16067 component = kmem_zalloc(MAXPATHLEN, KM_SLEEP);
16068 if (guid) {
16069 (void) snprintf(component, MAXPATHLEN,
16070 "disk@w%s,%x", wwn_str, lun);
16071 } else {
16072 (void) snprintf(component, MAXPATHLEN,
16073 "disk@p%x,%x", phy, lun);
16074 }
16075 if (ddi_pathname_obp_set(*lun_dip, component)
16076 != DDI_SUCCESS) {
16077 mptsas_log(mpt, CE_WARN, "mpt_sas driver "
16078 "unable to set obp-path for SAS "
16079 "object %s", component);
16080 ndi_rtn = NDI_FAILURE;
16081 goto phys_create_done;
16082 }
16083 }
16084 /*
16085 * Create the phy-num property for non-raid disk
16086 */
16087 if (ptgt->m_addr.mta_phymask != 0) {
16088 if (ndi_prop_update_int(DDI_DEV_T_NONE,
16089 *lun_dip, "phy-num", ptgt->m_phynum) !=
16090 DDI_PROP_SUCCESS) {
16091 mptsas_log(mpt, CE_WARN, "mptsas driver "
16092 "failed to create phy-num property for "
16093 "target %d", target);
16094 ndi_rtn = NDI_FAILURE;
16095 goto phys_create_done;
16096 }
16097 }
16098 phys_create_done:
16099 /*
16100 * If props were setup ok, online the lun
16101 */
16102 if (ndi_rtn == NDI_SUCCESS) {
16103 /*
16104 * Try to online the new node
16105 */
16106 ndi_rtn = ndi_devi_online(*lun_dip, NDI_ONLINE_ATTACH);
16107 }
16108
16109 /*
16110 * If success set rtn flag, else unwire alloc'd lun
16111 */
16112 if (ndi_rtn != NDI_SUCCESS) {
16113 NDBG12(("mptsas driver unable to online "
16114 "target %d lun %d", target, lun));
16115 ndi_prop_remove_all(*lun_dip);
16116 (void) ndi_devi_free(*lun_dip);
16117 *lun_dip = NULL;
16118 }
16119 }
16120
16121 scsi_hba_nodename_compatible_free(nodename, compatible);
16122
16123 if (wwn_str != NULL) {
16124 kmem_free(wwn_str, MPTSAS_WWN_STRLEN);
16125 }
16126 if (component != NULL) {
16127 kmem_free(component, MAXPATHLEN);
16128 }
16129
16130
16131 return ((ndi_rtn == NDI_SUCCESS) ? DDI_SUCCESS : DDI_FAILURE);
16132 }
16133
16134 static int
mptsas_probe_smp(dev_info_t * pdip,uint64_t wwn)16135 mptsas_probe_smp(dev_info_t *pdip, uint64_t wwn)
16136 {
16137 mptsas_t *mpt = DIP2MPT(pdip);
16138 struct smp_device smp_sd;
16139
16140 /* XXX An HBA driver should not be allocating an smp_device. */
16141 bzero(&smp_sd, sizeof (struct smp_device));
16142 smp_sd.smp_sd_address.smp_a_hba_tran = mpt->m_smptran;
16143 bcopy(&wwn, smp_sd.smp_sd_address.smp_a_wwn, SAS_WWN_BYTE_SIZE);
16144
16145 if (smp_probe(&smp_sd) != DDI_PROBE_SUCCESS)
16146 return (NDI_FAILURE);
16147 return (NDI_SUCCESS);
16148 }
16149
16150 static int
mptsas_config_smp(dev_info_t * pdip,uint64_t sas_wwn,dev_info_t ** smp_dip)16151 mptsas_config_smp(dev_info_t *pdip, uint64_t sas_wwn, dev_info_t **smp_dip)
16152 {
16153 mptsas_t *mpt = DIP2MPT(pdip);
16154 mptsas_smp_t *psmp = NULL;
16155 int rval;
16156 int phymask;
16157
16158 /*
16159 * Get the physical port associated to the iport
16160 * PHYMASK TODO
16161 */
16162 phymask = ddi_prop_get_int(DDI_DEV_T_ANY, pdip, 0,
16163 "phymask", 0);
16164 /*
16165 * Find the smp node in hash table with specified sas address and
16166 * physical port
16167 */
16168 psmp = mptsas_wwid_to_psmp(mpt, phymask, sas_wwn);
16169 if (psmp == NULL) {
16170 return (DDI_FAILURE);
16171 }
16172
16173 rval = mptsas_online_smp(pdip, psmp, smp_dip);
16174
16175 return (rval);
16176 }
16177
16178 static int
mptsas_online_smp(dev_info_t * pdip,mptsas_smp_t * smp_node,dev_info_t ** smp_dip)16179 mptsas_online_smp(dev_info_t *pdip, mptsas_smp_t *smp_node,
16180 dev_info_t **smp_dip)
16181 {
16182 char wwn_str[MPTSAS_WWN_STRLEN];
16183 char attached_wwn_str[MPTSAS_WWN_STRLEN];
16184 int ndi_rtn = NDI_FAILURE;
16185 int rval = 0;
16186 mptsas_smp_t dev_info;
16187 uint32_t page_address;
16188 mptsas_t *mpt = DIP2MPT(pdip);
16189 uint16_t dev_hdl;
16190 uint64_t sas_wwn;
16191 uint64_t smp_sas_wwn;
16192 uint8_t physport;
16193 uint8_t phy_id;
16194 uint16_t pdev_hdl;
16195 uint8_t numphys = 0;
16196 uint16_t i = 0;
16197 char phymask[MPTSAS_MAX_PHYS];
16198 char *iport = NULL;
16199 mptsas_phymask_t phy_mask = 0;
16200 uint16_t attached_devhdl;
16201 uint16_t bay_num, enclosure, io_flags;
16202
16203 (void) sprintf(wwn_str, "%"PRIx64, smp_node->m_addr.mta_wwn);
16204
16205 /*
16206 * Probe smp device, prevent the node of removed device from being
16207 * configured succesfully
16208 */
16209 if (mptsas_probe_smp(pdip, smp_node->m_addr.mta_wwn) != NDI_SUCCESS) {
16210 return (DDI_FAILURE);
16211 }
16212
16213 if ((*smp_dip = mptsas_find_smp_child(pdip, wwn_str)) != NULL) {
16214 return (DDI_SUCCESS);
16215 }
16216
16217 ndi_rtn = ndi_devi_alloc(pdip, "smp", DEVI_SID_NODEID, smp_dip);
16218
16219 /*
16220 * if lun alloc success, set props
16221 */
16222 if (ndi_rtn == NDI_SUCCESS) {
16223 /*
16224 * Set the flavor of the child to be SMP flavored
16225 */
16226 ndi_flavor_set(*smp_dip, SCSA_FLAVOR_SMP);
16227
16228 if (ndi_prop_update_string(DDI_DEV_T_NONE,
16229 *smp_dip, SMP_WWN, wwn_str) !=
16230 DDI_PROP_SUCCESS) {
16231 mptsas_log(mpt, CE_WARN, "mptsas unable to create "
16232 "property for smp device %s (sas_wwn)",
16233 wwn_str);
16234 ndi_rtn = NDI_FAILURE;
16235 goto smp_create_done;
16236 }
16237 (void) sprintf(wwn_str, "w%"PRIx64, smp_node->m_addr.mta_wwn);
16238 if (ndi_prop_update_string(DDI_DEV_T_NONE,
16239 *smp_dip, SCSI_ADDR_PROP_TARGET_PORT, wwn_str) !=
16240 DDI_PROP_SUCCESS) {
16241 mptsas_log(mpt, CE_WARN, "mptsas unable to create "
16242 "property for iport target-port %s (sas_wwn)",
16243 wwn_str);
16244 ndi_rtn = NDI_FAILURE;
16245 goto smp_create_done;
16246 }
16247
16248 mutex_enter(&mpt->m_mutex);
16249
16250 page_address = (MPI2_SAS_EXPAND_PGAD_FORM_HNDL &
16251 MPI2_SAS_EXPAND_PGAD_FORM_MASK) | smp_node->m_devhdl;
16252 rval = mptsas_get_sas_expander_page0(mpt, page_address,
16253 &dev_info);
16254 if (rval != DDI_SUCCESS) {
16255 mutex_exit(&mpt->m_mutex);
16256 mptsas_log(mpt, CE_WARN,
16257 "mptsas unable to get expander "
16258 "parent device info for %x", page_address);
16259 ndi_rtn = NDI_FAILURE;
16260 goto smp_create_done;
16261 }
16262
16263 smp_node->m_pdevhdl = dev_info.m_pdevhdl;
16264 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
16265 MPI2_SAS_DEVICE_PGAD_FORM_MASK) |
16266 (uint32_t)dev_info.m_pdevhdl;
16267 rval = mptsas_get_sas_device_page0(mpt, page_address,
16268 &dev_hdl, &sas_wwn, &smp_node->m_pdevinfo, &physport,
16269 &phy_id, &pdev_hdl, &bay_num, &enclosure, &io_flags);
16270 if (rval != DDI_SUCCESS) {
16271 mutex_exit(&mpt->m_mutex);
16272 mptsas_log(mpt, CE_WARN, "mptsas unable to get "
16273 "device info for %x", page_address);
16274 ndi_rtn = NDI_FAILURE;
16275 goto smp_create_done;
16276 }
16277
16278 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
16279 MPI2_SAS_DEVICE_PGAD_FORM_MASK) |
16280 (uint32_t)dev_info.m_devhdl;
16281 rval = mptsas_get_sas_device_page0(mpt, page_address,
16282 &dev_hdl, &smp_sas_wwn, &smp_node->m_deviceinfo,
16283 &physport, &phy_id, &pdev_hdl, &bay_num, &enclosure,
16284 &io_flags);
16285 if (rval != DDI_SUCCESS) {
16286 mutex_exit(&mpt->m_mutex);
16287 mptsas_log(mpt, CE_WARN, "mptsas unable to get "
16288 "device info for %x", page_address);
16289 ndi_rtn = NDI_FAILURE;
16290 goto smp_create_done;
16291 }
16292 mutex_exit(&mpt->m_mutex);
16293
16294 /*
16295 * If this smp direct attached to the controller
16296 * set the attached-port to the base wwid
16297 */
16298 if ((smp_node->m_deviceinfo & DEVINFO_DIRECT_ATTACHED)
16299 != DEVINFO_DIRECT_ATTACHED) {
16300 (void) sprintf(attached_wwn_str, "w%016"PRIx64,
16301 sas_wwn);
16302 } else {
16303 (void) sprintf(attached_wwn_str, "w%016"PRIx64,
16304 mpt->un.m_base_wwid);
16305 }
16306
16307 if (ndi_prop_update_string(DDI_DEV_T_NONE,
16308 *smp_dip, SCSI_ADDR_PROP_ATTACHED_PORT, attached_wwn_str) !=
16309 DDI_PROP_SUCCESS) {
16310 mptsas_log(mpt, CE_WARN, "mptsas unable to create "
16311 "property for smp attached-port %s (sas_wwn)",
16312 attached_wwn_str);
16313 ndi_rtn = NDI_FAILURE;
16314 goto smp_create_done;
16315 }
16316
16317 if (ndi_prop_create_boolean(DDI_DEV_T_NONE,
16318 *smp_dip, SMP_PROP) != DDI_PROP_SUCCESS) {
16319 mptsas_log(mpt, CE_WARN, "mptsas unable to "
16320 "create property for SMP %s (SMP_PROP) ",
16321 wwn_str);
16322 ndi_rtn = NDI_FAILURE;
16323 goto smp_create_done;
16324 }
16325
16326 /*
16327 * check the smp to see whether it direct
16328 * attached to the controller
16329 */
16330 if ((smp_node->m_deviceinfo & DEVINFO_DIRECT_ATTACHED)
16331 != DEVINFO_DIRECT_ATTACHED) {
16332 goto smp_create_done;
16333 }
16334 numphys = ddi_prop_get_int(DDI_DEV_T_ANY, pdip,
16335 DDI_PROP_DONTPASS, MPTSAS_NUM_PHYS, -1);
16336 if (numphys > 0) {
16337 goto smp_create_done;
16338 }
16339 /*
16340 * this iport is an old iport, we need to
16341 * reconfig the props for it.
16342 */
16343 if (ddi_prop_update_int(DDI_DEV_T_NONE, pdip,
16344 MPTSAS_VIRTUAL_PORT, 0) !=
16345 DDI_PROP_SUCCESS) {
16346 (void) ddi_prop_remove(DDI_DEV_T_NONE, pdip,
16347 MPTSAS_VIRTUAL_PORT);
16348 mptsas_log(mpt, CE_WARN, "mptsas virtual port "
16349 "prop update failed");
16350 goto smp_create_done;
16351 }
16352
16353 mutex_enter(&mpt->m_mutex);
16354 numphys = 0;
16355 iport = ddi_get_name_addr(pdip);
16356 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
16357 bzero(phymask, sizeof (phymask));
16358 (void) sprintf(phymask,
16359 "%x", mpt->m_phy_info[i].phy_mask);
16360 if (strcmp(phymask, iport) == 0) {
16361 phy_mask = mpt->m_phy_info[i].phy_mask;
16362 break;
16363 }
16364 }
16365
16366 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
16367 if ((phy_mask >> i) & 0x01) {
16368 numphys++;
16369 }
16370 }
16371 /*
16372 * Update PHY info for smhba
16373 */
16374 if (mptsas_smhba_phy_init(mpt)) {
16375 mutex_exit(&mpt->m_mutex);
16376 mptsas_log(mpt, CE_WARN, "mptsas phy update "
16377 "failed");
16378 goto smp_create_done;
16379 }
16380 mutex_exit(&mpt->m_mutex);
16381
16382 mptsas_smhba_set_all_phy_props(mpt, pdip, numphys, phy_mask,
16383 &attached_devhdl);
16384
16385 if (ddi_prop_update_int(DDI_DEV_T_NONE, pdip,
16386 MPTSAS_NUM_PHYS, numphys) !=
16387 DDI_PROP_SUCCESS) {
16388 (void) ddi_prop_remove(DDI_DEV_T_NONE, pdip,
16389 MPTSAS_NUM_PHYS);
16390 mptsas_log(mpt, CE_WARN, "mptsas update "
16391 "num phys props failed");
16392 goto smp_create_done;
16393 }
16394 /*
16395 * Add parent's props for SMHBA support
16396 */
16397 if (ddi_prop_update_string(DDI_DEV_T_NONE, pdip,
16398 SCSI_ADDR_PROP_ATTACHED_PORT, wwn_str) !=
16399 DDI_PROP_SUCCESS) {
16400 (void) ddi_prop_remove(DDI_DEV_T_NONE, pdip,
16401 SCSI_ADDR_PROP_ATTACHED_PORT);
16402 mptsas_log(mpt, CE_WARN, "mptsas update iport"
16403 "attached-port failed");
16404 goto smp_create_done;
16405 }
16406
16407 smp_create_done:
16408 /*
16409 * If props were setup ok, online the lun
16410 */
16411 if (ndi_rtn == NDI_SUCCESS) {
16412 /*
16413 * Try to online the new node
16414 */
16415 ndi_rtn = ndi_devi_online(*smp_dip, NDI_ONLINE_ATTACH);
16416 }
16417
16418 /*
16419 * If success set rtn flag, else unwire alloc'd lun
16420 */
16421 if (ndi_rtn != NDI_SUCCESS) {
16422 NDBG12(("mptsas unable to online "
16423 "SMP target %s", wwn_str));
16424 ndi_prop_remove_all(*smp_dip);
16425 (void) ndi_devi_free(*smp_dip);
16426 }
16427 }
16428
16429 return ((ndi_rtn == NDI_SUCCESS) ? DDI_SUCCESS : DDI_FAILURE);
16430 }
16431
16432 /* smp transport routine */
mptsas_smp_start(struct smp_pkt * smp_pkt)16433 static int mptsas_smp_start(struct smp_pkt *smp_pkt)
16434 {
16435 uint64_t wwn;
16436 Mpi2SmpPassthroughRequest_t req;
16437 Mpi2SmpPassthroughReply_t rep;
16438 uint32_t direction = 0;
16439 mptsas_t *mpt;
16440 int ret;
16441 uint64_t tmp64;
16442
16443 mpt = (mptsas_t *)smp_pkt->smp_pkt_address->
16444 smp_a_hba_tran->smp_tran_hba_private;
16445
16446 bcopy(smp_pkt->smp_pkt_address->smp_a_wwn, &wwn, SAS_WWN_BYTE_SIZE);
16447 /*
16448 * Need to compose a SMP request message
16449 * and call mptsas_do_passthru() function
16450 */
16451 bzero(&req, sizeof (req));
16452 bzero(&rep, sizeof (rep));
16453 req.PassthroughFlags = 0;
16454 req.PhysicalPort = 0xff;
16455 req.ChainOffset = 0;
16456 req.Function = MPI2_FUNCTION_SMP_PASSTHROUGH;
16457
16458 if ((smp_pkt->smp_pkt_reqsize & 0xffff0000ul) != 0) {
16459 smp_pkt->smp_pkt_reason = ERANGE;
16460 return (DDI_FAILURE);
16461 }
16462 req.RequestDataLength = LE_16((uint16_t)(smp_pkt->smp_pkt_reqsize - 4));
16463
16464 req.MsgFlags = 0;
16465 tmp64 = LE_64(wwn);
16466 bcopy(&tmp64, &req.SASAddress, SAS_WWN_BYTE_SIZE);
16467 if (smp_pkt->smp_pkt_rspsize > 0) {
16468 direction |= MPTSAS_PASS_THRU_DIRECTION_READ;
16469 }
16470 if (smp_pkt->smp_pkt_reqsize > 0) {
16471 direction |= MPTSAS_PASS_THRU_DIRECTION_WRITE;
16472 }
16473
16474 mutex_enter(&mpt->m_mutex);
16475 ret = mptsas_do_passthru(mpt, (uint8_t *)&req, (uint8_t *)&rep,
16476 (uint8_t *)smp_pkt->smp_pkt_rsp,
16477 offsetof(Mpi2SmpPassthroughRequest_t, SGL), sizeof (rep),
16478 smp_pkt->smp_pkt_rspsize - 4, direction,
16479 (uint8_t *)smp_pkt->smp_pkt_req, smp_pkt->smp_pkt_reqsize - 4,
16480 smp_pkt->smp_pkt_timeout, FKIOCTL);
16481 mutex_exit(&mpt->m_mutex);
16482 if (ret != 0) {
16483 cmn_err(CE_WARN, "smp_start do passthru error %d", ret);
16484 smp_pkt->smp_pkt_reason = (uchar_t)(ret);
16485 return (DDI_FAILURE);
16486 }
16487 /* do passthrough success, check the smp status */
16488 if (LE_16(rep.IOCStatus) != MPI2_IOCSTATUS_SUCCESS) {
16489 switch (LE_16(rep.IOCStatus)) {
16490 case MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE:
16491 smp_pkt->smp_pkt_reason = ENODEV;
16492 break;
16493 case MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN:
16494 smp_pkt->smp_pkt_reason = EOVERFLOW;
16495 break;
16496 case MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED:
16497 smp_pkt->smp_pkt_reason = EIO;
16498 break;
16499 default:
16500 mptsas_log(mpt, CE_NOTE, "smp_start: get unknown ioc"
16501 "status:%x", LE_16(rep.IOCStatus));
16502 smp_pkt->smp_pkt_reason = EIO;
16503 break;
16504 }
16505 return (DDI_FAILURE);
16506 }
16507 if (rep.SASStatus != MPI2_SASSTATUS_SUCCESS) {
16508 mptsas_log(mpt, CE_NOTE, "smp_start: get error SAS status:%x",
16509 rep.SASStatus);
16510 smp_pkt->smp_pkt_reason = EIO;
16511 return (DDI_FAILURE);
16512 }
16513
16514 return (DDI_SUCCESS);
16515 }
16516
16517 /*
16518 * If we didn't get a match, we need to get sas page0 for each device, and
16519 * untill we get a match. If failed, return NULL
16520 */
16521 static mptsas_target_t *
mptsas_phy_to_tgt(mptsas_t * mpt,mptsas_phymask_t phymask,uint8_t phy)16522 mptsas_phy_to_tgt(mptsas_t *mpt, mptsas_phymask_t phymask, uint8_t phy)
16523 {
16524 int i, j = 0;
16525 int rval = 0;
16526 uint16_t cur_handle;
16527 uint32_t page_address;
16528 mptsas_target_t *ptgt = NULL;
16529
16530 /*
16531 * PHY named device must be direct attached and attaches to
16532 * narrow port, if the iport is not parent of the device which
16533 * we are looking for.
16534 */
16535 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
16536 if ((1 << i) & phymask)
16537 j++;
16538 }
16539
16540 if (j > 1)
16541 return (NULL);
16542
16543 /*
16544 * Must be a narrow port and single device attached to the narrow port
16545 * So the physical port num of device which is equal to the iport's
16546 * port num is the device what we are looking for.
16547 */
16548
16549 if (mpt->m_phy_info[phy].phy_mask != phymask)
16550 return (NULL);
16551
16552 mutex_enter(&mpt->m_mutex);
16553
16554 ptgt = refhash_linear_search(mpt->m_targets, mptsas_target_eval_nowwn,
16555 &phy);
16556 if (ptgt != NULL) {
16557 mutex_exit(&mpt->m_mutex);
16558 return (ptgt);
16559 }
16560
16561 if (mpt->m_done_traverse_dev) {
16562 mutex_exit(&mpt->m_mutex);
16563 return (NULL);
16564 }
16565
16566 /* If didn't get a match, come here */
16567 cur_handle = mpt->m_dev_handle;
16568 for (; ; ) {
16569 ptgt = NULL;
16570 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE &
16571 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | (uint32_t)cur_handle;
16572 rval = mptsas_get_target_device_info(mpt, page_address,
16573 &cur_handle, &ptgt);
16574 if ((rval == DEV_INFO_FAIL_PAGE0) ||
16575 (rval == DEV_INFO_FAIL_ALLOC)) {
16576 break;
16577 }
16578 if ((rval == DEV_INFO_WRONG_DEVICE_TYPE) ||
16579 (rval == DEV_INFO_PHYS_DISK) ||
16580 (rval == DEV_INFO_FAIL_GUID)) {
16581 continue;
16582 }
16583 mpt->m_dev_handle = cur_handle;
16584
16585 if ((ptgt->m_addr.mta_wwn == 0) && (ptgt->m_phynum == phy)) {
16586 break;
16587 }
16588 }
16589
16590 mutex_exit(&mpt->m_mutex);
16591 return (ptgt);
16592 }
16593
16594 /*
16595 * The ptgt->m_addr.mta_wwn contains the wwid for each disk.
16596 * For Raid volumes, we need to check m_raidvol[x].m_raidwwid
16597 * If we didn't get a match, we need to get sas page0 for each device, and
16598 * untill we get a match
16599 * If failed, return NULL
16600 */
16601 static mptsas_target_t *
mptsas_wwid_to_ptgt(mptsas_t * mpt,mptsas_phymask_t phymask,uint64_t wwid)16602 mptsas_wwid_to_ptgt(mptsas_t *mpt, mptsas_phymask_t phymask, uint64_t wwid)
16603 {
16604 int rval = 0;
16605 uint16_t cur_handle;
16606 uint32_t page_address;
16607 mptsas_target_t *tmp_tgt = NULL;
16608 mptsas_target_addr_t addr;
16609
16610 addr.mta_wwn = wwid;
16611 addr.mta_phymask = phymask;
16612 mutex_enter(&mpt->m_mutex);
16613 tmp_tgt = refhash_lookup(mpt->m_targets, &addr);
16614 if (tmp_tgt != NULL) {
16615 mutex_exit(&mpt->m_mutex);
16616 return (tmp_tgt);
16617 }
16618
16619 if (phymask == 0) {
16620 /*
16621 * It's IR volume
16622 */
16623 rval = mptsas_get_raid_info(mpt);
16624 if (rval) {
16625 tmp_tgt = refhash_lookup(mpt->m_targets, &addr);
16626 }
16627 mutex_exit(&mpt->m_mutex);
16628 return (tmp_tgt);
16629 }
16630
16631 if (mpt->m_done_traverse_dev) {
16632 mutex_exit(&mpt->m_mutex);
16633 return (NULL);
16634 }
16635
16636 /* If didn't get a match, come here */
16637 cur_handle = mpt->m_dev_handle;
16638 for (;;) {
16639 tmp_tgt = NULL;
16640 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE &
16641 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | cur_handle;
16642 rval = mptsas_get_target_device_info(mpt, page_address,
16643 &cur_handle, &tmp_tgt);
16644 if ((rval == DEV_INFO_FAIL_PAGE0) ||
16645 (rval == DEV_INFO_FAIL_ALLOC)) {
16646 tmp_tgt = NULL;
16647 break;
16648 }
16649 if ((rval == DEV_INFO_WRONG_DEVICE_TYPE) ||
16650 (rval == DEV_INFO_PHYS_DISK) ||
16651 (rval == DEV_INFO_FAIL_GUID)) {
16652 continue;
16653 }
16654 mpt->m_dev_handle = cur_handle;
16655 if ((tmp_tgt->m_addr.mta_wwn) &&
16656 (tmp_tgt->m_addr.mta_wwn == wwid) &&
16657 (tmp_tgt->m_addr.mta_phymask == phymask)) {
16658 break;
16659 }
16660 }
16661
16662 mutex_exit(&mpt->m_mutex);
16663 return (tmp_tgt);
16664 }
16665
16666 static mptsas_smp_t *
mptsas_wwid_to_psmp(mptsas_t * mpt,mptsas_phymask_t phymask,uint64_t wwid)16667 mptsas_wwid_to_psmp(mptsas_t *mpt, mptsas_phymask_t phymask, uint64_t wwid)
16668 {
16669 int rval = 0;
16670 uint16_t cur_handle;
16671 uint32_t page_address;
16672 mptsas_smp_t smp_node, *psmp = NULL;
16673 mptsas_target_addr_t addr;
16674
16675 addr.mta_wwn = wwid;
16676 addr.mta_phymask = phymask;
16677 mutex_enter(&mpt->m_mutex);
16678 psmp = refhash_lookup(mpt->m_smp_targets, &addr);
16679 if (psmp != NULL) {
16680 mutex_exit(&mpt->m_mutex);
16681 return (psmp);
16682 }
16683
16684 if (mpt->m_done_traverse_smp) {
16685 mutex_exit(&mpt->m_mutex);
16686 return (NULL);
16687 }
16688
16689 /* If didn't get a match, come here */
16690 cur_handle = mpt->m_smp_devhdl;
16691 for (;;) {
16692 psmp = NULL;
16693 page_address = (MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL &
16694 MPI2_SAS_EXPAND_PGAD_FORM_MASK) | (uint32_t)cur_handle;
16695 rval = mptsas_get_sas_expander_page0(mpt, page_address,
16696 &smp_node);
16697 if (rval != DDI_SUCCESS) {
16698 break;
16699 }
16700 mpt->m_smp_devhdl = cur_handle = smp_node.m_devhdl;
16701 psmp = mptsas_smp_alloc(mpt, &smp_node);
16702 ASSERT(psmp);
16703 if ((psmp->m_addr.mta_wwn) && (psmp->m_addr.mta_wwn == wwid) &&
16704 (psmp->m_addr.mta_phymask == phymask)) {
16705 break;
16706 }
16707 }
16708
16709 mutex_exit(&mpt->m_mutex);
16710 return (psmp);
16711 }
16712
16713 mptsas_target_t *
mptsas_tgt_alloc(refhash_t * refhash,uint16_t devhdl,uint64_t wwid,uint32_t devinfo,mptsas_phymask_t phymask,uint8_t phynum)16714 mptsas_tgt_alloc(refhash_t *refhash, uint16_t devhdl, uint64_t wwid,
16715 uint32_t devinfo, mptsas_phymask_t phymask, uint8_t phynum)
16716 {
16717 mptsas_target_t *tmp_tgt = NULL;
16718 mptsas_target_addr_t addr;
16719
16720 addr.mta_wwn = wwid;
16721 addr.mta_phymask = phymask;
16722 tmp_tgt = refhash_lookup(refhash, &addr);
16723 if (tmp_tgt != NULL) {
16724 NDBG20(("Hash item already exist"));
16725 tmp_tgt->m_deviceinfo = devinfo;
16726 tmp_tgt->m_devhdl = devhdl; /* XXX - duplicate? */
16727 return (tmp_tgt);
16728 }
16729 tmp_tgt = kmem_zalloc(sizeof (struct mptsas_target), KM_SLEEP);
16730 if (tmp_tgt == NULL) {
16731 cmn_err(CE_WARN, "Fatal, allocated tgt failed");
16732 return (NULL);
16733 }
16734 tmp_tgt->m_devhdl = devhdl;
16735 tmp_tgt->m_addr.mta_wwn = wwid;
16736 tmp_tgt->m_deviceinfo = devinfo;
16737 tmp_tgt->m_addr.mta_phymask = phymask;
16738 tmp_tgt->m_phynum = phynum;
16739 /* Initialized the tgt structure */
16740 tmp_tgt->m_qfull_retries = QFULL_RETRIES;
16741 tmp_tgt->m_qfull_retry_interval =
16742 drv_usectohz(QFULL_RETRY_INTERVAL * 1000);
16743 tmp_tgt->m_t_throttle = MAX_THROTTLE;
16744 TAILQ_INIT(&tmp_tgt->m_active_cmdq);
16745
16746 refhash_insert(refhash, tmp_tgt);
16747
16748 return (tmp_tgt);
16749 }
16750
16751 static void
mptsas_smp_target_copy(mptsas_smp_t * src,mptsas_smp_t * dst)16752 mptsas_smp_target_copy(mptsas_smp_t *src, mptsas_smp_t *dst)
16753 {
16754 dst->m_devhdl = src->m_devhdl;
16755 dst->m_deviceinfo = src->m_deviceinfo;
16756 dst->m_pdevhdl = src->m_pdevhdl;
16757 dst->m_pdevinfo = src->m_pdevinfo;
16758 }
16759
16760 static mptsas_smp_t *
mptsas_smp_alloc(mptsas_t * mpt,mptsas_smp_t * data)16761 mptsas_smp_alloc(mptsas_t *mpt, mptsas_smp_t *data)
16762 {
16763 mptsas_target_addr_t addr;
16764 mptsas_smp_t *ret_data;
16765
16766 addr.mta_wwn = data->m_addr.mta_wwn;
16767 addr.mta_phymask = data->m_addr.mta_phymask;
16768 ret_data = refhash_lookup(mpt->m_smp_targets, &addr);
16769 /*
16770 * If there's already a matching SMP target, update its fields
16771 * in place. Since the address is not changing, it's safe to do
16772 * this. We cannot just bcopy() here because the structure we've
16773 * been given has invalid hash links.
16774 */
16775 if (ret_data != NULL) {
16776 mptsas_smp_target_copy(data, ret_data);
16777 return (ret_data);
16778 }
16779
16780 ret_data = kmem_alloc(sizeof (mptsas_smp_t), KM_SLEEP);
16781 bcopy(data, ret_data, sizeof (mptsas_smp_t));
16782 refhash_insert(mpt->m_smp_targets, ret_data);
16783 return (ret_data);
16784 }
16785
16786 /*
16787 * Functions for SGPIO LED support
16788 */
16789 static dev_info_t *
mptsas_get_dip_from_dev(dev_t dev,mptsas_phymask_t * phymask)16790 mptsas_get_dip_from_dev(dev_t dev, mptsas_phymask_t *phymask)
16791 {
16792 dev_info_t *dip;
16793 int prop;
16794 dip = e_ddi_hold_devi_by_dev(dev, 0);
16795 if (dip == NULL)
16796 return (dip);
16797 prop = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 0,
16798 "phymask", 0);
16799 *phymask = (mptsas_phymask_t)prop;
16800 ddi_release_devi(dip);
16801 return (dip);
16802 }
16803 static mptsas_target_t *
mptsas_addr_to_ptgt(mptsas_t * mpt,char * addr,mptsas_phymask_t phymask)16804 mptsas_addr_to_ptgt(mptsas_t *mpt, char *addr, mptsas_phymask_t phymask)
16805 {
16806 uint8_t phynum;
16807 uint64_t wwn;
16808 int lun;
16809 mptsas_target_t *ptgt = NULL;
16810
16811 if (mptsas_parse_address(addr, &wwn, &phynum, &lun) != DDI_SUCCESS) {
16812 return (NULL);
16813 }
16814 if (addr[0] == 'w') {
16815 ptgt = mptsas_wwid_to_ptgt(mpt, (int)phymask, wwn);
16816 } else {
16817 ptgt = mptsas_phy_to_tgt(mpt, (int)phymask, phynum);
16818 }
16819 return (ptgt);
16820 }
16821
16822 static int
mptsas_flush_led_status(mptsas_t * mpt,mptsas_enclosure_t * mep,uint16_t idx)16823 mptsas_flush_led_status(mptsas_t *mpt, mptsas_enclosure_t *mep, uint16_t idx)
16824 {
16825 uint32_t slotstatus = 0;
16826
16827 ASSERT3U(idx, <, mep->me_nslots);
16828
16829 /* Build an MPI2 Slot Status based on our view of the world */
16830 if (mep->me_slotleds[idx] & (1 << (MPTSAS_LEDCTL_LED_IDENT - 1)))
16831 slotstatus |= MPI2_SEP_REQ_SLOTSTATUS_IDENTIFY_REQUEST;
16832 if (mep->me_slotleds[idx] & (1 << (MPTSAS_LEDCTL_LED_FAIL - 1)))
16833 slotstatus |= MPI2_SEP_REQ_SLOTSTATUS_PREDICTED_FAULT;
16834 if (mep->me_slotleds[idx] & (1 << (MPTSAS_LEDCTL_LED_OK2RM - 1)))
16835 slotstatus |= MPI2_SEP_REQ_SLOTSTATUS_REQUEST_REMOVE;
16836
16837 /* Write it to the controller */
16838 NDBG14(("mptsas_ioctl: set LED status %x for slot %x",
16839 slotstatus, idx + mep->me_fslot));
16840 return (mptsas_send_sep(mpt, mep, idx, &slotstatus,
16841 MPI2_SEP_REQ_ACTION_WRITE_STATUS));
16842 }
16843
16844 /*
16845 * send sep request, use enclosure/slot addressing
16846 */
16847 static int
mptsas_send_sep(mptsas_t * mpt,mptsas_enclosure_t * mep,uint16_t idx,uint32_t * status,uint8_t act)16848 mptsas_send_sep(mptsas_t *mpt, mptsas_enclosure_t *mep, uint16_t idx,
16849 uint32_t *status, uint8_t act)
16850 {
16851 Mpi2SepRequest_t req;
16852 Mpi2SepReply_t rep;
16853 int ret;
16854 uint16_t enctype;
16855 uint16_t slot;
16856
16857 ASSERT(mutex_owned(&mpt->m_mutex));
16858
16859 /*
16860 * Look through the enclosures and make sure that this enclosure is
16861 * something that is directly attached device. If we didn't find an
16862 * enclosure for this device, don't send the ioctl.
16863 */
16864 enctype = mep->me_flags & MPI2_SAS_ENCLS0_FLAGS_MNG_MASK;
16865 if (enctype != MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SES &&
16866 enctype != MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO &&
16867 enctype != MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO) {
16868 return (ENOTTY);
16869 }
16870 slot = idx + mep->me_fslot;
16871
16872 bzero(&req, sizeof (req));
16873 bzero(&rep, sizeof (rep));
16874
16875 req.Function = MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR;
16876 req.Action = act;
16877 req.Flags = MPI2_SEP_REQ_FLAGS_ENCLOSURE_SLOT_ADDRESS;
16878 req.EnclosureHandle = LE_16(mep->me_enchdl);
16879 req.Slot = LE_16(slot);
16880 if (act == MPI2_SEP_REQ_ACTION_WRITE_STATUS) {
16881 req.SlotStatus = LE_32(*status);
16882 }
16883 ret = mptsas_do_passthru(mpt, (uint8_t *)&req, (uint8_t *)&rep, NULL,
16884 sizeof (req), sizeof (rep), 0, MPTSAS_PASS_THRU_DIRECTION_NONE,
16885 NULL, 0, 60, FKIOCTL);
16886 if (ret != 0) {
16887 mptsas_log(mpt, CE_NOTE, "mptsas_send_sep: passthru SEP "
16888 "Processor Request message error %d", ret);
16889 return (ret);
16890 }
16891 /* do passthrough success, check the ioc status */
16892 if (LE_16(rep.IOCStatus) != MPI2_IOCSTATUS_SUCCESS) {
16893 mptsas_log(mpt, CE_NOTE, "send_sep act %x: ioc "
16894 "status:%x loginfo %x", act, LE_16(rep.IOCStatus),
16895 LE_32(rep.IOCLogInfo));
16896 switch (LE_16(rep.IOCStatus) & MPI2_IOCSTATUS_MASK) {
16897 case MPI2_IOCSTATUS_INVALID_FUNCTION:
16898 case MPI2_IOCSTATUS_INVALID_VPID:
16899 case MPI2_IOCSTATUS_INVALID_FIELD:
16900 case MPI2_IOCSTATUS_INVALID_STATE:
16901 case MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED:
16902 case MPI2_IOCSTATUS_CONFIG_INVALID_ACTION:
16903 case MPI2_IOCSTATUS_CONFIG_INVALID_TYPE:
16904 case MPI2_IOCSTATUS_CONFIG_INVALID_PAGE:
16905 case MPI2_IOCSTATUS_CONFIG_INVALID_DATA:
16906 case MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS:
16907 return (EINVAL);
16908 case MPI2_IOCSTATUS_BUSY:
16909 return (EBUSY);
16910 case MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES:
16911 return (EAGAIN);
16912 case MPI2_IOCSTATUS_INVALID_SGL:
16913 case MPI2_IOCSTATUS_INTERNAL_ERROR:
16914 case MPI2_IOCSTATUS_CONFIG_CANT_COMMIT:
16915 default:
16916 return (EIO);
16917 }
16918 }
16919 if (act != MPI2_SEP_REQ_ACTION_WRITE_STATUS) {
16920 *status = LE_32(rep.SlotStatus);
16921 }
16922
16923 return (0);
16924 }
16925
16926 int
mptsas_dma_addr_create(mptsas_t * mpt,ddi_dma_attr_t dma_attr,ddi_dma_handle_t * dma_hdp,ddi_acc_handle_t * acc_hdp,caddr_t * dma_memp,uint32_t alloc_size,ddi_dma_cookie_t * cookiep)16927 mptsas_dma_addr_create(mptsas_t *mpt, ddi_dma_attr_t dma_attr,
16928 ddi_dma_handle_t *dma_hdp, ddi_acc_handle_t *acc_hdp, caddr_t *dma_memp,
16929 uint32_t alloc_size, ddi_dma_cookie_t *cookiep)
16930 {
16931 ddi_dma_cookie_t new_cookie;
16932 size_t alloc_len;
16933 uint_t ncookie;
16934
16935 if (cookiep == NULL)
16936 cookiep = &new_cookie;
16937
16938 if (ddi_dma_alloc_handle(mpt->m_dip, &dma_attr, DDI_DMA_SLEEP,
16939 NULL, dma_hdp) != DDI_SUCCESS) {
16940 return (FALSE);
16941 }
16942
16943 if (ddi_dma_mem_alloc(*dma_hdp, alloc_size, &mpt->m_dev_acc_attr,
16944 DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL, dma_memp, &alloc_len,
16945 acc_hdp) != DDI_SUCCESS) {
16946 ddi_dma_free_handle(dma_hdp);
16947 *dma_hdp = NULL;
16948 return (FALSE);
16949 }
16950
16951 if (ddi_dma_addr_bind_handle(*dma_hdp, NULL, *dma_memp, alloc_len,
16952 (DDI_DMA_RDWR | DDI_DMA_CONSISTENT), DDI_DMA_SLEEP, NULL,
16953 cookiep, &ncookie) != DDI_DMA_MAPPED) {
16954 (void) ddi_dma_mem_free(acc_hdp);
16955 ddi_dma_free_handle(dma_hdp);
16956 *dma_hdp = NULL;
16957 return (FALSE);
16958 }
16959
16960 return (TRUE);
16961 }
16962
16963 void
mptsas_dma_addr_destroy(ddi_dma_handle_t * dma_hdp,ddi_acc_handle_t * acc_hdp)16964 mptsas_dma_addr_destroy(ddi_dma_handle_t *dma_hdp, ddi_acc_handle_t *acc_hdp)
16965 {
16966 if (*dma_hdp == NULL)
16967 return;
16968
16969 (void) ddi_dma_unbind_handle(*dma_hdp);
16970 (void) ddi_dma_mem_free(acc_hdp);
16971 ddi_dma_free_handle(dma_hdp);
16972 *dma_hdp = NULL;
16973 }
16974