1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2015-2018 Solarflare Communications Inc.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright notice,
13 * this list of conditions and the following disclaimer in the documentation
14 * and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
18 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
26 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * The views and conclusions contained in the software and documentation are
29 * those of the authors and should not be interpreted as representing official
30 * policies, either expressed or implied, of the FreeBSD Project.
31 */
32
33 #include <sys/cdefs.h>
34 #include "efx.h"
35 #include "efx_impl.h"
36
37 #if EFSYS_OPT_MEDFORD2
38
39 static __checkReturn efx_rc_t
medford2_nic_get_required_pcie_bandwidth(__in efx_nic_t * enp,__out uint32_t * bandwidth_mbpsp)40 medford2_nic_get_required_pcie_bandwidth(
41 __in efx_nic_t *enp,
42 __out uint32_t *bandwidth_mbpsp)
43 {
44 uint32_t bandwidth;
45 efx_rc_t rc;
46
47 /* FIXME: support new Medford2 dynamic port modes */
48
49 if ((rc = ef10_nic_get_port_mode_bandwidth(enp,
50 &bandwidth)) != 0)
51 goto fail1;
52
53 *bandwidth_mbpsp = bandwidth;
54
55 return (0);
56
57 fail1:
58 EFSYS_PROBE1(fail1, efx_rc_t, rc);
59
60 return (rc);
61 }
62
63 __checkReturn efx_rc_t
medford2_board_cfg(__in efx_nic_t * enp)64 medford2_board_cfg(
65 __in efx_nic_t *enp)
66 {
67 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
68 uint32_t sysclk, dpcpu_clk;
69 uint32_t end_padding;
70 uint32_t bandwidth;
71 efx_rc_t rc;
72
73 /*
74 * Enable firmware workarounds for hardware errata.
75 * Expected responses are:
76 * - 0 (zero):
77 * Success: workaround enabled or disabled as requested.
78 * - MC_CMD_ERR_ENOSYS (reported as ENOTSUP):
79 * Firmware does not support the MC_CMD_WORKAROUND request.
80 * (assume that the workaround is not supported).
81 * - MC_CMD_ERR_ENOENT (reported as ENOENT):
82 * Firmware does not support the requested workaround.
83 * - MC_CMD_ERR_EPERM (reported as EACCES):
84 * Unprivileged function cannot enable/disable workarounds.
85 *
86 * See efx_mcdi_request_errcode() for MCDI error translations.
87 */
88
89 if (EFX_PCI_FUNCTION_IS_VF(encp)) {
90 /*
91 * Interrupt testing does not work for VFs on Medford2.
92 * See bug50084 and bug71432 comment 21.
93 */
94 encp->enc_bug41750_workaround = B_TRUE;
95 }
96
97 /* Chained multicast is always enabled on Medford2 */
98 encp->enc_bug26807_workaround = B_TRUE;
99
100 /*
101 * If the bug61265 workaround is enabled, then interrupt holdoff timers
102 * cannot be controlled by timer table writes, so MCDI must be used
103 * (timer table writes can still be used for wakeup timers).
104 */
105 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG61265, B_TRUE,
106 NULL);
107 if ((rc == 0) || (rc == EACCES))
108 encp->enc_bug61265_workaround = B_TRUE;
109 else if ((rc == ENOTSUP) || (rc == ENOENT))
110 encp->enc_bug61265_workaround = B_FALSE;
111 else
112 goto fail1;
113
114 /* Checksums for TSO sends should always be correct on Medford2. */
115 encp->enc_bug61297_workaround = B_FALSE;
116
117 /* Get clock frequencies (in MHz). */
118 if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)
119 goto fail2;
120
121 /*
122 * The Medford2 timer quantum is 1536 dpcpu_clk cycles, documented for
123 * the EV_TMR_VAL field of EV_TIMER_TBL. Scale for MHz and ns units.
124 */
125 encp->enc_evq_timer_quantum_ns = 1536000UL / dpcpu_clk; /* 1536 cycles */
126 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
127 FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
128
129 /* Alignment for receive packet DMA buffers */
130 encp->enc_rx_buf_align_start = 1;
131
132 /* Get the RX DMA end padding alignment configuration */
133 if ((rc = efx_mcdi_get_rxdp_config(enp, &end_padding)) != 0) {
134 if (rc != EACCES)
135 goto fail3;
136
137 /* Assume largest tail padding size supported by hardware */
138 end_padding = 256;
139 }
140 encp->enc_rx_buf_align_end = end_padding;
141
142 /*
143 * The maximum supported transmit queue size is 2048. TXQs with 4096
144 * descriptors are not supported as the top bit is used for vfifo
145 * stuffing.
146 */
147 encp->enc_txq_max_ndescs = 2048;
148
149 EFX_STATIC_ASSERT(MEDFORD2_PIOBUF_NBUFS <= EF10_MAX_PIOBUF_NBUFS);
150 encp->enc_piobuf_limit = MEDFORD2_PIOBUF_NBUFS;
151 encp->enc_piobuf_size = MEDFORD2_PIOBUF_SIZE;
152 encp->enc_piobuf_min_alloc_size = MEDFORD2_MIN_PIO_ALLOC_SIZE;
153
154 /*
155 * Medford2 stores a single global copy of VPD, not per-PF as on
156 * Huntington.
157 */
158 encp->enc_vpd_is_global = B_TRUE;
159
160 rc = medford2_nic_get_required_pcie_bandwidth(enp, &bandwidth);
161 if (rc != 0)
162 goto fail4;
163 encp->enc_required_pcie_bandwidth_mbps = bandwidth;
164 encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3;
165
166 return (0);
167
168 fail4:
169 EFSYS_PROBE(fail4);
170 fail3:
171 EFSYS_PROBE(fail3);
172 fail2:
173 EFSYS_PROBE(fail2);
174 fail1:
175 EFSYS_PROBE1(fail1, efx_rc_t, rc);
176
177 return (rc);
178 }
179
180 #endif /* EFSYS_OPT_MEDFORD2 */
181