1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2009 Hudson River Trading LLC
5 * Written by: John H. Baldwin <jhb@FreeBSD.org>
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30 /*
31 * Support for x86 machine check architecture.
32 */
33
34 #include <sys/cdefs.h>
35 #ifdef __amd64__
36 #define DEV_APIC
37 #else
38 #include "opt_apic.h"
39 #endif
40
41 #include <sys/param.h>
42 #include <sys/bus.h>
43 #include <sys/interrupt.h>
44 #include <sys/kernel.h>
45 #include <sys/lock.h>
46 #include <sys/malloc.h>
47 #include <sys/mutex.h>
48 #include <sys/proc.h>
49 #include <sys/sched.h>
50 #include <sys/smp.h>
51 #include <sys/sysctl.h>
52 #include <sys/systm.h>
53 #include <sys/taskqueue.h>
54 #include <machine/intr_machdep.h>
55 #include <x86/apicvar.h>
56 #include <machine/cpu.h>
57 #include <machine/cputypes.h>
58 #include <x86/mca.h>
59 #include <machine/md_var.h>
60 #include <machine/specialreg.h>
61
62 /* Modes for mca_scan() */
63 enum scan_mode {
64 POLLED,
65 MCE,
66 CMCI,
67 };
68
69 #ifdef DEV_APIC
70 /*
71 * State maintained for each monitored MCx bank to control the
72 * corrected machine check interrupt threshold.
73 */
74 struct cmc_state {
75 int max_threshold;
76 time_t last_intr;
77 };
78
79 struct amd_et_state {
80 int cur_threshold;
81 time_t last_intr;
82 };
83 #endif
84
85 struct mca_internal {
86 struct mca_record rec;
87 STAILQ_ENTRY(mca_internal) link;
88 };
89
90 struct mca_enumerator_ops {
91 unsigned int (*ctl)(int);
92 unsigned int (*status)(int);
93 unsigned int (*addr)(int);
94 unsigned int (*misc)(int);
95 };
96
97 static MALLOC_DEFINE(M_MCA, "MCA", "Machine Check Architecture");
98
99 static volatile int mca_count; /* Number of records stored. */
100 static int mca_banks; /* Number of per-CPU register banks. */
101 static int mca_maxcount = -1; /* Limit on records stored. (-1 = unlimited) */
102
103 static SYSCTL_NODE(_hw, OID_AUTO, mca, CTLFLAG_RD | CTLFLAG_MPSAFE, NULL,
104 "Machine Check Architecture");
105
106 static int mca_enabled = 1;
107 SYSCTL_INT(_hw_mca, OID_AUTO, enabled, CTLFLAG_RDTUN, &mca_enabled, 0,
108 "Administrative toggle for machine check support");
109
110 static int log_corrected = 1;
111 SYSCTL_INT(_hw_mca, OID_AUTO, log_corrected, CTLFLAG_RWTUN, &log_corrected, 0,
112 "Log corrected errors to the console");
113
114 static int amd10h_L1TP = 1;
115 SYSCTL_INT(_hw_mca, OID_AUTO, amd10h_L1TP, CTLFLAG_RDTUN, &amd10h_L1TP, 0,
116 "Administrative toggle for logging of level one TLB parity (L1TP) errors");
117
118 static int intel6h_HSD131;
119 SYSCTL_INT(_hw_mca, OID_AUTO, intel6h_HSD131, CTLFLAG_RDTUN, &intel6h_HSD131, 0,
120 "Administrative toggle for logging of spurious corrected errors");
121
122 int workaround_erratum383;
123 SYSCTL_INT(_hw_mca, OID_AUTO, erratum383, CTLFLAG_RDTUN,
124 &workaround_erratum383, 0,
125 "Is the workaround for Erratum 383 on AMD Family 10h processors enabled?");
126
127 static STAILQ_HEAD(, mca_internal) mca_freelist;
128 static int mca_freecount;
129 static STAILQ_HEAD(, mca_internal) mca_records;
130 static STAILQ_HEAD(, mca_internal) mca_pending;
131 static int mca_ticks = 300;
132 static struct taskqueue *mca_tq;
133 static struct task mca_resize_task;
134 static struct timeout_task mca_scan_task;
135 static struct mtx mca_lock;
136
137 static unsigned int
mca_ia32_ctl_reg(int bank)138 mca_ia32_ctl_reg(int bank)
139 {
140 return (MSR_MC_CTL(bank));
141 }
142
143 static unsigned int
mca_ia32_status_reg(int bank)144 mca_ia32_status_reg(int bank)
145 {
146 return (MSR_MC_STATUS(bank));
147 }
148
149 static unsigned int
mca_ia32_addr_reg(int bank)150 mca_ia32_addr_reg(int bank)
151 {
152 return (MSR_MC_ADDR(bank));
153 }
154
155 static unsigned int
mca_ia32_misc_reg(int bank)156 mca_ia32_misc_reg(int bank)
157 {
158 return (MSR_MC_MISC(bank));
159 }
160
161 static unsigned int
mca_smca_ctl_reg(int bank)162 mca_smca_ctl_reg(int bank)
163 {
164 return (MSR_SMCA_MC_CTL(bank));
165 }
166
167 static unsigned int
mca_smca_status_reg(int bank)168 mca_smca_status_reg(int bank)
169 {
170 return (MSR_SMCA_MC_STATUS(bank));
171 }
172
173 static unsigned int
mca_smca_addr_reg(int bank)174 mca_smca_addr_reg(int bank)
175 {
176 return (MSR_SMCA_MC_ADDR(bank));
177 }
178
179 static unsigned int
mca_smca_misc_reg(int bank)180 mca_smca_misc_reg(int bank)
181 {
182 return (MSR_SMCA_MC_MISC(bank));
183 }
184
185 static struct mca_enumerator_ops mca_msr_ops = {
186 .ctl = mca_ia32_ctl_reg,
187 .status = mca_ia32_status_reg,
188 .addr = mca_ia32_addr_reg,
189 .misc = mca_ia32_misc_reg
190 };
191
192 #ifdef DEV_APIC
193 static struct cmc_state **cmc_state; /* Indexed by cpuid, bank. */
194 static struct amd_et_state **amd_et_state; /* Indexed by cpuid, bank. */
195 static int cmc_throttle = 60; /* Time in seconds to throttle CMCI. */
196
197 static int amd_elvt = -1;
198
199 static inline bool
amd_thresholding_supported(void)200 amd_thresholding_supported(void)
201 {
202 if (cpu_vendor_id != CPU_VENDOR_AMD &&
203 cpu_vendor_id != CPU_VENDOR_HYGON)
204 return (false);
205 /*
206 * The RASCap register is wholly reserved in families 0x10-0x15 (through model 1F).
207 *
208 * It begins to be documented in family 0x15 model 30 and family 0x16,
209 * but neither of these families documents the ScalableMca bit, which
210 * supposedly defines the presence of this feature on family 0x17.
211 */
212 if (CPUID_TO_FAMILY(cpu_id) >= 0x10 && CPUID_TO_FAMILY(cpu_id) <= 0x16)
213 return (true);
214 if (CPUID_TO_FAMILY(cpu_id) >= 0x17)
215 return ((amd_rascap & AMDRAS_SCALABLE_MCA) != 0);
216 return (false);
217 }
218 #endif
219
220 static inline bool
cmci_supported(uint64_t mcg_cap)221 cmci_supported(uint64_t mcg_cap)
222 {
223 /*
224 * MCG_CAP_CMCI_P bit is reserved in AMD documentation. Until
225 * it is defined, do not use it to check for CMCI support.
226 */
227 if (cpu_vendor_id != CPU_VENDOR_INTEL)
228 return (false);
229 return ((mcg_cap & MCG_CAP_CMCI_P) != 0);
230 }
231
232 static inline bool
tes_supported(uint64_t mcg_cap)233 tes_supported(uint64_t mcg_cap)
234 {
235
236 /*
237 * MCG_CAP_TES_P bit is reserved in AMD documentation. Until
238 * it is defined, do not use it to check for TES support.
239 */
240 if (cpu_vendor_id != CPU_VENDOR_INTEL)
241 return (false);
242 return ((mcg_cap & MCG_CAP_TES_P) != 0);
243 }
244
245 static inline bool
ser_supported(uint64_t mcg_cap)246 ser_supported(uint64_t mcg_cap)
247 {
248
249 return (tes_supported(mcg_cap) && (mcg_cap & MCG_CAP_SER_P) != 0);
250 }
251
252 static int
sysctl_positive_int(SYSCTL_HANDLER_ARGS)253 sysctl_positive_int(SYSCTL_HANDLER_ARGS)
254 {
255 int error, value;
256
257 value = *(int *)arg1;
258 error = sysctl_handle_int(oidp, &value, 0, req);
259 if (error || req->newptr == NULL)
260 return (error);
261 if (value <= 0)
262 return (EINVAL);
263 *(int *)arg1 = value;
264 return (0);
265 }
266
267 static int
sysctl_mca_records(SYSCTL_HANDLER_ARGS)268 sysctl_mca_records(SYSCTL_HANDLER_ARGS)
269 {
270 int *name = (int *)arg1;
271 u_int namelen = arg2;
272 struct mca_record record;
273 struct mca_internal *rec;
274 int i;
275
276 if (namelen != 1)
277 return (EINVAL);
278
279 if (name[0] < 0 || name[0] >= mca_count)
280 return (EINVAL);
281
282 mtx_lock_spin(&mca_lock);
283 if (name[0] >= mca_count) {
284 mtx_unlock_spin(&mca_lock);
285 return (EINVAL);
286 }
287 i = 0;
288 STAILQ_FOREACH(rec, &mca_records, link) {
289 if (i == name[0]) {
290 record = rec->rec;
291 break;
292 }
293 i++;
294 }
295 mtx_unlock_spin(&mca_lock);
296 return (SYSCTL_OUT(req, &record, sizeof(record)));
297 }
298
299 static const char *
mca_error_ttype(uint16_t mca_error)300 mca_error_ttype(uint16_t mca_error)
301 {
302
303 switch ((mca_error & 0x000c) >> 2) {
304 case 0:
305 return ("I");
306 case 1:
307 return ("D");
308 case 2:
309 return ("G");
310 }
311 return ("?");
312 }
313
314 static const char *
mca_error_level(uint16_t mca_error)315 mca_error_level(uint16_t mca_error)
316 {
317
318 switch (mca_error & 0x0003) {
319 case 0:
320 return ("L0");
321 case 1:
322 return ("L1");
323 case 2:
324 return ("L2");
325 case 3:
326 return ("LG");
327 }
328 return ("L?");
329 }
330
331 static const char *
mca_error_request(uint16_t mca_error)332 mca_error_request(uint16_t mca_error)
333 {
334
335 switch ((mca_error & 0x00f0) >> 4) {
336 case 0x0:
337 return ("ERR");
338 case 0x1:
339 return ("RD");
340 case 0x2:
341 return ("WR");
342 case 0x3:
343 return ("DRD");
344 case 0x4:
345 return ("DWR");
346 case 0x5:
347 return ("IRD");
348 case 0x6:
349 return ("PREFETCH");
350 case 0x7:
351 return ("EVICT");
352 case 0x8:
353 return ("SNOOP");
354 }
355 return ("???");
356 }
357
358 static const char *
mca_error_mmtype(uint16_t mca_error)359 mca_error_mmtype(uint16_t mca_error)
360 {
361
362 switch ((mca_error & 0x70) >> 4) {
363 case 0x0:
364 return ("GEN");
365 case 0x1:
366 return ("RD");
367 case 0x2:
368 return ("WR");
369 case 0x3:
370 return ("AC");
371 case 0x4:
372 return ("MS");
373 }
374 return ("???");
375 }
376
377 static const char *
mca_addres_mode(uint64_t mca_misc)378 mca_addres_mode(uint64_t mca_misc)
379 {
380
381 switch ((mca_misc & MC_MISC_ADDRESS_MODE) >> 6) {
382 case 0x0:
383 return ("Segment Offset");
384 case 0x1:
385 return ("Linear Address");
386 case 0x2:
387 return ("Physical Address");
388 case 0x3:
389 return ("Memory Address");
390 case 0x7:
391 return ("Generic");
392 }
393 return ("???");
394 }
395
396 static int
mca_mute(const struct mca_record * rec)397 mca_mute(const struct mca_record *rec)
398 {
399
400 /*
401 * Skip spurious corrected parity errors generated by Intel Haswell-
402 * and Broadwell-based CPUs (see HSD131, HSM142, HSW131 and BDM48
403 * erratum respectively), unless reporting is enabled.
404 * Note that these errors also have been observed with the D0-stepping
405 * of Haswell, while at least initially the CPU specification updates
406 * suggested only the C0-stepping to be affected. Similarly, Celeron
407 * 2955U with a CPU ID of 0x45 apparently are also concerned with the
408 * same problem, with HSM142 only referring to 0x3c and 0x46.
409 */
410 if (cpu_vendor_id == CPU_VENDOR_INTEL &&
411 CPUID_TO_FAMILY(cpu_id) == 0x6 &&
412 (CPUID_TO_MODEL(cpu_id) == 0x3c || /* HSD131, HSM142, HSW131 */
413 CPUID_TO_MODEL(cpu_id) == 0x3d || /* BDM48 */
414 CPUID_TO_MODEL(cpu_id) == 0x45 ||
415 CPUID_TO_MODEL(cpu_id) == 0x46) && /* HSM142 */
416 rec->mr_bank == 0 &&
417 (rec->mr_status & 0xa0000000ffffffff) == 0x80000000000f0005 &&
418 !intel6h_HSD131)
419 return (1);
420
421 return (0);
422 }
423
424 /* Dump details about a single machine check. */
425 static void
mca_log(const struct mca_record * rec)426 mca_log(const struct mca_record *rec)
427 {
428 uint16_t mca_error;
429
430 if (mca_mute(rec))
431 return;
432
433 if (!log_corrected && (rec->mr_status & MC_STATUS_UC) == 0 &&
434 (!tes_supported(rec->mr_mcg_cap) ||
435 ((rec->mr_status & MC_STATUS_TES_STATUS) >> 53) != 0x2))
436 return;
437
438 printf("MCA: Bank %d, Status 0x%016llx\n", rec->mr_bank,
439 (long long)rec->mr_status);
440 printf("MCA: Global Cap 0x%016llx, Status 0x%016llx\n",
441 (long long)rec->mr_mcg_cap, (long long)rec->mr_mcg_status);
442 printf("MCA: Vendor \"%s\", ID 0x%x, APIC ID %d\n", cpu_vendor,
443 rec->mr_cpu_id, rec->mr_apic_id);
444 printf("MCA: CPU %d ", rec->mr_cpu);
445 if (rec->mr_status & MC_STATUS_UC)
446 printf("UNCOR ");
447 else {
448 printf("COR ");
449 if (cmci_supported(rec->mr_mcg_cap))
450 printf("(%lld) ", ((long long)rec->mr_status &
451 MC_STATUS_COR_COUNT) >> 38);
452 if (tes_supported(rec->mr_mcg_cap)) {
453 switch ((rec->mr_status & MC_STATUS_TES_STATUS) >> 53) {
454 case 0x1:
455 printf("(Green) ");
456 break;
457 case 0x2:
458 printf("(Yellow) ");
459 break;
460 }
461 }
462 }
463 if (rec->mr_status & MC_STATUS_EN)
464 printf("EN ");
465 if (rec->mr_status & MC_STATUS_PCC)
466 printf("PCC ");
467 if (ser_supported(rec->mr_mcg_cap)) {
468 if (rec->mr_status & MC_STATUS_S)
469 printf("S ");
470 if (rec->mr_status & MC_STATUS_AR)
471 printf("AR ");
472 }
473 if (rec->mr_status & MC_STATUS_OVER)
474 printf("OVER ");
475 mca_error = rec->mr_status & MC_STATUS_MCA_ERROR;
476 switch (mca_error) {
477 /* Simple error codes. */
478 case 0x0000:
479 printf("no error");
480 break;
481 case 0x0001:
482 printf("unclassified error");
483 break;
484 case 0x0002:
485 printf("ucode ROM parity error");
486 break;
487 case 0x0003:
488 printf("external error");
489 break;
490 case 0x0004:
491 printf("FRC error");
492 break;
493 case 0x0005:
494 printf("internal parity error");
495 break;
496 case 0x0006:
497 printf("SMM handler code access violation");
498 break;
499 case 0x0400:
500 printf("internal timer error");
501 break;
502 case 0x0e0b:
503 printf("generic I/O error");
504 if (rec->mr_cpu_vendor_id == CPU_VENDOR_INTEL &&
505 (rec->mr_status & MC_STATUS_MISCV)) {
506 printf(" (pci%d:%d:%d:%d)",
507 (int)((rec->mr_misc & MC_MISC_PCIE_SEG) >> 32),
508 (int)((rec->mr_misc & MC_MISC_PCIE_BUS) >> 24),
509 (int)((rec->mr_misc & MC_MISC_PCIE_SLOT) >> 19),
510 (int)((rec->mr_misc & MC_MISC_PCIE_FUNC) >> 16));
511 }
512 break;
513 default:
514 if ((mca_error & 0xfc00) == 0x0400) {
515 printf("internal error %x", mca_error & 0x03ff);
516 break;
517 }
518
519 /* Compound error codes. */
520
521 /* Memory hierarchy error. */
522 if ((mca_error & 0xeffc) == 0x000c) {
523 printf("%s memory error", mca_error_level(mca_error));
524 break;
525 }
526
527 /* TLB error. */
528 if ((mca_error & 0xeff0) == 0x0010) {
529 printf("%sTLB %s error", mca_error_ttype(mca_error),
530 mca_error_level(mca_error));
531 break;
532 }
533
534 /* Memory controller error. */
535 if ((mca_error & 0xef80) == 0x0080) {
536 printf("%s channel ", mca_error_mmtype(mca_error));
537 if ((mca_error & 0x000f) != 0x000f)
538 printf("%d", mca_error & 0x000f);
539 else
540 printf("??");
541 printf(" memory error");
542 break;
543 }
544
545 /* Cache error. */
546 if ((mca_error & 0xef00) == 0x0100) {
547 printf("%sCACHE %s %s error",
548 mca_error_ttype(mca_error),
549 mca_error_level(mca_error),
550 mca_error_request(mca_error));
551 break;
552 }
553
554 /* Extended memory error. */
555 if ((mca_error & 0xef80) == 0x0280) {
556 printf("%s channel ", mca_error_mmtype(mca_error));
557 if ((mca_error & 0x000f) != 0x000f)
558 printf("%d", mca_error & 0x000f);
559 else
560 printf("??");
561 printf(" extended memory error");
562 break;
563 }
564
565 /* Bus and/or Interconnect error. */
566 if ((mca_error & 0xe800) == 0x0800) {
567 printf("BUS%s ", mca_error_level(mca_error));
568 switch ((mca_error & 0x0600) >> 9) {
569 case 0:
570 printf("Source");
571 break;
572 case 1:
573 printf("Responder");
574 break;
575 case 2:
576 printf("Observer");
577 break;
578 default:
579 printf("???");
580 break;
581 }
582 printf(" %s ", mca_error_request(mca_error));
583 switch ((mca_error & 0x000c) >> 2) {
584 case 0:
585 printf("Memory");
586 break;
587 case 2:
588 printf("I/O");
589 break;
590 case 3:
591 printf("Other");
592 break;
593 default:
594 printf("???");
595 break;
596 }
597 if (mca_error & 0x0100)
598 printf(" timed out");
599 break;
600 }
601
602 printf("unknown error %x", mca_error);
603 break;
604 }
605 printf("\n");
606 if (rec->mr_status & MC_STATUS_ADDRV) {
607 printf("MCA: Address 0x%llx", (long long)rec->mr_addr);
608 if (ser_supported(rec->mr_mcg_cap) &&
609 (rec->mr_status & MC_STATUS_MISCV)) {
610 printf(" (Mode: %s, LSB: %d)",
611 mca_addres_mode(rec->mr_misc),
612 (int)(rec->mr_misc & MC_MISC_RA_LSB));
613 }
614 printf("\n");
615 }
616 if (rec->mr_status & MC_STATUS_MISCV)
617 printf("MCA: Misc 0x%llx\n", (long long)rec->mr_misc);
618 }
619
620 static bool
mca_is_mce(uint64_t mcg_cap,uint64_t status,bool * recoverablep)621 mca_is_mce(uint64_t mcg_cap, uint64_t status, bool *recoverablep)
622 {
623
624 /* Corrected error. */
625 if ((status & MC_STATUS_UC) == 0)
626 return (0);
627
628 /* Spurious MCA error. */
629 if ((status & MC_STATUS_EN) == 0)
630 return (0);
631
632 /* The processor does not support software error recovery. */
633 if (!ser_supported(mcg_cap)) {
634 *recoverablep = false;
635 return (1);
636 }
637
638 /* Context might have been corrupted. */
639 if (status & MC_STATUS_PCC) {
640 *recoverablep = false;
641 return (1);
642 }
643
644 /* Uncorrected software recoverable. */
645 if (status & MC_STATUS_S) {
646 /* Action required vs optional. */
647 if (status & MC_STATUS_AR)
648 *recoverablep = false;
649 return (1);
650 }
651
652 /* Uncorrected no action required. */
653 return (0);
654 }
655
656 static int
mca_check_status(enum scan_mode mode,uint64_t mcg_cap,int bank,struct mca_record * rec,bool * recoverablep)657 mca_check_status(enum scan_mode mode, uint64_t mcg_cap, int bank,
658 struct mca_record *rec, bool *recoverablep)
659 {
660 uint64_t status;
661 u_int p[4];
662 bool mce, recover;
663
664 status = rdmsr(mca_msr_ops.status(bank));
665 if (!(status & MC_STATUS_VAL))
666 return (0);
667
668 recover = *recoverablep;
669 mce = mca_is_mce(mcg_cap, status, &recover);
670 if (mce != (mode == MCE))
671 return (0);
672 *recoverablep = recover;
673
674 /* Save exception information. */
675 rec->mr_status = status;
676 rec->mr_bank = bank;
677 rec->mr_addr = 0;
678 if (status & MC_STATUS_ADDRV)
679 rec->mr_addr = rdmsr(mca_msr_ops.addr(bank));
680 rec->mr_misc = 0;
681 if (status & MC_STATUS_MISCV)
682 rec->mr_misc = rdmsr(mca_msr_ops.misc(bank));
683 rec->mr_tsc = rdtsc();
684 rec->mr_apic_id = PCPU_GET(apic_id);
685 rec->mr_mcg_cap = rdmsr(MSR_MCG_CAP);
686 rec->mr_mcg_status = rdmsr(MSR_MCG_STATUS);
687 rec->mr_cpu_id = cpu_id;
688 rec->mr_cpu_vendor_id = cpu_vendor_id;
689 rec->mr_cpu = PCPU_GET(cpuid);
690
691 /*
692 * Clear machine check. Don't do this for uncorrectable
693 * errors so that the BIOS can see them.
694 */
695 if (!mce || recover) {
696 wrmsr(mca_msr_ops.status(bank), 0);
697 do_cpuid(0, p);
698 }
699 return (1);
700 }
701
702 static void
mca_resize_freelist(void)703 mca_resize_freelist(void)
704 {
705 struct mca_internal *next, *rec;
706 STAILQ_HEAD(, mca_internal) tmplist;
707 int count, i, desired_max, desired_min;
708
709 /*
710 * Ensure we have at least one record for each bank and one
711 * record per CPU, but no more than twice that amount.
712 */
713 desired_min = imax(mp_ncpus, mca_banks);
714 desired_max = imax(mp_ncpus, mca_banks) * 2;
715 STAILQ_INIT(&tmplist);
716 mtx_lock_spin(&mca_lock);
717 while (mca_freecount > desired_max) {
718 rec = STAILQ_FIRST(&mca_freelist);
719 KASSERT(rec != NULL, ("mca_freecount is %d, but list is empty",
720 mca_freecount));
721 STAILQ_REMOVE_HEAD(&mca_freelist, link);
722 mca_freecount--;
723 STAILQ_INSERT_TAIL(&tmplist, rec, link);
724 }
725 while (mca_freecount < desired_min) {
726 count = desired_min - mca_freecount;
727 mtx_unlock_spin(&mca_lock);
728 for (i = 0; i < count; i++) {
729 rec = malloc(sizeof(*rec), M_MCA, M_WAITOK);
730 STAILQ_INSERT_TAIL(&tmplist, rec, link);
731 }
732 mtx_lock_spin(&mca_lock);
733 STAILQ_CONCAT(&mca_freelist, &tmplist);
734 mca_freecount += count;
735 }
736 mtx_unlock_spin(&mca_lock);
737 STAILQ_FOREACH_SAFE(rec, &tmplist, link, next)
738 free(rec, M_MCA);
739 }
740
741 static void
mca_resize(void * context,int pending)742 mca_resize(void *context, int pending)
743 {
744
745 mca_resize_freelist();
746 }
747
748 static void
mca_record_entry(enum scan_mode mode,const struct mca_record * record)749 mca_record_entry(enum scan_mode mode, const struct mca_record *record)
750 {
751 struct mca_internal *rec;
752
753 if (mode == POLLED) {
754 rec = malloc(sizeof(*rec), M_MCA, M_WAITOK);
755 mtx_lock_spin(&mca_lock);
756 } else {
757 mtx_lock_spin(&mca_lock);
758 rec = STAILQ_FIRST(&mca_freelist);
759 if (rec == NULL) {
760 printf("MCA: Unable to allocate space for an event.\n");
761 mca_log(record);
762 mtx_unlock_spin(&mca_lock);
763 return;
764 }
765 STAILQ_REMOVE_HEAD(&mca_freelist, link);
766 mca_freecount--;
767 }
768
769 rec->rec = *record;
770 STAILQ_INSERT_TAIL(&mca_pending, rec, link);
771 mtx_unlock_spin(&mca_lock);
772 }
773
774 #ifdef DEV_APIC
775 /*
776 * Update the interrupt threshold for a CMCI. The strategy is to use
777 * a low trigger that interrupts as soon as the first event occurs.
778 * However, if a steady stream of events arrive, the threshold is
779 * increased until the interrupts are throttled to once every
780 * cmc_throttle seconds or the periodic scan. If a periodic scan
781 * finds that the threshold is too high, it is lowered.
782 */
783 static int
update_threshold(enum scan_mode mode,int valid,int last_intr,int count,int cur_threshold,int max_threshold)784 update_threshold(enum scan_mode mode, int valid, int last_intr, int count,
785 int cur_threshold, int max_threshold)
786 {
787 u_int delta;
788 int limit;
789
790 delta = (u_int)(time_uptime - last_intr);
791 limit = cur_threshold;
792
793 /*
794 * If an interrupt was received less than cmc_throttle seconds
795 * since the previous interrupt and the count from the current
796 * event is greater than or equal to the current threshold,
797 * double the threshold up to the max.
798 */
799 if (mode == CMCI && valid) {
800 if (delta < cmc_throttle && count >= limit &&
801 limit < max_threshold) {
802 limit = min(limit << 1, max_threshold);
803 }
804 return (limit);
805 }
806
807 /*
808 * When the banks are polled, check to see if the threshold
809 * should be lowered.
810 */
811 if (mode != POLLED)
812 return (limit);
813
814 /* If a CMCI occurred recently, do nothing for now. */
815 if (delta < cmc_throttle)
816 return (limit);
817
818 /*
819 * Compute a new limit based on the average rate of events per
820 * cmc_throttle seconds since the last interrupt.
821 */
822 if (valid) {
823 limit = count * cmc_throttle / delta;
824 if (limit <= 0)
825 limit = 1;
826 else if (limit > max_threshold)
827 limit = max_threshold;
828 } else {
829 limit = 1;
830 }
831 return (limit);
832 }
833
834 static void
cmci_update(enum scan_mode mode,int bank,int valid,struct mca_record * rec)835 cmci_update(enum scan_mode mode, int bank, int valid, struct mca_record *rec)
836 {
837 struct cmc_state *cc;
838 uint64_t ctl;
839 int cur_threshold, new_threshold;
840 int count;
841
842 /* Fetch the current limit for this bank. */
843 cc = &cmc_state[PCPU_GET(cpuid)][bank];
844 ctl = rdmsr(MSR_MC_CTL2(bank));
845 count = (rec->mr_status & MC_STATUS_COR_COUNT) >> 38;
846 cur_threshold = ctl & MC_CTL2_THRESHOLD;
847
848 new_threshold = update_threshold(mode, valid, cc->last_intr, count,
849 cur_threshold, cc->max_threshold);
850
851 if (mode == CMCI && valid)
852 cc->last_intr = time_uptime;
853 if (new_threshold != cur_threshold) {
854 ctl &= ~MC_CTL2_THRESHOLD;
855 ctl |= new_threshold;
856 wrmsr(MSR_MC_CTL2(bank), ctl);
857 }
858 }
859
860 static void
amd_thresholding_update(enum scan_mode mode,int bank,int valid)861 amd_thresholding_update(enum scan_mode mode, int bank, int valid)
862 {
863 struct amd_et_state *cc;
864 uint64_t misc;
865 int new_threshold;
866 int count;
867
868 cc = &amd_et_state[PCPU_GET(cpuid)][bank];
869 misc = rdmsr(mca_msr_ops.misc(bank));
870 count = (misc & MC_MISC_AMD_CNT_MASK) >> MC_MISC_AMD_CNT_SHIFT;
871 count = count - (MC_MISC_AMD_CNT_MAX - cc->cur_threshold);
872
873 new_threshold = update_threshold(mode, valid, cc->last_intr, count,
874 cc->cur_threshold, MC_MISC_AMD_CNT_MAX);
875
876 cc->cur_threshold = new_threshold;
877 misc &= ~MC_MISC_AMD_CNT_MASK;
878 misc |= (uint64_t)(MC_MISC_AMD_CNT_MAX - cc->cur_threshold)
879 << MC_MISC_AMD_CNT_SHIFT;
880 misc &= ~MC_MISC_AMD_OVERFLOW;
881 wrmsr(mca_msr_ops.misc(bank), misc);
882 if (mode == CMCI && valid)
883 cc->last_intr = time_uptime;
884 }
885 #endif
886
887 /*
888 * This scans all the machine check banks of the current CPU to see if
889 * there are any machine checks. Any non-recoverable errors are
890 * reported immediately via mca_log(). The current thread must be
891 * pinned when this is called. The 'mode' parameter indicates if we
892 * are being called from the MC exception handler, the CMCI handler,
893 * or the periodic poller.
894 */
895 static int
mca_scan(enum scan_mode mode,bool * recoverablep)896 mca_scan(enum scan_mode mode, bool *recoverablep)
897 {
898 struct mca_record rec;
899 uint64_t mcg_cap;
900 int count = 0, i, valid;
901
902 mcg_cap = rdmsr(MSR_MCG_CAP);
903 for (i = 0; i < (mcg_cap & MCG_CAP_COUNT); i++) {
904 #ifdef DEV_APIC
905 /*
906 * For a CMCI, only check banks this CPU is
907 * responsible for.
908 */
909 if (mode == CMCI && !(PCPU_GET(cmci_mask) & 1 << i))
910 continue;
911 #endif
912
913 valid = mca_check_status(mode, mcg_cap, i, &rec, recoverablep);
914 if (valid) {
915 count++;
916 if (*recoverablep)
917 mca_record_entry(mode, &rec);
918 else
919 mca_log(&rec);
920 }
921
922 #ifdef DEV_APIC
923 /*
924 * If this is a bank this CPU monitors via CMCI,
925 * update the threshold.
926 */
927 if (PCPU_GET(cmci_mask) & 1 << i) {
928 if (cmc_state != NULL)
929 cmci_update(mode, i, valid, &rec);
930 else
931 amd_thresholding_update(mode, i, valid);
932 }
933 #endif
934 }
935 return (count);
936 }
937
938 /*
939 * Store a new record on the mca_records list while enforcing
940 * mca_maxcount.
941 */
942 static void
mca_store_record(struct mca_internal * mca)943 mca_store_record(struct mca_internal *mca)
944 {
945
946 /*
947 * If we are storing no records (mca_maxcount == 0),
948 * we just free this record.
949 *
950 * If we are storing records (mca_maxcount != 0) and
951 * we have free space on the list, store the record
952 * and increment mca_count.
953 *
954 * If we are storing records and we do not have free
955 * space on the list, store the new record at the
956 * tail and free the oldest one from the head.
957 */
958 if (mca_maxcount != 0)
959 STAILQ_INSERT_TAIL(&mca_records, mca, link);
960 if (mca_maxcount < 0 || mca_count < mca_maxcount)
961 mca_count++;
962 else {
963 if (mca_maxcount != 0) {
964 mca = STAILQ_FIRST(&mca_records);
965 STAILQ_REMOVE_HEAD(&mca_records, link);
966 }
967 STAILQ_INSERT_TAIL(&mca_freelist, mca, link);
968 mca_freecount++;
969 }
970 }
971
972 /*
973 * Do the work to process machine check records which have just been
974 * gathered. Print any pending logs to the console. Queue them for storage.
975 * Trigger a resizing of the free list.
976 */
977 static void
mca_process_records(enum scan_mode mode)978 mca_process_records(enum scan_mode mode)
979 {
980 struct mca_internal *mca;
981
982 mtx_lock_spin(&mca_lock);
983 while ((mca = STAILQ_FIRST(&mca_pending)) != NULL) {
984 STAILQ_REMOVE_HEAD(&mca_pending, link);
985 mca_log(&mca->rec);
986 mca_store_record(mca);
987 }
988 mtx_unlock_spin(&mca_lock);
989 if (mode == POLLED)
990 mca_resize_freelist();
991 else if (!cold)
992 taskqueue_enqueue(mca_tq, &mca_resize_task);
993 }
994
995 /*
996 * Scan the machine check banks on all CPUs by binding to each CPU in
997 * turn. If any of the CPUs contained new machine check records, log
998 * them to the console.
999 */
1000 static void
mca_scan_cpus(void * context,int pending)1001 mca_scan_cpus(void *context, int pending)
1002 {
1003 struct thread *td;
1004 int cpu;
1005 bool recoverable = true;
1006
1007 mca_resize_freelist();
1008 td = curthread;
1009 thread_lock(td);
1010 CPU_FOREACH(cpu) {
1011 sched_bind(td, cpu);
1012 thread_unlock(td);
1013 mca_scan(POLLED, &recoverable);
1014 thread_lock(td);
1015 sched_unbind(td);
1016 }
1017 thread_unlock(td);
1018 if (!STAILQ_EMPTY(&mca_pending))
1019 mca_process_records(POLLED);
1020 taskqueue_enqueue_timeout_sbt(mca_tq, &mca_scan_task,
1021 mca_ticks * SBT_1S, 0, C_PREL(1));
1022 }
1023
1024 static int
sysctl_mca_scan(SYSCTL_HANDLER_ARGS)1025 sysctl_mca_scan(SYSCTL_HANDLER_ARGS)
1026 {
1027 int error, i;
1028
1029 i = 0;
1030 error = sysctl_handle_int(oidp, &i, 0, req);
1031 if (error)
1032 return (error);
1033 if (i)
1034 taskqueue_enqueue_timeout_sbt(mca_tq, &mca_scan_task,
1035 0, 0, 0);
1036 return (0);
1037 }
1038
1039 static int
sysctl_mca_maxcount(SYSCTL_HANDLER_ARGS)1040 sysctl_mca_maxcount(SYSCTL_HANDLER_ARGS)
1041 {
1042 struct mca_internal *mca;
1043 int error, i;
1044 bool doresize;
1045
1046 i = mca_maxcount;
1047 error = sysctl_handle_int(oidp, &i, 0, req);
1048 if (error || req->newptr == NULL)
1049 return (error);
1050 mtx_lock_spin(&mca_lock);
1051 mca_maxcount = i;
1052 doresize = false;
1053 if (mca_maxcount >= 0)
1054 while (mca_count > mca_maxcount) {
1055 mca = STAILQ_FIRST(&mca_records);
1056 STAILQ_REMOVE_HEAD(&mca_records, link);
1057 mca_count--;
1058 STAILQ_INSERT_TAIL(&mca_freelist, mca, link);
1059 mca_freecount++;
1060 doresize = true;
1061 }
1062 mtx_unlock_spin(&mca_lock);
1063 if (doresize && !cold)
1064 taskqueue_enqueue(mca_tq, &mca_resize_task);
1065 return (error);
1066 }
1067
1068 static void
mca_startup(void * dummy)1069 mca_startup(void *dummy)
1070 {
1071
1072 if (mca_banks <= 0)
1073 return;
1074
1075 /* CMCIs during boot may have claimed items from the freelist. */
1076 mca_resize_freelist();
1077
1078 taskqueue_start_threads(&mca_tq, 1, PI_SWI(SWI_TQ), "mca taskq");
1079 taskqueue_enqueue_timeout_sbt(mca_tq, &mca_scan_task,
1080 mca_ticks * SBT_1S, 0, C_PREL(1));
1081 }
1082 SYSINIT(mca_startup, SI_SUB_KICK_SCHEDULER, SI_ORDER_ANY, mca_startup, NULL);
1083
1084 #ifdef DEV_APIC
1085 static void
cmci_setup(void)1086 cmci_setup(void)
1087 {
1088 int i;
1089
1090 cmc_state = malloc((mp_maxid + 1) * sizeof(struct cmc_state *), M_MCA,
1091 M_WAITOK);
1092 for (i = 0; i <= mp_maxid; i++)
1093 cmc_state[i] = malloc(sizeof(struct cmc_state) * mca_banks,
1094 M_MCA, M_WAITOK | M_ZERO);
1095 SYSCTL_ADD_PROC(NULL, SYSCTL_STATIC_CHILDREN(_hw_mca), OID_AUTO,
1096 "cmc_throttle", CTLTYPE_INT | CTLFLAG_RWTUN | CTLFLAG_MPSAFE,
1097 &cmc_throttle, 0, sysctl_positive_int, "I",
1098 "Interval in seconds to throttle corrected MC interrupts");
1099 }
1100
1101 static void
amd_thresholding_setup(void)1102 amd_thresholding_setup(void)
1103 {
1104 u_int i;
1105
1106 amd_et_state = malloc((mp_maxid + 1) * sizeof(struct amd_et_state *),
1107 M_MCA, M_WAITOK);
1108 for (i = 0; i <= mp_maxid; i++)
1109 amd_et_state[i] = malloc(sizeof(struct amd_et_state) *
1110 mca_banks, M_MCA, M_WAITOK | M_ZERO);
1111 SYSCTL_ADD_PROC(NULL, SYSCTL_STATIC_CHILDREN(_hw_mca), OID_AUTO,
1112 "cmc_throttle", CTLTYPE_INT | CTLFLAG_RWTUN | CTLFLAG_MPSAFE,
1113 &cmc_throttle, 0, sysctl_positive_int, "I",
1114 "Interval in seconds to throttle corrected MC interrupts");
1115 }
1116 #endif
1117
1118 static void
mca_setup(uint64_t mcg_cap)1119 mca_setup(uint64_t mcg_cap)
1120 {
1121
1122 /*
1123 * On AMD Family 10h processors, unless logging of level one TLB
1124 * parity (L1TP) errors is disabled, enable the recommended workaround
1125 * for Erratum 383.
1126 */
1127 if (cpu_vendor_id == CPU_VENDOR_AMD &&
1128 CPUID_TO_FAMILY(cpu_id) == 0x10 && amd10h_L1TP)
1129 workaround_erratum383 = 1;
1130
1131 mca_banks = mcg_cap & MCG_CAP_COUNT;
1132 mtx_init(&mca_lock, "mca", NULL, MTX_SPIN);
1133 STAILQ_INIT(&mca_records);
1134 STAILQ_INIT(&mca_pending);
1135 mca_tq = taskqueue_create_fast("mca", M_WAITOK,
1136 taskqueue_thread_enqueue, &mca_tq);
1137 TIMEOUT_TASK_INIT(mca_tq, &mca_scan_task, 0, mca_scan_cpus, NULL);
1138 STAILQ_INIT(&mca_freelist);
1139 TASK_INIT(&mca_resize_task, 0, mca_resize, NULL);
1140 mca_resize_freelist();
1141 SYSCTL_ADD_INT(NULL, SYSCTL_STATIC_CHILDREN(_hw_mca), OID_AUTO,
1142 "count", CTLFLAG_RD, (int *)(uintptr_t)&mca_count, 0,
1143 "Record count");
1144 SYSCTL_ADD_PROC(NULL, SYSCTL_STATIC_CHILDREN(_hw_mca), OID_AUTO,
1145 "maxcount", CTLTYPE_INT | CTLFLAG_RWTUN | CTLFLAG_MPSAFE,
1146 &mca_maxcount, 0, sysctl_mca_maxcount, "I",
1147 "Maximum record count (-1 is unlimited)");
1148 SYSCTL_ADD_PROC(NULL, SYSCTL_STATIC_CHILDREN(_hw_mca), OID_AUTO,
1149 "interval", CTLTYPE_INT | CTLFLAG_RWTUN | CTLFLAG_MPSAFE,
1150 &mca_ticks, 0, sysctl_positive_int, "I",
1151 "Periodic interval in seconds to scan for machine checks");
1152 SYSCTL_ADD_NODE(NULL, SYSCTL_STATIC_CHILDREN(_hw_mca), OID_AUTO,
1153 "records", CTLFLAG_RD | CTLFLAG_MPSAFE, sysctl_mca_records,
1154 "Machine check records");
1155 SYSCTL_ADD_PROC(NULL, SYSCTL_STATIC_CHILDREN(_hw_mca), OID_AUTO,
1156 "force_scan", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, NULL, 0,
1157 sysctl_mca_scan, "I", "Force an immediate scan for machine checks");
1158 #ifdef DEV_APIC
1159 if (cmci_supported(mcg_cap))
1160 cmci_setup();
1161 else if (amd_thresholding_supported())
1162 amd_thresholding_setup();
1163 #endif
1164 }
1165
1166 #ifdef DEV_APIC
1167 /*
1168 * See if we should monitor CMCI for this bank. If CMCI_EN is already
1169 * set in MC_CTL2, then another CPU is responsible for this bank, so
1170 * ignore it. If CMCI_EN returns zero after being set, then this bank
1171 * does not support CMCI_EN. If this CPU sets CMCI_EN, then it should
1172 * now monitor this bank.
1173 */
1174 static void
cmci_monitor(int i)1175 cmci_monitor(int i)
1176 {
1177 struct cmc_state *cc;
1178 uint64_t ctl;
1179
1180 KASSERT(i < mca_banks, ("CPU %d has more MC banks", PCPU_GET(cpuid)));
1181
1182 /*
1183 * It is possible for some APs to report CMCI support even if the BSP
1184 * does not, apparently due to a BIOS bug.
1185 */
1186 if (cmc_state == NULL) {
1187 if (bootverbose) {
1188 printf(
1189 "AP %d (%d,%d) reports CMCI support but the BSP does not\n",
1190 PCPU_GET(cpuid), PCPU_GET(apic_id),
1191 PCPU_GET(acpi_id));
1192 }
1193 return;
1194 }
1195
1196 ctl = rdmsr(MSR_MC_CTL2(i));
1197 if (ctl & MC_CTL2_CMCI_EN)
1198 /* Already monitored by another CPU. */
1199 return;
1200
1201 /* Set the threshold to one event for now. */
1202 ctl &= ~MC_CTL2_THRESHOLD;
1203 ctl |= MC_CTL2_CMCI_EN | 1;
1204 wrmsr(MSR_MC_CTL2(i), ctl);
1205 ctl = rdmsr(MSR_MC_CTL2(i));
1206 if (!(ctl & MC_CTL2_CMCI_EN))
1207 /* This bank does not support CMCI. */
1208 return;
1209
1210 cc = &cmc_state[PCPU_GET(cpuid)][i];
1211
1212 /* Determine maximum threshold. */
1213 ctl &= ~MC_CTL2_THRESHOLD;
1214 ctl |= 0x7fff;
1215 wrmsr(MSR_MC_CTL2(i), ctl);
1216 ctl = rdmsr(MSR_MC_CTL2(i));
1217 cc->max_threshold = ctl & MC_CTL2_THRESHOLD;
1218
1219 /* Start off with a threshold of 1. */
1220 ctl &= ~MC_CTL2_THRESHOLD;
1221 ctl |= 1;
1222 wrmsr(MSR_MC_CTL2(i), ctl);
1223
1224 /* Mark this bank as monitored. */
1225 PCPU_SET(cmci_mask, PCPU_GET(cmci_mask) | 1 << i);
1226 }
1227
1228 /*
1229 * For resume, reset the threshold for any banks we monitor back to
1230 * one and throw away the timestamp of the last interrupt.
1231 */
1232 static void
cmci_resume(int i)1233 cmci_resume(int i)
1234 {
1235 struct cmc_state *cc;
1236 uint64_t ctl;
1237
1238 KASSERT(i < mca_banks, ("CPU %d has more MC banks", PCPU_GET(cpuid)));
1239
1240 /* See cmci_monitor(). */
1241 if (cmc_state == NULL)
1242 return;
1243
1244 /* Ignore banks not monitored by this CPU. */
1245 if (!(PCPU_GET(cmci_mask) & 1 << i))
1246 return;
1247
1248 cc = &cmc_state[PCPU_GET(cpuid)][i];
1249 cc->last_intr = 0;
1250 ctl = rdmsr(MSR_MC_CTL2(i));
1251 ctl &= ~MC_CTL2_THRESHOLD;
1252 ctl |= MC_CTL2_CMCI_EN | 1;
1253 wrmsr(MSR_MC_CTL2(i), ctl);
1254 }
1255
1256 /*
1257 * Apply an AMD ET configuration to the corresponding MSR.
1258 */
1259 static void
amd_thresholding_start(struct amd_et_state * cc,int bank)1260 amd_thresholding_start(struct amd_et_state *cc, int bank)
1261 {
1262 uint64_t misc;
1263
1264 KASSERT(amd_elvt >= 0, ("ELVT offset is not set"));
1265
1266 misc = rdmsr(mca_msr_ops.misc(bank));
1267
1268 misc &= ~MC_MISC_AMD_INT_MASK;
1269 misc |= MC_MISC_AMD_INT_LVT;
1270
1271 misc &= ~MC_MISC_AMD_LVT_MASK;
1272 misc |= (uint64_t)amd_elvt << MC_MISC_AMD_LVT_SHIFT;
1273
1274 misc &= ~MC_MISC_AMD_CNT_MASK;
1275 misc |= (uint64_t)(MC_MISC_AMD_CNT_MAX - cc->cur_threshold)
1276 << MC_MISC_AMD_CNT_SHIFT;
1277
1278 misc &= ~MC_MISC_AMD_OVERFLOW;
1279 misc |= MC_MISC_AMD_CNTEN;
1280
1281 wrmsr(mca_msr_ops.misc(bank), misc);
1282 }
1283
1284 static void
amd_thresholding_monitor(int i)1285 amd_thresholding_monitor(int i)
1286 {
1287 struct amd_et_state *cc;
1288 uint64_t misc;
1289
1290 /*
1291 * Kludge: On 10h, banks after 4 are not thresholding but also may have
1292 * bogus Valid bits. Skip them. This is definitely fixed in 15h, but
1293 * I have not investigated whether it is fixed in earlier models.
1294 */
1295 if (CPUID_TO_FAMILY(cpu_id) < 0x15 && i >= 5)
1296 return;
1297
1298 /* The counter must be valid and present. */
1299 misc = rdmsr(mca_msr_ops.misc(i));
1300 if ((misc & (MC_MISC_AMD_VAL | MC_MISC_AMD_CNTP)) !=
1301 (MC_MISC_AMD_VAL | MC_MISC_AMD_CNTP))
1302 return;
1303
1304 /* The register should not be locked. */
1305 if ((misc & MC_MISC_AMD_LOCK) != 0) {
1306 if (bootverbose)
1307 printf("%s: 0x%jx: Bank %d: locked\n", __func__,
1308 (uintmax_t)misc, i);
1309 return;
1310 }
1311
1312 /*
1313 * If counter is enabled then either the firmware or another CPU
1314 * has already claimed it.
1315 */
1316 if ((misc & MC_MISC_AMD_CNTEN) != 0) {
1317 if (bootverbose)
1318 printf("%s: 0x%jx: Bank %d: already enabled\n",
1319 __func__, (uintmax_t)misc, i);
1320 return;
1321 }
1322
1323 /*
1324 * Configure an Extended Interrupt LVT register for reporting
1325 * counter overflows if that feature is supported and the first
1326 * extended register is available.
1327 */
1328 amd_elvt = lapic_enable_mca_elvt();
1329 if (amd_elvt < 0) {
1330 printf("%s: Bank %d: lapic enable mca elvt failed: %d\n",
1331 __func__, i, amd_elvt);
1332 return;
1333 }
1334
1335 cc = &amd_et_state[PCPU_GET(cpuid)][i];
1336 cc->cur_threshold = 1;
1337 amd_thresholding_start(cc, i);
1338
1339 /* Mark this bank as monitored. */
1340 PCPU_SET(cmci_mask, PCPU_GET(cmci_mask) | 1 << i);
1341 }
1342
1343 static void
amd_thresholding_resume(int i)1344 amd_thresholding_resume(int i)
1345 {
1346 struct amd_et_state *cc;
1347
1348 KASSERT(i < mca_banks, ("CPU %d has more MC banks", PCPU_GET(cpuid)));
1349
1350 /* Ignore banks not monitored by this CPU. */
1351 if (!(PCPU_GET(cmci_mask) & 1 << i))
1352 return;
1353
1354 cc = &amd_et_state[PCPU_GET(cpuid)][i];
1355 cc->last_intr = 0;
1356 cc->cur_threshold = 1;
1357 amd_thresholding_start(cc, i);
1358 }
1359 #endif
1360
1361 /*
1362 * Initializes per-CPU machine check registers and enables corrected
1363 * machine check interrupts.
1364 */
1365 static void
_mca_init(int boot)1366 _mca_init(int boot)
1367 {
1368 uint64_t mcg_cap;
1369 uint64_t ctl, mask;
1370 int i, skip, family;
1371
1372 family = CPUID_TO_FAMILY(cpu_id);
1373
1374 /* MCE is required. */
1375 if (!mca_enabled || !(cpu_feature & CPUID_MCE))
1376 return;
1377
1378 if (cpu_feature & CPUID_MCA) {
1379 if (boot)
1380 PCPU_SET(cmci_mask, 0);
1381
1382 mcg_cap = rdmsr(MSR_MCG_CAP);
1383 if (mcg_cap & MCG_CAP_CTL_P)
1384 /* Enable MCA features. */
1385 wrmsr(MSR_MCG_CTL, MCG_CTL_ENABLE);
1386 if (IS_BSP() && boot)
1387 mca_setup(mcg_cap);
1388
1389 /*
1390 * Disable logging of level one TLB parity (L1TP) errors by
1391 * the data cache as an alternative workaround for AMD Family
1392 * 10h Erratum 383. Unlike the recommended workaround, there
1393 * is no performance penalty to this workaround. However,
1394 * L1TP errors will go unreported.
1395 */
1396 if (cpu_vendor_id == CPU_VENDOR_AMD && family == 0x10 &&
1397 !amd10h_L1TP) {
1398 mask = rdmsr(MSR_MC0_CTL_MASK);
1399 if ((mask & (1UL << 5)) == 0)
1400 wrmsr(MSR_MC0_CTL_MASK, mask | (1UL << 5));
1401 }
1402 if (amd_rascap & AMDRAS_SCALABLE_MCA) {
1403 mca_msr_ops.ctl = mca_smca_ctl_reg;
1404 mca_msr_ops.status = mca_smca_status_reg;
1405 mca_msr_ops.addr = mca_smca_addr_reg;
1406 mca_msr_ops.misc = mca_smca_misc_reg;
1407 }
1408
1409 /* Enable local MCE if supported. */
1410 if (cpu_vendor_id == CPU_VENDOR_INTEL &&
1411 (mcg_cap & MCG_CAP_LMCE_P) &&
1412 (rdmsr(MSR_IA32_FEATURE_CONTROL) &
1413 IA32_FEATURE_CONTROL_LMCE_EN))
1414 wrmsr(MSR_MCG_EXT_CTL, rdmsr(MSR_MCG_EXT_CTL) | 1);
1415
1416 /*
1417 * The cmci_monitor() must not be executed
1418 * simultaneously by several CPUs.
1419 */
1420 if (boot)
1421 mtx_lock_spin(&mca_lock);
1422
1423 for (i = 0; i < (mcg_cap & MCG_CAP_COUNT); i++) {
1424 /* By default enable logging of all errors. */
1425 ctl = 0xffffffffffffffffUL;
1426 skip = 0;
1427
1428 if (cpu_vendor_id == CPU_VENDOR_INTEL) {
1429 /*
1430 * For P6 models before Nehalem MC0_CTL is
1431 * always enabled and reserved.
1432 */
1433 if (i == 0 && family == 0x6
1434 && CPUID_TO_MODEL(cpu_id) < 0x1a)
1435 skip = 1;
1436 } else if (cpu_vendor_id == CPU_VENDOR_AMD) {
1437 /* BKDG for Family 10h: unset GartTblWkEn. */
1438 if (i == MC_AMDNB_BANK && family >= 0xf &&
1439 family < 0x17)
1440 ctl &= ~(1UL << 10);
1441 }
1442
1443 if (!skip)
1444 wrmsr(mca_msr_ops.ctl(i), ctl);
1445
1446 #ifdef DEV_APIC
1447 if (cmci_supported(mcg_cap)) {
1448 if (boot)
1449 cmci_monitor(i);
1450 else
1451 cmci_resume(i);
1452 } else if (amd_thresholding_supported()) {
1453 if (boot)
1454 amd_thresholding_monitor(i);
1455 else
1456 amd_thresholding_resume(i);
1457 }
1458 #endif
1459
1460 /* Clear all errors. */
1461 wrmsr(mca_msr_ops.status(i), 0);
1462 }
1463 if (boot)
1464 mtx_unlock_spin(&mca_lock);
1465
1466 #ifdef DEV_APIC
1467 if (cmci_supported(mcg_cap) &&
1468 PCPU_GET(cmci_mask) != 0 && boot)
1469 lapic_enable_cmc();
1470 #endif
1471 }
1472
1473 load_cr4(rcr4() | CR4_MCE);
1474 }
1475
1476 /* Must be executed on each CPU during boot. */
1477 void
mca_init(void)1478 mca_init(void)
1479 {
1480
1481 _mca_init(1);
1482 }
1483
1484 /* Must be executed on each CPU during resume. */
1485 void
mca_resume(void)1486 mca_resume(void)
1487 {
1488
1489 _mca_init(0);
1490 }
1491
1492 /*
1493 * The machine check registers for the BSP cannot be initialized until
1494 * the local APIC is initialized. This happens at SI_SUB_CPU,
1495 * SI_ORDER_SECOND.
1496 */
1497 static void
mca_init_bsp(void * arg __unused)1498 mca_init_bsp(void *arg __unused)
1499 {
1500
1501 mca_init();
1502 }
1503 SYSINIT(mca_init_bsp, SI_SUB_CPU, SI_ORDER_ANY, mca_init_bsp, NULL);
1504
1505 /* Called when a machine check exception fires. */
1506 void
mca_intr(void)1507 mca_intr(void)
1508 {
1509 uint64_t mcg_status;
1510 int count;
1511 bool lmcs, recoverable;
1512
1513 if (!(cpu_feature & CPUID_MCA)) {
1514 /*
1515 * Just print the values of the old Pentium registers
1516 * and panic.
1517 */
1518 printf("MC Type: 0x%jx Address: 0x%jx\n",
1519 (uintmax_t)rdmsr(MSR_P5_MC_TYPE),
1520 (uintmax_t)rdmsr(MSR_P5_MC_ADDR));
1521 panic("Machine check exception");
1522 }
1523
1524 /* Scan the banks and check for any non-recoverable errors. */
1525 mcg_status = rdmsr(MSR_MCG_STATUS);
1526 recoverable = (mcg_status & MCG_STATUS_RIPV) != 0;
1527 lmcs = (cpu_vendor_id != CPU_VENDOR_INTEL ||
1528 (mcg_status & MCG_STATUS_LMCS));
1529 count = mca_scan(MCE, &recoverable);
1530
1531 if (!recoverable) {
1532 /*
1533 * Only panic if the error was detected local to this CPU.
1534 * Some errors will assert a machine check on all CPUs, but
1535 * only certain CPUs will find a valid bank to log.
1536 */
1537 while (!lmcs && count == 0)
1538 cpu_spinwait();
1539
1540 panic("Unrecoverable machine check exception");
1541 }
1542
1543 /* Clear MCIP. */
1544 wrmsr(MSR_MCG_STATUS, mcg_status & ~MCG_STATUS_MCIP);
1545 }
1546
1547 #ifdef DEV_APIC
1548 /* Called for a CMCI (correctable machine check interrupt). */
1549 void
cmc_intr(void)1550 cmc_intr(void)
1551 {
1552 bool recoverable = true;
1553
1554 /*
1555 * Serialize MCA bank scanning to prevent collisions from
1556 * sibling threads.
1557 *
1558 * If we found anything, log them to the console.
1559 */
1560 if (mca_scan(CMCI, &recoverable) != 0)
1561 mca_process_records(CMCI);
1562 }
1563 #endif
1564