xref: /linux/drivers/memory/tegra/mc.h (revision cdd5b5a9761fd66d17586e4f4ba6588c70e640ea)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (C) 2014 NVIDIA CORPORATION.  All rights reserved.
4  */
5 
6 #ifndef MEMORY_TEGRA_MC_H
7 #define MEMORY_TEGRA_MC_H
8 
9 #include <linux/bits.h>
10 #include <linux/io.h>
11 #include <linux/types.h>
12 
13 #include <soc/tegra/mc.h>
14 
15 #define MC_INTSTATUS					0x00
16 #define MC_INTMASK					0x04
17 #define MC_ERR_STATUS					0x08
18 #define MC_ERR_ADR					0x0c
19 #define MC_GART_ERROR_REQ				0x30
20 #define MC_EMEM_ADR_CFG					0x54
21 #define MC_DECERR_EMEM_OTHERS_STATUS			0x58
22 #define MC_SECURITY_VIOLATION_STATUS			0x74
23 #define MC_EMEM_ARB_CFG					0x90
24 #define MC_EMEM_ARB_OUTSTANDING_REQ			0x94
25 #define MC_EMEM_ARB_TIMING_RCD				0x98
26 #define MC_EMEM_ARB_TIMING_RP				0x9c
27 #define MC_EMEM_ARB_TIMING_RC				0xa0
28 #define MC_EMEM_ARB_TIMING_RAS				0xa4
29 #define MC_EMEM_ARB_TIMING_FAW				0xa8
30 #define MC_EMEM_ARB_TIMING_RRD				0xac
31 #define MC_EMEM_ARB_TIMING_RAP2PRE			0xb0
32 #define MC_EMEM_ARB_TIMING_WAP2PRE			0xb4
33 #define MC_EMEM_ARB_TIMING_R2R				0xb8
34 #define MC_EMEM_ARB_TIMING_W2W				0xbc
35 #define MC_EMEM_ARB_TIMING_R2W				0xc0
36 #define MC_EMEM_ARB_TIMING_W2R				0xc4
37 #define MC_EMEM_ARB_MISC2				0xc8
38 #define MC_EMEM_ARB_DA_TURNS				0xd0
39 #define MC_EMEM_ARB_DA_COVERS				0xd4
40 #define MC_EMEM_ARB_MISC0				0xd8
41 #define MC_EMEM_ARB_MISC1				0xdc
42 #define MC_EMEM_ARB_RING1_THROTTLE			0xe0
43 #define MC_EMEM_ARB_OVERRIDE				0xe8
44 #define MC_TIMING_CONTROL_DBG				0xf8
45 #define MC_TIMING_CONTROL				0xfc
46 #define MC_ERR_VPR_STATUS				0x654
47 #define MC_ERR_VPR_ADR					0x658
48 #define MC_ERR_SEC_STATUS				0x67c
49 #define MC_ERR_SEC_ADR					0x680
50 #define MC_ERR_MTS_STATUS				0x9b0
51 #define MC_ERR_MTS_ADR					0x9b4
52 #define MC_ERR_ROUTE_SANITY_STATUS			0x9c0
53 #define MC_ERR_ROUTE_SANITY_ADR				0x9c4
54 #define MC_ERR_GENERALIZED_CARVEOUT_STATUS		0xc00
55 #define MC_ERR_GENERALIZED_CARVEOUT_ADR			0xc04
56 #define MC_EMEM_ADR_CFG_CHANNEL_ENABLE			0xdf8
57 #define MC_GLOBAL_INTSTATUS				0xf24
58 #define MC_ERR_ADR_HI					0x11fc
59 
60 #define MC_INT_DECERR_ROUTE_SANITY			BIT(20)
61 #define MC_INT_DECERR_GENERALIZED_CARVEOUT		BIT(17)
62 #define MC_INT_DECERR_MTS				BIT(16)
63 #define MC_INT_SECERR_SEC				BIT(13)
64 #define MC_INT_DECERR_VPR				BIT(12)
65 #define MC_INT_INVALID_APB_ASID_UPDATE			BIT(11)
66 #define MC_INT_INVALID_SMMU_PAGE			BIT(10)
67 #define MC_INT_ARBITRATION_EMEM				BIT(9)
68 #define MC_INT_SECURITY_VIOLATION			BIT(8)
69 #define MC_INT_INVALID_GART_PAGE			BIT(7)
70 #define MC_INT_DECERR_EMEM				BIT(6)
71 
72 #define MC_ERR_STATUS_TYPE_SHIFT			28
73 #define MC_ERR_STATUS_TYPE_INVALID_SMMU_PAGE		(0x6 << 28)
74 #define MC_ERR_STATUS_TYPE_MASK				(0x7 << 28)
75 #define MC_ERR_STATUS_READABLE				BIT(27)
76 #define MC_ERR_STATUS_WRITABLE				BIT(26)
77 #define MC_ERR_STATUS_NONSECURE				BIT(25)
78 #define MC_ERR_STATUS_ADR_HI_SHIFT			20
79 #define MC_ERR_STATUS_ADR_HI_MASK			0x3
80 #define MC_ERR_STATUS_SECURITY				BIT(17)
81 #define MC_ERR_STATUS_RW				BIT(16)
82 
83 #define MC_EMEM_ADR_CFG_EMEM_NUMDEV			BIT(0)
84 
85 #define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE(x)		((x) & 0x1ff)
86 #define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK		0x1ff
87 
88 #define MC_EMEM_ARB_OUTSTANDING_REQ_MAX_MASK		0x1ff
89 #define MC_EMEM_ARB_OUTSTANDING_REQ_HOLDOFF_OVERRIDE	BIT(30)
90 #define MC_EMEM_ARB_OUTSTANDING_REQ_LIMIT_ENABLE	BIT(31)
91 
92 #define MC_EMEM_ARB_OVERRIDE_EACK_MASK			0x3
93 
94 #define MC_TIMING_UPDATE				BIT(0)
95 
96 #define MC_BROADCAST_CHANNEL				~0
97 
tegra_mc_scale_percents(u64 val,unsigned int percents)98 static inline u32 tegra_mc_scale_percents(u64 val, unsigned int percents)
99 {
100 	val = val * percents;
101 	do_div(val, 100);
102 
103 	return min_t(u64, val, U32_MAX);
104 }
105 
106 static inline struct tegra_mc *
icc_provider_to_tegra_mc(struct icc_provider * provider)107 icc_provider_to_tegra_mc(struct icc_provider *provider)
108 {
109 	return container_of(provider, struct tegra_mc, provider);
110 }
111 
mc_ch_readl(const struct tegra_mc * mc,int ch,unsigned long offset)112 static inline u32 mc_ch_readl(const struct tegra_mc *mc, int ch,
113 			      unsigned long offset)
114 {
115 	if (!mc->bcast_ch_regs)
116 		return 0;
117 
118 	if (ch == MC_BROADCAST_CHANNEL)
119 		return readl_relaxed(mc->bcast_ch_regs + offset);
120 
121 	return readl_relaxed(mc->ch_regs[ch] + offset);
122 }
123 
mc_ch_writel(const struct tegra_mc * mc,int ch,u32 value,unsigned long offset)124 static inline void mc_ch_writel(const struct tegra_mc *mc, int ch,
125 				u32 value, unsigned long offset)
126 {
127 	if (!mc->bcast_ch_regs)
128 		return;
129 
130 	if (ch == MC_BROADCAST_CHANNEL)
131 		writel_relaxed(value, mc->bcast_ch_regs + offset);
132 	else
133 		writel_relaxed(value, mc->ch_regs[ch] + offset);
134 }
135 
mc_readl(const struct tegra_mc * mc,unsigned long offset)136 static inline u32 mc_readl(const struct tegra_mc *mc, unsigned long offset)
137 {
138 	return readl_relaxed(mc->regs + offset);
139 }
140 
mc_writel(const struct tegra_mc * mc,u32 value,unsigned long offset)141 static inline void mc_writel(const struct tegra_mc *mc, u32 value,
142 			     unsigned long offset)
143 {
144 	writel_relaxed(value, mc->regs + offset);
145 }
146 
147 extern const struct tegra_mc_reset_ops tegra_mc_reset_ops_common;
148 
149 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
150 extern const struct tegra_mc_soc tegra20_mc_soc;
151 #endif
152 
153 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
154 extern const struct tegra_mc_soc tegra30_mc_soc;
155 #endif
156 
157 #ifdef CONFIG_ARCH_TEGRA_114_SOC
158 extern const struct tegra_mc_soc tegra114_mc_soc;
159 #endif
160 
161 #ifdef CONFIG_ARCH_TEGRA_124_SOC
162 extern const struct tegra_mc_soc tegra124_mc_soc;
163 #endif
164 
165 #ifdef CONFIG_ARCH_TEGRA_132_SOC
166 extern const struct tegra_mc_soc tegra132_mc_soc;
167 #endif
168 
169 #ifdef CONFIG_ARCH_TEGRA_210_SOC
170 extern const struct tegra_mc_soc tegra210_mc_soc;
171 #endif
172 
173 #ifdef CONFIG_ARCH_TEGRA_186_SOC
174 extern const struct tegra_mc_soc tegra186_mc_soc;
175 #endif
176 
177 #ifdef CONFIG_ARCH_TEGRA_194_SOC
178 extern const struct tegra_mc_soc tegra194_mc_soc;
179 #endif
180 
181 #ifdef CONFIG_ARCH_TEGRA_234_SOC
182 extern const struct tegra_mc_soc tegra234_mc_soc;
183 #endif
184 
185 #if defined(CONFIG_ARCH_TEGRA_3x_SOC) || \
186     defined(CONFIG_ARCH_TEGRA_114_SOC) || \
187     defined(CONFIG_ARCH_TEGRA_124_SOC) || \
188     defined(CONFIG_ARCH_TEGRA_132_SOC) || \
189     defined(CONFIG_ARCH_TEGRA_210_SOC)
190 int tegra30_mc_probe(struct tegra_mc *mc);
191 extern const struct tegra_mc_ops tegra30_mc_ops;
192 #endif
193 
194 #if defined(CONFIG_ARCH_TEGRA_186_SOC) || \
195     defined(CONFIG_ARCH_TEGRA_194_SOC) || \
196     defined(CONFIG_ARCH_TEGRA_234_SOC)
197 extern const struct tegra_mc_ops tegra186_mc_ops;
198 #endif
199 
200 irqreturn_t tegra30_mc_handle_irq(int irq, void *data);
201 extern const char * const tegra_mc_status_names[32];
202 extern const char * const tegra_mc_error_names[8];
203 
204 /*
205  * These IDs are for internal use of Tegra ICC drivers. The ID numbers are
206  * chosen such that they don't conflict with the device-tree ICC node IDs.
207  */
208 #define TEGRA_ICC_MC		1000
209 #define TEGRA_ICC_EMC		1001
210 #define TEGRA_ICC_EMEM		1002
211 
212 #endif /* MEMORY_TEGRA_MC_H */
213