1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2003 Matthew N. Dodd <winter@jurai.net>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 /*
31 * Written using information gleaned from the
32 * NVIDIA nForce/nForce2 AGPGART Linux Kernel Patch.
33 */
34
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/malloc.h>
38 #include <sys/kernel.h>
39 #include <sys/module.h>
40 #include <sys/bus.h>
41 #include <sys/lock.h>
42 #include <sys/mutex.h>
43 #include <sys/proc.h>
44
45 #include <dev/agp/agppriv.h>
46 #include <dev/agp/agpreg.h>
47 #include <dev/pci/pcivar.h>
48 #include <dev/pci/pcireg.h>
49
50 #include <vm/vm.h>
51 #include <vm/vm_object.h>
52 #include <vm/pmap.h>
53
54 #include <machine/bus.h>
55 #include <machine/resource.h>
56 #include <sys/rman.h>
57
58 #define NVIDIA_VENDORID 0x10de
59 #define NVIDIA_DEVICEID_NFORCE 0x01a4
60 #define NVIDIA_DEVICEID_NFORCE2 0x01e0
61
62 struct agp_nvidia_softc {
63 struct agp_softc agp;
64 u_int32_t initial_aperture; /* aperture size at startup */
65 struct agp_gatt * gatt;
66
67 device_t dev; /* AGP Controller */
68 device_t mc1_dev; /* Memory Controller */
69 device_t mc2_dev; /* Memory Controller */
70 device_t bdev; /* Bridge */
71
72 u_int32_t wbc_mask;
73 int num_dirs;
74 int num_active_entries;
75 off_t pg_offset;
76 };
77
78 static const char *agp_nvidia_match(device_t dev);
79 static int agp_nvidia_probe(device_t);
80 static int agp_nvidia_attach(device_t);
81 static int agp_nvidia_detach(device_t);
82 static u_int32_t agp_nvidia_get_aperture(device_t);
83 static int agp_nvidia_set_aperture(device_t, u_int32_t);
84 static int agp_nvidia_bind_page(device_t, vm_offset_t, vm_offset_t);
85 static int agp_nvidia_unbind_page(device_t, vm_offset_t);
86
87 static int nvidia_init_iorr(u_int32_t, u_int32_t);
88
89 static const char *
agp_nvidia_match(device_t dev)90 agp_nvidia_match (device_t dev)
91 {
92 if (pci_get_class(dev) != PCIC_BRIDGE ||
93 pci_get_subclass(dev) != PCIS_BRIDGE_HOST ||
94 pci_get_vendor(dev) != NVIDIA_VENDORID)
95 return (NULL);
96
97 switch (pci_get_device(dev)) {
98 case NVIDIA_DEVICEID_NFORCE:
99 return ("NVIDIA nForce AGP Controller");
100 case NVIDIA_DEVICEID_NFORCE2:
101 return ("NVIDIA nForce2 AGP Controller");
102 }
103 return (NULL);
104 }
105
106 static int
agp_nvidia_probe(device_t dev)107 agp_nvidia_probe (device_t dev)
108 {
109 const char *desc;
110
111 if (resource_disabled("agp", device_get_unit(dev)))
112 return (ENXIO);
113 desc = agp_nvidia_match(dev);
114 if (desc) {
115 device_set_desc(dev, desc);
116 return (BUS_PROBE_DEFAULT);
117 }
118 return (ENXIO);
119 }
120
121 static int
agp_nvidia_attach(device_t dev)122 agp_nvidia_attach (device_t dev)
123 {
124 struct agp_nvidia_softc *sc = device_get_softc(dev);
125 struct agp_gatt *gatt;
126 u_int32_t apbase;
127 u_int32_t aplimit;
128 u_int32_t temp;
129 int size;
130 int i;
131 int error;
132
133 switch (pci_get_device(dev)) {
134 case NVIDIA_DEVICEID_NFORCE:
135 sc->wbc_mask = 0x00010000;
136 break;
137 case NVIDIA_DEVICEID_NFORCE2:
138 sc->wbc_mask = 0x80000000;
139 break;
140 default:
141 device_printf(dev, "Bad chip id\n");
142 return (ENODEV);
143 }
144
145 /* AGP Controller */
146 sc->dev = dev;
147
148 /* Memory Controller 1 */
149 sc->mc1_dev = pci_find_bsf(pci_get_bus(dev), 0, 1);
150 if (sc->mc1_dev == NULL) {
151 device_printf(dev,
152 "Unable to find NVIDIA Memory Controller 1.\n");
153 return (ENODEV);
154 }
155
156 /* Memory Controller 2 */
157 sc->mc2_dev = pci_find_bsf(pci_get_bus(dev), 0, 2);
158 if (sc->mc2_dev == NULL) {
159 device_printf(dev,
160 "Unable to find NVIDIA Memory Controller 2.\n");
161 return (ENODEV);
162 }
163
164 /* AGP Host to PCI Bridge */
165 sc->bdev = pci_find_bsf(pci_get_bus(dev), 30, 0);
166 if (sc->bdev == NULL) {
167 device_printf(dev,
168 "Unable to find NVIDIA AGP Host to PCI Bridge.\n");
169 return (ENODEV);
170 }
171
172 error = agp_generic_attach(dev);
173 if (error)
174 return (error);
175
176 sc->initial_aperture = AGP_GET_APERTURE(dev);
177
178 for (;;) {
179 gatt = agp_alloc_gatt(dev);
180 if (gatt)
181 break;
182 /*
183 * Probably contigmalloc failure. Try reducing the
184 * aperture so that the gatt size reduces.
185 */
186 if (AGP_SET_APERTURE(dev, AGP_GET_APERTURE(dev) / 2))
187 goto fail;
188 }
189 sc->gatt = gatt;
190
191 apbase = rman_get_start(sc->agp.as_aperture);
192 aplimit = apbase + AGP_GET_APERTURE(dev) - 1;
193 pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_APBASE, apbase, 4);
194 pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_APLIMIT, aplimit, 4);
195 pci_write_config(sc->bdev, AGP_NVIDIA_3_APBASE, apbase, 4);
196 pci_write_config(sc->bdev, AGP_NVIDIA_3_APLIMIT, aplimit, 4);
197
198 error = nvidia_init_iorr(apbase, AGP_GET_APERTURE(dev));
199 if (error) {
200 device_printf(dev, "Failed to setup IORRs\n");
201 goto fail;
202 }
203
204 /* directory size is 64k */
205 size = AGP_GET_APERTURE(dev) / 1024 / 1024;
206 sc->num_dirs = size / 64;
207 sc->num_active_entries = (size == 32) ? 16384 : ((size * 1024) / 4);
208 sc->pg_offset = 0;
209 if (sc->num_dirs == 0) {
210 sc->num_dirs = 1;
211 sc->num_active_entries /= (64 / size);
212 sc->pg_offset = rounddown2(apbase & (64 * 1024 * 1024 - 1),
213 AGP_GET_APERTURE(dev)) / PAGE_SIZE;
214 }
215
216 /* (G)ATT Base Address */
217 for (i = 0; i < 8; i++) {
218 pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_ATTBASE(i),
219 (sc->gatt->ag_physical +
220 (i % sc->num_dirs) * 64 * 1024) | 1, 4);
221 }
222
223 /* GTLB Control */
224 temp = pci_read_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, 4);
225 pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, temp | 0x11, 4);
226
227 /* GART Control */
228 temp = pci_read_config(sc->dev, AGP_NVIDIA_0_APSIZE, 4);
229 pci_write_config(sc->dev, AGP_NVIDIA_0_APSIZE, temp | 0x100, 4);
230
231 return (0);
232 fail:
233 agp_generic_detach(dev);
234 return (ENOMEM);
235 }
236
237 static int
agp_nvidia_detach(device_t dev)238 agp_nvidia_detach (device_t dev)
239 {
240 struct agp_nvidia_softc *sc = device_get_softc(dev);
241 u_int32_t temp;
242
243 agp_free_cdev(dev);
244
245 /* GART Control */
246 temp = pci_read_config(sc->dev, AGP_NVIDIA_0_APSIZE, 4);
247 pci_write_config(sc->dev, AGP_NVIDIA_0_APSIZE, temp & ~(0x100), 4);
248
249 /* GTLB Control */
250 temp = pci_read_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, 4);
251 pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, temp & ~(0x11), 4);
252
253 /* Put the aperture back the way it started. */
254 AGP_SET_APERTURE(dev, sc->initial_aperture);
255
256 /* restore iorr for previous aperture size */
257 nvidia_init_iorr(rman_get_start(sc->agp.as_aperture),
258 sc->initial_aperture);
259
260 agp_free_gatt(sc->gatt);
261 agp_free_res(dev);
262
263 return (0);
264 }
265
266 static u_int32_t
agp_nvidia_get_aperture(device_t dev)267 agp_nvidia_get_aperture(device_t dev)
268 {
269 switch (pci_read_config(dev, AGP_NVIDIA_0_APSIZE, 1) & 0x0f) {
270 case 0: return (512 * 1024 * 1024);
271 case 8: return (256 * 1024 * 1024);
272 case 12: return (128 * 1024 * 1024);
273 case 14: return (64 * 1024 * 1024);
274 case 15: return (32 * 1024 * 1024);
275 default:
276 device_printf(dev, "Invalid aperture setting 0x%x\n",
277 pci_read_config(dev, AGP_NVIDIA_0_APSIZE, 1));
278 return 0;
279 }
280 }
281
282 static int
agp_nvidia_set_aperture(device_t dev,u_int32_t aperture)283 agp_nvidia_set_aperture(device_t dev, u_int32_t aperture)
284 {
285 u_int8_t val;
286 u_int8_t key;
287
288 switch (aperture) {
289 case (512 * 1024 * 1024): key = 0; break;
290 case (256 * 1024 * 1024): key = 8; break;
291 case (128 * 1024 * 1024): key = 12; break;
292 case (64 * 1024 * 1024): key = 14; break;
293 case (32 * 1024 * 1024): key = 15; break;
294 default:
295 device_printf(dev, "Invalid aperture size (%dMb)\n",
296 aperture / 1024 / 1024);
297 return (EINVAL);
298 }
299 val = pci_read_config(dev, AGP_NVIDIA_0_APSIZE, 1);
300 pci_write_config(dev, AGP_NVIDIA_0_APSIZE, ((val & ~0x0f) | key), 1);
301
302 return (0);
303 }
304
305 static int
agp_nvidia_bind_page(device_t dev,vm_offset_t offset,vm_offset_t physical)306 agp_nvidia_bind_page(device_t dev, vm_offset_t offset, vm_offset_t physical)
307 {
308 struct agp_nvidia_softc *sc = device_get_softc(dev);
309 u_int32_t index;
310
311 if (offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
312 return (EINVAL);
313
314 index = (sc->pg_offset + offset) >> AGP_PAGE_SHIFT;
315 sc->gatt->ag_virtual[index] = physical | 1;
316
317 return (0);
318 }
319
320 static int
agp_nvidia_unbind_page(device_t dev,vm_offset_t offset)321 agp_nvidia_unbind_page(device_t dev, vm_offset_t offset)
322 {
323 struct agp_nvidia_softc *sc = device_get_softc(dev);
324 u_int32_t index;
325
326 if (offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
327 return (EINVAL);
328
329 index = (sc->pg_offset + offset) >> AGP_PAGE_SHIFT;
330 sc->gatt->ag_virtual[index] = 0;
331
332 return (0);
333 }
334
335 static void
agp_nvidia_flush_tlb(device_t dev)336 agp_nvidia_flush_tlb (device_t dev)
337 {
338 struct agp_nvidia_softc *sc;
339 u_int32_t wbc_reg;
340 volatile u_int32_t *ag_virtual;
341 int i, pages;
342
343 sc = (struct agp_nvidia_softc *)device_get_softc(dev);
344
345 if (sc->wbc_mask) {
346 wbc_reg = pci_read_config(sc->mc1_dev, AGP_NVIDIA_1_WBC, 4);
347 wbc_reg |= sc->wbc_mask;
348 pci_write_config(sc->mc1_dev, AGP_NVIDIA_1_WBC, wbc_reg, 4);
349
350 /* Wait no more than 3 seconds. */
351 for (i = 0; i < 3000; i++) {
352 wbc_reg = pci_read_config(sc->mc1_dev,
353 AGP_NVIDIA_1_WBC, 4);
354 if ((sc->wbc_mask & wbc_reg) == 0)
355 break;
356 else
357 DELAY(1000);
358 }
359 if (i == 3000)
360 device_printf(dev,
361 "TLB flush took more than 3 seconds.\n");
362 }
363
364 ag_virtual = (volatile u_int32_t *)sc->gatt->ag_virtual;
365
366 /* Flush TLB entries. */
367 pages = sc->gatt->ag_entries * sizeof(u_int32_t) / PAGE_SIZE;
368 for(i = 0; i < pages; i++)
369 (void)ag_virtual[i * PAGE_SIZE / sizeof(u_int32_t)];
370 for(i = 0; i < pages; i++)
371 (void)ag_virtual[i * PAGE_SIZE / sizeof(u_int32_t)];
372 }
373
374 #define SYSCFG 0xC0010010
375 #define IORR_BASE0 0xC0010016
376 #define IORR_MASK0 0xC0010017
377 #define AMD_K7_NUM_IORR 2
378
379 static int
nvidia_init_iorr(u_int32_t addr,u_int32_t size)380 nvidia_init_iorr(u_int32_t addr, u_int32_t size)
381 {
382 quad_t base, mask, sys;
383 u_int32_t iorr_addr, free_iorr_addr;
384
385 /* Find the iorr that is already used for the addr */
386 /* If not found, determine the uppermost available iorr */
387 free_iorr_addr = AMD_K7_NUM_IORR;
388 for(iorr_addr = 0; iorr_addr < AMD_K7_NUM_IORR; iorr_addr++) {
389 base = rdmsr(IORR_BASE0 + 2 * iorr_addr);
390 mask = rdmsr(IORR_MASK0 + 2 * iorr_addr);
391
392 if ((base & 0xfffff000ULL) == (addr & 0xfffff000))
393 break;
394
395 if ((mask & 0x00000800ULL) == 0)
396 free_iorr_addr = iorr_addr;
397 }
398
399 if (iorr_addr >= AMD_K7_NUM_IORR) {
400 iorr_addr = free_iorr_addr;
401 if (iorr_addr >= AMD_K7_NUM_IORR)
402 return (EINVAL);
403 }
404
405 base = (addr & ~0xfff) | 0x18;
406 mask = (0xfULL << 32) | rounddown2(0xfffff000, size) | 0x800;
407 wrmsr(IORR_BASE0 + 2 * iorr_addr, base);
408 wrmsr(IORR_MASK0 + 2 * iorr_addr, mask);
409
410 sys = rdmsr(SYSCFG);
411 sys |= 0x00100000ULL;
412 wrmsr(SYSCFG, sys);
413
414 return (0);
415 }
416
417 static device_method_t agp_nvidia_methods[] = {
418 /* Device interface */
419 DEVMETHOD(device_probe, agp_nvidia_probe),
420 DEVMETHOD(device_attach, agp_nvidia_attach),
421 DEVMETHOD(device_detach, agp_nvidia_detach),
422 DEVMETHOD(device_shutdown, bus_generic_shutdown),
423 DEVMETHOD(device_suspend, bus_generic_suspend),
424 DEVMETHOD(device_resume, bus_generic_resume),
425
426 /* AGP interface */
427 DEVMETHOD(agp_get_aperture, agp_nvidia_get_aperture),
428 DEVMETHOD(agp_set_aperture, agp_nvidia_set_aperture),
429 DEVMETHOD(agp_bind_page, agp_nvidia_bind_page),
430 DEVMETHOD(agp_unbind_page, agp_nvidia_unbind_page),
431 DEVMETHOD(agp_flush_tlb, agp_nvidia_flush_tlb),
432
433 DEVMETHOD(agp_enable, agp_generic_enable),
434 DEVMETHOD(agp_alloc_memory, agp_generic_alloc_memory),
435 DEVMETHOD(agp_free_memory, agp_generic_free_memory),
436 DEVMETHOD(agp_bind_memory, agp_generic_bind_memory),
437 DEVMETHOD(agp_unbind_memory, agp_generic_unbind_memory),
438 { 0, 0 }
439 };
440
441 static driver_t agp_nvidia_driver = {
442 "agp",
443 agp_nvidia_methods,
444 sizeof(struct agp_nvidia_softc),
445 };
446
447 DRIVER_MODULE(agp_nvidia, hostb, agp_nvidia_driver, 0, 0);
448 MODULE_DEPEND(agp_nvidia, agp, 1, 1, 1);
449 MODULE_DEPEND(agp_nvidia, pci, 1, 1, 1);
450