1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * NVIDIA Tegra xHCI host controller driver
4 *
5 * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
6 * Copyright (C) 2014 Google, Inc.
7 */
8
9 #include <linux/clk.h>
10 #include <linux/delay.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/firmware.h>
13 #include <linux/interrupt.h>
14 #include <linux/iopoll.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/of.h>
18 #include <linux/of_irq.h>
19 #include <linux/phy/phy.h>
20 #include <linux/phy/tegra/xusb.h>
21 #include <linux/platform_device.h>
22 #include <linux/usb/ch9.h>
23 #include <linux/pm.h>
24 #include <linux/pm_domain.h>
25 #include <linux/pm_runtime.h>
26 #include <linux/regulator/consumer.h>
27 #include <linux/reset.h>
28 #include <linux/slab.h>
29 #include <linux/string_choices.h>
30 #include <linux/usb/otg.h>
31 #include <linux/usb/phy.h>
32 #include <linux/usb/role.h>
33 #include <soc/tegra/pmc.h>
34
35 #include "xhci.h"
36
37 #define TEGRA_XHCI_SS_HIGH_SPEED 120000000
38 #define TEGRA_XHCI_SS_LOW_SPEED 12000000
39
40 /* FPCI CFG registers */
41 #define XUSB_CFG_1 0x004
42 #define XUSB_IO_SPACE_EN BIT(0)
43 #define XUSB_MEM_SPACE_EN BIT(1)
44 #define XUSB_BUS_MASTER_EN BIT(2)
45 #define XUSB_CFG_4 0x010
46 #define XUSB_BASE_ADDR_SHIFT 15
47 #define XUSB_BASE_ADDR_MASK 0x1ffff
48 #define XUSB_CFG_7 0x01c
49 #define XUSB_BASE2_ADDR_SHIFT 16
50 #define XUSB_BASE2_ADDR_MASK 0xffff
51 #define XUSB_CFG_16 0x040
52 #define XUSB_CFG_24 0x060
53 #define XUSB_CFG_AXI_CFG 0x0f8
54 #define XUSB_CFG_ARU_C11_CSBRANGE 0x41c
55 #define XUSB_CFG_ARU_CONTEXT 0x43c
56 #define XUSB_CFG_ARU_CONTEXT_HS_PLS 0x478
57 #define XUSB_CFG_ARU_CONTEXT_FS_PLS 0x47c
58 #define XUSB_CFG_ARU_CONTEXT_HSFS_SPEED 0x480
59 #define XUSB_CFG_ARU_CONTEXT_HSFS_PP 0x484
60 #define XUSB_CFG_CSB_BASE_ADDR 0x800
61
62 /* FPCI mailbox registers */
63 /* XUSB_CFG_ARU_MBOX_CMD */
64 #define MBOX_DEST_FALC BIT(27)
65 #define MBOX_DEST_PME BIT(28)
66 #define MBOX_DEST_SMI BIT(29)
67 #define MBOX_DEST_XHCI BIT(30)
68 #define MBOX_INT_EN BIT(31)
69 /* XUSB_CFG_ARU_MBOX_DATA_IN and XUSB_CFG_ARU_MBOX_DATA_OUT */
70 #define CMD_DATA_SHIFT 0
71 #define CMD_DATA_MASK 0xffffff
72 #define CMD_TYPE_SHIFT 24
73 #define CMD_TYPE_MASK 0xff
74 /* XUSB_CFG_ARU_MBOX_OWNER */
75 #define MBOX_OWNER_NONE 0
76 #define MBOX_OWNER_FW 1
77 #define MBOX_OWNER_SW 2
78 #define XUSB_CFG_ARU_SMI_INTR 0x428
79 #define MBOX_SMI_INTR_FW_HANG BIT(1)
80 #define MBOX_SMI_INTR_EN BIT(3)
81
82 /* BAR2 registers */
83 #define XUSB_BAR2_ARU_MBOX_CMD 0x004
84 #define XUSB_BAR2_ARU_MBOX_DATA_IN 0x008
85 #define XUSB_BAR2_ARU_MBOX_DATA_OUT 0x00c
86 #define XUSB_BAR2_ARU_MBOX_OWNER 0x010
87 #define XUSB_BAR2_ARU_SMI_INTR 0x014
88 #define XUSB_BAR2_ARU_SMI_ARU_FW_SCRATCH_DATA0 0x01c
89 #define XUSB_BAR2_ARU_IFRDMA_CFG0 0x0e0
90 #define XUSB_BAR2_ARU_IFRDMA_CFG1 0x0e4
91 #define XUSB_BAR2_ARU_IFRDMA_STREAMID_FIELD 0x0e8
92 #define XUSB_BAR2_ARU_C11_CSBRANGE 0x9c
93 #define XUSB_BAR2_ARU_FW_SCRATCH 0x1000
94 #define XUSB_BAR2_CSB_BASE_ADDR 0x2000
95
96 /* IPFS registers */
97 #define IPFS_XUSB_HOST_MSI_BAR_SZ_0 0x0c0
98 #define IPFS_XUSB_HOST_MSI_AXI_BAR_ST_0 0x0c4
99 #define IPFS_XUSB_HOST_MSI_FPCI_BAR_ST_0 0x0c8
100 #define IPFS_XUSB_HOST_MSI_VEC0_0 0x100
101 #define IPFS_XUSB_HOST_MSI_EN_VEC0_0 0x140
102 #define IPFS_XUSB_HOST_CONFIGURATION_0 0x180
103 #define IPFS_EN_FPCI BIT(0)
104 #define IPFS_XUSB_HOST_FPCI_ERROR_MASKS_0 0x184
105 #define IPFS_XUSB_HOST_INTR_MASK_0 0x188
106 #define IPFS_IP_INT_MASK BIT(16)
107 #define IPFS_XUSB_HOST_INTR_ENABLE_0 0x198
108 #define IPFS_XUSB_HOST_UFPCI_CONFIG_0 0x19c
109 #define IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0 0x1bc
110 #define IPFS_XUSB_HOST_MCCIF_FIFOCTRL_0 0x1dc
111
112 #define CSB_PAGE_SELECT_MASK 0x7fffff
113 #define CSB_PAGE_SELECT_SHIFT 9
114 #define CSB_PAGE_OFFSET_MASK 0x1ff
115 #define CSB_PAGE_SELECT(addr) ((addr) >> (CSB_PAGE_SELECT_SHIFT) & \
116 CSB_PAGE_SELECT_MASK)
117 #define CSB_PAGE_OFFSET(addr) ((addr) & CSB_PAGE_OFFSET_MASK)
118
119 /* Falcon CSB registers */
120 #define XUSB_FALC_CPUCTL 0x100
121 #define CPUCTL_STARTCPU BIT(1)
122 #define CPUCTL_STATE_HALTED BIT(4)
123 #define CPUCTL_STATE_STOPPED BIT(5)
124 #define XUSB_FALC_BOOTVEC 0x104
125 #define XUSB_FALC_DMACTL 0x10c
126 #define XUSB_FALC_IMFILLRNG1 0x154
127 #define IMFILLRNG1_TAG_MASK 0xffff
128 #define IMFILLRNG1_TAG_LO_SHIFT 0
129 #define IMFILLRNG1_TAG_HI_SHIFT 16
130 #define XUSB_FALC_IMFILLCTL 0x158
131
132 /* CSB ARU registers */
133 #define XUSB_CSB_ARU_SCRATCH0 0x100100
134
135 /* MP CSB registers */
136 #define XUSB_CSB_MP_ILOAD_ATTR 0x101a00
137 #define XUSB_CSB_MP_ILOAD_BASE_LO 0x101a04
138 #define XUSB_CSB_MP_ILOAD_BASE_HI 0x101a08
139 #define XUSB_CSB_MP_L2IMEMOP_SIZE 0x101a10
140 #define L2IMEMOP_SIZE_SRC_OFFSET_SHIFT 8
141 #define L2IMEMOP_SIZE_SRC_OFFSET_MASK 0x3ff
142 #define L2IMEMOP_SIZE_SRC_COUNT_SHIFT 24
143 #define L2IMEMOP_SIZE_SRC_COUNT_MASK 0xff
144 #define XUSB_CSB_MP_L2IMEMOP_TRIG 0x101a14
145 #define L2IMEMOP_ACTION_SHIFT 24
146 #define L2IMEMOP_INVALIDATE_ALL (0x40 << L2IMEMOP_ACTION_SHIFT)
147 #define L2IMEMOP_LOAD_LOCKED_RESULT (0x11 << L2IMEMOP_ACTION_SHIFT)
148 #define XUSB_CSB_MEMPOOL_L2IMEMOP_RESULT 0x101a18
149 #define L2IMEMOP_RESULT_VLD BIT(31)
150 #define XUSB_CSB_MP_APMAP 0x10181c
151 #define APMAP_BOOTPATH BIT(31)
152
153 #define IMEM_BLOCK_SIZE 256
154
155 #define FW_IOCTL_TYPE_SHIFT 24
156 #define FW_IOCTL_CFGTBL_READ 17
157
158 struct tegra_xusb_fw_header {
159 __le32 boot_loadaddr_in_imem;
160 __le32 boot_codedfi_offset;
161 __le32 boot_codetag;
162 __le32 boot_codesize;
163 __le32 phys_memaddr;
164 __le16 reqphys_memsize;
165 __le16 alloc_phys_memsize;
166 __le32 rodata_img_offset;
167 __le32 rodata_section_start;
168 __le32 rodata_section_end;
169 __le32 main_fnaddr;
170 __le32 fwimg_cksum;
171 __le32 fwimg_created_time;
172 __le32 imem_resident_start;
173 __le32 imem_resident_end;
174 __le32 idirect_start;
175 __le32 idirect_end;
176 __le32 l2_imem_start;
177 __le32 l2_imem_end;
178 __le32 version_id;
179 u8 init_ddirect;
180 u8 reserved[3];
181 __le32 phys_addr_log_buffer;
182 __le32 total_log_entries;
183 __le32 dequeue_ptr;
184 __le32 dummy_var[2];
185 __le32 fwimg_len;
186 u8 magic[8];
187 __le32 ss_low_power_entry_timeout;
188 u8 num_hsic_port;
189 u8 padding[139]; /* Pad to 256 bytes */
190 };
191
192 struct tegra_xusb_phy_type {
193 const char *name;
194 unsigned int num;
195 };
196
197 struct tegra_xusb_mbox_regs {
198 u16 cmd;
199 u16 data_in;
200 u16 data_out;
201 u16 owner;
202 u16 smi_intr;
203 };
204
205 struct tegra_xusb_context_soc {
206 struct {
207 const unsigned int *offsets;
208 unsigned int num_offsets;
209 } ipfs;
210
211 struct {
212 const unsigned int *offsets;
213 unsigned int num_offsets;
214 } fpci;
215 };
216
217 struct tegra_xusb;
218 struct tegra_xusb_soc_ops {
219 u32 (*mbox_reg_readl)(struct tegra_xusb *tegra, unsigned int offset);
220 void (*mbox_reg_writel)(struct tegra_xusb *tegra, u32 value, unsigned int offset);
221 u32 (*csb_reg_readl)(struct tegra_xusb *tegra, unsigned int offset);
222 void (*csb_reg_writel)(struct tegra_xusb *tegra, u32 value, unsigned int offset);
223 };
224
225 struct tegra_xusb_soc {
226 const char *firmware;
227 const char * const *supply_names;
228 unsigned int num_supplies;
229 const struct tegra_xusb_phy_type *phy_types;
230 unsigned int num_types;
231 const struct tegra_xusb_context_soc *context;
232
233 struct {
234 struct {
235 unsigned int offset;
236 unsigned int count;
237 } usb2, ulpi, hsic, usb3;
238 } ports;
239
240 struct tegra_xusb_mbox_regs mbox;
241 const struct tegra_xusb_soc_ops *ops;
242
243 bool scale_ss_clock;
244 bool has_ipfs;
245 bool lpm_support;
246 bool otg_reset_sspi;
247
248 bool has_bar2;
249 };
250
251 struct tegra_xusb_context {
252 u32 *ipfs;
253 u32 *fpci;
254 };
255
256 struct tegra_xusb {
257 struct device *dev;
258 void __iomem *regs;
259 struct usb_hcd *hcd;
260
261 struct mutex lock;
262
263 int xhci_irq;
264 int mbox_irq;
265 int padctl_irq;
266
267 void __iomem *ipfs_base;
268 void __iomem *fpci_base;
269 void __iomem *bar2_base;
270 struct resource *bar2;
271
272 const struct tegra_xusb_soc *soc;
273
274 struct regulator_bulk_data *supplies;
275
276 struct tegra_xusb_padctl *padctl;
277
278 struct clk *host_clk;
279 struct clk *falcon_clk;
280 struct clk *ss_clk;
281 struct clk *ss_src_clk;
282 struct clk *hs_src_clk;
283 struct clk *fs_src_clk;
284 struct clk *pll_u_480m;
285 struct clk *clk_m;
286 struct clk *pll_e;
287
288 struct reset_control *host_rst;
289 struct reset_control *ss_rst;
290
291 struct device *genpd_dev_host;
292 struct device *genpd_dev_ss;
293 bool use_genpd;
294
295 struct phy **phys;
296 unsigned int num_phys;
297
298 struct usb_phy **usbphy;
299 unsigned int num_usb_phys;
300 int otg_usb2_port;
301 int otg_usb3_port;
302 bool host_mode;
303 struct notifier_block id_nb;
304 struct work_struct id_work;
305
306 /* Firmware loading related */
307 struct {
308 size_t size;
309 void *virt;
310 dma_addr_t phys;
311 } fw;
312
313 bool suspended;
314 struct tegra_xusb_context context;
315 u8 lp0_utmi_pad_mask;
316 };
317
318 static struct hc_driver __read_mostly tegra_xhci_hc_driver;
319
fpci_readl(struct tegra_xusb * tegra,unsigned int offset)320 static inline u32 fpci_readl(struct tegra_xusb *tegra, unsigned int offset)
321 {
322 return readl(tegra->fpci_base + offset);
323 }
324
fpci_writel(struct tegra_xusb * tegra,u32 value,unsigned int offset)325 static inline void fpci_writel(struct tegra_xusb *tegra, u32 value,
326 unsigned int offset)
327 {
328 writel(value, tegra->fpci_base + offset);
329 }
330
ipfs_readl(struct tegra_xusb * tegra,unsigned int offset)331 static inline u32 ipfs_readl(struct tegra_xusb *tegra, unsigned int offset)
332 {
333 return readl(tegra->ipfs_base + offset);
334 }
335
ipfs_writel(struct tegra_xusb * tegra,u32 value,unsigned int offset)336 static inline void ipfs_writel(struct tegra_xusb *tegra, u32 value,
337 unsigned int offset)
338 {
339 writel(value, tegra->ipfs_base + offset);
340 }
341
bar2_readl(struct tegra_xusb * tegra,unsigned int offset)342 static inline u32 bar2_readl(struct tegra_xusb *tegra, unsigned int offset)
343 {
344 return readl(tegra->bar2_base + offset);
345 }
346
bar2_writel(struct tegra_xusb * tegra,u32 value,unsigned int offset)347 static inline void bar2_writel(struct tegra_xusb *tegra, u32 value,
348 unsigned int offset)
349 {
350 writel(value, tegra->bar2_base + offset);
351 }
352
csb_readl(struct tegra_xusb * tegra,unsigned int offset)353 static u32 csb_readl(struct tegra_xusb *tegra, unsigned int offset)
354 {
355 const struct tegra_xusb_soc_ops *ops = tegra->soc->ops;
356
357 return ops->csb_reg_readl(tegra, offset);
358 }
359
csb_writel(struct tegra_xusb * tegra,u32 value,unsigned int offset)360 static void csb_writel(struct tegra_xusb *tegra, u32 value,
361 unsigned int offset)
362 {
363 const struct tegra_xusb_soc_ops *ops = tegra->soc->ops;
364
365 ops->csb_reg_writel(tegra, value, offset);
366 }
367
fpci_csb_readl(struct tegra_xusb * tegra,unsigned int offset)368 static u32 fpci_csb_readl(struct tegra_xusb *tegra, unsigned int offset)
369 {
370 u32 page = CSB_PAGE_SELECT(offset);
371 u32 ofs = CSB_PAGE_OFFSET(offset);
372
373 fpci_writel(tegra, page, XUSB_CFG_ARU_C11_CSBRANGE);
374
375 return fpci_readl(tegra, XUSB_CFG_CSB_BASE_ADDR + ofs);
376 }
377
fpci_csb_writel(struct tegra_xusb * tegra,u32 value,unsigned int offset)378 static void fpci_csb_writel(struct tegra_xusb *tegra, u32 value,
379 unsigned int offset)
380 {
381 u32 page = CSB_PAGE_SELECT(offset);
382 u32 ofs = CSB_PAGE_OFFSET(offset);
383
384 fpci_writel(tegra, page, XUSB_CFG_ARU_C11_CSBRANGE);
385 fpci_writel(tegra, value, XUSB_CFG_CSB_BASE_ADDR + ofs);
386 }
387
bar2_csb_readl(struct tegra_xusb * tegra,unsigned int offset)388 static u32 bar2_csb_readl(struct tegra_xusb *tegra, unsigned int offset)
389 {
390 u32 page = CSB_PAGE_SELECT(offset);
391 u32 ofs = CSB_PAGE_OFFSET(offset);
392
393 bar2_writel(tegra, page, XUSB_BAR2_ARU_C11_CSBRANGE);
394
395 return bar2_readl(tegra, XUSB_BAR2_CSB_BASE_ADDR + ofs);
396 }
397
bar2_csb_writel(struct tegra_xusb * tegra,u32 value,unsigned int offset)398 static void bar2_csb_writel(struct tegra_xusb *tegra, u32 value,
399 unsigned int offset)
400 {
401 u32 page = CSB_PAGE_SELECT(offset);
402 u32 ofs = CSB_PAGE_OFFSET(offset);
403
404 bar2_writel(tegra, page, XUSB_BAR2_ARU_C11_CSBRANGE);
405 bar2_writel(tegra, value, XUSB_BAR2_CSB_BASE_ADDR + ofs);
406 }
407
tegra_xusb_set_ss_clk(struct tegra_xusb * tegra,unsigned long rate)408 static int tegra_xusb_set_ss_clk(struct tegra_xusb *tegra,
409 unsigned long rate)
410 {
411 unsigned long new_parent_rate, old_parent_rate;
412 struct clk *clk = tegra->ss_src_clk;
413 unsigned int div;
414 int err;
415
416 if (clk_get_rate(clk) == rate)
417 return 0;
418
419 switch (rate) {
420 case TEGRA_XHCI_SS_HIGH_SPEED:
421 /*
422 * Reparent to PLLU_480M. Set divider first to avoid
423 * overclocking.
424 */
425 old_parent_rate = clk_get_rate(clk_get_parent(clk));
426 new_parent_rate = clk_get_rate(tegra->pll_u_480m);
427 div = new_parent_rate / rate;
428
429 err = clk_set_rate(clk, old_parent_rate / div);
430 if (err)
431 return err;
432
433 err = clk_set_parent(clk, tegra->pll_u_480m);
434 if (err)
435 return err;
436
437 /*
438 * The rate should already be correct, but set it again just
439 * to be sure.
440 */
441 err = clk_set_rate(clk, rate);
442 if (err)
443 return err;
444
445 break;
446
447 case TEGRA_XHCI_SS_LOW_SPEED:
448 /* Reparent to CLK_M */
449 err = clk_set_parent(clk, tegra->clk_m);
450 if (err)
451 return err;
452
453 err = clk_set_rate(clk, rate);
454 if (err)
455 return err;
456
457 break;
458
459 default:
460 dev_err(tegra->dev, "Invalid SS rate: %lu Hz\n", rate);
461 return -EINVAL;
462 }
463
464 if (clk_get_rate(clk) != rate) {
465 dev_err(tegra->dev, "SS clock doesn't match requested rate\n");
466 return -EINVAL;
467 }
468
469 return 0;
470 }
471
extract_field(u32 value,unsigned int start,unsigned int count)472 static unsigned long extract_field(u32 value, unsigned int start,
473 unsigned int count)
474 {
475 return (value >> start) & ((1 << count) - 1);
476 }
477
478 /* Command requests from the firmware */
479 enum tegra_xusb_mbox_cmd {
480 MBOX_CMD_MSG_ENABLED = 1,
481 MBOX_CMD_INC_FALC_CLOCK,
482 MBOX_CMD_DEC_FALC_CLOCK,
483 MBOX_CMD_INC_SSPI_CLOCK,
484 MBOX_CMD_DEC_SSPI_CLOCK,
485 MBOX_CMD_SET_BW, /* no ACK/NAK required */
486 MBOX_CMD_SET_SS_PWR_GATING,
487 MBOX_CMD_SET_SS_PWR_UNGATING,
488 MBOX_CMD_SAVE_DFE_CTLE_CTX,
489 MBOX_CMD_AIRPLANE_MODE_ENABLED, /* unused */
490 MBOX_CMD_AIRPLANE_MODE_DISABLED, /* unused */
491 MBOX_CMD_START_HSIC_IDLE,
492 MBOX_CMD_STOP_HSIC_IDLE,
493 MBOX_CMD_DBC_WAKE_STACK, /* unused */
494 MBOX_CMD_HSIC_PRETEND_CONNECT,
495 MBOX_CMD_RESET_SSPI,
496 MBOX_CMD_DISABLE_SS_LFPS_DETECTION,
497 MBOX_CMD_ENABLE_SS_LFPS_DETECTION,
498
499 MBOX_CMD_MAX,
500
501 /* Response message to above commands */
502 MBOX_CMD_ACK = 128,
503 MBOX_CMD_NAK
504 };
505
506 struct tegra_xusb_mbox_msg {
507 u32 cmd;
508 u32 data;
509 };
510
tegra_xusb_mbox_pack(const struct tegra_xusb_mbox_msg * msg)511 static inline u32 tegra_xusb_mbox_pack(const struct tegra_xusb_mbox_msg *msg)
512 {
513 return (msg->cmd & CMD_TYPE_MASK) << CMD_TYPE_SHIFT |
514 (msg->data & CMD_DATA_MASK) << CMD_DATA_SHIFT;
515 }
tegra_xusb_mbox_unpack(struct tegra_xusb_mbox_msg * msg,u32 value)516 static inline void tegra_xusb_mbox_unpack(struct tegra_xusb_mbox_msg *msg,
517 u32 value)
518 {
519 msg->cmd = (value >> CMD_TYPE_SHIFT) & CMD_TYPE_MASK;
520 msg->data = (value >> CMD_DATA_SHIFT) & CMD_DATA_MASK;
521 }
522
tegra_xusb_mbox_cmd_requires_ack(enum tegra_xusb_mbox_cmd cmd)523 static bool tegra_xusb_mbox_cmd_requires_ack(enum tegra_xusb_mbox_cmd cmd)
524 {
525 switch (cmd) {
526 case MBOX_CMD_SET_BW:
527 case MBOX_CMD_ACK:
528 case MBOX_CMD_NAK:
529 return false;
530
531 default:
532 return true;
533 }
534 }
535
tegra_xusb_mbox_send(struct tegra_xusb * tegra,const struct tegra_xusb_mbox_msg * msg)536 static int tegra_xusb_mbox_send(struct tegra_xusb *tegra,
537 const struct tegra_xusb_mbox_msg *msg)
538 {
539 const struct tegra_xusb_soc_ops *ops = tegra->soc->ops;
540 bool wait_for_idle = false;
541 u32 value;
542
543 /*
544 * Acquire the mailbox. The firmware still owns the mailbox for
545 * ACK/NAK messages.
546 */
547 if (!(msg->cmd == MBOX_CMD_ACK || msg->cmd == MBOX_CMD_NAK)) {
548 value = ops->mbox_reg_readl(tegra, tegra->soc->mbox.owner);
549 if (value != MBOX_OWNER_NONE) {
550 dev_err(tegra->dev, "mailbox is busy\n");
551 return -EBUSY;
552 }
553
554 ops->mbox_reg_writel(tegra, MBOX_OWNER_SW, tegra->soc->mbox.owner);
555
556 value = ops->mbox_reg_readl(tegra, tegra->soc->mbox.owner);
557 if (value != MBOX_OWNER_SW) {
558 dev_err(tegra->dev, "failed to acquire mailbox\n");
559 return -EBUSY;
560 }
561
562 wait_for_idle = true;
563 }
564
565 value = tegra_xusb_mbox_pack(msg);
566 ops->mbox_reg_writel(tegra, value, tegra->soc->mbox.data_in);
567
568 value = ops->mbox_reg_readl(tegra, tegra->soc->mbox.cmd);
569 value |= MBOX_INT_EN | MBOX_DEST_FALC;
570 ops->mbox_reg_writel(tegra, value, tegra->soc->mbox.cmd);
571
572 if (wait_for_idle) {
573 unsigned long timeout = jiffies + msecs_to_jiffies(250);
574
575 while (time_before(jiffies, timeout)) {
576 value = ops->mbox_reg_readl(tegra, tegra->soc->mbox.owner);
577 if (value == MBOX_OWNER_NONE)
578 break;
579
580 usleep_range(10, 20);
581 }
582
583 if (time_after(jiffies, timeout))
584 value = ops->mbox_reg_readl(tegra, tegra->soc->mbox.owner);
585
586 if (value != MBOX_OWNER_NONE)
587 return -ETIMEDOUT;
588 }
589
590 return 0;
591 }
592
tegra_xusb_mbox_irq(int irq,void * data)593 static irqreturn_t tegra_xusb_mbox_irq(int irq, void *data)
594 {
595 struct tegra_xusb *tegra = data;
596 const struct tegra_xusb_soc_ops *ops = tegra->soc->ops;
597 u32 value;
598
599 /* clear mailbox interrupts */
600 value = ops->mbox_reg_readl(tegra, tegra->soc->mbox.smi_intr);
601 ops->mbox_reg_writel(tegra, value, tegra->soc->mbox.smi_intr);
602
603 if (value & MBOX_SMI_INTR_FW_HANG)
604 dev_err(tegra->dev, "controller firmware hang\n");
605
606 return IRQ_WAKE_THREAD;
607 }
608
tegra_xusb_mbox_handle(struct tegra_xusb * tegra,const struct tegra_xusb_mbox_msg * msg)609 static void tegra_xusb_mbox_handle(struct tegra_xusb *tegra,
610 const struct tegra_xusb_mbox_msg *msg)
611 {
612 struct tegra_xusb_padctl *padctl = tegra->padctl;
613 const struct tegra_xusb_soc *soc = tegra->soc;
614 struct device *dev = tegra->dev;
615 struct tegra_xusb_mbox_msg rsp;
616 unsigned long mask;
617 unsigned int port;
618 bool idle, enable;
619 int err = 0;
620
621 memset(&rsp, 0, sizeof(rsp));
622
623 switch (msg->cmd) {
624 case MBOX_CMD_INC_FALC_CLOCK:
625 case MBOX_CMD_DEC_FALC_CLOCK:
626 rsp.data = clk_get_rate(tegra->falcon_clk) / 1000;
627 if (rsp.data != msg->data)
628 rsp.cmd = MBOX_CMD_NAK;
629 else
630 rsp.cmd = MBOX_CMD_ACK;
631
632 break;
633
634 case MBOX_CMD_INC_SSPI_CLOCK:
635 case MBOX_CMD_DEC_SSPI_CLOCK:
636 if (tegra->soc->scale_ss_clock) {
637 err = tegra_xusb_set_ss_clk(tegra, msg->data * 1000);
638 if (err < 0)
639 rsp.cmd = MBOX_CMD_NAK;
640 else
641 rsp.cmd = MBOX_CMD_ACK;
642
643 rsp.data = clk_get_rate(tegra->ss_src_clk) / 1000;
644 } else {
645 rsp.cmd = MBOX_CMD_ACK;
646 rsp.data = msg->data;
647 }
648
649 break;
650
651 case MBOX_CMD_SET_BW:
652 /*
653 * TODO: Request bandwidth once EMC scaling is supported.
654 * Ignore for now since ACK/NAK is not required for SET_BW
655 * messages.
656 */
657 break;
658
659 case MBOX_CMD_SAVE_DFE_CTLE_CTX:
660 err = tegra_xusb_padctl_usb3_save_context(padctl, msg->data);
661 if (err < 0) {
662 dev_err(dev, "failed to save context for USB3#%u: %d\n",
663 msg->data, err);
664 rsp.cmd = MBOX_CMD_NAK;
665 } else {
666 rsp.cmd = MBOX_CMD_ACK;
667 }
668
669 rsp.data = msg->data;
670 break;
671
672 case MBOX_CMD_START_HSIC_IDLE:
673 case MBOX_CMD_STOP_HSIC_IDLE:
674 if (msg->cmd == MBOX_CMD_STOP_HSIC_IDLE)
675 idle = false;
676 else
677 idle = true;
678
679 mask = extract_field(msg->data, 1 + soc->ports.hsic.offset,
680 soc->ports.hsic.count);
681
682 for_each_set_bit(port, &mask, 32) {
683 err = tegra_xusb_padctl_hsic_set_idle(padctl, port,
684 idle);
685 if (err < 0)
686 break;
687 }
688
689 if (err < 0) {
690 dev_err(dev, "failed to set HSIC#%u %s: %d\n", port,
691 idle ? "idle" : "busy", err);
692 rsp.cmd = MBOX_CMD_NAK;
693 } else {
694 rsp.cmd = MBOX_CMD_ACK;
695 }
696
697 rsp.data = msg->data;
698 break;
699
700 case MBOX_CMD_DISABLE_SS_LFPS_DETECTION:
701 case MBOX_CMD_ENABLE_SS_LFPS_DETECTION:
702 if (msg->cmd == MBOX_CMD_DISABLE_SS_LFPS_DETECTION)
703 enable = false;
704 else
705 enable = true;
706
707 mask = extract_field(msg->data, 1 + soc->ports.usb3.offset,
708 soc->ports.usb3.count);
709
710 for_each_set_bit(port, &mask, soc->ports.usb3.count) {
711 err = tegra_xusb_padctl_usb3_set_lfps_detect(padctl,
712 port,
713 enable);
714 if (err < 0)
715 break;
716
717 /*
718 * wait 500us for LFPS detector to be disabled before
719 * sending ACK
720 */
721 if (!enable)
722 usleep_range(500, 1000);
723 }
724
725 if (err < 0) {
726 dev_err(dev,
727 "failed to %s LFPS detection on USB3#%u: %d\n",
728 str_enable_disable(enable), port, err);
729 rsp.cmd = MBOX_CMD_NAK;
730 } else {
731 rsp.cmd = MBOX_CMD_ACK;
732 }
733
734 rsp.data = msg->data;
735 break;
736
737 default:
738 dev_warn(dev, "unknown message: %#x\n", msg->cmd);
739 break;
740 }
741
742 if (rsp.cmd) {
743 const char *cmd = (rsp.cmd == MBOX_CMD_ACK) ? "ACK" : "NAK";
744
745 err = tegra_xusb_mbox_send(tegra, &rsp);
746 if (err < 0)
747 dev_err(dev, "failed to send %s: %d\n", cmd, err);
748 }
749 }
750
tegra_xusb_mbox_thread(int irq,void * data)751 static irqreturn_t tegra_xusb_mbox_thread(int irq, void *data)
752 {
753 struct tegra_xusb *tegra = data;
754 const struct tegra_xusb_soc_ops *ops = tegra->soc->ops;
755 struct tegra_xusb_mbox_msg msg;
756 u32 value;
757
758 mutex_lock(&tegra->lock);
759
760 if (pm_runtime_suspended(tegra->dev) || tegra->suspended)
761 goto out;
762
763 value = ops->mbox_reg_readl(tegra, tegra->soc->mbox.data_out);
764 tegra_xusb_mbox_unpack(&msg, value);
765
766 value = ops->mbox_reg_readl(tegra, tegra->soc->mbox.cmd);
767 value &= ~MBOX_DEST_SMI;
768 ops->mbox_reg_writel(tegra, value, tegra->soc->mbox.cmd);
769
770 /* clear mailbox owner if no ACK/NAK is required */
771 if (!tegra_xusb_mbox_cmd_requires_ack(msg.cmd))
772 ops->mbox_reg_writel(tegra, MBOX_OWNER_NONE, tegra->soc->mbox.owner);
773
774 tegra_xusb_mbox_handle(tegra, &msg);
775
776 out:
777 mutex_unlock(&tegra->lock);
778 return IRQ_HANDLED;
779 }
780
tegra_xusb_config(struct tegra_xusb * tegra)781 static void tegra_xusb_config(struct tegra_xusb *tegra)
782 {
783 u32 regs = tegra->hcd->rsrc_start;
784 u32 value;
785
786 if (tegra->soc->has_ipfs) {
787 value = ipfs_readl(tegra, IPFS_XUSB_HOST_CONFIGURATION_0);
788 value |= IPFS_EN_FPCI;
789 ipfs_writel(tegra, value, IPFS_XUSB_HOST_CONFIGURATION_0);
790
791 usleep_range(10, 20);
792 }
793
794 /* Program BAR0 space */
795 value = fpci_readl(tegra, XUSB_CFG_4);
796 value &= ~(XUSB_BASE_ADDR_MASK << XUSB_BASE_ADDR_SHIFT);
797 value |= regs & (XUSB_BASE_ADDR_MASK << XUSB_BASE_ADDR_SHIFT);
798 fpci_writel(tegra, value, XUSB_CFG_4);
799
800 /* Program BAR2 space */
801 if (tegra->bar2) {
802 value = fpci_readl(tegra, XUSB_CFG_7);
803 value &= ~(XUSB_BASE2_ADDR_MASK << XUSB_BASE2_ADDR_SHIFT);
804 value |= tegra->bar2->start &
805 (XUSB_BASE2_ADDR_MASK << XUSB_BASE2_ADDR_SHIFT);
806 fpci_writel(tegra, value, XUSB_CFG_7);
807 }
808
809 usleep_range(100, 200);
810
811 /* Enable bus master */
812 value = fpci_readl(tegra, XUSB_CFG_1);
813 value |= XUSB_IO_SPACE_EN | XUSB_MEM_SPACE_EN | XUSB_BUS_MASTER_EN;
814 fpci_writel(tegra, value, XUSB_CFG_1);
815
816 if (tegra->soc->has_ipfs) {
817 /* Enable interrupt assertion */
818 value = ipfs_readl(tegra, IPFS_XUSB_HOST_INTR_MASK_0);
819 value |= IPFS_IP_INT_MASK;
820 ipfs_writel(tegra, value, IPFS_XUSB_HOST_INTR_MASK_0);
821
822 /* Set hysteresis */
823 ipfs_writel(tegra, 0x80, IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
824 }
825 }
826
tegra_xusb_clk_enable(struct tegra_xusb * tegra)827 static int tegra_xusb_clk_enable(struct tegra_xusb *tegra)
828 {
829 int err;
830
831 err = clk_prepare_enable(tegra->pll_e);
832 if (err < 0)
833 return err;
834
835 err = clk_prepare_enable(tegra->host_clk);
836 if (err < 0)
837 goto disable_plle;
838
839 err = clk_prepare_enable(tegra->ss_clk);
840 if (err < 0)
841 goto disable_host;
842
843 err = clk_prepare_enable(tegra->falcon_clk);
844 if (err < 0)
845 goto disable_ss;
846
847 err = clk_prepare_enable(tegra->fs_src_clk);
848 if (err < 0)
849 goto disable_falc;
850
851 err = clk_prepare_enable(tegra->hs_src_clk);
852 if (err < 0)
853 goto disable_fs_src;
854
855 if (tegra->soc->scale_ss_clock) {
856 err = tegra_xusb_set_ss_clk(tegra, TEGRA_XHCI_SS_HIGH_SPEED);
857 if (err < 0)
858 goto disable_hs_src;
859 }
860
861 return 0;
862
863 disable_hs_src:
864 clk_disable_unprepare(tegra->hs_src_clk);
865 disable_fs_src:
866 clk_disable_unprepare(tegra->fs_src_clk);
867 disable_falc:
868 clk_disable_unprepare(tegra->falcon_clk);
869 disable_ss:
870 clk_disable_unprepare(tegra->ss_clk);
871 disable_host:
872 clk_disable_unprepare(tegra->host_clk);
873 disable_plle:
874 clk_disable_unprepare(tegra->pll_e);
875 return err;
876 }
877
tegra_xusb_clk_disable(struct tegra_xusb * tegra)878 static void tegra_xusb_clk_disable(struct tegra_xusb *tegra)
879 {
880 clk_disable_unprepare(tegra->pll_e);
881 clk_disable_unprepare(tegra->host_clk);
882 clk_disable_unprepare(tegra->ss_clk);
883 clk_disable_unprepare(tegra->falcon_clk);
884 clk_disable_unprepare(tegra->fs_src_clk);
885 clk_disable_unprepare(tegra->hs_src_clk);
886 }
887
tegra_xusb_phy_enable(struct tegra_xusb * tegra)888 static int tegra_xusb_phy_enable(struct tegra_xusb *tegra)
889 {
890 unsigned int i;
891 int err;
892
893 for (i = 0; i < tegra->num_phys; i++) {
894 err = phy_init(tegra->phys[i]);
895 if (err)
896 goto disable_phy;
897
898 err = phy_power_on(tegra->phys[i]);
899 if (err) {
900 phy_exit(tegra->phys[i]);
901 goto disable_phy;
902 }
903 }
904
905 return 0;
906
907 disable_phy:
908 while (i--) {
909 phy_power_off(tegra->phys[i]);
910 phy_exit(tegra->phys[i]);
911 }
912
913 return err;
914 }
915
tegra_xusb_phy_disable(struct tegra_xusb * tegra)916 static void tegra_xusb_phy_disable(struct tegra_xusb *tegra)
917 {
918 unsigned int i;
919
920 for (i = 0; i < tegra->num_phys; i++) {
921 phy_power_off(tegra->phys[i]);
922 phy_exit(tegra->phys[i]);
923 }
924 }
925
926 #ifdef CONFIG_PM_SLEEP
tegra_xusb_init_context(struct tegra_xusb * tegra)927 static int tegra_xusb_init_context(struct tegra_xusb *tegra)
928 {
929 const struct tegra_xusb_context_soc *soc = tegra->soc->context;
930
931 tegra->context.ipfs = devm_kcalloc(tegra->dev, soc->ipfs.num_offsets,
932 sizeof(u32), GFP_KERNEL);
933 if (!tegra->context.ipfs)
934 return -ENOMEM;
935
936 tegra->context.fpci = devm_kcalloc(tegra->dev, soc->fpci.num_offsets,
937 sizeof(u32), GFP_KERNEL);
938 if (!tegra->context.fpci)
939 return -ENOMEM;
940
941 return 0;
942 }
943 #else
tegra_xusb_init_context(struct tegra_xusb * tegra)944 static inline int tegra_xusb_init_context(struct tegra_xusb *tegra)
945 {
946 return 0;
947 }
948 #endif
949
tegra_xusb_request_firmware(struct tegra_xusb * tegra)950 static int tegra_xusb_request_firmware(struct tegra_xusb *tegra)
951 {
952 struct tegra_xusb_fw_header *header;
953 const struct firmware *fw;
954 int err;
955
956 err = request_firmware(&fw, tegra->soc->firmware, tegra->dev);
957 if (err < 0) {
958 dev_err(tegra->dev, "failed to request firmware: %d\n", err);
959 return err;
960 }
961
962 /* Load Falcon controller with its firmware. */
963 header = (struct tegra_xusb_fw_header *)fw->data;
964 tegra->fw.size = le32_to_cpu(header->fwimg_len);
965
966 tegra->fw.virt = dma_alloc_coherent(tegra->dev, tegra->fw.size,
967 &tegra->fw.phys, GFP_KERNEL);
968 if (!tegra->fw.virt) {
969 dev_err(tegra->dev, "failed to allocate memory for firmware\n");
970 release_firmware(fw);
971 return -ENOMEM;
972 }
973
974 header = (struct tegra_xusb_fw_header *)tegra->fw.virt;
975 memcpy(tegra->fw.virt, fw->data, tegra->fw.size);
976 release_firmware(fw);
977
978 return 0;
979 }
980
tegra_xusb_wait_for_falcon(struct tegra_xusb * tegra)981 static int tegra_xusb_wait_for_falcon(struct tegra_xusb *tegra)
982 {
983 struct xhci_cap_regs __iomem *cap_regs;
984 struct xhci_op_regs __iomem *op_regs;
985 int ret;
986 u32 value;
987
988 cap_regs = tegra->regs;
989 op_regs = tegra->regs + HC_LENGTH(readl(&cap_regs->hc_capbase));
990
991 ret = readl_poll_timeout(&op_regs->status, value, !(value & STS_CNR), 1000, 200000);
992
993 if (ret)
994 dev_err(tegra->dev, "XHCI Controller not ready. Falcon state: 0x%x\n",
995 csb_readl(tegra, XUSB_FALC_CPUCTL));
996
997 return ret;
998 }
999
tegra_xusb_load_firmware_rom(struct tegra_xusb * tegra)1000 static int tegra_xusb_load_firmware_rom(struct tegra_xusb *tegra)
1001 {
1002 unsigned int code_tag_blocks, code_size_blocks, code_blocks;
1003 struct tegra_xusb_fw_header *header;
1004 struct device *dev = tegra->dev;
1005 time64_t timestamp;
1006 u64 address;
1007 u32 value;
1008 int err;
1009
1010 header = (struct tegra_xusb_fw_header *)tegra->fw.virt;
1011
1012 if (csb_readl(tegra, XUSB_CSB_MP_ILOAD_BASE_LO) != 0) {
1013 dev_info(dev, "Firmware already loaded, Falcon state %#x\n",
1014 csb_readl(tegra, XUSB_FALC_CPUCTL));
1015 return 0;
1016 }
1017
1018 /* Program the size of DFI into ILOAD_ATTR. */
1019 csb_writel(tegra, tegra->fw.size, XUSB_CSB_MP_ILOAD_ATTR);
1020
1021 /*
1022 * Boot code of the firmware reads the ILOAD_BASE registers
1023 * to get to the start of the DFI in system memory.
1024 */
1025 address = tegra->fw.phys + sizeof(*header);
1026 csb_writel(tegra, address >> 32, XUSB_CSB_MP_ILOAD_BASE_HI);
1027 csb_writel(tegra, address, XUSB_CSB_MP_ILOAD_BASE_LO);
1028
1029 /* Set BOOTPATH to 1 in APMAP. */
1030 csb_writel(tegra, APMAP_BOOTPATH, XUSB_CSB_MP_APMAP);
1031
1032 /* Invalidate L2IMEM. */
1033 csb_writel(tegra, L2IMEMOP_INVALIDATE_ALL, XUSB_CSB_MP_L2IMEMOP_TRIG);
1034
1035 /*
1036 * Initiate fetch of bootcode from system memory into L2IMEM.
1037 * Program bootcode location and size in system memory.
1038 */
1039 code_tag_blocks = DIV_ROUND_UP(le32_to_cpu(header->boot_codetag),
1040 IMEM_BLOCK_SIZE);
1041 code_size_blocks = DIV_ROUND_UP(le32_to_cpu(header->boot_codesize),
1042 IMEM_BLOCK_SIZE);
1043 code_blocks = code_tag_blocks + code_size_blocks;
1044
1045 value = ((code_tag_blocks & L2IMEMOP_SIZE_SRC_OFFSET_MASK) <<
1046 L2IMEMOP_SIZE_SRC_OFFSET_SHIFT) |
1047 ((code_size_blocks & L2IMEMOP_SIZE_SRC_COUNT_MASK) <<
1048 L2IMEMOP_SIZE_SRC_COUNT_SHIFT);
1049 csb_writel(tegra, value, XUSB_CSB_MP_L2IMEMOP_SIZE);
1050
1051 /* Trigger L2IMEM load operation. */
1052 csb_writel(tegra, L2IMEMOP_LOAD_LOCKED_RESULT,
1053 XUSB_CSB_MP_L2IMEMOP_TRIG);
1054
1055 /* Setup Falcon auto-fill. */
1056 csb_writel(tegra, code_size_blocks, XUSB_FALC_IMFILLCTL);
1057
1058 value = ((code_tag_blocks & IMFILLRNG1_TAG_MASK) <<
1059 IMFILLRNG1_TAG_LO_SHIFT) |
1060 ((code_blocks & IMFILLRNG1_TAG_MASK) <<
1061 IMFILLRNG1_TAG_HI_SHIFT);
1062 csb_writel(tegra, value, XUSB_FALC_IMFILLRNG1);
1063
1064 csb_writel(tegra, 0, XUSB_FALC_DMACTL);
1065
1066 /* wait for RESULT_VLD to get set */
1067 #define tegra_csb_readl(offset) csb_readl(tegra, offset)
1068 err = readx_poll_timeout(tegra_csb_readl,
1069 XUSB_CSB_MEMPOOL_L2IMEMOP_RESULT, value,
1070 value & L2IMEMOP_RESULT_VLD, 100, 10000);
1071 if (err < 0) {
1072 dev_err(dev, "DMA controller not ready %#010x\n", value);
1073 return err;
1074 }
1075 #undef tegra_csb_readl
1076
1077 csb_writel(tegra, le32_to_cpu(header->boot_codetag),
1078 XUSB_FALC_BOOTVEC);
1079
1080 /* Boot Falcon CPU and wait for USBSTS_CNR to get cleared. */
1081 csb_writel(tegra, CPUCTL_STARTCPU, XUSB_FALC_CPUCTL);
1082
1083 if (tegra_xusb_wait_for_falcon(tegra))
1084 return -EIO;
1085
1086 timestamp = le32_to_cpu(header->fwimg_created_time);
1087
1088 dev_info(dev, "Firmware timestamp: %ptTs UTC\n", ×tamp);
1089
1090 return 0;
1091 }
1092
tegra_xusb_read_firmware_header(struct tegra_xusb * tegra,u32 offset)1093 static u32 tegra_xusb_read_firmware_header(struct tegra_xusb *tegra, u32 offset)
1094 {
1095 /*
1096 * We only accept reading the firmware config table
1097 * The offset should not exceed the fw header structure
1098 */
1099 if (offset >= sizeof(struct tegra_xusb_fw_header))
1100 return 0;
1101
1102 bar2_writel(tegra, (FW_IOCTL_CFGTBL_READ << FW_IOCTL_TYPE_SHIFT) | offset,
1103 XUSB_BAR2_ARU_FW_SCRATCH);
1104 return bar2_readl(tegra, XUSB_BAR2_ARU_SMI_ARU_FW_SCRATCH_DATA0);
1105 }
1106
tegra_xusb_init_ifr_firmware(struct tegra_xusb * tegra)1107 static int tegra_xusb_init_ifr_firmware(struct tegra_xusb *tegra)
1108 {
1109 time64_t timestamp;
1110
1111 if (tegra_xusb_wait_for_falcon(tegra))
1112 return -EIO;
1113
1114 #define offsetof_32(X, Y) ((u8)(offsetof(X, Y) / sizeof(__le32)))
1115 timestamp = tegra_xusb_read_firmware_header(tegra, offsetof_32(struct tegra_xusb_fw_header,
1116 fwimg_created_time) << 2);
1117
1118 dev_info(tegra->dev, "Firmware timestamp: %ptTs UTC\n", ×tamp);
1119
1120 return 0;
1121 }
1122
tegra_xusb_load_firmware(struct tegra_xusb * tegra)1123 static int tegra_xusb_load_firmware(struct tegra_xusb *tegra)
1124 {
1125 if (!tegra->soc->firmware)
1126 return tegra_xusb_init_ifr_firmware(tegra);
1127 else
1128 return tegra_xusb_load_firmware_rom(tegra);
1129 }
1130
tegra_xusb_powerdomain_remove(struct device * dev,struct tegra_xusb * tegra)1131 static void tegra_xusb_powerdomain_remove(struct device *dev,
1132 struct tegra_xusb *tegra)
1133 {
1134 if (!tegra->use_genpd)
1135 return;
1136
1137 if (!IS_ERR_OR_NULL(tegra->genpd_dev_ss))
1138 dev_pm_domain_detach(tegra->genpd_dev_ss, true);
1139 if (!IS_ERR_OR_NULL(tegra->genpd_dev_host))
1140 dev_pm_domain_detach(tegra->genpd_dev_host, true);
1141 }
1142
tegra_xusb_powerdomain_init(struct device * dev,struct tegra_xusb * tegra)1143 static int tegra_xusb_powerdomain_init(struct device *dev,
1144 struct tegra_xusb *tegra)
1145 {
1146 int err;
1147
1148 tegra->genpd_dev_host = dev_pm_domain_attach_by_name(dev, "xusb_host");
1149 if (IS_ERR(tegra->genpd_dev_host)) {
1150 err = PTR_ERR(tegra->genpd_dev_host);
1151 dev_err(dev, "failed to get host pm-domain: %d\n", err);
1152 return err;
1153 }
1154
1155 tegra->genpd_dev_ss = dev_pm_domain_attach_by_name(dev, "xusb_ss");
1156 if (IS_ERR(tegra->genpd_dev_ss)) {
1157 err = PTR_ERR(tegra->genpd_dev_ss);
1158 dev_err(dev, "failed to get superspeed pm-domain: %d\n", err);
1159 return err;
1160 }
1161
1162 tegra->use_genpd = true;
1163
1164 return 0;
1165 }
1166
tegra_xusb_unpowergate_partitions(struct tegra_xusb * tegra)1167 static int tegra_xusb_unpowergate_partitions(struct tegra_xusb *tegra)
1168 {
1169 struct device *dev = tegra->dev;
1170 int rc;
1171
1172 if (tegra->use_genpd) {
1173 rc = pm_runtime_resume_and_get(tegra->genpd_dev_ss);
1174 if (rc < 0) {
1175 dev_err(dev, "failed to enable XUSB SS partition\n");
1176 return rc;
1177 }
1178
1179 rc = pm_runtime_resume_and_get(tegra->genpd_dev_host);
1180 if (rc < 0) {
1181 dev_err(dev, "failed to enable XUSB Host partition\n");
1182 pm_runtime_put_sync(tegra->genpd_dev_ss);
1183 return rc;
1184 }
1185 } else {
1186 rc = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_XUSBA,
1187 tegra->ss_clk,
1188 tegra->ss_rst);
1189 if (rc < 0) {
1190 dev_err(dev, "failed to enable XUSB SS partition\n");
1191 return rc;
1192 }
1193
1194 rc = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_XUSBC,
1195 tegra->host_clk,
1196 tegra->host_rst);
1197 if (rc < 0) {
1198 dev_err(dev, "failed to enable XUSB Host partition\n");
1199 tegra_powergate_power_off(TEGRA_POWERGATE_XUSBA);
1200 return rc;
1201 }
1202 }
1203
1204 return 0;
1205 }
1206
tegra_xusb_powergate_partitions(struct tegra_xusb * tegra)1207 static int tegra_xusb_powergate_partitions(struct tegra_xusb *tegra)
1208 {
1209 struct device *dev = tegra->dev;
1210 int rc;
1211
1212 if (tegra->use_genpd) {
1213 rc = pm_runtime_put_sync(tegra->genpd_dev_host);
1214 if (rc < 0) {
1215 dev_err(dev, "failed to disable XUSB Host partition\n");
1216 return rc;
1217 }
1218
1219 rc = pm_runtime_put_sync(tegra->genpd_dev_ss);
1220 if (rc < 0) {
1221 dev_err(dev, "failed to disable XUSB SS partition\n");
1222 pm_runtime_get_sync(tegra->genpd_dev_host);
1223 return rc;
1224 }
1225 } else {
1226 rc = tegra_powergate_power_off(TEGRA_POWERGATE_XUSBC);
1227 if (rc < 0) {
1228 dev_err(dev, "failed to disable XUSB Host partition\n");
1229 return rc;
1230 }
1231
1232 rc = tegra_powergate_power_off(TEGRA_POWERGATE_XUSBA);
1233 if (rc < 0) {
1234 dev_err(dev, "failed to disable XUSB SS partition\n");
1235 tegra_powergate_sequence_power_up(TEGRA_POWERGATE_XUSBC,
1236 tegra->host_clk,
1237 tegra->host_rst);
1238 return rc;
1239 }
1240 }
1241
1242 return 0;
1243 }
1244
__tegra_xusb_enable_firmware_messages(struct tegra_xusb * tegra)1245 static int __tegra_xusb_enable_firmware_messages(struct tegra_xusb *tegra)
1246 {
1247 struct tegra_xusb_mbox_msg msg;
1248 int err;
1249
1250 /* Enable firmware messages from controller. */
1251 msg.cmd = MBOX_CMD_MSG_ENABLED;
1252 msg.data = 0;
1253
1254 err = tegra_xusb_mbox_send(tegra, &msg);
1255 if (err < 0)
1256 dev_err(tegra->dev, "failed to enable messages: %d\n", err);
1257
1258 return err;
1259 }
1260
tegra_xusb_padctl_irq(int irq,void * data)1261 static irqreturn_t tegra_xusb_padctl_irq(int irq, void *data)
1262 {
1263 struct tegra_xusb *tegra = data;
1264
1265 mutex_lock(&tegra->lock);
1266
1267 if (tegra->suspended) {
1268 mutex_unlock(&tegra->lock);
1269 return IRQ_HANDLED;
1270 }
1271
1272 mutex_unlock(&tegra->lock);
1273
1274 pm_runtime_resume(tegra->dev);
1275
1276 return IRQ_HANDLED;
1277 }
1278
tegra_xusb_enable_firmware_messages(struct tegra_xusb * tegra)1279 static int tegra_xusb_enable_firmware_messages(struct tegra_xusb *tegra)
1280 {
1281 int err;
1282
1283 mutex_lock(&tegra->lock);
1284 err = __tegra_xusb_enable_firmware_messages(tegra);
1285 mutex_unlock(&tegra->lock);
1286
1287 return err;
1288 }
1289
tegra_xhci_set_port_power(struct tegra_xusb * tegra,bool main,bool set)1290 static void tegra_xhci_set_port_power(struct tegra_xusb *tegra, bool main,
1291 bool set)
1292 {
1293 struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
1294 struct usb_hcd *hcd = main ? xhci->main_hcd : xhci->shared_hcd;
1295 unsigned int wait = (!main && !set) ? 1000 : 10;
1296 u16 typeReq = set ? SetPortFeature : ClearPortFeature;
1297 u16 wIndex = main ? tegra->otg_usb2_port + 1 : tegra->otg_usb3_port + 1;
1298 u32 status;
1299 u32 stat_power = main ? USB_PORT_STAT_POWER : USB_SS_PORT_STAT_POWER;
1300 u32 status_val = set ? stat_power : 0;
1301
1302 dev_dbg(tegra->dev, "%s():%s %s port power\n", __func__,
1303 set ? "set" : "clear", main ? "HS" : "SS");
1304
1305 hcd->driver->hub_control(hcd, typeReq, USB_PORT_FEAT_POWER, wIndex,
1306 NULL, 0);
1307
1308 do {
1309 tegra_xhci_hc_driver.hub_control(hcd, GetPortStatus, 0, wIndex,
1310 (char *) &status, sizeof(status));
1311 if (status_val == (status & stat_power))
1312 break;
1313
1314 if (!main && !set)
1315 usleep_range(600, 700);
1316 else
1317 usleep_range(10, 20);
1318 } while (--wait > 0);
1319
1320 if (status_val != (status & stat_power))
1321 dev_info(tegra->dev, "failed to %s %s PP %d\n",
1322 set ? "set" : "clear",
1323 main ? "HS" : "SS", status);
1324 }
1325
tegra_xusb_get_phy(struct tegra_xusb * tegra,char * name,int port)1326 static struct phy *tegra_xusb_get_phy(struct tegra_xusb *tegra, char *name,
1327 int port)
1328 {
1329 unsigned int i, phy_count = 0;
1330
1331 for (i = 0; i < tegra->soc->num_types; i++) {
1332 if (!strncmp(tegra->soc->phy_types[i].name, name,
1333 strlen(name)))
1334 return tegra->phys[phy_count+port];
1335
1336 phy_count += tegra->soc->phy_types[i].num;
1337 }
1338
1339 return NULL;
1340 }
1341
tegra_xhci_id_work(struct work_struct * work)1342 static void tegra_xhci_id_work(struct work_struct *work)
1343 {
1344 struct tegra_xusb *tegra = container_of(work, struct tegra_xusb,
1345 id_work);
1346 struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
1347 struct tegra_xusb_mbox_msg msg;
1348 struct phy *phy = tegra_xusb_get_phy(tegra, "usb2",
1349 tegra->otg_usb2_port);
1350 u32 status;
1351 int ret;
1352
1353 dev_dbg(tegra->dev, "host mode %s\n", str_on_off(tegra->host_mode));
1354
1355 mutex_lock(&tegra->lock);
1356
1357 if (tegra->host_mode)
1358 phy_set_mode_ext(phy, PHY_MODE_USB_OTG, USB_ROLE_HOST);
1359 else
1360 phy_set_mode_ext(phy, PHY_MODE_USB_OTG, USB_ROLE_NONE);
1361
1362 mutex_unlock(&tegra->lock);
1363
1364 tegra->otg_usb3_port = tegra_xusb_padctl_get_usb3_companion(tegra->padctl,
1365 tegra->otg_usb2_port);
1366
1367 pm_runtime_get_sync(tegra->dev);
1368 if (tegra->host_mode) {
1369 /* switch to host mode */
1370 if (tegra->otg_usb3_port >= 0) {
1371 if (tegra->soc->otg_reset_sspi) {
1372 /* set PP=0 */
1373 tegra_xhci_hc_driver.hub_control(
1374 xhci->shared_hcd, GetPortStatus,
1375 0, tegra->otg_usb3_port+1,
1376 (char *) &status, sizeof(status));
1377 if (status & USB_SS_PORT_STAT_POWER)
1378 tegra_xhci_set_port_power(tegra, false,
1379 false);
1380
1381 /* reset OTG port SSPI */
1382 msg.cmd = MBOX_CMD_RESET_SSPI;
1383 msg.data = tegra->otg_usb3_port+1;
1384
1385 ret = tegra_xusb_mbox_send(tegra, &msg);
1386 if (ret < 0) {
1387 dev_info(tegra->dev,
1388 "failed to RESET_SSPI %d\n",
1389 ret);
1390 }
1391 }
1392
1393 tegra_xhci_set_port_power(tegra, false, true);
1394 }
1395
1396 tegra_xhci_set_port_power(tegra, true, true);
1397 pm_runtime_mark_last_busy(tegra->dev);
1398
1399 } else {
1400 if (tegra->otg_usb3_port >= 0)
1401 tegra_xhci_set_port_power(tegra, false, false);
1402
1403 tegra_xhci_set_port_power(tegra, true, false);
1404 }
1405 pm_runtime_put_autosuspend(tegra->dev);
1406 }
1407
1408 #if IS_ENABLED(CONFIG_PM) || IS_ENABLED(CONFIG_PM_SLEEP)
is_usb2_otg_phy(struct tegra_xusb * tegra,unsigned int index)1409 static bool is_usb2_otg_phy(struct tegra_xusb *tegra, unsigned int index)
1410 {
1411 return (tegra->usbphy[index] != NULL);
1412 }
1413
is_usb3_otg_phy(struct tegra_xusb * tegra,unsigned int index)1414 static bool is_usb3_otg_phy(struct tegra_xusb *tegra, unsigned int index)
1415 {
1416 struct tegra_xusb_padctl *padctl = tegra->padctl;
1417 unsigned int i;
1418 int port;
1419
1420 for (i = 0; i < tegra->num_usb_phys; i++) {
1421 if (is_usb2_otg_phy(tegra, i)) {
1422 port = tegra_xusb_padctl_get_usb3_companion(padctl, i);
1423 if ((port >= 0) && (index == (unsigned int)port))
1424 return true;
1425 }
1426 }
1427
1428 return false;
1429 }
1430
is_host_mode_phy(struct tegra_xusb * tegra,unsigned int phy_type,unsigned int index)1431 static bool is_host_mode_phy(struct tegra_xusb *tegra, unsigned int phy_type, unsigned int index)
1432 {
1433 if (strcmp(tegra->soc->phy_types[phy_type].name, "hsic") == 0)
1434 return true;
1435
1436 if (strcmp(tegra->soc->phy_types[phy_type].name, "usb2") == 0) {
1437 if (is_usb2_otg_phy(tegra, index))
1438 return ((index == tegra->otg_usb2_port) && tegra->host_mode);
1439 else
1440 return true;
1441 }
1442
1443 if (strcmp(tegra->soc->phy_types[phy_type].name, "usb3") == 0) {
1444 if (is_usb3_otg_phy(tegra, index))
1445 return ((index == tegra->otg_usb3_port) && tegra->host_mode);
1446 else
1447 return true;
1448 }
1449
1450 return false;
1451 }
1452 #endif
1453
tegra_xusb_get_usb2_port(struct tegra_xusb * tegra,struct usb_phy * usbphy)1454 static int tegra_xusb_get_usb2_port(struct tegra_xusb *tegra,
1455 struct usb_phy *usbphy)
1456 {
1457 unsigned int i;
1458
1459 for (i = 0; i < tegra->num_usb_phys; i++) {
1460 if (tegra->usbphy[i] && usbphy == tegra->usbphy[i])
1461 return i;
1462 }
1463
1464 return -1;
1465 }
1466
tegra_xhci_id_notify(struct notifier_block * nb,unsigned long action,void * data)1467 static int tegra_xhci_id_notify(struct notifier_block *nb,
1468 unsigned long action, void *data)
1469 {
1470 struct tegra_xusb *tegra = container_of(nb, struct tegra_xusb,
1471 id_nb);
1472 struct usb_phy *usbphy = (struct usb_phy *)data;
1473
1474 dev_dbg(tegra->dev, "%s(): action is %d", __func__, usbphy->last_event);
1475
1476 if ((tegra->host_mode && usbphy->last_event == USB_EVENT_ID) ||
1477 (!tegra->host_mode && usbphy->last_event != USB_EVENT_ID)) {
1478 dev_dbg(tegra->dev, "Same role(%d) received. Ignore",
1479 tegra->host_mode);
1480 return NOTIFY_OK;
1481 }
1482
1483 tegra->otg_usb2_port = tegra_xusb_get_usb2_port(tegra, usbphy);
1484
1485 tegra->host_mode = (usbphy->last_event == USB_EVENT_ID) ? true : false;
1486
1487 schedule_work(&tegra->id_work);
1488
1489 return NOTIFY_OK;
1490 }
1491
tegra_xusb_init_usb_phy(struct tegra_xusb * tegra)1492 static int tegra_xusb_init_usb_phy(struct tegra_xusb *tegra)
1493 {
1494 unsigned int i;
1495
1496 tegra->usbphy = devm_kcalloc(tegra->dev, tegra->num_usb_phys,
1497 sizeof(*tegra->usbphy), GFP_KERNEL);
1498 if (!tegra->usbphy)
1499 return -ENOMEM;
1500
1501 INIT_WORK(&tegra->id_work, tegra_xhci_id_work);
1502 tegra->id_nb.notifier_call = tegra_xhci_id_notify;
1503 tegra->otg_usb2_port = -EINVAL;
1504 tegra->otg_usb3_port = -EINVAL;
1505
1506 for (i = 0; i < tegra->num_usb_phys; i++) {
1507 struct phy *phy = tegra_xusb_get_phy(tegra, "usb2", i);
1508
1509 if (!phy)
1510 continue;
1511
1512 tegra->usbphy[i] = devm_usb_get_phy_by_node(tegra->dev,
1513 phy->dev.of_node,
1514 &tegra->id_nb);
1515 if (!IS_ERR(tegra->usbphy[i])) {
1516 dev_dbg(tegra->dev, "usbphy-%d registered", i);
1517 otg_set_host(tegra->usbphy[i]->otg, &tegra->hcd->self);
1518 } else {
1519 /*
1520 * usb-phy is optional, continue if its not available.
1521 */
1522 tegra->usbphy[i] = NULL;
1523 }
1524 }
1525
1526 return 0;
1527 }
1528
tegra_xusb_deinit_usb_phy(struct tegra_xusb * tegra)1529 static void tegra_xusb_deinit_usb_phy(struct tegra_xusb *tegra)
1530 {
1531 unsigned int i;
1532
1533 cancel_work_sync(&tegra->id_work);
1534
1535 for (i = 0; i < tegra->num_usb_phys; i++)
1536 if (tegra->usbphy[i])
1537 otg_set_host(tegra->usbphy[i]->otg, NULL);
1538 }
1539
tegra_xusb_probe(struct platform_device * pdev)1540 static int tegra_xusb_probe(struct platform_device *pdev)
1541 {
1542 struct tegra_xusb *tegra;
1543 struct device_node *np;
1544 struct resource *regs;
1545 struct xhci_hcd *xhci;
1546 unsigned int i, j, k;
1547 struct phy *phy;
1548 int err;
1549
1550 BUILD_BUG_ON(sizeof(struct tegra_xusb_fw_header) != 256);
1551
1552 tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
1553 if (!tegra)
1554 return -ENOMEM;
1555
1556 tegra->soc = of_device_get_match_data(&pdev->dev);
1557 mutex_init(&tegra->lock);
1558 tegra->dev = &pdev->dev;
1559
1560 err = tegra_xusb_init_context(tegra);
1561 if (err < 0)
1562 return err;
1563
1564 tegra->regs = devm_platform_get_and_ioremap_resource(pdev, 0, ®s);
1565 if (IS_ERR(tegra->regs))
1566 return PTR_ERR(tegra->regs);
1567
1568 tegra->fpci_base = devm_platform_ioremap_resource(pdev, 1);
1569 if (IS_ERR(tegra->fpci_base))
1570 return PTR_ERR(tegra->fpci_base);
1571
1572 if (tegra->soc->has_ipfs) {
1573 tegra->ipfs_base = devm_platform_ioremap_resource(pdev, 2);
1574 if (IS_ERR(tegra->ipfs_base))
1575 return PTR_ERR(tegra->ipfs_base);
1576 } else if (tegra->soc->has_bar2) {
1577 tegra->bar2_base = devm_platform_get_and_ioremap_resource(pdev, 2, &tegra->bar2);
1578 if (IS_ERR(tegra->bar2_base))
1579 return PTR_ERR(tegra->bar2_base);
1580 }
1581
1582 tegra->xhci_irq = platform_get_irq(pdev, 0);
1583 if (tegra->xhci_irq < 0)
1584 return tegra->xhci_irq;
1585
1586 tegra->mbox_irq = platform_get_irq(pdev, 1);
1587 if (tegra->mbox_irq < 0)
1588 return tegra->mbox_irq;
1589
1590 tegra->padctl = tegra_xusb_padctl_get(&pdev->dev);
1591 if (IS_ERR(tegra->padctl))
1592 return PTR_ERR(tegra->padctl);
1593
1594 np = of_parse_phandle(pdev->dev.of_node, "nvidia,xusb-padctl", 0);
1595 if (!np) {
1596 err = -ENODEV;
1597 goto put_padctl;
1598 }
1599
1600 tegra->padctl_irq = of_irq_get(np, 0);
1601 if (tegra->padctl_irq == -EPROBE_DEFER) {
1602 err = tegra->padctl_irq;
1603 goto put_padctl;
1604 } else if (tegra->padctl_irq <= 0) {
1605 /* Older device-trees don't have padctrl interrupt */
1606 tegra->padctl_irq = 0;
1607 dev_dbg(&pdev->dev,
1608 "%pOF is missing an interrupt, disabling PM support\n", np);
1609 }
1610
1611 tegra->host_clk = devm_clk_get(&pdev->dev, "xusb_host");
1612 if (IS_ERR(tegra->host_clk)) {
1613 err = PTR_ERR(tegra->host_clk);
1614 dev_err(&pdev->dev, "failed to get xusb_host: %d\n", err);
1615 goto put_padctl;
1616 }
1617
1618 tegra->falcon_clk = devm_clk_get(&pdev->dev, "xusb_falcon_src");
1619 if (IS_ERR(tegra->falcon_clk)) {
1620 err = PTR_ERR(tegra->falcon_clk);
1621 dev_err(&pdev->dev, "failed to get xusb_falcon_src: %d\n", err);
1622 goto put_padctl;
1623 }
1624
1625 tegra->ss_clk = devm_clk_get(&pdev->dev, "xusb_ss");
1626 if (IS_ERR(tegra->ss_clk)) {
1627 err = PTR_ERR(tegra->ss_clk);
1628 dev_err(&pdev->dev, "failed to get xusb_ss: %d\n", err);
1629 goto put_padctl;
1630 }
1631
1632 tegra->ss_src_clk = devm_clk_get(&pdev->dev, "xusb_ss_src");
1633 if (IS_ERR(tegra->ss_src_clk)) {
1634 err = PTR_ERR(tegra->ss_src_clk);
1635 dev_err(&pdev->dev, "failed to get xusb_ss_src: %d\n", err);
1636 goto put_padctl;
1637 }
1638
1639 tegra->hs_src_clk = devm_clk_get(&pdev->dev, "xusb_hs_src");
1640 if (IS_ERR(tegra->hs_src_clk)) {
1641 err = PTR_ERR(tegra->hs_src_clk);
1642 dev_err(&pdev->dev, "failed to get xusb_hs_src: %d\n", err);
1643 goto put_padctl;
1644 }
1645
1646 tegra->fs_src_clk = devm_clk_get(&pdev->dev, "xusb_fs_src");
1647 if (IS_ERR(tegra->fs_src_clk)) {
1648 err = PTR_ERR(tegra->fs_src_clk);
1649 dev_err(&pdev->dev, "failed to get xusb_fs_src: %d\n", err);
1650 goto put_padctl;
1651 }
1652
1653 tegra->pll_u_480m = devm_clk_get(&pdev->dev, "pll_u_480m");
1654 if (IS_ERR(tegra->pll_u_480m)) {
1655 err = PTR_ERR(tegra->pll_u_480m);
1656 dev_err(&pdev->dev, "failed to get pll_u_480m: %d\n", err);
1657 goto put_padctl;
1658 }
1659
1660 tegra->clk_m = devm_clk_get(&pdev->dev, "clk_m");
1661 if (IS_ERR(tegra->clk_m)) {
1662 err = PTR_ERR(tegra->clk_m);
1663 dev_err(&pdev->dev, "failed to get clk_m: %d\n", err);
1664 goto put_padctl;
1665 }
1666
1667 tegra->pll_e = devm_clk_get(&pdev->dev, "pll_e");
1668 if (IS_ERR(tegra->pll_e)) {
1669 err = PTR_ERR(tegra->pll_e);
1670 dev_err(&pdev->dev, "failed to get pll_e: %d\n", err);
1671 goto put_padctl;
1672 }
1673
1674 if (!of_property_present(pdev->dev.of_node, "power-domains")) {
1675 tegra->host_rst = devm_reset_control_get(&pdev->dev,
1676 "xusb_host");
1677 if (IS_ERR(tegra->host_rst)) {
1678 err = PTR_ERR(tegra->host_rst);
1679 dev_err(&pdev->dev,
1680 "failed to get xusb_host reset: %d\n", err);
1681 goto put_padctl;
1682 }
1683
1684 tegra->ss_rst = devm_reset_control_get(&pdev->dev, "xusb_ss");
1685 if (IS_ERR(tegra->ss_rst)) {
1686 err = PTR_ERR(tegra->ss_rst);
1687 dev_err(&pdev->dev, "failed to get xusb_ss reset: %d\n",
1688 err);
1689 goto put_padctl;
1690 }
1691 } else {
1692 err = tegra_xusb_powerdomain_init(&pdev->dev, tegra);
1693 if (err)
1694 goto put_powerdomains;
1695 }
1696
1697 tegra->supplies = devm_kcalloc(&pdev->dev, tegra->soc->num_supplies,
1698 sizeof(*tegra->supplies), GFP_KERNEL);
1699 if (!tegra->supplies) {
1700 err = -ENOMEM;
1701 goto put_powerdomains;
1702 }
1703
1704 regulator_bulk_set_supply_names(tegra->supplies,
1705 tegra->soc->supply_names,
1706 tegra->soc->num_supplies);
1707
1708 err = devm_regulator_bulk_get(&pdev->dev, tegra->soc->num_supplies,
1709 tegra->supplies);
1710 if (err) {
1711 dev_err(&pdev->dev, "failed to get regulators: %d\n", err);
1712 goto put_powerdomains;
1713 }
1714
1715 for (i = 0; i < tegra->soc->num_types; i++) {
1716 if (!strncmp(tegra->soc->phy_types[i].name, "usb2", 4))
1717 tegra->num_usb_phys = tegra->soc->phy_types[i].num;
1718 tegra->num_phys += tegra->soc->phy_types[i].num;
1719 }
1720
1721 tegra->phys = devm_kcalloc(&pdev->dev, tegra->num_phys,
1722 sizeof(*tegra->phys), GFP_KERNEL);
1723 if (!tegra->phys) {
1724 err = -ENOMEM;
1725 goto put_powerdomains;
1726 }
1727
1728 for (i = 0, k = 0; i < tegra->soc->num_types; i++) {
1729 char prop[8];
1730
1731 for (j = 0; j < tegra->soc->phy_types[i].num; j++) {
1732 snprintf(prop, sizeof(prop), "%s-%d",
1733 tegra->soc->phy_types[i].name, j);
1734
1735 phy = devm_phy_optional_get(&pdev->dev, prop);
1736 if (IS_ERR(phy)) {
1737 dev_err(&pdev->dev,
1738 "failed to get PHY %s: %ld\n", prop,
1739 PTR_ERR(phy));
1740 err = PTR_ERR(phy);
1741 goto put_powerdomains;
1742 }
1743
1744 tegra->phys[k++] = phy;
1745 }
1746 }
1747
1748 tegra->hcd = usb_create_hcd(&tegra_xhci_hc_driver, &pdev->dev,
1749 dev_name(&pdev->dev));
1750 if (!tegra->hcd) {
1751 err = -ENOMEM;
1752 goto put_powerdomains;
1753 }
1754
1755 tegra->hcd->skip_phy_initialization = 1;
1756 tegra->hcd->regs = tegra->regs;
1757 tegra->hcd->rsrc_start = regs->start;
1758 tegra->hcd->rsrc_len = resource_size(regs);
1759
1760 /*
1761 * This must happen after usb_create_hcd(), because usb_create_hcd()
1762 * will overwrite the drvdata of the device with the hcd it creates.
1763 */
1764 platform_set_drvdata(pdev, tegra);
1765
1766 err = tegra_xusb_clk_enable(tegra);
1767 if (err) {
1768 dev_err(tegra->dev, "failed to enable clocks: %d\n", err);
1769 goto put_hcd;
1770 }
1771
1772 err = regulator_bulk_enable(tegra->soc->num_supplies, tegra->supplies);
1773 if (err) {
1774 dev_err(tegra->dev, "failed to enable regulators: %d\n", err);
1775 goto disable_clk;
1776 }
1777
1778 err = tegra_xusb_phy_enable(tegra);
1779 if (err < 0) {
1780 dev_err(&pdev->dev, "failed to enable PHYs: %d\n", err);
1781 goto disable_regulator;
1782 }
1783
1784 /*
1785 * The XUSB Falcon microcontroller can only address 40 bits, so set
1786 * the DMA mask accordingly.
1787 */
1788 err = dma_set_mask_and_coherent(tegra->dev, DMA_BIT_MASK(40));
1789 if (err < 0) {
1790 dev_err(&pdev->dev, "failed to set DMA mask: %d\n", err);
1791 goto disable_phy;
1792 }
1793
1794 if (tegra->soc->firmware) {
1795 err = tegra_xusb_request_firmware(tegra);
1796 if (err < 0) {
1797 dev_err(&pdev->dev,
1798 "failed to request firmware: %d\n", err);
1799 goto disable_phy;
1800 }
1801 }
1802
1803 err = tegra_xusb_unpowergate_partitions(tegra);
1804 if (err)
1805 goto free_firmware;
1806
1807 tegra_xusb_config(tegra);
1808
1809 err = tegra_xusb_load_firmware(tegra);
1810 if (err < 0) {
1811 dev_err(&pdev->dev, "failed to load firmware: %d\n", err);
1812 goto powergate;
1813 }
1814
1815 err = usb_add_hcd(tegra->hcd, tegra->xhci_irq, IRQF_SHARED);
1816 if (err < 0) {
1817 dev_err(&pdev->dev, "failed to add USB HCD: %d\n", err);
1818 goto powergate;
1819 }
1820
1821 device_wakeup_enable(tegra->hcd->self.controller);
1822
1823 xhci = hcd_to_xhci(tegra->hcd);
1824
1825 xhci->shared_hcd = usb_create_shared_hcd(&tegra_xhci_hc_driver,
1826 &pdev->dev,
1827 dev_name(&pdev->dev),
1828 tegra->hcd);
1829 if (!xhci->shared_hcd) {
1830 dev_err(&pdev->dev, "failed to create shared HCD\n");
1831 err = -ENOMEM;
1832 goto remove_usb2;
1833 }
1834
1835 if (HCC_MAX_PSA(xhci->hcc_params) >= 4)
1836 xhci->shared_hcd->can_do_streams = 1;
1837
1838 err = usb_add_hcd(xhci->shared_hcd, tegra->xhci_irq, IRQF_SHARED);
1839 if (err < 0) {
1840 dev_err(&pdev->dev, "failed to add shared HCD: %d\n", err);
1841 goto put_usb3;
1842 }
1843
1844 err = devm_request_threaded_irq(&pdev->dev, tegra->mbox_irq,
1845 tegra_xusb_mbox_irq,
1846 tegra_xusb_mbox_thread, 0,
1847 dev_name(&pdev->dev), tegra);
1848 if (err < 0) {
1849 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
1850 goto remove_usb3;
1851 }
1852
1853 if (tegra->padctl_irq) {
1854 err = devm_request_threaded_irq(&pdev->dev, tegra->padctl_irq,
1855 NULL, tegra_xusb_padctl_irq,
1856 IRQF_ONESHOT, dev_name(&pdev->dev),
1857 tegra);
1858 if (err < 0) {
1859 dev_err(&pdev->dev, "failed to request padctl IRQ: %d\n", err);
1860 goto remove_usb3;
1861 }
1862 }
1863
1864 err = tegra_xusb_enable_firmware_messages(tegra);
1865 if (err < 0) {
1866 dev_err(&pdev->dev, "failed to enable messages: %d\n", err);
1867 goto remove_usb3;
1868 }
1869
1870 err = tegra_xusb_init_usb_phy(tegra);
1871 if (err < 0) {
1872 dev_err(&pdev->dev, "failed to init USB PHY: %d\n", err);
1873 goto remove_usb3;
1874 }
1875
1876 /* Enable wake for both USB 2.0 and USB 3.0 roothubs */
1877 device_init_wakeup(&tegra->hcd->self.root_hub->dev, true);
1878 device_init_wakeup(&xhci->shared_hcd->self.root_hub->dev, true);
1879
1880 pm_runtime_use_autosuspend(tegra->dev);
1881 pm_runtime_set_autosuspend_delay(tegra->dev, 2000);
1882 pm_runtime_mark_last_busy(tegra->dev);
1883 pm_runtime_set_active(tegra->dev);
1884
1885 if (tegra->padctl_irq) {
1886 device_init_wakeup(tegra->dev, true);
1887 pm_runtime_enable(tegra->dev);
1888 }
1889
1890 return 0;
1891
1892 remove_usb3:
1893 usb_remove_hcd(xhci->shared_hcd);
1894 put_usb3:
1895 usb_put_hcd(xhci->shared_hcd);
1896 remove_usb2:
1897 usb_remove_hcd(tegra->hcd);
1898 powergate:
1899 tegra_xusb_powergate_partitions(tegra);
1900 free_firmware:
1901 dma_free_coherent(&pdev->dev, tegra->fw.size, tegra->fw.virt,
1902 tegra->fw.phys);
1903 disable_phy:
1904 tegra_xusb_phy_disable(tegra);
1905 disable_regulator:
1906 regulator_bulk_disable(tegra->soc->num_supplies, tegra->supplies);
1907 disable_clk:
1908 tegra_xusb_clk_disable(tegra);
1909 put_hcd:
1910 usb_put_hcd(tegra->hcd);
1911 put_powerdomains:
1912 tegra_xusb_powerdomain_remove(&pdev->dev, tegra);
1913 put_padctl:
1914 of_node_put(np);
1915 tegra_xusb_padctl_put(tegra->padctl);
1916 return err;
1917 }
1918
tegra_xusb_disable(struct tegra_xusb * tegra)1919 static void tegra_xusb_disable(struct tegra_xusb *tegra)
1920 {
1921 tegra_xusb_powergate_partitions(tegra);
1922 tegra_xusb_powerdomain_remove(tegra->dev, tegra);
1923 tegra_xusb_phy_disable(tegra);
1924 tegra_xusb_clk_disable(tegra);
1925 regulator_bulk_disable(tegra->soc->num_supplies, tegra->supplies);
1926 }
1927
tegra_xusb_remove(struct platform_device * pdev)1928 static void tegra_xusb_remove(struct platform_device *pdev)
1929 {
1930 struct tegra_xusb *tegra = platform_get_drvdata(pdev);
1931 struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
1932
1933 tegra_xusb_deinit_usb_phy(tegra);
1934
1935 pm_runtime_get_sync(&pdev->dev);
1936 usb_remove_hcd(xhci->shared_hcd);
1937 usb_put_hcd(xhci->shared_hcd);
1938 xhci->shared_hcd = NULL;
1939 usb_remove_hcd(tegra->hcd);
1940 usb_put_hcd(tegra->hcd);
1941
1942 dma_free_coherent(&pdev->dev, tegra->fw.size, tegra->fw.virt,
1943 tegra->fw.phys);
1944
1945 if (tegra->padctl_irq)
1946 pm_runtime_disable(&pdev->dev);
1947
1948 pm_runtime_put(&pdev->dev);
1949
1950 tegra_xusb_disable(tegra);
1951 tegra_xusb_padctl_put(tegra->padctl);
1952 }
1953
tegra_xusb_shutdown(struct platform_device * pdev)1954 static void tegra_xusb_shutdown(struct platform_device *pdev)
1955 {
1956 struct tegra_xusb *tegra = platform_get_drvdata(pdev);
1957
1958 pm_runtime_get_sync(&pdev->dev);
1959 disable_irq(tegra->xhci_irq);
1960 xhci_shutdown(tegra->hcd);
1961 tegra_xusb_disable(tegra);
1962 }
1963
xhci_hub_ports_suspended(struct xhci_hub * hub)1964 static bool xhci_hub_ports_suspended(struct xhci_hub *hub)
1965 {
1966 struct device *dev = hub->hcd->self.controller;
1967 bool status = true;
1968 unsigned int i;
1969 u32 value;
1970
1971 for (i = 0; i < hub->num_ports; i++) {
1972 value = readl(hub->ports[i]->addr);
1973 if ((value & PORT_PE) == 0)
1974 continue;
1975
1976 if ((value & PORT_PLS_MASK) != XDEV_U3) {
1977 dev_info(dev, "%u-%u isn't suspended: %#010x\n",
1978 hub->hcd->self.busnum, i + 1, value);
1979 status = false;
1980 }
1981 }
1982
1983 return status;
1984 }
1985
tegra_xusb_check_ports(struct tegra_xusb * tegra)1986 static int tegra_xusb_check_ports(struct tegra_xusb *tegra)
1987 {
1988 struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
1989 struct xhci_bus_state *bus_state = &xhci->usb2_rhub.bus_state;
1990 unsigned long flags;
1991 int err = 0;
1992
1993 if (bus_state->bus_suspended) {
1994 /* xusb_hub_suspend() has just directed one or more USB2 port(s)
1995 * to U3 state, it takes 3ms to enter U3.
1996 */
1997 usleep_range(3000, 4000);
1998 }
1999
2000 spin_lock_irqsave(&xhci->lock, flags);
2001
2002 if (!xhci_hub_ports_suspended(&xhci->usb2_rhub) ||
2003 !xhci_hub_ports_suspended(&xhci->usb3_rhub))
2004 err = -EBUSY;
2005
2006 spin_unlock_irqrestore(&xhci->lock, flags);
2007
2008 return err;
2009 }
2010
tegra_xusb_save_context(struct tegra_xusb * tegra)2011 static void tegra_xusb_save_context(struct tegra_xusb *tegra)
2012 {
2013 const struct tegra_xusb_context_soc *soc = tegra->soc->context;
2014 struct tegra_xusb_context *ctx = &tegra->context;
2015 unsigned int i;
2016
2017 if (soc->ipfs.num_offsets > 0) {
2018 for (i = 0; i < soc->ipfs.num_offsets; i++)
2019 ctx->ipfs[i] = ipfs_readl(tegra, soc->ipfs.offsets[i]);
2020 }
2021
2022 if (soc->fpci.num_offsets > 0) {
2023 for (i = 0; i < soc->fpci.num_offsets; i++)
2024 ctx->fpci[i] = fpci_readl(tegra, soc->fpci.offsets[i]);
2025 }
2026 }
2027
tegra_xusb_restore_context(struct tegra_xusb * tegra)2028 static void tegra_xusb_restore_context(struct tegra_xusb *tegra)
2029 {
2030 const struct tegra_xusb_context_soc *soc = tegra->soc->context;
2031 struct tegra_xusb_context *ctx = &tegra->context;
2032 unsigned int i;
2033
2034 if (soc->fpci.num_offsets > 0) {
2035 for (i = 0; i < soc->fpci.num_offsets; i++)
2036 fpci_writel(tegra, ctx->fpci[i], soc->fpci.offsets[i]);
2037 }
2038
2039 if (soc->ipfs.num_offsets > 0) {
2040 for (i = 0; i < soc->ipfs.num_offsets; i++)
2041 ipfs_writel(tegra, ctx->ipfs[i], soc->ipfs.offsets[i]);
2042 }
2043 }
2044
tegra_xhci_portsc_to_speed(struct tegra_xusb * tegra,u32 portsc)2045 static enum usb_device_speed tegra_xhci_portsc_to_speed(struct tegra_xusb *tegra, u32 portsc)
2046 {
2047 if (DEV_LOWSPEED(portsc))
2048 return USB_SPEED_LOW;
2049
2050 if (DEV_HIGHSPEED(portsc))
2051 return USB_SPEED_HIGH;
2052
2053 if (DEV_FULLSPEED(portsc))
2054 return USB_SPEED_FULL;
2055
2056 if (DEV_SUPERSPEED_ANY(portsc))
2057 return USB_SPEED_SUPER;
2058
2059 return USB_SPEED_UNKNOWN;
2060 }
2061
tegra_xhci_enable_phy_sleepwalk_wake(struct tegra_xusb * tegra)2062 static void tegra_xhci_enable_phy_sleepwalk_wake(struct tegra_xusb *tegra)
2063 {
2064 struct tegra_xusb_padctl *padctl = tegra->padctl;
2065 struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
2066 enum usb_device_speed speed;
2067 struct phy *phy;
2068 unsigned int index, offset;
2069 unsigned int i, j, k;
2070 struct xhci_hub *rhub;
2071 u32 portsc;
2072
2073 for (i = 0, k = 0; i < tegra->soc->num_types; i++) {
2074 if (strcmp(tegra->soc->phy_types[i].name, "usb3") == 0)
2075 rhub = &xhci->usb3_rhub;
2076 else
2077 rhub = &xhci->usb2_rhub;
2078
2079 if (strcmp(tegra->soc->phy_types[i].name, "hsic") == 0)
2080 offset = tegra->soc->ports.usb2.count;
2081 else
2082 offset = 0;
2083
2084 for (j = 0; j < tegra->soc->phy_types[i].num; j++) {
2085 phy = tegra->phys[k++];
2086
2087 if (!phy)
2088 continue;
2089
2090 index = j + offset;
2091
2092 if (index >= rhub->num_ports)
2093 continue;
2094
2095 if (!is_host_mode_phy(tegra, i, j))
2096 continue;
2097
2098 portsc = readl(rhub->ports[index]->addr);
2099 speed = tegra_xhci_portsc_to_speed(tegra, portsc);
2100 tegra_xusb_padctl_enable_phy_sleepwalk(padctl, phy, speed);
2101 tegra_xusb_padctl_enable_phy_wake(padctl, phy);
2102 }
2103 }
2104 }
2105
tegra_xhci_disable_phy_wake(struct tegra_xusb * tegra)2106 static void tegra_xhci_disable_phy_wake(struct tegra_xusb *tegra)
2107 {
2108 struct tegra_xusb_padctl *padctl = tegra->padctl;
2109 unsigned int i;
2110
2111 for (i = 0; i < tegra->num_usb_phys; i++) {
2112 struct phy *phy = tegra_xusb_get_phy(tegra, "usb2", i);
2113
2114 if (!phy)
2115 continue;
2116
2117 if (tegra_xusb_padctl_remote_wake_detected(padctl, phy))
2118 tegra_phy_xusb_utmi_pad_power_on(phy);
2119 }
2120
2121 for (i = 0; i < tegra->num_phys; i++) {
2122 if (!tegra->phys[i])
2123 continue;
2124
2125 if (tegra_xusb_padctl_remote_wake_detected(padctl, tegra->phys[i]))
2126 dev_dbg(tegra->dev, "%pOF remote wake detected\n",
2127 tegra->phys[i]->dev.of_node);
2128
2129 tegra_xusb_padctl_disable_phy_wake(padctl, tegra->phys[i]);
2130 }
2131 }
2132
tegra_xhci_disable_phy_sleepwalk(struct tegra_xusb * tegra)2133 static void tegra_xhci_disable_phy_sleepwalk(struct tegra_xusb *tegra)
2134 {
2135 struct tegra_xusb_padctl *padctl = tegra->padctl;
2136 unsigned int i;
2137
2138 for (i = 0; i < tegra->num_phys; i++) {
2139 if (!tegra->phys[i])
2140 continue;
2141
2142 tegra_xusb_padctl_disable_phy_sleepwalk(padctl, tegra->phys[i]);
2143 }
2144 }
2145
tegra_xhci_program_utmi_power_lp0_exit(struct tegra_xusb * tegra)2146 static void tegra_xhci_program_utmi_power_lp0_exit(struct tegra_xusb *tegra)
2147 {
2148 unsigned int i, index_to_usb2;
2149 struct phy *phy;
2150
2151 for (i = 0; i < tegra->soc->num_types; i++) {
2152 if (strcmp(tegra->soc->phy_types[i].name, "usb2") == 0)
2153 index_to_usb2 = i;
2154 }
2155
2156 for (i = 0; i < tegra->num_usb_phys; i++) {
2157 if (!is_host_mode_phy(tegra, index_to_usb2, i))
2158 continue;
2159
2160 phy = tegra_xusb_get_phy(tegra, "usb2", i);
2161 if (tegra->lp0_utmi_pad_mask & BIT(i))
2162 tegra_phy_xusb_utmi_pad_power_on(phy);
2163 else
2164 tegra_phy_xusb_utmi_pad_power_down(phy);
2165 }
2166 }
2167
tegra_xusb_enter_elpg(struct tegra_xusb * tegra,bool is_auto_resume)2168 static int tegra_xusb_enter_elpg(struct tegra_xusb *tegra, bool is_auto_resume)
2169 {
2170 struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
2171 struct device *dev = tegra->dev;
2172 bool wakeup = is_auto_resume ? true : device_may_wakeup(dev);
2173 unsigned int i;
2174 int err;
2175 u32 usbcmd;
2176 u32 portsc;
2177
2178 dev_dbg(dev, "entering ELPG\n");
2179
2180 usbcmd = readl(&xhci->op_regs->command);
2181 usbcmd &= ~CMD_EIE;
2182 writel(usbcmd, &xhci->op_regs->command);
2183
2184 err = tegra_xusb_check_ports(tegra);
2185 if (err < 0) {
2186 dev_err(tegra->dev, "not all ports suspended: %d\n", err);
2187 goto out;
2188 }
2189
2190 for (i = 0; i < xhci->usb2_rhub.num_ports; i++) {
2191 if (!xhci->usb2_rhub.ports[i])
2192 continue;
2193 portsc = readl(xhci->usb2_rhub.ports[i]->addr);
2194 tegra->lp0_utmi_pad_mask &= ~BIT(i);
2195 if (((portsc & PORT_PLS_MASK) == XDEV_U3) || ((portsc & DEV_SPEED_MASK) == XDEV_FS))
2196 tegra->lp0_utmi_pad_mask |= BIT(i);
2197 }
2198
2199 err = xhci_suspend(xhci, wakeup);
2200 if (err < 0) {
2201 dev_err(tegra->dev, "failed to suspend XHCI: %d\n", err);
2202 goto out;
2203 }
2204
2205 tegra_xusb_save_context(tegra);
2206
2207 if (wakeup)
2208 tegra_xhci_enable_phy_sleepwalk_wake(tegra);
2209
2210 tegra_xusb_powergate_partitions(tegra);
2211
2212 for (i = 0; i < tegra->num_phys; i++) {
2213 if (!tegra->phys[i])
2214 continue;
2215
2216 phy_power_off(tegra->phys[i]);
2217 if (!wakeup)
2218 phy_exit(tegra->phys[i]);
2219 }
2220
2221 tegra_xusb_clk_disable(tegra);
2222
2223 out:
2224 if (!err)
2225 dev_dbg(tegra->dev, "entering ELPG done\n");
2226 else {
2227 usbcmd = readl(&xhci->op_regs->command);
2228 usbcmd |= CMD_EIE;
2229 writel(usbcmd, &xhci->op_regs->command);
2230
2231 dev_dbg(tegra->dev, "entering ELPG failed\n");
2232 pm_runtime_mark_last_busy(tegra->dev);
2233 }
2234
2235 return err;
2236 }
2237
tegra_xusb_exit_elpg(struct tegra_xusb * tegra,bool is_auto_resume)2238 static int tegra_xusb_exit_elpg(struct tegra_xusb *tegra, bool is_auto_resume)
2239 {
2240 struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
2241 struct device *dev = tegra->dev;
2242 bool wakeup = is_auto_resume ? true : device_may_wakeup(dev);
2243 unsigned int i;
2244 u32 usbcmd;
2245 int err;
2246
2247 dev_dbg(dev, "exiting ELPG\n");
2248 pm_runtime_mark_last_busy(tegra->dev);
2249
2250 err = tegra_xusb_clk_enable(tegra);
2251 if (err < 0) {
2252 dev_err(tegra->dev, "failed to enable clocks: %d\n", err);
2253 goto out;
2254 }
2255
2256 err = tegra_xusb_unpowergate_partitions(tegra);
2257 if (err)
2258 goto disable_clks;
2259
2260 if (wakeup)
2261 tegra_xhci_disable_phy_wake(tegra);
2262
2263 for (i = 0; i < tegra->num_phys; i++) {
2264 if (!tegra->phys[i])
2265 continue;
2266
2267 if (!wakeup)
2268 phy_init(tegra->phys[i]);
2269
2270 phy_power_on(tegra->phys[i]);
2271 }
2272 if (tegra->suspended)
2273 tegra_xhci_program_utmi_power_lp0_exit(tegra);
2274
2275 tegra_xusb_config(tegra);
2276 tegra_xusb_restore_context(tegra);
2277
2278 err = tegra_xusb_load_firmware(tegra);
2279 if (err < 0) {
2280 dev_err(tegra->dev, "failed to load firmware: %d\n", err);
2281 goto disable_phy;
2282 }
2283
2284 err = __tegra_xusb_enable_firmware_messages(tegra);
2285 if (err < 0) {
2286 dev_err(tegra->dev, "failed to enable messages: %d\n", err);
2287 goto disable_phy;
2288 }
2289
2290 if (wakeup)
2291 tegra_xhci_disable_phy_sleepwalk(tegra);
2292
2293 err = xhci_resume(xhci, false, is_auto_resume);
2294 if (err < 0) {
2295 dev_err(tegra->dev, "failed to resume XHCI: %d\n", err);
2296 goto disable_phy;
2297 }
2298
2299 usbcmd = readl(&xhci->op_regs->command);
2300 usbcmd |= CMD_EIE;
2301 writel(usbcmd, &xhci->op_regs->command);
2302
2303 goto out;
2304
2305 disable_phy:
2306 for (i = 0; i < tegra->num_phys; i++) {
2307 if (!tegra->phys[i])
2308 continue;
2309
2310 phy_power_off(tegra->phys[i]);
2311 if (!wakeup)
2312 phy_exit(tegra->phys[i]);
2313 }
2314 tegra_xusb_powergate_partitions(tegra);
2315 disable_clks:
2316 tegra_xusb_clk_disable(tegra);
2317 out:
2318 if (!err)
2319 dev_dbg(dev, "exiting ELPG done\n");
2320 else
2321 dev_dbg(dev, "exiting ELPG failed\n");
2322
2323 return err;
2324 }
2325
tegra_xusb_suspend(struct device * dev)2326 static __maybe_unused int tegra_xusb_suspend(struct device *dev)
2327 {
2328 struct tegra_xusb *tegra = dev_get_drvdata(dev);
2329 int err;
2330
2331 synchronize_irq(tegra->mbox_irq);
2332
2333 mutex_lock(&tegra->lock);
2334
2335 if (pm_runtime_suspended(dev)) {
2336 err = tegra_xusb_exit_elpg(tegra, true);
2337 if (err < 0)
2338 goto out;
2339 }
2340
2341 err = tegra_xusb_enter_elpg(tegra, false);
2342 if (err < 0) {
2343 if (pm_runtime_suspended(dev)) {
2344 pm_runtime_disable(dev);
2345 pm_runtime_set_active(dev);
2346 pm_runtime_enable(dev);
2347 }
2348
2349 goto out;
2350 }
2351
2352 out:
2353 if (!err) {
2354 tegra->suspended = true;
2355 pm_runtime_disable(dev);
2356
2357 if (device_may_wakeup(dev)) {
2358 if (enable_irq_wake(tegra->padctl_irq))
2359 dev_err(dev, "failed to enable padctl wakes\n");
2360 }
2361 }
2362
2363 mutex_unlock(&tegra->lock);
2364
2365 return err;
2366 }
2367
tegra_xusb_resume(struct device * dev)2368 static __maybe_unused int tegra_xusb_resume(struct device *dev)
2369 {
2370 struct tegra_xusb *tegra = dev_get_drvdata(dev);
2371 int err;
2372
2373 mutex_lock(&tegra->lock);
2374
2375 if (!tegra->suspended) {
2376 mutex_unlock(&tegra->lock);
2377 return 0;
2378 }
2379
2380 err = tegra_xusb_exit_elpg(tegra, false);
2381 if (err < 0) {
2382 mutex_unlock(&tegra->lock);
2383 return err;
2384 }
2385
2386 if (device_may_wakeup(dev)) {
2387 if (disable_irq_wake(tegra->padctl_irq))
2388 dev_err(dev, "failed to disable padctl wakes\n");
2389 }
2390 tegra->suspended = false;
2391 mutex_unlock(&tegra->lock);
2392
2393 pm_runtime_set_active(dev);
2394 pm_runtime_enable(dev);
2395
2396 return 0;
2397 }
2398
tegra_xusb_runtime_suspend(struct device * dev)2399 static __maybe_unused int tegra_xusb_runtime_suspend(struct device *dev)
2400 {
2401 struct tegra_xusb *tegra = dev_get_drvdata(dev);
2402 int ret;
2403
2404 synchronize_irq(tegra->mbox_irq);
2405 mutex_lock(&tegra->lock);
2406 ret = tegra_xusb_enter_elpg(tegra, true);
2407 mutex_unlock(&tegra->lock);
2408
2409 return ret;
2410 }
2411
tegra_xusb_runtime_resume(struct device * dev)2412 static __maybe_unused int tegra_xusb_runtime_resume(struct device *dev)
2413 {
2414 struct tegra_xusb *tegra = dev_get_drvdata(dev);
2415 int err;
2416
2417 mutex_lock(&tegra->lock);
2418 err = tegra_xusb_exit_elpg(tegra, true);
2419 mutex_unlock(&tegra->lock);
2420
2421 return err;
2422 }
2423
2424 static const struct dev_pm_ops tegra_xusb_pm_ops = {
2425 SET_RUNTIME_PM_OPS(tegra_xusb_runtime_suspend,
2426 tegra_xusb_runtime_resume, NULL)
2427 SET_SYSTEM_SLEEP_PM_OPS(tegra_xusb_suspend, tegra_xusb_resume)
2428 };
2429
2430 static const char * const tegra124_supply_names[] = {
2431 "avddio-pex",
2432 "dvddio-pex",
2433 "avdd-usb",
2434 "hvdd-usb-ss",
2435 };
2436
2437 static const struct tegra_xusb_phy_type tegra124_phy_types[] = {
2438 { .name = "usb3", .num = 2, },
2439 { .name = "usb2", .num = 3, },
2440 { .name = "hsic", .num = 2, },
2441 };
2442
2443 static const unsigned int tegra124_xusb_context_ipfs[] = {
2444 IPFS_XUSB_HOST_MSI_BAR_SZ_0,
2445 IPFS_XUSB_HOST_MSI_AXI_BAR_ST_0,
2446 IPFS_XUSB_HOST_MSI_FPCI_BAR_ST_0,
2447 IPFS_XUSB_HOST_MSI_VEC0_0,
2448 IPFS_XUSB_HOST_MSI_EN_VEC0_0,
2449 IPFS_XUSB_HOST_FPCI_ERROR_MASKS_0,
2450 IPFS_XUSB_HOST_INTR_MASK_0,
2451 IPFS_XUSB_HOST_INTR_ENABLE_0,
2452 IPFS_XUSB_HOST_UFPCI_CONFIG_0,
2453 IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0,
2454 IPFS_XUSB_HOST_MCCIF_FIFOCTRL_0,
2455 };
2456
2457 static const unsigned int tegra124_xusb_context_fpci[] = {
2458 XUSB_CFG_ARU_CONTEXT_HS_PLS,
2459 XUSB_CFG_ARU_CONTEXT_FS_PLS,
2460 XUSB_CFG_ARU_CONTEXT_HSFS_SPEED,
2461 XUSB_CFG_ARU_CONTEXT_HSFS_PP,
2462 XUSB_CFG_ARU_CONTEXT,
2463 XUSB_CFG_AXI_CFG,
2464 XUSB_CFG_24,
2465 XUSB_CFG_16,
2466 };
2467
2468 static const struct tegra_xusb_context_soc tegra124_xusb_context = {
2469 .ipfs = {
2470 .num_offsets = ARRAY_SIZE(tegra124_xusb_context_ipfs),
2471 .offsets = tegra124_xusb_context_ipfs,
2472 },
2473 .fpci = {
2474 .num_offsets = ARRAY_SIZE(tegra124_xusb_context_fpci),
2475 .offsets = tegra124_xusb_context_fpci,
2476 },
2477 };
2478
2479 static const struct tegra_xusb_soc_ops tegra124_ops = {
2480 .mbox_reg_readl = &fpci_readl,
2481 .mbox_reg_writel = &fpci_writel,
2482 .csb_reg_readl = &fpci_csb_readl,
2483 .csb_reg_writel = &fpci_csb_writel,
2484 };
2485
2486 static const struct tegra_xusb_soc tegra124_soc = {
2487 .firmware = "nvidia/tegra124/xusb.bin",
2488 .supply_names = tegra124_supply_names,
2489 .num_supplies = ARRAY_SIZE(tegra124_supply_names),
2490 .phy_types = tegra124_phy_types,
2491 .num_types = ARRAY_SIZE(tegra124_phy_types),
2492 .context = &tegra124_xusb_context,
2493 .ports = {
2494 .usb2 = { .offset = 4, .count = 4, },
2495 .hsic = { .offset = 6, .count = 2, },
2496 .usb3 = { .offset = 0, .count = 2, },
2497 },
2498 .scale_ss_clock = true,
2499 .has_ipfs = true,
2500 .otg_reset_sspi = false,
2501 .ops = &tegra124_ops,
2502 .mbox = {
2503 .cmd = 0xe4,
2504 .data_in = 0xe8,
2505 .data_out = 0xec,
2506 .owner = 0xf0,
2507 .smi_intr = XUSB_CFG_ARU_SMI_INTR,
2508 },
2509 };
2510 MODULE_FIRMWARE("nvidia/tegra124/xusb.bin");
2511
2512 static const char * const tegra210_supply_names[] = {
2513 "dvddio-pex",
2514 "hvddio-pex",
2515 "avdd-usb",
2516 };
2517
2518 static const struct tegra_xusb_phy_type tegra210_phy_types[] = {
2519 { .name = "usb3", .num = 4, },
2520 { .name = "usb2", .num = 4, },
2521 { .name = "hsic", .num = 1, },
2522 };
2523
2524 static const struct tegra_xusb_soc tegra210_soc = {
2525 .firmware = "nvidia/tegra210/xusb.bin",
2526 .supply_names = tegra210_supply_names,
2527 .num_supplies = ARRAY_SIZE(tegra210_supply_names),
2528 .phy_types = tegra210_phy_types,
2529 .num_types = ARRAY_SIZE(tegra210_phy_types),
2530 .context = &tegra124_xusb_context,
2531 .ports = {
2532 .usb2 = { .offset = 4, .count = 4, },
2533 .hsic = { .offset = 8, .count = 1, },
2534 .usb3 = { .offset = 0, .count = 4, },
2535 },
2536 .scale_ss_clock = false,
2537 .has_ipfs = true,
2538 .otg_reset_sspi = true,
2539 .ops = &tegra124_ops,
2540 .mbox = {
2541 .cmd = 0xe4,
2542 .data_in = 0xe8,
2543 .data_out = 0xec,
2544 .owner = 0xf0,
2545 .smi_intr = XUSB_CFG_ARU_SMI_INTR,
2546 },
2547 };
2548 MODULE_FIRMWARE("nvidia/tegra210/xusb.bin");
2549
2550 static const char * const tegra186_supply_names[] = {
2551 };
2552 MODULE_FIRMWARE("nvidia/tegra186/xusb.bin");
2553
2554 static const struct tegra_xusb_phy_type tegra186_phy_types[] = {
2555 { .name = "usb3", .num = 3, },
2556 { .name = "usb2", .num = 3, },
2557 { .name = "hsic", .num = 1, },
2558 };
2559
2560 static const struct tegra_xusb_context_soc tegra186_xusb_context = {
2561 .fpci = {
2562 .num_offsets = ARRAY_SIZE(tegra124_xusb_context_fpci),
2563 .offsets = tegra124_xusb_context_fpci,
2564 },
2565 };
2566
2567 static const struct tegra_xusb_soc tegra186_soc = {
2568 .firmware = "nvidia/tegra186/xusb.bin",
2569 .supply_names = tegra186_supply_names,
2570 .num_supplies = ARRAY_SIZE(tegra186_supply_names),
2571 .phy_types = tegra186_phy_types,
2572 .num_types = ARRAY_SIZE(tegra186_phy_types),
2573 .context = &tegra186_xusb_context,
2574 .ports = {
2575 .usb3 = { .offset = 0, .count = 3, },
2576 .usb2 = { .offset = 3, .count = 3, },
2577 .hsic = { .offset = 6, .count = 1, },
2578 },
2579 .scale_ss_clock = false,
2580 .has_ipfs = false,
2581 .otg_reset_sspi = false,
2582 .ops = &tegra124_ops,
2583 .mbox = {
2584 .cmd = 0xe4,
2585 .data_in = 0xe8,
2586 .data_out = 0xec,
2587 .owner = 0xf0,
2588 .smi_intr = XUSB_CFG_ARU_SMI_INTR,
2589 },
2590 .lpm_support = true,
2591 };
2592
2593 static const char * const tegra194_supply_names[] = {
2594 };
2595
2596 static const struct tegra_xusb_phy_type tegra194_phy_types[] = {
2597 { .name = "usb3", .num = 4, },
2598 { .name = "usb2", .num = 4, },
2599 };
2600
2601 static const struct tegra_xusb_soc tegra194_soc = {
2602 .firmware = "nvidia/tegra194/xusb.bin",
2603 .supply_names = tegra194_supply_names,
2604 .num_supplies = ARRAY_SIZE(tegra194_supply_names),
2605 .phy_types = tegra194_phy_types,
2606 .num_types = ARRAY_SIZE(tegra194_phy_types),
2607 .context = &tegra186_xusb_context,
2608 .ports = {
2609 .usb3 = { .offset = 0, .count = 4, },
2610 .usb2 = { .offset = 4, .count = 4, },
2611 },
2612 .scale_ss_clock = false,
2613 .has_ipfs = false,
2614 .otg_reset_sspi = false,
2615 .ops = &tegra124_ops,
2616 .mbox = {
2617 .cmd = 0x68,
2618 .data_in = 0x6c,
2619 .data_out = 0x70,
2620 .owner = 0x74,
2621 .smi_intr = XUSB_CFG_ARU_SMI_INTR,
2622 },
2623 .lpm_support = true,
2624 };
2625 MODULE_FIRMWARE("nvidia/tegra194/xusb.bin");
2626
2627 static const struct tegra_xusb_soc_ops tegra234_ops = {
2628 .mbox_reg_readl = &bar2_readl,
2629 .mbox_reg_writel = &bar2_writel,
2630 .csb_reg_readl = &bar2_csb_readl,
2631 .csb_reg_writel = &bar2_csb_writel,
2632 };
2633
2634 static const struct tegra_xusb_soc tegra234_soc = {
2635 .supply_names = tegra194_supply_names,
2636 .num_supplies = ARRAY_SIZE(tegra194_supply_names),
2637 .phy_types = tegra194_phy_types,
2638 .num_types = ARRAY_SIZE(tegra194_phy_types),
2639 .context = &tegra186_xusb_context,
2640 .ports = {
2641 .usb3 = { .offset = 0, .count = 4, },
2642 .usb2 = { .offset = 4, .count = 4, },
2643 },
2644 .scale_ss_clock = false,
2645 .has_ipfs = false,
2646 .otg_reset_sspi = false,
2647 .ops = &tegra234_ops,
2648 .mbox = {
2649 .cmd = XUSB_BAR2_ARU_MBOX_CMD,
2650 .data_in = XUSB_BAR2_ARU_MBOX_DATA_IN,
2651 .data_out = XUSB_BAR2_ARU_MBOX_DATA_OUT,
2652 .owner = XUSB_BAR2_ARU_MBOX_OWNER,
2653 .smi_intr = XUSB_BAR2_ARU_SMI_INTR,
2654 },
2655 .lpm_support = true,
2656 .has_bar2 = true,
2657 };
2658
2659 static const struct of_device_id tegra_xusb_of_match[] = {
2660 { .compatible = "nvidia,tegra124-xusb", .data = &tegra124_soc },
2661 { .compatible = "nvidia,tegra210-xusb", .data = &tegra210_soc },
2662 { .compatible = "nvidia,tegra186-xusb", .data = &tegra186_soc },
2663 { .compatible = "nvidia,tegra194-xusb", .data = &tegra194_soc },
2664 { .compatible = "nvidia,tegra234-xusb", .data = &tegra234_soc },
2665 { },
2666 };
2667 MODULE_DEVICE_TABLE(of, tegra_xusb_of_match);
2668
2669 static struct platform_driver tegra_xusb_driver = {
2670 .probe = tegra_xusb_probe,
2671 .remove = tegra_xusb_remove,
2672 .shutdown = tegra_xusb_shutdown,
2673 .driver = {
2674 .name = "tegra-xusb",
2675 .pm = &tegra_xusb_pm_ops,
2676 .of_match_table = tegra_xusb_of_match,
2677 },
2678 };
2679
tegra_xhci_quirks(struct device * dev,struct xhci_hcd * xhci)2680 static void tegra_xhci_quirks(struct device *dev, struct xhci_hcd *xhci)
2681 {
2682 struct tegra_xusb *tegra = dev_get_drvdata(dev);
2683
2684 if (tegra && tegra->soc->lpm_support)
2685 xhci->quirks |= XHCI_LPM_SUPPORT;
2686 }
2687
tegra_xhci_setup(struct usb_hcd * hcd)2688 static int tegra_xhci_setup(struct usb_hcd *hcd)
2689 {
2690 return xhci_gen_setup(hcd, tegra_xhci_quirks);
2691 }
2692
tegra_xhci_hub_control(struct usb_hcd * hcd,u16 type_req,u16 value,u16 index,char * buf,u16 length)2693 static int tegra_xhci_hub_control(struct usb_hcd *hcd, u16 type_req, u16 value, u16 index,
2694 char *buf, u16 length)
2695 {
2696 struct tegra_xusb *tegra = dev_get_drvdata(hcd->self.controller);
2697 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2698 struct xhci_hub *rhub;
2699 struct xhci_bus_state *bus_state;
2700 int port = (index & 0xff) - 1;
2701 unsigned int i;
2702 struct xhci_port **ports;
2703 u32 portsc;
2704 int ret;
2705 struct phy *phy;
2706
2707 rhub = &xhci->usb2_rhub;
2708 bus_state = &rhub->bus_state;
2709 if (bus_state->resuming_ports && hcd->speed == HCD_USB2) {
2710 ports = rhub->ports;
2711 i = rhub->num_ports;
2712 while (i--) {
2713 if (!test_bit(i, &bus_state->resuming_ports))
2714 continue;
2715 portsc = readl(ports[i]->addr);
2716 if ((portsc & PORT_PLS_MASK) == XDEV_RESUME)
2717 tegra_phy_xusb_utmi_pad_power_on(
2718 tegra_xusb_get_phy(tegra, "usb2", (int) i));
2719 }
2720 }
2721
2722 if (hcd->speed == HCD_USB2) {
2723 phy = tegra_xusb_get_phy(tegra, "usb2", port);
2724 if ((type_req == ClearPortFeature) && (value == USB_PORT_FEAT_SUSPEND)) {
2725 if (!index || index > rhub->num_ports)
2726 return -EPIPE;
2727 tegra_phy_xusb_utmi_pad_power_on(phy);
2728 }
2729 if ((type_req == SetPortFeature) && (value == USB_PORT_FEAT_RESET)) {
2730 if (!index || index > rhub->num_ports)
2731 return -EPIPE;
2732 ports = rhub->ports;
2733 portsc = readl(ports[port]->addr);
2734 if (portsc & PORT_CONNECT)
2735 tegra_phy_xusb_utmi_pad_power_on(phy);
2736 }
2737 }
2738
2739 ret = xhci_hub_control(hcd, type_req, value, index, buf, length);
2740 if (ret < 0)
2741 return ret;
2742
2743 if (hcd->speed == HCD_USB2) {
2744 /* Use phy where we set previously */
2745 if ((type_req == SetPortFeature) && (value == USB_PORT_FEAT_SUSPEND))
2746 /* We don't suspend the PAD while HNP role swap happens on the OTG port */
2747 if (!((hcd->self.otg_port == (port + 1)) && hcd->self.b_hnp_enable))
2748 tegra_phy_xusb_utmi_pad_power_down(phy);
2749
2750 if ((type_req == ClearPortFeature) && (value == USB_PORT_FEAT_C_CONNECTION)) {
2751 ports = rhub->ports;
2752 portsc = readl(ports[port]->addr);
2753 if (!(portsc & PORT_CONNECT)) {
2754 /* We don't suspend the PAD while HNP role swap happens on the OTG
2755 * port
2756 */
2757 if (!((hcd->self.otg_port == (port + 1)) && hcd->self.b_hnp_enable))
2758 tegra_phy_xusb_utmi_pad_power_down(phy);
2759 }
2760 }
2761 if ((type_req == SetPortFeature) && (value == USB_PORT_FEAT_TEST))
2762 tegra_phy_xusb_utmi_pad_power_on(phy);
2763 }
2764
2765 return ret;
2766 }
2767
2768 static const struct xhci_driver_overrides tegra_xhci_overrides __initconst = {
2769 .reset = tegra_xhci_setup,
2770 .hub_control = tegra_xhci_hub_control,
2771 };
2772
tegra_xusb_init(void)2773 static int __init tegra_xusb_init(void)
2774 {
2775 xhci_init_driver(&tegra_xhci_hc_driver, &tegra_xhci_overrides);
2776
2777 return platform_driver_register(&tegra_xusb_driver);
2778 }
2779 module_init(tegra_xusb_init);
2780
tegra_xusb_exit(void)2781 static void __exit tegra_xusb_exit(void)
2782 {
2783 platform_driver_unregister(&tegra_xusb_driver);
2784 }
2785 module_exit(tegra_xusb_exit);
2786
2787 MODULE_AUTHOR("Andrew Bresticker <abrestic@chromium.org>");
2788 MODULE_DESCRIPTION("NVIDIA Tegra XUSB xHCI host-controller driver");
2789 MODULE_LICENSE("GPL v2");
2790