1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2019-2020 Realtek Corporation
3 */
4
5 #ifndef __RTW89_CORE_H__
6 #define __RTW89_CORE_H__
7
8 #include <linux/average.h>
9 #include <linux/bitfield.h>
10 #include <linux/dmi.h>
11 #include <linux/firmware.h>
12 #include <linux/iopoll.h>
13 #include <linux/workqueue.h>
14 #include <net/mac80211.h>
15 #if defined(__FreeBSD__)
16 #include <linux/seq_file.h>
17 #include <linux/lockdep.h>
18 #include <linux/interrupt.h>
19 #include <linux/pm.h>
20 #endif
21
22 struct rtw89_dev;
23 struct rtw89_pci_info;
24 struct rtw89_mac_gen_def;
25 struct rtw89_phy_gen_def;
26 struct rtw89_fw_blacklist;
27 struct rtw89_efuse_block_cfg;
28 struct rtw89_h2c_rf_tssi;
29 struct rtw89_fw_txpwr_track_cfg;
30 struct rtw89_phy_rfk_log_fmt;
31 struct rtw89_debugfs;
32 struct rtw89_regd_data;
33
34 extern const struct ieee80211_ops rtw89_ops;
35
36 #define MASKBYTE0 0xff
37 #define MASKBYTE1 0xff00
38 #define MASKBYTE2 0xff0000
39 #define MASKBYTE3 0xff000000
40 #define MASKBYTE4 0xff00000000ULL
41 #define MASKHWORD 0xffff0000
42 #define MASKLWORD 0x0000ffff
43 #define MASKDWORD 0xffffffff
44 #define RFREG_MASK 0xfffff
45 #define INV_RF_DATA 0xffffffff
46 #define BYPASS_CR_DATA 0xbabecafe
47
48 #define RTW89_TRACK_WORK_PERIOD round_jiffies_relative(HZ * 2)
49 #define RTW89_TRACK_PS_WORK_PERIOD msecs_to_jiffies(100)
50 #define RTW89_FORBID_BA_TIMER round_jiffies_relative(HZ * 4)
51 #define CFO_TRACK_MAX_USER 64
52 #define MAX_RSSI 110
53 #define RSSI_FACTOR 1
54 #define RTW89_RSSI_RAW_TO_DBM(rssi) ((s8)((rssi) >> RSSI_FACTOR) - MAX_RSSI)
55 #define RTW89_TX_DIV_RSSI_RAW_TH (2 << RSSI_FACTOR)
56 #define DELTA_SWINGIDX_SIZE 30
57
58 #define RTW89_RADIOTAP_ROOM_HE sizeof(struct ieee80211_radiotap_he)
59 #define RTW89_RADIOTAP_ROOM_EHT \
60 (sizeof(struct ieee80211_radiotap_tlv) + \
61 ALIGN(struct_size((struct ieee80211_radiotap_eht *)0, user_info, 1), 4) + \
62 sizeof(struct ieee80211_radiotap_tlv) + \
63 ALIGN(sizeof(struct ieee80211_radiotap_eht_usig), 4))
64 #define RTW89_RADIOTAP_ROOM \
65 ALIGN(max(RTW89_RADIOTAP_ROOM_HE, RTW89_RADIOTAP_ROOM_EHT), 64)
66
67 #define RTW89_HTC_MASK_VARIANT GENMASK(1, 0)
68 #define RTW89_HTC_VARIANT_HE 3
69 #define RTW89_HTC_MASK_CTL_ID GENMASK(5, 2)
70 #define RTW89_HTC_VARIANT_HE_CID_OM 1
71 #define RTW89_HTC_VARIANT_HE_CID_CAS 6
72 #define RTW89_HTC_MASK_CTL_INFO GENMASK(31, 6)
73
74 #define RTW89_HTC_MASK_HTC_OM_RX_NSS GENMASK(8, 6)
75 enum htc_om_channel_width {
76 HTC_OM_CHANNEL_WIDTH_20 = 0,
77 HTC_OM_CHANNEL_WIDTH_40 = 1,
78 HTC_OM_CHANNEL_WIDTH_80 = 2,
79 HTC_OM_CHANNEL_WIDTH_160_OR_80_80 = 3,
80 };
81 #define RTW89_HTC_MASK_HTC_OM_CH_WIDTH GENMASK(10, 9)
82 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DIS BIT(11)
83 #define RTW89_HTC_MASK_HTC_OM_TX_NSTS GENMASK(14, 12)
84 #define RTW89_HTC_MASK_HTC_OM_ER_SU_DIS BIT(15)
85 #define RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR BIT(16)
86 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS BIT(17)
87
88 #define RTW89_TF_PAD GENMASK(11, 0)
89 #define RTW89_TF_BASIC_USER_INFO_SZ 6
90
91 #define RTW89_GET_TF_USER_INFO_AID12(data) \
92 le32_get_bits(*((const __le32 *)(data)), GENMASK(11, 0))
93 #define RTW89_GET_TF_USER_INFO_RUA(data) \
94 le32_get_bits(*((const __le32 *)(data)), GENMASK(19, 12))
95 #define RTW89_GET_TF_USER_INFO_UL_MCS(data) \
96 le32_get_bits(*((const __le32 *)(data)), GENMASK(24, 21))
97
98 enum rtw89_subband {
99 RTW89_CH_2G = 0,
100 RTW89_CH_5G_BAND_1 = 1,
101 /* RTW89_CH_5G_BAND_2 = 2, unused */
102 RTW89_CH_5G_BAND_3 = 3,
103 RTW89_CH_5G_BAND_4 = 4,
104
105 RTW89_CH_6G_BAND_IDX0, /* Low */
106 RTW89_CH_6G_BAND_IDX1, /* Low */
107 RTW89_CH_6G_BAND_IDX2, /* Mid */
108 RTW89_CH_6G_BAND_IDX3, /* Mid */
109 RTW89_CH_6G_BAND_IDX4, /* High */
110 RTW89_CH_6G_BAND_IDX5, /* High */
111 RTW89_CH_6G_BAND_IDX6, /* Ultra-high */
112 RTW89_CH_6G_BAND_IDX7, /* Ultra-high */
113
114 RTW89_SUBBAND_NR,
115 RTW89_SUBBAND_2GHZ_5GHZ_NR = RTW89_CH_5G_BAND_4 + 1,
116 };
117
118 enum rtw89_gain_offset {
119 RTW89_GAIN_OFFSET_2G_CCK,
120 RTW89_GAIN_OFFSET_2G_OFDM,
121 RTW89_GAIN_OFFSET_5G_LOW,
122 RTW89_GAIN_OFFSET_5G_MID,
123 RTW89_GAIN_OFFSET_5G_HIGH,
124 RTW89_GAIN_OFFSET_6G_L0,
125 RTW89_GAIN_OFFSET_6G_L1,
126 RTW89_GAIN_OFFSET_6G_M0,
127 RTW89_GAIN_OFFSET_6G_M1,
128 RTW89_GAIN_OFFSET_6G_H0,
129 RTW89_GAIN_OFFSET_6G_H1,
130 RTW89_GAIN_OFFSET_6G_UH0,
131 RTW89_GAIN_OFFSET_6G_UH1,
132
133 RTW89_GAIN_OFFSET_NR,
134 };
135
136 enum rtw89_hci_type {
137 RTW89_HCI_TYPE_PCIE,
138 RTW89_HCI_TYPE_USB,
139 RTW89_HCI_TYPE_SDIO,
140
141 RTW89_HCI_TYPE_NUM,
142 };
143
144 enum rtw89_hci_dle_type {
145 RTW89_HCI_DLE_TYPE_PCIE,
146 RTW89_HCI_DLE_TYPE_USB2,
147 RTW89_HCI_DLE_TYPE_USB3,
148 RTW89_HCI_DLE_TYPE_SDIO,
149
150 RTW89_HCI_DLE_TYPE_NUM,
151 };
152
153 enum rtw89_core_chip_id {
154 RTL8852A,
155 RTL8852B,
156 RTL8852BT,
157 RTL8852C,
158 RTL8851B,
159 RTL8922A,
160 };
161
162 enum rtw89_chip_gen {
163 RTW89_CHIP_AX,
164 RTW89_CHIP_BE,
165
166 RTW89_CHIP_GEN_NUM,
167 };
168
169 enum rtw89_cv {
170 CHIP_CAV,
171 CHIP_CBV,
172 CHIP_CCV,
173 CHIP_CDV,
174 CHIP_CEV,
175 CHIP_CFV,
176 CHIP_CV_MAX,
177 CHIP_CV_INVALID = CHIP_CV_MAX,
178 };
179
180 enum rtw89_bacam_ver {
181 RTW89_BACAM_V0,
182 RTW89_BACAM_V1,
183
184 RTW89_BACAM_V0_EXT = 99,
185 };
186
187 enum rtw89_core_tx_type {
188 RTW89_CORE_TX_TYPE_DATA,
189 RTW89_CORE_TX_TYPE_MGMT,
190 RTW89_CORE_TX_TYPE_FWCMD,
191 };
192
193 enum rtw89_core_rx_type {
194 RTW89_CORE_RX_TYPE_WIFI = 0,
195 RTW89_CORE_RX_TYPE_PPDU_STAT = 1,
196 RTW89_CORE_RX_TYPE_CHAN_INFO = 2,
197 RTW89_CORE_RX_TYPE_BB_SCOPE = 3,
198 RTW89_CORE_RX_TYPE_F2P_TXCMD = 4,
199 RTW89_CORE_RX_TYPE_SS2FW = 5,
200 RTW89_CORE_RX_TYPE_TX_REPORT = 6,
201 RTW89_CORE_RX_TYPE_TX_REL_HOST = 7,
202 RTW89_CORE_RX_TYPE_DFS_REPORT = 8,
203 RTW89_CORE_RX_TYPE_TX_REL_CPU = 9,
204 RTW89_CORE_RX_TYPE_C2H = 10,
205 RTW89_CORE_RX_TYPE_CSI = 11,
206 RTW89_CORE_RX_TYPE_CQI = 12,
207 RTW89_CORE_RX_TYPE_H2C = 13,
208 RTW89_CORE_RX_TYPE_FWDL = 14,
209 };
210
211 enum rtw89_txq_flags {
212 RTW89_TXQ_F_AMPDU = 0,
213 RTW89_TXQ_F_BLOCK_BA = 1,
214 RTW89_TXQ_F_FORBID_BA = 2,
215 };
216
217 enum rtw89_net_type {
218 RTW89_NET_TYPE_NO_LINK = 0,
219 RTW89_NET_TYPE_AD_HOC = 1,
220 RTW89_NET_TYPE_INFRA = 2,
221 RTW89_NET_TYPE_AP_MODE = 3,
222 };
223
224 enum rtw89_wifi_role {
225 RTW89_WIFI_ROLE_NONE,
226 RTW89_WIFI_ROLE_STATION,
227 RTW89_WIFI_ROLE_AP,
228 RTW89_WIFI_ROLE_AP_VLAN,
229 RTW89_WIFI_ROLE_ADHOC,
230 RTW89_WIFI_ROLE_ADHOC_MASTER,
231 RTW89_WIFI_ROLE_MESH_POINT,
232 RTW89_WIFI_ROLE_MONITOR,
233 RTW89_WIFI_ROLE_P2P_DEVICE,
234 RTW89_WIFI_ROLE_P2P_CLIENT,
235 RTW89_WIFI_ROLE_P2P_GO,
236 RTW89_WIFI_ROLE_NAN,
237 RTW89_WIFI_ROLE_MLME_MAX
238 };
239
240 enum rtw89_upd_mode {
241 RTW89_ROLE_CREATE,
242 RTW89_ROLE_REMOVE,
243 RTW89_ROLE_TYPE_CHANGE,
244 RTW89_ROLE_INFO_CHANGE,
245 RTW89_ROLE_CON_DISCONN,
246 RTW89_ROLE_BAND_SW,
247 RTW89_ROLE_FW_RESTORE,
248 };
249
250 enum rtw89_self_role {
251 RTW89_SELF_ROLE_CLIENT,
252 RTW89_SELF_ROLE_AP,
253 RTW89_SELF_ROLE_AP_CLIENT
254 };
255
256 enum rtw89_msk_sO_el {
257 RTW89_NO_MSK,
258 RTW89_SMA,
259 RTW89_TMA,
260 RTW89_BSSID
261 };
262
263 enum rtw89_sch_tx_sel {
264 RTW89_SCH_TX_SEL_ALL,
265 RTW89_SCH_TX_SEL_HIQ,
266 RTW89_SCH_TX_SEL_MG0,
267 RTW89_SCH_TX_SEL_MACID,
268 };
269
270 /* RTW89_ADDR_CAM_SEC_NONE : not enabled
271 * RTW89_ADDR_CAM_SEC_ALL_UNI : 0 - 6 unicast
272 * RTW89_ADDR_CAM_SEC_NORMAL : 0 - 1 unicast, 2 - 4 group, 5 - 6 BIP
273 * RTW89_ADDR_CAM_SEC_4GROUP : 0 - 1 unicast, 2 - 5 group, 6 BIP
274 */
275 enum rtw89_add_cam_sec_mode {
276 RTW89_ADDR_CAM_SEC_NONE = 0,
277 RTW89_ADDR_CAM_SEC_ALL_UNI = 1,
278 RTW89_ADDR_CAM_SEC_NORMAL = 2,
279 RTW89_ADDR_CAM_SEC_4GROUP = 3,
280 };
281
282 enum rtw89_sec_key_type {
283 RTW89_SEC_KEY_TYPE_NONE = 0,
284 RTW89_SEC_KEY_TYPE_WEP40 = 1,
285 RTW89_SEC_KEY_TYPE_WEP104 = 2,
286 RTW89_SEC_KEY_TYPE_TKIP = 3,
287 RTW89_SEC_KEY_TYPE_WAPI = 4,
288 RTW89_SEC_KEY_TYPE_GCMSMS4 = 5,
289 RTW89_SEC_KEY_TYPE_CCMP128 = 6,
290 RTW89_SEC_KEY_TYPE_CCMP256 = 7,
291 RTW89_SEC_KEY_TYPE_GCMP128 = 8,
292 RTW89_SEC_KEY_TYPE_GCMP256 = 9,
293 RTW89_SEC_KEY_TYPE_BIP_CCMP128 = 10,
294 };
295
296 enum rtw89_port {
297 RTW89_PORT_0 = 0,
298 RTW89_PORT_1 = 1,
299 RTW89_PORT_2 = 2,
300 RTW89_PORT_3 = 3,
301 RTW89_PORT_4 = 4,
302 RTW89_PORT_NUM
303 };
304
305 enum rtw89_band {
306 RTW89_BAND_2G = 0,
307 RTW89_BAND_5G = 1,
308 RTW89_BAND_6G = 2,
309 RTW89_BAND_NUM,
310 };
311
312 enum rtw89_hw_rate {
313 RTW89_HW_RATE_CCK1 = 0x0,
314 RTW89_HW_RATE_CCK2 = 0x1,
315 RTW89_HW_RATE_CCK5_5 = 0x2,
316 RTW89_HW_RATE_CCK11 = 0x3,
317 RTW89_HW_RATE_OFDM6 = 0x4,
318 RTW89_HW_RATE_OFDM9 = 0x5,
319 RTW89_HW_RATE_OFDM12 = 0x6,
320 RTW89_HW_RATE_OFDM18 = 0x7,
321 RTW89_HW_RATE_OFDM24 = 0x8,
322 RTW89_HW_RATE_OFDM36 = 0x9,
323 RTW89_HW_RATE_OFDM48 = 0xA,
324 RTW89_HW_RATE_OFDM54 = 0xB,
325 RTW89_HW_RATE_MCS0 = 0x80,
326 RTW89_HW_RATE_MCS1 = 0x81,
327 RTW89_HW_RATE_MCS2 = 0x82,
328 RTW89_HW_RATE_MCS3 = 0x83,
329 RTW89_HW_RATE_MCS4 = 0x84,
330 RTW89_HW_RATE_MCS5 = 0x85,
331 RTW89_HW_RATE_MCS6 = 0x86,
332 RTW89_HW_RATE_MCS7 = 0x87,
333 RTW89_HW_RATE_MCS8 = 0x88,
334 RTW89_HW_RATE_MCS9 = 0x89,
335 RTW89_HW_RATE_MCS10 = 0x8A,
336 RTW89_HW_RATE_MCS11 = 0x8B,
337 RTW89_HW_RATE_MCS12 = 0x8C,
338 RTW89_HW_RATE_MCS13 = 0x8D,
339 RTW89_HW_RATE_MCS14 = 0x8E,
340 RTW89_HW_RATE_MCS15 = 0x8F,
341 RTW89_HW_RATE_MCS16 = 0x90,
342 RTW89_HW_RATE_MCS17 = 0x91,
343 RTW89_HW_RATE_MCS18 = 0x92,
344 RTW89_HW_RATE_MCS19 = 0x93,
345 RTW89_HW_RATE_MCS20 = 0x94,
346 RTW89_HW_RATE_MCS21 = 0x95,
347 RTW89_HW_RATE_MCS22 = 0x96,
348 RTW89_HW_RATE_MCS23 = 0x97,
349 RTW89_HW_RATE_MCS24 = 0x98,
350 RTW89_HW_RATE_MCS25 = 0x99,
351 RTW89_HW_RATE_MCS26 = 0x9A,
352 RTW89_HW_RATE_MCS27 = 0x9B,
353 RTW89_HW_RATE_MCS28 = 0x9C,
354 RTW89_HW_RATE_MCS29 = 0x9D,
355 RTW89_HW_RATE_MCS30 = 0x9E,
356 RTW89_HW_RATE_MCS31 = 0x9F,
357 RTW89_HW_RATE_VHT_NSS1_MCS0 = 0x100,
358 RTW89_HW_RATE_VHT_NSS1_MCS1 = 0x101,
359 RTW89_HW_RATE_VHT_NSS1_MCS2 = 0x102,
360 RTW89_HW_RATE_VHT_NSS1_MCS3 = 0x103,
361 RTW89_HW_RATE_VHT_NSS1_MCS4 = 0x104,
362 RTW89_HW_RATE_VHT_NSS1_MCS5 = 0x105,
363 RTW89_HW_RATE_VHT_NSS1_MCS6 = 0x106,
364 RTW89_HW_RATE_VHT_NSS1_MCS7 = 0x107,
365 RTW89_HW_RATE_VHT_NSS1_MCS8 = 0x108,
366 RTW89_HW_RATE_VHT_NSS1_MCS9 = 0x109,
367 RTW89_HW_RATE_VHT_NSS2_MCS0 = 0x110,
368 RTW89_HW_RATE_VHT_NSS2_MCS1 = 0x111,
369 RTW89_HW_RATE_VHT_NSS2_MCS2 = 0x112,
370 RTW89_HW_RATE_VHT_NSS2_MCS3 = 0x113,
371 RTW89_HW_RATE_VHT_NSS2_MCS4 = 0x114,
372 RTW89_HW_RATE_VHT_NSS2_MCS5 = 0x115,
373 RTW89_HW_RATE_VHT_NSS2_MCS6 = 0x116,
374 RTW89_HW_RATE_VHT_NSS2_MCS7 = 0x117,
375 RTW89_HW_RATE_VHT_NSS2_MCS8 = 0x118,
376 RTW89_HW_RATE_VHT_NSS2_MCS9 = 0x119,
377 RTW89_HW_RATE_VHT_NSS3_MCS0 = 0x120,
378 RTW89_HW_RATE_VHT_NSS3_MCS1 = 0x121,
379 RTW89_HW_RATE_VHT_NSS3_MCS2 = 0x122,
380 RTW89_HW_RATE_VHT_NSS3_MCS3 = 0x123,
381 RTW89_HW_RATE_VHT_NSS3_MCS4 = 0x124,
382 RTW89_HW_RATE_VHT_NSS3_MCS5 = 0x125,
383 RTW89_HW_RATE_VHT_NSS3_MCS6 = 0x126,
384 RTW89_HW_RATE_VHT_NSS3_MCS7 = 0x127,
385 RTW89_HW_RATE_VHT_NSS3_MCS8 = 0x128,
386 RTW89_HW_RATE_VHT_NSS3_MCS9 = 0x129,
387 RTW89_HW_RATE_VHT_NSS4_MCS0 = 0x130,
388 RTW89_HW_RATE_VHT_NSS4_MCS1 = 0x131,
389 RTW89_HW_RATE_VHT_NSS4_MCS2 = 0x132,
390 RTW89_HW_RATE_VHT_NSS4_MCS3 = 0x133,
391 RTW89_HW_RATE_VHT_NSS4_MCS4 = 0x134,
392 RTW89_HW_RATE_VHT_NSS4_MCS5 = 0x135,
393 RTW89_HW_RATE_VHT_NSS4_MCS6 = 0x136,
394 RTW89_HW_RATE_VHT_NSS4_MCS7 = 0x137,
395 RTW89_HW_RATE_VHT_NSS4_MCS8 = 0x138,
396 RTW89_HW_RATE_VHT_NSS4_MCS9 = 0x139,
397 RTW89_HW_RATE_HE_NSS1_MCS0 = 0x180,
398 RTW89_HW_RATE_HE_NSS1_MCS1 = 0x181,
399 RTW89_HW_RATE_HE_NSS1_MCS2 = 0x182,
400 RTW89_HW_RATE_HE_NSS1_MCS3 = 0x183,
401 RTW89_HW_RATE_HE_NSS1_MCS4 = 0x184,
402 RTW89_HW_RATE_HE_NSS1_MCS5 = 0x185,
403 RTW89_HW_RATE_HE_NSS1_MCS6 = 0x186,
404 RTW89_HW_RATE_HE_NSS1_MCS7 = 0x187,
405 RTW89_HW_RATE_HE_NSS1_MCS8 = 0x188,
406 RTW89_HW_RATE_HE_NSS1_MCS9 = 0x189,
407 RTW89_HW_RATE_HE_NSS1_MCS10 = 0x18A,
408 RTW89_HW_RATE_HE_NSS1_MCS11 = 0x18B,
409 RTW89_HW_RATE_HE_NSS2_MCS0 = 0x190,
410 RTW89_HW_RATE_HE_NSS2_MCS1 = 0x191,
411 RTW89_HW_RATE_HE_NSS2_MCS2 = 0x192,
412 RTW89_HW_RATE_HE_NSS2_MCS3 = 0x193,
413 RTW89_HW_RATE_HE_NSS2_MCS4 = 0x194,
414 RTW89_HW_RATE_HE_NSS2_MCS5 = 0x195,
415 RTW89_HW_RATE_HE_NSS2_MCS6 = 0x196,
416 RTW89_HW_RATE_HE_NSS2_MCS7 = 0x197,
417 RTW89_HW_RATE_HE_NSS2_MCS8 = 0x198,
418 RTW89_HW_RATE_HE_NSS2_MCS9 = 0x199,
419 RTW89_HW_RATE_HE_NSS2_MCS10 = 0x19A,
420 RTW89_HW_RATE_HE_NSS2_MCS11 = 0x19B,
421 RTW89_HW_RATE_HE_NSS3_MCS0 = 0x1A0,
422 RTW89_HW_RATE_HE_NSS3_MCS1 = 0x1A1,
423 RTW89_HW_RATE_HE_NSS3_MCS2 = 0x1A2,
424 RTW89_HW_RATE_HE_NSS3_MCS3 = 0x1A3,
425 RTW89_HW_RATE_HE_NSS3_MCS4 = 0x1A4,
426 RTW89_HW_RATE_HE_NSS3_MCS5 = 0x1A5,
427 RTW89_HW_RATE_HE_NSS3_MCS6 = 0x1A6,
428 RTW89_HW_RATE_HE_NSS3_MCS7 = 0x1A7,
429 RTW89_HW_RATE_HE_NSS3_MCS8 = 0x1A8,
430 RTW89_HW_RATE_HE_NSS3_MCS9 = 0x1A9,
431 RTW89_HW_RATE_HE_NSS3_MCS10 = 0x1AA,
432 RTW89_HW_RATE_HE_NSS3_MCS11 = 0x1AB,
433 RTW89_HW_RATE_HE_NSS4_MCS0 = 0x1B0,
434 RTW89_HW_RATE_HE_NSS4_MCS1 = 0x1B1,
435 RTW89_HW_RATE_HE_NSS4_MCS2 = 0x1B2,
436 RTW89_HW_RATE_HE_NSS4_MCS3 = 0x1B3,
437 RTW89_HW_RATE_HE_NSS4_MCS4 = 0x1B4,
438 RTW89_HW_RATE_HE_NSS4_MCS5 = 0x1B5,
439 RTW89_HW_RATE_HE_NSS4_MCS6 = 0x1B6,
440 RTW89_HW_RATE_HE_NSS4_MCS7 = 0x1B7,
441 RTW89_HW_RATE_HE_NSS4_MCS8 = 0x1B8,
442 RTW89_HW_RATE_HE_NSS4_MCS9 = 0x1B9,
443 RTW89_HW_RATE_HE_NSS4_MCS10 = 0x1BA,
444 RTW89_HW_RATE_HE_NSS4_MCS11 = 0x1BB,
445
446 RTW89_HW_RATE_V1_MCS0 = 0x100,
447 RTW89_HW_RATE_V1_MCS1 = 0x101,
448 RTW89_HW_RATE_V1_MCS2 = 0x102,
449 RTW89_HW_RATE_V1_MCS3 = 0x103,
450 RTW89_HW_RATE_V1_MCS4 = 0x104,
451 RTW89_HW_RATE_V1_MCS5 = 0x105,
452 RTW89_HW_RATE_V1_MCS6 = 0x106,
453 RTW89_HW_RATE_V1_MCS7 = 0x107,
454 RTW89_HW_RATE_V1_MCS8 = 0x108,
455 RTW89_HW_RATE_V1_MCS9 = 0x109,
456 RTW89_HW_RATE_V1_MCS10 = 0x10A,
457 RTW89_HW_RATE_V1_MCS11 = 0x10B,
458 RTW89_HW_RATE_V1_MCS12 = 0x10C,
459 RTW89_HW_RATE_V1_MCS13 = 0x10D,
460 RTW89_HW_RATE_V1_MCS14 = 0x10E,
461 RTW89_HW_RATE_V1_MCS15 = 0x10F,
462 RTW89_HW_RATE_V1_MCS16 = 0x110,
463 RTW89_HW_RATE_V1_MCS17 = 0x111,
464 RTW89_HW_RATE_V1_MCS18 = 0x112,
465 RTW89_HW_RATE_V1_MCS19 = 0x113,
466 RTW89_HW_RATE_V1_MCS20 = 0x114,
467 RTW89_HW_RATE_V1_MCS21 = 0x115,
468 RTW89_HW_RATE_V1_MCS22 = 0x116,
469 RTW89_HW_RATE_V1_MCS23 = 0x117,
470 RTW89_HW_RATE_V1_MCS24 = 0x118,
471 RTW89_HW_RATE_V1_MCS25 = 0x119,
472 RTW89_HW_RATE_V1_MCS26 = 0x11A,
473 RTW89_HW_RATE_V1_MCS27 = 0x11B,
474 RTW89_HW_RATE_V1_MCS28 = 0x11C,
475 RTW89_HW_RATE_V1_MCS29 = 0x11D,
476 RTW89_HW_RATE_V1_MCS30 = 0x11E,
477 RTW89_HW_RATE_V1_MCS31 = 0x11F,
478 RTW89_HW_RATE_V1_VHT_NSS1_MCS0 = 0x200,
479 RTW89_HW_RATE_V1_VHT_NSS1_MCS1 = 0x201,
480 RTW89_HW_RATE_V1_VHT_NSS1_MCS2 = 0x202,
481 RTW89_HW_RATE_V1_VHT_NSS1_MCS3 = 0x203,
482 RTW89_HW_RATE_V1_VHT_NSS1_MCS4 = 0x204,
483 RTW89_HW_RATE_V1_VHT_NSS1_MCS5 = 0x205,
484 RTW89_HW_RATE_V1_VHT_NSS1_MCS6 = 0x206,
485 RTW89_HW_RATE_V1_VHT_NSS1_MCS7 = 0x207,
486 RTW89_HW_RATE_V1_VHT_NSS1_MCS8 = 0x208,
487 RTW89_HW_RATE_V1_VHT_NSS1_MCS9 = 0x209,
488 RTW89_HW_RATE_V1_VHT_NSS1_MCS10 = 0x20A,
489 RTW89_HW_RATE_V1_VHT_NSS1_MCS11 = 0x20B,
490 RTW89_HW_RATE_V1_VHT_NSS2_MCS0 = 0x220,
491 RTW89_HW_RATE_V1_VHT_NSS2_MCS1 = 0x221,
492 RTW89_HW_RATE_V1_VHT_NSS2_MCS2 = 0x222,
493 RTW89_HW_RATE_V1_VHT_NSS2_MCS3 = 0x223,
494 RTW89_HW_RATE_V1_VHT_NSS2_MCS4 = 0x224,
495 RTW89_HW_RATE_V1_VHT_NSS2_MCS5 = 0x225,
496 RTW89_HW_RATE_V1_VHT_NSS2_MCS6 = 0x226,
497 RTW89_HW_RATE_V1_VHT_NSS2_MCS7 = 0x227,
498 RTW89_HW_RATE_V1_VHT_NSS2_MCS8 = 0x228,
499 RTW89_HW_RATE_V1_VHT_NSS2_MCS9 = 0x229,
500 RTW89_HW_RATE_V1_VHT_NSS2_MCS10 = 0x22A,
501 RTW89_HW_RATE_V1_VHT_NSS2_MCS11 = 0x22B,
502 RTW89_HW_RATE_V1_VHT_NSS3_MCS0 = 0x240,
503 RTW89_HW_RATE_V1_VHT_NSS3_MCS1 = 0x241,
504 RTW89_HW_RATE_V1_VHT_NSS3_MCS2 = 0x242,
505 RTW89_HW_RATE_V1_VHT_NSS3_MCS3 = 0x243,
506 RTW89_HW_RATE_V1_VHT_NSS3_MCS4 = 0x244,
507 RTW89_HW_RATE_V1_VHT_NSS3_MCS5 = 0x245,
508 RTW89_HW_RATE_V1_VHT_NSS3_MCS6 = 0x246,
509 RTW89_HW_RATE_V1_VHT_NSS3_MCS7 = 0x247,
510 RTW89_HW_RATE_V1_VHT_NSS3_MCS8 = 0x248,
511 RTW89_HW_RATE_V1_VHT_NSS3_MCS9 = 0x249,
512 RTW89_HW_RATE_V1_VHT_NSS3_MCS10 = 0x24A,
513 RTW89_HW_RATE_V1_VHT_NSS3_MCS11 = 0x24B,
514 RTW89_HW_RATE_V1_VHT_NSS4_MCS0 = 0x260,
515 RTW89_HW_RATE_V1_VHT_NSS4_MCS1 = 0x261,
516 RTW89_HW_RATE_V1_VHT_NSS4_MCS2 = 0x262,
517 RTW89_HW_RATE_V1_VHT_NSS4_MCS3 = 0x263,
518 RTW89_HW_RATE_V1_VHT_NSS4_MCS4 = 0x264,
519 RTW89_HW_RATE_V1_VHT_NSS4_MCS5 = 0x265,
520 RTW89_HW_RATE_V1_VHT_NSS4_MCS6 = 0x266,
521 RTW89_HW_RATE_V1_VHT_NSS4_MCS7 = 0x267,
522 RTW89_HW_RATE_V1_VHT_NSS4_MCS8 = 0x268,
523 RTW89_HW_RATE_V1_VHT_NSS4_MCS9 = 0x269,
524 RTW89_HW_RATE_V1_VHT_NSS4_MCS10 = 0x26A,
525 RTW89_HW_RATE_V1_VHT_NSS4_MCS11 = 0x26B,
526 RTW89_HW_RATE_V1_HE_NSS1_MCS0 = 0x300,
527 RTW89_HW_RATE_V1_HE_NSS1_MCS1 = 0x301,
528 RTW89_HW_RATE_V1_HE_NSS1_MCS2 = 0x302,
529 RTW89_HW_RATE_V1_HE_NSS1_MCS3 = 0x303,
530 RTW89_HW_RATE_V1_HE_NSS1_MCS4 = 0x304,
531 RTW89_HW_RATE_V1_HE_NSS1_MCS5 = 0x305,
532 RTW89_HW_RATE_V1_HE_NSS1_MCS6 = 0x306,
533 RTW89_HW_RATE_V1_HE_NSS1_MCS7 = 0x307,
534 RTW89_HW_RATE_V1_HE_NSS1_MCS8 = 0x308,
535 RTW89_HW_RATE_V1_HE_NSS1_MCS9 = 0x309,
536 RTW89_HW_RATE_V1_HE_NSS1_MCS10 = 0x30A,
537 RTW89_HW_RATE_V1_HE_NSS1_MCS11 = 0x30B,
538 RTW89_HW_RATE_V1_HE_NSS2_MCS0 = 0x320,
539 RTW89_HW_RATE_V1_HE_NSS2_MCS1 = 0x321,
540 RTW89_HW_RATE_V1_HE_NSS2_MCS2 = 0x322,
541 RTW89_HW_RATE_V1_HE_NSS2_MCS3 = 0x323,
542 RTW89_HW_RATE_V1_HE_NSS2_MCS4 = 0x324,
543 RTW89_HW_RATE_V1_HE_NSS2_MCS5 = 0x325,
544 RTW89_HW_RATE_V1_HE_NSS2_MCS6 = 0x326,
545 RTW89_HW_RATE_V1_HE_NSS2_MCS7 = 0x327,
546 RTW89_HW_RATE_V1_HE_NSS2_MCS8 = 0x328,
547 RTW89_HW_RATE_V1_HE_NSS2_MCS9 = 0x329,
548 RTW89_HW_RATE_V1_HE_NSS2_MCS10 = 0x32A,
549 RTW89_HW_RATE_V1_HE_NSS2_MCS11 = 0x32B,
550 RTW89_HW_RATE_V1_HE_NSS3_MCS0 = 0x340,
551 RTW89_HW_RATE_V1_HE_NSS3_MCS1 = 0x341,
552 RTW89_HW_RATE_V1_HE_NSS3_MCS2 = 0x342,
553 RTW89_HW_RATE_V1_HE_NSS3_MCS3 = 0x343,
554 RTW89_HW_RATE_V1_HE_NSS3_MCS4 = 0x344,
555 RTW89_HW_RATE_V1_HE_NSS3_MCS5 = 0x345,
556 RTW89_HW_RATE_V1_HE_NSS3_MCS6 = 0x346,
557 RTW89_HW_RATE_V1_HE_NSS3_MCS7 = 0x347,
558 RTW89_HW_RATE_V1_HE_NSS3_MCS8 = 0x348,
559 RTW89_HW_RATE_V1_HE_NSS3_MCS9 = 0x349,
560 RTW89_HW_RATE_V1_HE_NSS3_MCS10 = 0x34A,
561 RTW89_HW_RATE_V1_HE_NSS3_MCS11 = 0x34B,
562 RTW89_HW_RATE_V1_HE_NSS4_MCS0 = 0x360,
563 RTW89_HW_RATE_V1_HE_NSS4_MCS1 = 0x361,
564 RTW89_HW_RATE_V1_HE_NSS4_MCS2 = 0x362,
565 RTW89_HW_RATE_V1_HE_NSS4_MCS3 = 0x363,
566 RTW89_HW_RATE_V1_HE_NSS4_MCS4 = 0x364,
567 RTW89_HW_RATE_V1_HE_NSS4_MCS5 = 0x365,
568 RTW89_HW_RATE_V1_HE_NSS4_MCS6 = 0x366,
569 RTW89_HW_RATE_V1_HE_NSS4_MCS7 = 0x367,
570 RTW89_HW_RATE_V1_HE_NSS4_MCS8 = 0x368,
571 RTW89_HW_RATE_V1_HE_NSS4_MCS9 = 0x369,
572 RTW89_HW_RATE_V1_HE_NSS4_MCS10 = 0x36A,
573 RTW89_HW_RATE_V1_HE_NSS4_MCS11 = 0x36B,
574 RTW89_HW_RATE_V1_EHT_NSS1_MCS0 = 0x400,
575 RTW89_HW_RATE_V1_EHT_NSS1_MCS1 = 0x401,
576 RTW89_HW_RATE_V1_EHT_NSS1_MCS2 = 0x402,
577 RTW89_HW_RATE_V1_EHT_NSS1_MCS3 = 0x403,
578 RTW89_HW_RATE_V1_EHT_NSS1_MCS4 = 0x404,
579 RTW89_HW_RATE_V1_EHT_NSS1_MCS5 = 0x405,
580 RTW89_HW_RATE_V1_EHT_NSS1_MCS6 = 0x406,
581 RTW89_HW_RATE_V1_EHT_NSS1_MCS7 = 0x407,
582 RTW89_HW_RATE_V1_EHT_NSS1_MCS8 = 0x408,
583 RTW89_HW_RATE_V1_EHT_NSS1_MCS9 = 0x409,
584 RTW89_HW_RATE_V1_EHT_NSS1_MCS10 = 0x40A,
585 RTW89_HW_RATE_V1_EHT_NSS1_MCS11 = 0x40B,
586 RTW89_HW_RATE_V1_EHT_NSS1_MCS12 = 0x40C,
587 RTW89_HW_RATE_V1_EHT_NSS1_MCS13 = 0x40D,
588 RTW89_HW_RATE_V1_EHT_NSS1_MCS14 = 0x40E,
589 RTW89_HW_RATE_V1_EHT_NSS1_MCS15 = 0x40F,
590 RTW89_HW_RATE_V1_EHT_NSS2_MCS0 = 0x420,
591 RTW89_HW_RATE_V1_EHT_NSS2_MCS1 = 0x421,
592 RTW89_HW_RATE_V1_EHT_NSS2_MCS2 = 0x422,
593 RTW89_HW_RATE_V1_EHT_NSS2_MCS3 = 0x423,
594 RTW89_HW_RATE_V1_EHT_NSS2_MCS4 = 0x424,
595 RTW89_HW_RATE_V1_EHT_NSS2_MCS5 = 0x425,
596 RTW89_HW_RATE_V1_EHT_NSS2_MCS6 = 0x426,
597 RTW89_HW_RATE_V1_EHT_NSS2_MCS7 = 0x427,
598 RTW89_HW_RATE_V1_EHT_NSS2_MCS8 = 0x428,
599 RTW89_HW_RATE_V1_EHT_NSS2_MCS9 = 0x429,
600 RTW89_HW_RATE_V1_EHT_NSS2_MCS10 = 0x42A,
601 RTW89_HW_RATE_V1_EHT_NSS2_MCS11 = 0x42B,
602 RTW89_HW_RATE_V1_EHT_NSS2_MCS12 = 0x42C,
603 RTW89_HW_RATE_V1_EHT_NSS2_MCS13 = 0x42D,
604 RTW89_HW_RATE_V1_EHT_NSS3_MCS0 = 0x440,
605 RTW89_HW_RATE_V1_EHT_NSS3_MCS1 = 0x441,
606 RTW89_HW_RATE_V1_EHT_NSS3_MCS2 = 0x442,
607 RTW89_HW_RATE_V1_EHT_NSS3_MCS3 = 0x443,
608 RTW89_HW_RATE_V1_EHT_NSS3_MCS4 = 0x444,
609 RTW89_HW_RATE_V1_EHT_NSS3_MCS5 = 0x445,
610 RTW89_HW_RATE_V1_EHT_NSS3_MCS6 = 0x446,
611 RTW89_HW_RATE_V1_EHT_NSS3_MCS7 = 0x447,
612 RTW89_HW_RATE_V1_EHT_NSS3_MCS8 = 0x448,
613 RTW89_HW_RATE_V1_EHT_NSS3_MCS9 = 0x449,
614 RTW89_HW_RATE_V1_EHT_NSS3_MCS10 = 0x44A,
615 RTW89_HW_RATE_V1_EHT_NSS3_MCS11 = 0x44B,
616 RTW89_HW_RATE_V1_EHT_NSS3_MCS12 = 0x44C,
617 RTW89_HW_RATE_V1_EHT_NSS3_MCS13 = 0x44D,
618 RTW89_HW_RATE_V1_EHT_NSS4_MCS0 = 0x460,
619 RTW89_HW_RATE_V1_EHT_NSS4_MCS1 = 0x461,
620 RTW89_HW_RATE_V1_EHT_NSS4_MCS2 = 0x462,
621 RTW89_HW_RATE_V1_EHT_NSS4_MCS3 = 0x463,
622 RTW89_HW_RATE_V1_EHT_NSS4_MCS4 = 0x464,
623 RTW89_HW_RATE_V1_EHT_NSS4_MCS5 = 0x465,
624 RTW89_HW_RATE_V1_EHT_NSS4_MCS6 = 0x466,
625 RTW89_HW_RATE_V1_EHT_NSS4_MCS7 = 0x467,
626 RTW89_HW_RATE_V1_EHT_NSS4_MCS8 = 0x468,
627 RTW89_HW_RATE_V1_EHT_NSS4_MCS9 = 0x469,
628 RTW89_HW_RATE_V1_EHT_NSS4_MCS10 = 0x46A,
629 RTW89_HW_RATE_V1_EHT_NSS4_MCS11 = 0x46B,
630 RTW89_HW_RATE_V1_EHT_NSS4_MCS12 = 0x46C,
631 RTW89_HW_RATE_V1_EHT_NSS4_MCS13 = 0x46D,
632
633 RTW89_HW_RATE_NR,
634 RTW89_HW_RATE_INVAL,
635
636 RTW89_HW_RATE_MASK_MOD = GENMASK(8, 7),
637 RTW89_HW_RATE_MASK_VAL = GENMASK(6, 0),
638 RTW89_HW_RATE_V1_MASK_MOD = GENMASK(10, 8),
639 RTW89_HW_RATE_V1_MASK_VAL = GENMASK(7, 0),
640 };
641
642 /* 2G channels,
643 * 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
644 */
645 #define RTW89_2G_CH_NUM 14
646
647 /* 5G channels,
648 * 36, 38, 40, 42, 44, 46, 48, 50,
649 * 52, 54, 56, 58, 60, 62, 64,
650 * 100, 102, 104, 106, 108, 110, 112, 114,
651 * 116, 118, 120, 122, 124, 126, 128, 130,
652 * 132, 134, 136, 138, 140, 142, 144,
653 * 149, 151, 153, 155, 157, 159, 161, 163,
654 * 165, 167, 169, 171, 173, 175, 177
655 */
656 #define RTW89_5G_CH_NUM 53
657
658 /* 6G channels,
659 * 1, 3, 5, 7, 9, 11, 13, 15,
660 * 17, 19, 21, 23, 25, 27, 29, 33,
661 * 35, 37, 39, 41, 43, 45, 47, 49,
662 * 51, 53, 55, 57, 59, 61, 65, 67,
663 * 69, 71, 73, 75, 77, 79, 81, 83,
664 * 85, 87, 89, 91, 93, 97, 99, 101,
665 * 103, 105, 107, 109, 111, 113, 115, 117,
666 * 119, 121, 123, 125, 129, 131, 133, 135,
667 * 137, 139, 141, 143, 145, 147, 149, 151,
668 * 153, 155, 157, 161, 163, 165, 167, 169,
669 * 171, 173, 175, 177, 179, 181, 183, 185,
670 * 187, 189, 193, 195, 197, 199, 201, 203,
671 * 205, 207, 209, 211, 213, 215, 217, 219,
672 * 221, 225, 227, 229, 231, 233, 235, 237,
673 * 239, 241, 243, 245, 247, 249, 251, 253,
674 */
675 #define RTW89_6G_CH_NUM 120
676
677 enum rtw89_rate_section {
678 RTW89_RS_CCK,
679 RTW89_RS_OFDM,
680 RTW89_RS_MCS, /* for HT/VHT/HE */
681 RTW89_RS_HEDCM,
682 RTW89_RS_OFFSET,
683 RTW89_RS_NUM,
684 RTW89_RS_LMT_NUM = RTW89_RS_MCS + 1,
685 RTW89_RS_TX_SHAPE_NUM = RTW89_RS_OFDM + 1,
686 };
687
688 enum rtw89_rate_offset_indexes {
689 RTW89_RATE_OFFSET_HE,
690 RTW89_RATE_OFFSET_VHT,
691 RTW89_RATE_OFFSET_HT,
692 RTW89_RATE_OFFSET_OFDM,
693 RTW89_RATE_OFFSET_CCK,
694 RTW89_RATE_OFFSET_DLRU_EHT,
695 RTW89_RATE_OFFSET_DLRU_HE,
696 RTW89_RATE_OFFSET_EHT,
697 __RTW89_RATE_OFFSET_NUM,
698
699 RTW89_RATE_OFFSET_NUM_AX = RTW89_RATE_OFFSET_CCK + 1,
700 RTW89_RATE_OFFSET_NUM_BE = RTW89_RATE_OFFSET_EHT + 1,
701 };
702
703 enum rtw89_rate_num {
704 RTW89_RATE_CCK_NUM = 4,
705 RTW89_RATE_OFDM_NUM = 8,
706 RTW89_RATE_HEDCM_NUM = 4, /* for HEDCM MCS0/1/3/4 */
707
708 RTW89_RATE_MCS_NUM_AX = 12,
709 RTW89_RATE_MCS_NUM_BE = 16,
710 __RTW89_RATE_MCS_NUM = 16,
711 };
712
713 enum rtw89_nss {
714 RTW89_NSS_1 = 0,
715 RTW89_NSS_2 = 1,
716 /* HE DCM only support 1ss and 2ss */
717 RTW89_NSS_HEDCM_NUM = RTW89_NSS_2 + 1,
718 RTW89_NSS_3 = 2,
719 RTW89_NSS_4 = 3,
720 RTW89_NSS_NUM,
721 };
722
723 enum rtw89_ntx {
724 RTW89_1TX = 0,
725 RTW89_2TX = 1,
726 RTW89_NTX_NUM,
727 };
728
729 enum rtw89_beamforming_type {
730 RTW89_NONBF = 0,
731 RTW89_BF = 1,
732 RTW89_BF_NUM,
733 };
734
735 enum rtw89_ofdma_type {
736 RTW89_NON_OFDMA = 0,
737 RTW89_OFDMA = 1,
738 RTW89_OFDMA_NUM,
739 };
740
741 /* neither insert new in the middle, nor change any given definition */
742 enum rtw89_regulation_type {
743 RTW89_WW = 0,
744 RTW89_ETSI = 1,
745 RTW89_FCC = 2,
746 RTW89_MKK = 3,
747 RTW89_NA = 4,
748 RTW89_IC = 5,
749 RTW89_KCC = 6,
750 RTW89_ACMA = 7,
751 RTW89_NCC = 8,
752 RTW89_MEXICO = 9,
753 RTW89_CHILE = 10,
754 RTW89_UKRAINE = 11,
755 RTW89_CN = 12,
756 RTW89_QATAR = 13,
757 RTW89_UK = 14,
758 RTW89_THAILAND = 15,
759 RTW89_REGD_NUM,
760 };
761
762 enum rtw89_reg_6ghz_power {
763 RTW89_REG_6GHZ_POWER_VLP = 0,
764 RTW89_REG_6GHZ_POWER_LPI = 1,
765 RTW89_REG_6GHZ_POWER_STD = 2,
766
767 NUM_OF_RTW89_REG_6GHZ_POWER,
768 RTW89_REG_6GHZ_POWER_DFLT = RTW89_REG_6GHZ_POWER_VLP,
769 };
770
771 #define RTW89_MIN_VALID_POWER_CONSTRAINT (-10) /* unit: dBm */
772
773 /* calculate based on ieee80211 Transmit Power Envelope */
774 struct rtw89_reg_6ghz_tpe {
775 bool valid;
776 s8 constraint; /* unit: dBm */
777 };
778
779 enum rtw89_fw_pkt_ofld_type {
780 RTW89_PKT_OFLD_TYPE_PROBE_RSP = 0,
781 RTW89_PKT_OFLD_TYPE_PS_POLL = 1,
782 RTW89_PKT_OFLD_TYPE_NULL_DATA = 2,
783 RTW89_PKT_OFLD_TYPE_QOS_NULL = 3,
784 RTW89_PKT_OFLD_TYPE_CTS2SELF = 4,
785 RTW89_PKT_OFLD_TYPE_ARP_RSP = 5,
786 RTW89_PKT_OFLD_TYPE_NDP = 6,
787 RTW89_PKT_OFLD_TYPE_EAPOL_KEY = 7,
788 RTW89_PKT_OFLD_TYPE_SA_QUERY = 8,
789 RTW89_PKT_OFLD_TYPE_PROBE_REQ = 12,
790 RTW89_PKT_OFLD_TYPE_NUM,
791 };
792
793 struct rtw89_txpwr_byrate {
794 s8 cck[RTW89_RATE_CCK_NUM];
795 s8 ofdm[RTW89_RATE_OFDM_NUM];
796 s8 mcs[RTW89_OFDMA_NUM][RTW89_NSS_NUM][__RTW89_RATE_MCS_NUM];
797 s8 hedcm[RTW89_OFDMA_NUM][RTW89_NSS_HEDCM_NUM][RTW89_RATE_HEDCM_NUM];
798 s8 offset[__RTW89_RATE_OFFSET_NUM];
799 s8 trap;
800 };
801
802 struct rtw89_rate_desc {
803 enum rtw89_nss nss;
804 enum rtw89_rate_section rs;
805 enum rtw89_ofdma_type ofdma;
806 u8 idx;
807 };
808
809 #define PHY_STS_HDR_LEN 8
810 #define RF_PATH_MAX 4
811 #define RTW89_MAX_PPDU_CNT 8
812 struct rtw89_rx_phy_ppdu {
813 void *buf;
814 u32 len;
815 u8 rssi_avg;
816 u8 rssi[RF_PATH_MAX];
817 u8 mac_id;
818 u8 chan_idx;
819 u8 phy_idx;
820 u8 ie;
821 u16 rate;
822 u8 rpl_avg;
823 u8 rpl_path[RF_PATH_MAX];
824 u8 rpl_fd[RF_PATH_MAX];
825 u8 bw_idx;
826 u8 rx_path_en;
827 struct {
828 bool has;
829 u8 avg_snr;
830 u8 evm_max;
831 u8 evm_min;
832 } ofdm;
833 bool has_data;
834 bool has_bcn;
835 bool ldpc;
836 bool stbc;
837 bool to_self;
838 bool valid;
839 bool hdr_2_en;
840 };
841
842 enum rtw89_mac_idx {
843 RTW89_MAC_0 = 0,
844 RTW89_MAC_1 = 1,
845 RTW89_MAC_NUM,
846 };
847
848 enum rtw89_phy_idx {
849 RTW89_PHY_0 = 0,
850 RTW89_PHY_1 = 1,
851 RTW89_PHY_NUM,
852 };
853
854 #define __RTW89_MLD_MAX_LINK_NUM 2
855 #define RTW89_MLD_NON_STA_LINK_NUM 1
856
857 enum rtw89_chanctx_idx {
858 RTW89_CHANCTX_0 = 0,
859 RTW89_CHANCTX_1 = 1,
860
861 NUM_OF_RTW89_CHANCTX,
862 RTW89_CHANCTX_IDLE = NUM_OF_RTW89_CHANCTX,
863 };
864
865 enum rtw89_rf_path {
866 RF_PATH_A = 0,
867 RF_PATH_B = 1,
868 RF_PATH_C = 2,
869 RF_PATH_D = 3,
870 RF_PATH_AB,
871 RF_PATH_AC,
872 RF_PATH_AD,
873 RF_PATH_BC,
874 RF_PATH_BD,
875 RF_PATH_CD,
876 RF_PATH_ABC,
877 RF_PATH_ABD,
878 RF_PATH_ACD,
879 RF_PATH_BCD,
880 RF_PATH_ABCD,
881 };
882
883 enum rtw89_rf_path_bit {
884 RF_A = BIT(0),
885 RF_B = BIT(1),
886 RF_C = BIT(2),
887 RF_D = BIT(3),
888
889 RF_AB = (RF_A | RF_B),
890 RF_AC = (RF_A | RF_C),
891 RF_AD = (RF_A | RF_D),
892 RF_BC = (RF_B | RF_C),
893 RF_BD = (RF_B | RF_D),
894 RF_CD = (RF_C | RF_D),
895
896 RF_ABC = (RF_A | RF_B | RF_C),
897 RF_ABD = (RF_A | RF_B | RF_D),
898 RF_ACD = (RF_A | RF_C | RF_D),
899 RF_BCD = (RF_B | RF_C | RF_D),
900
901 RF_ABCD = (RF_A | RF_B | RF_C | RF_D),
902 };
903
904 enum rtw89_bandwidth {
905 RTW89_CHANNEL_WIDTH_20 = 0,
906 RTW89_CHANNEL_WIDTH_40 = 1,
907 RTW89_CHANNEL_WIDTH_80 = 2,
908 RTW89_CHANNEL_WIDTH_160 = 3,
909 RTW89_CHANNEL_WIDTH_320 = 4,
910
911 /* keep index order above */
912 RTW89_CHANNEL_WIDTH_ORDINARY_NUM = 5,
913
914 RTW89_CHANNEL_WIDTH_80_80 = 5,
915 RTW89_CHANNEL_WIDTH_5 = 6,
916 RTW89_CHANNEL_WIDTH_10 = 7,
917 };
918
919 enum rtw89_ps_mode {
920 RTW89_PS_MODE_NONE = 0,
921 RTW89_PS_MODE_RFOFF = 1,
922 RTW89_PS_MODE_CLK_GATED = 2,
923 RTW89_PS_MODE_PWR_GATED = 3,
924 };
925
926 #define RTW89_2G_BW_NUM (RTW89_CHANNEL_WIDTH_40 + 1)
927 #define RTW89_5G_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1)
928 #define RTW89_6G_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1)
929 #define RTW89_BYR_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1)
930 #define RTW89_PPE_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1)
931
932 enum rtw89_pe_duration {
933 RTW89_PE_DURATION_0 = 0,
934 RTW89_PE_DURATION_8 = 1,
935 RTW89_PE_DURATION_16 = 2,
936 RTW89_PE_DURATION_16_20 = 3,
937 };
938
939 enum rtw89_ru_bandwidth {
940 RTW89_RU26 = 0,
941 RTW89_RU52 = 1,
942 RTW89_RU106 = 2,
943 RTW89_RU52_26 = 3,
944 RTW89_RU106_26 = 4,
945 RTW89_RU_NUM,
946 };
947
948 enum rtw89_sc_offset {
949 RTW89_SC_DONT_CARE = 0,
950 RTW89_SC_20_UPPER = 1,
951 RTW89_SC_20_LOWER = 2,
952 RTW89_SC_20_UPMOST = 3,
953 RTW89_SC_20_LOWEST = 4,
954 RTW89_SC_20_UP2X = 5,
955 RTW89_SC_20_LOW2X = 6,
956 RTW89_SC_20_UP3X = 7,
957 RTW89_SC_20_LOW3X = 8,
958 RTW89_SC_40_UPPER = 9,
959 RTW89_SC_40_LOWER = 10,
960 };
961
962 /* only mgd features can be added to the enum */
963 enum rtw89_wow_flags {
964 RTW89_WOW_FLAG_EN_MAGIC_PKT,
965 RTW89_WOW_FLAG_EN_REKEY_PKT,
966 RTW89_WOW_FLAG_EN_DISCONNECT,
967 RTW89_WOW_FLAG_EN_PATTERN,
968 RTW89_WOW_FLAG_NUM,
969 };
970
971 struct rtw89_chan {
972 u8 channel;
973 u8 primary_channel;
974 enum rtw89_band band_type;
975 enum rtw89_bandwidth band_width;
976
977 /* The follow-up are derived from the above. We must ensure that it
978 * is assigned correctly in rtw89_chan_create() if new one is added.
979 */
980 u32 freq;
981 enum rtw89_subband subband_type;
982 enum rtw89_sc_offset pri_ch_idx;
983 u8 pri_sb_idx;
984 };
985
986 struct rtw89_chan_rcd {
987 u8 prev_primary_channel;
988 enum rtw89_band prev_band_type;
989 bool band_changed;
990 };
991
992 struct rtw89_channel_help_params {
993 u32 tx_en;
994 };
995
996 struct rtw89_port_reg {
997 u32 port_cfg;
998 u32 tbtt_prohib;
999 u32 bcn_area;
1000 u32 bcn_early;
1001 u32 tbtt_early;
1002 u32 tbtt_agg;
1003 u32 bcn_space;
1004 u32 bcn_forcetx;
1005 u32 bcn_err_cnt;
1006 u32 bcn_err_flag;
1007 u32 dtim_ctrl;
1008 u32 tbtt_shift;
1009 u32 bcn_cnt_tmr;
1010 u32 tsftr_l;
1011 u32 tsftr_h;
1012 u32 md_tsft;
1013 u32 bss_color;
1014 u32 mbssid;
1015 u32 mbssid_drop;
1016 u32 tsf_sync;
1017 u32 ptcl_dbg;
1018 u32 ptcl_dbg_info;
1019 u32 bcn_drop_all;
1020 u32 hiq_win[RTW89_PORT_NUM];
1021 };
1022
1023 struct rtw89_txwd_body {
1024 __le32 dword0;
1025 __le32 dword1;
1026 __le32 dword2;
1027 __le32 dword3;
1028 __le32 dword4;
1029 __le32 dword5;
1030 } __packed;
1031
1032 struct rtw89_txwd_body_v1 {
1033 __le32 dword0;
1034 __le32 dword1;
1035 __le32 dword2;
1036 __le32 dword3;
1037 __le32 dword4;
1038 __le32 dword5;
1039 __le32 dword6;
1040 __le32 dword7;
1041 } __packed;
1042
1043 struct rtw89_txwd_body_v2 {
1044 __le32 dword0;
1045 __le32 dword1;
1046 __le32 dword2;
1047 __le32 dword3;
1048 __le32 dword4;
1049 __le32 dword5;
1050 __le32 dword6;
1051 __le32 dword7;
1052 } __packed;
1053
1054 struct rtw89_txwd_info {
1055 __le32 dword0;
1056 __le32 dword1;
1057 __le32 dword2;
1058 __le32 dword3;
1059 __le32 dword4;
1060 __le32 dword5;
1061 } __packed;
1062
1063 struct rtw89_txwd_info_v2 {
1064 __le32 dword0;
1065 __le32 dword1;
1066 __le32 dword2;
1067 __le32 dword3;
1068 __le32 dword4;
1069 __le32 dword5;
1070 __le32 dword6;
1071 __le32 dword7;
1072 } __packed;
1073
1074 struct rtw89_rx_desc_info {
1075 u16 pkt_size;
1076 u8 pkt_type;
1077 u8 drv_info_size;
1078 u8 phy_rpt_size;
1079 u8 hdr_cnv_size;
1080 u8 shift;
1081 u8 wl_hd_iv_len;
1082 bool long_rxdesc;
1083 bool bb_sel;
1084 bool mac_info_valid;
1085 u16 data_rate;
1086 u8 gi_ltf;
1087 u8 bw;
1088 u32 free_run_cnt;
1089 u8 user_id;
1090 bool sr_en;
1091 u8 ppdu_cnt;
1092 u8 ppdu_type;
1093 bool icv_err;
1094 bool crc32_err;
1095 bool hw_dec;
1096 bool sw_dec;
1097 bool addr1_match;
1098 u8 frag;
1099 u16 seq;
1100 u8 frame_type;
1101 u8 rx_pl_id;
1102 bool addr_cam_valid;
1103 u8 addr_cam_id;
1104 u8 sec_cam_id;
1105 u8 mac_id;
1106 u16 offset;
1107 u16 rxd_len;
1108 bool ready;
1109 u16 rssi;
1110 };
1111
1112 struct rtw89_rxdesc_short {
1113 __le32 dword0;
1114 __le32 dword1;
1115 __le32 dword2;
1116 __le32 dword3;
1117 } __packed;
1118
1119 struct rtw89_rxdesc_short_v2 {
1120 __le32 dword0;
1121 __le32 dword1;
1122 __le32 dword2;
1123 __le32 dword3;
1124 __le32 dword4;
1125 __le32 dword5;
1126 } __packed;
1127
1128 struct rtw89_rxdesc_long {
1129 __le32 dword0;
1130 __le32 dword1;
1131 __le32 dword2;
1132 __le32 dword3;
1133 __le32 dword4;
1134 __le32 dword5;
1135 __le32 dword6;
1136 __le32 dword7;
1137 } __packed;
1138
1139 struct rtw89_rxdesc_long_v2 {
1140 __le32 dword0;
1141 __le32 dword1;
1142 __le32 dword2;
1143 __le32 dword3;
1144 __le32 dword4;
1145 __le32 dword5;
1146 __le32 dword6;
1147 __le32 dword7;
1148 __le32 dword8;
1149 __le32 dword9;
1150 } __packed;
1151
1152 struct rtw89_rxdesc_phy_rpt_v2 {
1153 __le32 dword0;
1154 __le32 dword1;
1155 } __packed;
1156
1157 struct rtw89_tx_desc_info {
1158 u16 pkt_size;
1159 u8 wp_offset;
1160 u8 mac_id;
1161 u8 qsel;
1162 u8 ch_dma;
1163 u8 hdr_llc_len;
1164 bool is_bmc;
1165 bool en_wd_info;
1166 bool wd_page;
1167 bool use_rate;
1168 bool dis_data_fb;
1169 bool tid_indicate;
1170 bool agg_en;
1171 bool bk;
1172 u8 ampdu_density;
1173 u8 ampdu_num;
1174 bool sec_en;
1175 u8 addr_info_nr;
1176 u8 sec_keyid;
1177 u8 sec_type;
1178 u8 sec_cam_idx;
1179 u8 sec_seq[6];
1180 u16 data_rate;
1181 u16 data_retry_lowest_rate;
1182 bool fw_dl;
1183 u16 seq;
1184 bool a_ctrl_bsr;
1185 u8 hw_ssn_sel;
1186 #define RTW89_MGMT_HW_SSN_SEL 1
1187 u8 hw_seq_mode;
1188 #define RTW89_MGMT_HW_SEQ_MODE 1
1189 bool hiq;
1190 u8 port;
1191 bool er_cap;
1192 bool stbc;
1193 bool ldpc;
1194 bool upd_wlan_hdr;
1195 bool mlo;
1196 bool sw_mld;
1197 };
1198
1199 struct rtw89_core_tx_request {
1200 enum rtw89_core_tx_type tx_type;
1201
1202 struct sk_buff *skb;
1203 struct ieee80211_vif *vif;
1204 struct ieee80211_sta *sta;
1205 struct rtw89_vif_link *rtwvif_link;
1206 struct rtw89_sta_link *rtwsta_link;
1207 struct rtw89_tx_desc_info desc_info;
1208 };
1209
1210 struct rtw89_txq {
1211 struct list_head list;
1212 unsigned long flags;
1213 int wait_cnt;
1214 };
1215
1216 struct rtw89_mac_ax_gnt {
1217 u8 gnt_bt_sw_en;
1218 u8 gnt_bt;
1219 u8 gnt_wl_sw_en;
1220 u8 gnt_wl;
1221 } __packed;
1222
1223 struct rtw89_mac_ax_wl_act {
1224 u8 wlan_act_en;
1225 u8 wlan_act;
1226 } __packed;
1227
1228 #define RTW89_MAC_AX_COEX_GNT_NR 2
1229 struct rtw89_mac_ax_coex_gnt {
1230 struct rtw89_mac_ax_gnt band[RTW89_MAC_AX_COEX_GNT_NR];
1231 struct rtw89_mac_ax_wl_act bt[RTW89_MAC_AX_COEX_GNT_NR];
1232 };
1233
1234 enum rtw89_btc_ncnt {
1235 BTC_NCNT_POWER_ON = 0x0,
1236 BTC_NCNT_POWER_OFF,
1237 BTC_NCNT_INIT_COEX,
1238 BTC_NCNT_SCAN_START,
1239 BTC_NCNT_SCAN_FINISH,
1240 BTC_NCNT_SPECIAL_PACKET,
1241 BTC_NCNT_SWITCH_BAND,
1242 BTC_NCNT_RFK_TIMEOUT,
1243 BTC_NCNT_SHOW_COEX_INFO,
1244 BTC_NCNT_ROLE_INFO,
1245 BTC_NCNT_CONTROL,
1246 BTC_NCNT_RADIO_STATE,
1247 BTC_NCNT_CUSTOMERIZE,
1248 BTC_NCNT_WL_RFK,
1249 BTC_NCNT_WL_STA,
1250 BTC_NCNT_WL_STA_LAST,
1251 BTC_NCNT_FWINFO,
1252 BTC_NCNT_TIMER,
1253 BTC_NCNT_SWITCH_CHBW,
1254 BTC_NCNT_RESUME_DL_FW,
1255 BTC_NCNT_COUNTRYCODE,
1256 BTC_NCNT_NUM,
1257 };
1258
1259 enum rtw89_btc_btinfo {
1260 BTC_BTINFO_L0 = 0,
1261 BTC_BTINFO_L1,
1262 BTC_BTINFO_L2,
1263 BTC_BTINFO_L3,
1264 BTC_BTINFO_H0,
1265 BTC_BTINFO_H1,
1266 BTC_BTINFO_H2,
1267 BTC_BTINFO_H3,
1268 BTC_BTINFO_MAX
1269 };
1270
1271 enum rtw89_btc_dcnt {
1272 BTC_DCNT_RUN = 0x0,
1273 BTC_DCNT_CX_RUNINFO,
1274 BTC_DCNT_RPT,
1275 BTC_DCNT_RPT_HANG,
1276 BTC_DCNT_CYCLE,
1277 BTC_DCNT_CYCLE_HANG,
1278 BTC_DCNT_W1,
1279 BTC_DCNT_W1_HANG,
1280 BTC_DCNT_B1,
1281 BTC_DCNT_B1_HANG,
1282 BTC_DCNT_TDMA_NONSYNC,
1283 BTC_DCNT_SLOT_NONSYNC,
1284 BTC_DCNT_BTCNT_HANG,
1285 BTC_DCNT_BTTX_HANG,
1286 BTC_DCNT_WL_SLOT_DRIFT,
1287 BTC_DCNT_WL_STA_LAST,
1288 BTC_DCNT_BT_SLOT_DRIFT,
1289 BTC_DCNT_BT_SLOT_FLOOD,
1290 BTC_DCNT_FDDT_TRIG,
1291 BTC_DCNT_E2G,
1292 BTC_DCNT_E2G_HANG,
1293 BTC_DCNT_WL_FW_VER_MATCH,
1294 BTC_DCNT_NULL_TX_FAIL,
1295 BTC_DCNT_WL_STA_NTFY,
1296 BTC_DCNT_NUM,
1297 };
1298
1299 enum rtw89_btc_wl_state_cnt {
1300 BTC_WCNT_SCANAP = 0x0,
1301 BTC_WCNT_DHCP,
1302 BTC_WCNT_EAPOL,
1303 BTC_WCNT_ARP,
1304 BTC_WCNT_SCBDUPDATE,
1305 BTC_WCNT_RFK_REQ,
1306 BTC_WCNT_RFK_GO,
1307 BTC_WCNT_RFK_REJECT,
1308 BTC_WCNT_RFK_TIMEOUT,
1309 BTC_WCNT_CH_UPDATE,
1310 BTC_WCNT_DBCC_ALL_2G,
1311 BTC_WCNT_DBCC_CHG,
1312 BTC_WCNT_RX_OK_LAST,
1313 BTC_WCNT_RX_OK_LAST2S,
1314 BTC_WCNT_RX_ERR_LAST,
1315 BTC_WCNT_RX_ERR_LAST2S,
1316 BTC_WCNT_RX_LAST,
1317 BTC_WCNT_NUM
1318 };
1319
1320 enum rtw89_btc_bt_state_cnt {
1321 BTC_BCNT_RETRY = 0x0,
1322 BTC_BCNT_REINIT,
1323 BTC_BCNT_REENABLE,
1324 BTC_BCNT_SCBDREAD,
1325 BTC_BCNT_RELINK,
1326 BTC_BCNT_IGNOWL,
1327 BTC_BCNT_INQPAG,
1328 BTC_BCNT_INQ,
1329 BTC_BCNT_PAGE,
1330 BTC_BCNT_ROLESW,
1331 BTC_BCNT_AFH,
1332 BTC_BCNT_INFOUPDATE,
1333 BTC_BCNT_INFOSAME,
1334 BTC_BCNT_SCBDUPDATE,
1335 BTC_BCNT_HIPRI_TX,
1336 BTC_BCNT_HIPRI_RX,
1337 BTC_BCNT_LOPRI_TX,
1338 BTC_BCNT_LOPRI_RX,
1339 BTC_BCNT_POLUT,
1340 BTC_BCNT_POLUT_NOW,
1341 BTC_BCNT_POLUT_DIFF,
1342 BTC_BCNT_RATECHG,
1343 BTC_BCNT_BTTXPWR_UPDATE,
1344 BTC_BCNT_NUM,
1345 };
1346
1347 enum rtw89_btc_bt_profile {
1348 BTC_BT_NOPROFILE = 0,
1349 BTC_BT_HFP = BIT(0),
1350 BTC_BT_HID = BIT(1),
1351 BTC_BT_A2DP = BIT(2),
1352 BTC_BT_PAN = BIT(3),
1353 BTC_PROFILE_MAX = 4,
1354 };
1355
1356 struct rtw89_btc_ant_info {
1357 u8 type; /* shared, dedicated */
1358 u8 num;
1359 u8 isolation;
1360
1361 u8 single_pos: 1;/* Single antenna at S0 or S1 */
1362 u8 diversity: 1;
1363 u8 btg_pos: 2;
1364 u8 stream_cnt: 4;
1365 };
1366
1367 struct rtw89_btc_ant_info_v7 {
1368 u8 type; /* shared, dedicated(non-shared) */
1369 u8 num; /* antenna count */
1370 u8 isolation;
1371 u8 single_pos;/* wifi 1ss-1ant at 0:S0 or 1:S1 */
1372
1373 u8 diversity; /* only for wifi use 1-antenna */
1374 u8 btg_pos; /* btg-circuit at 0:S0/1:S1/others:all */
1375 u8 stream_cnt; /* spatial_stream count */
1376 u8 rsvd;
1377 } __packed;
1378
1379 enum rtw89_tfc_dir {
1380 RTW89_TFC_UL,
1381 RTW89_TFC_DL,
1382 };
1383
1384 struct rtw89_btc_wl_smap {
1385 u32 busy: 1;
1386 u32 scan: 1;
1387 u32 connecting: 1;
1388 u32 roaming: 1;
1389 u32 dbccing: 1;
1390 u32 _4way: 1;
1391 u32 rf_off: 1;
1392 u32 lps: 2;
1393 u32 ips: 1;
1394 u32 init_ok: 1;
1395 u32 traffic_dir : 2;
1396 u32 rf_off_pre: 1;
1397 u32 lps_pre: 2;
1398 u32 lps_exiting: 1;
1399 u32 emlsr: 1;
1400 };
1401
1402 enum rtw89_tfc_interval {
1403 RTW89_TFC_INTERVAL_100MS,
1404 RTW89_TFC_INTERVAL_2SEC,
1405 };
1406
1407 enum rtw89_tfc_lv {
1408 RTW89_TFC_IDLE,
1409 RTW89_TFC_ULTRA_LOW,
1410 RTW89_TFC_LOW,
1411 RTW89_TFC_MID,
1412 RTW89_TFC_HIGH,
1413 };
1414
1415 DECLARE_EWMA(tp, 10, 2);
1416
1417 struct rtw89_traffic_stats {
1418 /* units in bytes */
1419 u64 tx_unicast;
1420 u64 rx_unicast;
1421 u32 tx_avg_len;
1422 u32 rx_avg_len;
1423
1424 /* count for packets */
1425 u64 tx_cnt;
1426 u64 rx_cnt;
1427
1428 /* units in Mbps */
1429 u32 tx_throughput;
1430 u32 rx_throughput;
1431 u32 tx_throughput_raw;
1432 u32 rx_throughput_raw;
1433
1434 u32 rx_tf_acc;
1435 u32 rx_tf_periodic;
1436
1437 enum rtw89_tfc_lv tx_tfc_lv;
1438 enum rtw89_tfc_lv rx_tfc_lv;
1439 struct ewma_tp tx_ewma_tp;
1440 struct ewma_tp rx_ewma_tp;
1441
1442 u16 tx_rate;
1443 u16 rx_rate;
1444 };
1445
1446 struct rtw89_btc_chdef {
1447 u8 center_ch;
1448 u8 band;
1449 u8 chan;
1450 enum rtw89_sc_offset offset;
1451 enum rtw89_bandwidth bw;
1452 };
1453
1454 struct rtw89_btc_statistic {
1455 u8 rssi; /* 0%~110% (dBm = rssi -110) */
1456 struct rtw89_traffic_stats traffic;
1457 };
1458
1459 #define BTC_WL_RSSI_THMAX 4
1460
1461 struct rtw89_btc_wl_link_info {
1462 struct rtw89_btc_chdef chdef;
1463 struct rtw89_btc_statistic stat;
1464 enum rtw89_tfc_dir dir;
1465 u8 rssi_state[BTC_WL_RSSI_THMAX];
1466 u8 mac_addr[ETH_ALEN];
1467 u8 busy;
1468 u8 ch;
1469 u8 bw;
1470 u8 band;
1471 u8 role;
1472 u8 pid;
1473 u8 phy;
1474 u8 dtim_period;
1475 u8 mode;
1476 u8 tx_1ss_limit;
1477
1478 u8 mac_id;
1479 u8 tx_retry;
1480
1481 u32 bcn_period;
1482 u32 busy_t;
1483 u32 tx_time;
1484 u32 client_cnt;
1485 u32 rx_rate_drop_cnt;
1486 u32 noa_duration;
1487
1488 u32 active: 1;
1489 u32 noa: 1;
1490 u32 client_ps: 1;
1491 u32 connected: 2;
1492 };
1493
1494 union rtw89_btc_wl_state_map {
1495 u32 val;
1496 struct rtw89_btc_wl_smap map;
1497 };
1498
1499 struct rtw89_btc_bt_hfp_desc {
1500 u32 exist: 1;
1501 u32 type: 2;
1502 u32 rsvd: 29;
1503 };
1504
1505 struct rtw89_btc_bt_hid_desc {
1506 u32 exist: 1;
1507 u32 slot_info: 2;
1508 u32 pair_cnt: 2;
1509 u32 type: 8;
1510 u32 rsvd: 19;
1511 };
1512
1513 struct rtw89_btc_bt_a2dp_desc {
1514 u8 exist: 1;
1515 u8 exist_last: 1;
1516 u8 play_latency: 1;
1517 u8 type: 3;
1518 u8 active: 1;
1519 u8 sink: 1;
1520 u32 handle_update: 1;
1521 u32 devinfo_query: 1;
1522 u32 no_empty_streak_2s: 8;
1523 u32 no_empty_streak_max: 8;
1524 u32 rsvd: 6;
1525
1526 u8 bitpool;
1527 u16 vendor_id;
1528 u32 device_name;
1529 u32 flush_time;
1530 };
1531
1532 struct rtw89_btc_bt_pan_desc {
1533 u32 exist: 1;
1534 u32 type: 1;
1535 u32 active: 1;
1536 u32 rsvd: 29;
1537 };
1538
1539 struct rtw89_btc_bt_rfk_info {
1540 u32 run: 1;
1541 u32 req: 1;
1542 u32 timeout: 1;
1543 u32 rsvd: 29;
1544 };
1545
1546 union rtw89_btc_bt_rfk_info_map {
1547 u32 val;
1548 struct rtw89_btc_bt_rfk_info map;
1549 };
1550
1551 struct rtw89_btc_bt_ver_info {
1552 u32 fw_coex; /* match with which coex_ver */
1553 u32 fw;
1554 };
1555
1556 struct rtw89_btc_bool_sta_chg {
1557 u32 now: 1;
1558 u32 last: 1;
1559 u32 remain: 1;
1560 u32 srvd: 29;
1561 };
1562
1563 struct rtw89_btc_u8_sta_chg {
1564 u8 now;
1565 u8 last;
1566 u8 remain;
1567 u8 rsvd;
1568 };
1569
1570 struct rtw89_btc_wl_scan_info {
1571 u8 band[RTW89_PHY_NUM];
1572 u8 phy_map;
1573 u8 rsvd;
1574 };
1575
1576 struct rtw89_btc_wl_dbcc_info {
1577 u8 op_band[RTW89_PHY_NUM]; /* op band in each phy */
1578 u8 scan_band[RTW89_PHY_NUM]; /* scan band in each phy */
1579 u8 real_band[RTW89_PHY_NUM];
1580 u8 role[RTW89_PHY_NUM]; /* role in each phy */
1581 };
1582
1583 struct rtw89_btc_wl_mlo_info {
1584 u8 wmode[RTW89_PHY_NUM]; /* enum phl_mr_wmode */
1585 u8 ch_type[RTW89_PHY_NUM]; /* enum phl_mr_ch_type */
1586 u8 hwb_rf_band[RTW89_PHY_NUM]; /* enum band_type, RF-band for HW-band */
1587 u8 path_rf_band[RTW89_PHY_NUM]; /* enum band_type, RF-band for PHY0/1 */
1588
1589 u8 wtype; /* enum phl_mr_wtype */
1590 u8 mrcx_mode;
1591 u8 mrcx_act_hwb_map;
1592 u8 mrcx_bt_slot_rsp;
1593
1594 u8 rf_combination; /* enum btc_mlo_rf_combin 0:2+0, 1:0+2, 2:1+1,3:2+2 */
1595 u8 mlo_en; /* MLO enable */
1596 u8 mlo_adie; /* a-die count */
1597 u8 dual_hw_band_en; /* both 2 HW-band link exist */
1598
1599 u32 link_status; /* enum mlo_dbcc_mode_type */
1600 };
1601
1602 struct rtw89_btc_wl_active_role {
1603 u8 connected: 1;
1604 u8 pid: 3;
1605 u8 phy: 1;
1606 u8 noa: 1;
1607 u8 band: 2;
1608
1609 u8 client_ps: 1;
1610 u8 bw: 7;
1611
1612 u8 role;
1613 u8 ch;
1614
1615 u16 tx_lvl;
1616 u16 rx_lvl;
1617 u16 tx_rate;
1618 u16 rx_rate;
1619 };
1620
1621 struct rtw89_btc_wl_active_role_v1 {
1622 u8 connected: 1;
1623 u8 pid: 3;
1624 u8 phy: 1;
1625 u8 noa: 1;
1626 u8 band: 2;
1627
1628 u8 client_ps: 1;
1629 u8 bw: 7;
1630
1631 u8 role;
1632 u8 ch;
1633
1634 u16 tx_lvl;
1635 u16 rx_lvl;
1636 u16 tx_rate;
1637 u16 rx_rate;
1638
1639 u32 noa_duration; /* ms */
1640 };
1641
1642 struct rtw89_btc_wl_active_role_v2 {
1643 u8 connected: 1;
1644 u8 pid: 3;
1645 u8 phy: 1;
1646 u8 noa: 1;
1647 u8 band: 2;
1648
1649 u8 client_ps: 1;
1650 u8 bw: 7;
1651
1652 u8 role;
1653 u8 ch;
1654
1655 u32 noa_duration; /* ms */
1656 };
1657
1658 struct rtw89_btc_wl_active_role_v7 {
1659 u8 connected;
1660 u8 pid;
1661 u8 phy;
1662 u8 noa;
1663
1664 u8 band;
1665 u8 client_ps;
1666 u8 bw;
1667 u8 role;
1668
1669 u8 ch;
1670 u8 noa_dur;
1671 u8 client_cnt;
1672 u8 rsvd2;
1673 } __packed;
1674
1675 struct rtw89_btc_wl_role_info_bpos {
1676 u16 none: 1;
1677 u16 station: 1;
1678 u16 ap: 1;
1679 u16 vap: 1;
1680 u16 adhoc: 1;
1681 u16 adhoc_master: 1;
1682 u16 mesh: 1;
1683 u16 moniter: 1;
1684 u16 p2p_device: 1;
1685 u16 p2p_gc: 1;
1686 u16 p2p_go: 1;
1687 u16 nan: 1;
1688 };
1689
1690 struct rtw89_btc_wl_scc_ctrl {
1691 u8 null_role1;
1692 u8 null_role2;
1693 u8 ebt_null; /* if tx null at EBT slot */
1694 };
1695
1696 union rtw89_btc_wl_role_info_map {
1697 u16 val;
1698 struct rtw89_btc_wl_role_info_bpos role;
1699 };
1700
1701 struct rtw89_btc_wl_role_info { /* struct size must be n*4 bytes */
1702 u8 connect_cnt;
1703 u8 link_mode;
1704 union rtw89_btc_wl_role_info_map role_map;
1705 struct rtw89_btc_wl_active_role active_role[RTW89_PORT_NUM];
1706 };
1707
1708 struct rtw89_btc_wl_role_info_v1 { /* struct size must be n*4 bytes */
1709 u8 connect_cnt;
1710 u8 link_mode;
1711 union rtw89_btc_wl_role_info_map role_map;
1712 struct rtw89_btc_wl_active_role_v1 active_role_v1[RTW89_PORT_NUM];
1713 u32 mrole_type; /* btc_wl_mrole_type */
1714 u32 mrole_noa_duration; /* ms */
1715
1716 u32 dbcc_en: 1;
1717 u32 dbcc_chg: 1;
1718 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */
1719 u32 link_mode_chg: 1;
1720 u32 rsvd: 27;
1721 };
1722
1723 struct rtw89_btc_wl_role_info_v2 { /* struct size must be n*4 bytes */
1724 u8 connect_cnt;
1725 u8 link_mode;
1726 union rtw89_btc_wl_role_info_map role_map;
1727 struct rtw89_btc_wl_active_role_v2 active_role_v2[RTW89_PORT_NUM];
1728 u32 mrole_type; /* btc_wl_mrole_type */
1729 u32 mrole_noa_duration; /* ms */
1730
1731 u32 dbcc_en: 1;
1732 u32 dbcc_chg: 1;
1733 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */
1734 u32 link_mode_chg: 1;
1735 u32 rsvd: 27;
1736 };
1737
1738 struct rtw89_btc_wl_rlink { /* H2C info, struct size must be n*4 bytes */
1739 u8 connected;
1740 u8 pid;
1741 u8 phy;
1742 u8 noa;
1743
1744 u8 rf_band; /* enum band_type RF band: 2.4G/5G/6G */
1745 u8 active; /* 0:rlink is under doze */
1746 u8 bw; /* enum channel_width */
1747 u8 role; /*enum role_type */
1748
1749 u8 ch;
1750 u8 noa_dur; /* ms */
1751 u8 client_cnt; /* for Role = P2P-Go/AP */
1752 u8 mode; /* wifi protocol */
1753 } __packed;
1754
1755 #define RTW89_BE_BTC_WL_MAX_ROLE_NUMBER 6
1756 struct rtw89_btc_wl_role_info_v7 { /* struct size must be n*4 bytes */
1757 u8 connect_cnt;
1758 u8 link_mode;
1759 u8 link_mode_chg;
1760 u8 p2p_2g;
1761
1762 struct rtw89_btc_wl_active_role_v7 active_role[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER];
1763
1764 u32 role_map;
1765 u32 mrole_type; /* btc_wl_mrole_type */
1766 u32 mrole_noa_duration; /* ms */
1767 u32 dbcc_en;
1768 u32 dbcc_chg;
1769 u32 dbcc_2g_phy; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */
1770 } __packed;
1771
1772 struct rtw89_btc_wl_role_info_v8 { /* H2C info, struct size must be n*4 bytes */
1773 u8 connect_cnt;
1774 u8 link_mode;
1775 u8 link_mode_chg;
1776 u8 p2p_2g;
1777
1778 u8 pta_req_band;
1779 u8 dbcc_en; /* 1+1 and 2.4G-included */
1780 u8 dbcc_chg;
1781 u8 dbcc_2g_phy; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */
1782
1783 struct rtw89_btc_wl_rlink rlink[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER][RTW89_MAC_NUM];
1784
1785 u32 role_map;
1786 u32 mrole_type; /* btc_wl_mrole_type */
1787 u32 mrole_noa_duration; /* ms */
1788 } __packed;
1789
1790 struct rtw89_btc_wl_ver_info {
1791 u32 fw_coex; /* match with which coex_ver */
1792 u32 fw;
1793 u32 mac;
1794 u32 bb;
1795 u32 rf;
1796 };
1797
1798 struct rtw89_btc_wl_afh_info {
1799 u8 en;
1800 u8 ch;
1801 u8 bw;
1802 u8 rsvd;
1803 } __packed;
1804
1805 struct rtw89_btc_wl_rfk_info {
1806 u32 state: 2;
1807 u32 path_map: 4;
1808 u32 phy_map: 2;
1809 u32 band: 2;
1810 u32 type: 8;
1811 u32 con_rfk: 1;
1812 u32 rsvd: 13;
1813
1814 u32 start_time;
1815 u32 proc_time;
1816 };
1817
1818 struct rtw89_btc_bt_smap {
1819 u32 connect: 1;
1820 u32 ble_connect: 1;
1821 u32 acl_busy: 1;
1822 u32 sco_busy: 1;
1823 u32 mesh_busy: 1;
1824 u32 inq_pag: 1;
1825 };
1826
1827 union rtw89_btc_bt_state_map {
1828 u32 val;
1829 struct rtw89_btc_bt_smap map;
1830 };
1831
1832 #define BTC_BT_RSSI_THMAX 4
1833 #define BTC_BT_AFH_GROUP 12
1834 #define BTC_BT_AFH_LE_GROUP 5
1835
1836 struct rtw89_btc_bt_txpwr_desc {
1837 s8 br_dbm;
1838 s8 le_dbm;
1839 u8 br_gain_index;
1840 u8 le_gain_index;
1841 };
1842
1843 struct rtw89_btc_bt_link_info {
1844 struct rtw89_btc_u8_sta_chg profile_cnt;
1845 struct rtw89_btc_bool_sta_chg multi_link;
1846 struct rtw89_btc_bool_sta_chg relink;
1847 struct rtw89_btc_bt_hfp_desc hfp_desc;
1848 struct rtw89_btc_bt_hid_desc hid_desc;
1849 struct rtw89_btc_bt_a2dp_desc a2dp_desc;
1850 struct rtw89_btc_bt_pan_desc pan_desc;
1851 union rtw89_btc_bt_state_map status;
1852 struct rtw89_btc_bt_txpwr_desc bt_txpwr_desc;
1853
1854 u8 sut_pwr_level[BTC_PROFILE_MAX];
1855 u8 golden_rx_shift[BTC_PROFILE_MAX];
1856 u8 rssi_state[BTC_BT_RSSI_THMAX];
1857 u8 afh_map[BTC_BT_AFH_GROUP];
1858 u8 afh_map_le[BTC_BT_AFH_LE_GROUP];
1859
1860 u32 role_sw: 1;
1861 u32 slave_role: 1;
1862 u32 afh_update: 1;
1863 u32 cqddr: 1;
1864 u32 rssi: 8;
1865 u32 tx_3m: 1;
1866 u32 rsvd: 19;
1867 };
1868
1869 struct rtw89_btc_3rdcx_info {
1870 u8 type; /* 0: none, 1:zigbee, 2:LTE */
1871 u8 hw_coex;
1872 u16 rsvd;
1873 };
1874
1875 struct rtw89_btc_dm_emap {
1876 u32 init: 1;
1877 u32 pta_owner: 1;
1878 u32 wl_rfk_timeout: 1;
1879 u32 bt_rfk_timeout: 1;
1880 u32 wl_fw_hang: 1;
1881 u32 cycle_hang: 1;
1882 u32 w1_hang: 1;
1883 u32 b1_hang: 1;
1884 u32 tdma_no_sync: 1;
1885 u32 slot_no_sync: 1;
1886 u32 wl_slot_drift: 1;
1887 u32 bt_slot_drift: 1;
1888 u32 role_num_mismatch: 1;
1889 u32 null1_tx_late: 1;
1890 u32 bt_afh_conflict: 1;
1891 u32 bt_leafh_conflict: 1;
1892 u32 bt_slot_flood: 1;
1893 u32 wl_e2g_hang: 1;
1894 u32 wl_ver_mismatch: 1;
1895 u32 bt_ver_mismatch: 1;
1896 u32 rfe_type0: 1;
1897 u32 h2c_buffer_over: 1;
1898 u32 bt_tx_hang: 1; /* for SNR too low bug, BT has no Tx req*/
1899 u32 wl_no_sta_ntfy: 1;
1900
1901 u32 h2c_bmap_mismatch: 1;
1902 u32 c2h_bmap_mismatch: 1;
1903 u32 h2c_struct_invalid: 1;
1904 u32 c2h_struct_invalid: 1;
1905 u32 h2c_c2h_buffer_mismatch: 1;
1906 };
1907
1908 union rtw89_btc_dm_error_map {
1909 u32 val;
1910 struct rtw89_btc_dm_emap map;
1911 };
1912
1913 struct rtw89_btc_rf_para {
1914 u32 tx_pwr_freerun;
1915 u32 rx_gain_freerun;
1916 u32 tx_pwr_perpkt;
1917 u32 rx_gain_perpkt;
1918 };
1919
1920 struct rtw89_btc_wl_nhm {
1921 u8 instant_wl_nhm_dbm;
1922 u8 instant_wl_nhm_per_mhz;
1923 u16 valid_record_times;
1924 s8 record_pwr[16];
1925 u8 record_ratio[16];
1926 s8 pwr; /* dbm_per_MHz */
1927 u8 ratio;
1928 u8 current_status;
1929 u8 refresh;
1930 bool start_flag;
1931 s8 pwr_max;
1932 s8 pwr_min;
1933 };
1934
1935 struct rtw89_btc_wl_info {
1936 struct rtw89_btc_wl_link_info link_info[RTW89_PORT_NUM];
1937 struct rtw89_btc_wl_link_info rlink_info[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER][RTW89_MAC_NUM];
1938 struct rtw89_btc_wl_rfk_info rfk_info;
1939 struct rtw89_btc_wl_ver_info ver_info;
1940 struct rtw89_btc_wl_afh_info afh_info;
1941 struct rtw89_btc_wl_role_info role_info;
1942 struct rtw89_btc_wl_role_info_v1 role_info_v1;
1943 struct rtw89_btc_wl_role_info_v2 role_info_v2;
1944 struct rtw89_btc_wl_role_info_v7 role_info_v7;
1945 struct rtw89_btc_wl_role_info_v8 role_info_v8;
1946 struct rtw89_btc_wl_scan_info scan_info;
1947 struct rtw89_btc_wl_dbcc_info dbcc_info;
1948 struct rtw89_btc_wl_mlo_info mlo_info;
1949 struct rtw89_btc_rf_para rf_para;
1950 struct rtw89_btc_wl_nhm nhm;
1951 union rtw89_btc_wl_state_map status;
1952
1953 u8 port_id[RTW89_WIFI_ROLE_MLME_MAX];
1954 u8 rssi_level;
1955 u8 cn_report;
1956 u8 coex_mode;
1957 u8 pta_req_mac;
1958 u8 bt_polut_type[RTW89_PHY_NUM]; /* BT polluted WL-Tx type for phy0/1 */
1959
1960 bool is_5g_hi_channel;
1961 bool go_client_exist;
1962 bool noa_exist;
1963 bool pta_reg_mac_chg;
1964 bool bg_mode;
1965 bool he_mode;
1966 bool scbd_change;
1967 bool fw_ver_mismatch;
1968 bool client_cnt_inc_2g;
1969 bool link_mode_chg;
1970 bool dbcc_chg;
1971 u32 scbd;
1972 };
1973
1974 struct rtw89_btc_module {
1975 struct rtw89_btc_ant_info ant;
1976 u8 rfe_type;
1977 u8 cv;
1978
1979 u8 bt_solo: 1;
1980 u8 bt_pos: 1;
1981 u8 switch_type: 1;
1982 u8 wa_type: 3;
1983
1984 u8 kt_ver_adie;
1985 };
1986
1987 struct rtw89_btc_module_v7 {
1988 u8 rfe_type;
1989 u8 kt_ver;
1990 u8 bt_solo;
1991 u8 bt_pos; /* wl-end view: get from efuse, must compare bt.btg_type*/
1992
1993 u8 switch_type; /* WL/BT switch type: 0: internal, 1: external */
1994 u8 wa_type; /* WA type: 0:none, 1: 51B 5G_Hi-Ch_Rx */
1995 u8 kt_ver_adie;
1996 u8 rsvd;
1997
1998 struct rtw89_btc_ant_info_v7 ant;
1999 } __packed;
2000
2001 union rtw89_btc_module_info {
2002 struct rtw89_btc_module md;
2003 struct rtw89_btc_module_v7 md_v7;
2004 };
2005
2006 #define RTW89_BTC_DM_MAXSTEP 30
2007 #define RTW89_BTC_DM_CNT_MAX (RTW89_BTC_DM_MAXSTEP * 8)
2008
2009 struct rtw89_btc_dm_step {
2010 u16 step[RTW89_BTC_DM_MAXSTEP];
2011 u8 step_pos;
2012 bool step_ov;
2013 };
2014
2015 struct rtw89_btc_init_info {
2016 struct rtw89_btc_module module;
2017 u8 wl_guard_ch;
2018
2019 u8 wl_only: 1;
2020 u8 wl_init_ok: 1;
2021 u8 dbcc_en: 1;
2022 u8 cx_other: 1;
2023 u8 bt_only: 1;
2024
2025 u16 rsvd;
2026 };
2027
2028 struct rtw89_btc_init_info_v7 {
2029 u8 wl_guard_ch;
2030 u8 wl_only;
2031 u8 wl_init_ok;
2032 u8 rsvd3;
2033
2034 u8 cx_other;
2035 u8 bt_only;
2036 u8 pta_mode;
2037 u8 pta_direction;
2038
2039 struct rtw89_btc_module_v7 module;
2040 } __packed;
2041
2042 union rtw89_btc_init_info_u {
2043 struct rtw89_btc_init_info init;
2044 struct rtw89_btc_init_info_v7 init_v7;
2045 };
2046
2047 struct rtw89_btc_wl_tx_limit_para {
2048 u16 enable;
2049 u32 tx_time; /* unit: us */
2050 u16 tx_retry;
2051 };
2052
2053 enum rtw89_btc_bt_scan_type {
2054 BTC_SCAN_INQ = 0,
2055 BTC_SCAN_PAGE,
2056 BTC_SCAN_BLE,
2057 BTC_SCAN_INIT,
2058 BTC_SCAN_TV,
2059 BTC_SCAN_ADV,
2060 BTC_SCAN_MAX1,
2061 };
2062
2063 enum rtw89_btc_ble_scan_type {
2064 CXSCAN_BG = 0,
2065 CXSCAN_INIT,
2066 CXSCAN_LE,
2067 CXSCAN_MAX
2068 };
2069
2070 #define RTW89_BTC_BTC_SCAN_V1_FLAG_ENABLE BIT(0)
2071 #define RTW89_BTC_BTC_SCAN_V1_FLAG_INTERLACE BIT(1)
2072
2073 struct rtw89_btc_bt_scan_info_v1 {
2074 __le16 win;
2075 __le16 intvl;
2076 __le32 flags;
2077 } __packed;
2078
2079 struct rtw89_btc_bt_scan_info_v2 {
2080 __le16 win;
2081 __le16 intvl;
2082 } __packed;
2083
2084 struct rtw89_btc_fbtc_btscan_v1 {
2085 u8 fver; /* btc_ver::fcxbtscan */
2086 u8 rsvd;
2087 __le16 rsvd2;
2088 struct rtw89_btc_bt_scan_info_v1 scan[BTC_SCAN_MAX1];
2089 } __packed;
2090
2091 struct rtw89_btc_fbtc_btscan_v2 {
2092 u8 fver; /* btc_ver::fcxbtscan */
2093 u8 type;
2094 __le16 rsvd2;
2095 struct rtw89_btc_bt_scan_info_v2 para[CXSCAN_MAX];
2096 } __packed;
2097
2098 struct rtw89_btc_fbtc_btscan_v7 {
2099 u8 fver; /* btc_ver::fcxbtscan */
2100 u8 type;
2101 u8 rsvd0;
2102 u8 rsvd1;
2103 struct rtw89_btc_bt_scan_info_v2 para[CXSCAN_MAX];
2104 } __packed;
2105
2106 union rtw89_btc_fbtc_btscan {
2107 struct rtw89_btc_fbtc_btscan_v1 v1;
2108 struct rtw89_btc_fbtc_btscan_v2 v2;
2109 struct rtw89_btc_fbtc_btscan_v7 v7;
2110 };
2111
2112 struct rtw89_btc_bt_info {
2113 struct rtw89_btc_bt_link_info link_info;
2114 struct rtw89_btc_bt_scan_info_v1 scan_info_v1[BTC_SCAN_MAX1];
2115 struct rtw89_btc_bt_scan_info_v2 scan_info_v2[CXSCAN_MAX];
2116 struct rtw89_btc_bt_ver_info ver_info;
2117 struct rtw89_btc_bool_sta_chg enable;
2118 struct rtw89_btc_bool_sta_chg inq_pag;
2119 struct rtw89_btc_rf_para rf_para;
2120 union rtw89_btc_bt_rfk_info_map rfk_info;
2121
2122 u8 raw_info[BTC_BTINFO_MAX]; /* raw bt info from mailbox */
2123 u8 txpwr_info[BTC_BTINFO_MAX];
2124 u8 rssi_level;
2125
2126 u32 scbd;
2127 u32 feature;
2128
2129 u32 mbx_avl: 1;
2130 u32 whql_test: 1;
2131 u32 igno_wl: 1;
2132 u32 reinit: 1;
2133 u32 ble_scan_en: 1;
2134 u32 btg_type: 1;
2135 u32 inq: 1;
2136 u32 pag: 1;
2137 u32 run_patch_code: 1;
2138 u32 hi_lna_rx: 1;
2139 u32 scan_rx_low_pri: 1;
2140 u32 scan_info_update: 1;
2141 u32 lna_constrain: 3;
2142 u32 rsvd: 17;
2143 };
2144
2145 struct rtw89_btc_cx {
2146 struct rtw89_btc_wl_info wl;
2147 struct rtw89_btc_bt_info bt;
2148 struct rtw89_btc_3rdcx_info other;
2149 u32 state_map;
2150 u32 cnt_bt[BTC_BCNT_NUM];
2151 u32 cnt_wl[BTC_WCNT_NUM];
2152 };
2153
2154 struct rtw89_btc_fbtc_tdma {
2155 u8 type; /* btc_ver::fcxtdma */
2156 u8 rxflctrl;
2157 u8 txpause;
2158 u8 wtgle_n;
2159 u8 leak_n;
2160 u8 ext_ctrl;
2161 u8 rxflctrl_role;
2162 u8 option_ctrl;
2163 } __packed;
2164
2165 struct rtw89_btc_fbtc_tdma_v3 {
2166 u8 fver; /* btc_ver::fcxtdma */
2167 u8 rsvd;
2168 __le16 rsvd1;
2169 struct rtw89_btc_fbtc_tdma tdma;
2170 } __packed;
2171
2172 union rtw89_btc_fbtc_tdma_le32 {
2173 struct rtw89_btc_fbtc_tdma v1;
2174 struct rtw89_btc_fbtc_tdma_v3 v3;
2175 };
2176
2177 #define CXMREG_MAX 30
2178 #define CXMREG_MAX_V2 20
2179 #define FCXMAX_STEP 255 /*STEP trace record cnt, Max:65535, default:255*/
2180 #define BTC_CYCLE_SLOT_MAX 48 /* must be even number, non-zero */
2181
2182 enum rtw89_btc_bt_sta_counter {
2183 BTC_BCNT_RFK_REQ = 0,
2184 BTC_BCNT_RFK_GO = 1,
2185 BTC_BCNT_RFK_REJECT = 2,
2186 BTC_BCNT_RFK_FAIL = 3,
2187 BTC_BCNT_RFK_TIMEOUT = 4,
2188 BTC_BCNT_HI_TX = 5,
2189 BTC_BCNT_HI_RX = 6,
2190 BTC_BCNT_LO_TX = 7,
2191 BTC_BCNT_LO_RX = 8,
2192 BTC_BCNT_POLLUTED = 9,
2193 BTC_BCNT_STA_MAX
2194 };
2195
2196 enum rtw89_btc_bt_sta_counter_v105 {
2197 BTC_BCNT_RFK_REQ_V105 = 0,
2198 BTC_BCNT_HI_TX_V105 = 1,
2199 BTC_BCNT_HI_RX_V105 = 2,
2200 BTC_BCNT_LO_TX_V105 = 3,
2201 BTC_BCNT_LO_RX_V105 = 4,
2202 BTC_BCNT_POLLUTED_V105 = 5,
2203 BTC_BCNT_STA_MAX_V105
2204 };
2205
2206 struct rtw89_btc_fbtc_rpt_ctrl_v1 {
2207 u16 fver; /* btc_ver::fcxbtcrpt */
2208 u16 rpt_cnt; /* tmr counters */
2209 u32 wl_fw_coex_ver; /* match which driver's coex version */
2210 u32 wl_fw_cx_offload;
2211 u32 wl_fw_ver;
2212 u32 rpt_enable;
2213 u32 rpt_para; /* ms */
2214 u32 mb_send_fail_cnt; /* fw send mailbox fail counter */
2215 u32 mb_send_ok_cnt; /* fw send mailbox ok counter */
2216 u32 mb_recv_cnt; /* fw recv mailbox counter */
2217 u32 mb_a2dp_empty_cnt; /* a2dp empty count */
2218 u32 mb_a2dp_flct_cnt; /* a2dp empty flow control counter */
2219 u32 mb_a2dp_full_cnt; /* a2dp empty full counter */
2220 u32 bt_rfk_cnt[BTC_BCNT_HI_TX];
2221 u32 c2h_cnt; /* fw send c2h counter */
2222 u32 h2c_cnt; /* fw recv h2c counter */
2223 } __packed;
2224
2225 struct rtw89_btc_fbtc_rpt_ctrl_info {
2226 __le32 cnt; /* fw report counter */
2227 __le32 en; /* report map */
2228 __le32 para; /* not used */
2229
2230 __le32 cnt_c2h; /* fw send c2h counter */
2231 __le32 cnt_h2c; /* fw recv h2c counter */
2232 __le32 len_c2h; /* The total length of the last C2H */
2233
2234 __le32 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */
2235 __le32 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */
2236 } __packed;
2237
2238 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 {
2239 __le32 cx_ver; /* match which driver's coex version */
2240 __le32 fw_ver;
2241 __le32 en; /* report map */
2242
2243 __le16 cnt; /* fw report counter */
2244 __le16 cnt_c2h; /* fw send c2h counter */
2245 __le16 cnt_h2c; /* fw recv h2c counter */
2246 __le16 len_c2h; /* The total length of the last C2H */
2247
2248 __le16 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */
2249 __le16 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */
2250 } __packed;
2251
2252 struct rtw89_btc_fbtc_rpt_ctrl_info_v8 {
2253 __le16 cnt; /* fw report counter */
2254 __le16 cnt_c2h; /* fw send c2h counter */
2255 __le16 cnt_h2c; /* fw recv h2c counter */
2256 __le16 len_c2h; /* The total length of the last C2H */
2257
2258 __le16 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */
2259 __le16 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */
2260
2261 __le32 cx_ver; /* match which driver's coex version */
2262 __le32 fw_ver;
2263 __le32 en; /* report map */
2264 } __packed;
2265
2266 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info {
2267 __le32 cx_ver; /* match which driver's coex version */
2268 __le32 cx_offload;
2269 __le32 fw_ver;
2270 } __packed;
2271
2272 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty {
2273 __le32 cnt_empty; /* a2dp empty count */
2274 __le32 cnt_flowctrl; /* a2dp empty flow control counter */
2275 __le32 cnt_tx;
2276 __le32 cnt_ack;
2277 __le32 cnt_nack;
2278 } __packed;
2279
2280 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox {
2281 __le32 cnt_send_ok; /* fw send mailbox ok counter */
2282 __le32 cnt_send_fail; /* fw send mailbox fail counter */
2283 __le32 cnt_recv; /* fw recv mailbox counter */
2284 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty a2dp;
2285 } __packed;
2286
2287 struct rtw89_btc_fbtc_rpt_ctrl_v4 {
2288 u8 fver;
2289 u8 rsvd;
2290 __le16 rsvd1;
2291 struct rtw89_btc_fbtc_rpt_ctrl_info rpt_info;
2292 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info wl_fw_info;
2293 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info;
2294 __le32 bt_cnt[BTC_BCNT_STA_MAX];
2295 struct rtw89_mac_ax_gnt gnt_val[RTW89_PHY_NUM];
2296 } __packed;
2297
2298 struct rtw89_btc_fbtc_rpt_ctrl_v5 {
2299 u8 fver;
2300 u8 rsvd;
2301 __le16 rsvd1;
2302
2303 u8 gnt_val[RTW89_PHY_NUM][4];
2304 __le16 bt_cnt[BTC_BCNT_STA_MAX];
2305
2306 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info;
2307 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info;
2308 } __packed;
2309
2310 struct rtw89_btc_fbtc_rpt_ctrl_v105 {
2311 u8 fver;
2312 u8 rsvd;
2313 __le16 rsvd1;
2314
2315 u8 gnt_val[RTW89_PHY_NUM][4];
2316 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105];
2317
2318 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info;
2319 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info;
2320 } __packed;
2321
2322 struct rtw89_btc_fbtc_rpt_ctrl_v7 {
2323 u8 fver;
2324 u8 rsvd0;
2325 u8 rsvd1;
2326 u8 rsvd2;
2327
2328 u8 gnt_val[RTW89_PHY_NUM][4];
2329 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105];
2330
2331 struct rtw89_btc_fbtc_rpt_ctrl_info_v8 rpt_info;
2332 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info;
2333 } __packed;
2334
2335 struct rtw89_btc_fbtc_rpt_ctrl_v8 {
2336 u8 fver;
2337 u8 rsvd0;
2338 u8 rpt_len_max_l; /* BTC_RPT_MAX bit0~7 */
2339 u8 rpt_len_max_h; /* BTC_RPT_MAX bit8~15 */
2340
2341 u8 gnt_val[RTW89_PHY_NUM][4];
2342 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105];
2343
2344 struct rtw89_btc_fbtc_rpt_ctrl_info_v8 rpt_info;
2345 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info;
2346 } __packed;
2347
2348 union rtw89_btc_fbtc_rpt_ctrl_ver_info {
2349 struct rtw89_btc_fbtc_rpt_ctrl_v1 v1;
2350 struct rtw89_btc_fbtc_rpt_ctrl_v4 v4;
2351 struct rtw89_btc_fbtc_rpt_ctrl_v5 v5;
2352 struct rtw89_btc_fbtc_rpt_ctrl_v105 v105;
2353 struct rtw89_btc_fbtc_rpt_ctrl_v7 v7;
2354 struct rtw89_btc_fbtc_rpt_ctrl_v8 v8;
2355 };
2356
2357 enum rtw89_fbtc_ext_ctrl_type {
2358 CXECTL_OFF = 0x0, /* tdma off */
2359 CXECTL_B2 = 0x1, /* allow B2 (beacon-early) */
2360 CXECTL_EXT = 0x2,
2361 CXECTL_MAX
2362 };
2363
2364 union rtw89_btc_fbtc_rxflct {
2365 u8 val;
2366 u8 type: 3;
2367 u8 tgln_n: 5;
2368 };
2369
2370 enum rtw89_btc_cxst_state {
2371 CXST_OFF = 0x0,
2372 CXST_B2W = 0x1,
2373 CXST_W1 = 0x2,
2374 CXST_W2 = 0x3,
2375 CXST_W2B = 0x4,
2376 CXST_B1 = 0x5,
2377 CXST_B2 = 0x6,
2378 CXST_B3 = 0x7,
2379 CXST_B4 = 0x8,
2380 CXST_LK = 0x9,
2381 CXST_BLK = 0xa,
2382 CXST_E2G = 0xb,
2383 CXST_E5G = 0xc,
2384 CXST_EBT = 0xd,
2385 CXST_ENULL = 0xe,
2386 CXST_WLK = 0xf,
2387 CXST_W1FDD = 0x10,
2388 CXST_B1FDD = 0x11,
2389 CXST_MAX = 0x12,
2390 };
2391
2392 enum rtw89_btc_cxevnt {
2393 CXEVNT_TDMA_ENTRY = 0x0,
2394 CXEVNT_WL_TMR,
2395 CXEVNT_B1_TMR,
2396 CXEVNT_B2_TMR,
2397 CXEVNT_B3_TMR,
2398 CXEVNT_B4_TMR,
2399 CXEVNT_W2B_TMR,
2400 CXEVNT_B2W_TMR,
2401 CXEVNT_BCN_EARLY,
2402 CXEVNT_A2DP_EMPTY,
2403 CXEVNT_LK_END,
2404 CXEVNT_RX_ISR,
2405 CXEVNT_RX_FC0,
2406 CXEVNT_RX_FC1,
2407 CXEVNT_BT_RELINK,
2408 CXEVNT_BT_RETRY,
2409 CXEVNT_E2G,
2410 CXEVNT_E5G,
2411 CXEVNT_EBT,
2412 CXEVNT_ENULL,
2413 CXEVNT_DRV_WLK,
2414 CXEVNT_BCN_OK,
2415 CXEVNT_BT_CHANGE,
2416 CXEVNT_EBT_EXTEND,
2417 CXEVNT_E2G_NULL1,
2418 CXEVNT_B1FDD_TMR,
2419 CXEVNT_MAX
2420 };
2421
2422 enum {
2423 CXBCN_ALL = 0x0,
2424 CXBCN_ALL_OK,
2425 CXBCN_BT_SLOT,
2426 CXBCN_BT_OK,
2427 CXBCN_MAX
2428 };
2429
2430 enum btc_slot_type {
2431 SLOT_MIX = 0x0, /* accept BT Lower-Pri Tx/Rx request 0x778 = 1 */
2432 SLOT_ISO = 0x1, /* no accept BT Lower-Pri Tx/Rx request 0x778 = d*/
2433 CXSTYPE_NUM,
2434 };
2435
2436 enum { /* TIME */
2437 CXT_BT = 0x0,
2438 CXT_WL = 0x1,
2439 CXT_MAX
2440 };
2441
2442 enum { /* TIME-A2DP */
2443 CXT_FLCTRL_OFF = 0x0,
2444 CXT_FLCTRL_ON = 0x1,
2445 CXT_FLCTRL_MAX
2446 };
2447
2448 enum { /* STEP TYPE */
2449 CXSTEP_NONE = 0x0,
2450 CXSTEP_EVNT = 0x1,
2451 CXSTEP_SLOT = 0x2,
2452 CXSTEP_MAX,
2453 };
2454
2455 enum rtw89_btc_afh_map_type { /*AFH MAP TYPE */
2456 RPT_BT_AFH_SEQ_LEGACY = 0x10,
2457 RPT_BT_AFH_SEQ_LE = 0x20
2458 };
2459
2460 #define BTC_DBG_MAX1 32
2461 struct rtw89_btc_fbtc_gpio_dbg_v1 {
2462 u8 fver; /* btc_ver::fcxgpiodbg */
2463 u8 rsvd;
2464 __le16 rsvd2;
2465 __le32 en_map; /* which debug signal (see btc_wl_gpio_debug) is enable */
2466 __le32 pre_state; /* the debug signal is 1 or 0 */
2467 u8 gpio_map[BTC_DBG_MAX1]; /*the debug signals to GPIO-Position */
2468 } __packed;
2469
2470 struct rtw89_btc_fbtc_gpio_dbg_v7 {
2471 u8 fver;
2472 u8 rsvd0;
2473 u8 rsvd1;
2474 u8 rsvd2;
2475
2476 u8 gpio_map[BTC_DBG_MAX1];
2477
2478 __le32 en_map;
2479 __le32 pre_state;
2480 } __packed;
2481
2482 union rtw89_btc_fbtc_gpio_dbg {
2483 struct rtw89_btc_fbtc_gpio_dbg_v1 v1;
2484 struct rtw89_btc_fbtc_gpio_dbg_v7 v7;
2485 };
2486
2487 struct rtw89_btc_fbtc_mreg_val_v1 {
2488 u8 fver; /* btc_ver::fcxmreg */
2489 u8 reg_num;
2490 __le16 rsvd;
2491 __le32 mreg_val[CXMREG_MAX];
2492 } __packed;
2493
2494 struct rtw89_btc_fbtc_mreg_val_v2 {
2495 u8 fver; /* btc_ver::fcxmreg */
2496 u8 reg_num;
2497 __le16 rsvd;
2498 __le32 mreg_val[CXMREG_MAX_V2];
2499 } __packed;
2500
2501 struct rtw89_btc_fbtc_mreg_val_v7 {
2502 u8 fver;
2503 u8 reg_num;
2504 u8 rsvd0;
2505 u8 rsvd1;
2506 __le32 mreg_val[CXMREG_MAX_V2];
2507 } __packed;
2508
2509 union rtw89_btc_fbtc_mreg_val {
2510 struct rtw89_btc_fbtc_mreg_val_v1 v1;
2511 struct rtw89_btc_fbtc_mreg_val_v2 v2;
2512 struct rtw89_btc_fbtc_mreg_val_v7 v7;
2513 };
2514
2515 #define RTW89_DEF_FBTC_MREG(__type, __bytes, __offset) \
2516 { .type = cpu_to_le16(__type), .bytes = cpu_to_le16(__bytes), \
2517 .offset = cpu_to_le32(__offset), }
2518
2519 struct rtw89_btc_fbtc_mreg {
2520 __le16 type;
2521 __le16 bytes;
2522 __le32 offset;
2523 } __packed;
2524
2525 struct rtw89_btc_fbtc_slot {
2526 __le16 dur;
2527 __le32 cxtbl;
2528 __le16 cxtype;
2529 } __packed;
2530
2531 struct rtw89_btc_fbtc_slots {
2532 u8 fver; /* btc_ver::fcxslots */
2533 u8 tbl_num;
2534 __le16 rsvd;
2535 __le32 update_map;
2536 struct rtw89_btc_fbtc_slot slot[CXST_MAX];
2537 } __packed;
2538
2539 struct rtw89_btc_fbtc_slot_v7 {
2540 __le16 dur; /* slot duration */
2541 __le16 cxtype;
2542 __le32 cxtbl;
2543 } __packed;
2544
2545 struct rtw89_btc_fbtc_slot_u16 {
2546 __le16 dur; /* slot duration */
2547 __le16 cxtype;
2548 __le16 cxtbl_l16; /* coex table [15:0] */
2549 __le16 cxtbl_h16; /* coex table [31:16] */
2550 } __packed;
2551
2552 struct rtw89_btc_fbtc_1slot_v7 {
2553 u8 fver;
2554 u8 sid; /* slot id */
2555 __le16 rsvd;
2556 struct rtw89_btc_fbtc_slot_v7 slot;
2557 } __packed;
2558
2559 struct rtw89_btc_fbtc_slots_v7 {
2560 u8 fver;
2561 u8 slot_cnt;
2562 u8 rsvd0;
2563 u8 rsvd1;
2564 struct rtw89_btc_fbtc_slot_u16 slot[CXST_MAX];
2565 __le32 update_map;
2566 } __packed;
2567
2568 union rtw89_btc_fbtc_slots_info {
2569 struct rtw89_btc_fbtc_slots v1;
2570 struct rtw89_btc_fbtc_slots_v7 v7;
2571 } __packed;
2572
2573 struct rtw89_btc_fbtc_step {
2574 u8 type;
2575 u8 val;
2576 __le16 difft;
2577 } __packed;
2578
2579 struct rtw89_btc_fbtc_steps_v2 {
2580 u8 fver; /* btc_ver::fcxstep */
2581 u8 rsvd;
2582 __le16 cnt;
2583 __le16 pos_old;
2584 __le16 pos_new;
2585 struct rtw89_btc_fbtc_step step[FCXMAX_STEP];
2586 } __packed;
2587
2588 struct rtw89_btc_fbtc_steps_v3 {
2589 u8 fver;
2590 u8 en;
2591 __le16 rsvd;
2592 __le32 cnt;
2593 struct rtw89_btc_fbtc_step step[FCXMAX_STEP];
2594 } __packed;
2595
2596 union rtw89_btc_fbtc_steps_info {
2597 struct rtw89_btc_fbtc_steps_v2 v2;
2598 struct rtw89_btc_fbtc_steps_v3 v3;
2599 };
2600
2601 struct rtw89_btc_fbtc_cysta_v2 { /* statistics for cycles */
2602 u8 fver; /* btc_ver::fcxcysta */
2603 u8 rsvd;
2604 __le16 cycles; /* total cycle number */
2605 __le16 cycles_a2dp[CXT_FLCTRL_MAX];
2606 __le16 a2dpept; /* a2dp empty cnt */
2607 __le16 a2dpeptto; /* a2dp empty timeout cnt*/
2608 __le16 tavg_cycle[CXT_MAX]; /* avg wl/bt cycle time */
2609 __le16 tmax_cycle[CXT_MAX]; /* max wl/bt cycle time */
2610 __le16 tmaxdiff_cycle[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */
2611 __le16 tavg_a2dp[CXT_FLCTRL_MAX]; /* avg a2dp PSTDMA/TDMA time */
2612 __le16 tmax_a2dp[CXT_FLCTRL_MAX]; /* max a2dp PSTDMA/TDMA time */
2613 __le16 tavg_a2dpept; /* avg a2dp empty time */
2614 __le16 tmax_a2dpept; /* max a2dp empty time */
2615 __le16 tavg_lk; /* avg leak-slot time */
2616 __le16 tmax_lk; /* max leak-slot time */
2617 __le32 slot_cnt[CXST_MAX]; /* slot count */
2618 __le32 bcn_cnt[CXBCN_MAX];
2619 __le32 leakrx_cnt; /* the rximr occur at leak slot */
2620 __le32 collision_cnt; /* counter for event/timer occur at same time */
2621 __le32 skip_cnt;
2622 __le32 exception;
2623 __le32 except_cnt;
2624 __le16 tslot_cycle[BTC_CYCLE_SLOT_MAX];
2625 } __packed;
2626
2627 struct rtw89_btc_fbtc_fdd_try_info {
2628 __le16 cycles[CXT_FLCTRL_MAX];
2629 __le16 tavg[CXT_FLCTRL_MAX]; /* avg try BT-Slot-TDD/BT-slot-FDD time */
2630 __le16 tmax[CXT_FLCTRL_MAX]; /* max try BT-Slot-TDD/BT-slot-FDD time */
2631 } __packed;
2632
2633 struct rtw89_btc_fbtc_cycle_time_info {
2634 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */
2635 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */
2636 __le16 tmaxdiff[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */
2637 } __packed;
2638
2639 struct rtw89_btc_fbtc_cycle_time_info_v5 {
2640 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */
2641 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */
2642 } __packed;
2643
2644 struct rtw89_btc_fbtc_a2dp_trx_stat {
2645 u8 empty_cnt;
2646 u8 retry_cnt;
2647 u8 tx_rate;
2648 u8 tx_cnt;
2649 u8 ack_cnt;
2650 u8 nack_cnt;
2651 u8 rsvd1;
2652 u8 rsvd2;
2653 } __packed;
2654
2655 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 {
2656 u8 empty_cnt;
2657 u8 retry_cnt;
2658 u8 tx_rate;
2659 u8 tx_cnt;
2660 u8 ack_cnt;
2661 u8 nack_cnt;
2662 u8 no_empty_cnt;
2663 u8 rsvd;
2664 } __packed;
2665
2666 struct rtw89_btc_fbtc_cycle_a2dp_empty_info {
2667 __le16 cnt; /* a2dp empty cnt */
2668 __le16 cnt_timeout; /* a2dp empty timeout cnt*/
2669 __le16 tavg; /* avg a2dp empty time */
2670 __le16 tmax; /* max a2dp empty time */
2671 } __packed;
2672
2673 struct rtw89_btc_fbtc_cycle_leak_info {
2674 __le32 cnt_rximr; /* the rximr occur at leak slot */
2675 __le16 tavg; /* avg leak-slot time */
2676 __le16 tmax; /* max leak-slot time */
2677 } __packed;
2678
2679 struct rtw89_btc_fbtc_cycle_leak_info_v7 {
2680 __le16 tavg;
2681 __le16 tamx;
2682 __le32 cnt_rximr;
2683 } __packed;
2684
2685 #define RTW89_BTC_FDDT_PHASE_CYCLE GENMASK(9, 0)
2686 #define RTW89_BTC_FDDT_TRAIN_STEP GENMASK(15, 10)
2687
2688 struct rtw89_btc_fbtc_cycle_fddt_info {
2689 __le16 train_cycle;
2690 __le16 tp;
2691
2692 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */
2693 s8 bt_tx_power; /* decrease Tx power (dB) */
2694 s8 bt_rx_gain; /* LNA constrain level */
2695 u8 no_empty_cnt;
2696
2697 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */
2698 u8 cn; /* condition_num */
2699 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */
2700 u8 train_result; /* refer to enum btc_fddt_check_map */
2701 } __packed;
2702
2703 #define RTW89_BTC_FDDT_CELL_TRAIN_STATE GENMASK(3, 0)
2704 #define RTW89_BTC_FDDT_CELL_TRAIN_PHASE GENMASK(7, 4)
2705
2706 struct rtw89_btc_fbtc_cycle_fddt_info_v5 {
2707 __le16 train_cycle;
2708 __le16 tp;
2709
2710 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */
2711 s8 bt_tx_power; /* decrease Tx power (dB) */
2712 s8 bt_rx_gain; /* LNA constrain level */
2713 u8 no_empty_cnt;
2714
2715 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */
2716 u8 cn; /* condition_num */
2717 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */
2718 u8 train_result; /* refer to enum btc_fddt_check_map */
2719 } __packed;
2720
2721 struct rtw89_btc_fbtc_fddt_cell_status {
2722 s8 wl_tx_pwr;
2723 s8 bt_tx_pwr;
2724 s8 bt_rx_gain;
2725 u8 state_phase; /* [0:3] train state, [4:7] train phase */
2726 } __packed;
2727
2728 struct rtw89_btc_fbtc_cysta_v3 { /* statistics for cycles */
2729 u8 fver;
2730 u8 rsvd;
2731 __le16 cycles; /* total cycle number */
2732 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX];
2733 struct rtw89_btc_fbtc_cycle_time_info cycle_time;
2734 struct rtw89_btc_fbtc_fdd_try_info fdd_try;
2735 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept;
2736 struct rtw89_btc_fbtc_a2dp_trx_stat a2dp_trx[BTC_CYCLE_SLOT_MAX];
2737 struct rtw89_btc_fbtc_cycle_leak_info leak_slot;
2738 __le32 slot_cnt[CXST_MAX]; /* slot count */
2739 __le32 bcn_cnt[CXBCN_MAX];
2740 __le32 collision_cnt; /* counter for event/timer occur at the same time */
2741 __le32 skip_cnt;
2742 __le32 except_cnt;
2743 __le32 except_map;
2744 } __packed;
2745
2746 #define FDD_TRAIN_WL_DIRECTION 2
2747 #define FDD_TRAIN_WL_RSSI_LEVEL 5
2748 #define FDD_TRAIN_BT_RSSI_LEVEL 5
2749
2750 struct rtw89_btc_fbtc_cysta_v4 { /* statistics for cycles */
2751 u8 fver;
2752 u8 rsvd;
2753 u8 collision_cnt; /* counter for event/timer occur at the same time */
2754 u8 except_cnt;
2755
2756 __le16 skip_cnt;
2757 __le16 cycles; /* total cycle number */
2758
2759 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */
2760 __le16 slot_cnt[CXST_MAX]; /* slot count */
2761 __le16 bcn_cnt[CXBCN_MAX];
2762 struct rtw89_btc_fbtc_cycle_time_info cycle_time;
2763 struct rtw89_btc_fbtc_cycle_leak_info leak_slot;
2764 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept;
2765 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX];
2766 struct rtw89_btc_fbtc_cycle_fddt_info fddt_trx[BTC_CYCLE_SLOT_MAX];
2767 struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION]
2768 [FDD_TRAIN_WL_RSSI_LEVEL]
2769 [FDD_TRAIN_BT_RSSI_LEVEL];
2770 __le32 except_map;
2771 } __packed;
2772
2773 struct rtw89_btc_fbtc_cysta_v5 { /* statistics for cycles */
2774 u8 fver;
2775 u8 rsvd;
2776 u8 collision_cnt; /* counter for event/timer occur at the same time */
2777 u8 except_cnt;
2778 u8 wl_rx_err_ratio[BTC_CYCLE_SLOT_MAX];
2779
2780 __le16 skip_cnt;
2781 __le16 cycles; /* total cycle number */
2782
2783 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */
2784 __le16 slot_cnt[CXST_MAX]; /* slot count */
2785 __le16 bcn_cnt[CXBCN_MAX];
2786 struct rtw89_btc_fbtc_cycle_time_info_v5 cycle_time;
2787 struct rtw89_btc_fbtc_cycle_leak_info leak_slot;
2788 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept;
2789 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX];
2790 struct rtw89_btc_fbtc_cycle_fddt_info_v5 fddt_trx[BTC_CYCLE_SLOT_MAX];
2791 struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION]
2792 [FDD_TRAIN_WL_RSSI_LEVEL]
2793 [FDD_TRAIN_BT_RSSI_LEVEL];
2794 __le32 except_map;
2795 } __packed;
2796
2797 struct rtw89_btc_fbtc_cysta_v7 { /* statistics for cycles */
2798 u8 fver;
2799 u8 rsvd;
2800 u8 collision_cnt; /* counter for event/timer occur at the same time */
2801 u8 except_cnt;
2802
2803 u8 wl_rx_err_ratio[BTC_CYCLE_SLOT_MAX];
2804
2805 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX];
2806
2807 __le16 skip_cnt;
2808 __le16 cycles; /* total cycle number */
2809
2810 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */
2811 __le16 slot_cnt[CXST_MAX]; /* slot count */
2812 __le16 bcn_cnt[CXBCN_MAX];
2813
2814 struct rtw89_btc_fbtc_cycle_time_info_v5 cycle_time;
2815 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept;
2816 struct rtw89_btc_fbtc_cycle_leak_info_v7 leak_slot;
2817
2818 __le32 except_map;
2819 } __packed;
2820
2821 union rtw89_btc_fbtc_cysta_info {
2822 struct rtw89_btc_fbtc_cysta_v2 v2;
2823 struct rtw89_btc_fbtc_cysta_v3 v3;
2824 struct rtw89_btc_fbtc_cysta_v4 v4;
2825 struct rtw89_btc_fbtc_cysta_v5 v5;
2826 struct rtw89_btc_fbtc_cysta_v7 v7;
2827 };
2828
2829 struct rtw89_btc_fbtc_cynullsta_v1 { /* cycle null statistics */
2830 u8 fver; /* btc_ver::fcxnullsta */
2831 u8 rsvd;
2832 __le16 rsvd2;
2833 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */
2834 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */
2835 __le32 result[2][4]; /* 0:fail, 1:ok, 2:on_time, 3:retry */
2836 } __packed;
2837
2838 struct rtw89_btc_fbtc_cynullsta_v2 { /* cycle null statistics */
2839 u8 fver; /* btc_ver::fcxnullsta */
2840 u8 rsvd;
2841 __le16 rsvd2;
2842 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */
2843 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */
2844 __le32 result[2][5]; /* 0:fail, 1:ok, 2:on_time, 3:retry, 4:tx */
2845 } __packed;
2846
2847 struct rtw89_btc_fbtc_cynullsta_v7 { /* cycle null statistics */
2848 u8 fver;
2849 u8 rsvd0;
2850 u8 rsvd1;
2851 u8 rsvd2;
2852
2853 __le32 tmax[2];
2854 __le32 tavg[2];
2855 __le32 result[2][5];
2856 } __packed;
2857
2858 union rtw89_btc_fbtc_cynullsta_info {
2859 struct rtw89_btc_fbtc_cynullsta_v1 v1; /* info from fw */
2860 struct rtw89_btc_fbtc_cynullsta_v2 v2;
2861 struct rtw89_btc_fbtc_cynullsta_v7 v7;
2862 };
2863
2864 struct rtw89_btc_fbtc_btver_v1 {
2865 u8 fver; /* btc_ver::fcxbtver */
2866 u8 rsvd;
2867 __le16 rsvd2;
2868 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */
2869 __le32 fw_ver;
2870 __le32 feature;
2871 } __packed;
2872
2873 struct rtw89_btc_fbtc_btver_v7 {
2874 u8 fver;
2875 u8 rsvd0;
2876 u8 rsvd1;
2877 u8 rsvd2;
2878
2879 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */
2880 __le32 fw_ver;
2881 __le32 feature;
2882 } __packed;
2883
2884 union rtw89_btc_fbtc_btver {
2885 struct rtw89_btc_fbtc_btver_v1 v1;
2886 struct rtw89_btc_fbtc_btver_v7 v7;
2887 } __packed;
2888
2889 struct rtw89_btc_fbtc_btafh {
2890 u8 fver; /* btc_ver::fcxbtafh */
2891 u8 rsvd;
2892 __le16 rsvd2;
2893 u8 afh_l[4]; /*bit0:2402, bit1: 2403.... bit31:2433 */
2894 u8 afh_m[4]; /*bit0:2434, bit1: 2435.... bit31:2465 */
2895 u8 afh_h[4]; /*bit0:2466, bit1:2467......bit14:2480 */
2896 } __packed;
2897
2898 struct rtw89_btc_fbtc_btafh_v2 {
2899 u8 fver; /* btc_ver::fcxbtafh */
2900 u8 rsvd;
2901 u8 rsvd2;
2902 u8 map_type;
2903 u8 afh_l[4];
2904 u8 afh_m[4];
2905 u8 afh_h[4];
2906 u8 afh_le_a[4];
2907 u8 afh_le_b[4];
2908 } __packed;
2909
2910 struct rtw89_btc_fbtc_btafh_v7 {
2911 u8 fver;
2912 u8 map_type;
2913 u8 rsvd0;
2914 u8 rsvd1;
2915 u8 afh_l[4]; /*bit0:2402, bit1:2403.... bit31:2433 */
2916 u8 afh_m[4]; /*bit0:2434, bit1:2435.... bit31:2465 */
2917 u8 afh_h[4]; /*bit0:2466, bit1:2467.....bit14:2480 */
2918 u8 afh_le_a[4];
2919 u8 afh_le_b[4];
2920 } __packed;
2921
2922 struct rtw89_btc_fbtc_btdevinfo {
2923 u8 fver; /* btc_ver::fcxbtdevinfo */
2924 u8 rsvd;
2925 __le16 vendor_id;
2926 __le32 dev_name; /* only 24 bits valid */
2927 __le32 flush_time;
2928 } __packed;
2929
2930 #define RTW89_BTC_WL_DEF_TX_PWR GENMASK(7, 0)
2931 struct rtw89_btc_rf_trx_para {
2932 u32 wl_tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */
2933 u32 wl_rx_gain; /* rx gain table index (TBD.) */
2934 u8 bt_tx_power; /* decrease Tx power (dB) */
2935 u8 bt_rx_gain; /* LNA constrain level */
2936 };
2937
2938 struct rtw89_btc_trx_info {
2939 u8 tx_lvl;
2940 u8 rx_lvl;
2941 u8 wl_rssi;
2942 u8 bt_rssi;
2943
2944 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */
2945 s8 rx_gain; /* rx gain table index (TBD.) */
2946 s8 bt_tx_power; /* decrease Tx power (dB) */
2947 s8 bt_rx_gain; /* LNA constrain level */
2948
2949 u8 cn; /* condition_num */
2950 s8 nhm;
2951 u8 bt_profile;
2952 u8 rsvd2;
2953
2954 u16 tx_rate;
2955 u16 rx_rate;
2956
2957 u32 tx_tp;
2958 u32 rx_tp;
2959 u32 rx_err_ratio;
2960 };
2961
2962 enum btc_rf_path {
2963 BTC_RF_S0 = 0,
2964 BTC_RF_S1 = 1,
2965 BTC_RF_NUM,
2966 };
2967
2968 struct rtw89_btc_fbtc_outsrc_set_info {
2969 u8 rf_band[BTC_RF_NUM]; /* 0:2G, 1:non-2G */
2970 u8 btg_rx[BTC_RF_NUM];
2971 u8 nbtg_tx[BTC_RF_NUM];
2972
2973 struct rtw89_mac_ax_gnt gnt_set[BTC_RF_NUM]; /* refer to btc_gnt_ctrl */
2974 struct rtw89_mac_ax_wl_act wlact_set[BTC_RF_NUM]; /* BT0/BT1 */
2975
2976 u8 pta_req_hw_band;
2977 u8 rf_gbt_source;
2978 } __packed;
2979
2980 union rtw89_btc_fbtc_slot_u {
2981 struct rtw89_btc_fbtc_slot v1[CXST_MAX];
2982 struct rtw89_btc_fbtc_slot_v7 v7[CXST_MAX];
2983 };
2984
2985 struct rtw89_btc_dm {
2986 struct rtw89_btc_fbtc_outsrc_set_info ost_info_last; /* outsrc API setup info */
2987 struct rtw89_btc_fbtc_outsrc_set_info ost_info; /* outsrc API setup info */
2988 union rtw89_btc_fbtc_slot_u slot;
2989 union rtw89_btc_fbtc_slot_u slot_now;
2990 struct rtw89_btc_fbtc_tdma tdma;
2991 struct rtw89_btc_fbtc_tdma tdma_now;
2992 struct rtw89_mac_ax_coex_gnt gnt;
2993 union rtw89_btc_init_info_u init_info; /* pass to wl_fw if offload */
2994 struct rtw89_btc_rf_trx_para rf_trx_para;
2995 struct rtw89_btc_wl_tx_limit_para wl_tx_limit;
2996 struct rtw89_btc_dm_step dm_step;
2997 struct rtw89_btc_wl_scc_ctrl wl_scc;
2998 struct rtw89_btc_trx_info trx_info;
2999 union rtw89_btc_dm_error_map error;
3000 u32 cnt_dm[BTC_DCNT_NUM];
3001 u32 cnt_notify[BTC_NCNT_NUM];
3002
3003 u32 update_slot_map;
3004 u32 set_ant_path;
3005 u32 e2g_slot_limit;
3006 u32 e2g_slot_nulltx_time;
3007
3008 u32 wl_only: 1;
3009 u32 wl_fw_cx_offload: 1;
3010 u32 freerun: 1;
3011 u32 fddt_train: 1;
3012 u32 wl_ps_ctrl: 2;
3013 u32 wl_mimo_ps: 1;
3014 u32 leak_ap: 1;
3015 u32 noisy_level: 3;
3016 u32 coex_info_map: 8;
3017 u32 bt_only: 1;
3018 u32 wl_btg_rx: 2;
3019 u32 trx_para_level: 8;
3020 u32 wl_stb_chg: 1;
3021 u32 pta_owner: 1;
3022
3023 u32 tdma_instant_excute: 1;
3024 u32 wl_btg_rx_rb: 2;
3025
3026 u16 slot_dur[CXST_MAX];
3027 u16 bt_slot_flood;
3028
3029 u8 run_reason;
3030 u8 run_action;
3031
3032 u8 wl_pre_agc: 2;
3033 u8 wl_lna2: 1;
3034 u8 freerun_chk: 1;
3035 u8 wl_pre_agc_rb: 2;
3036 u8 bt_select: 2; /* 0:s0, 1:s1, 2:s0 & s1, refer to enum btc_bt_index */
3037 u8 slot_req_more: 1;
3038 };
3039
3040 struct rtw89_btc_ctrl {
3041 u32 manual: 1;
3042 u32 igno_bt: 1;
3043 u32 always_freerun: 1;
3044 u32 trace_step: 16;
3045 u32 rsvd: 12;
3046 };
3047
3048 struct rtw89_btc_ctrl_v7 {
3049 u8 manual;
3050 u8 igno_bt;
3051 u8 always_freerun;
3052 u8 rsvd;
3053 } __packed;
3054
3055 union rtw89_btc_ctrl_list {
3056 struct rtw89_btc_ctrl ctrl;
3057 struct rtw89_btc_ctrl_v7 ctrl_v7;
3058 };
3059
3060 struct rtw89_btc_dbg {
3061 /* cmd "rb" */
3062 bool rb_done;
3063 u32 rb_val;
3064 };
3065
3066 enum rtw89_btc_btf_fw_event {
3067 BTF_EVNT_RPT = 0,
3068 BTF_EVNT_BT_INFO = 1,
3069 BTF_EVNT_BT_SCBD = 2,
3070 BTF_EVNT_BT_REG = 3,
3071 BTF_EVNT_CX_RUNINFO = 4,
3072 BTF_EVNT_BT_PSD = 5,
3073 BTF_EVNT_BT_DEV_INFO = 6, /* fwc2hfunc > 0 */
3074 BTF_EVNT_BT_LEAUDIO_INFO = 7, /* fwc2hfunc > 1 */
3075 BTF_EVNT_BUF_OVERFLOW,
3076 BTF_EVNT_C2H_LOOPBACK,
3077 BTF_EVNT_BT_QUERY_TXPWR, /* fwc2hfunc > 3 */
3078 BTF_EVNT_MAX,
3079 };
3080
3081 enum btf_fw_event_report {
3082 BTC_RPT_TYPE_CTRL = 0x0,
3083 BTC_RPT_TYPE_TDMA,
3084 BTC_RPT_TYPE_SLOT,
3085 BTC_RPT_TYPE_CYSTA,
3086 BTC_RPT_TYPE_STEP,
3087 BTC_RPT_TYPE_NULLSTA,
3088 BTC_RPT_TYPE_FDDT, /* added by ver->fwevntrptl == 1 */
3089 BTC_RPT_TYPE_MREG,
3090 BTC_RPT_TYPE_GPIO_DBG,
3091 BTC_RPT_TYPE_BT_VER,
3092 BTC_RPT_TYPE_BT_SCAN,
3093 BTC_RPT_TYPE_BT_AFH,
3094 BTC_RPT_TYPE_BT_DEVICE,
3095 BTC_RPT_TYPE_TEST,
3096 BTC_RPT_TYPE_MAX = 31,
3097
3098 __BTC_RPT_TYPE_V0_SAME = BTC_RPT_TYPE_NULLSTA,
3099 __BTC_RPT_TYPE_V0_MAX = 12,
3100 };
3101
3102 enum rtw_btc_btf_reg_type {
3103 REG_MAC = 0x0,
3104 REG_BB = 0x1,
3105 REG_RF = 0x2,
3106 REG_BT_RF = 0x3,
3107 REG_BT_MODEM = 0x4,
3108 REG_BT_BLUEWIZE = 0x5,
3109 REG_BT_VENDOR = 0x6,
3110 REG_BT_LE = 0x7,
3111 REG_MAX_TYPE,
3112 };
3113
3114 struct rtw89_btc_rpt_cmn_info {
3115 u32 rx_cnt;
3116 u32 rx_len;
3117 u32 req_len; /* expected rsp len */
3118 u8 req_fver; /* expected rsp fver */
3119 u8 rsp_fver; /* fver from fw */
3120 u8 valid;
3121 } __packed;
3122
3123 union rtw89_btc_fbtc_btafh_info {
3124 struct rtw89_btc_fbtc_btafh v1;
3125 struct rtw89_btc_fbtc_btafh_v2 v2;
3126 struct rtw89_btc_fbtc_btafh_v7 v7;
3127 };
3128
3129 struct rtw89_btc_report_ctrl_state {
3130 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3131 union rtw89_btc_fbtc_rpt_ctrl_ver_info finfo;
3132 };
3133
3134 struct rtw89_btc_rpt_fbtc_tdma {
3135 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3136 union rtw89_btc_fbtc_tdma_le32 finfo;
3137 };
3138
3139 struct rtw89_btc_rpt_fbtc_slots {
3140 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3141 union rtw89_btc_fbtc_slots_info finfo; /* info from fw */
3142 };
3143
3144 struct rtw89_btc_rpt_fbtc_cysta {
3145 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3146 union rtw89_btc_fbtc_cysta_info finfo;
3147 };
3148
3149 struct rtw89_btc_rpt_fbtc_step {
3150 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3151 union rtw89_btc_fbtc_steps_info finfo; /* info from fw */
3152 };
3153
3154 struct rtw89_btc_rpt_fbtc_nullsta {
3155 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3156 union rtw89_btc_fbtc_cynullsta_info finfo;
3157 };
3158
3159 struct rtw89_btc_rpt_fbtc_mreg {
3160 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3161 union rtw89_btc_fbtc_mreg_val finfo; /* info from fw */
3162 };
3163
3164 struct rtw89_btc_rpt_fbtc_gpio_dbg {
3165 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3166 union rtw89_btc_fbtc_gpio_dbg finfo; /* info from fw */
3167 };
3168
3169 struct rtw89_btc_rpt_fbtc_btver {
3170 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3171 union rtw89_btc_fbtc_btver finfo; /* info from fw */
3172 };
3173
3174 struct rtw89_btc_rpt_fbtc_btscan {
3175 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3176 union rtw89_btc_fbtc_btscan finfo; /* info from fw */
3177 };
3178
3179 struct rtw89_btc_rpt_fbtc_btafh {
3180 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3181 union rtw89_btc_fbtc_btafh_info finfo;
3182 };
3183
3184 struct rtw89_btc_rpt_fbtc_btdev {
3185 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3186 struct rtw89_btc_fbtc_btdevinfo finfo; /* info from fw */
3187 };
3188
3189 enum rtw89_btc_btfre_type {
3190 BTFRE_INVALID_INPUT = 0x0, /* invalid input parameters */
3191 BTFRE_UNDEF_TYPE,
3192 BTFRE_EXCEPTION,
3193 BTFRE_MAX,
3194 };
3195
3196 struct rtw89_btc_ver {
3197 enum rtw89_core_chip_id chip_id;
3198 u32 fw_ver_code;
3199
3200 u8 fcxbtcrpt;
3201 u8 fcxtdma;
3202 u8 fcxslots;
3203 u8 fcxcysta;
3204 u8 fcxstep;
3205 u8 fcxnullsta;
3206 u8 fcxmreg;
3207 u8 fcxgpiodbg;
3208 u8 fcxbtver;
3209 u8 fcxbtscan;
3210 u8 fcxbtafh;
3211 u8 fcxbtdevinfo;
3212 u8 fwlrole;
3213 u8 frptmap;
3214 u8 fcxctrl;
3215 u8 fcxinit;
3216
3217 u8 fwevntrptl;
3218 u8 fwc2hfunc;
3219 u8 drvinfo_type;
3220 u16 info_buf;
3221 u8 max_role_num;
3222 u8 fcxosi;
3223 u8 fcxmlo;
3224 u8 bt_desired;
3225 };
3226
3227 struct rtw89_btc_btf_fwinfo {
3228 u32 cnt_c2h;
3229 u32 cnt_h2c;
3230 u32 cnt_h2c_fail;
3231 u32 event[BTF_EVNT_MAX];
3232
3233 u32 err[BTFRE_MAX];
3234 u32 len_mismch;
3235 u32 fver_mismch;
3236 u32 rpt_en_map;
3237
3238 struct rtw89_btc_ver fw_subver;
3239 struct rtw89_btc_report_ctrl_state rpt_ctrl;
3240 struct rtw89_btc_rpt_fbtc_tdma rpt_fbtc_tdma;
3241 struct rtw89_btc_rpt_fbtc_slots rpt_fbtc_slots;
3242 struct rtw89_btc_rpt_fbtc_cysta rpt_fbtc_cysta;
3243 struct rtw89_btc_rpt_fbtc_step rpt_fbtc_step;
3244 struct rtw89_btc_rpt_fbtc_nullsta rpt_fbtc_nullsta;
3245 struct rtw89_btc_rpt_fbtc_mreg rpt_fbtc_mregval;
3246 struct rtw89_btc_rpt_fbtc_gpio_dbg rpt_fbtc_gpio_dbg;
3247 struct rtw89_btc_rpt_fbtc_btver rpt_fbtc_btver;
3248 struct rtw89_btc_rpt_fbtc_btscan rpt_fbtc_btscan;
3249 struct rtw89_btc_rpt_fbtc_btafh rpt_fbtc_btafh;
3250 struct rtw89_btc_rpt_fbtc_btdev rpt_fbtc_btdev;
3251 };
3252
3253 #define RTW89_BTC_POLICY_MAXLEN 512
3254
3255 struct rtw89_btc {
3256 const struct rtw89_btc_ver *ver;
3257
3258 struct rtw89_btc_cx cx;
3259 struct rtw89_btc_dm dm;
3260 union rtw89_btc_ctrl_list ctrl;
3261 union rtw89_btc_module_info mdinfo;
3262 struct rtw89_btc_btf_fwinfo fwinfo;
3263 struct rtw89_btc_dbg dbg;
3264
3265 struct wiphy_work eapol_notify_work;
3266 struct wiphy_work arp_notify_work;
3267 struct wiphy_work dhcp_notify_work;
3268 struct wiphy_work icmp_notify_work;
3269
3270 u32 bt_req_len;
3271
3272 u8 policy[RTW89_BTC_POLICY_MAXLEN];
3273 u8 ant_type;
3274 u8 btg_pos;
3275 u16 policy_len;
3276 u16 policy_type;
3277 u32 hubmsg_cnt;
3278 bool bt_req_en;
3279 bool update_policy_force;
3280 bool lps;
3281 bool manual_ctrl;
3282 };
3283
3284 enum rtw89_btc_hmsg {
3285 RTW89_BTC_HMSG_TMR_EN = 0x0,
3286 RTW89_BTC_HMSG_BT_REG_READBACK = 0x1,
3287 RTW89_BTC_HMSG_SET_BT_REQ_SLOT = 0x2,
3288 RTW89_BTC_HMSG_FW_EV = 0x3,
3289 RTW89_BTC_HMSG_BT_LINK_CHG = 0x4,
3290 RTW89_BTC_HMSG_SET_BT_REQ_STBC = 0x5,
3291
3292 NUM_OF_RTW89_BTC_HMSG,
3293 };
3294
3295 enum rtw89_ra_mode {
3296 RTW89_RA_MODE_CCK = BIT(0),
3297 RTW89_RA_MODE_OFDM = BIT(1),
3298 RTW89_RA_MODE_HT = BIT(2),
3299 RTW89_RA_MODE_VHT = BIT(3),
3300 RTW89_RA_MODE_HE = BIT(4),
3301 RTW89_RA_MODE_EHT = BIT(5),
3302 };
3303
3304 enum rtw89_ra_report_mode {
3305 RTW89_RA_RPT_MODE_LEGACY,
3306 RTW89_RA_RPT_MODE_HT,
3307 RTW89_RA_RPT_MODE_VHT,
3308 RTW89_RA_RPT_MODE_HE,
3309 RTW89_RA_RPT_MODE_EHT,
3310 };
3311
3312 enum rtw89_dig_noisy_level {
3313 RTW89_DIG_NOISY_LEVEL0 = -1,
3314 RTW89_DIG_NOISY_LEVEL1 = 0,
3315 RTW89_DIG_NOISY_LEVEL2 = 1,
3316 RTW89_DIG_NOISY_LEVEL3 = 2,
3317 RTW89_DIG_NOISY_LEVEL_MAX = 3,
3318 };
3319
3320 enum rtw89_gi_ltf {
3321 RTW89_GILTF_LGI_4XHE32 = 0,
3322 RTW89_GILTF_SGI_4XHE08 = 1,
3323 RTW89_GILTF_2XHE16 = 2,
3324 RTW89_GILTF_2XHE08 = 3,
3325 RTW89_GILTF_1XHE16 = 4,
3326 RTW89_GILTF_1XHE08 = 5,
3327 RTW89_GILTF_MAX
3328 };
3329
3330 enum rtw89_rx_frame_type {
3331 RTW89_RX_TYPE_MGNT = 0,
3332 RTW89_RX_TYPE_CTRL = 1,
3333 RTW89_RX_TYPE_DATA = 2,
3334 RTW89_RX_TYPE_RSVD = 3,
3335 };
3336
3337 enum rtw89_efuse_block {
3338 RTW89_EFUSE_BLOCK_SYS = 0,
3339 RTW89_EFUSE_BLOCK_RF = 1,
3340 RTW89_EFUSE_BLOCK_HCI_DIG_PCIE_SDIO = 2,
3341 RTW89_EFUSE_BLOCK_HCI_DIG_USB = 3,
3342 RTW89_EFUSE_BLOCK_HCI_PHY_PCIE = 4,
3343 RTW89_EFUSE_BLOCK_HCI_PHY_USB3 = 5,
3344 RTW89_EFUSE_BLOCK_HCI_PHY_USB2 = 6,
3345 RTW89_EFUSE_BLOCK_ADIE = 7,
3346
3347 RTW89_EFUSE_BLOCK_NUM,
3348 RTW89_EFUSE_BLOCK_IGNORE,
3349 };
3350
3351 struct rtw89_ra_info {
3352 u8 is_dis_ra:1;
3353 /* Bit0 : CCK
3354 * Bit1 : OFDM
3355 * Bit2 : HT
3356 * Bit3 : VHT
3357 * Bit4 : HE
3358 * Bit5 : EHT
3359 */
3360 u8 mode_ctrl:6;
3361 u8 bw_cap:3; /* enum rtw89_bandwidth */
3362 u8 macid;
3363 u8 dcm_cap:1;
3364 u8 er_cap:1;
3365 u8 init_rate_lv:2;
3366 u8 upd_all:1;
3367 u8 en_sgi:1;
3368 u8 ldpc_cap:1;
3369 u8 stbc_cap:1;
3370 u8 ss_num:3;
3371 u8 giltf:3;
3372 u8 upd_bw_nss_mask:1;
3373 u8 upd_mask:1;
3374 u64 ra_mask; /* 63 bits ra_mask + 1 bit CSI ctrl */
3375 /* BFee CSI */
3376 u8 band_num;
3377 u8 ra_csi_rate_en:1;
3378 u8 fixed_csi_rate_en:1;
3379 u8 cr_tbl_sel:1;
3380 u8 fix_giltf_en:1;
3381 u8 fix_giltf:3;
3382 u8 rsvd2:1;
3383 u8 csi_mcs_ss_idx;
3384 u8 csi_mode:2;
3385 u8 csi_gi_ltf:3;
3386 u8 csi_bw:3;
3387 };
3388
3389 #define RTW89_PPDU_MAC_INFO_USR_SIZE 4
3390 #define RTW89_PPDU_MAC_INFO_SIZE 8
3391 #define RTW89_PPDU_MAC_RX_CNT_SIZE 96
3392 #define RTW89_PPDU_MAC_RX_CNT_SIZE_V1 128
3393
3394 #define RTW89_MAX_RX_AGG_NUM 64
3395 #define RTW89_MAX_TX_AGG_NUM 128
3396
3397 struct rtw89_ampdu_params {
3398 u16 agg_num;
3399 bool amsdu;
3400 };
3401
3402 struct rtw89_ra_report {
3403 struct rate_info txrate;
3404 u32 bit_rate;
3405 u16 hw_rate;
3406 bool might_fallback_legacy;
3407 };
3408
3409 DECLARE_EWMA(rssi, 10, 16);
3410 DECLARE_EWMA(evm, 10, 16);
3411 DECLARE_EWMA(snr, 10, 16);
3412
3413 struct rtw89_ba_cam_entry {
3414 struct list_head list;
3415 u8 tid;
3416 };
3417
3418 #define RTW89_MAX_ADDR_CAM_NUM 128
3419 #define RTW89_MAX_BSSID_CAM_NUM 20
3420 #define RTW89_MAX_SEC_CAM_NUM 128
3421 #define RTW89_MAX_BA_CAM_NUM 24
3422 #define RTW89_SEC_CAM_IN_ADDR_CAM 7
3423
3424 struct rtw89_addr_cam_entry {
3425 u8 addr_cam_idx;
3426 u8 offset;
3427 u8 len;
3428 u8 valid : 1;
3429 u8 addr_mask : 6;
3430 u8 wapi : 1;
3431 u8 mask_sel : 2;
3432 u8 bssid_cam_idx: 6;
3433
3434 u8 sec_ent_mode;
3435 DECLARE_BITMAP(sec_cam_map, RTW89_SEC_CAM_IN_ADDR_CAM);
3436 u8 sec_ent_keyid[RTW89_SEC_CAM_IN_ADDR_CAM];
3437 u8 sec_ent[RTW89_SEC_CAM_IN_ADDR_CAM];
3438 };
3439
3440 struct rtw89_bssid_cam_entry {
3441 u8 bssid[ETH_ALEN];
3442 u8 phy_idx;
3443 u8 bssid_cam_idx;
3444 u8 offset;
3445 u8 len;
3446 u8 valid : 1;
3447 u8 num;
3448 };
3449
3450 struct rtw89_sec_cam_entry {
3451 u8 sec_cam_idx;
3452 u8 offset;
3453 u8 len;
3454 u8 type : 4;
3455 u8 ext_key : 1;
3456 u8 spp_mode : 1;
3457 /* 256 bits */
3458 u8 key[32];
3459
3460 struct ieee80211_key_conf *key_conf;
3461 };
3462
3463 struct rtw89_sta_link {
3464 struct rtw89_sta *rtwsta;
3465 struct list_head dlink_schd;
3466 unsigned int link_id;
3467
3468 u8 mac_id;
3469 u8 tx_retry;
3470 bool er_cap;
3471 struct rtw89_vif_link *rtwvif_link;
3472 struct rtw89_ra_info ra;
3473 struct rtw89_ra_report ra_report;
3474 int max_agg_wait;
3475 u8 prev_rssi;
3476 struct ewma_rssi avg_rssi;
3477 struct ewma_rssi rssi[RF_PATH_MAX];
3478 struct ewma_snr avg_snr;
3479 struct ewma_evm evm_1ss;
3480 struct ewma_evm evm_min[RF_PATH_MAX];
3481 struct ewma_evm evm_max[RF_PATH_MAX];
3482 struct ieee80211_rx_status rx_status;
3483 u16 rx_hw_rate;
3484 __le32 htc_template;
3485 struct rtw89_addr_cam_entry addr_cam; /* AP mode or TDLS peer only */
3486 struct rtw89_bssid_cam_entry bssid_cam; /* TDLS peer only */
3487 struct list_head ba_cam_list;
3488
3489 bool use_cfg_mask;
3490 struct cfg80211_bitrate_mask mask;
3491
3492 bool cctl_tx_time;
3493 u32 ampdu_max_time:4;
3494 bool cctl_tx_retry_limit;
3495 u32 data_tx_cnt_lmt:6;
3496 };
3497
3498 struct rtw89_efuse {
3499 bool valid;
3500 bool power_k_valid;
3501 u8 xtal_cap;
3502 u8 addr[ETH_ALEN];
3503 u8 rfe_type;
3504 char country_code[2];
3505 u8 adc_td;
3506 };
3507
3508 struct rtw89_phy_rate_pattern {
3509 u64 ra_mask;
3510 u16 rate;
3511 u8 ra_mode;
3512 bool enable;
3513 };
3514
3515 struct rtw89_tx_wait_info {
3516 struct rcu_head rcu_head;
3517 struct completion completion;
3518 bool tx_done;
3519 };
3520
3521 struct rtw89_tx_skb_data {
3522 struct rtw89_tx_wait_info __rcu *wait;
3523 u8 hci_priv[];
3524 };
3525
3526 #define RTW89_SCAN_NULL_TIMEOUT 30
3527
3528 #define RTW89_ROC_IDLE_TIMEOUT 500
3529 #define RTW89_ROC_TX_TIMEOUT 30
3530 enum rtw89_roc_state {
3531 RTW89_ROC_IDLE,
3532 RTW89_ROC_NORMAL,
3533 RTW89_ROC_MGMT,
3534 };
3535
3536 struct rtw89_roc {
3537 struct ieee80211_channel chan;
3538 struct wiphy_delayed_work roc_work;
3539 enum ieee80211_roc_type type;
3540 enum rtw89_roc_state state;
3541 int duration;
3542 unsigned int link_id;
3543 };
3544
3545 #define RTW89_P2P_MAX_NOA_NUM 2
3546
3547 struct rtw89_p2p_ie_head {
3548 u8 eid;
3549 u8 ie_len;
3550 u8 oui[3];
3551 u8 oui_type;
3552 } __packed;
3553
3554 struct rtw89_noa_attr_head {
3555 u8 attr_type;
3556 __le16 attr_len;
3557 u8 index;
3558 u8 oppps_ctwindow;
3559 } __packed;
3560
3561 struct rtw89_p2p_noa_ie {
3562 struct rtw89_p2p_ie_head p2p_head;
3563 struct rtw89_noa_attr_head noa_head;
3564 struct ieee80211_p2p_noa_desc noa_desc[RTW89_P2P_MAX_NOA_NUM];
3565 } __packed;
3566
3567 struct rtw89_p2p_noa_setter {
3568 struct rtw89_p2p_noa_ie ie;
3569 u8 noa_count;
3570 u8 noa_index;
3571 };
3572
3573 struct rtw89_ps_noa_once_handler {
3574 bool in_duration;
3575 u64 tsf_begin;
3576 u64 tsf_end;
3577 struct wiphy_delayed_work set_work;
3578 struct wiphy_delayed_work clr_work;
3579 };
3580
3581 struct rtw89_vif_link {
3582 struct rtw89_vif *rtwvif;
3583 struct list_head dlink_schd;
3584 unsigned int link_id;
3585
3586 bool chanctx_assigned; /* only valid when running with chanctx_ops */
3587 enum rtw89_chanctx_idx chanctx_idx;
3588 enum rtw89_reg_6ghz_power reg_6ghz_power;
3589 struct rtw89_reg_6ghz_tpe reg_6ghz_tpe;
3590
3591 u8 mac_id;
3592 u8 port;
3593 u8 mac_addr[ETH_ALEN];
3594 u8 bssid[ETH_ALEN];
3595 u8 phy_idx;
3596 u8 mac_idx;
3597 u8 net_type;
3598 u8 wifi_role;
3599 u8 self_role;
3600 u8 wmm;
3601 u8 bcn_hit_cond;
3602 u8 bcn_bw_idx;
3603 u8 hit_rule;
3604 u8 last_noa_nr;
3605 u64 sync_bcn_tsf;
3606 u64 last_sync_bcn_tsf;
3607 bool rand_tsf_done;
3608 bool trigger;
3609 bool lsig_txop;
3610 u8 tgt_ind;
3611 u8 frm_tgt_ind;
3612 bool wowlan_pattern;
3613 bool wowlan_uc;
3614 bool wowlan_magic;
3615 bool is_hesta;
3616 bool last_a_ctrl;
3617 bool dyn_tb_bedge_en;
3618 bool pre_pwr_diff_en;
3619 bool pwr_diff_en;
3620 u8 def_tri_idx;
3621 struct wiphy_work update_beacon_work;
3622 struct wiphy_delayed_work csa_beacon_work;
3623 struct rtw89_addr_cam_entry addr_cam;
3624 struct rtw89_bssid_cam_entry bssid_cam;
3625 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS];
3626 struct rtw89_phy_rate_pattern rate_pattern;
3627 struct list_head general_pkt_list;
3628 struct rtw89_p2p_noa_setter p2p_noa;
3629 struct rtw89_ps_noa_once_handler noa_once;
3630 struct wiphy_delayed_work mcc_gc_detect_beacon_work;
3631 u8 detect_bcn_count;
3632 };
3633
3634 enum rtw89_lv1_rcvy_step {
3635 RTW89_LV1_RCVY_STEP_1,
3636 RTW89_LV1_RCVY_STEP_2,
3637 };
3638
3639 struct rtw89_hci_ops {
3640 int (*tx_write)(struct rtw89_dev *rtwdev, struct rtw89_core_tx_request *tx_req);
3641 void (*tx_kick_off)(struct rtw89_dev *rtwdev, u8 txch);
3642 void (*flush_queues)(struct rtw89_dev *rtwdev, u32 queues, bool drop);
3643 void (*reset)(struct rtw89_dev *rtwdev);
3644 int (*start)(struct rtw89_dev *rtwdev);
3645 void (*stop)(struct rtw89_dev *rtwdev);
3646 void (*pause)(struct rtw89_dev *rtwdev, bool pause);
3647 void (*switch_mode)(struct rtw89_dev *rtwdev, bool low_power);
3648 void (*recalc_int_mit)(struct rtw89_dev *rtwdev);
3649
3650 u8 (*read8)(struct rtw89_dev *rtwdev, u32 addr);
3651 u16 (*read16)(struct rtw89_dev *rtwdev, u32 addr);
3652 u32 (*read32)(struct rtw89_dev *rtwdev, u32 addr);
3653 void (*write8)(struct rtw89_dev *rtwdev, u32 addr, u8 data);
3654 void (*write16)(struct rtw89_dev *rtwdev, u32 addr, u16 data);
3655 void (*write32)(struct rtw89_dev *rtwdev, u32 addr, u32 data);
3656
3657 int (*mac_pre_init)(struct rtw89_dev *rtwdev);
3658 int (*mac_pre_deinit)(struct rtw89_dev *rtwdev);
3659 int (*mac_post_init)(struct rtw89_dev *rtwdev);
3660 int (*deinit)(struct rtw89_dev *rtwdev);
3661
3662 u32 (*check_and_reclaim_tx_resource)(struct rtw89_dev *rtwdev, u8 txch);
3663 int (*mac_lv1_rcvy)(struct rtw89_dev *rtwdev, enum rtw89_lv1_rcvy_step step);
3664 void (*dump_err_status)(struct rtw89_dev *rtwdev);
3665 int (*napi_poll)(struct napi_struct *napi, int budget);
3666
3667 /* Deal with locks inside recovery_start and recovery_complete callbacks
3668 * by hci instance, and handle things which need to consider under SER.
3669 * e.g. turn on/off interrupts except for the one for halt notification.
3670 */
3671 void (*recovery_start)(struct rtw89_dev *rtwdev);
3672 void (*recovery_complete)(struct rtw89_dev *rtwdev);
3673
3674 void (*ctrl_txdma_ch)(struct rtw89_dev *rtwdev, bool enable);
3675 void (*ctrl_txdma_fw_ch)(struct rtw89_dev *rtwdev, bool enable);
3676 void (*ctrl_trxhci)(struct rtw89_dev *rtwdev, bool enable);
3677 int (*poll_txdma_ch_idle)(struct rtw89_dev *rtwdev);
3678 void (*clr_idx_all)(struct rtw89_dev *rtwdev);
3679 void (*clear)(struct rtw89_dev *rtwdev, struct pci_dev *pdev);
3680 void (*disable_intr)(struct rtw89_dev *rtwdev);
3681 void (*enable_intr)(struct rtw89_dev *rtwdev);
3682 int (*rst_bdram)(struct rtw89_dev *rtwdev);
3683 };
3684
3685 struct rtw89_hci_info {
3686 const struct rtw89_hci_ops *ops;
3687 enum rtw89_hci_type type;
3688 enum rtw89_hci_dle_type dle_type;
3689 u32 rpwm_addr;
3690 u32 cpwm_addr;
3691 bool paused;
3692 };
3693
3694 struct rtw89_chip_ops {
3695 int (*enable_bb_rf)(struct rtw89_dev *rtwdev);
3696 int (*disable_bb_rf)(struct rtw89_dev *rtwdev);
3697 void (*bb_preinit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);
3698 void (*bb_postinit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);
3699 void (*bb_reset)(struct rtw89_dev *rtwdev,
3700 enum rtw89_phy_idx phy_idx);
3701 void (*bb_sethw)(struct rtw89_dev *rtwdev);
3702 u32 (*read_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
3703 u32 addr, u32 mask);
3704 bool (*write_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
3705 u32 addr, u32 mask, u32 data);
3706 void (*set_channel)(struct rtw89_dev *rtwdev,
3707 const struct rtw89_chan *chan,
3708 enum rtw89_mac_idx mac_idx,
3709 enum rtw89_phy_idx phy_idx);
3710 void (*set_channel_help)(struct rtw89_dev *rtwdev, bool enter,
3711 struct rtw89_channel_help_params *p,
3712 const struct rtw89_chan *chan,
3713 enum rtw89_mac_idx mac_idx,
3714 enum rtw89_phy_idx phy_idx);
3715 int (*read_efuse)(struct rtw89_dev *rtwdev, u8 *log_map,
3716 enum rtw89_efuse_block block);
3717 int (*read_phycap)(struct rtw89_dev *rtwdev, u8 *phycap_map);
3718 void (*fem_setup)(struct rtw89_dev *rtwdev);
3719 void (*rfe_gpio)(struct rtw89_dev *rtwdev);
3720 void (*rfk_hw_init)(struct rtw89_dev *rtwdev);
3721 void (*rfk_init)(struct rtw89_dev *rtwdev);
3722 void (*rfk_init_late)(struct rtw89_dev *rtwdev);
3723 void (*rfk_channel)(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link);
3724 void (*rfk_band_changed)(struct rtw89_dev *rtwdev,
3725 enum rtw89_phy_idx phy_idx,
3726 const struct rtw89_chan *chan);
3727 void (*rfk_scan)(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
3728 bool start);
3729 void (*rfk_track)(struct rtw89_dev *rtwdev);
3730 void (*power_trim)(struct rtw89_dev *rtwdev);
3731 void (*set_txpwr)(struct rtw89_dev *rtwdev,
3732 const struct rtw89_chan *chan,
3733 enum rtw89_phy_idx phy_idx);
3734 void (*set_txpwr_ctrl)(struct rtw89_dev *rtwdev,
3735 enum rtw89_phy_idx phy_idx);
3736 int (*init_txpwr_unit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);
3737 u8 (*get_thermal)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path);
3738 u32 (*chan_to_rf18_val)(struct rtw89_dev *rtwdev,
3739 const struct rtw89_chan *chan);
3740 void (*ctrl_btg_bt_rx)(struct rtw89_dev *rtwdev, bool en,
3741 enum rtw89_phy_idx phy_idx);
3742 void (*query_ppdu)(struct rtw89_dev *rtwdev,
3743 struct rtw89_rx_phy_ppdu *phy_ppdu,
3744 struct ieee80211_rx_status *status);
3745 void (*convert_rpl_to_rssi)(struct rtw89_dev *rtwdev,
3746 struct rtw89_rx_phy_ppdu *phy_ppdu);
3747 void (*phy_rpt_to_rssi)(struct rtw89_dev *rtwdev,
3748 struct rtw89_rx_desc_info *desc_info,
3749 struct ieee80211_rx_status *rx_status);
3750 void (*ctrl_nbtg_bt_tx)(struct rtw89_dev *rtwdev, bool en,
3751 enum rtw89_phy_idx phy_idx);
3752 void (*cfg_txrx_path)(struct rtw89_dev *rtwdev);
3753 void (*set_txpwr_ul_tb_offset)(struct rtw89_dev *rtwdev,
3754 s8 pw_ofst, enum rtw89_mac_idx mac_idx);
3755 void (*digital_pwr_comp)(struct rtw89_dev *rtwdev,
3756 enum rtw89_phy_idx phy_idx);
3757 int (*pwr_on_func)(struct rtw89_dev *rtwdev);
3758 int (*pwr_off_func)(struct rtw89_dev *rtwdev);
3759 void (*query_rxdesc)(struct rtw89_dev *rtwdev,
3760 struct rtw89_rx_desc_info *desc_info,
3761 u8 *data, u32 data_offset);
3762 void (*fill_txdesc)(struct rtw89_dev *rtwdev,
3763 struct rtw89_tx_desc_info *desc_info,
3764 void *txdesc);
3765 void (*fill_txdesc_fwcmd)(struct rtw89_dev *rtwdev,
3766 struct rtw89_tx_desc_info *desc_info,
3767 void *txdesc);
3768 int (*cfg_ctrl_path)(struct rtw89_dev *rtwdev, bool wl);
3769 int (*mac_cfg_gnt)(struct rtw89_dev *rtwdev,
3770 const struct rtw89_mac_ax_coex_gnt *gnt_cfg);
3771 int (*stop_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx,
3772 u32 *tx_en, enum rtw89_sch_tx_sel sel);
3773 int (*resume_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en);
3774 int (*h2c_dctl_sec_cam)(struct rtw89_dev *rtwdev,
3775 struct rtw89_vif_link *rtwvif_link,
3776 struct rtw89_sta_link *rtwsta_link);
3777 int (*h2c_default_cmac_tbl)(struct rtw89_dev *rtwdev,
3778 struct rtw89_vif_link *rtwvif_link,
3779 struct rtw89_sta_link *rtwsta_link);
3780 int (*h2c_assoc_cmac_tbl)(struct rtw89_dev *rtwdev,
3781 struct rtw89_vif_link *rtwvif_link,
3782 struct rtw89_sta_link *rtwsta_link);
3783 int (*h2c_ampdu_cmac_tbl)(struct rtw89_dev *rtwdev,
3784 struct rtw89_vif_link *rtwvif_link,
3785 struct rtw89_sta_link *rtwsta_link);
3786 int (*h2c_txtime_cmac_tbl)(struct rtw89_dev *rtwdev,
3787 struct rtw89_sta_link *rtwsta_link);
3788 int (*h2c_punctured_cmac_tbl)(struct rtw89_dev *rtwdev,
3789 struct rtw89_vif_link *rtwvif_link,
3790 u16 punctured);
3791 int (*h2c_default_dmac_tbl)(struct rtw89_dev *rtwdev,
3792 struct rtw89_vif_link *rtwvif_link,
3793 struct rtw89_sta_link *rtwsta_link);
3794 int (*h2c_update_beacon)(struct rtw89_dev *rtwdev,
3795 struct rtw89_vif_link *rtwvif_link);
3796 int (*h2c_ba_cam)(struct rtw89_dev *rtwdev,
3797 struct rtw89_vif_link *rtwvif_link,
3798 struct rtw89_sta_link *rtwsta_link,
3799 bool valid, struct ieee80211_ampdu_params *params);
3800
3801 void (*btc_set_rfe)(struct rtw89_dev *rtwdev);
3802 void (*btc_init_cfg)(struct rtw89_dev *rtwdev);
3803 void (*btc_set_wl_pri)(struct rtw89_dev *rtwdev, u8 map, bool state);
3804 void (*btc_set_wl_txpwr_ctrl)(struct rtw89_dev *rtwdev, u32 txpwr_val);
3805 s8 (*btc_get_bt_rssi)(struct rtw89_dev *rtwdev, s8 val);
3806 void (*btc_update_bt_cnt)(struct rtw89_dev *rtwdev);
3807 void (*btc_wl_s1_standby)(struct rtw89_dev *rtwdev, bool state);
3808 void (*btc_set_policy)(struct rtw89_dev *rtwdev, u16 policy_type);
3809 void (*btc_set_wl_rx_gain)(struct rtw89_dev *rtwdev, u32 level);
3810 };
3811
3812 enum rtw89_dma_ch {
3813 RTW89_DMA_ACH0 = 0,
3814 RTW89_DMA_ACH1 = 1,
3815 RTW89_DMA_ACH2 = 2,
3816 RTW89_DMA_ACH3 = 3,
3817 RTW89_DMA_ACH4 = 4,
3818 RTW89_DMA_ACH5 = 5,
3819 RTW89_DMA_ACH6 = 6,
3820 RTW89_DMA_ACH7 = 7,
3821 RTW89_DMA_B0MG = 8,
3822 RTW89_DMA_B0HI = 9,
3823 RTW89_DMA_B1MG = 10,
3824 RTW89_DMA_B1HI = 11,
3825 RTW89_DMA_H2C = 12,
3826 RTW89_DMA_CH_NUM = 13
3827 };
3828
3829 #define MLO_MODE_FOR_BB0_BB1_RF(bb0, bb1, rf) ((rf) << 12 | (bb1) << 4 | (bb0))
3830
3831 enum rtw89_mlo_dbcc_mode {
3832 MLO_DBCC_NOT_SUPPORT = 1,
3833 MLO_0_PLUS_2_1RF = MLO_MODE_FOR_BB0_BB1_RF(0, 2, 1),
3834 MLO_0_PLUS_2_2RF = MLO_MODE_FOR_BB0_BB1_RF(0, 2, 2),
3835 MLO_1_PLUS_1_1RF = MLO_MODE_FOR_BB0_BB1_RF(1, 1, 1),
3836 MLO_1_PLUS_1_2RF = MLO_MODE_FOR_BB0_BB1_RF(1, 1, 2),
3837 MLO_2_PLUS_0_1RF = MLO_MODE_FOR_BB0_BB1_RF(2, 0, 1),
3838 MLO_2_PLUS_0_2RF = MLO_MODE_FOR_BB0_BB1_RF(2, 0, 2),
3839 MLO_2_PLUS_2_2RF = MLO_MODE_FOR_BB0_BB1_RF(2, 2, 2),
3840 DBCC_LEGACY = 0xffffffff,
3841 };
3842
3843 enum rtw89_scan_be_operation {
3844 RTW89_SCAN_OP_STOP,
3845 RTW89_SCAN_OP_START,
3846 RTW89_SCAN_OP_SETPARM,
3847 RTW89_SCAN_OP_GETRPT,
3848 RTW89_SCAN_OP_NUM
3849 };
3850
3851 enum rtw89_scan_be_mode {
3852 RTW89_SCAN_MODE_SA,
3853 RTW89_SCAN_MODE_MACC,
3854 RTW89_SCAN_MODE_NUM
3855 };
3856
3857 enum rtw89_scan_be_opmode {
3858 RTW89_SCAN_OPMODE_NONE,
3859 RTW89_SCAN_OPMODE_TBTT,
3860 RTW89_SCAN_OPMODE_INTV,
3861 RTW89_SCAN_OPMODE_CNT,
3862 RTW89_SCAN_OPMODE_NUM,
3863 };
3864
3865 struct rtw89_scan_option {
3866 bool enable;
3867 bool target_ch_mode;
3868 u8 num_macc_role;
3869 u8 num_opch;
3870 u8 repeat;
3871 u16 norm_pd;
3872 u16 slow_pd;
3873 u16 norm_cy;
3874 u8 opch_end;
3875 u16 delay; /* in unit of ms */
3876 u64 prohib_chan;
3877 enum rtw89_phy_idx band;
3878 enum rtw89_scan_be_operation operation;
3879 enum rtw89_scan_be_mode scan_mode;
3880 enum rtw89_mlo_dbcc_mode mlo_mode;
3881 };
3882
3883 enum rtw89_qta_mode {
3884 RTW89_QTA_SCC,
3885 RTW89_QTA_DBCC,
3886 RTW89_QTA_DLFW,
3887 RTW89_QTA_WOW,
3888
3889 /* keep last */
3890 RTW89_QTA_INVALID,
3891 };
3892
3893 struct rtw89_hfc_ch_cfg {
3894 u16 min;
3895 u16 max;
3896 #define grp_0 0
3897 #define grp_1 1
3898 #define grp_num 2
3899 u8 grp;
3900 };
3901
3902 struct rtw89_hfc_ch_info {
3903 u16 aval;
3904 u16 used;
3905 };
3906
3907 struct rtw89_hfc_pub_cfg {
3908 u16 grp0;
3909 u16 grp1;
3910 u16 pub_max;
3911 u16 wp_thrd;
3912 };
3913
3914 struct rtw89_hfc_pub_info {
3915 u16 g0_used;
3916 u16 g1_used;
3917 u16 g0_aval;
3918 u16 g1_aval;
3919 u16 pub_aval;
3920 u16 wp_aval;
3921 };
3922
3923 struct rtw89_hfc_prec_cfg {
3924 u16 ch011_prec;
3925 u16 h2c_prec;
3926 u16 wp_ch07_prec;
3927 u16 wp_ch811_prec;
3928 u8 ch011_full_cond;
3929 u8 h2c_full_cond;
3930 u8 wp_ch07_full_cond;
3931 u8 wp_ch811_full_cond;
3932 };
3933
3934 struct rtw89_hfc_param {
3935 bool en;
3936 bool h2c_en;
3937 u8 mode;
3938 const struct rtw89_hfc_ch_cfg *ch_cfg;
3939 struct rtw89_hfc_ch_info ch_info[RTW89_DMA_CH_NUM];
3940 struct rtw89_hfc_pub_cfg pub_cfg;
3941 struct rtw89_hfc_pub_info pub_info;
3942 struct rtw89_hfc_prec_cfg prec_cfg;
3943 };
3944
3945 struct rtw89_hfc_param_ini {
3946 const struct rtw89_hfc_ch_cfg *ch_cfg;
3947 const struct rtw89_hfc_pub_cfg *pub_cfg;
3948 const struct rtw89_hfc_prec_cfg *prec_cfg;
3949 u8 mode;
3950 };
3951
3952 struct rtw89_dle_size {
3953 u16 pge_size;
3954 u16 lnk_pge_num;
3955 u16 unlnk_pge_num;
3956 /* for WiFi 7 chips below */
3957 u32 srt_ofst;
3958 };
3959
3960 struct rtw89_wde_quota {
3961 u16 hif;
3962 u16 wcpu;
3963 u16 pkt_in;
3964 u16 cpu_io;
3965 };
3966
3967 struct rtw89_ple_quota {
3968 u16 cma0_tx;
3969 u16 cma1_tx;
3970 u16 c2h;
3971 u16 h2c;
3972 u16 wcpu;
3973 u16 mpdu_proc;
3974 u16 cma0_dma;
3975 u16 cma1_dma;
3976 u16 bb_rpt;
3977 u16 wd_rel;
3978 u16 cpu_io;
3979 u16 tx_rpt;
3980 /* for WiFi 7 chips below */
3981 u16 h2d;
3982 };
3983
3984 struct rtw89_rsvd_quota {
3985 u16 mpdu_info_tbl;
3986 u16 b0_csi;
3987 u16 b1_csi;
3988 u16 b0_lmr;
3989 u16 b1_lmr;
3990 u16 b0_ftm;
3991 u16 b1_ftm;
3992 u16 b0_smr;
3993 u16 b1_smr;
3994 u16 others;
3995 };
3996
3997 struct rtw89_dle_rsvd_size {
3998 u32 srt_ofst;
3999 u32 size;
4000 };
4001
4002 struct rtw89_dle_mem {
4003 enum rtw89_qta_mode mode;
4004 const struct rtw89_dle_size *wde_size;
4005 const struct rtw89_dle_size *ple_size;
4006 const struct rtw89_wde_quota *wde_min_qt;
4007 const struct rtw89_wde_quota *wde_max_qt;
4008 const struct rtw89_ple_quota *ple_min_qt;
4009 const struct rtw89_ple_quota *ple_max_qt;
4010 /* for WiFi 7 chips below */
4011 const struct rtw89_rsvd_quota *rsvd_qt;
4012 const struct rtw89_dle_rsvd_size *rsvd0_size;
4013 const struct rtw89_dle_rsvd_size *rsvd1_size;
4014 };
4015
4016 struct rtw89_reg_def {
4017 u32 addr;
4018 u32 mask;
4019 };
4020
4021 struct rtw89_reg2_def {
4022 u32 addr;
4023 u32 data;
4024 };
4025
4026 struct rtw89_reg3_def {
4027 u32 addr;
4028 u32 mask;
4029 u32 data;
4030 };
4031
4032 struct rtw89_reg5_def {
4033 u8 flag; /* recognized by parsers */
4034 u8 path;
4035 u32 addr;
4036 u32 mask;
4037 u32 data;
4038 };
4039
4040 struct rtw89_reg_imr {
4041 u32 addr;
4042 u32 clr;
4043 u32 set;
4044 };
4045
4046 struct rtw89_phy_table {
4047 const struct rtw89_reg2_def *regs;
4048 u32 n_regs;
4049 enum rtw89_rf_path rf_path;
4050 void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg,
4051 enum rtw89_rf_path rf_path, void *data);
4052 };
4053
4054 struct rtw89_txpwr_table {
4055 const void *data;
4056 u32 size;
4057 void (*load)(struct rtw89_dev *rtwdev,
4058 const struct rtw89_txpwr_table *tbl);
4059 };
4060
4061 struct rtw89_txpwr_rule_2ghz {
4062 const s8 (*lmt)[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
4063 [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
4064 [RTW89_REGD_NUM][RTW89_2G_CH_NUM];
4065 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM]
4066 [RTW89_REGD_NUM][RTW89_2G_CH_NUM];
4067 };
4068
4069 struct rtw89_txpwr_rule_5ghz {
4070 const s8 (*lmt)[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
4071 [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
4072 [RTW89_REGD_NUM][RTW89_5G_CH_NUM];
4073 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM]
4074 [RTW89_REGD_NUM][RTW89_5G_CH_NUM];
4075 };
4076
4077 struct rtw89_txpwr_rule_6ghz {
4078 const s8 (*lmt)[RTW89_6G_BW_NUM][RTW89_NTX_NUM]
4079 [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
4080 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER]
4081 [RTW89_6G_CH_NUM];
4082 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM]
4083 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER]
4084 [RTW89_6G_CH_NUM];
4085 };
4086
4087 struct rtw89_tx_shape {
4088 const u8 (*lmt)[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM][RTW89_REGD_NUM];
4089 const u8 (*lmt_ru)[RTW89_BAND_NUM][RTW89_REGD_NUM];
4090 };
4091
4092 struct rtw89_rfe_parms {
4093 const struct rtw89_txpwr_table *byr_tbl;
4094 struct rtw89_txpwr_rule_2ghz rule_2ghz;
4095 struct rtw89_txpwr_rule_5ghz rule_5ghz;
4096 struct rtw89_txpwr_rule_6ghz rule_6ghz;
4097 struct rtw89_txpwr_rule_2ghz rule_da_2ghz;
4098 struct rtw89_txpwr_rule_5ghz rule_da_5ghz;
4099 struct rtw89_txpwr_rule_6ghz rule_da_6ghz;
4100 struct rtw89_tx_shape tx_shape;
4101 bool has_da;
4102 };
4103
4104 struct rtw89_rfe_parms_conf {
4105 const struct rtw89_rfe_parms *rfe_parms;
4106 u8 rfe_type;
4107 };
4108
4109 #define RTW89_TXPWR_CONF_DFLT_RFE_TYPE 0x0
4110
4111 struct rtw89_txpwr_conf {
4112 u8 rfe_type;
4113 u8 ent_sz;
4114 u32 num_ents;
4115 const void *data;
4116 };
4117
rtw89_txpwr_entcpy(void * entry,const void * cursor,u8 size,const struct rtw89_txpwr_conf * conf)4118 static inline bool rtw89_txpwr_entcpy(void *entry, const void *cursor, u8 size,
4119 const struct rtw89_txpwr_conf *conf)
4120 {
4121 u8 valid_size = min(size, conf->ent_sz);
4122
4123 memcpy(entry, cursor, valid_size);
4124 return true;
4125 }
4126
4127 #define rtw89_txpwr_conf_valid(conf) (!!(conf)->data)
4128
4129 #if defined(__linux__)
4130 #define rtw89_for_each_in_txpwr_conf(entry, cursor, conf) \
4131 for (typecheck(const void *, cursor), (cursor) = (conf)->data; \
4132 (cursor) < (conf)->data + (conf)->num_ents * (conf)->ent_sz; \
4133 (cursor) += (conf)->ent_sz) \
4134 if (rtw89_txpwr_entcpy(&(entry), cursor, sizeof(entry), conf))
4135 #elif defined(__FreeBSD__)
4136 #define rtw89_for_each_in_txpwr_conf(entry, cursor, conf) \
4137 for (typecheck(const u8 *, cursor), (cursor) = (conf)->data, \
4138 memcpy(&(entry), cursor, \
4139 min_t(u8, sizeof(entry), (conf)->ent_sz)); \
4140 (cursor) < (const u8 *)(conf)->data + (conf)->num_ents * (conf)->ent_sz; \
4141 (cursor) += (conf)->ent_sz) \
4142 if (rtw89_txpwr_entcpy(&(entry), cursor, sizeof(entry), conf))
4143 #endif
4144
4145 struct rtw89_txpwr_byrate_data {
4146 struct rtw89_txpwr_conf conf;
4147 struct rtw89_txpwr_table tbl;
4148 };
4149
4150 struct rtw89_txpwr_lmt_2ghz_data {
4151 struct rtw89_txpwr_conf conf;
4152 s8 v[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
4153 [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
4154 [RTW89_REGD_NUM][RTW89_2G_CH_NUM];
4155 };
4156
4157 struct rtw89_txpwr_lmt_5ghz_data {
4158 struct rtw89_txpwr_conf conf;
4159 s8 v[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
4160 [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
4161 [RTW89_REGD_NUM][RTW89_5G_CH_NUM];
4162 };
4163
4164 struct rtw89_txpwr_lmt_6ghz_data {
4165 struct rtw89_txpwr_conf conf;
4166 s8 v[RTW89_6G_BW_NUM][RTW89_NTX_NUM]
4167 [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
4168 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER]
4169 [RTW89_6G_CH_NUM];
4170 };
4171
4172 struct rtw89_txpwr_lmt_ru_2ghz_data {
4173 struct rtw89_txpwr_conf conf;
4174 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM]
4175 [RTW89_REGD_NUM][RTW89_2G_CH_NUM];
4176 };
4177
4178 struct rtw89_txpwr_lmt_ru_5ghz_data {
4179 struct rtw89_txpwr_conf conf;
4180 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM]
4181 [RTW89_REGD_NUM][RTW89_5G_CH_NUM];
4182 };
4183
4184 struct rtw89_txpwr_lmt_ru_6ghz_data {
4185 struct rtw89_txpwr_conf conf;
4186 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM]
4187 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER]
4188 [RTW89_6G_CH_NUM];
4189 };
4190
4191 struct rtw89_tx_shape_lmt_data {
4192 struct rtw89_txpwr_conf conf;
4193 u8 v[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM][RTW89_REGD_NUM];
4194 };
4195
4196 struct rtw89_tx_shape_lmt_ru_data {
4197 struct rtw89_txpwr_conf conf;
4198 u8 v[RTW89_BAND_NUM][RTW89_REGD_NUM];
4199 };
4200
4201 struct rtw89_rfe_data {
4202 struct rtw89_txpwr_byrate_data byrate;
4203 struct rtw89_txpwr_lmt_2ghz_data lmt_2ghz;
4204 struct rtw89_txpwr_lmt_5ghz_data lmt_5ghz;
4205 struct rtw89_txpwr_lmt_6ghz_data lmt_6ghz;
4206 struct rtw89_txpwr_lmt_2ghz_data da_lmt_2ghz;
4207 struct rtw89_txpwr_lmt_5ghz_data da_lmt_5ghz;
4208 struct rtw89_txpwr_lmt_6ghz_data da_lmt_6ghz;
4209 struct rtw89_txpwr_lmt_ru_2ghz_data lmt_ru_2ghz;
4210 struct rtw89_txpwr_lmt_ru_5ghz_data lmt_ru_5ghz;
4211 struct rtw89_txpwr_lmt_ru_6ghz_data lmt_ru_6ghz;
4212 struct rtw89_txpwr_lmt_ru_2ghz_data da_lmt_ru_2ghz;
4213 struct rtw89_txpwr_lmt_ru_5ghz_data da_lmt_ru_5ghz;
4214 struct rtw89_txpwr_lmt_ru_6ghz_data da_lmt_ru_6ghz;
4215 struct rtw89_tx_shape_lmt_data tx_shape_lmt;
4216 struct rtw89_tx_shape_lmt_ru_data tx_shape_lmt_ru;
4217 struct rtw89_rfe_parms rfe_parms;
4218 };
4219
4220 struct rtw89_page_regs {
4221 u32 hci_fc_ctrl;
4222 u32 ch_page_ctrl;
4223 u32 ach_page_ctrl;
4224 u32 ach_page_info;
4225 u32 pub_page_info3;
4226 u32 pub_page_ctrl1;
4227 u32 pub_page_ctrl2;
4228 u32 pub_page_info1;
4229 u32 pub_page_info2;
4230 u32 wp_page_ctrl1;
4231 u32 wp_page_ctrl2;
4232 u32 wp_page_info1;
4233 };
4234
4235 struct rtw89_imr_info {
4236 u32 wdrls_imr_set;
4237 u32 wsec_imr_reg;
4238 u32 wsec_imr_set;
4239 u32 mpdu_tx_imr_set;
4240 u32 mpdu_rx_imr_set;
4241 u32 sta_sch_imr_set;
4242 u32 txpktctl_imr_b0_reg;
4243 u32 txpktctl_imr_b0_clr;
4244 u32 txpktctl_imr_b0_set;
4245 u32 txpktctl_imr_b1_reg;
4246 u32 txpktctl_imr_b1_clr;
4247 u32 txpktctl_imr_b1_set;
4248 u32 wde_imr_clr;
4249 u32 wde_imr_set;
4250 u32 ple_imr_clr;
4251 u32 ple_imr_set;
4252 u32 host_disp_imr_clr;
4253 u32 host_disp_imr_set;
4254 u32 cpu_disp_imr_clr;
4255 u32 cpu_disp_imr_set;
4256 u32 other_disp_imr_clr;
4257 u32 other_disp_imr_set;
4258 u32 bbrpt_com_err_imr_reg;
4259 u32 bbrpt_chinfo_err_imr_reg;
4260 u32 bbrpt_err_imr_set;
4261 u32 bbrpt_dfs_err_imr_reg;
4262 u32 ptcl_imr_clr;
4263 u32 ptcl_imr_set;
4264 u32 cdma_imr_0_reg;
4265 u32 cdma_imr_0_clr;
4266 u32 cdma_imr_0_set;
4267 u32 cdma_imr_1_reg;
4268 u32 cdma_imr_1_clr;
4269 u32 cdma_imr_1_set;
4270 u32 phy_intf_imr_reg;
4271 u32 phy_intf_imr_clr;
4272 u32 phy_intf_imr_set;
4273 u32 rmac_imr_reg;
4274 u32 rmac_imr_clr;
4275 u32 rmac_imr_set;
4276 u32 tmac_imr_reg;
4277 u32 tmac_imr_clr;
4278 u32 tmac_imr_set;
4279 };
4280
4281 struct rtw89_imr_table {
4282 const struct rtw89_reg_imr *regs;
4283 u32 n_regs;
4284 };
4285
4286 struct rtw89_xtal_info {
4287 u32 xcap_reg;
4288 u32 sc_xo_mask;
4289 u32 sc_xi_mask;
4290 };
4291
4292 struct rtw89_rrsr_cfgs {
4293 struct rtw89_reg3_def ref_rate;
4294 struct rtw89_reg3_def rsc;
4295 };
4296
4297 struct rtw89_rfkill_regs {
4298 struct rtw89_reg3_def pinmux;
4299 struct rtw89_reg3_def mode;
4300 };
4301
4302 struct rtw89_dig_regs {
4303 u32 seg0_pd_reg;
4304 u32 pd_lower_bound_mask;
4305 u32 pd_spatial_reuse_en;
4306 u32 bmode_pd_reg;
4307 u32 bmode_cca_rssi_limit_en;
4308 u32 bmode_pd_lower_bound_reg;
4309 u32 bmode_rssi_nocca_low_th_mask;
4310 struct rtw89_reg_def p0_lna_init;
4311 struct rtw89_reg_def p1_lna_init;
4312 struct rtw89_reg_def p0_tia_init;
4313 struct rtw89_reg_def p1_tia_init;
4314 struct rtw89_reg_def p0_rxb_init;
4315 struct rtw89_reg_def p1_rxb_init;
4316 struct rtw89_reg_def p0_p20_pagcugc_en;
4317 struct rtw89_reg_def p0_s20_pagcugc_en;
4318 struct rtw89_reg_def p1_p20_pagcugc_en;
4319 struct rtw89_reg_def p1_s20_pagcugc_en;
4320 };
4321
4322 struct rtw89_edcca_regs {
4323 u32 edcca_level;
4324 u32 edcca_mask;
4325 u32 edcca_p_mask;
4326 u32 ppdu_level;
4327 u32 ppdu_mask;
4328 struct rtw89_edcca_p_regs {
4329 u32 rpt_a;
4330 u32 rpt_b;
4331 u32 rpt_sel;
4332 u32 rpt_sel_mask;
4333 } p[RTW89_PHY_NUM];
4334 u32 rpt_sel_be;
4335 u32 rpt_sel_be_mask;
4336 u32 tx_collision_t2r_st;
4337 u32 tx_collision_t2r_st_mask;
4338 };
4339
4340 struct rtw89_phy_ul_tb_info {
4341 bool dyn_tb_tri_en;
4342 u8 def_if_bandedge;
4343 };
4344
4345 struct rtw89_antdiv_stats {
4346 struct ewma_rssi cck_rssi_avg;
4347 struct ewma_rssi ofdm_rssi_avg;
4348 struct ewma_rssi non_legacy_rssi_avg;
4349 u16 pkt_cnt_cck;
4350 u16 pkt_cnt_ofdm;
4351 u16 pkt_cnt_non_legacy;
4352 u32 evm;
4353 };
4354
4355 struct rtw89_antdiv_info {
4356 struct rtw89_antdiv_stats target_stats;
4357 struct rtw89_antdiv_stats main_stats;
4358 struct rtw89_antdiv_stats aux_stats;
4359 u8 training_count;
4360 u8 rssi_pre;
4361 bool get_stats;
4362 };
4363
4364 enum rtw89_chanctx_state {
4365 RTW89_CHANCTX_STATE_MCC_START,
4366 RTW89_CHANCTX_STATE_MCC_STOP,
4367 };
4368
4369 enum rtw89_chanctx_callbacks {
4370 RTW89_CHANCTX_CALLBACK_PLACEHOLDER,
4371 RTW89_CHANCTX_CALLBACK_RFK,
4372 RTW89_CHANCTX_CALLBACK_TAS,
4373
4374 NUM_OF_RTW89_CHANCTX_CALLBACKS,
4375 };
4376
4377 struct rtw89_chanctx_listener {
4378 void (*callbacks[NUM_OF_RTW89_CHANCTX_CALLBACKS])
4379 (struct rtw89_dev *rtwdev, enum rtw89_chanctx_state state);
4380 };
4381
4382 struct rtw89_chip_info {
4383 enum rtw89_core_chip_id chip_id;
4384 enum rtw89_chip_gen chip_gen;
4385 const struct rtw89_chip_ops *ops;
4386 const struct rtw89_mac_gen_def *mac_def;
4387 const struct rtw89_phy_gen_def *phy_def;
4388 const char *fw_basename;
4389 u8 fw_format_max;
4390 bool try_ce_fw;
4391 u8 bbmcu_nr;
4392 u32 needed_fw_elms;
4393 const struct rtw89_fw_blacklist *fw_blacklist;
4394 u32 fifo_size;
4395 bool small_fifo_size;
4396 u32 dle_scc_rsvd_size;
4397 u16 max_amsdu_limit;
4398 bool dis_2g_40m_ul_ofdma;
4399 u32 rsvd_ple_ofst;
4400 const struct rtw89_hfc_param_ini *hfc_param_ini[RTW89_HCI_TYPE_NUM];
4401 const struct rtw89_dle_mem *dle_mem[RTW89_HCI_DLE_TYPE_NUM];
4402 u8 wde_qempty_acq_grpnum;
4403 u8 wde_qempty_mgq_grpsel;
4404 u32 rf_base_addr[2];
4405 u8 thermal_th[2];
4406 u8 support_macid_num;
4407 u8 support_link_num;
4408 u8 support_chanctx_num;
4409 u8 support_bands;
4410 u16 support_bandwidths;
4411 bool support_unii4;
4412 bool support_rnr;
4413 bool support_ant_gain;
4414 bool support_tas;
4415 bool support_sar_by_ant;
4416 bool ul_tb_waveform_ctrl;
4417 bool ul_tb_pwr_diff;
4418 bool rx_freq_frome_ie;
4419 bool hw_sec_hdr;
4420 bool hw_mgmt_tx_encrypt;
4421 bool hw_tkip_crypto;
4422 bool hw_mlo_bmc_crypto;
4423 u8 rf_path_num;
4424 u8 tx_nss;
4425 u8 rx_nss;
4426 u8 acam_num;
4427 u8 bcam_num;
4428 u8 scam_num;
4429 u8 bacam_num;
4430 u8 bacam_dynamic_num;
4431 enum rtw89_bacam_ver bacam_ver;
4432 u8 ppdu_max_usr;
4433
4434 u8 sec_ctrl_efuse_size;
4435 u32 physical_efuse_size;
4436 u32 logical_efuse_size;
4437 u32 limit_efuse_size;
4438 u32 dav_phy_efuse_size;
4439 u32 dav_log_efuse_size;
4440 u32 phycap_addr;
4441 u32 phycap_size;
4442 const struct rtw89_efuse_block_cfg *efuse_blocks;
4443
4444 const struct rtw89_pwr_cfg * const *pwr_on_seq;
4445 const struct rtw89_pwr_cfg * const *pwr_off_seq;
4446 const struct rtw89_phy_table *bb_table;
4447 const struct rtw89_phy_table *bb_gain_table;
4448 const struct rtw89_phy_table *rf_table[RF_PATH_MAX];
4449 const struct rtw89_phy_table *nctl_table;
4450 const struct rtw89_rfk_tbl *nctl_post_table;
4451 const struct rtw89_phy_dig_gain_table *dig_table;
4452 const struct rtw89_dig_regs *dig_regs;
4453 const struct rtw89_phy_tssi_dbw_table *tssi_dbw_table;
4454
4455 /* NULL if no rfe-specific, or a null-terminated array by rfe_parms */
4456 const struct rtw89_rfe_parms_conf *rfe_parms_conf;
4457 const struct rtw89_rfe_parms *dflt_parms;
4458 const struct rtw89_chanctx_listener *chanctx_listener;
4459
4460 u8 txpwr_factor_bb;
4461 u8 txpwr_factor_rf;
4462 u8 txpwr_factor_mac;
4463
4464 u32 para_ver;
4465 u32 wlcx_desired;
4466 u8 scbd;
4467 u8 mailbox;
4468
4469 u8 afh_guard_ch;
4470 const u8 *wl_rssi_thres;
4471 const u8 *bt_rssi_thres;
4472 u8 rssi_tol;
4473
4474 u8 mon_reg_num;
4475 const struct rtw89_btc_fbtc_mreg *mon_reg;
4476 u8 rf_para_ulink_num;
4477 const struct rtw89_btc_rf_trx_para *rf_para_ulink;
4478 u8 rf_para_dlink_num;
4479 const struct rtw89_btc_rf_trx_para *rf_para_dlink;
4480 u8 ps_mode_supported;
4481 u8 low_power_hci_modes;
4482
4483 u32 h2c_cctl_func_id;
4484 u32 hci_func_en_addr;
4485 u32 h2c_desc_size;
4486 u32 txwd_body_size;
4487 u32 txwd_info_size;
4488 u32 h2c_ctrl_reg;
4489 const u32 *h2c_regs;
4490 struct rtw89_reg_def h2c_counter_reg;
4491 u32 c2h_ctrl_reg;
4492 const u32 *c2h_regs;
4493 struct rtw89_reg_def c2h_counter_reg;
4494 const struct rtw89_page_regs *page_regs;
4495 const u32 *wow_reason_reg;
4496 bool cfo_src_fd;
4497 bool cfo_hw_comp;
4498 const struct rtw89_reg_def *dcfo_comp;
4499 u8 dcfo_comp_sft;
4500 const struct rtw89_imr_info *imr_info;
4501 const struct rtw89_imr_table *imr_dmac_table;
4502 const struct rtw89_imr_table *imr_cmac_table;
4503 const struct rtw89_rrsr_cfgs *rrsr_cfgs;
4504 struct rtw89_reg_def bss_clr_vld;
4505 u32 bss_clr_map_reg;
4506 const struct rtw89_rfkill_regs *rfkill_init;
4507 struct rtw89_reg_def rfkill_get;
4508 u32 dma_ch_mask;
4509 const struct rtw89_edcca_regs *edcca_regs;
4510 const struct wiphy_wowlan_support *wowlan_stub;
4511 const struct rtw89_xtal_info *xtal_info;
4512 };
4513
4514 struct rtw89_chip_variant {
4515 bool no_mcs_12_13: 1;
4516 u32 fw_min_ver_code;
4517 };
4518
4519 union rtw89_bus_info {
4520 const struct rtw89_pci_info *pci;
4521 };
4522
4523 struct rtw89_driver_info {
4524 const struct rtw89_chip_info *chip;
4525 const struct rtw89_chip_variant *variant;
4526 const struct dmi_system_id *quirks;
4527 union rtw89_bus_info bus;
4528 };
4529
4530 enum rtw89_hcifc_mode {
4531 RTW89_HCIFC_POH = 0,
4532 RTW89_HCIFC_STF = 1,
4533 RTW89_HCIFC_SDIO = 2,
4534
4535 /* keep last */
4536 RTW89_HCIFC_MODE_INVALID,
4537 };
4538
4539 struct rtw89_dle_info {
4540 const struct rtw89_rsvd_quota *rsvd_qt;
4541 enum rtw89_qta_mode qta_mode;
4542 u16 ple_pg_size;
4543 u16 ple_free_pg;
4544 u16 c0_rx_qta;
4545 u16 c1_rx_qta;
4546 };
4547
4548 enum rtw89_host_rpr_mode {
4549 RTW89_RPR_MODE_POH = 0,
4550 RTW89_RPR_MODE_STF
4551 };
4552
4553 #define RTW89_COMPLETION_BUF_SIZE 40
4554 #define RTW89_WAIT_COND_IDLE UINT_MAX
4555
4556 struct rtw89_completion_data {
4557 bool err;
4558 u8 buf[RTW89_COMPLETION_BUF_SIZE];
4559 };
4560
4561 struct rtw89_wait_info {
4562 atomic_t cond;
4563 struct completion completion;
4564 struct rtw89_completion_data data;
4565 };
4566
4567 #define RTW89_WAIT_FOR_COND_TIMEOUT msecs_to_jiffies(100)
4568
rtw89_init_wait(struct rtw89_wait_info * wait)4569 static inline void rtw89_init_wait(struct rtw89_wait_info *wait)
4570 {
4571 init_completion(&wait->completion);
4572 atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE);
4573 }
4574
4575 struct rtw89_mac_info {
4576 struct rtw89_dle_info dle_info;
4577 struct rtw89_hfc_param hfc_param;
4578 enum rtw89_qta_mode qta_mode;
4579 u8 rpwm_seq_num;
4580 u8 cpwm_seq_num;
4581
4582 /* see RTW89_FW_OFLD_WAIT_COND series for wait condition */
4583 struct rtw89_wait_info fw_ofld_wait;
4584 /* see RTW89_PS_WAIT_COND series for wait condition */
4585 struct rtw89_wait_info ps_wait;
4586 };
4587
4588 enum rtw89_fwdl_check_type {
4589 RTW89_FWDL_CHECK_FREERTOS_DONE,
4590 RTW89_FWDL_CHECK_WCPU_FWDL_DONE,
4591 RTW89_FWDL_CHECK_DCPU_FWDL_DONE,
4592 RTW89_FWDL_CHECK_BB0_FWDL_DONE,
4593 RTW89_FWDL_CHECK_BB1_FWDL_DONE,
4594 };
4595
4596 enum rtw89_fw_type {
4597 RTW89_FW_NORMAL = 1,
4598 RTW89_FW_WOWLAN = 3,
4599 RTW89_FW_NORMAL_CE = 5,
4600 RTW89_FW_BBMCU0 = 64,
4601 RTW89_FW_BBMCU1 = 65,
4602 RTW89_FW_LOGFMT = 255,
4603 };
4604
4605 #define RTW89_FW_FEATURE_GROUP(_grp, _features...) \
4606 RTW89_FW_FEATURE_##_grp##_MIN, \
4607 __RTW89_FW_FEATURE_##_grp##_S = RTW89_FW_FEATURE_##_grp##_MIN - 1, \
4608 _features \
4609 __RTW89_FW_FEATURE_##_grp##_E, \
4610 RTW89_FW_FEATURE_##_grp##_MAX = __RTW89_FW_FEATURE_##_grp##_E - 1
4611
4612 enum rtw89_fw_feature {
4613 RTW89_FW_FEATURE_OLD_HT_RA_FORMAT,
4614 RTW89_FW_FEATURE_SCAN_OFFLOAD,
4615 RTW89_FW_FEATURE_TX_WAKE,
4616 RTW89_FW_FEATURE_GROUP(CRASH_TRIGGER,
4617 RTW89_FW_FEATURE_CRASH_TRIGGER_TYPE_0,
4618 RTW89_FW_FEATURE_CRASH_TRIGGER_TYPE_1,
4619 ),
4620 RTW89_FW_FEATURE_NO_PACKET_DROP,
4621 RTW89_FW_FEATURE_NO_DEEP_PS,
4622 RTW89_FW_FEATURE_NO_LPS_PG,
4623 RTW89_FW_FEATURE_BEACON_FILTER,
4624 RTW89_FW_FEATURE_MACID_PAUSE_SLEEP,
4625 RTW89_FW_FEATURE_SCAN_OFFLOAD_BE_V0,
4626 RTW89_FW_FEATURE_WOW_REASON_V1,
4627 RTW89_FW_FEATURE_RFK_PRE_NOTIFY_V0,
4628 RTW89_FW_FEATURE_RFK_PRE_NOTIFY_V1,
4629 RTW89_FW_FEATURE_RFK_RXDCK_V0,
4630 RTW89_FW_FEATURE_RFK_IQK_V0,
4631 RTW89_FW_FEATURE_NO_WOW_CPU_IO_RX,
4632 RTW89_FW_FEATURE_NOTIFY_AP_INFO,
4633 RTW89_FW_FEATURE_CH_INFO_BE_V0,
4634 RTW89_FW_FEATURE_LPS_CH_INFO,
4635 RTW89_FW_FEATURE_NO_PHYCAP_P1,
4636 RTW89_FW_FEATURE_NO_POWER_DIFFERENCE,
4637 RTW89_FW_FEATURE_BEACON_LOSS_COUNT_V1,
4638 RTW89_FW_FEATURE_SCAN_OFFLOAD_EXTRA_OP,
4639 RTW89_FW_FEATURE_RFK_NTFY_MCC_V0,
4640 RTW89_FW_FEATURE_LPS_DACK_BY_C2H_REG,
4641 };
4642
4643 struct rtw89_fw_suit {
4644 enum rtw89_fw_type type;
4645 const u8 *data;
4646 u32 size;
4647 u8 major_ver;
4648 u8 minor_ver;
4649 u8 sub_ver;
4650 u8 sub_idex;
4651 u16 build_year;
4652 u16 build_mon;
4653 u16 build_date;
4654 u16 build_hour;
4655 u16 build_min;
4656 u8 cmd_ver;
4657 u8 hdr_ver;
4658 u32 commitid;
4659 };
4660
4661 #define RTW89_FW_VER_CODE(major, minor, sub, idx) \
4662 (((major) << 24) | ((minor) << 16) | ((sub) << 8) | (idx))
4663 #define RTW89_FW_SUIT_VER_CODE(s) \
4664 RTW89_FW_VER_CODE((s)->major_ver, (s)->minor_ver, (s)->sub_ver, (s)->sub_idex)
4665
4666 #define RTW89_MFW_HDR_VER_CODE(mfw_hdr) \
4667 RTW89_FW_VER_CODE((mfw_hdr)->ver.major, \
4668 (mfw_hdr)->ver.minor, \
4669 (mfw_hdr)->ver.sub, \
4670 (mfw_hdr)->ver.idx)
4671
4672 #define RTW89_FW_HDR_VER_CODE(fw_hdr) \
4673 RTW89_FW_VER_CODE(le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MAJOR_VERSION), \
4674 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MINOR_VERSION), \
4675 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBVERSION), \
4676 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBINDEX))
4677
4678 struct rtw89_fw_req_info {
4679 const struct firmware *firmware;
4680 struct completion completion;
4681 };
4682
4683 struct rtw89_fw_log {
4684 struct rtw89_fw_suit suit;
4685 bool enable;
4686 u32 last_fmt_id;
4687 u32 fmt_count;
4688 const __le32 *fmt_ids;
4689 const char *(*fmts)[];
4690 };
4691
4692 struct rtw89_fw_elm_info {
4693 struct rtw89_phy_table *bb_tbl;
4694 struct rtw89_phy_table *bb_gain;
4695 struct rtw89_phy_table *rf_radio[RF_PATH_MAX];
4696 struct rtw89_phy_table *rf_nctl;
4697 struct rtw89_fw_txpwr_track_cfg *txpwr_trk;
4698 struct rtw89_phy_rfk_log_fmt *rfk_log_fmt;
4699 const struct rtw89_regd_data *regd;
4700 };
4701
4702 enum rtw89_fw_mss_dev_type {
4703 RTW89_FW_MSS_DEV_TYPE_FWSEC_DEF = 0xF,
4704 RTW89_FW_MSS_DEV_TYPE_FWSEC_INV = 0xFF,
4705 };
4706
4707 struct rtw89_fw_secure {
4708 bool secure_boot: 1;
4709 bool can_mss_v1: 1;
4710 bool can_mss_v0: 1;
4711 u32 sb_sel_mgn;
4712 u8 mss_dev_type;
4713 u8 mss_cust_idx;
4714 u8 mss_key_num;
4715 u8 mss_idx; /* v0 */
4716 };
4717
4718 struct rtw89_fw_info {
4719 struct rtw89_fw_req_info req;
4720 int fw_format;
4721 u8 h2c_seq;
4722 u8 rec_seq;
4723 u8 h2c_counter;
4724 u8 c2h_counter;
4725 struct rtw89_fw_suit normal;
4726 struct rtw89_fw_suit wowlan;
4727 struct rtw89_fw_suit bbmcu0;
4728 struct rtw89_fw_suit bbmcu1;
4729 struct rtw89_fw_log log;
4730 u32 feature_map;
4731 struct rtw89_fw_elm_info elm_info;
4732 struct rtw89_fw_secure sec;
4733 };
4734
4735 #define RTW89_CHK_FW_FEATURE(_feat, _fw) \
4736 (!!((_fw)->feature_map & BIT(RTW89_FW_FEATURE_ ## _feat)))
4737
4738 #define RTW89_CHK_FW_FEATURE_GROUP(_grp, _fw) \
4739 (!!((_fw)->feature_map & GENMASK(RTW89_FW_FEATURE_ ## _grp ## _MAX, \
4740 RTW89_FW_FEATURE_ ## _grp ## _MIN)))
4741
4742 #define RTW89_SET_FW_FEATURE(_fw_feature, _fw) \
4743 ((_fw)->feature_map |= BIT(_fw_feature))
4744
4745 struct rtw89_cam_info {
4746 DECLARE_BITMAP(addr_cam_map, RTW89_MAX_ADDR_CAM_NUM);
4747 DECLARE_BITMAP(bssid_cam_map, RTW89_MAX_BSSID_CAM_NUM);
4748 DECLARE_BITMAP(sec_cam_map, RTW89_MAX_SEC_CAM_NUM);
4749 DECLARE_BITMAP(ba_cam_map, RTW89_MAX_BA_CAM_NUM);
4750 struct rtw89_ba_cam_entry ba_cam_entry[RTW89_MAX_BA_CAM_NUM];
4751 const struct rtw89_sec_cam_entry *sec_entries[RTW89_MAX_SEC_CAM_NUM];
4752 };
4753
4754 enum rtw89_sar_sources {
4755 RTW89_SAR_SOURCE_NONE,
4756 RTW89_SAR_SOURCE_COMMON,
4757 RTW89_SAR_SOURCE_ACPI,
4758
4759 RTW89_SAR_SOURCE_NR,
4760 };
4761
4762 enum rtw89_sar_subband {
4763 RTW89_SAR_2GHZ_SUBBAND,
4764 RTW89_SAR_5GHZ_SUBBAND_1_2, /* U-NII-1 and U-NII-2 */
4765 RTW89_SAR_5GHZ_SUBBAND_2_E, /* U-NII-2-Extended */
4766 RTW89_SAR_5GHZ_SUBBAND_3_4, /* U-NII-3 and U-NII-4 */
4767 RTW89_SAR_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */
4768 RTW89_SAR_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */
4769 RTW89_SAR_6GHZ_SUBBAND_6, /* U-NII-6 */
4770 RTW89_SAR_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */
4771 RTW89_SAR_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */
4772 RTW89_SAR_6GHZ_SUBBAND_8, /* U-NII-8 */
4773
4774 RTW89_SAR_SUBBAND_NR,
4775 };
4776
4777 struct rtw89_sar_cfg_common {
4778 bool set[RTW89_SAR_SUBBAND_NR];
4779 s32 cfg[RTW89_SAR_SUBBAND_NR];
4780 };
4781
4782 enum rtw89_acpi_sar_subband {
4783 RTW89_ACPI_SAR_2GHZ_SUBBAND,
4784 RTW89_ACPI_SAR_5GHZ_SUBBAND_1, /* U-NII-1 */
4785 RTW89_ACPI_SAR_5GHZ_SUBBAND_2, /* U-NII-2 */
4786 RTW89_ACPI_SAR_5GHZ_SUBBAND_2E, /* U-NII-2-Extended */
4787 RTW89_ACPI_SAR_5GHZ_SUBBAND_3_4, /* U-NII-3 and U-NII-4 */
4788 RTW89_ACPI_SAR_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */
4789 RTW89_ACPI_SAR_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */
4790 RTW89_ACPI_SAR_6GHZ_SUBBAND_6, /* U-NII-6 */
4791 RTW89_ACPI_SAR_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */
4792 RTW89_ACPI_SAR_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */
4793 RTW89_ACPI_SAR_6GHZ_SUBBAND_8, /* U-NII-8 */
4794
4795 NUM_OF_RTW89_ACPI_SAR_SUBBAND,
4796 RTW89_ACPI_SAR_SUBBAND_NR_LEGACY = RTW89_ACPI_SAR_5GHZ_SUBBAND_3_4 + 1,
4797 RTW89_ACPI_SAR_SUBBAND_NR_HAS_6GHZ = RTW89_ACPI_SAR_6GHZ_SUBBAND_8 + 1,
4798 };
4799
4800 #define TXPWR_FACTOR_OF_RTW89_ACPI_SAR 3 /* unit: 0.125 dBm */
4801 #define MAX_VAL_OF_RTW89_ACPI_SAR S16_MAX
4802 #define MIN_VAL_OF_RTW89_ACPI_SAR S16_MIN
4803 #define MAX_NUM_OF_RTW89_ACPI_SAR_TBL 6
4804 #define NUM_OF_RTW89_ACPI_SAR_RF_PATH (RF_PATH_B + 1)
4805
4806 struct rtw89_sar_entry_from_acpi {
4807 s16 v[NUM_OF_RTW89_ACPI_SAR_SUBBAND][NUM_OF_RTW89_ACPI_SAR_RF_PATH];
4808 };
4809
4810 struct rtw89_sar_table_from_acpi {
4811 /* If this table is active, must fill all fields according to either
4812 * configuration in BIOS or some default values for SAR to work well.
4813 */
4814 struct rtw89_sar_entry_from_acpi entries[RTW89_REGD_NUM];
4815 };
4816
4817 struct rtw89_sar_indicator_from_acpi {
4818 bool enable_sync;
4819 unsigned int fields;
4820 u8 (*rfpath_to_antidx)(enum rtw89_rf_path rfpath);
4821
4822 /* Select among @tables of container, rtw89_sar_cfg_acpi, by path.
4823 * Not design with pointers since addresses will be invalid after
4824 * sync content with local container instance.
4825 */
4826 u8 tblsel[NUM_OF_RTW89_ACPI_SAR_RF_PATH];
4827 };
4828
4829 struct rtw89_sar_cfg_acpi {
4830 u8 downgrade_2tx;
4831 unsigned int valid_num;
4832 struct rtw89_sar_table_from_acpi tables[MAX_NUM_OF_RTW89_ACPI_SAR_TBL];
4833 struct rtw89_sar_indicator_from_acpi indicator;
4834 };
4835
4836 struct rtw89_sar_info {
4837 /* used to decide how to access SAR cfg union */
4838 enum rtw89_sar_sources src;
4839
4840 /* reserved for different knids of SAR cfg struct.
4841 * supposed that a single cfg struct cannot handle various SAR sources.
4842 */
4843 union {
4844 struct rtw89_sar_cfg_common cfg_common;
4845 struct rtw89_sar_cfg_acpi cfg_acpi;
4846 };
4847 };
4848
4849 enum rtw89_ant_gain_subband {
4850 RTW89_ANT_GAIN_2GHZ_SUBBAND,
4851 RTW89_ANT_GAIN_5GHZ_SUBBAND_1, /* U-NII-1 */
4852 RTW89_ANT_GAIN_5GHZ_SUBBAND_2, /* U-NII-2 */
4853 RTW89_ANT_GAIN_5GHZ_SUBBAND_2E, /* U-NII-2-Extended */
4854 RTW89_ANT_GAIN_5GHZ_SUBBAND_3_4, /* U-NII-3 and U-NII-4 */
4855 RTW89_ANT_GAIN_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */
4856 RTW89_ANT_GAIN_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */
4857 RTW89_ANT_GAIN_6GHZ_SUBBAND_6, /* U-NII-6 */
4858 RTW89_ANT_GAIN_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */
4859 RTW89_ANT_GAIN_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */
4860 RTW89_ANT_GAIN_6GHZ_SUBBAND_8, /* U-NII-8 */
4861
4862 RTW89_ANT_GAIN_SUBBAND_NR,
4863 };
4864
4865 enum rtw89_ant_gain_domain_type {
4866 RTW89_ANT_GAIN_ETSI = 0,
4867
4868 RTW89_ANT_GAIN_DOMAIN_NUM,
4869 };
4870
4871 #define RTW89_ANT_GAIN_CHAIN_NUM 2
4872 struct rtw89_ant_gain_info {
4873 s8 offset[RTW89_ANT_GAIN_CHAIN_NUM][RTW89_ANT_GAIN_SUBBAND_NR];
4874 u32 regd_enabled;
4875 bool block_country;
4876 };
4877
4878 struct rtw89_6ghz_span {
4879 enum rtw89_sar_subband sar_subband_low;
4880 enum rtw89_sar_subband sar_subband_high;
4881 enum rtw89_acpi_sar_subband acpi_sar_subband_low;
4882 enum rtw89_acpi_sar_subband acpi_sar_subband_high;
4883 enum rtw89_ant_gain_subband ant_gain_subband_low;
4884 enum rtw89_ant_gain_subband ant_gain_subband_high;
4885 };
4886
4887 #define RTW89_SAR_SPAN_VALID(span) ((span)->sar_subband_high)
4888 #define RTW89_ACPI_SAR_SPAN_VALID(span) ((span)->acpi_sar_subband_high)
4889 #define RTW89_ANT_GAIN_SPAN_VALID(span) ((span)->ant_gain_subband_high)
4890
4891 enum rtw89_tas_state {
4892 RTW89_TAS_STATE_DPR_OFF,
4893 RTW89_TAS_STATE_DPR_ON,
4894 RTW89_TAS_STATE_STATIC_SAR,
4895 };
4896
4897 #define RTW89_TAS_TX_RATIO_WINDOW 6
4898 #define RTW89_TAS_TXPWR_WINDOW 180
4899 struct rtw89_tas_info {
4900 u16 tx_ratio_history[RTW89_TAS_TX_RATIO_WINDOW];
4901 u64 txpwr_history[RTW89_TAS_TXPWR_WINDOW];
4902 u8 enabled_countries;
4903 u8 txpwr_head_idx;
4904 u8 txpwr_tail_idx;
4905 u8 tx_ratio_idx;
4906 u16 total_tx_ratio;
4907 u64 total_txpwr;
4908 u64 instant_txpwr;
4909 u32 window_size;
4910 s8 dpr_on_threshold;
4911 s8 dpr_off_threshold;
4912 enum rtw89_tas_state backup_state;
4913 enum rtw89_tas_state state;
4914 bool keep_history;
4915 bool block_regd;
4916 bool enable;
4917 bool pause;
4918 };
4919
4920 struct rtw89_chanctx_cfg {
4921 enum rtw89_chanctx_idx idx;
4922 int ref_count;
4923 };
4924
4925 enum rtw89_chanctx_changes {
4926 RTW89_CHANCTX_REMOTE_STA_CHANGE,
4927 RTW89_CHANCTX_BCN_OFFSET_CHANGE,
4928 RTW89_CHANCTX_P2P_PS_CHANGE,
4929 RTW89_CHANCTX_BT_SLOT_CHANGE,
4930 RTW89_CHANCTX_TSF32_TOGGLE_CHANGE,
4931
4932 NUM_OF_RTW89_CHANCTX_CHANGES,
4933 RTW89_CHANCTX_CHANGE_DFLT = NUM_OF_RTW89_CHANCTX_CHANGES,
4934 };
4935
4936 enum rtw89_entity_mode {
4937 RTW89_ENTITY_MODE_SCC_OR_SMLD,
4938 RTW89_ENTITY_MODE_MCC_PREPARE,
4939 RTW89_ENTITY_MODE_MCC,
4940
4941 NUM_OF_RTW89_ENTITY_MODE,
4942 RTW89_ENTITY_MODE_INVALID = -EINVAL,
4943 RTW89_ENTITY_MODE_UNHANDLED = -ESRCH,
4944 };
4945
4946 #define RTW89_MAX_INTERFACE_NUM 2
4947
4948 /* only valid when running with chanctx_ops */
4949 struct rtw89_entity_mgnt {
4950 struct list_head active_list;
4951 struct rtw89_vif *active_roles[RTW89_MAX_INTERFACE_NUM];
4952 enum rtw89_chanctx_idx chanctx_tbl[RTW89_MAX_INTERFACE_NUM]
4953 [__RTW89_MLD_MAX_LINK_NUM];
4954 };
4955
4956 struct rtw89_chanctx {
4957 struct cfg80211_chan_def chandef;
4958 struct rtw89_chan chan;
4959 struct rtw89_chan_rcd rcd;
4960
4961 /* only assigned when running with chanctx_ops */
4962 struct rtw89_chanctx_cfg *cfg;
4963 };
4964
4965 struct rtw89_edcca_bak {
4966 u8 a;
4967 u8 p;
4968 u8 ppdu;
4969 u8 th_old;
4970 };
4971
4972 enum rtw89_dm_type {
4973 RTW89_DM_DYNAMIC_EDCCA,
4974 RTW89_DM_THERMAL_PROTECT,
4975 RTW89_DM_TAS,
4976 RTW89_DM_MLO,
4977 };
4978
4979 #define RTW89_THERMAL_PROT_LV_MAX 5
4980 #define RTW89_THERMAL_PROT_STEP 5 /* -5% for each level */
4981
4982 struct rtw89_hal {
4983 u32 rx_fltr;
4984 u8 cv;
4985 u8 acv;
4986 u32 antenna_tx;
4987 u32 antenna_rx;
4988 u8 tx_nss;
4989 u8 rx_nss;
4990 bool tx_path_diversity;
4991 bool ant_diversity;
4992 bool ant_diversity_fixed;
4993 bool support_cckpd;
4994 bool support_igi;
4995 bool no_mcs_12_13;
4996
4997 atomic_t roc_chanctx_idx;
4998 u8 roc_link_index;
4999
5000 DECLARE_BITMAP(changes, NUM_OF_RTW89_CHANCTX_CHANGES);
5001 DECLARE_BITMAP(entity_map, NUM_OF_RTW89_CHANCTX);
5002 struct rtw89_chanctx chanctx[NUM_OF_RTW89_CHANCTX];
5003 struct cfg80211_chan_def roc_chandef;
5004
5005 bool entity_active[RTW89_PHY_NUM];
5006 bool entity_pause;
5007 enum rtw89_entity_mode entity_mode;
5008 struct rtw89_entity_mgnt entity_mgnt;
5009
5010 u32 disabled_dm_bitmap; /* bitmap of enum rtw89_dm_type */
5011
5012 u8 thermal_prot_th;
5013 u8 thermal_prot_lv; /* 0 ~ RTW89_THERMAL_PROT_LV_MAX */
5014 };
5015
5016 #define RTW89_MAX_MAC_ID_NUM 128
5017 #define RTW89_MAX_PKT_OFLD_NUM 255
5018
5019 enum rtw89_flags {
5020 RTW89_FLAG_POWERON,
5021 RTW89_FLAG_DMAC_FUNC,
5022 RTW89_FLAG_CMAC0_FUNC,
5023 RTW89_FLAG_CMAC1_FUNC,
5024 RTW89_FLAG_FW_RDY,
5025 RTW89_FLAG_RUNNING,
5026 RTW89_FLAG_PROBE_DONE,
5027 RTW89_FLAG_BFEE_MON,
5028 RTW89_FLAG_BFEE_EN,
5029 RTW89_FLAG_BFEE_TIMER_KEEP,
5030 RTW89_FLAG_NAPI_RUNNING,
5031 RTW89_FLAG_LEISURE_PS,
5032 RTW89_FLAG_LOW_POWER_MODE,
5033 RTW89_FLAG_INACTIVE_PS,
5034 RTW89_FLAG_CRASH_SIMULATING,
5035 RTW89_FLAG_SER_HANDLING,
5036 RTW89_FLAG_WOWLAN,
5037 RTW89_FLAG_FORBIDDEN_TRACK_WORK,
5038 RTW89_FLAG_CHANGING_INTERFACE,
5039 RTW89_FLAG_HW_RFKILL_STATE,
5040 RTW89_FLAG_UNPLUGGED,
5041
5042 NUM_OF_RTW89_FLAGS,
5043 };
5044
5045 enum rtw89_quirks {
5046 RTW89_QUIRK_PCI_BER,
5047 RTW89_QUIRK_THERMAL_PROT_120C,
5048 RTW89_QUIRK_THERMAL_PROT_110C,
5049
5050 NUM_OF_RTW89_QUIRKS,
5051 };
5052
5053 enum rtw89_custid {
5054 RTW89_CUSTID_NONE,
5055 RTW89_CUSTID_ACER,
5056 RTW89_CUSTID_AMD,
5057 RTW89_CUSTID_ASUS,
5058 RTW89_CUSTID_DELL,
5059 RTW89_CUSTID_HP,
5060 RTW89_CUSTID_LENOVO,
5061 };
5062
5063 enum rtw89_pkt_drop_sel {
5064 RTW89_PKT_DROP_SEL_MACID_BE_ONCE,
5065 RTW89_PKT_DROP_SEL_MACID_BK_ONCE,
5066 RTW89_PKT_DROP_SEL_MACID_VI_ONCE,
5067 RTW89_PKT_DROP_SEL_MACID_VO_ONCE,
5068 RTW89_PKT_DROP_SEL_MACID_ALL,
5069 RTW89_PKT_DROP_SEL_MG0_ONCE,
5070 RTW89_PKT_DROP_SEL_HIQ_ONCE,
5071 RTW89_PKT_DROP_SEL_HIQ_PORT,
5072 RTW89_PKT_DROP_SEL_HIQ_MBSSID,
5073 RTW89_PKT_DROP_SEL_BAND,
5074 RTW89_PKT_DROP_SEL_BAND_ONCE,
5075 RTW89_PKT_DROP_SEL_REL_MACID,
5076 RTW89_PKT_DROP_SEL_REL_HIQ_PORT,
5077 RTW89_PKT_DROP_SEL_REL_HIQ_MBSSID,
5078 };
5079
5080 struct rtw89_pkt_drop_params {
5081 enum rtw89_pkt_drop_sel sel;
5082 enum rtw89_mac_idx mac_band;
5083 u8 macid;
5084 u8 port;
5085 u8 mbssid;
5086 bool tf_trs;
5087 u32 macid_band_sel[4];
5088 };
5089
5090 struct rtw89_pkt_stat {
5091 u16 beacon_nr;
5092 u8 beacon_rate;
5093 u32 rx_rate_cnt[RTW89_HW_RATE_NR];
5094 };
5095
5096 DECLARE_EWMA(thermal, 4, 4);
5097
5098 struct rtw89_phy_stat {
5099 struct ewma_thermal avg_thermal[RF_PATH_MAX];
5100 u8 last_thermal_max;
5101 struct ewma_rssi bcn_rssi;
5102 struct rtw89_pkt_stat cur_pkt_stat;
5103 struct rtw89_pkt_stat last_pkt_stat;
5104 };
5105
5106 enum rtw89_rfk_report_state {
5107 RTW89_RFK_STATE_START = 0x0,
5108 RTW89_RFK_STATE_OK = 0x1,
5109 RTW89_RFK_STATE_FAIL = 0x2,
5110 RTW89_RFK_STATE_TIMEOUT = 0x3,
5111 RTW89_RFK_STATE_H2C_CMD_ERR = 0x4,
5112 };
5113
5114 struct rtw89_rfk_wait_info {
5115 struct completion completion;
5116 ktime_t start_time;
5117 enum rtw89_rfk_report_state state;
5118 u8 version;
5119 };
5120
5121 #define RTW89_DACK_PATH_NR 2
5122 #define RTW89_DACK_IDX_NR 2
5123 #define RTW89_DACK_MSBK_NR 16
5124 struct rtw89_dack_info {
5125 bool dack_done;
5126 u8 msbk_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR][RTW89_DACK_MSBK_NR];
5127 u8 dadck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR];
5128 u16 addck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR];
5129 u16 biask_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR];
5130 u32 dack_cnt;
5131 bool addck_timeout[RTW89_DACK_PATH_NR];
5132 bool dadck_timeout[RTW89_DACK_PATH_NR];
5133 bool msbk_timeout[RTW89_DACK_PATH_NR];
5134 };
5135
5136 enum rtw89_rfk_chs_nrs {
5137 __RTW89_RFK_CHS_NR_V0 = 2,
5138 __RTW89_RFK_CHS_NR_V1 = 3,
5139
5140 RTW89_RFK_CHS_NR = __RTW89_RFK_CHS_NR_V1,
5141 };
5142
5143 struct rtw89_rfk_mcc_info_data {
5144 u8 ch[RTW89_RFK_CHS_NR];
5145 u8 band[RTW89_RFK_CHS_NR];
5146 u8 bw[RTW89_RFK_CHS_NR];
5147 u8 table_idx;
5148 };
5149
5150 struct rtw89_rfk_mcc_info {
5151 struct rtw89_rfk_mcc_info_data data[2];
5152 };
5153
5154 #define RTW89_IQK_CHS_NR 2
5155 #define RTW89_IQK_PATH_NR 4
5156
5157 struct rtw89_lck_info {
5158 u8 thermal[RF_PATH_MAX];
5159 };
5160
5161 struct rtw89_rx_dck_info {
5162 u8 thermal[RF_PATH_MAX];
5163 };
5164
5165 struct rtw89_iqk_info {
5166 bool lok_cor_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
5167 bool lok_fin_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
5168 bool lok_fail[RTW89_IQK_PATH_NR];
5169 bool iqk_tx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
5170 bool iqk_rx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
5171 u32 iqk_fail_cnt;
5172 bool is_iqk_init;
5173 u32 iqk_channel[RTW89_IQK_CHS_NR];
5174 u8 iqk_band[RTW89_IQK_PATH_NR];
5175 u8 iqk_ch[RTW89_IQK_PATH_NR];
5176 u8 iqk_bw[RTW89_IQK_PATH_NR];
5177 u8 iqk_times;
5178 u8 version;
5179 u32 nb_txcfir[RTW89_IQK_PATH_NR];
5180 u32 nb_rxcfir[RTW89_IQK_PATH_NR];
5181 u32 bp_txkresult[RTW89_IQK_PATH_NR];
5182 u32 bp_rxkresult[RTW89_IQK_PATH_NR];
5183 u32 bp_iqkenable[RTW89_IQK_PATH_NR];
5184 bool is_wb_txiqk[RTW89_IQK_PATH_NR];
5185 bool is_wb_rxiqk[RTW89_IQK_PATH_NR];
5186 bool is_nbiqk;
5187 bool iqk_fft_en;
5188 bool iqk_xym_en;
5189 bool iqk_sram_en;
5190 bool iqk_cfir_en;
5191 u32 syn1to2;
5192 u8 iqk_mcc_ch[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
5193 u8 iqk_table_idx[RTW89_IQK_PATH_NR];
5194 u32 lok_idac[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
5195 u32 lok_vbuf[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
5196 };
5197
5198 #define RTW89_DPK_RF_PATH 2
5199 #define RTW89_DPK_AVG_THERMAL_NUM 8
5200 #define RTW89_DPK_BKUP_NUM 2
5201 struct rtw89_dpk_bkup_para {
5202 enum rtw89_band band;
5203 enum rtw89_bandwidth bw;
5204 u8 ch;
5205 u8 path_ok;
5206 u8 mdpd_en;
5207 u8 txagc_dpk;
5208 u8 ther_dpk;
5209 u8 gs;
5210 u16 pwsf;
5211 };
5212
5213 struct rtw89_dpk_info {
5214 bool is_dpk_enable;
5215 bool is_dpk_reload_en;
5216 u8 dpk_gs[RTW89_PHY_NUM];
5217 u16 dc_i[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
5218 u16 dc_q[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
5219 u8 corr_val[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
5220 u8 corr_idx[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
5221 u8 cur_idx[RTW89_DPK_RF_PATH];
5222 u8 cur_k_set;
5223 struct rtw89_dpk_bkup_para bp[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
5224 u8 max_dpk_txagc[RTW89_DPK_RF_PATH];
5225 u32 dpk_order[RTW89_DPK_RF_PATH];
5226 };
5227
5228 struct rtw89_fem_info {
5229 bool elna_2g;
5230 bool elna_5g;
5231 bool epa_2g;
5232 bool epa_5g;
5233 bool epa_6g;
5234 };
5235
5236 struct rtw89_phy_ch_info {
5237 u8 rssi_min;
5238 u16 rssi_min_macid;
5239 u8 pre_rssi_min;
5240 u8 rssi_max;
5241 u16 rssi_max_macid;
5242 u8 rxsc_160;
5243 u8 rxsc_80;
5244 u8 rxsc_40;
5245 u8 rxsc_20;
5246 u8 rxsc_l;
5247 u8 is_noisy;
5248 };
5249
5250 struct rtw89_agc_gaincode_set {
5251 u8 lna_idx;
5252 u8 tia_idx;
5253 u8 rxb_idx;
5254 };
5255
5256 #define IGI_RSSI_TH_NUM 5
5257 #define FA_TH_NUM 4
5258 #define TIA_LNA_OP1DB_NUM 8
5259 #define LNA_GAIN_NUM 7
5260 #define TIA_GAIN_NUM 2
5261 struct rtw89_dig_info {
5262 struct rtw89_agc_gaincode_set cur_gaincode;
5263 bool force_gaincode_idx_en;
5264 struct rtw89_agc_gaincode_set force_gaincode;
5265 u8 igi_rssi_th[IGI_RSSI_TH_NUM];
5266 u16 fa_th[FA_TH_NUM];
5267 u8 igi_rssi;
5268 u8 igi_fa_rssi;
5269 u8 fa_rssi_ofst;
5270 u8 dyn_igi_max;
5271 u8 dyn_igi_min;
5272 bool dyn_pd_th_en;
5273 u8 dyn_pd_th_max;
5274 u8 pd_low_th_ofst;
5275 u8 ib_pbk;
5276 s8 ib_pkpwr;
5277 s8 lna_gain_a[LNA_GAIN_NUM];
5278 s8 lna_gain_g[LNA_GAIN_NUM];
5279 s8 *lna_gain;
5280 s8 tia_gain_a[TIA_GAIN_NUM];
5281 s8 tia_gain_g[TIA_GAIN_NUM];
5282 s8 *tia_gain;
5283 u32 bak_dig;
5284 bool is_linked_pre;
5285 bool bypass_dig;
5286 bool pause_dig;
5287 };
5288
5289 enum rtw89_multi_cfo_mode {
5290 RTW89_PKT_BASED_AVG_MODE = 0,
5291 RTW89_ENTRY_BASED_AVG_MODE = 1,
5292 RTW89_TP_BASED_AVG_MODE = 2,
5293 };
5294
5295 enum rtw89_phy_cfo_status {
5296 RTW89_PHY_DCFO_STATE_NORMAL = 0,
5297 RTW89_PHY_DCFO_STATE_ENHANCE = 1,
5298 RTW89_PHY_DCFO_STATE_HOLD = 2,
5299 RTW89_PHY_DCFO_STATE_MAX
5300 };
5301
5302 enum rtw89_phy_cfo_ul_ofdma_acc_mode {
5303 RTW89_CFO_UL_OFDMA_ACC_DISABLE = 0,
5304 RTW89_CFO_UL_OFDMA_ACC_ENABLE = 1
5305 };
5306
5307 struct rtw89_cfo_tracking_info {
5308 u16 cfo_timer_ms;
5309 bool cfo_trig_by_timer_en;
5310 enum rtw89_phy_cfo_status phy_cfo_status;
5311 enum rtw89_phy_cfo_ul_ofdma_acc_mode cfo_ul_ofdma_acc_mode;
5312 u8 phy_cfo_trk_cnt;
5313 bool is_adjust;
5314 enum rtw89_multi_cfo_mode rtw89_multi_cfo_mode;
5315 bool apply_compensation;
5316 u8 crystal_cap;
5317 u8 crystal_cap_default;
5318 u8 def_x_cap;
5319 s8 x_cap_ofst;
5320 u32 sta_cfo_tolerance;
5321 s32 cfo_tail[CFO_TRACK_MAX_USER];
5322 u16 cfo_cnt[CFO_TRACK_MAX_USER];
5323 s32 cfo_avg_pre;
5324 s32 cfo_avg[CFO_TRACK_MAX_USER];
5325 s32 pre_cfo_avg[CFO_TRACK_MAX_USER];
5326 s32 dcfo_avg;
5327 s32 dcfo_avg_pre;
5328 u32 packet_count;
5329 u32 packet_count_pre;
5330 s32 residual_cfo_acc;
5331 u8 phy_cfotrk_state;
5332 u8 phy_cfotrk_cnt;
5333 bool divergence_lock_en;
5334 u8 x_cap_lb;
5335 u8 x_cap_ub;
5336 u8 lock_cnt;
5337 };
5338
5339 enum rtw89_tssi_mode {
5340 RTW89_TSSI_NORMAL = 0,
5341 RTW89_TSSI_SCAN = 1,
5342 };
5343
5344 enum rtw89_tssi_alimk_band {
5345 TSSI_ALIMK_2G = 0,
5346 TSSI_ALIMK_5GL,
5347 TSSI_ALIMK_5GM,
5348 TSSI_ALIMK_5GH,
5349 TSSI_ALIMK_MAX
5350 };
5351
5352 /* 2GL, 2GH, 5GL1, 5GH1, 5GM1, 5GM2, 5GH1, 5GH2 */
5353 #define TSSI_TRIM_CH_GROUP_NUM 8
5354 #define TSSI_TRIM_CH_GROUP_NUM_6G 16
5355
5356 #define TSSI_CCK_CH_GROUP_NUM 6
5357 #define TSSI_MCS_2G_CH_GROUP_NUM 5
5358 #define TSSI_MCS_5G_CH_GROUP_NUM 14
5359 #define TSSI_MCS_6G_CH_GROUP_NUM 32
5360 #define TSSI_MCS_CH_GROUP_NUM \
5361 (TSSI_MCS_2G_CH_GROUP_NUM + TSSI_MCS_5G_CH_GROUP_NUM)
5362 #define TSSI_MAX_CH_NUM 67
5363 #define TSSI_ALIMK_VALUE_NUM 8
5364
5365 struct rtw89_tssi_info {
5366 u8 thermal[RF_PATH_MAX];
5367 s8 tssi_trim[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM];
5368 s8 tssi_trim_6g[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM_6G];
5369 s8 tssi_cck[RF_PATH_MAX][TSSI_CCK_CH_GROUP_NUM];
5370 s8 tssi_mcs[RF_PATH_MAX][TSSI_MCS_CH_GROUP_NUM];
5371 s8 tssi_6g_mcs[RF_PATH_MAX][TSSI_MCS_6G_CH_GROUP_NUM];
5372 s8 extra_ofst[RF_PATH_MAX];
5373 bool tssi_tracking_check[RF_PATH_MAX];
5374 u8 default_txagc_offset[RF_PATH_MAX];
5375 u32 base_thermal[RF_PATH_MAX];
5376 bool check_backup_aligmk[RF_PATH_MAX][TSSI_MAX_CH_NUM];
5377 u32 alignment_backup_by_ch[RF_PATH_MAX][TSSI_MAX_CH_NUM][TSSI_ALIMK_VALUE_NUM];
5378 u32 alignment_value[RF_PATH_MAX][TSSI_ALIMK_MAX][TSSI_ALIMK_VALUE_NUM];
5379 bool alignment_done[RF_PATH_MAX][TSSI_ALIMK_MAX];
5380 u64 tssi_alimk_time;
5381 };
5382
5383 struct rtw89_power_trim_info {
5384 bool pg_thermal_trim;
5385 bool pg_pa_bias_trim;
5386 u8 thermal_trim[RF_PATH_MAX];
5387 u8 pa_bias_trim[RF_PATH_MAX];
5388 u8 pad_bias_trim[RF_PATH_MAX];
5389 };
5390
5391 enum rtw89_regd_func {
5392 RTW89_REGD_FUNC_TAS = 0, /* TAS (Time Average SAR) */
5393 RTW89_REGD_FUNC_DAG = 1, /* DAG (Dynamic Antenna Gain) */
5394
5395 NUM_OF_RTW89_REGD_FUNC,
5396 };
5397
5398 struct rtw89_regd {
5399 char alpha2[3];
5400 u8 txpwr_regd[RTW89_BAND_NUM];
5401 DECLARE_BITMAP(func_bitmap, NUM_OF_RTW89_REGD_FUNC);
5402 };
5403
5404 struct rtw89_regd_data {
5405 unsigned int nr;
5406 struct rtw89_regd map[] __counted_by(nr);
5407 };
5408
5409 struct rtw89_regd_ctrl {
5410 unsigned int nr;
5411 const struct rtw89_regd *map;
5412 };
5413
5414 #define RTW89_REGD_MAX_COUNTRY_NUM U8_MAX
5415 #define RTW89_5GHZ_UNII4_CHANNEL_NUM 3
5416 #define RTW89_5GHZ_UNII4_START_INDEX 25
5417
5418 struct rtw89_regulatory_info {
5419 struct rtw89_regd_ctrl ctrl;
5420 const struct rtw89_regd *regd;
5421 enum rtw89_reg_6ghz_power reg_6ghz_power;
5422 struct rtw89_reg_6ghz_tpe reg_6ghz_tpe;
5423 bool txpwr_uk_follow_etsi;
5424
5425 DECLARE_BITMAP(block_unii4, RTW89_REGD_MAX_COUNTRY_NUM);
5426 DECLARE_BITMAP(block_6ghz, RTW89_REGD_MAX_COUNTRY_NUM);
5427 DECLARE_BITMAP(block_6ghz_sp, RTW89_REGD_MAX_COUNTRY_NUM);
5428 DECLARE_BITMAP(block_6ghz_vlp, RTW89_REGD_MAX_COUNTRY_NUM);
5429 };
5430
5431 enum rtw89_ifs_clm_application {
5432 RTW89_IFS_CLM_INIT = 0,
5433 RTW89_IFS_CLM_BACKGROUND = 1,
5434 RTW89_IFS_CLM_ACS = 2,
5435 RTW89_IFS_CLM_DIG = 3,
5436 RTW89_IFS_CLM_TDMA_DIG = 4,
5437 RTW89_IFS_CLM_DBG = 5,
5438 RTW89_IFS_CLM_DBG_MANUAL = 6
5439 };
5440
5441 enum rtw89_env_racing_lv {
5442 RTW89_RAC_RELEASE = 0,
5443 RTW89_RAC_LV_1 = 1,
5444 RTW89_RAC_LV_2 = 2,
5445 RTW89_RAC_LV_3 = 3,
5446 RTW89_RAC_LV_4 = 4,
5447 RTW89_RAC_MAX_NUM = 5
5448 };
5449
5450 struct rtw89_ccx_para_info {
5451 enum rtw89_env_racing_lv rac_lv;
5452 u16 mntr_time;
5453 u8 nhm_manual_th_ofst;
5454 u8 nhm_manual_th0;
5455 enum rtw89_ifs_clm_application ifs_clm_app;
5456 u32 ifs_clm_manual_th_times;
5457 u32 ifs_clm_manual_th0;
5458 u8 fahm_manual_th_ofst;
5459 u8 fahm_manual_th0;
5460 u8 fahm_numer_opt;
5461 u8 fahm_denom_opt;
5462 };
5463
5464 enum rtw89_ccx_edcca_opt_sc_idx {
5465 RTW89_CCX_EDCCA_SEG0_P0 = 0,
5466 RTW89_CCX_EDCCA_SEG0_S1 = 1,
5467 RTW89_CCX_EDCCA_SEG0_S2 = 2,
5468 RTW89_CCX_EDCCA_SEG0_S3 = 3,
5469 RTW89_CCX_EDCCA_SEG1_P0 = 4,
5470 RTW89_CCX_EDCCA_SEG1_S1 = 5,
5471 RTW89_CCX_EDCCA_SEG1_S2 = 6,
5472 RTW89_CCX_EDCCA_SEG1_S3 = 7
5473 };
5474
5475 enum rtw89_ccx_edcca_opt_bw_idx {
5476 RTW89_CCX_EDCCA_BW20_0 = 0,
5477 RTW89_CCX_EDCCA_BW20_1 = 1,
5478 RTW89_CCX_EDCCA_BW20_2 = 2,
5479 RTW89_CCX_EDCCA_BW20_3 = 3,
5480 RTW89_CCX_EDCCA_BW20_4 = 4,
5481 RTW89_CCX_EDCCA_BW20_5 = 5,
5482 RTW89_CCX_EDCCA_BW20_6 = 6,
5483 RTW89_CCX_EDCCA_BW20_7 = 7
5484 };
5485
5486 #define RTW89_NHM_TH_NUM 11
5487 #define RTW89_FAHM_TH_NUM 11
5488 #define RTW89_NHM_RPT_NUM 12
5489 #define RTW89_FAHM_RPT_NUM 12
5490 #define RTW89_IFS_CLM_NUM 4
5491 struct rtw89_env_monitor_info {
5492 u8 ccx_watchdog_result;
5493 bool ccx_ongoing;
5494 u8 ccx_rac_lv;
5495 bool ccx_manual_ctrl;
5496 u16 ifs_clm_mntr_time;
5497 enum rtw89_ifs_clm_application ifs_clm_app;
5498 u16 ccx_period;
5499 u8 ccx_unit_idx;
5500 u16 ifs_clm_th_l[RTW89_IFS_CLM_NUM];
5501 u16 ifs_clm_th_h[RTW89_IFS_CLM_NUM];
5502 u16 ifs_clm_tx;
5503 u16 ifs_clm_edcca_excl_cca;
5504 u16 ifs_clm_ofdmfa;
5505 u16 ifs_clm_ofdmcca_excl_fa;
5506 u16 ifs_clm_cckfa;
5507 u16 ifs_clm_cckcca_excl_fa;
5508 u16 ifs_clm_total_ifs;
5509 u8 ifs_clm_his[RTW89_IFS_CLM_NUM];
5510 u16 ifs_clm_avg[RTW89_IFS_CLM_NUM];
5511 u16 ifs_clm_cca[RTW89_IFS_CLM_NUM];
5512 u8 ifs_clm_tx_ratio;
5513 u8 ifs_clm_edcca_excl_cca_ratio;
5514 u8 ifs_clm_cck_fa_ratio;
5515 u8 ifs_clm_ofdm_fa_ratio;
5516 u8 ifs_clm_cck_cca_excl_fa_ratio;
5517 u8 ifs_clm_ofdm_cca_excl_fa_ratio;
5518 u16 ifs_clm_cck_fa_permil;
5519 u16 ifs_clm_ofdm_fa_permil;
5520 u32 ifs_clm_ifs_avg[RTW89_IFS_CLM_NUM];
5521 u32 ifs_clm_cca_avg[RTW89_IFS_CLM_NUM];
5522 };
5523
5524 enum rtw89_ser_rcvy_step {
5525 RTW89_SER_DRV_STOP_TX,
5526 RTW89_SER_DRV_STOP_RX,
5527 RTW89_SER_DRV_STOP_RUN,
5528 RTW89_SER_HAL_STOP_DMA,
5529 RTW89_SER_SUPPRESS_LOG,
5530 RTW89_NUM_OF_SER_FLAGS
5531 };
5532
5533 struct rtw89_ser {
5534 u8 state;
5535 u8 alarm_event;
5536 bool prehandle_l1;
5537
5538 struct work_struct ser_hdl_work;
5539 struct delayed_work ser_alarm_work;
5540 const struct state_ent *st_tbl;
5541 const struct event_ent *ev_tbl;
5542 struct list_head msg_q;
5543 spinlock_t msg_q_lock; /* lock when read/write ser msg */
5544 DECLARE_BITMAP(flags, RTW89_NUM_OF_SER_FLAGS);
5545 };
5546
5547 enum rtw89_mac_ax_ps_mode {
5548 RTW89_MAC_AX_PS_MODE_ACTIVE = 0,
5549 RTW89_MAC_AX_PS_MODE_LEGACY = 1,
5550 RTW89_MAC_AX_PS_MODE_WMMPS = 2,
5551 RTW89_MAC_AX_PS_MODE_MAX = 3,
5552 };
5553
5554 enum rtw89_last_rpwm_mode {
5555 RTW89_LAST_RPWM_PS = 0x0,
5556 RTW89_LAST_RPWM_ACTIVE = 0x6,
5557 };
5558
5559 struct rtw89_lps_parm {
5560 u8 macid;
5561 u8 psmode; /* enum rtw89_mac_ax_ps_mode */
5562 u8 lastrpwm; /* enum rtw89_last_rpwm_mode */
5563 };
5564
5565 struct rtw89_ppdu_sts_info {
5566 struct sk_buff_head rx_queue[RTW89_PHY_NUM];
5567 u8 curr_rx_ppdu_cnt[RTW89_PHY_NUM];
5568 };
5569
5570 struct rtw89_early_h2c {
5571 struct list_head list;
5572 u8 *h2c;
5573 u16 h2c_len;
5574 };
5575
5576 struct rtw89_hw_scan_extra_op {
5577 bool set;
5578 u8 macid;
5579 u8 port;
5580 struct rtw89_chan chan;
5581 struct rtw89_vif_link *rtwvif_link;
5582 };
5583
5584 struct rtw89_hw_scan_info {
5585 struct rtw89_vif_link *scanning_vif;
5586 struct list_head pkt_list[NUM_NL80211_BANDS];
5587 struct list_head chan_list;
5588 struct rtw89_chan op_chan;
5589 struct rtw89_hw_scan_extra_op extra_op;
5590 bool connected;
5591 bool abort;
5592 u16 delay; /* in unit of ms */
5593 u8 seq: 2;
5594 };
5595
5596 enum rtw89_phy_bb_gain_band {
5597 RTW89_BB_GAIN_BAND_2G = 0,
5598 RTW89_BB_GAIN_BAND_5G_L = 1,
5599 RTW89_BB_GAIN_BAND_5G_M = 2,
5600 RTW89_BB_GAIN_BAND_5G_H = 3,
5601 RTW89_BB_GAIN_BAND_6G_L = 4,
5602 RTW89_BB_GAIN_BAND_6G_M = 5,
5603 RTW89_BB_GAIN_BAND_6G_H = 6,
5604 RTW89_BB_GAIN_BAND_6G_UH = 7,
5605
5606 RTW89_BB_GAIN_BAND_NR,
5607 };
5608
5609 enum rtw89_phy_gain_band_be {
5610 RTW89_BB_GAIN_BAND_2G_BE = 0,
5611 RTW89_BB_GAIN_BAND_5G_L_BE = 1,
5612 RTW89_BB_GAIN_BAND_5G_M_BE = 2,
5613 RTW89_BB_GAIN_BAND_5G_H_BE = 3,
5614 RTW89_BB_GAIN_BAND_6G_L0_BE = 4,
5615 RTW89_BB_GAIN_BAND_6G_L1_BE = 5,
5616 RTW89_BB_GAIN_BAND_6G_M0_BE = 6,
5617 RTW89_BB_GAIN_BAND_6G_M1_BE = 7,
5618 RTW89_BB_GAIN_BAND_6G_H0_BE = 8,
5619 RTW89_BB_GAIN_BAND_6G_H1_BE = 9,
5620 RTW89_BB_GAIN_BAND_6G_UH0_BE = 10,
5621 RTW89_BB_GAIN_BAND_6G_UH1_BE = 11,
5622
5623 RTW89_BB_GAIN_BAND_NR_BE,
5624 };
5625
5626 enum rtw89_phy_bb_bw_be {
5627 RTW89_BB_BW_20_40 = 0,
5628 RTW89_BB_BW_80_160_320 = 1,
5629
5630 RTW89_BB_BW_NR_BE,
5631 };
5632
5633 enum rtw89_bw20_sc {
5634 RTW89_BW20_SC_20M = 1,
5635 RTW89_BW20_SC_40M = 2,
5636 RTW89_BW20_SC_80M = 4,
5637 RTW89_BW20_SC_160M = 8,
5638 RTW89_BW20_SC_320M = 16,
5639 };
5640
5641 enum rtw89_cmac_table_bw {
5642 RTW89_CMAC_BW_20M = 0,
5643 RTW89_CMAC_BW_40M = 1,
5644 RTW89_CMAC_BW_80M = 2,
5645 RTW89_CMAC_BW_160M = 3,
5646 RTW89_CMAC_BW_320M = 4,
5647
5648 RTW89_CMAC_BW_NR,
5649 };
5650
5651 enum rtw89_phy_bb_rxsc_num {
5652 RTW89_BB_RXSC_NUM_40 = 9, /* SC: 0, 1~8 */
5653 RTW89_BB_RXSC_NUM_80 = 13, /* SC: 0, 1~8, 9~12 */
5654 RTW89_BB_RXSC_NUM_160 = 15, /* SC: 0, 1~8, 9~12, 13~14 */
5655 };
5656
5657 struct rtw89_phy_bb_gain_info {
5658 s8 lna_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM];
5659 s8 tia_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][TIA_GAIN_NUM];
5660 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM];
5661 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM];
5662 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]
5663 [LNA_GAIN_NUM + 1]; /* TIA0_LNA0~6 + TIA1_LNA6 */
5664 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX];
5665 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]
5666 [RTW89_BB_RXSC_NUM_40];
5667 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]
5668 [RTW89_BB_RXSC_NUM_80];
5669 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]
5670 [RTW89_BB_RXSC_NUM_160];
5671 };
5672
5673 struct rtw89_phy_bb_gain_info_be {
5674 s8 lna_gain[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE][RF_PATH_MAX]
5675 [LNA_GAIN_NUM];
5676 s8 tia_gain[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE][RF_PATH_MAX]
5677 [TIA_GAIN_NUM];
5678 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE]
5679 [RF_PATH_MAX][LNA_GAIN_NUM];
5680 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE]
5681 [RF_PATH_MAX][LNA_GAIN_NUM];
5682 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE]
5683 [RF_PATH_MAX][LNA_GAIN_NUM + 1];
5684 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX]
5685 [RTW89_BW20_SC_20M];
5686 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX]
5687 [RTW89_BW20_SC_40M];
5688 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX]
5689 [RTW89_BW20_SC_80M];
5690 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX]
5691 [RTW89_BW20_SC_160M];
5692 };
5693
5694 struct rtw89_phy_efuse_gain {
5695 bool offset_valid;
5696 bool comp_valid;
5697 s8 offset[RF_PATH_MAX][RTW89_GAIN_OFFSET_NR]; /* S(8, 0) */
5698 s8 offset_base[RTW89_PHY_NUM]; /* S(8, 4) */
5699 s8 rssi_base[RTW89_PHY_NUM]; /* S(8, 4) */
5700 s8 comp[RF_PATH_MAX][RTW89_SUBBAND_NR]; /* S(8, 0) */
5701 };
5702
5703 #define RTW89_MAX_PATTERN_NUM 18
5704 #define RTW89_MAX_PATTERN_MASK_SIZE 4
5705 #define RTW89_MAX_PATTERN_SIZE 128
5706
5707 struct rtw89_wow_cam_info {
5708 bool r_w;
5709 u8 idx;
5710 u32 mask[RTW89_MAX_PATTERN_MASK_SIZE];
5711 u16 crc;
5712 bool negative_pattern_match;
5713 bool skip_mac_hdr;
5714 bool uc;
5715 bool mc;
5716 bool bc;
5717 bool valid;
5718 };
5719
5720 struct rtw89_wow_key_info {
5721 u8 ptk_tx_iv[8];
5722 u8 valid_check;
5723 u8 symbol_check_en;
5724 u8 gtk_keyidx;
5725 u8 rsvd[5];
5726 u8 ptk_rx_iv[8];
5727 u8 gtk_rx_iv[4][8];
5728 } __packed;
5729
5730 struct rtw89_wow_gtk_info {
5731 u8 kck[32];
5732 u8 kek[32];
5733 u8 tk1[16];
5734 u8 txmickey[8];
5735 u8 rxmickey[8];
5736 __le32 igtk_keyid;
5737 __le64 ipn;
5738 u8 igtk[2][32];
5739 u8 psk[32];
5740 } __packed;
5741
5742 struct rtw89_wow_aoac_report {
5743 u8 rpt_ver;
5744 u8 sec_type;
5745 u8 key_idx;
5746 u8 pattern_idx;
5747 u8 rekey_ok;
5748 u8 ptk_tx_iv[8];
5749 u8 eapol_key_replay_count[8];
5750 u8 gtk[32];
5751 u8 ptk_rx_iv[8];
5752 u8 gtk_rx_iv[4][8];
5753 u64 igtk_key_id;
5754 u64 igtk_ipn;
5755 u8 igtk[32];
5756 u8 csa_pri_ch;
5757 u8 csa_bw;
5758 u8 csa_ch_offset;
5759 u8 csa_chsw_failed;
5760 u8 csa_ch_band;
5761 };
5762
5763 struct rtw89_wow_param {
5764 struct rtw89_vif_link *rtwvif_link;
5765 DECLARE_BITMAP(flags, RTW89_WOW_FLAG_NUM);
5766 struct rtw89_wow_cam_info patterns[RTW89_MAX_PATTERN_NUM];
5767 struct rtw89_wow_key_info key_info;
5768 struct rtw89_wow_gtk_info gtk_info;
5769 struct rtw89_wow_aoac_report aoac_rpt;
5770 u8 pattern_cnt;
5771 u8 ptk_alg;
5772 u8 gtk_alg;
5773 u8 ptk_keyidx;
5774 u8 akm;
5775
5776 /* see RTW89_WOW_WAIT_COND series for wait condition */
5777 struct rtw89_wait_info wait;
5778
5779 bool pno_inited;
5780 struct list_head pno_pkt_list;
5781 struct cfg80211_sched_scan_request *nd_config;
5782 };
5783
5784 struct rtw89_mcc_limit {
5785 bool enable;
5786 u16 max_tob; /* TU; max time offset behind */
5787 u16 max_toa; /* TU; max time offset ahead */
5788 u16 max_dur; /* TU */
5789 };
5790
5791 struct rtw89_mcc_policy {
5792 u8 c2h_rpt;
5793 u8 tx_null_early;
5794 u8 dis_tx_null;
5795 u8 in_curr_ch;
5796 u8 dis_sw_retry;
5797 u8 sw_retry_count;
5798 };
5799
5800 struct rtw89_mcc_role {
5801 struct rtw89_vif_link *rtwvif_link;
5802 struct rtw89_mcc_policy policy;
5803 struct rtw89_mcc_limit limit;
5804
5805 const struct rtw89_mcc_courtesy_cfg *crtz;
5806
5807 /* only valid when running with FW MRC mechanism */
5808 u8 slot_idx;
5809
5810 /* byte-array in LE order for FW */
5811 u8 macid_bitmap[BITS_TO_BYTES(RTW89_MAX_MAC_ID_NUM)];
5812 u8 probe_count;
5813
5814 u16 duration; /* TU */
5815 u16 beacon_interval; /* TU */
5816 bool is_2ghz;
5817 bool is_go;
5818 bool is_gc;
5819 bool ignore_bcn;
5820 };
5821
5822 struct rtw89_mcc_bt_role {
5823 u16 duration; /* TU */
5824 };
5825
5826 struct rtw89_mcc_courtesy_cfg {
5827 u8 slot_num;
5828 u8 macid_tgt;
5829 };
5830
5831 struct rtw89_mcc_courtesy {
5832 struct rtw89_mcc_courtesy_cfg ref;
5833 struct rtw89_mcc_courtesy_cfg aux;
5834 };
5835
5836 enum rtw89_mcc_plan {
5837 RTW89_MCC_PLAN_TAIL_BT,
5838 RTW89_MCC_PLAN_MID_BT,
5839 RTW89_MCC_PLAN_NO_BT,
5840
5841 NUM_OF_RTW89_MCC_PLAN,
5842 };
5843
5844 struct rtw89_mcc_pattern {
5845 s16 tob_ref; /* TU; time offset behind of reference role */
5846 s16 toa_ref; /* TU; time offset ahead of reference role */
5847 s16 tob_aux; /* TU; time offset behind of auxiliary role */
5848 s16 toa_aux; /* TU; time offset ahead of auxiliary role */
5849
5850 enum rtw89_mcc_plan plan;
5851 struct rtw89_mcc_courtesy courtesy;
5852 };
5853
5854 struct rtw89_mcc_sync {
5855 bool enable;
5856 u16 offset; /* TU */
5857 u8 macid_src;
5858 u8 band_src;
5859 u8 port_src;
5860 u8 macid_tgt;
5861 u8 band_tgt;
5862 u8 port_tgt;
5863 };
5864
5865 struct rtw89_mcc_config {
5866 struct rtw89_mcc_pattern pattern;
5867 struct rtw89_mcc_sync sync;
5868 u64 start_tsf;
5869 u64 start_tsf_in_aux_domain;
5870 u64 prepare_delay;
5871 u16 mcc_interval; /* TU */
5872 u16 beacon_offset; /* TU */
5873 };
5874
5875 enum rtw89_mcc_mode {
5876 RTW89_MCC_MODE_GO_STA,
5877 RTW89_MCC_MODE_GC_STA,
5878 };
5879
5880 struct rtw89_mcc_info {
5881 struct rtw89_wait_info wait;
5882
5883 u8 group;
5884 enum rtw89_mcc_mode mode;
5885 struct rtw89_mcc_role role_ref; /* reference role */
5886 struct rtw89_mcc_role role_aux; /* auxiliary role */
5887 struct rtw89_mcc_bt_role bt_role;
5888 struct rtw89_mcc_config config;
5889 };
5890
5891 enum rtw89_mlo_mode {
5892 RTW89_MLO_MODE_MLSR = 0,
5893
5894 NUM_OF_RTW89_MLO_MODE,
5895 };
5896
5897 struct rtw89_mlo_info {
5898 struct rtw89_wait_info wait;
5899 };
5900
5901 struct rtw89_dev {
5902 struct ieee80211_hw *hw;
5903 struct device *dev;
5904 const struct ieee80211_ops *ops;
5905
5906 bool dbcc_en;
5907 bool support_mlo;
5908 enum rtw89_mlo_dbcc_mode mlo_dbcc_mode;
5909 struct rtw89_hw_scan_info scan_info;
5910 const struct rtw89_chip_info *chip;
5911 const struct rtw89_chip_variant *variant;
5912 const struct rtw89_pci_info *pci_info;
5913 const struct rtw89_rfe_parms *rfe_parms;
5914 struct rtw89_hal hal;
5915 struct rtw89_mcc_info mcc;
5916 struct rtw89_mlo_info mlo;
5917 struct rtw89_mac_info mac;
5918 struct rtw89_fw_info fw;
5919 struct rtw89_hci_info hci;
5920 struct rtw89_efuse efuse;
5921 struct rtw89_traffic_stats stats;
5922 struct rtw89_rfe_data *rfe_data;
5923 enum rtw89_custid custid;
5924
5925 struct rtw89_sta_link __rcu *assoc_link_on_macid[RTW89_MAX_MAC_ID_NUM];
5926 refcount_t refcount_ap_info;
5927
5928 struct list_head rtwvifs_list;
5929 /* used to protect rf read write */
5930 struct mutex rf_mutex;
5931 struct workqueue_struct *txq_wq;
5932 struct work_struct txq_work;
5933 struct delayed_work txq_reinvoke_work;
5934 /* used to protect ba_list and forbid_ba_list */
5935 spinlock_t ba_lock;
5936 /* txqs to setup ba session */
5937 struct list_head ba_list;
5938 /* txqs to forbid ba session */
5939 struct list_head forbid_ba_list;
5940 struct work_struct ba_work;
5941 /* used to protect rpwm */
5942 spinlock_t rpwm_lock;
5943
5944 struct rtw89_cam_info cam_info;
5945
5946 struct sk_buff_head c2h_queue;
5947 struct wiphy_work c2h_work;
5948 struct wiphy_work ips_work;
5949 struct wiphy_work cancel_6ghz_probe_work;
5950 struct work_struct load_firmware_work;
5951
5952 struct list_head early_h2c_list;
5953
5954 struct rtw89_ser ser;
5955
5956 DECLARE_BITMAP(hw_port, RTW89_PORT_NUM);
5957 DECLARE_BITMAP(mac_id_map, RTW89_MAX_MAC_ID_NUM);
5958 DECLARE_BITMAP(flags, NUM_OF_RTW89_FLAGS);
5959 DECLARE_BITMAP(pkt_offload, RTW89_MAX_PKT_OFLD_NUM);
5960 DECLARE_BITMAP(quirks, NUM_OF_RTW89_QUIRKS);
5961
5962 struct rtw89_phy_stat phystat;
5963 struct rtw89_rfk_wait_info rfk_wait;
5964 struct rtw89_dack_info dack;
5965 struct rtw89_iqk_info iqk;
5966 struct rtw89_dpk_info dpk;
5967 struct rtw89_rfk_mcc_info rfk_mcc;
5968 struct rtw89_lck_info lck;
5969 struct rtw89_rx_dck_info rx_dck;
5970 bool is_tssi_mode[RF_PATH_MAX];
5971 bool is_bt_iqk_timeout;
5972
5973 struct rtw89_fem_info fem;
5974 struct rtw89_txpwr_byrate byr[RTW89_BAND_NUM][RTW89_BYR_BW_NUM];
5975 struct rtw89_tssi_info tssi;
5976 struct rtw89_power_trim_info pwr_trim;
5977
5978 struct rtw89_cfo_tracking_info cfo_tracking;
5979 union {
5980 struct rtw89_phy_bb_gain_info ax;
5981 struct rtw89_phy_bb_gain_info_be be;
5982 } bb_gain;
5983 struct rtw89_phy_efuse_gain efuse_gain;
5984 struct rtw89_phy_ul_tb_info ul_tb_info;
5985 struct rtw89_antdiv_info antdiv;
5986
5987 struct rtw89_bb_ctx {
5988 enum rtw89_phy_idx phy_idx;
5989 struct rtw89_env_monitor_info env_monitor;
5990 struct rtw89_dig_info dig;
5991 struct rtw89_phy_ch_info ch_info;
5992 struct rtw89_edcca_bak edcca_bak;
5993 } bbs[RTW89_PHY_NUM];
5994
5995 struct wiphy_delayed_work track_work;
5996 struct wiphy_delayed_work track_ps_work;
5997 struct wiphy_delayed_work chanctx_work;
5998 struct wiphy_delayed_work coex_act1_work;
5999 struct wiphy_delayed_work coex_bt_devinfo_work;
6000 struct wiphy_delayed_work coex_rfk_chk_work;
6001 struct wiphy_delayed_work cfo_track_work;
6002 struct wiphy_delayed_work mcc_prepare_done_work;
6003 struct delayed_work forbid_ba_work;
6004 struct wiphy_delayed_work antdiv_work;
6005 struct rtw89_ppdu_sts_info ppdu_sts;
6006 u8 total_sta_assoc;
6007 bool scanning;
6008
6009 struct rtw89_regulatory_info regulatory;
6010 struct rtw89_sar_info sar;
6011 struct rtw89_tas_info tas;
6012 struct rtw89_ant_gain_info ant_gain;
6013
6014 struct rtw89_btc btc;
6015 enum rtw89_ps_mode ps_mode;
6016 bool lps_enabled;
6017
6018 struct rtw89_wow_param wow;
6019
6020 /* napi structure */
6021 struct net_device *netdev;
6022 struct napi_struct napi;
6023 int napi_budget_countdown;
6024
6025 struct rtw89_debugfs *debugfs;
6026
6027 /* HCI related data, keep last */
6028 u8 priv[] __aligned(sizeof(void *));
6029 };
6030
6031 struct rtw89_link_conf_container {
6032 struct ieee80211_bss_conf *link_conf[IEEE80211_MLD_MAX_NUM_LINKS];
6033 };
6034
6035 #define RTW89_VIF_IDLE_LINK_ID 0
6036
6037 struct rtw89_vif {
6038 struct rtw89_dev *rtwdev;
6039 struct list_head list;
6040 struct list_head mgnt_entry;
6041 struct rtw89_link_conf_container __rcu *snap_link_confs;
6042
6043 u8 mac_addr[ETH_ALEN];
6044 __be32 ip_addr;
6045
6046 struct rtw89_traffic_stats stats;
6047 struct rtw89_traffic_stats stats_ps;
6048 u32 tdls_peer;
6049
6050 struct ieee80211_scan_ies *scan_ies;
6051 struct cfg80211_scan_request *scan_req;
6052
6053 struct rtw89_roc roc;
6054 bool offchan;
6055
6056 enum rtw89_mlo_mode mlo_mode;
6057
6058 struct list_head dlink_pool;
6059 u8 links_inst_valid_num;
6060 DECLARE_BITMAP(links_inst_map, __RTW89_MLD_MAX_LINK_NUM);
6061 struct rtw89_vif_link *links[IEEE80211_MLD_MAX_NUM_LINKS];
6062 struct rtw89_vif_link links_inst[] __counted_by(links_inst_valid_num);
6063 };
6064
rtw89_vif_assign_link_is_valid(struct rtw89_vif_link ** rtwvif_link,const struct rtw89_vif * rtwvif,unsigned int link_id)6065 static inline bool rtw89_vif_assign_link_is_valid(struct rtw89_vif_link **rtwvif_link,
6066 const struct rtw89_vif *rtwvif,
6067 unsigned int link_id)
6068 {
6069 *rtwvif_link = rtwvif->links[link_id];
6070 return !!*rtwvif_link;
6071 }
6072
6073 #define rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) \
6074 for (link_id = 0; link_id < IEEE80211_MLD_MAX_NUM_LINKS; link_id++) \
6075 if (rtw89_vif_assign_link_is_valid(&(rtwvif_link), rtwvif, link_id))
6076
6077 enum rtw89_sta_flags {
6078 RTW89_REMOTE_STA_IN_PS,
6079
6080 NUM_OF_RTW89_STA_FLAGS,
6081 };
6082
6083 struct rtw89_sta {
6084 struct rtw89_dev *rtwdev;
6085 struct rtw89_vif *rtwvif;
6086
6087 DECLARE_BITMAP(flags, NUM_OF_RTW89_STA_FLAGS);
6088
6089 bool disassoc;
6090
6091 struct sk_buff_head roc_queue;
6092
6093 struct rtw89_ampdu_params ampdu_params[IEEE80211_NUM_TIDS];
6094 DECLARE_BITMAP(ampdu_map, IEEE80211_NUM_TIDS);
6095
6096 DECLARE_BITMAP(pairwise_sec_cam_map, RTW89_MAX_SEC_CAM_NUM);
6097
6098 struct list_head dlink_pool;
6099 u8 links_inst_valid_num;
6100 DECLARE_BITMAP(links_inst_map, __RTW89_MLD_MAX_LINK_NUM);
6101 struct rtw89_sta_link *links[IEEE80211_MLD_MAX_NUM_LINKS];
6102 struct rtw89_sta_link links_inst[] __counted_by(links_inst_valid_num);
6103 };
6104
rtw89_sta_assign_link_is_valid(struct rtw89_sta_link ** rtwsta_link,const struct rtw89_sta * rtwsta,unsigned int link_id)6105 static inline bool rtw89_sta_assign_link_is_valid(struct rtw89_sta_link **rtwsta_link,
6106 const struct rtw89_sta *rtwsta,
6107 unsigned int link_id)
6108 {
6109 *rtwsta_link = rtwsta->links[link_id];
6110 return !!*rtwsta_link;
6111 }
6112
6113 #define rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) \
6114 for (link_id = 0; link_id < IEEE80211_MLD_MAX_NUM_LINKS; link_id++) \
6115 if (rtw89_sta_assign_link_is_valid(&(rtwsta_link), rtwsta, link_id))
6116
rtw89_vif_get_main_macid(struct rtw89_vif * rtwvif)6117 static inline u8 rtw89_vif_get_main_macid(struct rtw89_vif *rtwvif)
6118 {
6119 /* const after init, so no need to check if active first */
6120 return rtwvif->links_inst[0].mac_id;
6121 }
6122
rtw89_vif_get_main_port(struct rtw89_vif * rtwvif)6123 static inline u8 rtw89_vif_get_main_port(struct rtw89_vif *rtwvif)
6124 {
6125 /* const after init, so no need to check if active first */
6126 return rtwvif->links_inst[0].port;
6127 }
6128
6129 static inline struct rtw89_vif_link *
rtw89_vif_get_link_inst(struct rtw89_vif * rtwvif,u8 index)6130 rtw89_vif_get_link_inst(struct rtw89_vif *rtwvif, u8 index)
6131 {
6132 if (index >= rtwvif->links_inst_valid_num ||
6133 !test_bit(index, rtwvif->links_inst_map))
6134 return NULL;
6135 return &rtwvif->links_inst[index];
6136 }
6137
6138 static inline
rtw89_vif_link_inst_get_index(struct rtw89_vif_link * rtwvif_link)6139 u8 rtw89_vif_link_inst_get_index(struct rtw89_vif_link *rtwvif_link)
6140 {
6141 struct rtw89_vif *rtwvif = rtwvif_link->rtwvif;
6142
6143 return rtwvif_link - rtwvif->links_inst;
6144 }
6145
rtw89_sta_get_main_macid(struct rtw89_sta * rtwsta)6146 static inline u8 rtw89_sta_get_main_macid(struct rtw89_sta *rtwsta)
6147 {
6148 /* const after init, so no need to check if active first */
6149 return rtwsta->links_inst[0].mac_id;
6150 }
6151
6152 static inline struct rtw89_sta_link *
rtw89_sta_get_link_inst(struct rtw89_sta * rtwsta,u8 index)6153 rtw89_sta_get_link_inst(struct rtw89_sta *rtwsta, u8 index)
6154 {
6155 if (index >= rtwsta->links_inst_valid_num ||
6156 !test_bit(index, rtwsta->links_inst_map))
6157 return NULL;
6158 return &rtwsta->links_inst[index];
6159 }
6160
6161 static inline
rtw89_sta_link_inst_get_index(struct rtw89_sta_link * rtwsta_link)6162 u8 rtw89_sta_link_inst_get_index(struct rtw89_sta_link *rtwsta_link)
6163 {
6164 struct rtw89_sta *rtwsta = rtwsta_link->rtwsta;
6165
6166 return rtwsta_link - rtwsta->links_inst;
6167 }
6168
rtw89_assoc_link_set(struct rtw89_sta_link * rtwsta_link)6169 static inline void rtw89_assoc_link_set(struct rtw89_sta_link *rtwsta_link)
6170 {
6171 struct rtw89_sta *rtwsta = rtwsta_link->rtwsta;
6172 struct rtw89_dev *rtwdev = rtwsta->rtwdev;
6173
6174 rcu_assign_pointer(rtwdev->assoc_link_on_macid[rtwsta_link->mac_id],
6175 rtwsta_link);
6176 }
6177
rtw89_assoc_link_clr(struct rtw89_sta_link * rtwsta_link)6178 static inline void rtw89_assoc_link_clr(struct rtw89_sta_link *rtwsta_link)
6179 {
6180 struct rtw89_sta *rtwsta = rtwsta_link->rtwsta;
6181 struct rtw89_dev *rtwdev = rtwsta->rtwdev;
6182
6183 rcu_assign_pointer(rtwdev->assoc_link_on_macid[rtwsta_link->mac_id],
6184 NULL);
6185 synchronize_rcu();
6186 }
6187
6188 static inline struct rtw89_sta_link *
rtw89_assoc_link_rcu_dereference(struct rtw89_dev * rtwdev,u8 macid)6189 rtw89_assoc_link_rcu_dereference(struct rtw89_dev *rtwdev, u8 macid)
6190 {
6191 return rcu_dereference(rtwdev->assoc_link_on_macid[macid]);
6192 }
6193
6194 #define rtw89_get_designated_link(links_holder) \
6195 ({ \
6196 typeof(links_holder) p = links_holder; \
6197 list_first_entry_or_null(&p->dlink_pool, typeof(*p->links_inst), dlink_schd); \
6198 })
6199
rtw89_hci_tx_write(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)6200 static inline int rtw89_hci_tx_write(struct rtw89_dev *rtwdev,
6201 struct rtw89_core_tx_request *tx_req)
6202 {
6203 return rtwdev->hci.ops->tx_write(rtwdev, tx_req);
6204 }
6205
rtw89_hci_reset(struct rtw89_dev * rtwdev)6206 static inline void rtw89_hci_reset(struct rtw89_dev *rtwdev)
6207 {
6208 rtwdev->hci.ops->reset(rtwdev);
6209 }
6210
rtw89_hci_start(struct rtw89_dev * rtwdev)6211 static inline int rtw89_hci_start(struct rtw89_dev *rtwdev)
6212 {
6213 return rtwdev->hci.ops->start(rtwdev);
6214 }
6215
rtw89_hci_stop(struct rtw89_dev * rtwdev)6216 static inline void rtw89_hci_stop(struct rtw89_dev *rtwdev)
6217 {
6218 rtwdev->hci.ops->stop(rtwdev);
6219 }
6220
rtw89_hci_deinit(struct rtw89_dev * rtwdev)6221 static inline int rtw89_hci_deinit(struct rtw89_dev *rtwdev)
6222 {
6223 return rtwdev->hci.ops->deinit(rtwdev);
6224 }
6225
rtw89_hci_pause(struct rtw89_dev * rtwdev,bool pause)6226 static inline void rtw89_hci_pause(struct rtw89_dev *rtwdev, bool pause)
6227 {
6228 rtwdev->hci.ops->pause(rtwdev, pause);
6229 }
6230
rtw89_hci_switch_mode(struct rtw89_dev * rtwdev,bool low_power)6231 static inline void rtw89_hci_switch_mode(struct rtw89_dev *rtwdev, bool low_power)
6232 {
6233 rtwdev->hci.ops->switch_mode(rtwdev, low_power);
6234 }
6235
rtw89_hci_recalc_int_mit(struct rtw89_dev * rtwdev)6236 static inline void rtw89_hci_recalc_int_mit(struct rtw89_dev *rtwdev)
6237 {
6238 rtwdev->hci.ops->recalc_int_mit(rtwdev);
6239 }
6240
rtw89_hci_check_and_reclaim_tx_resource(struct rtw89_dev * rtwdev,u8 txch)6241 static inline u32 rtw89_hci_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 txch)
6242 {
6243 return rtwdev->hci.ops->check_and_reclaim_tx_resource(rtwdev, txch);
6244 }
6245
rtw89_hci_tx_kick_off(struct rtw89_dev * rtwdev,u8 txch)6246 static inline void rtw89_hci_tx_kick_off(struct rtw89_dev *rtwdev, u8 txch)
6247 {
6248 return rtwdev->hci.ops->tx_kick_off(rtwdev, txch);
6249 }
6250
rtw89_hci_mac_pre_deinit(struct rtw89_dev * rtwdev)6251 static inline int rtw89_hci_mac_pre_deinit(struct rtw89_dev *rtwdev)
6252 {
6253 return rtwdev->hci.ops->mac_pre_deinit(rtwdev);
6254 }
6255
rtw89_hci_flush_queues(struct rtw89_dev * rtwdev,u32 queues,bool drop)6256 static inline void rtw89_hci_flush_queues(struct rtw89_dev *rtwdev, u32 queues,
6257 bool drop)
6258 {
6259 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags))
6260 return;
6261
6262 if (rtwdev->hci.ops->flush_queues)
6263 return rtwdev->hci.ops->flush_queues(rtwdev, queues, drop);
6264 }
6265
rtw89_hci_recovery_start(struct rtw89_dev * rtwdev)6266 static inline void rtw89_hci_recovery_start(struct rtw89_dev *rtwdev)
6267 {
6268 if (rtwdev->hci.ops->recovery_start)
6269 rtwdev->hci.ops->recovery_start(rtwdev);
6270 }
6271
rtw89_hci_recovery_complete(struct rtw89_dev * rtwdev)6272 static inline void rtw89_hci_recovery_complete(struct rtw89_dev *rtwdev)
6273 {
6274 if (rtwdev->hci.ops->recovery_complete)
6275 rtwdev->hci.ops->recovery_complete(rtwdev);
6276 }
6277
rtw89_hci_enable_intr(struct rtw89_dev * rtwdev)6278 static inline void rtw89_hci_enable_intr(struct rtw89_dev *rtwdev)
6279 {
6280 if (rtwdev->hci.ops->enable_intr)
6281 rtwdev->hci.ops->enable_intr(rtwdev);
6282 }
6283
rtw89_hci_disable_intr(struct rtw89_dev * rtwdev)6284 static inline void rtw89_hci_disable_intr(struct rtw89_dev *rtwdev)
6285 {
6286 if (rtwdev->hci.ops->disable_intr)
6287 rtwdev->hci.ops->disable_intr(rtwdev);
6288 }
6289
rtw89_hci_ctrl_txdma_ch(struct rtw89_dev * rtwdev,bool enable)6290 static inline void rtw89_hci_ctrl_txdma_ch(struct rtw89_dev *rtwdev, bool enable)
6291 {
6292 if (rtwdev->hci.ops->ctrl_txdma_ch)
6293 rtwdev->hci.ops->ctrl_txdma_ch(rtwdev, enable);
6294 }
6295
rtw89_hci_ctrl_txdma_fw_ch(struct rtw89_dev * rtwdev,bool enable)6296 static inline void rtw89_hci_ctrl_txdma_fw_ch(struct rtw89_dev *rtwdev, bool enable)
6297 {
6298 if (rtwdev->hci.ops->ctrl_txdma_fw_ch)
6299 rtwdev->hci.ops->ctrl_txdma_fw_ch(rtwdev, enable);
6300 }
6301
rtw89_hci_ctrl_trxhci(struct rtw89_dev * rtwdev,bool enable)6302 static inline void rtw89_hci_ctrl_trxhci(struct rtw89_dev *rtwdev, bool enable)
6303 {
6304 if (rtwdev->hci.ops->ctrl_trxhci)
6305 rtwdev->hci.ops->ctrl_trxhci(rtwdev, enable);
6306 }
6307
rtw89_hci_poll_txdma_ch_idle(struct rtw89_dev * rtwdev)6308 static inline int rtw89_hci_poll_txdma_ch_idle(struct rtw89_dev *rtwdev)
6309 {
6310 int ret = 0;
6311
6312 if (rtwdev->hci.ops->poll_txdma_ch_idle)
6313 ret = rtwdev->hci.ops->poll_txdma_ch_idle(rtwdev);
6314 return ret;
6315 }
6316
rtw89_hci_clr_idx_all(struct rtw89_dev * rtwdev)6317 static inline void rtw89_hci_clr_idx_all(struct rtw89_dev *rtwdev)
6318 {
6319 if (rtwdev->hci.ops->clr_idx_all)
6320 rtwdev->hci.ops->clr_idx_all(rtwdev);
6321 }
6322
rtw89_hci_rst_bdram(struct rtw89_dev * rtwdev)6323 static inline int rtw89_hci_rst_bdram(struct rtw89_dev *rtwdev)
6324 {
6325 int ret = 0;
6326
6327 if (rtwdev->hci.ops->rst_bdram)
6328 ret = rtwdev->hci.ops->rst_bdram(rtwdev);
6329 return ret;
6330 }
6331
rtw89_hci_clear(struct rtw89_dev * rtwdev,struct pci_dev * pdev)6332 static inline void rtw89_hci_clear(struct rtw89_dev *rtwdev, struct pci_dev *pdev)
6333 {
6334 if (rtwdev->hci.ops->clear)
6335 rtwdev->hci.ops->clear(rtwdev, pdev);
6336 }
6337
6338 static inline
RTW89_TX_SKB_CB(struct sk_buff * skb)6339 struct rtw89_tx_skb_data *RTW89_TX_SKB_CB(struct sk_buff *skb)
6340 {
6341 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
6342
6343 return (struct rtw89_tx_skb_data *)info->status.status_driver_data;
6344 }
6345
rtw89_read8(struct rtw89_dev * rtwdev,u32 addr)6346 static inline u8 rtw89_read8(struct rtw89_dev *rtwdev, u32 addr)
6347 {
6348 return rtwdev->hci.ops->read8(rtwdev, addr);
6349 }
6350
rtw89_read16(struct rtw89_dev * rtwdev,u32 addr)6351 static inline u16 rtw89_read16(struct rtw89_dev *rtwdev, u32 addr)
6352 {
6353 return rtwdev->hci.ops->read16(rtwdev, addr);
6354 }
6355
rtw89_read32(struct rtw89_dev * rtwdev,u32 addr)6356 static inline u32 rtw89_read32(struct rtw89_dev *rtwdev, u32 addr)
6357 {
6358 return rtwdev->hci.ops->read32(rtwdev, addr);
6359 }
6360
rtw89_write8(struct rtw89_dev * rtwdev,u32 addr,u8 data)6361 static inline void rtw89_write8(struct rtw89_dev *rtwdev, u32 addr, u8 data)
6362 {
6363 rtwdev->hci.ops->write8(rtwdev, addr, data);
6364 }
6365
rtw89_write16(struct rtw89_dev * rtwdev,u32 addr,u16 data)6366 static inline void rtw89_write16(struct rtw89_dev *rtwdev, u32 addr, u16 data)
6367 {
6368 rtwdev->hci.ops->write16(rtwdev, addr, data);
6369 }
6370
rtw89_write32(struct rtw89_dev * rtwdev,u32 addr,u32 data)6371 static inline void rtw89_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data)
6372 {
6373 rtwdev->hci.ops->write32(rtwdev, addr, data);
6374 }
6375
6376 static inline void
rtw89_write8_set(struct rtw89_dev * rtwdev,u32 addr,u8 bit)6377 rtw89_write8_set(struct rtw89_dev *rtwdev, u32 addr, u8 bit)
6378 {
6379 u8 val;
6380
6381 val = rtw89_read8(rtwdev, addr);
6382 rtw89_write8(rtwdev, addr, val | bit);
6383 }
6384
6385 static inline void
rtw89_write16_set(struct rtw89_dev * rtwdev,u32 addr,u16 bit)6386 rtw89_write16_set(struct rtw89_dev *rtwdev, u32 addr, u16 bit)
6387 {
6388 u16 val;
6389
6390 val = rtw89_read16(rtwdev, addr);
6391 rtw89_write16(rtwdev, addr, val | bit);
6392 }
6393
6394 static inline void
rtw89_write32_set(struct rtw89_dev * rtwdev,u32 addr,u32 bit)6395 rtw89_write32_set(struct rtw89_dev *rtwdev, u32 addr, u32 bit)
6396 {
6397 u32 val;
6398
6399 val = rtw89_read32(rtwdev, addr);
6400 rtw89_write32(rtwdev, addr, val | bit);
6401 }
6402
6403 static inline void
rtw89_write8_clr(struct rtw89_dev * rtwdev,u32 addr,u8 bit)6404 rtw89_write8_clr(struct rtw89_dev *rtwdev, u32 addr, u8 bit)
6405 {
6406 u8 val;
6407
6408 val = rtw89_read8(rtwdev, addr);
6409 rtw89_write8(rtwdev, addr, val & ~bit);
6410 }
6411
6412 static inline void
rtw89_write16_clr(struct rtw89_dev * rtwdev,u32 addr,u16 bit)6413 rtw89_write16_clr(struct rtw89_dev *rtwdev, u32 addr, u16 bit)
6414 {
6415 u16 val;
6416
6417 val = rtw89_read16(rtwdev, addr);
6418 rtw89_write16(rtwdev, addr, val & ~bit);
6419 }
6420
6421 static inline void
rtw89_write32_clr(struct rtw89_dev * rtwdev,u32 addr,u32 bit)6422 rtw89_write32_clr(struct rtw89_dev *rtwdev, u32 addr, u32 bit)
6423 {
6424 u32 val;
6425
6426 val = rtw89_read32(rtwdev, addr);
6427 rtw89_write32(rtwdev, addr, val & ~bit);
6428 }
6429
6430 static inline u32
rtw89_read32_mask(struct rtw89_dev * rtwdev,u32 addr,u32 mask)6431 rtw89_read32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask)
6432 {
6433 u32 shift = __ffs(mask);
6434 u32 orig;
6435 u32 ret;
6436
6437 orig = rtw89_read32(rtwdev, addr);
6438 ret = (orig & mask) >> shift;
6439
6440 return ret;
6441 }
6442
6443 static inline u16
rtw89_read16_mask(struct rtw89_dev * rtwdev,u32 addr,u32 mask)6444 rtw89_read16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask)
6445 {
6446 u32 shift = __ffs(mask);
6447 u32 orig;
6448 u32 ret;
6449
6450 orig = rtw89_read16(rtwdev, addr);
6451 ret = (orig & mask) >> shift;
6452
6453 return ret;
6454 }
6455
6456 static inline u8
rtw89_read8_mask(struct rtw89_dev * rtwdev,u32 addr,u32 mask)6457 rtw89_read8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask)
6458 {
6459 u32 shift = __ffs(mask);
6460 u32 orig;
6461 u32 ret;
6462
6463 orig = rtw89_read8(rtwdev, addr);
6464 ret = (orig & mask) >> shift;
6465
6466 return ret;
6467 }
6468
6469 static inline void
rtw89_write32_mask(struct rtw89_dev * rtwdev,u32 addr,u32 mask,u32 data)6470 rtw89_write32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u32 data)
6471 {
6472 u32 shift = __ffs(mask);
6473 u32 orig;
6474 u32 set;
6475
6476 WARN(addr & 0x3, "should be 4-byte aligned, addr = 0x%08x\n", addr);
6477
6478 orig = rtw89_read32(rtwdev, addr);
6479 set = (orig & ~mask) | ((data << shift) & mask);
6480 rtw89_write32(rtwdev, addr, set);
6481 }
6482
6483 static inline void
rtw89_write16_mask(struct rtw89_dev * rtwdev,u32 addr,u32 mask,u16 data)6484 rtw89_write16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u16 data)
6485 {
6486 u32 shift;
6487 u16 orig, set;
6488
6489 mask &= 0xffff;
6490 shift = __ffs(mask);
6491
6492 orig = rtw89_read16(rtwdev, addr);
6493 set = (orig & ~mask) | ((data << shift) & mask);
6494 rtw89_write16(rtwdev, addr, set);
6495 }
6496
6497 static inline void
rtw89_write8_mask(struct rtw89_dev * rtwdev,u32 addr,u32 mask,u8 data)6498 rtw89_write8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u8 data)
6499 {
6500 u32 shift;
6501 u8 orig, set;
6502
6503 mask &= 0xff;
6504 shift = __ffs(mask);
6505
6506 orig = rtw89_read8(rtwdev, addr);
6507 set = (orig & ~mask) | ((data << shift) & mask);
6508 rtw89_write8(rtwdev, addr, set);
6509 }
6510
6511 static inline u32
rtw89_read_rf(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask)6512 rtw89_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
6513 u32 addr, u32 mask)
6514 {
6515 u32 val;
6516
6517 mutex_lock(&rtwdev->rf_mutex);
6518 val = rtwdev->chip->ops->read_rf(rtwdev, rf_path, addr, mask);
6519 mutex_unlock(&rtwdev->rf_mutex);
6520
6521 return val;
6522 }
6523
6524 static inline void
rtw89_write_rf(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask,u32 data)6525 rtw89_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
6526 u32 addr, u32 mask, u32 data)
6527 {
6528 mutex_lock(&rtwdev->rf_mutex);
6529 rtwdev->chip->ops->write_rf(rtwdev, rf_path, addr, mask, data);
6530 mutex_unlock(&rtwdev->rf_mutex);
6531 }
6532
rtw89_txq_to_txq(struct rtw89_txq * rtwtxq)6533 static inline struct ieee80211_txq *rtw89_txq_to_txq(struct rtw89_txq *rtwtxq)
6534 {
6535 void *p = rtwtxq;
6536
6537 return container_of(p, struct ieee80211_txq, drv_priv);
6538 }
6539
rtw89_core_txq_init(struct rtw89_dev * rtwdev,struct ieee80211_txq * txq)6540 static inline void rtw89_core_txq_init(struct rtw89_dev *rtwdev,
6541 struct ieee80211_txq *txq)
6542 {
6543 struct rtw89_txq *rtwtxq;
6544
6545 if (!txq)
6546 return;
6547
6548 rtwtxq = (struct rtw89_txq *)txq->drv_priv;
6549 INIT_LIST_HEAD(&rtwtxq->list);
6550 }
6551
rtwvif_to_vif(struct rtw89_vif * rtwvif)6552 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw89_vif *rtwvif)
6553 {
6554 void *p = rtwvif;
6555
6556 return container_of(p, struct ieee80211_vif, drv_priv);
6557 }
6558
rtwvif_to_vif_safe(struct rtw89_vif * rtwvif)6559 static inline struct ieee80211_vif *rtwvif_to_vif_safe(struct rtw89_vif *rtwvif)
6560 {
6561 return rtwvif ? rtwvif_to_vif(rtwvif) : NULL;
6562 }
6563
6564 static inline
rtwvif_link_to_vif(struct rtw89_vif_link * rtwvif_link)6565 struct ieee80211_vif *rtwvif_link_to_vif(struct rtw89_vif_link *rtwvif_link)
6566 {
6567 return rtwvif_to_vif(rtwvif_link->rtwvif);
6568 }
6569
6570 static inline
rtwvif_link_to_vif_safe(struct rtw89_vif_link * rtwvif_link)6571 struct ieee80211_vif *rtwvif_link_to_vif_safe(struct rtw89_vif_link *rtwvif_link)
6572 {
6573 return rtwvif_link ? rtwvif_link_to_vif(rtwvif_link) : NULL;
6574 }
6575
vif_to_rtwvif(struct ieee80211_vif * vif)6576 static inline struct rtw89_vif *vif_to_rtwvif(struct ieee80211_vif *vif)
6577 {
6578 return (struct rtw89_vif *)vif->drv_priv;
6579 }
6580
vif_to_rtwvif_safe(struct ieee80211_vif * vif)6581 static inline struct rtw89_vif *vif_to_rtwvif_safe(struct ieee80211_vif *vif)
6582 {
6583 return vif ? vif_to_rtwvif(vif) : NULL;
6584 }
6585
rtwsta_to_sta(struct rtw89_sta * rtwsta)6586 static inline struct ieee80211_sta *rtwsta_to_sta(struct rtw89_sta *rtwsta)
6587 {
6588 void *p = rtwsta;
6589
6590 return container_of(p, struct ieee80211_sta, drv_priv);
6591 }
6592
rtwsta_to_sta_safe(struct rtw89_sta * rtwsta)6593 static inline struct ieee80211_sta *rtwsta_to_sta_safe(struct rtw89_sta *rtwsta)
6594 {
6595 return rtwsta ? rtwsta_to_sta(rtwsta) : NULL;
6596 }
6597
6598 static inline
rtwsta_link_to_sta(struct rtw89_sta_link * rtwsta_link)6599 struct ieee80211_sta *rtwsta_link_to_sta(struct rtw89_sta_link *rtwsta_link)
6600 {
6601 return rtwsta_to_sta(rtwsta_link->rtwsta);
6602 }
6603
6604 static inline
rtwsta_link_to_sta_safe(struct rtw89_sta_link * rtwsta_link)6605 struct ieee80211_sta *rtwsta_link_to_sta_safe(struct rtw89_sta_link *rtwsta_link)
6606 {
6607 return rtwsta_link ? rtwsta_link_to_sta(rtwsta_link) : NULL;
6608 }
6609
sta_to_rtwsta(struct ieee80211_sta * sta)6610 static inline struct rtw89_sta *sta_to_rtwsta(struct ieee80211_sta *sta)
6611 {
6612 return (struct rtw89_sta *)sta->drv_priv;
6613 }
6614
sta_to_rtwsta_safe(struct ieee80211_sta * sta)6615 static inline struct rtw89_sta *sta_to_rtwsta_safe(struct ieee80211_sta *sta)
6616 {
6617 return sta ? sta_to_rtwsta(sta) : NULL;
6618 }
6619
6620 static inline struct ieee80211_bss_conf *
__rtw89_vif_rcu_dereference_link(struct rtw89_vif_link * rtwvif_link,bool * nolink)6621 __rtw89_vif_rcu_dereference_link(struct rtw89_vif_link *rtwvif_link, bool *nolink)
6622 {
6623 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
6624 struct rtw89_vif *rtwvif = rtwvif_link->rtwvif;
6625 struct rtw89_link_conf_container *snap;
6626 struct ieee80211_bss_conf *bss_conf;
6627
6628 snap = rcu_dereference(rtwvif->snap_link_confs);
6629 if (snap) {
6630 bss_conf = snap->link_conf[rtwvif_link->link_id];
6631 goto out;
6632 }
6633
6634 bss_conf = rcu_dereference(vif->link_conf[rtwvif_link->link_id]);
6635
6636 out:
6637 if (unlikely(!bss_conf)) {
6638 *nolink = true;
6639 return &vif->bss_conf;
6640 }
6641
6642 *nolink = false;
6643 return bss_conf;
6644 }
6645
6646 #define rtw89_vif_rcu_dereference_link(rtwvif_link, assert) \
6647 ({ \
6648 typeof(rtwvif_link) p = rtwvif_link; \
6649 struct ieee80211_bss_conf *bss_conf; \
6650 bool nolink; \
6651 \
6652 bss_conf = __rtw89_vif_rcu_dereference_link(p, &nolink); \
6653 if (unlikely(nolink) && (assert)) \
6654 rtw89_err(p->rtwvif->rtwdev, \
6655 "%s: cannot find exact bss_conf for link_id %u\n",\
6656 __func__, p->link_id); \
6657 bss_conf; \
6658 })
6659
6660 static inline struct ieee80211_link_sta *
__rtw89_sta_rcu_dereference_link(struct rtw89_sta_link * rtwsta_link,bool * nolink)6661 __rtw89_sta_rcu_dereference_link(struct rtw89_sta_link *rtwsta_link, bool *nolink)
6662 {
6663 struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link);
6664 struct ieee80211_link_sta *link_sta;
6665
6666 link_sta = rcu_dereference(sta->link[rtwsta_link->link_id]);
6667 if (unlikely(!link_sta)) {
6668 *nolink = true;
6669 return &sta->deflink;
6670 }
6671
6672 *nolink = false;
6673 return link_sta;
6674 }
6675
6676 #define rtw89_sta_rcu_dereference_link(rtwsta_link, assert) \
6677 ({ \
6678 typeof(rtwsta_link) p = rtwsta_link; \
6679 struct ieee80211_link_sta *link_sta; \
6680 bool nolink; \
6681 \
6682 link_sta = __rtw89_sta_rcu_dereference_link(p, &nolink); \
6683 if (unlikely(nolink) && (assert)) \
6684 rtw89_err(p->rtwsta->rtwdev, \
6685 "%s: cannot find exact link_sta for link_id %u\n",\
6686 __func__, p->link_id); \
6687 link_sta; \
6688 })
6689
rtw89_hw_to_rate_info_bw(enum rtw89_bandwidth hw_bw)6690 static inline u8 rtw89_hw_to_rate_info_bw(enum rtw89_bandwidth hw_bw)
6691 {
6692 if (hw_bw == RTW89_CHANNEL_WIDTH_160)
6693 return RATE_INFO_BW_160;
6694 else if (hw_bw == RTW89_CHANNEL_WIDTH_80)
6695 return RATE_INFO_BW_80;
6696 else if (hw_bw == RTW89_CHANNEL_WIDTH_40)
6697 return RATE_INFO_BW_40;
6698 else
6699 return RATE_INFO_BW_20;
6700 }
6701
6702 static inline
rtw89_hw_to_nl80211_band(enum rtw89_band hw_band)6703 enum nl80211_band rtw89_hw_to_nl80211_band(enum rtw89_band hw_band)
6704 {
6705 switch (hw_band) {
6706 default:
6707 case RTW89_BAND_2G:
6708 return NL80211_BAND_2GHZ;
6709 case RTW89_BAND_5G:
6710 return NL80211_BAND_5GHZ;
6711 case RTW89_BAND_6G:
6712 return NL80211_BAND_6GHZ;
6713 }
6714 }
6715
6716 static inline
rtw89_nl80211_to_hw_band(enum nl80211_band nl_band)6717 enum rtw89_band rtw89_nl80211_to_hw_band(enum nl80211_band nl_band)
6718 {
6719 switch (nl_band) {
6720 default:
6721 case NL80211_BAND_2GHZ:
6722 return RTW89_BAND_2G;
6723 case NL80211_BAND_5GHZ:
6724 return RTW89_BAND_5G;
6725 case NL80211_BAND_6GHZ:
6726 return RTW89_BAND_6G;
6727 }
6728 }
6729
6730 static inline
nl_to_rtw89_bandwidth(enum nl80211_chan_width width)6731 enum rtw89_bandwidth nl_to_rtw89_bandwidth(enum nl80211_chan_width width)
6732 {
6733 switch (width) {
6734 default:
6735 WARN(1, "Not support bandwidth %d\n", width);
6736 fallthrough;
6737 case NL80211_CHAN_WIDTH_20_NOHT:
6738 case NL80211_CHAN_WIDTH_20:
6739 return RTW89_CHANNEL_WIDTH_20;
6740 case NL80211_CHAN_WIDTH_40:
6741 return RTW89_CHANNEL_WIDTH_40;
6742 case NL80211_CHAN_WIDTH_80:
6743 return RTW89_CHANNEL_WIDTH_80;
6744 case NL80211_CHAN_WIDTH_160:
6745 return RTW89_CHANNEL_WIDTH_160;
6746 }
6747 }
6748
6749 static inline
rtw89_he_rua_to_ru_alloc(u16 rua)6750 enum nl80211_he_ru_alloc rtw89_he_rua_to_ru_alloc(u16 rua)
6751 {
6752 switch (rua) {
6753 default:
6754 WARN(1, "Invalid RU allocation: %d\n", rua);
6755 fallthrough;
6756 case 0 ... 36:
6757 return NL80211_RATE_INFO_HE_RU_ALLOC_26;
6758 case 37 ... 52:
6759 return NL80211_RATE_INFO_HE_RU_ALLOC_52;
6760 case 53 ... 60:
6761 return NL80211_RATE_INFO_HE_RU_ALLOC_106;
6762 case 61 ... 64:
6763 return NL80211_RATE_INFO_HE_RU_ALLOC_242;
6764 case 65 ... 66:
6765 return NL80211_RATE_INFO_HE_RU_ALLOC_484;
6766 case 67:
6767 return NL80211_RATE_INFO_HE_RU_ALLOC_996;
6768 case 68:
6769 return NL80211_RATE_INFO_HE_RU_ALLOC_2x996;
6770 }
6771 }
6772
6773 static inline
rtw89_get_addr_cam_of(struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)6774 struct rtw89_addr_cam_entry *rtw89_get_addr_cam_of(struct rtw89_vif_link *rtwvif_link,
6775 struct rtw89_sta_link *rtwsta_link)
6776 {
6777 if (rtwsta_link) {
6778 struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link);
6779
6780 if (rtwvif_link->net_type == RTW89_NET_TYPE_AP_MODE || sta->tdls)
6781 return &rtwsta_link->addr_cam;
6782 }
6783 return &rtwvif_link->addr_cam;
6784 }
6785
6786 static inline
rtw89_get_bssid_cam_of(struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)6787 struct rtw89_bssid_cam_entry *rtw89_get_bssid_cam_of(struct rtw89_vif_link *rtwvif_link,
6788 struct rtw89_sta_link *rtwsta_link)
6789 {
6790 if (rtwsta_link) {
6791 struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link);
6792
6793 if (sta->tdls)
6794 return &rtwsta_link->bssid_cam;
6795 }
6796 return &rtwvif_link->bssid_cam;
6797 }
6798
6799 static inline
rtw89_chip_set_channel_prepare(struct rtw89_dev * rtwdev,struct rtw89_channel_help_params * p,const struct rtw89_chan * chan,enum rtw89_mac_idx mac_idx,enum rtw89_phy_idx phy_idx)6800 void rtw89_chip_set_channel_prepare(struct rtw89_dev *rtwdev,
6801 struct rtw89_channel_help_params *p,
6802 const struct rtw89_chan *chan,
6803 enum rtw89_mac_idx mac_idx,
6804 enum rtw89_phy_idx phy_idx)
6805 {
6806 rtwdev->chip->ops->set_channel_help(rtwdev, true, p, chan,
6807 mac_idx, phy_idx);
6808 }
6809
6810 static inline
rtw89_chip_set_channel_done(struct rtw89_dev * rtwdev,struct rtw89_channel_help_params * p,const struct rtw89_chan * chan,enum rtw89_mac_idx mac_idx,enum rtw89_phy_idx phy_idx)6811 void rtw89_chip_set_channel_done(struct rtw89_dev *rtwdev,
6812 struct rtw89_channel_help_params *p,
6813 const struct rtw89_chan *chan,
6814 enum rtw89_mac_idx mac_idx,
6815 enum rtw89_phy_idx phy_idx)
6816 {
6817 rtwdev->chip->ops->set_channel_help(rtwdev, false, p, chan,
6818 mac_idx, phy_idx);
6819 }
6820
6821 static inline
rtw89_chandef_get(struct rtw89_dev * rtwdev,enum rtw89_chanctx_idx idx)6822 const struct cfg80211_chan_def *rtw89_chandef_get(struct rtw89_dev *rtwdev,
6823 enum rtw89_chanctx_idx idx)
6824 {
6825 struct rtw89_hal *hal = &rtwdev->hal;
6826 enum rtw89_chanctx_idx roc_idx = atomic_read(&hal->roc_chanctx_idx);
6827
6828 if (roc_idx == idx)
6829 return &hal->roc_chandef;
6830
6831 return &hal->chanctx[idx].chandef;
6832 }
6833
6834 static inline
rtw89_chan_get(struct rtw89_dev * rtwdev,enum rtw89_chanctx_idx idx)6835 const struct rtw89_chan *rtw89_chan_get(struct rtw89_dev *rtwdev,
6836 enum rtw89_chanctx_idx idx)
6837 {
6838 struct rtw89_hal *hal = &rtwdev->hal;
6839
6840 return &hal->chanctx[idx].chan;
6841 }
6842
6843 static inline
rtw89_chan_rcd_get(struct rtw89_dev * rtwdev,enum rtw89_chanctx_idx idx)6844 const struct rtw89_chan_rcd *rtw89_chan_rcd_get(struct rtw89_dev *rtwdev,
6845 enum rtw89_chanctx_idx idx)
6846 {
6847 struct rtw89_hal *hal = &rtwdev->hal;
6848
6849 return &hal->chanctx[idx].rcd;
6850 }
6851
6852 static inline
rtw89_chan_rcd_get_by_chan(const struct rtw89_chan * chan)6853 const struct rtw89_chan_rcd *rtw89_chan_rcd_get_by_chan(const struct rtw89_chan *chan)
6854 {
6855 const struct rtw89_chanctx *chanctx =
6856 container_of_const(chan, struct rtw89_chanctx, chan);
6857
6858 return &chanctx->rcd;
6859 }
6860
6861 static inline
rtw89_scan_chan_get(struct rtw89_dev * rtwdev)6862 const struct rtw89_chan *rtw89_scan_chan_get(struct rtw89_dev *rtwdev)
6863 {
6864 struct rtw89_vif_link *rtwvif_link = rtwdev->scan_info.scanning_vif;
6865
6866 if (rtwvif_link)
6867 return rtw89_chan_get(rtwdev, rtwvif_link->chanctx_idx);
6868 else
6869 return rtw89_chan_get(rtwdev, RTW89_CHANCTX_0);
6870 }
6871
rtw89_chip_fem_setup(struct rtw89_dev * rtwdev)6872 static inline void rtw89_chip_fem_setup(struct rtw89_dev *rtwdev)
6873 {
6874 const struct rtw89_chip_info *chip = rtwdev->chip;
6875
6876 if (chip->ops->fem_setup)
6877 chip->ops->fem_setup(rtwdev);
6878 }
6879
rtw89_chip_rfe_gpio(struct rtw89_dev * rtwdev)6880 static inline void rtw89_chip_rfe_gpio(struct rtw89_dev *rtwdev)
6881 {
6882 const struct rtw89_chip_info *chip = rtwdev->chip;
6883
6884 if (chip->ops->rfe_gpio)
6885 chip->ops->rfe_gpio(rtwdev);
6886 }
6887
rtw89_chip_rfk_hw_init(struct rtw89_dev * rtwdev)6888 static inline void rtw89_chip_rfk_hw_init(struct rtw89_dev *rtwdev)
6889 {
6890 const struct rtw89_chip_info *chip = rtwdev->chip;
6891
6892 if (chip->ops->rfk_hw_init)
6893 chip->ops->rfk_hw_init(rtwdev);
6894 }
6895
6896 static inline
rtw89_chip_bb_preinit(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)6897 void rtw89_chip_bb_preinit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
6898 {
6899 const struct rtw89_chip_info *chip = rtwdev->chip;
6900
6901 if (chip->ops->bb_preinit)
6902 chip->ops->bb_preinit(rtwdev, phy_idx);
6903 }
6904
6905 static inline
rtw89_chip_bb_postinit(struct rtw89_dev * rtwdev)6906 void rtw89_chip_bb_postinit(struct rtw89_dev *rtwdev)
6907 {
6908 const struct rtw89_chip_info *chip = rtwdev->chip;
6909
6910 if (!chip->ops->bb_postinit)
6911 return;
6912
6913 chip->ops->bb_postinit(rtwdev, RTW89_PHY_0);
6914
6915 if (rtwdev->dbcc_en)
6916 chip->ops->bb_postinit(rtwdev, RTW89_PHY_1);
6917 }
6918
rtw89_chip_bb_sethw(struct rtw89_dev * rtwdev)6919 static inline void rtw89_chip_bb_sethw(struct rtw89_dev *rtwdev)
6920 {
6921 const struct rtw89_chip_info *chip = rtwdev->chip;
6922
6923 if (chip->ops->bb_sethw)
6924 chip->ops->bb_sethw(rtwdev);
6925 }
6926
rtw89_chip_rfk_init(struct rtw89_dev * rtwdev)6927 static inline void rtw89_chip_rfk_init(struct rtw89_dev *rtwdev)
6928 {
6929 const struct rtw89_chip_info *chip = rtwdev->chip;
6930
6931 if (chip->ops->rfk_init)
6932 chip->ops->rfk_init(rtwdev);
6933 }
6934
rtw89_chip_rfk_init_late(struct rtw89_dev * rtwdev)6935 static inline void rtw89_chip_rfk_init_late(struct rtw89_dev *rtwdev)
6936 {
6937 const struct rtw89_chip_info *chip = rtwdev->chip;
6938
6939 if (chip->ops->rfk_init_late)
6940 chip->ops->rfk_init_late(rtwdev);
6941 }
6942
rtw89_chip_rfk_channel(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link)6943 static inline void rtw89_chip_rfk_channel(struct rtw89_dev *rtwdev,
6944 struct rtw89_vif_link *rtwvif_link)
6945 {
6946 const struct rtw89_chip_info *chip = rtwdev->chip;
6947
6948 if (chip->ops->rfk_channel)
6949 chip->ops->rfk_channel(rtwdev, rtwvif_link);
6950 }
6951
rtw89_chip_rfk_band_changed(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,const struct rtw89_chan * chan)6952 static inline void rtw89_chip_rfk_band_changed(struct rtw89_dev *rtwdev,
6953 enum rtw89_phy_idx phy_idx,
6954 const struct rtw89_chan *chan)
6955 {
6956 const struct rtw89_chip_info *chip = rtwdev->chip;
6957
6958 if (chip->ops->rfk_band_changed)
6959 chip->ops->rfk_band_changed(rtwdev, phy_idx, chan);
6960 }
6961
rtw89_chip_rfk_scan(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,bool start)6962 static inline void rtw89_chip_rfk_scan(struct rtw89_dev *rtwdev,
6963 struct rtw89_vif_link *rtwvif_link, bool start)
6964 {
6965 const struct rtw89_chip_info *chip = rtwdev->chip;
6966
6967 if (chip->ops->rfk_scan)
6968 chip->ops->rfk_scan(rtwdev, rtwvif_link, start);
6969 }
6970
rtw89_chip_rfk_track(struct rtw89_dev * rtwdev)6971 static inline void rtw89_chip_rfk_track(struct rtw89_dev *rtwdev)
6972 {
6973 const struct rtw89_chip_info *chip = rtwdev->chip;
6974
6975 if (chip->ops->rfk_track)
6976 chip->ops->rfk_track(rtwdev);
6977 }
6978
rtw89_chip_set_txpwr_ctrl(struct rtw89_dev * rtwdev)6979 static inline void rtw89_chip_set_txpwr_ctrl(struct rtw89_dev *rtwdev)
6980 {
6981 const struct rtw89_chip_info *chip = rtwdev->chip;
6982
6983 if (!chip->ops->set_txpwr_ctrl)
6984 return;
6985
6986 chip->ops->set_txpwr_ctrl(rtwdev, RTW89_PHY_0);
6987 if (rtwdev->dbcc_en)
6988 chip->ops->set_txpwr_ctrl(rtwdev, RTW89_PHY_1);
6989 }
6990
rtw89_chip_power_trim(struct rtw89_dev * rtwdev)6991 static inline void rtw89_chip_power_trim(struct rtw89_dev *rtwdev)
6992 {
6993 const struct rtw89_chip_info *chip = rtwdev->chip;
6994
6995 if (chip->ops->power_trim)
6996 chip->ops->power_trim(rtwdev);
6997 }
6998
__rtw89_chip_init_txpwr_unit(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)6999 static inline void __rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev,
7000 enum rtw89_phy_idx phy_idx)
7001 {
7002 const struct rtw89_chip_info *chip = rtwdev->chip;
7003
7004 if (chip->ops->init_txpwr_unit)
7005 chip->ops->init_txpwr_unit(rtwdev, phy_idx);
7006 }
7007
rtw89_chip_init_txpwr_unit(struct rtw89_dev * rtwdev)7008 static inline void rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev)
7009 {
7010 __rtw89_chip_init_txpwr_unit(rtwdev, RTW89_PHY_0);
7011 if (rtwdev->dbcc_en)
7012 __rtw89_chip_init_txpwr_unit(rtwdev, RTW89_PHY_1);
7013 }
7014
rtw89_chip_get_thermal(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path)7015 static inline u8 rtw89_chip_get_thermal(struct rtw89_dev *rtwdev,
7016 enum rtw89_rf_path rf_path)
7017 {
7018 const struct rtw89_chip_info *chip = rtwdev->chip;
7019
7020 if (!chip->ops->get_thermal)
7021 return 0x10;
7022
7023 return chip->ops->get_thermal(rtwdev, rf_path);
7024 }
7025
rtw89_chip_chan_to_rf18_val(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan)7026 static inline u32 rtw89_chip_chan_to_rf18_val(struct rtw89_dev *rtwdev,
7027 const struct rtw89_chan *chan)
7028 {
7029 const struct rtw89_chip_info *chip = rtwdev->chip;
7030
7031 if (!chip->ops->chan_to_rf18_val)
7032 return 0;
7033
7034 return chip->ops->chan_to_rf18_val(rtwdev, chan);
7035 }
7036
rtw89_chip_query_ppdu(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu,struct ieee80211_rx_status * status)7037 static inline void rtw89_chip_query_ppdu(struct rtw89_dev *rtwdev,
7038 struct rtw89_rx_phy_ppdu *phy_ppdu,
7039 struct ieee80211_rx_status *status)
7040 {
7041 const struct rtw89_chip_info *chip = rtwdev->chip;
7042
7043 if (chip->ops->query_ppdu)
7044 chip->ops->query_ppdu(rtwdev, phy_ppdu, status);
7045 }
7046
rtw89_chip_convert_rpl_to_rssi(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu)7047 static inline void rtw89_chip_convert_rpl_to_rssi(struct rtw89_dev *rtwdev,
7048 struct rtw89_rx_phy_ppdu *phy_ppdu)
7049 {
7050 const struct rtw89_chip_info *chip = rtwdev->chip;
7051
7052 if (chip->ops->convert_rpl_to_rssi)
7053 chip->ops->convert_rpl_to_rssi(rtwdev, phy_ppdu);
7054 }
7055
rtw89_chip_phy_rpt_to_rssi(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,struct ieee80211_rx_status * rx_status)7056 static inline void rtw89_chip_phy_rpt_to_rssi(struct rtw89_dev *rtwdev,
7057 struct rtw89_rx_desc_info *desc_info,
7058 struct ieee80211_rx_status *rx_status)
7059 {
7060 const struct rtw89_chip_info *chip = rtwdev->chip;
7061
7062 if (chip->ops->phy_rpt_to_rssi)
7063 chip->ops->phy_rpt_to_rssi(rtwdev, desc_info, rx_status);
7064 }
7065
rtw89_ctrl_nbtg_bt_tx(struct rtw89_dev * rtwdev,bool en,enum rtw89_phy_idx phy_idx)7066 static inline void rtw89_ctrl_nbtg_bt_tx(struct rtw89_dev *rtwdev, bool en,
7067 enum rtw89_phy_idx phy_idx)
7068 {
7069 const struct rtw89_chip_info *chip = rtwdev->chip;
7070
7071 if (chip->ops->ctrl_nbtg_bt_tx)
7072 chip->ops->ctrl_nbtg_bt_tx(rtwdev, en, phy_idx);
7073 }
7074
rtw89_chip_cfg_txrx_path(struct rtw89_dev * rtwdev)7075 static inline void rtw89_chip_cfg_txrx_path(struct rtw89_dev *rtwdev)
7076 {
7077 const struct rtw89_chip_info *chip = rtwdev->chip;
7078
7079 if (chip->ops->cfg_txrx_path)
7080 chip->ops->cfg_txrx_path(rtwdev);
7081 }
7082
rtw89_chip_digital_pwr_comp(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)7083 static inline void rtw89_chip_digital_pwr_comp(struct rtw89_dev *rtwdev,
7084 enum rtw89_phy_idx phy_idx)
7085 {
7086 const struct rtw89_chip_info *chip = rtwdev->chip;
7087
7088 if (chip->ops->digital_pwr_comp)
7089 chip->ops->digital_pwr_comp(rtwdev, phy_idx);
7090 }
7091
rtw89_load_txpwr_table(struct rtw89_dev * rtwdev,const struct rtw89_txpwr_table * tbl)7092 static inline void rtw89_load_txpwr_table(struct rtw89_dev *rtwdev,
7093 const struct rtw89_txpwr_table *tbl)
7094 {
7095 tbl->load(rtwdev, tbl);
7096 }
7097
rtw89_regd_get(struct rtw89_dev * rtwdev,u8 band)7098 static inline u8 rtw89_regd_get(struct rtw89_dev *rtwdev, u8 band)
7099 {
7100 const struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory;
7101 const struct rtw89_regd *regd = regulatory->regd;
7102 u8 txpwr_regd = regd->txpwr_regd[band];
7103
7104 if (regulatory->txpwr_uk_follow_etsi && txpwr_regd == RTW89_UK)
7105 return RTW89_ETSI;
7106
7107 return txpwr_regd;
7108 }
7109
rtw89_ctrl_btg_bt_rx(struct rtw89_dev * rtwdev,bool en,enum rtw89_phy_idx phy_idx)7110 static inline void rtw89_ctrl_btg_bt_rx(struct rtw89_dev *rtwdev, bool en,
7111 enum rtw89_phy_idx phy_idx)
7112 {
7113 const struct rtw89_chip_info *chip = rtwdev->chip;
7114
7115 if (chip->ops->ctrl_btg_bt_rx)
7116 chip->ops->ctrl_btg_bt_rx(rtwdev, en, phy_idx);
7117 }
7118
7119 static inline
rtw89_chip_query_rxdesc(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,u8 * data,u32 data_offset)7120 void rtw89_chip_query_rxdesc(struct rtw89_dev *rtwdev,
7121 struct rtw89_rx_desc_info *desc_info,
7122 u8 *data, u32 data_offset)
7123 {
7124 const struct rtw89_chip_info *chip = rtwdev->chip;
7125
7126 chip->ops->query_rxdesc(rtwdev, desc_info, data, data_offset);
7127 }
7128
7129 static inline
rtw89_chip_fill_txdesc(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,void * txdesc)7130 void rtw89_chip_fill_txdesc(struct rtw89_dev *rtwdev,
7131 struct rtw89_tx_desc_info *desc_info,
7132 void *txdesc)
7133 {
7134 const struct rtw89_chip_info *chip = rtwdev->chip;
7135
7136 chip->ops->fill_txdesc(rtwdev, desc_info, txdesc);
7137 }
7138
7139 static inline
rtw89_chip_fill_txdesc_fwcmd(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,void * txdesc)7140 void rtw89_chip_fill_txdesc_fwcmd(struct rtw89_dev *rtwdev,
7141 struct rtw89_tx_desc_info *desc_info,
7142 void *txdesc)
7143 {
7144 const struct rtw89_chip_info *chip = rtwdev->chip;
7145
7146 chip->ops->fill_txdesc_fwcmd(rtwdev, desc_info, txdesc);
7147 }
7148
7149 static inline
rtw89_chip_mac_cfg_gnt(struct rtw89_dev * rtwdev,const struct rtw89_mac_ax_coex_gnt * gnt_cfg)7150 void rtw89_chip_mac_cfg_gnt(struct rtw89_dev *rtwdev,
7151 const struct rtw89_mac_ax_coex_gnt *gnt_cfg)
7152 {
7153 const struct rtw89_chip_info *chip = rtwdev->chip;
7154
7155 chip->ops->mac_cfg_gnt(rtwdev, gnt_cfg);
7156 }
7157
rtw89_chip_cfg_ctrl_path(struct rtw89_dev * rtwdev,bool wl)7158 static inline void rtw89_chip_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl)
7159 {
7160 const struct rtw89_chip_info *chip = rtwdev->chip;
7161
7162 chip->ops->cfg_ctrl_path(rtwdev, wl);
7163 }
7164
7165 static inline
rtw89_chip_stop_sch_tx(struct rtw89_dev * rtwdev,u8 mac_idx,u32 * tx_en,enum rtw89_sch_tx_sel sel)7166 int rtw89_chip_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx,
7167 u32 *tx_en, enum rtw89_sch_tx_sel sel)
7168 {
7169 const struct rtw89_chip_info *chip = rtwdev->chip;
7170
7171 return chip->ops->stop_sch_tx(rtwdev, mac_idx, tx_en, sel);
7172 }
7173
7174 static inline
rtw89_chip_resume_sch_tx(struct rtw89_dev * rtwdev,u8 mac_idx,u32 tx_en)7175 int rtw89_chip_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en)
7176 {
7177 const struct rtw89_chip_info *chip = rtwdev->chip;
7178
7179 return chip->ops->resume_sch_tx(rtwdev, mac_idx, tx_en);
7180 }
7181
7182 static inline
rtw89_chip_h2c_dctl_sec_cam(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)7183 int rtw89_chip_h2c_dctl_sec_cam(struct rtw89_dev *rtwdev,
7184 struct rtw89_vif_link *rtwvif_link,
7185 struct rtw89_sta_link *rtwsta_link)
7186 {
7187 const struct rtw89_chip_info *chip = rtwdev->chip;
7188
7189 if (!chip->ops->h2c_dctl_sec_cam)
7190 return 0;
7191 return chip->ops->h2c_dctl_sec_cam(rtwdev, rtwvif_link, rtwsta_link);
7192 }
7193
get_hdr_bssid(struct ieee80211_hdr * hdr)7194 static inline u8 *get_hdr_bssid(struct ieee80211_hdr *hdr)
7195 {
7196 __le16 fc = hdr->frame_control;
7197
7198 if (ieee80211_has_tods(fc))
7199 return hdr->addr1;
7200 else if (ieee80211_has_fromds(fc))
7201 return hdr->addr2;
7202 else
7203 return hdr->addr3;
7204 }
7205
7206 static inline
rtw89_sta_has_beamformer_cap(struct ieee80211_link_sta * link_sta)7207 bool rtw89_sta_has_beamformer_cap(struct ieee80211_link_sta *link_sta)
7208 {
7209 if ((link_sta->vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) ||
7210 (link_sta->vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE) ||
7211 (link_sta->he_cap.he_cap_elem.phy_cap_info[3] &
7212 IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) ||
7213 (link_sta->he_cap.he_cap_elem.phy_cap_info[4] &
7214 IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER))
7215 return true;
7216 return false;
7217 }
7218
7219 static inline
rtw89_sta_link_has_su_mu_4xhe08(struct ieee80211_link_sta * link_sta)7220 bool rtw89_sta_link_has_su_mu_4xhe08(struct ieee80211_link_sta *link_sta)
7221 {
7222 if (link_sta->he_cap.he_cap_elem.phy_cap_info[7] &
7223 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI)
7224 return true;
7225
7226 return false;
7227 }
7228
7229 static inline
rtw89_sta_link_has_er_su_4xhe08(struct ieee80211_link_sta * link_sta)7230 bool rtw89_sta_link_has_er_su_4xhe08(struct ieee80211_link_sta *link_sta)
7231 {
7232 if (link_sta->he_cap.he_cap_elem.phy_cap_info[8] &
7233 IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI)
7234 return true;
7235
7236 return false;
7237 }
7238
rtw89_fw_suit_get(struct rtw89_dev * rtwdev,enum rtw89_fw_type type)7239 static inline struct rtw89_fw_suit *rtw89_fw_suit_get(struct rtw89_dev *rtwdev,
7240 #if defined(__linux__)
7241 enum rtw89_fw_type type)
7242 #elif defined(__FreeBSD__)
7243 const enum rtw89_fw_type type)
7244 #endif
7245 {
7246 struct rtw89_fw_info *fw_info = &rtwdev->fw;
7247
7248 switch (type) {
7249 case RTW89_FW_WOWLAN:
7250 return &fw_info->wowlan;
7251 case RTW89_FW_LOGFMT:
7252 return &fw_info->log.suit;
7253 case RTW89_FW_BBMCU0:
7254 return &fw_info->bbmcu0;
7255 case RTW89_FW_BBMCU1:
7256 return &fw_info->bbmcu1;
7257 default:
7258 break;
7259 }
7260
7261 return &fw_info->normal;
7262 }
7263
rtw89_alloc_skb_for_rx(struct rtw89_dev * rtwdev,unsigned int length)7264 static inline struct sk_buff *rtw89_alloc_skb_for_rx(struct rtw89_dev *rtwdev,
7265 unsigned int length)
7266 {
7267 struct sk_buff *skb;
7268
7269 if (rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR) {
7270 skb = dev_alloc_skb(length + RTW89_RADIOTAP_ROOM);
7271 if (!skb)
7272 return NULL;
7273
7274 skb_reserve(skb, RTW89_RADIOTAP_ROOM);
7275 return skb;
7276 }
7277
7278 return dev_alloc_skb(length);
7279 }
7280
rtw89_core_tx_wait_complete(struct rtw89_dev * rtwdev,struct rtw89_tx_skb_data * skb_data,bool tx_done)7281 static inline void rtw89_core_tx_wait_complete(struct rtw89_dev *rtwdev,
7282 struct rtw89_tx_skb_data *skb_data,
7283 bool tx_done)
7284 {
7285 struct rtw89_tx_wait_info *wait;
7286
7287 rcu_read_lock();
7288
7289 wait = rcu_dereference(skb_data->wait);
7290 if (!wait)
7291 goto out;
7292
7293 wait->tx_done = tx_done;
7294 complete(&wait->completion);
7295
7296 out:
7297 rcu_read_unlock();
7298 }
7299
rtw89_is_mlo_1_1(struct rtw89_dev * rtwdev)7300 static inline bool rtw89_is_mlo_1_1(struct rtw89_dev *rtwdev)
7301 {
7302 switch (rtwdev->mlo_dbcc_mode) {
7303 case MLO_1_PLUS_1_1RF:
7304 case MLO_1_PLUS_1_2RF:
7305 case DBCC_LEGACY:
7306 return true;
7307 default:
7308 return false;
7309 }
7310 }
7311
rtw89_get_active_phy_bitmap(struct rtw89_dev * rtwdev)7312 static inline u8 rtw89_get_active_phy_bitmap(struct rtw89_dev *rtwdev)
7313 {
7314 if (!rtwdev->dbcc_en)
7315 return BIT(RTW89_PHY_0);
7316
7317 switch (rtwdev->mlo_dbcc_mode) {
7318 case MLO_0_PLUS_2_1RF:
7319 case MLO_0_PLUS_2_2RF:
7320 return BIT(RTW89_PHY_1);
7321 case MLO_1_PLUS_1_1RF:
7322 case MLO_1_PLUS_1_2RF:
7323 case MLO_2_PLUS_2_2RF:
7324 case DBCC_LEGACY:
7325 return BIT(RTW89_PHY_0) | BIT(RTW89_PHY_1);
7326 case MLO_2_PLUS_0_1RF:
7327 case MLO_2_PLUS_0_2RF:
7328 default:
7329 return BIT(RTW89_PHY_0);
7330 }
7331 }
7332
7333 #define rtw89_for_each_active_bb(rtwdev, bb) \
7334 for (u8 __active_bb_bitmap = rtw89_get_active_phy_bitmap(rtwdev), \
7335 __phy_idx = 0; __phy_idx < RTW89_PHY_NUM; __phy_idx++) \
7336 if (__active_bb_bitmap & BIT(__phy_idx) && \
7337 (bb = &rtwdev->bbs[__phy_idx]))
7338
7339 #define rtw89_for_each_capab_bb(rtwdev, bb) \
7340 for (u8 __phy_idx_max = rtwdev->dbcc_en ? RTW89_PHY_1 : RTW89_PHY_0, \
7341 __phy_idx = 0; __phy_idx <= __phy_idx_max; __phy_idx++) \
7342 if ((bb = &rtwdev->bbs[__phy_idx]))
7343
7344 static inline
rtw89_get_bb_ctx(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)7345 struct rtw89_bb_ctx *rtw89_get_bb_ctx(struct rtw89_dev *rtwdev,
7346 enum rtw89_phy_idx phy_idx)
7347 {
7348 if (phy_idx >= RTW89_PHY_NUM)
7349 return &rtwdev->bbs[RTW89_PHY_0];
7350
7351 return &rtwdev->bbs[phy_idx];
7352 }
7353
rtw89_is_rtl885xb(struct rtw89_dev * rtwdev)7354 static inline bool rtw89_is_rtl885xb(struct rtw89_dev *rtwdev)
7355 {
7356 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
7357
7358 if (chip_id == RTL8852B || chip_id == RTL8851B || chip_id == RTL8852BT)
7359 return true;
7360
7361 return false;
7362 }
7363
rtw89_bytes_to_mbps(u64 bytes,enum rtw89_tfc_interval interval)7364 static inline u32 rtw89_bytes_to_mbps(u64 bytes, enum rtw89_tfc_interval interval)
7365 {
7366 switch (interval) {
7367 default:
7368 case RTW89_TFC_INTERVAL_2SEC:
7369 return bytes >> 18; /* bytes/2s --> Mbps */;
7370 case RTW89_TFC_INTERVAL_100MS:
7371 return (bytes * 10) >> 17; /* bytes/100ms --> Mbps */
7372 }
7373 }
7374
7375 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
7376 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel);
7377 int rtw89_h2c_tx(struct rtw89_dev *rtwdev,
7378 struct sk_buff *skb, bool fwdl);
7379 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel);
7380 int rtw89_core_tx_kick_off_and_wait(struct rtw89_dev *rtwdev, struct sk_buff *skb,
7381 int qsel, unsigned int timeout);
7382 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev,
7383 struct rtw89_tx_desc_info *desc_info,
7384 void *txdesc);
7385 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev,
7386 struct rtw89_tx_desc_info *desc_info,
7387 void *txdesc);
7388 void rtw89_core_fill_txdesc_v2(struct rtw89_dev *rtwdev,
7389 struct rtw89_tx_desc_info *desc_info,
7390 void *txdesc);
7391 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev,
7392 struct rtw89_tx_desc_info *desc_info,
7393 void *txdesc);
7394 void rtw89_core_fill_txdesc_fwcmd_v2(struct rtw89_dev *rtwdev,
7395 struct rtw89_tx_desc_info *desc_info,
7396 void *txdesc);
7397 void rtw89_core_rx(struct rtw89_dev *rtwdev,
7398 struct rtw89_rx_desc_info *desc_info,
7399 struct sk_buff *skb);
7400 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev,
7401 struct rtw89_rx_desc_info *desc_info,
7402 u8 *data, u32 data_offset);
7403 void rtw89_core_query_rxdesc_v2(struct rtw89_dev *rtwdev,
7404 struct rtw89_rx_desc_info *desc_info,
7405 u8 *data, u32 data_offset);
7406 void rtw89_core_napi_start(struct rtw89_dev *rtwdev);
7407 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev);
7408 int rtw89_core_napi_init(struct rtw89_dev *rtwdev);
7409 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev);
7410 int rtw89_core_sta_link_add(struct rtw89_dev *rtwdev,
7411 struct rtw89_vif_link *rtwvif_link,
7412 struct rtw89_sta_link *rtwsta_link);
7413 int rtw89_core_sta_link_assoc(struct rtw89_dev *rtwdev,
7414 struct rtw89_vif_link *rtwvif_link,
7415 struct rtw89_sta_link *rtwsta_link);
7416 int rtw89_core_sta_link_disassoc(struct rtw89_dev *rtwdev,
7417 struct rtw89_vif_link *rtwvif_link,
7418 struct rtw89_sta_link *rtwsta_link);
7419 int rtw89_core_sta_link_disconnect(struct rtw89_dev *rtwdev,
7420 struct rtw89_vif_link *rtwvif_link,
7421 struct rtw89_sta_link *rtwsta_link);
7422 int rtw89_core_sta_link_remove(struct rtw89_dev *rtwdev,
7423 struct rtw89_vif_link *rtwvif_link,
7424 struct rtw89_sta_link *rtwsta_link);
7425 void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev,
7426 struct ieee80211_sta *sta,
7427 struct cfg80211_tid_config *tid_config);
7428 void rtw89_core_rfkill_poll(struct rtw89_dev *rtwdev, bool force);
7429 void rtw89_check_quirks(struct rtw89_dev *rtwdev, const struct dmi_system_id *quirks);
7430 int rtw89_core_init(struct rtw89_dev *rtwdev);
7431 void rtw89_core_deinit(struct rtw89_dev *rtwdev);
7432 int rtw89_core_register(struct rtw89_dev *rtwdev);
7433 void rtw89_core_unregister(struct rtw89_dev *rtwdev);
7434 struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device,
7435 u32 bus_data_size,
7436 const struct rtw89_chip_info *chip,
7437 const struct rtw89_chip_variant *variant);
7438 void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev);
7439 u8 rtw89_acquire_mac_id(struct rtw89_dev *rtwdev);
7440 void rtw89_release_mac_id(struct rtw89_dev *rtwdev, u8 mac_id);
7441 void rtw89_init_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
7442 u8 mac_id, u8 port);
7443 void rtw89_init_sta(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
7444 struct rtw89_sta *rtwsta, u8 mac_id);
7445 struct rtw89_vif_link *rtw89_vif_set_link(struct rtw89_vif *rtwvif,
7446 unsigned int link_id);
7447 void rtw89_vif_unset_link(struct rtw89_vif *rtwvif, unsigned int link_id);
7448 struct rtw89_sta_link *rtw89_sta_set_link(struct rtw89_sta *rtwsta,
7449 unsigned int link_id);
7450 void rtw89_sta_unset_link(struct rtw89_sta *rtwsta, unsigned int link_id);
7451 void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev);
7452 const struct rtw89_6ghz_span *
7453 rtw89_get_6ghz_span(struct rtw89_dev *rtwdev, u32 center_freq);
7454 void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef);
7455 void rtw89_get_channel_params(const struct cfg80211_chan_def *chandef,
7456 struct rtw89_chan *chan);
7457 int rtw89_set_channel(struct rtw89_dev *rtwdev);
7458 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size);
7459 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit);
7460 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits);
7461 int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev,
7462 struct rtw89_sta_link *rtwsta_link, u8 tid,
7463 u8 *cam_idx);
7464 int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev,
7465 struct rtw89_sta_link *rtwsta_link, u8 tid,
7466 u8 *cam_idx);
7467 void rtw89_core_free_sta_pending_ba(struct rtw89_dev *rtwdev,
7468 struct ieee80211_sta *sta);
7469 void rtw89_core_free_sta_pending_forbid_ba(struct rtw89_dev *rtwdev,
7470 struct ieee80211_sta *sta);
7471 void rtw89_core_free_sta_pending_roc_tx(struct rtw89_dev *rtwdev,
7472 struct ieee80211_sta *sta);
7473 void rtw89_vif_type_mapping(struct rtw89_vif_link *rtwvif_link, bool assoc);
7474 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev);
7475 void rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev,
7476 struct rtw89_vif_link *rtwvif_link);
7477 bool rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate, u16 *bitrate);
7478 int rtw89_regd_setup(struct rtw89_dev *rtwdev);
7479 int rtw89_regd_init_hint(struct rtw89_dev *rtwdev);
7480 const char *rtw89_regd_get_string(enum rtw89_regulation_type regd);
7481 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev,
7482 struct rtw89_traffic_stats *stats);
7483 int rtw89_wait_for_cond(struct rtw89_wait_info *wait, unsigned int cond);
7484 void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond,
7485 const struct rtw89_completion_data *data);
7486 int rtw89_core_start(struct rtw89_dev *rtwdev);
7487 void rtw89_core_stop(struct rtw89_dev *rtwdev);
7488 void rtw89_core_update_beacon_work(struct wiphy *wiphy, struct wiphy_work *work);
7489 void rtw89_core_csa_beacon_work(struct wiphy *wiphy, struct wiphy_work *work);
7490 int rtw89_core_send_nullfunc(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
7491 bool qos, bool ps, int timeout);
7492 void rtw89_roc_work(struct wiphy *wiphy, struct wiphy_work *work);
7493 void rtw89_roc_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
7494 void rtw89_roc_end(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
7495 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
7496 const u8 *mac_addr, bool hw_scan);
7497 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev,
7498 struct rtw89_vif_link *rtwvif_link, bool hw_scan);
7499 int rtw89_reg_6ghz_recalc(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
7500 bool active);
7501 void rtw89_core_update_p2p_ps(struct rtw89_dev *rtwdev,
7502 struct rtw89_vif_link *rtwvif_link,
7503 struct ieee80211_bss_conf *bss_conf);
7504 void rtw89_core_ntfy_btc_event(struct rtw89_dev *rtwdev, enum rtw89_btc_hmsg event);
7505 int rtw89_core_mlsr_switch(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
7506 unsigned int link_id);
7507
7508 #if defined(__linux__)
7509 #define rtw89_static_assert(_x) static_assert(_x)
7510 #elif defined(__FreeBSD__)
7511 #define rtw89_static_assert(_x) _Static_assert(_x, "bad array size")
7512 #endif
7513
7514 #endif
7515