1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2011-2013 Qlogic Corporation 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 18 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 21 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29 /* 30 * File: qla_hw.h 31 * Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656. 32 */ 33 #ifndef _QLA_HW_H_ 34 #define _QLA_HW_H_ 35 36 #define Q8_MAX_NUM_MULTICAST_ADDRS 128 37 #define Q8_MAC_ADDR_LEN 6 38 39 /* 40 * Firmware Interface 41 */ 42 43 /* 44 * Command Response Interface - Commands 45 */ 46 typedef struct qla_cdrp { 47 uint32_t cmd; 48 uint32_t cmd_arg1; 49 uint32_t cmd_arg2; 50 uint32_t cmd_arg3; 51 uint32_t rsp; 52 uint32_t rsp_arg1; 53 uint32_t rsp_arg2; 54 uint32_t rsp_arg3; 55 } qla_cdrp_t; 56 57 #define Q8_CMD_RD_MAX_RDS_PER_CNTXT 0x80000002 58 #define Q8_CMD_RD_MAX_SDS_PER_CNTXT 0x80000003 59 #define Q8_CMD_RD_MAX_RULES_PER_CNTXT 0x80000004 60 #define Q8_CMD_RD_MAX_RX_CNTXT 0x80000005 61 #define Q8_CMD_RD_MAX_TX_CNTXT 0x80000006 62 #define Q8_CMD_CREATE_RX_CNTXT 0x80000007 63 #define Q8_CMD_DESTROY_RX_CNTXT 0x80000008 64 #define Q8_CMD_CREATE_TX_CNTXT 0x80000009 65 #define Q8_CMD_DESTROY_TX_CNTXT 0x8000000A 66 #define Q8_CMD_SETUP_STATS 0x8000000E 67 #define Q8_CMD_GET_STATS 0x8000000F 68 #define Q8_CMD_DELETE_STATS 0x80000010 69 #define Q8_CMD_GEN_INT 0x80000011 70 #define Q8_CMD_SET_MTU 0x80000012 71 #define Q8_CMD_GET_FLOW_CNTRL 0x80000016 72 #define Q8_CMD_SET_FLOW_CNTRL 0x80000017 73 #define Q8_CMD_RD_MAX_MTU 0x80000018 74 #define Q8_CMD_RD_MAX_LRO 0x80000019 75 76 /* 77 * Command Response Interface - Response 78 */ 79 #define Q8_RSP_SUCCESS 0x00000000 80 #define Q8_RSP_NO_HOST_MEM 0x00000001 81 #define Q8_RSP_NO_HOST_RSRC 0x00000002 82 #define Q8_RSP_NO_CARD_CRB 0x00000003 83 #define Q8_RSP_NO_CARD_MEM 0x00000004 84 #define Q8_RSP_NO_CARD_RSRC 0x00000005 85 #define Q8_RSP_INVALID_ARGS 0x00000006 86 #define Q8_RSP_INVALID_ACTION 0x00000007 87 #define Q8_RSP_INVALID_STATE 0x00000008 88 #define Q8_RSP_NOT_SUPPORTED 0x00000009 89 #define Q8_RSP_NOT_PERMITTED 0x0000000A 90 #define Q8_RSP_NOT_READY 0x0000000B 91 #define Q8_RSP_DOES_NOT_EXIST 0x0000000C 92 #define Q8_RSP_ALREADY_EXISTS 0x0000000D 93 #define Q8_RSP_BAD_SIGNATURE 0x0000000E 94 #define Q8_RSP_CMD_NOT_IMPLEMENTED 0x0000000F 95 #define Q8_RSP_CMD_INVALID 0x00000010 96 #define Q8_RSP_TIMEOUT 0x00000011 97 98 /* 99 * Transmit Related Definitions 100 */ 101 102 /* 103 * Transmit Context - Q8_CMD_CREATE_TX_CNTXT Command Configuration Data 104 */ 105 106 typedef struct _q80_tx_cntxt_req { 107 uint64_t rsp_dma_addr; /* rsp from firmware is DMA'ed here */ 108 uint64_t cmd_cons_dma_addr; 109 uint64_t rsrvd0; 110 111 uint32_t caps[4]; /* capabilities - bit vector*/ 112 #define CNTXT_CAP0_BASEFW 0x0001 113 #define CNTXT_CAP0_LEGACY_MN 0x0004 114 #define CNTXT_CAP0_LSO 0x0040 115 116 uint32_t intr_mode; /* Interrupt Mode */ 117 #define CNTXT_INTR_MODE_UNIQUE 0x0000 118 #define CNTXT_INTR_MODE_SHARED 0x0001 119 120 uint64_t rsrvd1; 121 uint16_t msi_index; 122 uint16_t rsrvd2; 123 uint64_t phys_addr; /* physical address of transmit ring 124 * in system memory */ 125 uint32_t num_entries; /* number of entries in transmit ring */ 126 uint8_t rsrvd3[128]; 127 } __packed q80_tx_cntxt_req_t; /* 188 bytes total */ 128 129 /* 130 * Transmit Context - Response from Firmware to Q8_CMD_CREATE_TX_CNTXT 131 */ 132 133 typedef struct _q80_tx_cntxt_rsp { 134 uint32_t cntxt_state; /* starting state */ 135 #define CNTXT_STATE_ALLOCATED_NOT_ACTIVE 0x0001 136 #define CNTXT_STATE_ACTIVE 0x0002 137 #define CNTXT_STATE_QUIESCED 0x0004 138 139 uint16_t cntxt_id; /* handle for context */ 140 uint8_t phys_port_id; /* physical id of port */ 141 uint8_t virt_port_id; /* virtual or logical id of port */ 142 uint32_t producer_reg; /* producer register for transmit ring */ 143 uint32_t intr_mask_reg; /* interrupt mask register */ 144 uint8_t rsrvd[128]; 145 } __packed q80_tx_cntxt_rsp_t; /* 144 bytes */ 146 147 /* 148 * Transmit Command Descriptor 149 * These commands are issued on the Transmit Ring associated with a Transmit 150 * context 151 */ 152 typedef struct _q80_tx_cmd { 153 uint8_t tcp_hdr_off; /* TCP Header Offset */ 154 uint8_t ip_hdr_off; /* IP Header Offset */ 155 uint16_t flags_opcode; /* Bits 0-6: flags; 7-12: opcode */ 156 157 /* flags field */ 158 #define Q8_TX_CMD_FLAGS_MULTICAST 0x01 159 #define Q8_TX_CMD_FLAGS_LSO_TSO 0x02 160 #define Q8_TX_CMD_FLAGS_VLAN_TAGGED 0x10 161 #define Q8_TX_CMD_FLAGS_HW_VLAN_ID 0x40 162 163 /* opcode field */ 164 #define Q8_TX_CMD_OP_XMT_UDP_CHKSUM_IPV6 (0xC << 7) 165 #define Q8_TX_CMD_OP_XMT_TCP_CHKSUM_IPV6 (0xB << 7) 166 #define Q8_TX_CMD_OP_XMT_TCP_LSO_IPV6 (0x6 << 7) 167 #define Q8_TX_CMD_OP_XMT_TCP_LSO (0x5 << 7) 168 #define Q8_TX_CMD_OP_XMT_UDP_CHKSUM (0x3 << 7) 169 #define Q8_TX_CMD_OP_XMT_TCP_CHKSUM (0x2 << 7) 170 #define Q8_TX_CMD_OP_XMT_ETHER (0x1 << 7) 171 172 uint8_t n_bufs; /* # of data segs in data buffer */ 173 uint8_t data_len_lo; /* data length lower 8 bits */ 174 uint16_t data_len_hi; /* data length upper 16 bits */ 175 176 uint64_t buf2_addr; /* buffer 2 address */ 177 178 uint16_t rsrvd0; 179 uint16_t mss; /* MSS for this packet */ 180 uint8_t port_cntxtid; /* Bits 7-4: ContextId; 3-0: reserved */ 181 182 #define Q8_TX_CMD_PORT_CNXTID(c_id) ((c_id & 0xF) << 4) 183 184 uint8_t total_hdr_len; /* MAC+IP+TCP Header Length for LSO */ 185 uint16_t rsrvd1; 186 187 uint64_t buf3_addr; /* buffer 3 address */ 188 uint64_t buf1_addr; /* buffer 1 address */ 189 190 uint16_t buf1_len; /* length of buffer 1 */ 191 uint16_t buf2_len; /* length of buffer 2 */ 192 uint16_t buf3_len; /* length of buffer 3 */ 193 uint16_t buf4_len; /* length of buffer 4 */ 194 195 uint64_t buf4_addr; /* buffer 4 address */ 196 197 uint32_t rsrvd2; 198 uint16_t rsrvd3; 199 uint16_t vlan_tci; /* VLAN TCI when hw tagging is enabled*/ 200 201 } __packed q80_tx_cmd_t; /* 64 bytes */ 202 203 #define Q8_TX_CMD_MAX_SEGMENTS 4 204 #define Q8_TX_CMD_TSO_ALIGN 2 205 #define Q8_TX_MAX_SEGMENTS 14 206 207 /* 208 * Receive Related Definitions 209 */ 210 /* 211 * Receive Context - Q8_CMD_CREATE_RX_CNTXT Command Configuration Data 212 */ 213 214 typedef struct _q80_rq_sds_ring { 215 uint64_t phys_addr; /* physical addr of status ring in system memory */ 216 uint32_t size; /* number of entries in status ring */ 217 uint16_t msi_index; 218 uint16_t rsrvd; 219 } __packed q80_rq_sds_ring_t; /* 16 bytes */ 220 221 typedef struct _q80_rq_rds_ring { 222 uint64_t phys_addr; /* physical addr of rcv ring in system memory */ 223 uint64_t buf_size; /* packet buffer size */ 224 uint32_t size; /* number of entries in ring */ 225 uint32_t rsrvd; 226 } __packed q80_rq_rds_ring_t; /* 24 bytes */ 227 228 typedef struct _q80_rq_rcv_cntxt { 229 uint64_t rsp_dma_addr; /* rsp from firmware is DMA'ed here */ 230 uint32_t caps[4]; /* bit vector */ 231 #define CNTXT_CAP0_JUMBO 0x0080 /* Contiguous Jumbo buffers*/ 232 #define CNTXT_CAP0_LRO 0x0100 233 #define CNTXT_CAP0_HW_LRO 0x0800 /* HW LRO */ 234 235 uint32_t intr_mode; /* same as q80_tx_cntxt_req_t */ 236 uint32_t rds_intr_mode; /* same as q80_tx_cntxt_req_t */ 237 238 uint32_t rds_ring_offset; /* rds configuration relative to data[0] */ 239 uint32_t sds_ring_offset; /* sds configuration relative to data[0] */ 240 241 uint16_t num_rds_rings; 242 uint16_t num_sds_rings; 243 244 uint8_t rsrvd1[132]; 245 } __packed q80_rq_rcv_cntxt_t; /* 176 bytes header + rds + sds ring rqsts */ 246 247 /* 248 * Receive Context - Response from Firmware to Q8_CMD_CREATE_RX_CNTXT 249 */ 250 251 typedef struct _q80_rsp_rds_ring { 252 uint32_t producer_reg; 253 uint32_t rsrvd; 254 } __packed q80_rsp_rds_ring_t; /* 8 bytes */ 255 256 typedef struct _q80_rsp_sds_ring { 257 uint32_t consumer_reg; 258 uint32_t intr_mask_reg; 259 } __packed q80_rsp_sds_ring_t; /* 8 bytes */ 260 261 typedef struct _q80_rsp_rcv_cntxt { 262 uint32_t rds_ring_offset; /* rds configuration relative to data[0] */ 263 uint32_t sds_ring_offset; /* sds configuration relative to data[0] */ 264 265 uint32_t cntxt_state; /* starting state */ 266 uint32_t funcs_per_port; /* number of PCI functions sharing each port */ 267 268 uint16_t num_rds_rings; 269 uint16_t num_sds_rings; 270 271 uint16_t cntxt_id; /* handle for context */ 272 273 uint8_t phys_port; /* physical id of port */ 274 uint8_t virt_port; /* virtual or logical id of port */ 275 276 uint8_t rsrvd[128]; 277 uint8_t data[0]; 278 } __packed q80_rsp_rcv_cntxt_t; /* 152 bytes header + rds + sds ring rspncs */ 279 280 /* 281 * Note: 282 * Transmit Context 283 * 188 (rq) + 144 (rsp) = 332 bytes are required 284 * 285 * Receive Context 286 * 1 RDS and 1 SDS rings: (16+24+176)+(8+8+152) = 384 bytes 287 * 288 * 3 RDS and 4 SDS rings: (((16+24)*3)+176) + (((8+8)*4)+152) = 289 * = 296 + 216 = 512 bytes 290 * Clearly this within the minimum PAGE size of most O.S platforms 291 * (typically 4Kbytes). Hence it is simpler to simply allocate one PAGE 292 * and then carve out space for each context. It is also a good idea to 293 * to throw in the shadown register for the consumer index of the transmit 294 * ring in this PAGE. 295 */ 296 297 /* 298 * Receive Descriptor corresponding to each entry in the receive ring 299 */ 300 typedef struct _q80_rcv_desc { 301 uint16_t handle; 302 uint16_t rsrvd; 303 uint32_t buf_size; /* buffer size in bytes */ 304 uint64_t buf_addr; /* physical address of buffer */ 305 } __packed q80_recv_desc_t; 306 307 /* 308 * Status Descriptor corresponding to each entry in the Status ring 309 */ 310 typedef struct _q80_stat_desc { 311 uint64_t data[2]; 312 } __packed q80_stat_desc_t; 313 314 /* 315 * definitions for data[0] field of Status Descriptor 316 */ 317 #define Q8_STAT_DESC_OWNER(data) ((data >> 56) & 0x3) 318 #define Q8_STAT_DESC_OWNER_HOST 0x1 319 #define Q8_STAT_DESC_OWNER_FW 0x2 320 321 #define Q8_STAT_DESC_OWNER_MASK (((uint64_t)0x3) << 56) 322 #define Q8_STAT_DESC_SET_OWNER(owner) (uint64_t)(((uint64_t)owner) << 56) 323 324 #define Q8_STAT_DESC_OPCODE(data) ((data >> 58) & 0x003F) 325 #define Q8_STAT_DESC_OPCODE_SYN_OFFLOAD 0x03 326 #define Q8_STAT_DESC_OPCODE_RCV_PKT 0x04 327 #define Q8_STAT_DESC_OPCODE_CTRL_MSG 0x05 328 #define Q8_STAT_DESC_OPCODE_LRO_PKT 0x12 329 330 /* 331 * definitions for data[0] field of Status Descriptor for standard frames 332 * status descriptor opcode equals 0x04 333 */ 334 #define Q8_STAT_DESC_PORT(data) ((data) & 0x000F) 335 #define Q8_STAT_DESC_STATUS(data) ((data >> 4) & 0x000F) 336 #define Q8_STAT_DESC_STATUS_NO_CHKSUM 0x01 337 #define Q8_STAT_DESC_STATUS_CHKSUM_OK 0x02 338 #define Q8_STAT_DESC_STATUS_CHKSUM_ERR 0x03 339 340 #define Q8_STAT_DESC_TYPE(data) ((data >> 8) & 0x000F) 341 #define Q8_STAT_DESC_TOTAL_LENGTH(data) ((data >> 12) & 0xFFFF) 342 #define Q8_STAT_DESC_HANDLE(data) ((data >> 28) & 0xFFFF) 343 #define Q8_STAT_DESC_PROTOCOL(data) ((data >> 44) & 0x000F) 344 #define Q8_STAT_DESC_L2_OFFSET(data) ((data >> 48) & 0x001F) 345 #define Q8_STAT_DESC_COUNT(data) ((data >> 53) & 0x0007) 346 347 /* 348 * definitions for data[0-1] fields of Status Descriptor for LRO 349 * status descriptor opcode equals 0x05 350 */ 351 /* definitions for data[0] field */ 352 #define Q8_LRO_STAT_DESC_HANDLE(data) ((data) & 0xFFFF) 353 #define Q8_LRO_STAT_DESC_PAYLOAD_LENGTH(data) ((data >> 16) & 0xFFFF) 354 #define Q8_LRO_STAT_DESC_L2_OFFSET(data) ((data >> 32) & 0xFF) 355 #define Q8_LRO_STAT_DESC_L4_OFFSET(data) ((data >> 40) & 0xFF) 356 #define Q8_LRO_STAT_DESC_TS_PRESENT(data) ((data >> 48) & 0x1) 357 #define Q8_LRO_STAT_DESC_TYPE(data) ((data >> 49) & 0x7) 358 #define Q8_LRO_STAT_DESC_PUSH_BIT(data) ((data >> 52) & 0x1) 359 360 /* definitions for data[1] field */ 361 #define Q8_LRO_STAT_DESC_SEQ_NUM(data) (uint32_t)(data) 362 363 /** Driver Related Definitions Begin **/ 364 365 #define MAX_RDS_RINGS 2 /* Max# of Receive Descriptor Rings */ 366 #define MAX_SDS_RINGS 4 /* Max# of Status Descriptor Rings */ 367 #define TX_SMALL_PKT_SIZE 128 /* size in bytes of small packets */ 368 369 /* The number of descriptors should be a power of 2 */ 370 #define NUM_TX_DESCRIPTORS 2048 371 #define NUM_RX_DESCRIPTORS 8192 372 //#define NUM_RX_JUMBO_DESCRIPTORS 1024 373 #define NUM_RX_JUMBO_DESCRIPTORS 2048 374 //#define NUM_STATUS_DESCRIPTORS 8192 375 #define NUM_STATUS_DESCRIPTORS 2048 376 377 typedef struct _q80_rcv_cntxt_req { 378 q80_rq_rcv_cntxt_t rx_req; 379 q80_rq_rds_ring_t rds_req[MAX_RDS_RINGS]; 380 q80_rq_sds_ring_t sds_req[MAX_SDS_RINGS]; 381 } __packed q80_rcv_cntxt_req_t; 382 383 typedef struct _q80_rcv_cntxt_rsp { 384 q80_rsp_rcv_cntxt_t rx_rsp; 385 q80_rsp_rds_ring_t rds_rsp[MAX_RDS_RINGS]; 386 q80_rsp_sds_ring_t sds_rsp[MAX_SDS_RINGS]; 387 } __packed q80_rcv_cntxt_rsp_t; 388 389 /* 390 * structure describing various dma buffers 391 */ 392 #define RDS_RING_INDEX_NORMAL 0 393 #define RDS_RING_INDEX_JUMBO 1 394 395 typedef struct qla_dmabuf { 396 volatile struct { 397 uint32_t tx_ring :1, 398 rds_ring :1, 399 sds_ring :1, 400 context :1; 401 } flags; 402 403 qla_dma_t tx_ring; 404 qla_dma_t rds_ring[MAX_RDS_RINGS]; 405 qla_dma_t sds_ring[MAX_SDS_RINGS]; 406 qla_dma_t context; 407 } qla_dmabuf_t; 408 409 /** Driver Related Definitions End **/ 410 411 /* 412 * Firmware Control Descriptor 413 */ 414 typedef struct _qla_fw_cds_hdr { 415 uint64_t cmd; 416 #define Q8_FWCD_CNTRL_REQ (0x13 << 23) 417 uint8_t opcode; 418 uint8_t cookie; 419 uint16_t cntxt_id; 420 uint8_t response; 421 #define Q8_FW_CDS_HDR_COMPLETION 0x1 422 uint16_t rsrvd; 423 uint8_t sub_opcode; 424 } __packed qla_fw_cds_hdr_t; 425 426 /* 427 * definitions for opcode in qla_fw_cds_hdr_t 428 */ 429 #define Q8_FWCD_OPCODE_CONFIG_RSS 0x01 430 #define Q8_FWCD_OPCODE_CONFIG_RSS_TABLE 0x02 431 #define Q8_FWCD_OPCODE_CONFIG_INTR_COALESCING 0x03 432 #define Q8_FWCD_OPCODE_CONFIG_LED 0x04 433 #define Q8_FWCD_OPCODE_CONFIG_MAC_ADDR 0x06 434 #define Q8_FWCD_OPCODE_LRO_FLOW 0x07 435 #define Q8_FWCD_OPCODE_GET_SNMP_STATS 0x08 436 #define Q8_FWCD_OPCODE_CONFIG_MAC_RCV_MODE 0x0C 437 #define Q8_FWCD_OPCODE_STATISTICS 0x10 438 #define Q8_FWCD_OPCODE_CONFIG_IPADDR 0x12 439 #define Q8_FWCD_OPCODE_CONFIG_LOOPBACK 0x13 440 #define Q8_FWCD_OPCODE_LINK_EVENT_REQ 0x15 441 #define Q8_FWCD_OPCODE_CONFIG_BRIDGING 0x17 442 #define Q8_FWCD_OPCODE_CONFIG_LRO 0x18 443 444 /* 445 * Configure RSS 446 */ 447 typedef struct _qla_fw_cds_config_rss { 448 qla_fw_cds_hdr_t hdr; 449 uint8_t hash_type; 450 #define Q8_FWCD_RSS_HASH_TYPE_IPV4_TCP (0x2 << 4) 451 #define Q8_FWCD_RSS_HASH_TYPE_IPV4_IP (0x1 << 4) 452 #define Q8_FWCD_RSS_HASH_TYPE_IPV4_TCP_IP (0x3 << 4) 453 #define Q8_FWCD_RSS_HASH_TYPE_IPV6_TCP (0x2 << 6) 454 #define Q8_FWCD_RSS_HASH_TYPE_IPV6_IP (0x1 << 6) 455 #define Q8_FWCD_RSS_HASH_TYPE_IPV6_TCP_IP (0x3 << 6) 456 457 uint8_t flags; 458 #define Q8_FWCD_RSS_FLAGS_ENABLE_RSS 0x1 459 #define Q8_FWCD_RSS_FLAGS_USE_IND_TABLE 0x2 460 uint8_t rsrvd[4]; 461 uint16_t ind_tbl_mask; 462 uint64_t rss_key[5]; 463 } __packed qla_fw_cds_config_rss_t; 464 465 /* 466 * Configure RSS Table 467 */ 468 typedef struct _qla_fw_cds_config_rss_table { 469 qla_fw_cds_hdr_t hdr; 470 uint64_t index; 471 uint8_t table[40]; 472 } __packed qla_fw_cds_config_rss_table_t; 473 474 /* 475 * Configure Interrupt Coalescing 476 */ 477 typedef struct _qla_fw_cds_config_intr_coalesc { 478 qla_fw_cds_hdr_t hdr; 479 uint16_t rsrvd0; 480 uint16_t rsrvd1; 481 uint16_t flags; 482 uint16_t rsrvd2; 483 uint64_t rsrvd3; 484 uint16_t max_rcv_pkts; 485 uint16_t max_rcv_usecs; 486 uint16_t max_snd_pkts; 487 uint16_t max_snd_usecs; 488 uint64_t rsrvd4; 489 uint64_t rsrvd5; 490 uint32_t usecs_to; 491 uint8_t timer_type; 492 #define Q8_FWCMD_INTR_COALESC_TIMER_NONE 0x00 493 #define Q8_FWCMD_INTR_COALESC_TIMER_ONCE 0x01 494 #define Q8_FWCMD_INTR_COALESC_TIMER_PERIODIC 0x02 495 496 uint8_t sds_ring_bitmask; 497 #define Q8_FWCMD_INTR_COALESC_SDS_RING_0 0x01 498 #define Q8_FWCMD_INTR_COALESC_SDS_RING_1 0x02 499 #define Q8_FWCMD_INTR_COALESC_SDS_RING_2 0x04 500 #define Q8_FWCMD_INTR_COALESC_SDS_RING_3 0x08 501 502 uint16_t rsrvd6; 503 } __packed qla_fw_cds_config_intr_coalesc_t; 504 505 /* 506 * Configure LED Parameters 507 */ 508 typedef struct _qla_fw_cds_config_led { 509 qla_fw_cds_hdr_t hdr; 510 uint32_t cntxt_id; 511 uint32_t blink_rate; 512 uint32_t blink_state; 513 uint32_t rsrvd; 514 } __packed qla_fw_cds_config_led_t; 515 516 /* 517 * Configure MAC Address 518 */ 519 typedef struct _qla_fw_cds_config_mac_addr { 520 qla_fw_cds_hdr_t hdr; 521 uint8_t cmd; 522 #define Q8_FWCD_ADD_MAC_ADDR 0x1 523 #define Q8_FWCD_DEL_MAC_ADDR 0x2 524 uint8_t rsrvd; 525 uint8_t mac_addr[6]; 526 } __packed qla_fw_cds_config_mac_addr_t; 527 528 /* 529 * Configure Add/Delete LRO 530 */ 531 typedef struct _qla_fw_cds_config_lro { 532 qla_fw_cds_hdr_t hdr; 533 uint32_t dst_ip_addr; 534 uint32_t src_ip_addr; 535 uint16_t dst_tcp_port; 536 uint16_t src_tcp_port; 537 uint8_t ipv6; 538 uint8_t time_stamp; 539 uint16_t rsrvd; 540 uint32_t rss_hash; 541 uint32_t host_handle; 542 } __packed qla_fw_cds_config_lro_t; 543 544 /* 545 * Get SNMP Statistics 546 */ 547 typedef struct _qla_fw_cds_get_snmp { 548 qla_fw_cds_hdr_t hdr; 549 uint64_t phys_addr; 550 uint16_t size; 551 uint16_t cntxt_id; 552 uint32_t rsrvd; 553 } __packed qla_fw_cds_get_snmp_t; 554 555 typedef struct _qla_snmp_stats { 556 uint64_t jabber_state; 557 uint64_t false_carrier; 558 uint64_t rsrvd; 559 uint64_t mac_cntrl; 560 uint64_t align_errors; 561 uint64_t chksum_errors; 562 uint64_t oversize_frames; 563 uint64_t tx_errors; 564 uint64_t mac_rcv_errors; 565 uint64_t phy_rcv_errors; 566 uint64_t rcv_pause; 567 uint64_t tx_pause; 568 } __packed qla_snmp_stats_t; 569 570 /* 571 * Enable Link Event Requests 572 */ 573 typedef struct _qla_link_event_req { 574 qla_fw_cds_hdr_t hdr; 575 uint8_t enable; 576 uint8_t get_clnk_params; 577 uint8_t pad[6]; 578 } __packed qla_link_event_req_t; 579 580 /* 581 * Set MAC Receive Mode 582 */ 583 typedef struct _qla_set_mac_rcv_mode { 584 qla_fw_cds_hdr_t hdr; 585 586 uint32_t mode; 587 #define Q8_MAC_RCV_RESET_PROMISC_ALLMULTI 0x00 588 #define Q8_MAC_RCV_ENABLE_PROMISCUOUS 0x01 589 #define Q8_MAC_RCV_ENABLE_ALLMULTI 0x02 590 591 uint8_t pad[4]; 592 } __packed qla_set_mac_rcv_mode_t; 593 594 /* 595 * Configure IP Address 596 */ 597 typedef struct _qla_config_ipv4 { 598 qla_fw_cds_hdr_t hdr; 599 600 uint64_t cmd; 601 #define Q8_CONFIG_CMD_IP_ENABLE 0x02 602 #define Q8_CONFIG_CMD_IP_DISABLE 0x03 603 604 uint64_t ipv4_addr; 605 } __packed qla_config_ipv4_t; 606 607 /* 608 * Configure LRO 609 */ 610 typedef struct _qla_config_lro { 611 qla_fw_cds_hdr_t hdr; 612 613 uint64_t cmd; 614 #define Q8_CONFIG_LRO_ENABLE 0x08 615 } __packed qla_config_lro_t; 616 617 /* 618 * Control Messages Received on SDS Ring 619 */ 620 /* Header */ 621 typedef struct _qla_cntrl_msg_hdr { 622 uint16_t rsrvd0; 623 uint16_t err_code; 624 uint8_t rsp_type; 625 uint8_t comp_id; 626 uint16_t tag; 627 #define Q8_CTRL_MSG_TAG_DESC_COUNT_MASK (0x7 << 5) 628 #define Q8_CTRL_MSG_TAG_OWNER_MASK (0x3 << 8) 629 #define Q8_CTRL_MSG_TAG_OPCODE_MASK (0x3F << 10) 630 } __packed qla_cntrl_msg_hdr_t; 631 632 /* 633 * definitions for rsp_type in qla_cntrl_msg_hdr_t 634 */ 635 #define Q8_CTRL_CONFIG_MAC_RSP 0x85 636 #define Q8_CTRL_LRO_FLOW_DELETE_RSP 0x86 637 #define Q8_CTRL_LRO_FLOW_ADD_FAILURE_RSP 0x87 638 #define Q8_CTRL_GET_SNMP_STATS_RSP 0x88 639 #define Q8_CTRL_GET_NETWORK_STATS_RSP 0x8C 640 #define Q8_CTRL_LINK_EVENT_NOTIFICATION 0x8D 641 642 /* 643 * Configure MAC Response 644 */ 645 typedef struct _qla_config_mac_rsp { 646 uint32_t rval; 647 uint32_t rsrvd; 648 } __packed qla_config_mac_rsp_t; 649 650 /* 651 * LRO Flow Response (can be LRO Flow Delete and LRO Flow Add Failure) 652 */ 653 typedef struct _qla_lro_flow_rsp { 654 uint32_t handle; 655 uint32_t rss_hash; 656 uint32_t dst_ip; 657 uint32_t src_ip; 658 uint16_t dst_tcp_port; 659 uint16_t src_tcp_port; 660 uint8_t ipv6; 661 uint8_t rsrvd0; 662 uint16_t rsrvd1; 663 } __packed qla_lro_flow_rsp_t; 664 665 /* 666 * Get SNMP Statistics Response 667 */ 668 typedef struct _qla_get_snmp_stats_rsp { 669 uint64_t rsrvd; 670 } __packed qla_get_snmp_stats_rsp_t; 671 672 /* 673 * Get Network Statistics Response 674 */ 675 typedef struct _qla_get_net_stats_rsp { 676 uint64_t rsrvd; 677 } __packed qla_get_net_stats_rsp_t; 678 679 /* 680 * Link Event Notification 681 */ 682 typedef struct _qla_link_event { 683 uint32_t cable_oui; 684 uint16_t cable_length; 685 686 uint16_t link_speed; 687 #define Q8_LE_SPEED_MASK 0xFFF 688 #define Q8_LE_SPEED_10GBPS 0x710 689 #define Q8_LE_SPEED_1GBPS 0x3E8 690 #define Q8_LE_SPEED_100MBPS 0x064 691 #define Q8_LE_SPEED_10MBPS 0x00A 692 693 uint8_t link_up;/* 0 = down; else up */ 694 695 uint8_t mod_info; 696 #define Q8_LE_MI_MODULE_NOT_PRESENT 0x01 697 #define Q8_LE_MI_UNKNOWN_OPTICAL_MODULE 0x02 698 #define Q8_LE_MI_SR_LR_OPTICAL_MODULE 0x03 699 #define Q8_LE_MI_LRM_OPTICAL_MODULE 0x04 700 #define Q8_LE_MI_SFP_1G_MODULE 0x05 701 #define Q8_LE_MI_UNSUPPORTED_TWINAX 0x06 702 #define Q8_LE_MI_UNSUPPORTED_TWINAX_LENGTH 0x07 703 #define Q8_LE_MI_SUPPORTED_TWINAX 0x08 704 705 uint8_t fduplex; /* 1 = full duplex; 0 = half duplex */ 706 uint8_t autoneg; /* 1 = autoneg enable; 0 = disabled */ 707 uint32_t rsrvd; 708 } __packed qla_link_event_t; 709 710 typedef struct _qla_sds { 711 q80_stat_desc_t *sds_ring_base; /* start of sds ring */ 712 uint32_t sdsr_next; /* next entry in SDS ring to process */ 713 struct lro_ctrl lro; 714 void *rxb_free; 715 uint32_t rx_free; 716 void *rxjb_free; 717 uint32_t rxj_free; 718 volatile uint32_t rcv_active; 719 } qla_sds_t; 720 721 #define QL_FRAME_HDR_SIZE (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN +\ 722 sizeof (struct ip) + sizeof (struct tcphdr) + 16) 723 /* 724 * struct for storing hardware specific information for a given interface 725 */ 726 typedef struct _qla_hw { 727 struct { 728 uint32_t 729 lro :1, 730 init_tx_cnxt :1, 731 init_rx_cnxt :1, 732 fduplex :1, 733 autoneg :1, 734 link_up :1; 735 } flags; 736 737 uint16_t link_speed; 738 uint16_t cable_length; 739 uint16_t cable_oui; 740 uint8_t mod_info; 741 uint8_t rsrvd; 742 743 uint32_t max_rds_per_cntxt; 744 uint32_t max_sds_per_cntxt; 745 uint32_t max_rules_per_cntxt; 746 uint32_t max_rcv_cntxts; 747 uint32_t max_xmt_cntxts; 748 uint32_t max_mtu; 749 uint32_t max_lro; 750 751 uint8_t mac_addr[ETHER_ADDR_LEN]; 752 753 uint16_t num_rds_rings; 754 uint16_t num_sds_rings; 755 756 qla_dmabuf_t dma_buf; 757 758 /* Transmit Side */ 759 760 q80_tx_cmd_t *tx_ring_base; 761 762 q80_tx_cntxt_req_t *tx_cntxt_req; /* TX Context Request */ 763 bus_addr_t tx_cntxt_req_paddr; 764 765 q80_tx_cntxt_rsp_t *tx_cntxt_rsp; /* TX Context Response */ 766 bus_addr_t tx_cntxt_rsp_paddr; 767 768 uint32_t *tx_cons; /* tx consumer shadow reg */ 769 bus_addr_t tx_cons_paddr; 770 771 volatile uint32_t txr_free; /* # of free entries in tx ring */ 772 volatile uint32_t txr_next; /* # next available tx ring entry */ 773 volatile uint32_t txr_comp; /* index of last tx entry completed */ 774 775 uint32_t tx_prod_reg; 776 777 /* Receive Side */ 778 volatile uint32_t rx_next; /* next standard rcv ring to arm fw */ 779 volatile int32_t rxj_next; /* next jumbo rcv ring to arm fw */ 780 781 volatile int32_t rx_in; /* next standard rcv ring to add mbufs */ 782 volatile int32_t rxj_in; /* next jumbo rcv ring to add mbufs */ 783 784 q80_rcv_cntxt_req_t *rx_cntxt_req; /* Rcv Context Request */ 785 bus_addr_t rx_cntxt_req_paddr; 786 q80_rcv_cntxt_rsp_t *rx_cntxt_rsp; /* Rcv Context Response */ 787 bus_addr_t rx_cntxt_rsp_paddr; 788 789 qla_sds_t sds[MAX_SDS_RINGS]; 790 791 uint8_t frame_hdr[QL_FRAME_HDR_SIZE]; 792 } qla_hw_t; 793 794 #define QL_UPDATE_RDS_PRODUCER_INDEX(ha, i, val) \ 795 WRITE_REG32(ha, ((ha->hw.rx_cntxt_rsp)->rds_rsp[i].producer_reg +\ 796 0x1b2000), val) 797 798 #define QL_UPDATE_TX_PRODUCER_INDEX(ha, val) \ 799 WRITE_REG32(ha, (ha->hw.tx_prod_reg + 0x1b2000), val) 800 801 #define QL_UPDATE_SDS_CONSUMER_INDEX(ha, i, val) \ 802 WRITE_REG32(ha, ((ha->hw.rx_cntxt_rsp)->sds_rsp[i].consumer_reg +\ 803 0x1b2000), val) 804 805 #define QL_CLEAR_INTERRUPTS(ha) \ 806 if (ha->pci_func == 0) {\ 807 WRITE_REG32(ha, Q8_INT_TARGET_STATUS_F0, 0xFFFFFFFF);\ 808 } else {\ 809 WRITE_REG32(ha, Q8_INT_TARGET_STATUS_F1, 0xFFFFFFFF);\ 810 }\ 811 812 #define QL_ENABLE_INTERRUPTS(ha, sds_index) \ 813 {\ 814 q80_rsp_sds_ring_t *rsp_sds;\ 815 rsp_sds = &((ha->hw.rx_cntxt_rsp)->sds_rsp[sds_index]);\ 816 WRITE_REG32(ha, (rsp_sds->intr_mask_reg + 0x1b2000), 0x1);\ 817 } 818 819 #define QL_DISABLE_INTERRUPTS(ha, sds_index) \ 820 {\ 821 q80_rsp_sds_ring_t *rsp_sds;\ 822 rsp_sds = &((ha->hw.rx_cntxt_rsp)->sds_rsp[sds_index]);\ 823 WRITE_REG32(ha, (rsp_sds->intr_mask_reg + 0x1b2000), 0x0);\ 824 } 825 826 #define QL_BUFFER_ALIGN 16 827 828 #endif /* #ifndef _QLA_HW_H_ */ 829