1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2023 Intel Corporation 4 */ 5 6 #ifndef _XE_PCI_TYPES_H_ 7 #define _XE_PCI_TYPES_H_ 8 9 #include <linux/types.h> 10 11 struct xe_graphics_desc { 12 const char *name; 13 u8 ver; 14 u8 rel; 15 16 u8 dma_mask_size; /* available DMA address bits */ 17 u8 va_bits; 18 u8 vm_max_level; 19 u8 vram_flags; 20 21 u64 hw_engine_mask; /* hardware engines provided by graphics IP */ 22 23 u32 tile_mmio_ext_size; /* size of MMIO extension space, per-tile */ 24 25 u8 max_remote_tiles:2; 26 27 u8 has_asid:1; 28 u8 has_atomic_enable_pte_bit:1; 29 u8 has_flat_ccs:1; 30 u8 has_indirect_ring_state:1; 31 u8 has_range_tlb_invalidation:1; 32 u8 has_usm:1; 33 }; 34 35 struct xe_media_desc { 36 const char *name; 37 u8 ver; 38 u8 rel; 39 40 u64 hw_engine_mask; /* hardware engines provided by media IP */ 41 42 u8 has_indirect_ring_state:1; 43 }; 44 45 struct gmdid_map { 46 unsigned int ver; 47 const void *ip; 48 }; 49 50 #endif 51