1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
3 *
4 * Copyright (c) 2003 Peter Wemm.
5 * Copyright (c) 1990 The Regents of the University of California.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the name of the University nor the names of its contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * SUCH DAMAGE.
31 */
32
33 #include "opt_capsicum.h"
34 #include "opt_ktrace.h"
35
36 #include <sys/param.h>
37 #include <sys/systm.h>
38 #include <sys/capsicum.h>
39 #include <sys/kernel.h>
40 #include <sys/ktrace.h>
41 #include <sys/lock.h>
42 #include <sys/malloc.h>
43 #include <sys/mutex.h>
44 #include <sys/pcpu.h>
45 #include <sys/priv.h>
46 #include <sys/proc.h>
47 #include <sys/smp.h>
48 #include <sys/sysent.h>
49 #include <sys/sysproto.h>
50 #include <sys/uio.h>
51
52 #include <vm/vm.h>
53 #include <vm/pmap.h>
54 #include <vm/vm_kern.h> /* for kernel_map */
55 #include <vm/vm_map.h>
56 #include <vm/vm_extern.h>
57
58 #include <machine/frame.h>
59 #include <machine/md_var.h>
60 #include <machine/pcb.h>
61 #include <machine/specialreg.h>
62 #include <machine/sysarch.h>
63 #include <machine/tss.h>
64 #include <machine/vmparam.h>
65
66 #include <security/audit/audit.h>
67
68 static void user_ldt_deref(struct proc_ldt *pldt);
69 static void user_ldt_derefl(struct proc_ldt *pldt);
70
71 #define MAX_LD 8192
72
73 int max_ldt_segment = 512;
74 SYSCTL_INT(_machdep, OID_AUTO, max_ldt_segment, CTLFLAG_RDTUN,
75 &max_ldt_segment, 0,
76 "Maximum number of allowed LDT segments in the single address space");
77
78 static void
max_ldt_segment_init(void * arg __unused)79 max_ldt_segment_init(void *arg __unused)
80 {
81
82 if (max_ldt_segment <= 0)
83 max_ldt_segment = 1;
84 if (max_ldt_segment > MAX_LD)
85 max_ldt_segment = MAX_LD;
86 }
87 SYSINIT(maxldt, SI_SUB_VM_CONF, SI_ORDER_ANY, max_ldt_segment_init, NULL);
88
89 #ifndef _SYS_SYSPROTO_H_
90 struct sysarch_args {
91 int op;
92 char *parms;
93 };
94 #endif
95
96 int
sysarch_ldt(struct thread * td,struct sysarch_args * uap,int uap_space)97 sysarch_ldt(struct thread *td, struct sysarch_args *uap, int uap_space)
98 {
99 struct i386_ldt_args *largs, la;
100 struct user_segment_descriptor *lp;
101 int error = 0;
102
103 /*
104 * XXXKIB check that the BSM generation code knows to encode
105 * the op argument.
106 */
107 AUDIT_ARG_CMD(uap->op);
108 if (uap_space == UIO_USERSPACE) {
109 error = copyin(uap->parms, &la, sizeof(struct i386_ldt_args));
110 if (error != 0)
111 return (error);
112 largs = &la;
113 } else
114 largs = (struct i386_ldt_args *)uap->parms;
115
116 switch (uap->op) {
117 case I386_GET_LDT:
118 error = amd64_get_ldt(td, largs);
119 break;
120 case I386_SET_LDT:
121 if (largs->descs != NULL && largs->num > max_ldt_segment)
122 return (EINVAL);
123 set_pcb_flags(td->td_pcb, PCB_FULL_IRET);
124 if (largs->descs != NULL) {
125 lp = malloc(largs->num * sizeof(struct
126 user_segment_descriptor), M_TEMP, M_WAITOK);
127 error = copyin(largs->descs, lp, largs->num *
128 sizeof(struct user_segment_descriptor));
129 if (error == 0)
130 error = amd64_set_ldt(td, largs, lp);
131 free(lp, M_TEMP);
132 } else {
133 error = amd64_set_ldt(td, largs, NULL);
134 }
135 break;
136 }
137 return (error);
138 }
139
140 void
update_gdt_gsbase(struct thread * td,uint32_t base)141 update_gdt_gsbase(struct thread *td, uint32_t base)
142 {
143 struct user_segment_descriptor *sd;
144
145 if (td != curthread)
146 return;
147 set_pcb_flags(td->td_pcb, PCB_FULL_IRET);
148 critical_enter();
149 sd = PCPU_GET(gs32p);
150 sd->sd_lobase = base & 0xffffff;
151 sd->sd_hibase = (base >> 24) & 0xff;
152 critical_exit();
153 }
154
155 void
update_gdt_fsbase(struct thread * td,uint32_t base)156 update_gdt_fsbase(struct thread *td, uint32_t base)
157 {
158 struct user_segment_descriptor *sd;
159
160 if (td != curthread)
161 return;
162 set_pcb_flags(td->td_pcb, PCB_FULL_IRET);
163 critical_enter();
164 sd = PCPU_GET(fs32p);
165 sd->sd_lobase = base & 0xffffff;
166 sd->sd_hibase = (base >> 24) & 0xff;
167 critical_exit();
168 }
169
170 int
sysarch(struct thread * td,struct sysarch_args * uap)171 sysarch(struct thread *td, struct sysarch_args *uap)
172 {
173 struct pcb *pcb;
174 struct vm_map *map;
175 uint32_t i386base;
176 uint64_t a64base;
177 struct i386_ioperm_args iargs;
178 struct i386_get_xfpustate i386xfpu;
179 struct i386_set_pkru i386pkru;
180 struct amd64_get_xfpustate a64xfpu;
181 struct amd64_set_pkru a64pkru;
182 int error;
183
184 #ifdef CAPABILITY_MODE
185 /*
186 * When adding new operations, add a new case statement here to
187 * explicitly indicate whether or not the operation is safe to
188 * perform in capability mode.
189 */
190 switch (uap->op) {
191 case I386_GET_LDT:
192 case I386_SET_LDT:
193 case I386_GET_IOPERM:
194 case I386_GET_FSBASE:
195 case I386_SET_FSBASE:
196 case I386_GET_GSBASE:
197 case I386_SET_GSBASE:
198 case I386_GET_XFPUSTATE:
199 case I386_SET_PKRU:
200 case I386_CLEAR_PKRU:
201 case AMD64_GET_FSBASE:
202 case AMD64_SET_FSBASE:
203 case AMD64_GET_GSBASE:
204 case AMD64_SET_GSBASE:
205 case AMD64_GET_XFPUSTATE:
206 case AMD64_SET_PKRU:
207 case AMD64_CLEAR_PKRU:
208 case AMD64_GET_TLSBASE:
209 case AMD64_SET_TLSBASE:
210 case AMD64_DISABLE_TLSBASE:
211 break;
212
213 case I386_SET_IOPERM:
214 default:
215 if (CAP_TRACING(td))
216 ktrcapfail(CAPFAIL_SYSCALL, &uap->op);
217 if (IN_CAPABILITY_MODE(td))
218 return (ECAPMODE);
219 break;
220 }
221 #endif
222
223 if (uap->op == I386_GET_LDT || uap->op == I386_SET_LDT)
224 return (sysarch_ldt(td, uap, UIO_USERSPACE));
225
226 error = 0;
227 pcb = td->td_pcb;
228
229 /*
230 * XXXKIB check that the BSM generation code knows to encode
231 * the op argument.
232 */
233 AUDIT_ARG_CMD(uap->op);
234 switch (uap->op) {
235 case I386_GET_IOPERM:
236 case I386_SET_IOPERM:
237 if ((error = copyin(uap->parms, &iargs,
238 sizeof(struct i386_ioperm_args))) != 0)
239 return (error);
240 break;
241 case I386_GET_XFPUSTATE:
242 if ((error = copyin(uap->parms, &i386xfpu,
243 sizeof(struct i386_get_xfpustate))) != 0)
244 return (error);
245 a64xfpu.addr = (void *)(uintptr_t)i386xfpu.addr;
246 a64xfpu.len = i386xfpu.len;
247 break;
248 case I386_SET_PKRU:
249 case I386_CLEAR_PKRU:
250 if ((error = copyin(uap->parms, &i386pkru,
251 sizeof(struct i386_set_pkru))) != 0)
252 return (error);
253 a64pkru.addr = (void *)(uintptr_t)i386pkru.addr;
254 a64pkru.len = i386pkru.len;
255 a64pkru.keyidx = i386pkru.keyidx;
256 a64pkru.flags = i386pkru.flags;
257 break;
258 case AMD64_GET_XFPUSTATE:
259 if ((error = copyin(uap->parms, &a64xfpu,
260 sizeof(struct amd64_get_xfpustate))) != 0)
261 return (error);
262 break;
263 case AMD64_SET_PKRU:
264 case AMD64_CLEAR_PKRU:
265 if ((error = copyin(uap->parms, &a64pkru,
266 sizeof(struct amd64_set_pkru))) != 0)
267 return (error);
268 break;
269 default:
270 break;
271 }
272
273 switch (uap->op) {
274 case I386_GET_IOPERM:
275 error = amd64_get_ioperm(td, &iargs);
276 if (error == 0)
277 error = copyout(&iargs, uap->parms,
278 sizeof(struct i386_ioperm_args));
279 break;
280 case I386_SET_IOPERM:
281 error = amd64_set_ioperm(td, &iargs);
282 break;
283 case I386_GET_FSBASE:
284 update_pcb_bases(pcb);
285 i386base = pcb->pcb_fsbase;
286 error = copyout(&i386base, uap->parms, sizeof(i386base));
287 break;
288 case I386_SET_FSBASE:
289 error = copyin(uap->parms, &i386base, sizeof(i386base));
290 if (error == 0) {
291 set_pcb_flags(pcb, PCB_FULL_IRET);
292 pcb->pcb_fsbase = i386base;
293 td->td_frame->tf_fs = _ufssel;
294 update_gdt_fsbase(td, i386base);
295 }
296 break;
297 case I386_GET_GSBASE:
298 update_pcb_bases(pcb);
299 i386base = pcb->pcb_gsbase;
300 error = copyout(&i386base, uap->parms, sizeof(i386base));
301 break;
302 case I386_SET_GSBASE:
303 error = copyin(uap->parms, &i386base, sizeof(i386base));
304 if (error == 0) {
305 set_pcb_flags(pcb, PCB_FULL_IRET);
306 pcb->pcb_gsbase = i386base;
307 td->td_frame->tf_gs = _ugssel;
308 update_gdt_gsbase(td, i386base);
309 }
310 break;
311 case AMD64_GET_FSBASE:
312 update_pcb_bases(pcb);
313 error = copyout(&pcb->pcb_fsbase, uap->parms,
314 sizeof(pcb->pcb_fsbase));
315 break;
316 case AMD64_GET_TLSBASE:
317 if ((pcb->pcb_flags & PCB_TLSBASE) == 0) {
318 error = ESRCH;
319 } else {
320 error = copyout(&pcb->pcb_tlsbase, uap->parms,
321 sizeof(pcb->pcb_tlsbase));
322 }
323 break;
324
325 case AMD64_SET_FSBASE:
326 case AMD64_SET_TLSBASE:
327 error = copyin(uap->parms, &a64base, sizeof(a64base));
328 if (error == 0) {
329 if (a64base < curproc->p_sysent->sv_maxuser) {
330 set_pcb_flags(pcb, PCB_FULL_IRET);
331 pcb->pcb_fsbase = a64base;
332 td->td_frame->tf_fs = _ufssel;
333 if (uap->op == AMD64_SET_TLSBASE) {
334 pcb->pcb_tlsbase = a64base;
335 set_pcb_flags(pcb, PCB_TLSBASE);
336 }
337 } else
338 error = EINVAL;
339 }
340 break;
341
342 case AMD64_GET_GSBASE:
343 update_pcb_bases(pcb);
344 error = copyout(&pcb->pcb_gsbase, uap->parms,
345 sizeof(pcb->pcb_gsbase));
346 break;
347
348 case AMD64_SET_GSBASE:
349 error = copyin(uap->parms, &a64base, sizeof(a64base));
350 if (error == 0) {
351 if (a64base < curproc->p_sysent->sv_maxuser) {
352 set_pcb_flags(pcb, PCB_FULL_IRET);
353 pcb->pcb_gsbase = a64base;
354 td->td_frame->tf_gs = _ugssel;
355 } else
356 error = EINVAL;
357 }
358 break;
359
360 case I386_GET_XFPUSTATE:
361 case AMD64_GET_XFPUSTATE:
362 if (a64xfpu.len > cpu_max_ext_state_size -
363 sizeof(struct savefpu))
364 return (EINVAL);
365 fpugetregs(td);
366 error = copyout((char *)(get_pcb_user_save_td(td) + 1),
367 a64xfpu.addr, a64xfpu.len);
368 break;
369
370 case I386_SET_PKRU:
371 case AMD64_SET_PKRU: {
372 vm_offset_t addr, start, end;
373 vm_size_t len;
374
375 addr = (uintptr_t)a64pkru.addr;
376 len = a64pkru.len;
377
378 /*
379 * Read-lock the map to synchronize with parallel
380 * pmap_vmspace_copy() on fork.
381 */
382 map = &td->td_proc->p_vmspace->vm_map;
383 vm_map_lock_read(map);
384 if (len == 0 || !vm_map_check_boundary(map, addr, addr + len)) {
385 vm_map_unlock_read(map);
386 error = EINVAL;
387 break;
388 }
389 start = trunc_page(addr);
390 end = round_page(addr + len);
391 error = pmap_pkru_set(PCPU_GET(curpmap), start, end,
392 a64pkru.keyidx, a64pkru.flags);
393 vm_map_unlock_read(map);
394 break;
395 }
396
397 case I386_CLEAR_PKRU:
398 case AMD64_CLEAR_PKRU: {
399 vm_offset_t addr, start, end;
400 vm_size_t len;
401
402 if (a64pkru.flags != 0 || a64pkru.keyidx != 0) {
403 error = EINVAL;
404 break;
405 }
406
407 addr = (uintptr_t)a64pkru.addr;
408 len = a64pkru.len;
409
410 map = &td->td_proc->p_vmspace->vm_map;
411 vm_map_lock_read(map);
412 if (len == 0 || !vm_map_check_boundary(map, addr, addr + len)) {
413 vm_map_unlock_read(map);
414 error = EINVAL;
415 break;
416 }
417 start = trunc_page(addr);
418 end = round_page(addr + len);
419 error = pmap_pkru_clear(PCPU_GET(curpmap), start, end);
420 vm_map_unlock_read(map);
421 break;
422 }
423
424 case AMD64_DISABLE_TLSBASE:
425 clear_pcb_flags(pcb, PCB_TLSBASE);
426 update_pcb_bases(pcb);
427 break;
428
429 default:
430 error = EINVAL;
431 break;
432 }
433 return (error);
434 }
435
436 int
amd64_set_ioperm(struct thread * td,struct i386_ioperm_args * uap)437 amd64_set_ioperm(struct thread *td, struct i386_ioperm_args *uap)
438 {
439 char *iomap;
440 struct amd64tss *tssp;
441 struct system_segment_descriptor *tss_sd;
442 struct pcb *pcb;
443 u_int i;
444 int error;
445
446 if ((error = priv_check(td, PRIV_IO)) != 0)
447 return (error);
448 if ((error = securelevel_gt(td->td_ucred, 0)) != 0)
449 return (error);
450 if (uap->start > uap->start + uap->length ||
451 uap->start + uap->length > IOPAGES * PAGE_SIZE * NBBY)
452 return (EINVAL);
453
454 /*
455 * XXX
456 * While this is restricted to root, we should probably figure out
457 * whether any other driver is using this i/o address, as so not to
458 * cause confusion. This probably requires a global 'usage registry'.
459 */
460 pcb = td->td_pcb;
461 if (pcb->pcb_tssp == NULL) {
462 tssp = kmem_malloc(ctob(IOPAGES + 1), M_WAITOK);
463 pmap_pti_add_kva((vm_offset_t)tssp, (vm_offset_t)tssp +
464 ctob(IOPAGES + 1), false);
465 iomap = (char *)&tssp[1];
466 memset(iomap, 0xff, IOPERM_BITMAP_SIZE);
467 critical_enter();
468 /* Takes care of tss_rsp0. */
469 memcpy(tssp, PCPU_PTR(common_tss), sizeof(struct amd64tss));
470 tssp->tss_iobase = sizeof(*tssp);
471 pcb->pcb_tssp = tssp;
472 tss_sd = PCPU_GET(tss);
473 tss_sd->sd_lobase = (u_long)tssp & 0xffffff;
474 tss_sd->sd_hibase = ((u_long)tssp >> 24) & 0xfffffffffful;
475 tss_sd->sd_type = SDT_SYSTSS;
476 ltr(GSEL(GPROC0_SEL, SEL_KPL));
477 PCPU_SET(tssp, tssp);
478 critical_exit();
479 } else
480 iomap = (char *)&pcb->pcb_tssp[1];
481 for (i = uap->start; i < uap->start + uap->length; i++) {
482 if (uap->enable)
483 iomap[i >> 3] &= ~(1 << (i & 7));
484 else
485 iomap[i >> 3] |= (1 << (i & 7));
486 }
487 return (error);
488 }
489
490 int
amd64_get_ioperm(struct thread * td,struct i386_ioperm_args * uap)491 amd64_get_ioperm(struct thread *td, struct i386_ioperm_args *uap)
492 {
493 int i, state;
494 char *iomap;
495
496 if (uap->start >= IOPAGES * PAGE_SIZE * NBBY)
497 return (EINVAL);
498 if (td->td_pcb->pcb_tssp == NULL) {
499 uap->length = 0;
500 goto done;
501 }
502
503 iomap = (char *)&td->td_pcb->pcb_tssp[1];
504
505 i = uap->start;
506 state = (iomap[i >> 3] >> (i & 7)) & 1;
507 uap->enable = !state;
508 uap->length = 1;
509
510 for (i = uap->start + 1; i < IOPAGES * PAGE_SIZE * NBBY; i++) {
511 if (state != ((iomap[i >> 3] >> (i & 7)) & 1))
512 break;
513 uap->length++;
514 }
515
516 done:
517 return (0);
518 }
519
520 /*
521 * Update the GDT entry pointing to the LDT to point to the LDT of the
522 * current process.
523 */
524 static void
set_user_ldt(struct mdproc * mdp)525 set_user_ldt(struct mdproc *mdp)
526 {
527
528 *PCPU_GET(ldt) = mdp->md_ldt_sd;
529 lldt(GSEL(GUSERLDT_SEL, SEL_KPL));
530 }
531
532 static void
set_user_ldt_rv(void * arg)533 set_user_ldt_rv(void *arg)
534 {
535 struct proc *orig, *target;
536 struct proc_ldt *ldt;
537
538 orig = arg;
539 target = curthread->td_proc;
540
541 ldt = (void *)atomic_load_acq_ptr((uintptr_t *)&orig->p_md.md_ldt);
542 if (target->p_md.md_ldt != ldt)
543 return;
544
545 set_user_ldt(&target->p_md);
546 }
547
548 struct proc_ldt *
user_ldt_alloc(struct proc * p,int force)549 user_ldt_alloc(struct proc *p, int force)
550 {
551 struct proc_ldt *pldt, *new_ldt;
552 struct mdproc *mdp;
553 struct soft_segment_descriptor sldt;
554 vm_offset_t sva;
555 vm_size_t sz;
556
557 mtx_assert(&dt_lock, MA_OWNED);
558 mdp = &p->p_md;
559 if (!force && mdp->md_ldt != NULL)
560 return (mdp->md_ldt);
561 mtx_unlock(&dt_lock);
562 new_ldt = malloc(sizeof(struct proc_ldt), M_SUBPROC, M_WAITOK);
563 sz = max_ldt_segment * sizeof(struct user_segment_descriptor);
564 new_ldt->ldt_base = kmem_malloc(sz, M_WAITOK | M_ZERO);
565 sva = (uintptr_t)new_ldt->ldt_base;
566 pmap_pti_add_kva(sva, sva + sz, false);
567 new_ldt->ldt_refcnt = 1;
568 sldt.ssd_base = sva;
569 sldt.ssd_limit = sz - 1;
570 sldt.ssd_type = SDT_SYSLDT;
571 sldt.ssd_dpl = SEL_KPL;
572 sldt.ssd_p = 1;
573 sldt.ssd_long = 0;
574 sldt.ssd_def32 = 0;
575 sldt.ssd_gran = 0;
576 mtx_lock(&dt_lock);
577 pldt = mdp->md_ldt;
578 if (pldt != NULL && !force) {
579 pmap_pti_remove_kva(sva, sva + sz);
580 kmem_free(new_ldt->ldt_base, sz);
581 free(new_ldt, M_SUBPROC);
582 return (pldt);
583 }
584
585 if (pldt != NULL) {
586 bcopy(pldt->ldt_base, new_ldt->ldt_base, max_ldt_segment *
587 sizeof(struct user_segment_descriptor));
588 user_ldt_derefl(pldt);
589 }
590 critical_enter();
591 ssdtosyssd(&sldt, &p->p_md.md_ldt_sd);
592 atomic_thread_fence_rel();
593 mdp->md_ldt = new_ldt;
594 critical_exit();
595 smp_rendezvous(NULL, set_user_ldt_rv, NULL, p);
596
597 return (mdp->md_ldt);
598 }
599
600 void
user_ldt_free(struct thread * td)601 user_ldt_free(struct thread *td)
602 {
603 struct proc *p = td->td_proc;
604 struct mdproc *mdp = &p->p_md;
605 struct proc_ldt *pldt;
606
607 mtx_lock(&dt_lock);
608 if ((pldt = mdp->md_ldt) == NULL) {
609 mtx_unlock(&dt_lock);
610 return;
611 }
612
613 critical_enter();
614 mdp->md_ldt = NULL;
615 atomic_thread_fence_rel();
616 bzero(&mdp->md_ldt_sd, sizeof(mdp->md_ldt_sd));
617 if (td == curthread)
618 lldt(GSEL(GNULL_SEL, SEL_KPL));
619 critical_exit();
620 user_ldt_deref(pldt);
621 }
622
623 static void
user_ldt_derefl(struct proc_ldt * pldt)624 user_ldt_derefl(struct proc_ldt *pldt)
625 {
626 vm_offset_t sva;
627 vm_size_t sz;
628
629 if (--pldt->ldt_refcnt == 0) {
630 sva = (vm_offset_t)pldt->ldt_base;
631 sz = max_ldt_segment * sizeof(struct user_segment_descriptor);
632 pmap_pti_remove_kva(sva, sva + sz);
633 kmem_free(pldt->ldt_base, sz);
634 free(pldt, M_SUBPROC);
635 }
636 }
637
638 static void
user_ldt_deref(struct proc_ldt * pldt)639 user_ldt_deref(struct proc_ldt *pldt)
640 {
641
642 mtx_assert(&dt_lock, MA_OWNED);
643 user_ldt_derefl(pldt);
644 mtx_unlock(&dt_lock);
645 }
646
647 /*
648 * Note for the authors of compat layers (linux, etc): copyout() in
649 * the function below is not a problem since it presents data in
650 * arch-specific format (i.e. i386-specific in this case), not in
651 * the OS-specific one.
652 */
653 int
amd64_get_ldt(struct thread * td,struct i386_ldt_args * uap)654 amd64_get_ldt(struct thread *td, struct i386_ldt_args *uap)
655 {
656 struct proc_ldt *pldt;
657 struct user_segment_descriptor *lp;
658 uint64_t *data;
659 u_int i, num;
660 int error;
661
662 #ifdef DEBUG
663 printf("amd64_get_ldt: start=%u num=%u descs=%p\n",
664 uap->start, uap->num, (void *)uap->descs);
665 #endif
666
667 pldt = td->td_proc->p_md.md_ldt;
668 if (pldt == NULL || uap->start >= max_ldt_segment || uap->num == 0) {
669 td->td_retval[0] = 0;
670 return (0);
671 }
672 num = min(uap->num, max_ldt_segment - uap->start);
673 lp = &((struct user_segment_descriptor *)(pldt->ldt_base))[uap->start];
674 data = malloc(num * sizeof(struct user_segment_descriptor), M_TEMP,
675 M_WAITOK);
676 mtx_lock(&dt_lock);
677 for (i = 0; i < num; i++)
678 data[i] = ((volatile uint64_t *)lp)[i];
679 mtx_unlock(&dt_lock);
680 error = copyout(data, uap->descs, num *
681 sizeof(struct user_segment_descriptor));
682 free(data, M_TEMP);
683 if (error == 0)
684 td->td_retval[0] = num;
685 return (error);
686 }
687
688 int
amd64_set_ldt(struct thread * td,struct i386_ldt_args * uap,struct user_segment_descriptor * descs)689 amd64_set_ldt(struct thread *td, struct i386_ldt_args *uap,
690 struct user_segment_descriptor *descs)
691 {
692 struct mdproc *mdp;
693 struct proc_ldt *pldt;
694 struct user_segment_descriptor *dp;
695 struct proc *p;
696 u_int largest_ld, i;
697 int error;
698
699 #ifdef DEBUG
700 printf("amd64_set_ldt: start=%u num=%u descs=%p\n",
701 uap->start, uap->num, (void *)uap->descs);
702 #endif
703 mdp = &td->td_proc->p_md;
704 error = 0;
705
706 set_pcb_flags(td->td_pcb, PCB_FULL_IRET);
707 p = td->td_proc;
708 if (descs == NULL) {
709 /* Free descriptors */
710 if (uap->start == 0 && uap->num == 0)
711 uap->num = max_ldt_segment;
712 if (uap->num == 0)
713 return (EINVAL);
714 if ((pldt = mdp->md_ldt) == NULL ||
715 uap->start >= max_ldt_segment)
716 return (0);
717 largest_ld = uap->start + uap->num;
718 if (largest_ld > max_ldt_segment)
719 largest_ld = max_ldt_segment;
720 if (largest_ld < uap->start)
721 return (EINVAL);
722 mtx_lock(&dt_lock);
723 for (i = uap->start; i < largest_ld; i++)
724 ((volatile uint64_t *)(pldt->ldt_base))[i] = 0;
725 mtx_unlock(&dt_lock);
726 return (0);
727 }
728
729 if (!(uap->start == LDT_AUTO_ALLOC && uap->num == 1)) {
730 /* verify range of descriptors to modify */
731 largest_ld = uap->start + uap->num;
732 if (uap->start >= max_ldt_segment ||
733 largest_ld > max_ldt_segment ||
734 largest_ld < uap->start)
735 return (EINVAL);
736 }
737
738 /* Check descriptors for access violations */
739 for (i = 0; i < uap->num; i++) {
740 dp = &descs[i];
741
742 switch (dp->sd_type) {
743 case SDT_SYSNULL: /* system null */
744 dp->sd_p = 0;
745 break;
746 case SDT_SYS286TSS:
747 case SDT_SYSLDT:
748 case SDT_SYS286BSY:
749 case SDT_SYS286CGT:
750 case SDT_SYSTASKGT:
751 case SDT_SYS286IGT:
752 case SDT_SYS286TGT:
753 case SDT_SYSNULL2:
754 case SDT_SYSTSS:
755 case SDT_SYSNULL3:
756 case SDT_SYSBSY:
757 case SDT_SYSCGT:
758 case SDT_SYSNULL4:
759 case SDT_SYSIGT:
760 case SDT_SYSTGT:
761 return (EACCES);
762
763 /* memory segment types */
764 case SDT_MEMEC: /* memory execute only conforming */
765 case SDT_MEMEAC: /* memory execute only accessed conforming */
766 case SDT_MEMERC: /* memory execute read conforming */
767 case SDT_MEMERAC: /* memory execute read accessed conforming */
768 /* Must be "present" if executable and conforming. */
769 if (dp->sd_p == 0)
770 return (EACCES);
771 break;
772 case SDT_MEMRO: /* memory read only */
773 case SDT_MEMROA: /* memory read only accessed */
774 case SDT_MEMRW: /* memory read write */
775 case SDT_MEMRWA: /* memory read write accessed */
776 case SDT_MEMROD: /* memory read only expand dwn limit */
777 case SDT_MEMRODA: /* memory read only expand dwn lim accessed */
778 case SDT_MEMRWD: /* memory read write expand dwn limit */
779 case SDT_MEMRWDA: /* memory read write expand dwn lim acessed */
780 case SDT_MEME: /* memory execute only */
781 case SDT_MEMEA: /* memory execute only accessed */
782 case SDT_MEMER: /* memory execute read */
783 case SDT_MEMERA: /* memory execute read accessed */
784 break;
785 default:
786 return(EINVAL);
787 }
788
789 /* Only user (ring-3) descriptors may be present. */
790 if ((dp->sd_p != 0) && (dp->sd_dpl != SEL_UPL))
791 return (EACCES);
792 }
793
794 if (uap->start == LDT_AUTO_ALLOC && uap->num == 1) {
795 /* Allocate a free slot */
796 mtx_lock(&dt_lock);
797 pldt = user_ldt_alloc(p, 0);
798 if (pldt == NULL) {
799 mtx_unlock(&dt_lock);
800 return (ENOMEM);
801 }
802
803 /*
804 * start scanning a bit up to leave room for NVidia and
805 * Wine, which still user the "Blat" method of allocation.
806 */
807 i = 16;
808 dp = &((struct user_segment_descriptor *)(pldt->ldt_base))[i];
809 for (; i < max_ldt_segment; ++i, ++dp) {
810 if (dp->sd_type == SDT_SYSNULL)
811 break;
812 }
813 if (i >= max_ldt_segment) {
814 mtx_unlock(&dt_lock);
815 return (ENOSPC);
816 }
817 uap->start = i;
818 error = amd64_set_ldt_data(td, i, 1, descs);
819 mtx_unlock(&dt_lock);
820 } else {
821 largest_ld = uap->start + uap->num;
822 if (largest_ld > max_ldt_segment)
823 return (EINVAL);
824 mtx_lock(&dt_lock);
825 if (user_ldt_alloc(p, 0) != NULL) {
826 error = amd64_set_ldt_data(td, uap->start, uap->num,
827 descs);
828 }
829 mtx_unlock(&dt_lock);
830 }
831 if (error == 0)
832 td->td_retval[0] = uap->start;
833 return (error);
834 }
835
836 int
amd64_set_ldt_data(struct thread * td,int start,int num,struct user_segment_descriptor * descs)837 amd64_set_ldt_data(struct thread *td, int start, int num,
838 struct user_segment_descriptor *descs)
839 {
840 struct mdproc *mdp;
841 struct proc_ldt *pldt;
842 volatile uint64_t *dst, *src;
843 int i;
844
845 mtx_assert(&dt_lock, MA_OWNED);
846
847 mdp = &td->td_proc->p_md;
848 pldt = mdp->md_ldt;
849 dst = (volatile uint64_t *)(pldt->ldt_base);
850 src = (volatile uint64_t *)descs;
851 for (i = 0; i < num; i++)
852 dst[start + i] = src[i];
853 return (0);
854 }
855