1 /* SPDX-License-Identifier: GPL-2.0 OR MIT */ 2 /* 3 * Copyright 2014-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #ifndef __KFD_TOPOLOGY_H__ 25 #define __KFD_TOPOLOGY_H__ 26 27 #include <linux/dmi.h> 28 #include <linux/types.h> 29 #include <linux/list.h> 30 #include <linux/kfd_sysfs.h> 31 #include "kfd_crat.h" 32 33 #define KFD_TOPOLOGY_PUBLIC_NAME_SIZE 32 34 35 #define HSA_DBG_WATCH_ADDR_MASK_LO_BIT_GFX9 6 36 #define HSA_DBG_WATCH_ADDR_MASK_LO_BIT_GFX9_4_3 7 37 #define HSA_DBG_WATCH_ADDR_MASK_LO_BIT_GFX10 7 38 #define HSA_DBG_WATCH_ADDR_MASK_HI_BIT \ 39 (29 << HSA_DBG_WATCH_ADDR_MASK_HI_BIT_SHIFT) 40 #define HSA_DBG_WATCH_ADDR_MASK_HI_BIT_GFX9_4_3 \ 41 (30 << HSA_DBG_WATCH_ADDR_MASK_HI_BIT_SHIFT) 42 43 struct kfd_node_properties { 44 uint64_t hive_id; 45 uint32_t cpu_cores_count; 46 uint32_t simd_count; 47 uint32_t mem_banks_count; 48 uint32_t caches_count; 49 uint32_t io_links_count; 50 uint32_t p2p_links_count; 51 uint32_t cpu_core_id_base; 52 uint32_t simd_id_base; 53 uint32_t capability; 54 uint32_t capability2; 55 uint64_t debug_prop; 56 uint32_t max_waves_per_simd; 57 uint32_t lds_size_in_kb; 58 uint32_t gds_size_in_kb; 59 uint32_t num_gws; 60 uint32_t wave_front_size; 61 uint32_t array_count; 62 uint32_t simd_arrays_per_engine; 63 uint32_t cu_per_simd_array; 64 uint32_t simd_per_cu; 65 uint32_t max_slots_scratch_cu; 66 uint32_t engine_id; 67 uint32_t gfx_target_version; 68 uint32_t vendor_id; 69 uint32_t device_id; 70 uint32_t location_id; 71 uint32_t domain; 72 uint32_t max_engine_clk_fcompute; 73 uint32_t max_engine_clk_ccompute; 74 int32_t drm_render_minor; 75 uint32_t num_sdma_engines; 76 uint32_t num_sdma_xgmi_engines; 77 uint32_t num_sdma_queues_per_engine; 78 uint32_t num_cp_queues; 79 uint32_t cwsr_size; 80 uint32_t ctl_stack_size; 81 uint32_t eop_buffer_size; 82 uint32_t debug_memory_size; 83 char name[KFD_TOPOLOGY_PUBLIC_NAME_SIZE]; 84 }; 85 86 struct kfd_mem_properties { 87 struct list_head list; 88 uint32_t heap_type; 89 uint64_t size_in_bytes; 90 uint32_t flags; 91 uint32_t width; 92 uint32_t mem_clk_max; 93 struct kfd_node *gpu; 94 struct kobject *kobj; 95 struct attribute attr; 96 }; 97 98 #define CACHE_SIBLINGMAP_SIZE 128 99 100 struct kfd_cache_properties { 101 struct list_head list; 102 uint32_t processor_id_low; 103 uint32_t cache_level; 104 uint32_t cache_size; 105 uint32_t cacheline_size; 106 uint32_t cachelines_per_tag; 107 uint32_t cache_assoc; 108 uint32_t cache_latency; 109 uint32_t cache_type; 110 uint8_t sibling_map[CACHE_SIBLINGMAP_SIZE]; 111 struct kfd_node *gpu; 112 struct kobject *kobj; 113 struct attribute attr; 114 uint32_t sibling_map_size; 115 }; 116 117 struct kfd_iolink_properties { 118 struct list_head list; 119 uint32_t iolink_type; 120 uint32_t ver_maj; 121 uint32_t ver_min; 122 uint32_t node_from; 123 uint32_t node_to; 124 uint32_t weight; 125 uint32_t min_latency; 126 uint32_t max_latency; 127 uint32_t min_bandwidth; 128 uint32_t max_bandwidth; 129 uint32_t rec_transfer_size; 130 uint32_t rec_sdma_eng_id_mask; 131 uint32_t flags; 132 struct kfd_node *gpu; 133 struct kobject *kobj; 134 struct attribute attr; 135 }; 136 137 struct kfd_perf_properties { 138 struct list_head list; 139 char block_name[16]; 140 uint32_t max_concurrent; 141 struct attribute_group *attr_group; 142 }; 143 144 struct kfd_topology_device { 145 struct list_head list; 146 uint32_t gpu_id; 147 uint32_t proximity_domain; 148 struct kfd_node_properties node_props; 149 struct list_head mem_props; 150 struct list_head cache_props; 151 struct list_head io_link_props; 152 struct list_head p2p_link_props; 153 struct list_head perf_props; 154 struct kfd_node *gpu; 155 struct kobject *kobj_node; 156 struct kobject *kobj_mem; 157 struct kobject *kobj_cache; 158 struct kobject *kobj_iolink; 159 struct kobject *kobj_p2plink; 160 struct kobject *kobj_perf; 161 struct attribute attr_gpuid; 162 struct attribute attr_name; 163 struct attribute attr_props; 164 union { 165 uint8_t oem_id[CRAT_OEMID_LENGTH]; 166 uint64_t oem_id64; 167 }; 168 uint8_t oem_table_id[CRAT_OEMTABLEID_LENGTH]; 169 uint32_t oem_revision; 170 }; 171 172 struct kfd_system_properties { 173 uint32_t num_devices; /* Number of H-NUMA nodes */ 174 uint32_t generation_count; 175 uint64_t platform_oem; 176 uint64_t platform_id; 177 uint64_t platform_rev; 178 struct kobject *kobj_topology; 179 struct kobject *kobj_nodes; 180 struct attribute attr_genid; 181 struct attribute attr_props; 182 }; 183 184 struct dmi_mem_device { 185 struct dmi_header header; 186 u16 physical_handle; 187 u16 error_handle; 188 u16 total_width; 189 u16 data_width; 190 u16 size; 191 u8 form_factor; 192 u8 device_set; 193 u8 device_locator; 194 u8 bank_locator; 195 u8 memory_type; 196 u16 type_detail; 197 u16 speed; 198 } __packed; 199 200 struct kfd_topology_device *kfd_create_topology_device( 201 struct list_head *device_list); 202 void kfd_release_topology_device_list(struct list_head *device_list); 203 204 #endif /* __KFD_TOPOLOGY_H__ */ 205