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Searched defs:mask2 (Results 1 – 25 of 53) sorted by relevance

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/linux/drivers/ras/amd/atl/
H A Dsystem.c67 static void df3p5_get_masks_shifts(u32 mask0, u32 mask1, u32 mask2) in df3p5_get_masks_shifts()
79 static void df4_get_masks_shifts(u32 mask0, u32 mask1, u32 mask2) in df4_get_masks_shifts()
96 u32 mask0, mask1, mask2; in df4_get_fabric_id_mask_registers() local
/linux/tools/testing/selftests/bpf/progs/
H A Dcpumask_success.c100 struct bpf_cpumask *mask1, *mask2, *mask3, *mask4; in create_cpumask_set() local
254 struct bpf_cpumask *mask1, *mask2; in BPF_PROG() local
318 struct bpf_cpumask *mask1, *mask2, *dst1, *dst2; in BPF_PROG() local
365 struct bpf_cpumask *mask1, *mask2, *dst1, *dst2; in BPF_PROG() local
407 struct bpf_cpumask *mask1, *mask2, *dst1, *dst2; in BPF_PROG() local
755 struct bpf_cpumask *mask1, *mask2; in BPF_PROG() local
/linux/arch/mips/sgi-ip22/
H A Dip22-int.c114 u8 mask2; in indy_local0_irqdispatch() local
136 u8 mask2; in indy_local1_irqdispatch() local
/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc_helper.c287 uint8_t shift2, uint32_t mask2, uint32_t *field_value2) in generic_reg_get2()
297 uint8_t shift2, uint32_t mask2, uint32_t *field_value2, in generic_reg_get3()
309 uint8_t shift2, uint32_t mask2, uint32_t *field_value2, in generic_reg_get4()
323 uint8_t shift2, uint32_t mask2, uint32_t *field_value2, in generic_reg_get5()
339 uint8_t shift2, uint32_t mask2, uint32_t *field_value2, in generic_reg_get6()
357 uint8_t shift2, uint32_t mask2, uint32_t *field_value2, in generic_reg_get7()
377 uint8_t shift2, uint32_t mask2, uint32_t *field_value2, in generic_reg_get8()
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn31/
H A Dirq_service_dcn31.c208 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
222 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn32/
H A Dirq_service_dcn32.c209 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
223 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn302/
H A Dirq_service_dcn302.c195 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
213 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn30/
H A Dirq_service_dcn30.c220 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
234 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn21/
H A Dirq_service_dcn21.c213 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
227 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn314/
H A Dirq_service_dcn314.c210 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
224 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn401/
H A Dirq_service_dcn401.c189 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
203 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn351/
H A Dirq_service_dcn351.c186 #define IRQ_REG_ENTRY(base, block, reg_num, reg1, mask1, reg2, mask2)\ argument
200 #define IRQ_REG_ENTRY_DMUB(base, reg1, mask1, reg2, mask2)\ argument
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn315/
H A Dirq_service_dcn315.c215 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
229 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn35/
H A Dirq_service_dcn35.c207 #define IRQ_REG_ENTRY(base, block, reg_num, reg1, mask1, reg2, mask2)\ argument
221 #define IRQ_REG_ENTRY_DMUB(base, reg1, mask1, reg2, mask2)\ argument
/linux/include/linux/
H A Dcpumask.h345 #define for_each_cpu_and(cpu, mask1, mask2) \ argument
363 #define for_each_cpu_andnot(cpu, mask1, mask2) \ argument
380 #define for_each_cpu_or(cpu, mask1, mask2) \ argument
423 const struct cpumask *mask2, in cpumask_any_and_but()
857 #define cpumask_any_and(mask1, mask2) cpumask_first_and((mask1), (mask2)) argument
/linux/drivers/net/hamradio/
H A Dhdlcdrv.c159 unsigned int mask1, mask2, mask3, mask4, mask5, mask6, word; in hdlcdrv_receiver() local
255 unsigned int mask1, mask2, mask3; in hdlcdrv_transmitter() local
/linux/lib/
H A Dcpumask_kunit.c26 #define EXPECT_FOR_EACH_CPU_OP_EQ(test, op, mask1, mask2) \ argument
/linux/drivers/net/wireless/ath/ath9k/
H A Dar9002_mac.c36 u32 mask2 = 0; in ar9002_hw_get_isr() local
/linux/fs/affs/
H A Dbitmap.c122 u32 blk, bmap, bit, mask, mask2, tmp; in affs_alloc_block() local
/linux/drivers/gpu/drm/amd/display/dc/irq/dce120/
H A Dirq_service_dce120.c103 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn20/
H A Dirq_service_dcn20.c203 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn10/
H A Dirq_service_dcn10.c200 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn303/
H A Dirq_service_dcn303.c138 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
/linux/sound/soc/codecs/
H A Dcs35l33.c269 unsigned int mask2 = CS35L33_SDOUT_3ST_TDM; in cs35l33_sdout_event() local
962 unsigned int sticky_val1, sticky_val2, current_val, mask1, mask2; in cs35l33_irq_thread() local
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn201/
H A Dirq_service_dcn201.c152 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument

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