| /linux/drivers/ras/amd/atl/ |
| H A D | system.c | 56 static void df3_get_masks_shifts(u32 mask0, u32 mask1) in df3_get_masks_shifts()
67 static void df3p5_get_masks_shifts(u32 mask0, u32 mask1, u32 mask2) in df3p5_get_masks_shifts()
79 static void df4_get_masks_shifts(u32 mask0, u32 mask1, u32 mask2) in df4_get_masks_shifts()
96 u32 mask0, mask1, mask2; in df4_get_fabric_id_mask_registers() local
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| /linux/drivers/gpu/drm/amd/display/dc/ |
| H A D | dc_helper.c | 108 uint8_t shift1, uint32_t mask1, uint32_t field_value1, in set_reg_field_values()
223 uint8_t shift1, uint32_t mask1, uint32_t field_value1, in generic_reg_update_ex()
251 uint8_t shift1, uint32_t mask1, uint32_t field_value1, in generic_reg_set_ex()
286 uint8_t shift1, uint32_t mask1, uint32_t *field_value1, in generic_reg_get2()
296 uint8_t shift1, uint32_t mask1, uint32_t *field_value1, in generic_reg_get3()
308 uint8_t shift1, uint32_t mask1, uint32_t *field_value1, in generic_reg_get4()
322 uint8_t shift1, uint32_t mask1, uint32_t *field_value1, in generic_reg_get5()
338 uint8_t shift1, uint32_t mask1, uint32_t *field_value1, in generic_reg_get6()
356 uint8_t shift1, uint32_t mask1, uint32_t *field_value1, in generic_reg_get7()
376 uint8_t shift1, uint32_t mask1, uint32_t *field_value1, in generic_reg_get8()
[all …]
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| /linux/tools/testing/selftests/bpf/progs/ |
| H A D | cpumask_success.c | 100 struct bpf_cpumask *mask1, *mask2, *mask3, *mask4; in create_cpumask_set() local
254 struct bpf_cpumask *mask1, *mask2; in BPF_PROG() local
318 struct bpf_cpumask *mask1, *mask2, *dst1, *dst2; in BPF_PROG() local
365 struct bpf_cpumask *mask1, *mask2, *dst1, *dst2; in BPF_PROG() local
407 struct bpf_cpumask *mask1, *mask2, *dst1, *dst2; in BPF_PROG() local
573 struct bpf_cpumask **mask1) in _global_mask_array_rcu()
755 struct bpf_cpumask *mask1, *mask2; in BPF_PROG() local
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| /linux/drivers/gpu/drm/amd/display/dmub/src/ |
| H A D | dmub_reg.c | 45 uint32_t mask1, uint32_t field_value1, in set_reg_field_values()
73 uint32_t mask1, uint32_t field_value1, ...) in dmub_reg_update()
90 uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...) in dmub_reg_set()
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| /linux/drivers/gpu/drm/amd/display/dc/irq/dcn31/ |
| H A D | irq_service_dcn31.c | 208 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
222 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
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| /linux/drivers/gpu/drm/amd/display/dc/irq/dcn32/ |
| H A D | irq_service_dcn32.c | 209 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
223 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
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| /linux/drivers/gpu/drm/amd/display/dc/irq/dcn302/ |
| H A D | irq_service_dcn302.c | 195 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
213 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
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| /linux/drivers/gpu/drm/amd/display/dc/irq/dcn30/ |
| H A D | irq_service_dcn30.c | 220 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
234 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
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| /linux/drivers/gpu/drm/amd/display/dc/irq/dcn21/ |
| H A D | irq_service_dcn21.c | 213 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
227 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
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| /linux/drivers/gpu/drm/amd/display/dc/irq/dcn314/ |
| H A D | irq_service_dcn314.c | 210 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
224 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
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| /linux/drivers/gpu/drm/amd/display/dc/irq/dcn401/ |
| H A D | irq_service_dcn401.c | 189 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
203 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
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| /linux/drivers/gpu/drm/amd/display/dc/irq/dcn351/ |
| H A D | irq_service_dcn351.c | 186 #define IRQ_REG_ENTRY(base, block, reg_num, reg1, mask1, reg2, mask2)\ argument
200 #define IRQ_REG_ENTRY_DMUB(base, reg1, mask1, reg2, mask2)\ argument
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| /linux/drivers/gpu/drm/amd/display/dc/irq/dcn315/ |
| H A D | irq_service_dcn315.c | 215 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
229 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
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| /linux/drivers/gpu/drm/amd/display/dc/irq/dcn35/ |
| H A D | irq_service_dcn35.c | 207 #define IRQ_REG_ENTRY(base, block, reg_num, reg1, mask1, reg2, mask2)\ argument
221 #define IRQ_REG_ENTRY_DMUB(base, reg1, mask1, reg2, mask2)\ argument
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| /linux/drivers/net/hamradio/ |
| H A D | hdlcdrv.c | 159 unsigned int mask1, mask2, mask3, mask4, mask5, mask6, word; in hdlcdrv_receiver() local
255 unsigned int mask1, mask2, mask3; in hdlcdrv_transmitter() local
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| /linux/arch/mips/sgi-ip27/ |
| H A D | ip27-nmi.c | 127 u64 mask0, mask1, pend0, pend1; in nmi_dump_hub_irq() local
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| /linux/lib/ |
| H A D | cpumask_kunit.c | 26 #define EXPECT_FOR_EACH_CPU_OP_EQ(test, op, mask1, mask2) \ argument
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| /linux/arch/alpha/kernel/ |
| H A D | sys_rawhide.c | 102 unsigned int mask, mask1, hose; in rawhide_mask_and_ack_irq() local
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| H A D | sys_titan.c | 69 unsigned long mask0, mask1, mask2, mask3, dummy; in titan_update_irq_hw() local
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| /linux/drivers/gpu/drm/amd/display/dc/irq/dce120/ |
| H A D | irq_service_dce120.c | 103 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
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| /linux/drivers/gpu/drm/amd/display/dc/irq/dcn20/ |
| H A D | irq_service_dcn20.c | 203 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
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| /linux/drivers/gpu/drm/amd/display/dc/irq/dcn10/ |
| H A D | irq_service_dcn10.c | 200 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
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| /linux/drivers/gpu/drm/amd/display/dc/irq/dcn303/ |
| H A D | irq_service_dcn303.c | 138 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
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| /linux/drivers/gpu/drm/amd/display/dc/irq/dcn201/ |
| H A D | irq_service_dcn201.c | 152 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
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| /linux/drivers/media/test-drivers/vidtv/ |
| H A D | vidtv_pes.c | 89 u64 mask1; in vidtv_pes_write_pts_dts() local
|